1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3*572ff6f6SMatthew Dillon * Copyright (c) 2002-2006 Atheros Communications, Inc.
4*572ff6f6SMatthew Dillon *
5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8*572ff6f6SMatthew Dillon *
9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*572ff6f6SMatthew Dillon *
17*572ff6f6SMatthew Dillon * $FreeBSD$
18*572ff6f6SMatthew Dillon */
19*572ff6f6SMatthew Dillon #include "opt_ah.h"
20*572ff6f6SMatthew Dillon
21*572ff6f6SMatthew Dillon #include "ah.h"
22*572ff6f6SMatthew Dillon #include "ah_internal.h"
23*572ff6f6SMatthew Dillon #include "ah_desc.h"
24*572ff6f6SMatthew Dillon
25*572ff6f6SMatthew Dillon #include "ar5211/ar5211.h"
26*572ff6f6SMatthew Dillon #include "ar5211/ar5211reg.h"
27*572ff6f6SMatthew Dillon #include "ar5211/ar5211desc.h"
28*572ff6f6SMatthew Dillon
29*572ff6f6SMatthew Dillon /*
30*572ff6f6SMatthew Dillon * Get the RXDP.
31*572ff6f6SMatthew Dillon */
32*572ff6f6SMatthew Dillon uint32_t
ar5211GetRxDP(struct ath_hal * ah,HAL_RX_QUEUE qtype)33*572ff6f6SMatthew Dillon ar5211GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype)
34*572ff6f6SMatthew Dillon {
35*572ff6f6SMatthew Dillon
36*572ff6f6SMatthew Dillon HALASSERT(qtype == HAL_RX_QUEUE_HP);
37*572ff6f6SMatthew Dillon return OS_REG_READ(ah, AR_RXDP);
38*572ff6f6SMatthew Dillon }
39*572ff6f6SMatthew Dillon
40*572ff6f6SMatthew Dillon /*
41*572ff6f6SMatthew Dillon * Set the RxDP.
42*572ff6f6SMatthew Dillon */
43*572ff6f6SMatthew Dillon void
ar5211SetRxDP(struct ath_hal * ah,uint32_t rxdp,HAL_RX_QUEUE qtype)44*572ff6f6SMatthew Dillon ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
45*572ff6f6SMatthew Dillon {
46*572ff6f6SMatthew Dillon
47*572ff6f6SMatthew Dillon HALASSERT(qtype == HAL_RX_QUEUE_HP);
48*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RXDP, rxdp);
49*572ff6f6SMatthew Dillon HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
50*572ff6f6SMatthew Dillon }
51*572ff6f6SMatthew Dillon
52*572ff6f6SMatthew Dillon
53*572ff6f6SMatthew Dillon /*
54*572ff6f6SMatthew Dillon * Set Receive Enable bits.
55*572ff6f6SMatthew Dillon */
56*572ff6f6SMatthew Dillon void
ar5211EnableReceive(struct ath_hal * ah)57*572ff6f6SMatthew Dillon ar5211EnableReceive(struct ath_hal *ah)
58*572ff6f6SMatthew Dillon {
59*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
60*572ff6f6SMatthew Dillon }
61*572ff6f6SMatthew Dillon
62*572ff6f6SMatthew Dillon /*
63*572ff6f6SMatthew Dillon * Stop Receive at the DMA engine
64*572ff6f6SMatthew Dillon */
65*572ff6f6SMatthew Dillon HAL_BOOL
ar5211StopDmaReceive(struct ath_hal * ah)66*572ff6f6SMatthew Dillon ar5211StopDmaReceive(struct ath_hal *ah)
67*572ff6f6SMatthew Dillon {
68*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
69*572ff6f6SMatthew Dillon if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
70*572ff6f6SMatthew Dillon #ifdef AH_DEBUG
71*572ff6f6SMatthew Dillon ath_hal_printf(ah, "%s failed to stop in 10ms\n"
72*572ff6f6SMatthew Dillon "AR_CR=0x%08X\nAR_DIAG_SW=0x%08X\n"
73*572ff6f6SMatthew Dillon , __func__
74*572ff6f6SMatthew Dillon , OS_REG_READ(ah, AR_CR)
75*572ff6f6SMatthew Dillon , OS_REG_READ(ah, AR_DIAG_SW)
76*572ff6f6SMatthew Dillon );
77*572ff6f6SMatthew Dillon #endif
78*572ff6f6SMatthew Dillon return AH_FALSE;
79*572ff6f6SMatthew Dillon } else {
80*572ff6f6SMatthew Dillon return AH_TRUE;
81*572ff6f6SMatthew Dillon }
82*572ff6f6SMatthew Dillon }
83*572ff6f6SMatthew Dillon
84*572ff6f6SMatthew Dillon /*
85*572ff6f6SMatthew Dillon * Start Transmit at the PCU engine (unpause receive)
86*572ff6f6SMatthew Dillon */
87*572ff6f6SMatthew Dillon void
ar5211StartPcuReceive(struct ath_hal * ah)88*572ff6f6SMatthew Dillon ar5211StartPcuReceive(struct ath_hal *ah)
89*572ff6f6SMatthew Dillon {
90*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_DIAG_SW,
91*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
92*572ff6f6SMatthew Dillon }
93*572ff6f6SMatthew Dillon
94*572ff6f6SMatthew Dillon /*
95*572ff6f6SMatthew Dillon * Stop Transmit at the PCU engine (pause receive)
96*572ff6f6SMatthew Dillon */
97*572ff6f6SMatthew Dillon void
ar5211StopPcuReceive(struct ath_hal * ah)98*572ff6f6SMatthew Dillon ar5211StopPcuReceive(struct ath_hal *ah)
99*572ff6f6SMatthew Dillon {
100*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_DIAG_SW,
101*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
102*572ff6f6SMatthew Dillon }
103*572ff6f6SMatthew Dillon
104*572ff6f6SMatthew Dillon /*
105*572ff6f6SMatthew Dillon * Set multicast filter 0 (lower 32-bits)
106*572ff6f6SMatthew Dillon * filter 1 (upper 32-bits)
107*572ff6f6SMatthew Dillon */
108*572ff6f6SMatthew Dillon void
ar5211SetMulticastFilter(struct ath_hal * ah,uint32_t filter0,uint32_t filter1)109*572ff6f6SMatthew Dillon ar5211SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
110*572ff6f6SMatthew Dillon {
111*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
112*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
113*572ff6f6SMatthew Dillon }
114*572ff6f6SMatthew Dillon
115*572ff6f6SMatthew Dillon /*
116*572ff6f6SMatthew Dillon * Clear multicast filter by index
117*572ff6f6SMatthew Dillon */
118*572ff6f6SMatthew Dillon HAL_BOOL
ar5211ClrMulticastFilterIndex(struct ath_hal * ah,uint32_t ix)119*572ff6f6SMatthew Dillon ar5211ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
120*572ff6f6SMatthew Dillon {
121*572ff6f6SMatthew Dillon uint32_t val;
122*572ff6f6SMatthew Dillon
123*572ff6f6SMatthew Dillon if (ix >= 64)
124*572ff6f6SMatthew Dillon return AH_FALSE;
125*572ff6f6SMatthew Dillon if (ix >= 32) {
126*572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_MCAST_FIL1);
127*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
128*572ff6f6SMatthew Dillon } else {
129*572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_MCAST_FIL0);
130*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
131*572ff6f6SMatthew Dillon }
132*572ff6f6SMatthew Dillon return AH_TRUE;
133*572ff6f6SMatthew Dillon }
134*572ff6f6SMatthew Dillon
135*572ff6f6SMatthew Dillon /*
136*572ff6f6SMatthew Dillon * Set multicast filter by index
137*572ff6f6SMatthew Dillon */
138*572ff6f6SMatthew Dillon HAL_BOOL
ar5211SetMulticastFilterIndex(struct ath_hal * ah,uint32_t ix)139*572ff6f6SMatthew Dillon ar5211SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
140*572ff6f6SMatthew Dillon {
141*572ff6f6SMatthew Dillon uint32_t val;
142*572ff6f6SMatthew Dillon
143*572ff6f6SMatthew Dillon if (ix >= 64)
144*572ff6f6SMatthew Dillon return AH_FALSE;
145*572ff6f6SMatthew Dillon if (ix >= 32) {
146*572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_MCAST_FIL1);
147*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
148*572ff6f6SMatthew Dillon } else {
149*572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_MCAST_FIL0);
150*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
151*572ff6f6SMatthew Dillon }
152*572ff6f6SMatthew Dillon return AH_TRUE;
153*572ff6f6SMatthew Dillon }
154*572ff6f6SMatthew Dillon
155*572ff6f6SMatthew Dillon /*
156*572ff6f6SMatthew Dillon * Get receive filter.
157*572ff6f6SMatthew Dillon */
158*572ff6f6SMatthew Dillon uint32_t
ar5211GetRxFilter(struct ath_hal * ah)159*572ff6f6SMatthew Dillon ar5211GetRxFilter(struct ath_hal *ah)
160*572ff6f6SMatthew Dillon {
161*572ff6f6SMatthew Dillon return OS_REG_READ(ah, AR_RX_FILTER);
162*572ff6f6SMatthew Dillon }
163*572ff6f6SMatthew Dillon
164*572ff6f6SMatthew Dillon /*
165*572ff6f6SMatthew Dillon * Set receive filter.
166*572ff6f6SMatthew Dillon */
167*572ff6f6SMatthew Dillon void
ar5211SetRxFilter(struct ath_hal * ah,uint32_t bits)168*572ff6f6SMatthew Dillon ar5211SetRxFilter(struct ath_hal *ah, uint32_t bits)
169*572ff6f6SMatthew Dillon {
170*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RX_FILTER, bits);
171*572ff6f6SMatthew Dillon }
172*572ff6f6SMatthew Dillon
173*572ff6f6SMatthew Dillon /*
174*572ff6f6SMatthew Dillon * Initialize RX descriptor, by clearing the status and clearing
175*572ff6f6SMatthew Dillon * the size. This is not strictly HW dependent, but we want the
176*572ff6f6SMatthew Dillon * control and status words to be opaque above the hal.
177*572ff6f6SMatthew Dillon */
178*572ff6f6SMatthew Dillon HAL_BOOL
ar5211SetupRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t size,u_int flags)179*572ff6f6SMatthew Dillon ar5211SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
180*572ff6f6SMatthew Dillon uint32_t size, u_int flags)
181*572ff6f6SMatthew Dillon {
182*572ff6f6SMatthew Dillon struct ar5211_desc *ads = AR5211DESC(ds);
183*572ff6f6SMatthew Dillon
184*572ff6f6SMatthew Dillon ads->ds_ctl0 = 0;
185*572ff6f6SMatthew Dillon ads->ds_ctl1 = size & AR_BufLen;
186*572ff6f6SMatthew Dillon if (ads->ds_ctl1 != size) {
187*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
188*572ff6f6SMatthew Dillon __func__, size);
189*572ff6f6SMatthew Dillon return AH_FALSE;
190*572ff6f6SMatthew Dillon }
191*572ff6f6SMatthew Dillon if (flags & HAL_RXDESC_INTREQ)
192*572ff6f6SMatthew Dillon ads->ds_ctl1 |= AR_RxInterReq;
193*572ff6f6SMatthew Dillon ads->ds_status0 = ads->ds_status1 = 0;
194*572ff6f6SMatthew Dillon
195*572ff6f6SMatthew Dillon return AH_TRUE;
196*572ff6f6SMatthew Dillon }
197*572ff6f6SMatthew Dillon
198*572ff6f6SMatthew Dillon /*
199*572ff6f6SMatthew Dillon * Process an RX descriptor, and return the status to the caller.
200*572ff6f6SMatthew Dillon * Copy some hardware specific items into the software portion
201*572ff6f6SMatthew Dillon * of the descriptor.
202*572ff6f6SMatthew Dillon *
203*572ff6f6SMatthew Dillon * NB: the caller is responsible for validating the memory contents
204*572ff6f6SMatthew Dillon * of the descriptor (e.g. flushing any cached copy).
205*572ff6f6SMatthew Dillon */
206*572ff6f6SMatthew Dillon HAL_STATUS
ar5211ProcRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t pa,struct ath_desc * nds,uint64_t tsf,struct ath_rx_status * rs)207*572ff6f6SMatthew Dillon ar5211ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
208*572ff6f6SMatthew Dillon uint32_t pa, struct ath_desc *nds, uint64_t tsf,
209*572ff6f6SMatthew Dillon struct ath_rx_status *rs)
210*572ff6f6SMatthew Dillon {
211*572ff6f6SMatthew Dillon struct ar5211_desc *ads = AR5211DESC(ds);
212*572ff6f6SMatthew Dillon struct ar5211_desc *ands = AR5211DESC(nds);
213*572ff6f6SMatthew Dillon
214*572ff6f6SMatthew Dillon if ((ads->ds_status1 & AR_Done) == 0)
215*572ff6f6SMatthew Dillon return HAL_EINPROGRESS;
216*572ff6f6SMatthew Dillon /*
217*572ff6f6SMatthew Dillon * Given the use of a self-linked tail be very sure that the hw is
218*572ff6f6SMatthew Dillon * done with this descriptor; the hw may have done this descriptor
219*572ff6f6SMatthew Dillon * once and picked it up again...make sure the hw has moved on.
220*572ff6f6SMatthew Dillon */
221*572ff6f6SMatthew Dillon if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
222*572ff6f6SMatthew Dillon return HAL_EINPROGRESS;
223*572ff6f6SMatthew Dillon
224*572ff6f6SMatthew Dillon rs->rs_datalen = ads->ds_status0 & AR_DataLen;
225*572ff6f6SMatthew Dillon rs->rs_tstamp = MS(ads->ds_status1, AR_RcvTimestamp);
226*572ff6f6SMatthew Dillon rs->rs_status = 0;
227*572ff6f6SMatthew Dillon if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
228*572ff6f6SMatthew Dillon if (ads->ds_status1 & AR_CRCErr)
229*572ff6f6SMatthew Dillon rs->rs_status |= HAL_RXERR_CRC;
230*572ff6f6SMatthew Dillon else if (ads->ds_status1 & AR_DecryptCRCErr)
231*572ff6f6SMatthew Dillon rs->rs_status |= HAL_RXERR_DECRYPT;
232*572ff6f6SMatthew Dillon else {
233*572ff6f6SMatthew Dillon rs->rs_status |= HAL_RXERR_PHY;
234*572ff6f6SMatthew Dillon rs->rs_phyerr = MS(ads->ds_status1, AR_PHYErr);
235*572ff6f6SMatthew Dillon }
236*572ff6f6SMatthew Dillon }
237*572ff6f6SMatthew Dillon /* XXX what about KeyCacheMiss? */
238*572ff6f6SMatthew Dillon rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
239*572ff6f6SMatthew Dillon if (ads->ds_status1 & AR_KeyIdxValid)
240*572ff6f6SMatthew Dillon rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
241*572ff6f6SMatthew Dillon else
242*572ff6f6SMatthew Dillon rs->rs_keyix = HAL_RXKEYIX_INVALID;
243*572ff6f6SMatthew Dillon /* NB: caller expected to do rate table mapping */
244*572ff6f6SMatthew Dillon rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
245*572ff6f6SMatthew Dillon rs->rs_antenna = MS(ads->ds_status0, AR_RcvAntenna);
246*572ff6f6SMatthew Dillon rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;
247*572ff6f6SMatthew Dillon
248*572ff6f6SMatthew Dillon return HAL_OK;
249*572ff6f6SMatthew Dillon }
250