1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2002-2006 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon #include "opt_ah.h"
20572ff6f6SMatthew Dillon
21572ff6f6SMatthew Dillon /*
22572ff6f6SMatthew Dillon * Chips specific device attachment and device info collection
23572ff6f6SMatthew Dillon * Connects Init Reg Vectors, EEPROM Data, and device Functions.
24572ff6f6SMatthew Dillon */
25572ff6f6SMatthew Dillon #include "ah.h"
26572ff6f6SMatthew Dillon #include "ah_internal.h"
27572ff6f6SMatthew Dillon #include "ah_devid.h"
28572ff6f6SMatthew Dillon
29572ff6f6SMatthew Dillon #include "ar5211/ar5211.h"
30572ff6f6SMatthew Dillon #include "ar5211/ar5211reg.h"
31572ff6f6SMatthew Dillon #include "ar5211/ar5211phy.h"
32572ff6f6SMatthew Dillon
33572ff6f6SMatthew Dillon #include "ah_eeprom_v3.h"
34572ff6f6SMatthew Dillon
35572ff6f6SMatthew Dillon /* Add static register initialization vectors */
36572ff6f6SMatthew Dillon #include "ar5211/boss.ini"
37572ff6f6SMatthew Dillon
38572ff6f6SMatthew Dillon /*
39572ff6f6SMatthew Dillon * Structure to hold 11b tuning information for Beanie/Sombrero
40572ff6f6SMatthew Dillon * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12
41572ff6f6SMatthew Dillon */
42572ff6f6SMatthew Dillon typedef struct {
43572ff6f6SMatthew Dillon uint32_t refClkSel; /* reference clock, 1 for 16 MHz */
44572ff6f6SMatthew Dillon uint32_t channelSelect; /* P[7:4]S[3:0] bits */
45572ff6f6SMatthew Dillon uint16_t channel5111; /* 11a channel for 5111 */
46572ff6f6SMatthew Dillon } CHAN_INFO_2GHZ;
47572ff6f6SMatthew Dillon
48572ff6f6SMatthew Dillon #define CI_2GHZ_INDEX_CORRECTION 19
49572ff6f6SMatthew Dillon static const CHAN_INFO_2GHZ chan2GHzData[] = {
50572ff6f6SMatthew Dillon { 1, 0x46, 96 }, /* 2312 -19 */
51572ff6f6SMatthew Dillon { 1, 0x46, 97 }, /* 2317 -18 */
52572ff6f6SMatthew Dillon { 1, 0x46, 98 }, /* 2322 -17 */
53572ff6f6SMatthew Dillon { 1, 0x46, 99 }, /* 2327 -16 */
54572ff6f6SMatthew Dillon { 1, 0x46, 100 }, /* 2332 -15 */
55572ff6f6SMatthew Dillon { 1, 0x46, 101 }, /* 2337 -14 */
56572ff6f6SMatthew Dillon { 1, 0x46, 102 }, /* 2342 -13 */
57572ff6f6SMatthew Dillon { 1, 0x46, 103 }, /* 2347 -12 */
58572ff6f6SMatthew Dillon { 1, 0x46, 104 }, /* 2352 -11 */
59572ff6f6SMatthew Dillon { 1, 0x46, 105 }, /* 2357 -10 */
60572ff6f6SMatthew Dillon { 1, 0x46, 106 }, /* 2362 -9 */
61572ff6f6SMatthew Dillon { 1, 0x46, 107 }, /* 2367 -8 */
62572ff6f6SMatthew Dillon { 1, 0x46, 108 }, /* 2372 -7 */
63572ff6f6SMatthew Dillon /* index -6 to 0 are pad to make this a nolookup table */
64572ff6f6SMatthew Dillon { 1, 0x46, 116 }, /* -6 */
65572ff6f6SMatthew Dillon { 1, 0x46, 116 }, /* -5 */
66572ff6f6SMatthew Dillon { 1, 0x46, 116 }, /* -4 */
67572ff6f6SMatthew Dillon { 1, 0x46, 116 }, /* -3 */
68572ff6f6SMatthew Dillon { 1, 0x46, 116 }, /* -2 */
69572ff6f6SMatthew Dillon { 1, 0x46, 116 }, /* -1 */
70572ff6f6SMatthew Dillon { 1, 0x46, 116 }, /* 0 */
71572ff6f6SMatthew Dillon { 1, 0x46, 116 }, /* 2412 1 */
72572ff6f6SMatthew Dillon { 1, 0x46, 117 }, /* 2417 2 */
73572ff6f6SMatthew Dillon { 1, 0x46, 118 }, /* 2422 3 */
74572ff6f6SMatthew Dillon { 1, 0x46, 119 }, /* 2427 4 */
75572ff6f6SMatthew Dillon { 1, 0x46, 120 }, /* 2432 5 */
76572ff6f6SMatthew Dillon { 1, 0x46, 121 }, /* 2437 6 */
77572ff6f6SMatthew Dillon { 1, 0x46, 122 }, /* 2442 7 */
78572ff6f6SMatthew Dillon { 1, 0x46, 123 }, /* 2447 8 */
79572ff6f6SMatthew Dillon { 1, 0x46, 124 }, /* 2452 9 */
80572ff6f6SMatthew Dillon { 1, 0x46, 125 }, /* 2457 10 */
81572ff6f6SMatthew Dillon { 1, 0x46, 126 }, /* 2462 11 */
82572ff6f6SMatthew Dillon { 1, 0x46, 127 }, /* 2467 12 */
83572ff6f6SMatthew Dillon { 1, 0x46, 128 }, /* 2472 13 */
84572ff6f6SMatthew Dillon { 1, 0x44, 124 }, /* 2484 14 */
85572ff6f6SMatthew Dillon { 1, 0x46, 136 }, /* 2512 15 */
86572ff6f6SMatthew Dillon { 1, 0x46, 140 }, /* 2532 16 */
87572ff6f6SMatthew Dillon { 1, 0x46, 144 }, /* 2552 17 */
88572ff6f6SMatthew Dillon { 1, 0x46, 148 }, /* 2572 18 */
89572ff6f6SMatthew Dillon { 1, 0x46, 152 }, /* 2592 19 */
90572ff6f6SMatthew Dillon { 1, 0x46, 156 }, /* 2612 20 */
91572ff6f6SMatthew Dillon { 1, 0x46, 160 }, /* 2632 21 */
92572ff6f6SMatthew Dillon { 1, 0x46, 164 }, /* 2652 22 */
93572ff6f6SMatthew Dillon { 1, 0x46, 168 }, /* 2672 23 */
94572ff6f6SMatthew Dillon { 1, 0x46, 172 }, /* 2692 24 */
95572ff6f6SMatthew Dillon { 1, 0x46, 176 }, /* 2712 25 */
96572ff6f6SMatthew Dillon { 1, 0x46, 180 } /* 2732 26 */
97572ff6f6SMatthew Dillon };
98572ff6f6SMatthew Dillon
99572ff6f6SMatthew Dillon /* Power timeouts in usec to wait for chip to wake-up. */
100572ff6f6SMatthew Dillon #define POWER_UP_TIME 2000
101572ff6f6SMatthew Dillon
102572ff6f6SMatthew Dillon #define DELAY_PLL_SETTLE 300 /* 300 us */
103572ff6f6SMatthew Dillon #define DELAY_BASE_ACTIVATE 100 /* 100 us */
104572ff6f6SMatthew Dillon
105572ff6f6SMatthew Dillon #define NUM_RATES 8
106572ff6f6SMatthew Dillon
107572ff6f6SMatthew Dillon static HAL_BOOL ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask);
108572ff6f6SMatthew Dillon static HAL_BOOL ar5211SetChannel(struct ath_hal *,
109572ff6f6SMatthew Dillon const struct ieee80211_channel *);
110572ff6f6SMatthew Dillon static int16_t ar5211RunNoiseFloor(struct ath_hal *,
111572ff6f6SMatthew Dillon uint8_t runTime, int16_t startingNF);
112572ff6f6SMatthew Dillon static HAL_BOOL ar5211IsNfGood(struct ath_hal *,
113572ff6f6SMatthew Dillon struct ieee80211_channel *chan);
114572ff6f6SMatthew Dillon static HAL_BOOL ar5211SetRf6and7(struct ath_hal *,
115572ff6f6SMatthew Dillon const struct ieee80211_channel *chan);
116572ff6f6SMatthew Dillon static HAL_BOOL ar5211SetBoardValues(struct ath_hal *,
117572ff6f6SMatthew Dillon const struct ieee80211_channel *chan);
118572ff6f6SMatthew Dillon static void ar5211SetPowerTable(struct ath_hal *,
119572ff6f6SMatthew Dillon PCDACS_EEPROM *pSrcStruct, uint16_t channel);
120572ff6f6SMatthew Dillon static HAL_BOOL ar5211SetTransmitPower(struct ath_hal *,
121572ff6f6SMatthew Dillon const struct ieee80211_channel *);
122572ff6f6SMatthew Dillon static void ar5211SetRateTable(struct ath_hal *,
123572ff6f6SMatthew Dillon RD_EDGES_POWER *pRdEdgesPower, TRGT_POWER_INFO *pPowerInfo,
124572ff6f6SMatthew Dillon uint16_t numChannels, const struct ieee80211_channel *chan);
125572ff6f6SMatthew Dillon static uint16_t ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue,
126572ff6f6SMatthew Dillon const PCDACS_EEPROM *pSrcStruct);
127572ff6f6SMatthew Dillon static HAL_BOOL ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue,
128572ff6f6SMatthew Dillon const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue);
129572ff6f6SMatthew Dillon static uint16_t ar5211GetInterpolatedValue(uint16_t target,
130572ff6f6SMatthew Dillon uint16_t srcLeft, uint16_t srcRight,
131572ff6f6SMatthew Dillon uint16_t targetLeft, uint16_t targetRight, HAL_BOOL scaleUp);
132572ff6f6SMatthew Dillon static void ar5211GetLowerUpperValues(uint16_t value,
133572ff6f6SMatthew Dillon const uint16_t *pList, uint16_t listSize,
134572ff6f6SMatthew Dillon uint16_t *pLowerValue, uint16_t *pUpperValue);
135572ff6f6SMatthew Dillon static void ar5211GetLowerUpperPcdacs(uint16_t pcdac,
136572ff6f6SMatthew Dillon uint16_t channel, const PCDACS_EEPROM *pSrcStruct,
137572ff6f6SMatthew Dillon uint16_t *pLowerPcdac, uint16_t *pUpperPcdac);
138572ff6f6SMatthew Dillon
139572ff6f6SMatthew Dillon static void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *);
140572ff6f6SMatthew Dillon static void ar5211RequestRfgain(struct ath_hal *);
141572ff6f6SMatthew Dillon static HAL_BOOL ar5211InvalidGainReadback(struct ath_hal *, GAIN_VALUES *);
142572ff6f6SMatthew Dillon static HAL_BOOL ar5211IsGainAdjustNeeded(struct ath_hal *, const GAIN_VALUES *);
143572ff6f6SMatthew Dillon static int32_t ar5211AdjustGain(struct ath_hal *, GAIN_VALUES *);
144572ff6f6SMatthew Dillon static void ar5211SetOperatingMode(struct ath_hal *, int opmode);
145572ff6f6SMatthew Dillon
146572ff6f6SMatthew Dillon /*
147572ff6f6SMatthew Dillon * Places the device in and out of reset and then places sane
148572ff6f6SMatthew Dillon * values in the registers based on EEPROM config, initialization
149572ff6f6SMatthew Dillon * vectors (as determined by the mode), and station configuration
150572ff6f6SMatthew Dillon *
151572ff6f6SMatthew Dillon * bChannelChange is used to preserve DMA/PCU registers across
152572ff6f6SMatthew Dillon * a HW Reset during channel change.
153572ff6f6SMatthew Dillon */
154572ff6f6SMatthew Dillon HAL_BOOL
ar5211Reset(struct ath_hal * ah,HAL_OPMODE opmode,struct ieee80211_channel * chan,HAL_BOOL bChannelChange,HAL_RESET_TYPE resetType,HAL_STATUS * status)155572ff6f6SMatthew Dillon ar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode,
156572ff6f6SMatthew Dillon struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
157b14ca477SMatthew Dillon HAL_RESET_TYPE resetType,
158572ff6f6SMatthew Dillon HAL_STATUS *status)
159572ff6f6SMatthew Dillon {
160572ff6f6SMatthew Dillon uint32_t softLedCfg, softLedState;
161572ff6f6SMatthew Dillon #define N(a) (sizeof (a) /sizeof (a[0]))
162572ff6f6SMatthew Dillon #define FAIL(_code) do { ecode = _code; goto bad; } while (0)
163572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
164572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ichan;
165572ff6f6SMatthew Dillon uint32_t i, ledstate;
166572ff6f6SMatthew Dillon HAL_STATUS ecode;
167572ff6f6SMatthew Dillon int q;
168572ff6f6SMatthew Dillon
169572ff6f6SMatthew Dillon uint32_t data, synthDelay;
170572ff6f6SMatthew Dillon uint32_t macStaId1;
171572ff6f6SMatthew Dillon uint16_t modesIndex = 0, freqIndex = 0;
172572ff6f6SMatthew Dillon uint32_t saveFrameSeqCount[AR_NUM_DCU];
173572ff6f6SMatthew Dillon uint32_t saveTsfLow = 0, saveTsfHigh = 0;
174572ff6f6SMatthew Dillon uint32_t saveDefAntenna;
175572ff6f6SMatthew Dillon
176572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET,
177572ff6f6SMatthew Dillon "%s: opmode %u channel %u/0x%x %s channel\n",
178572ff6f6SMatthew Dillon __func__, opmode, chan->ic_freq, chan->ic_flags,
179572ff6f6SMatthew Dillon bChannelChange ? "change" : "same");
180572ff6f6SMatthew Dillon
181572ff6f6SMatthew Dillon OS_MARK(ah, AH_MARK_RESET, bChannelChange);
182572ff6f6SMatthew Dillon /*
183572ff6f6SMatthew Dillon * Map public channel to private.
184572ff6f6SMatthew Dillon */
185572ff6f6SMatthew Dillon ichan = ath_hal_checkchannel(ah, chan);
186572ff6f6SMatthew Dillon if (ichan == AH_NULL)
187572ff6f6SMatthew Dillon FAIL(HAL_EINVAL);
188572ff6f6SMatthew Dillon switch (opmode) {
189572ff6f6SMatthew Dillon case HAL_M_STA:
190572ff6f6SMatthew Dillon case HAL_M_IBSS:
191572ff6f6SMatthew Dillon case HAL_M_HOSTAP:
192572ff6f6SMatthew Dillon case HAL_M_MONITOR:
193572ff6f6SMatthew Dillon break;
194572ff6f6SMatthew Dillon default:
195572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
196572ff6f6SMatthew Dillon "%s: invalid operating mode %u\n", __func__, opmode);
197572ff6f6SMatthew Dillon FAIL(HAL_EINVAL);
198572ff6f6SMatthew Dillon break;
199572ff6f6SMatthew Dillon }
200572ff6f6SMatthew Dillon HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3);
201572ff6f6SMatthew Dillon
202572ff6f6SMatthew Dillon /* Preserve certain DMA hardware registers on a channel change */
203572ff6f6SMatthew Dillon if (bChannelChange) {
204572ff6f6SMatthew Dillon /*
205572ff6f6SMatthew Dillon * Need to save/restore the TSF because of an issue
206572ff6f6SMatthew Dillon * that accelerates the TSF during a chip reset.
207572ff6f6SMatthew Dillon *
208572ff6f6SMatthew Dillon * We could use system timer routines to more
209572ff6f6SMatthew Dillon * accurately restore the TSF, but
210572ff6f6SMatthew Dillon * 1. Timer routines on certain platforms are
211572ff6f6SMatthew Dillon * not accurate enough (e.g. 1 ms resolution).
212572ff6f6SMatthew Dillon * 2. It would still not be accurate.
213572ff6f6SMatthew Dillon *
214572ff6f6SMatthew Dillon * The most important aspect of this workaround,
215572ff6f6SMatthew Dillon * is that, after reset, the TSF is behind
216572ff6f6SMatthew Dillon * other STAs TSFs. This will allow the STA to
217572ff6f6SMatthew Dillon * properly resynchronize its TSF in adhoc mode.
218572ff6f6SMatthew Dillon */
219572ff6f6SMatthew Dillon saveTsfLow = OS_REG_READ(ah, AR_TSF_L32);
220572ff6f6SMatthew Dillon saveTsfHigh = OS_REG_READ(ah, AR_TSF_U32);
221572ff6f6SMatthew Dillon
222572ff6f6SMatthew Dillon /* Read frame sequence count */
223572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
224572ff6f6SMatthew Dillon saveFrameSeqCount[0] = OS_REG_READ(ah, AR_D0_SEQNUM);
225572ff6f6SMatthew Dillon } else {
226572ff6f6SMatthew Dillon for (i = 0; i < AR_NUM_DCU; i++)
227572ff6f6SMatthew Dillon saveFrameSeqCount[i] = OS_REG_READ(ah, AR_DSEQNUM(i));
228572ff6f6SMatthew Dillon }
229572ff6f6SMatthew Dillon if (!IEEE80211_IS_CHAN_DFS(chan))
230572ff6f6SMatthew Dillon chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
231572ff6f6SMatthew Dillon }
232572ff6f6SMatthew Dillon
233572ff6f6SMatthew Dillon /*
234572ff6f6SMatthew Dillon * Preserve the antenna on a channel change
235572ff6f6SMatthew Dillon */
236572ff6f6SMatthew Dillon saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
237572ff6f6SMatthew Dillon if (saveDefAntenna == 0)
238572ff6f6SMatthew Dillon saveDefAntenna = 1;
239572ff6f6SMatthew Dillon
240572ff6f6SMatthew Dillon /* Save hardware flag before chip reset clears the register */
241572ff6f6SMatthew Dillon macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
242572ff6f6SMatthew Dillon
243572ff6f6SMatthew Dillon /* Save led state from pci config register */
244572ff6f6SMatthew Dillon ledstate = OS_REG_READ(ah, AR_PCICFG) &
245572ff6f6SMatthew Dillon (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK |
246572ff6f6SMatthew Dillon AR_PCICFG_LEDSLOW);
247572ff6f6SMatthew Dillon softLedCfg = OS_REG_READ(ah, AR_GPIOCR);
248572ff6f6SMatthew Dillon softLedState = OS_REG_READ(ah, AR_GPIODO);
249572ff6f6SMatthew Dillon
250572ff6f6SMatthew Dillon if (!ar5211ChipReset(ah, chan)) {
251572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
252572ff6f6SMatthew Dillon FAIL(HAL_EIO);
253572ff6f6SMatthew Dillon }
254572ff6f6SMatthew Dillon
255572ff6f6SMatthew Dillon /* Setup the indices for the next set of register array writes */
256572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_5GHZ(chan)) {
257572ff6f6SMatthew Dillon freqIndex = 1;
258572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_TURBO(chan))
259572ff6f6SMatthew Dillon modesIndex = 2;
260572ff6f6SMatthew Dillon else if (IEEE80211_IS_CHAN_A(chan))
261572ff6f6SMatthew Dillon modesIndex = 1;
262572ff6f6SMatthew Dillon else {
263572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
264572ff6f6SMatthew Dillon "%s: invalid channel %u/0x%x\n",
265572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags);
266572ff6f6SMatthew Dillon FAIL(HAL_EINVAL);
267572ff6f6SMatthew Dillon }
268572ff6f6SMatthew Dillon } else {
269572ff6f6SMatthew Dillon freqIndex = 2;
270572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_B(chan))
271572ff6f6SMatthew Dillon modesIndex = 3;
272572ff6f6SMatthew Dillon else if (IEEE80211_IS_CHAN_PUREG(chan))
273572ff6f6SMatthew Dillon modesIndex = 4;
274572ff6f6SMatthew Dillon else {
275572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
276572ff6f6SMatthew Dillon "%s: invalid channel %u/0x%x\n",
277572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags);
278572ff6f6SMatthew Dillon FAIL(HAL_EINVAL);
279572ff6f6SMatthew Dillon }
280572ff6f6SMatthew Dillon }
281572ff6f6SMatthew Dillon
282572ff6f6SMatthew Dillon /* Set correct Baseband to analog shift setting to access analog chips. */
283572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
284572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
285572ff6f6SMatthew Dillon } else {
286572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
287572ff6f6SMatthew Dillon }
288572ff6f6SMatthew Dillon
289572ff6f6SMatthew Dillon /* Write parameters specific to AR5211 */
290572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
291572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_2GHZ(chan) &&
292572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) {
293572ff6f6SMatthew Dillon HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
294572ff6f6SMatthew Dillon uint32_t ob2GHz, db2GHz;
295572ff6f6SMatthew Dillon
296572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_CCK(chan)) {
297572ff6f6SMatthew Dillon ob2GHz = ee->ee_ob2GHz[0];
298572ff6f6SMatthew Dillon db2GHz = ee->ee_db2GHz[0];
299572ff6f6SMatthew Dillon } else {
300572ff6f6SMatthew Dillon ob2GHz = ee->ee_ob2GHz[1];
301572ff6f6SMatthew Dillon db2GHz = ee->ee_db2GHz[1];
302572ff6f6SMatthew Dillon }
303572ff6f6SMatthew Dillon ob2GHz = ath_hal_reverseBits(ob2GHz, 3);
304572ff6f6SMatthew Dillon db2GHz = ath_hal_reverseBits(db2GHz, 3);
305572ff6f6SMatthew Dillon ar5211Mode2_4[25][freqIndex] =
306572ff6f6SMatthew Dillon (ar5211Mode2_4[25][freqIndex] & ~0xC0) |
307572ff6f6SMatthew Dillon ((ob2GHz << 6) & 0xC0);
308572ff6f6SMatthew Dillon ar5211Mode2_4[26][freqIndex] =
309572ff6f6SMatthew Dillon (ar5211Mode2_4[26][freqIndex] & ~0x0F) |
310572ff6f6SMatthew Dillon (((ob2GHz >> 2) & 0x1) |
311572ff6f6SMatthew Dillon ((db2GHz << 1) & 0x0E));
312572ff6f6SMatthew Dillon }
313572ff6f6SMatthew Dillon for (i = 0; i < N(ar5211Mode2_4); i++)
314572ff6f6SMatthew Dillon OS_REG_WRITE(ah, ar5211Mode2_4[i][0],
315572ff6f6SMatthew Dillon ar5211Mode2_4[i][freqIndex]);
316572ff6f6SMatthew Dillon }
317572ff6f6SMatthew Dillon
318572ff6f6SMatthew Dillon /* Write the analog registers 6 and 7 before other config */
319572ff6f6SMatthew Dillon ar5211SetRf6and7(ah, chan);
320572ff6f6SMatthew Dillon
321572ff6f6SMatthew Dillon /* Write registers that vary across all modes */
322572ff6f6SMatthew Dillon for (i = 0; i < N(ar5211Modes); i++)
323572ff6f6SMatthew Dillon OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]);
324572ff6f6SMatthew Dillon
325572ff6f6SMatthew Dillon /* Write RFGain Parameters that differ between 2.4 and 5 GHz */
326572ff6f6SMatthew Dillon for (i = 0; i < N(ar5211BB_RfGain); i++)
327572ff6f6SMatthew Dillon OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]);
328572ff6f6SMatthew Dillon
329572ff6f6SMatthew Dillon /* Write Common Array Parameters */
330572ff6f6SMatthew Dillon for (i = 0; i < N(ar5211Common); i++) {
331572ff6f6SMatthew Dillon uint32_t reg = ar5211Common[i][0];
332572ff6f6SMatthew Dillon /* On channel change, don't reset the PCU registers */
333572ff6f6SMatthew Dillon if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))
334572ff6f6SMatthew Dillon OS_REG_WRITE(ah, reg, ar5211Common[i][1]);
335572ff6f6SMatthew Dillon }
336572ff6f6SMatthew Dillon
337572ff6f6SMatthew Dillon /* Fix pre-AR5211 register values, this includes AR5311s. */
338572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
339572ff6f6SMatthew Dillon /*
340572ff6f6SMatthew Dillon * The TX and RX latency values have changed locations
341572ff6f6SMatthew Dillon * within the USEC register in AR5211. Since they're
342572ff6f6SMatthew Dillon * set via the .ini, for both AR5211 and AR5311, they
343572ff6f6SMatthew Dillon * are written properly here for AR5311.
344572ff6f6SMatthew Dillon */
345572ff6f6SMatthew Dillon data = OS_REG_READ(ah, AR_USEC);
346572ff6f6SMatthew Dillon /* Must be 0 for proper write in AR5311 */
347572ff6f6SMatthew Dillon HALASSERT((data & 0x00700000) == 0);
348572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_USEC,
349572ff6f6SMatthew Dillon (data & (AR_USEC_M | AR_USEC_32_M | AR5311_USEC_TX_LAT_M)) |
350572ff6f6SMatthew Dillon ((29 << AR5311_USEC_RX_LAT_S) & AR5311_USEC_RX_LAT_M));
351572ff6f6SMatthew Dillon /* The following registers exist only on AR5311. */
352572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0);
353572ff6f6SMatthew Dillon
354572ff6f6SMatthew Dillon /* Set proper ADC & DAC delays for AR5311. */
355572ff6f6SMatthew Dillon OS_REG_WRITE(ah, 0x00009878, 0x00000008);
356572ff6f6SMatthew Dillon
357572ff6f6SMatthew Dillon /* Enable the PCU FIFO corruption ECO on AR5311. */
358572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_DIAG_SW,
359572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_DIAG_SW) | AR5311_DIAG_SW_USE_ECO);
360572ff6f6SMatthew Dillon }
361572ff6f6SMatthew Dillon
362572ff6f6SMatthew Dillon /* Restore certain DMA hardware registers on a channel change */
363572ff6f6SMatthew Dillon if (bChannelChange) {
364572ff6f6SMatthew Dillon /* Restore TSF */
365572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_TSF_L32, saveTsfLow);
366572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_TSF_U32, saveTsfHigh);
367572ff6f6SMatthew Dillon
368572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
369572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_D0_SEQNUM, saveFrameSeqCount[0]);
370572ff6f6SMatthew Dillon } else {
371572ff6f6SMatthew Dillon for (i = 0; i < AR_NUM_DCU; i++)
372572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_DSEQNUM(i), saveFrameSeqCount[i]);
373572ff6f6SMatthew Dillon }
374572ff6f6SMatthew Dillon }
375572ff6f6SMatthew Dillon
376572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
377572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
378572ff6f6SMatthew Dillon | macStaId1
379572ff6f6SMatthew Dillon );
380572ff6f6SMatthew Dillon ar5211SetOperatingMode(ah, opmode);
381572ff6f6SMatthew Dillon
382572ff6f6SMatthew Dillon /* Restore previous led state */
383572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
384572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg);
385572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_GPIODO, softLedState);
386572ff6f6SMatthew Dillon
387572ff6f6SMatthew Dillon /* Restore previous antenna */
388572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
389572ff6f6SMatthew Dillon
390572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
391572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
392572ff6f6SMatthew Dillon
393572ff6f6SMatthew Dillon /* Restore bmiss rssi & count thresholds */
394572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
395572ff6f6SMatthew Dillon
396572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
397572ff6f6SMatthew Dillon
398572ff6f6SMatthew Dillon /*
399572ff6f6SMatthew Dillon * for pre-Production Oahu only.
400572ff6f6SMatthew Dillon * Disable clock gating in all DMA blocks. Helps when using
401572ff6f6SMatthew Dillon * 11B and AES but results in higher power consumption.
402572ff6f6SMatthew Dillon */
403572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_OAHU &&
404572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev < AR_SREV_OAHU_PROD) {
405572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_CFG,
406572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_CFG) | AR_CFG_CLK_GATE_DIS);
407572ff6f6SMatthew Dillon }
408572ff6f6SMatthew Dillon
409572ff6f6SMatthew Dillon /* Setup the transmit power values. */
410572ff6f6SMatthew Dillon if (!ar5211SetTransmitPower(ah, chan)) {
411572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
412572ff6f6SMatthew Dillon "%s: error init'ing transmit power\n", __func__);
413572ff6f6SMatthew Dillon FAIL(HAL_EIO);
414572ff6f6SMatthew Dillon }
415572ff6f6SMatthew Dillon
416572ff6f6SMatthew Dillon /*
417572ff6f6SMatthew Dillon * Configurable OFDM spoofing for 11n compatibility; used
418572ff6f6SMatthew Dillon * only when operating in station mode.
419572ff6f6SMatthew Dillon */
420572ff6f6SMatthew Dillon if (opmode != HAL_M_HOSTAP &&
421572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_11nCompat & HAL_DIAG_11N_SERVICES) != 0) {
422572ff6f6SMatthew Dillon /* NB: override the .ini setting */
423572ff6f6SMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
424572ff6f6SMatthew Dillon AR_PHY_FRAME_CTL_ERR_SERV,
425572ff6f6SMatthew Dillon MS(AH_PRIVATE(ah)->ah_11nCompat, HAL_DIAG_11N_SERVICES)&1);
426572ff6f6SMatthew Dillon }
427572ff6f6SMatthew Dillon
428572ff6f6SMatthew Dillon /* Setup board specific options for EEPROM version 3 */
429572ff6f6SMatthew Dillon ar5211SetBoardValues(ah, chan);
430572ff6f6SMatthew Dillon
431572ff6f6SMatthew Dillon if (!ar5211SetChannel(ah, chan)) {
432572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
433572ff6f6SMatthew Dillon __func__);
434572ff6f6SMatthew Dillon FAIL(HAL_EIO);
435572ff6f6SMatthew Dillon }
436572ff6f6SMatthew Dillon
437572ff6f6SMatthew Dillon /* Activate the PHY */
438572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B &&
439572ff6f6SMatthew Dillon IEEE80211_IS_CHAN_2GHZ(chan))
440572ff6f6SMatthew Dillon OS_REG_WRITE(ah, 0xd808, 0x502); /* required for FPGA */
441572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
442572ff6f6SMatthew Dillon
443572ff6f6SMatthew Dillon /*
444572ff6f6SMatthew Dillon * Wait for the frequency synth to settle (synth goes on
445572ff6f6SMatthew Dillon * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
446572ff6f6SMatthew Dillon * Value is in 100ns increments.
447572ff6f6SMatthew Dillon */
448572ff6f6SMatthew Dillon data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_M;
449572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_CCK(chan)) {
450572ff6f6SMatthew Dillon synthDelay = (4 * data) / 22;
451572ff6f6SMatthew Dillon } else {
452572ff6f6SMatthew Dillon synthDelay = data / 10;
453572ff6f6SMatthew Dillon }
454572ff6f6SMatthew Dillon /*
455572ff6f6SMatthew Dillon * There is an issue if the AP starts the calibration before
456572ff6f6SMatthew Dillon * the baseband timeout completes. This could result in the
457572ff6f6SMatthew Dillon * rxclear false triggering. Add an extra delay to ensure this
458572ff6f6SMatthew Dillon * this does not happen.
459572ff6f6SMatthew Dillon */
460572ff6f6SMatthew Dillon OS_DELAY(synthDelay + DELAY_BASE_ACTIVATE);
461572ff6f6SMatthew Dillon
462572ff6f6SMatthew Dillon /* Calibrate the AGC and wait for completion. */
463572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
464572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
465572ff6f6SMatthew Dillon (void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0);
466572ff6f6SMatthew Dillon
467572ff6f6SMatthew Dillon /* Perform noise floor and set status */
468572ff6f6SMatthew Dillon if (!ar5211CalNoiseFloor(ah, chan)) {
469572ff6f6SMatthew Dillon if (!IEEE80211_IS_CHAN_CCK(chan))
470572ff6f6SMatthew Dillon chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
471572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
472572ff6f6SMatthew Dillon "%s: noise floor calibration failed\n", __func__);
473572ff6f6SMatthew Dillon FAIL(HAL_EIO);
474572ff6f6SMatthew Dillon }
475572ff6f6SMatthew Dillon
476572ff6f6SMatthew Dillon /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
477572ff6f6SMatthew Dillon if (ahp->ah_calibrationTime != 0) {
478572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,
479572ff6f6SMatthew Dillon AR_PHY_TIMING_CTRL4_DO_IQCAL | (INIT_IQCAL_LOG_COUNT_MAX << AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S));
480572ff6f6SMatthew Dillon ahp->ah_bIQCalibration = AH_TRUE;
481572ff6f6SMatthew Dillon }
482572ff6f6SMatthew Dillon
483572ff6f6SMatthew Dillon /* set 1:1 QCU to DCU mapping for all queues */
484572ff6f6SMatthew Dillon for (q = 0; q < AR_NUM_DCU; q++)
485572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_DQCUMASK(q), 1<<q);
486572ff6f6SMatthew Dillon
487572ff6f6SMatthew Dillon for (q = 0; q < HAL_NUM_TX_QUEUES; q++)
488572ff6f6SMatthew Dillon ar5211ResetTxQueue(ah, q);
489572ff6f6SMatthew Dillon
490572ff6f6SMatthew Dillon /* Setup QCU0 transmit interrupt masks (TX_ERR, TX_OK, TX_DESC, TX_URN) */
491572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_IMR_S0,
492572ff6f6SMatthew Dillon (AR_IMR_S0_QCU_TXOK & AR_QCU_0) |
493572ff6f6SMatthew Dillon (AR_IMR_S0_QCU_TXDESC & (AR_QCU_0<<AR_IMR_S0_QCU_TXDESC_S)));
494572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0));
495572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0));
496572ff6f6SMatthew Dillon
497572ff6f6SMatthew Dillon /*
498572ff6f6SMatthew Dillon * GBL_EIFS must always be written after writing
499572ff6f6SMatthew Dillon * to any QCUMASK register.
500572ff6f6SMatthew Dillon */
501572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, OS_REG_READ(ah, AR_D_GBL_IFS_EIFS));
502572ff6f6SMatthew Dillon
503572ff6f6SMatthew Dillon /* Now set up the Interrupt Mask Register and save it for future use */
504572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_IMR, INIT_INTERRUPT_MASK);
505572ff6f6SMatthew Dillon ahp->ah_maskReg = INIT_INTERRUPT_MASK;
506572ff6f6SMatthew Dillon
507572ff6f6SMatthew Dillon /* Enable bus error interrupts */
508572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) |
509572ff6f6SMatthew Dillon AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR);
510572ff6f6SMatthew Dillon
511572ff6f6SMatthew Dillon /* Enable interrupts specific to AP */
512572ff6f6SMatthew Dillon if (opmode == HAL_M_HOSTAP) {
513572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_MIB);
514572ff6f6SMatthew Dillon ahp->ah_maskReg |= AR_IMR_MIB;
515572ff6f6SMatthew Dillon }
516572ff6f6SMatthew Dillon
517572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_rfkillEnabled)
518572ff6f6SMatthew Dillon ar5211EnableRfKill(ah);
519572ff6f6SMatthew Dillon
520572ff6f6SMatthew Dillon /*
521572ff6f6SMatthew Dillon * Writing to AR_BEACON will start timers. Hence it should
522572ff6f6SMatthew Dillon * be the last register to be written. Do not reset tsf, do
523572ff6f6SMatthew Dillon * not enable beacons at this point, but preserve other values
524572ff6f6SMatthew Dillon * like beaconInterval.
525572ff6f6SMatthew Dillon */
526572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_BEACON,
527572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
528572ff6f6SMatthew Dillon
529572ff6f6SMatthew Dillon /* Restore user-specified slot time and timeouts */
530572ff6f6SMatthew Dillon if (ahp->ah_sifstime != (u_int) -1)
531572ff6f6SMatthew Dillon ar5211SetSifsTime(ah, ahp->ah_sifstime);
532572ff6f6SMatthew Dillon if (ahp->ah_slottime != (u_int) -1)
533572ff6f6SMatthew Dillon ar5211SetSlotTime(ah, ahp->ah_slottime);
534572ff6f6SMatthew Dillon if (ahp->ah_acktimeout != (u_int) -1)
535572ff6f6SMatthew Dillon ar5211SetAckTimeout(ah, ahp->ah_acktimeout);
536572ff6f6SMatthew Dillon if (ahp->ah_ctstimeout != (u_int) -1)
537572ff6f6SMatthew Dillon ar5211SetCTSTimeout(ah, ahp->ah_ctstimeout);
538572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_diagreg != 0)
539572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
540572ff6f6SMatthew Dillon
541572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
542572ff6f6SMatthew Dillon
543572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
544572ff6f6SMatthew Dillon
545572ff6f6SMatthew Dillon return AH_TRUE;
546572ff6f6SMatthew Dillon bad:
547572ff6f6SMatthew Dillon if (status != AH_NULL)
548572ff6f6SMatthew Dillon *status = ecode;
549572ff6f6SMatthew Dillon return AH_FALSE;
550572ff6f6SMatthew Dillon #undef FAIL
551572ff6f6SMatthew Dillon #undef N
552572ff6f6SMatthew Dillon }
553572ff6f6SMatthew Dillon
554572ff6f6SMatthew Dillon /*
555572ff6f6SMatthew Dillon * Places the PHY and Radio chips into reset. A full reset
556572ff6f6SMatthew Dillon * must be called to leave this state. The PCI/MAC/PCU are
557572ff6f6SMatthew Dillon * not placed into reset as we must receive interrupt to
558572ff6f6SMatthew Dillon * re-enable the hardware.
559572ff6f6SMatthew Dillon */
560572ff6f6SMatthew Dillon HAL_BOOL
ar5211PhyDisable(struct ath_hal * ah)561572ff6f6SMatthew Dillon ar5211PhyDisable(struct ath_hal *ah)
562572ff6f6SMatthew Dillon {
563572ff6f6SMatthew Dillon return ar5211SetResetReg(ah, AR_RC_BB);
564572ff6f6SMatthew Dillon }
565572ff6f6SMatthew Dillon
566572ff6f6SMatthew Dillon /*
567572ff6f6SMatthew Dillon * Places all of hardware into reset
568572ff6f6SMatthew Dillon */
569572ff6f6SMatthew Dillon HAL_BOOL
ar5211Disable(struct ath_hal * ah)570572ff6f6SMatthew Dillon ar5211Disable(struct ath_hal *ah)
571572ff6f6SMatthew Dillon {
572572ff6f6SMatthew Dillon if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
573572ff6f6SMatthew Dillon return AH_FALSE;
574572ff6f6SMatthew Dillon /*
575572ff6f6SMatthew Dillon * Reset the HW - PCI must be reset after the rest of the
576572ff6f6SMatthew Dillon * device has been reset.
577572ff6f6SMatthew Dillon */
578572ff6f6SMatthew Dillon if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
579572ff6f6SMatthew Dillon return AH_FALSE;
580572ff6f6SMatthew Dillon OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */
581572ff6f6SMatthew Dillon
582572ff6f6SMatthew Dillon return AH_TRUE;
583572ff6f6SMatthew Dillon }
584572ff6f6SMatthew Dillon
585572ff6f6SMatthew Dillon /*
586572ff6f6SMatthew Dillon * Places the hardware into reset and then pulls it out of reset
587572ff6f6SMatthew Dillon *
588572ff6f6SMatthew Dillon * Only write the PLL if we're changing to or from CCK mode
589572ff6f6SMatthew Dillon *
590572ff6f6SMatthew Dillon * Attach calls with channelFlags = 0, as the coldreset should have
591572ff6f6SMatthew Dillon * us in the correct mode and we cannot check the hwchannel flags.
592572ff6f6SMatthew Dillon */
593572ff6f6SMatthew Dillon HAL_BOOL
ar5211ChipReset(struct ath_hal * ah,const struct ieee80211_channel * chan)594572ff6f6SMatthew Dillon ar5211ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
595572ff6f6SMatthew Dillon {
596572ff6f6SMatthew Dillon if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
597572ff6f6SMatthew Dillon return AH_FALSE;
598572ff6f6SMatthew Dillon
599572ff6f6SMatthew Dillon /* NB: called from attach with chan null */
600572ff6f6SMatthew Dillon if (chan != AH_NULL) {
601572ff6f6SMatthew Dillon /* Set CCK and Turbo modes correctly */
602572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TURBO, IEEE80211_IS_CHAN_TURBO(chan) ?
603572ff6f6SMatthew Dillon AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT : 0);
604572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_B(chan)) {
605572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR5211_PHY_MODE,
606572ff6f6SMatthew Dillon AR5211_PHY_MODE_CCK | AR5211_PHY_MODE_RF2GHZ);
607572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
608572ff6f6SMatthew Dillon /* Wait for the PLL to settle */
609572ff6f6SMatthew Dillon OS_DELAY(DELAY_PLL_SETTLE);
610572ff6f6SMatthew Dillon } else if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
611572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
612572ff6f6SMatthew Dillon OS_DELAY(DELAY_PLL_SETTLE);
613572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR5211_PHY_MODE,
614572ff6f6SMatthew Dillon AR5211_PHY_MODE_OFDM | (IEEE80211_IS_CHAN_2GHZ(chan) ?
615572ff6f6SMatthew Dillon AR5211_PHY_MODE_RF2GHZ :
616572ff6f6SMatthew Dillon AR5211_PHY_MODE_RF5GHZ));
617572ff6f6SMatthew Dillon }
618572ff6f6SMatthew Dillon }
619572ff6f6SMatthew Dillon
620572ff6f6SMatthew Dillon /*
621572ff6f6SMatthew Dillon * Reset the HW - PCI must be reset after the rest of the
622572ff6f6SMatthew Dillon * device has been reset
623572ff6f6SMatthew Dillon */
624572ff6f6SMatthew Dillon if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
625572ff6f6SMatthew Dillon return AH_FALSE;
626572ff6f6SMatthew Dillon OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */
627572ff6f6SMatthew Dillon
628572ff6f6SMatthew Dillon /* Bring out of sleep mode (AGAIN) */
629572ff6f6SMatthew Dillon if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
630572ff6f6SMatthew Dillon return AH_FALSE;
631572ff6f6SMatthew Dillon
632572ff6f6SMatthew Dillon /* Clear warm reset register */
633572ff6f6SMatthew Dillon return ar5211SetResetReg(ah, 0);
634572ff6f6SMatthew Dillon }
635572ff6f6SMatthew Dillon
636572ff6f6SMatthew Dillon /*
637572ff6f6SMatthew Dillon * Recalibrate the lower PHY chips to account for temperature/environment
638572ff6f6SMatthew Dillon * changes.
639572ff6f6SMatthew Dillon */
640572ff6f6SMatthew Dillon HAL_BOOL
ar5211PerCalibrationN(struct ath_hal * ah,struct ieee80211_channel * chan,u_int chainMask,HAL_BOOL longCal,HAL_BOOL * isCalDone)641572ff6f6SMatthew Dillon ar5211PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
642572ff6f6SMatthew Dillon u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone)
643572ff6f6SMatthew Dillon {
644572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
645572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ichan;
646572ff6f6SMatthew Dillon int32_t qCoff, qCoffDenom;
647572ff6f6SMatthew Dillon uint32_t data;
648572ff6f6SMatthew Dillon int32_t iqCorrMeas;
649572ff6f6SMatthew Dillon int32_t iCoff, iCoffDenom;
650572ff6f6SMatthew Dillon uint32_t powerMeasQ, powerMeasI;
651572ff6f6SMatthew Dillon
652572ff6f6SMatthew Dillon ichan = ath_hal_checkchannel(ah, chan);
653572ff6f6SMatthew Dillon if (ichan == AH_NULL) {
654572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
655572ff6f6SMatthew Dillon "%s: invalid channel %u/0x%x; no mapping\n",
656572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags);
657572ff6f6SMatthew Dillon return AH_FALSE;
658572ff6f6SMatthew Dillon }
659572ff6f6SMatthew Dillon /* IQ calibration in progress. Check to see if it has finished. */
660572ff6f6SMatthew Dillon if (ahp->ah_bIQCalibration &&
661572ff6f6SMatthew Dillon !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
662572ff6f6SMatthew Dillon /* IQ Calibration has finished. */
663572ff6f6SMatthew Dillon ahp->ah_bIQCalibration = AH_FALSE;
664572ff6f6SMatthew Dillon
665572ff6f6SMatthew Dillon /* Read calibration results. */
666572ff6f6SMatthew Dillon powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I);
667572ff6f6SMatthew Dillon powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q);
668572ff6f6SMatthew Dillon iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS);
669572ff6f6SMatthew Dillon
670572ff6f6SMatthew Dillon /*
671572ff6f6SMatthew Dillon * Prescale these values to remove 64-bit operation requirement at the loss
672572ff6f6SMatthew Dillon * of a little precision.
673572ff6f6SMatthew Dillon */
674572ff6f6SMatthew Dillon iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
675572ff6f6SMatthew Dillon qCoffDenom = powerMeasQ / 64;
676572ff6f6SMatthew Dillon
677572ff6f6SMatthew Dillon /* Protect against divide-by-0. */
678572ff6f6SMatthew Dillon if (iCoffDenom != 0 && qCoffDenom != 0) {
679572ff6f6SMatthew Dillon iCoff = (-iqCorrMeas) / iCoffDenom;
680572ff6f6SMatthew Dillon /* IQCORR_Q_I_COFF is a signed 6 bit number */
681572ff6f6SMatthew Dillon iCoff = iCoff & 0x3f;
682572ff6f6SMatthew Dillon
683572ff6f6SMatthew Dillon qCoff = ((int32_t)powerMeasI / qCoffDenom) - 64;
684572ff6f6SMatthew Dillon /* IQCORR_Q_Q_COFF is a signed 5 bit number */
685572ff6f6SMatthew Dillon qCoff = qCoff & 0x1f;
686572ff6f6SMatthew Dillon
687572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasI = 0x%08x\n",
688572ff6f6SMatthew Dillon powerMeasI);
689572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasQ = 0x%08x\n",
690572ff6f6SMatthew Dillon powerMeasQ);
691572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, "iqCorrMeas = 0x%08x\n",
692572ff6f6SMatthew Dillon iqCorrMeas);
693572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, "iCoff = %d\n",
694572ff6f6SMatthew Dillon iCoff);
695572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, "qCoff = %d\n",
696572ff6f6SMatthew Dillon qCoff);
697572ff6f6SMatthew Dillon
698572ff6f6SMatthew Dillon /* Write IQ */
699572ff6f6SMatthew Dillon data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |
700572ff6f6SMatthew Dillon AR_PHY_TIMING_CTRL4_IQCORR_ENABLE |
701572ff6f6SMatthew Dillon (((uint32_t)iCoff) << AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S) |
702572ff6f6SMatthew Dillon ((uint32_t)qCoff);
703572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data);
704572ff6f6SMatthew Dillon }
705572ff6f6SMatthew Dillon }
706572ff6f6SMatthew Dillon *isCalDone = !ahp->ah_bIQCalibration;
707572ff6f6SMatthew Dillon
708572ff6f6SMatthew Dillon if (longCal) {
709572ff6f6SMatthew Dillon /* Perform noise floor and set status */
710572ff6f6SMatthew Dillon if (!ar5211IsNfGood(ah, chan)) {
711572ff6f6SMatthew Dillon /* report up and clear internal state */
712572ff6f6SMatthew Dillon chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
713572ff6f6SMatthew Dillon return AH_FALSE;
714572ff6f6SMatthew Dillon }
715572ff6f6SMatthew Dillon if (!ar5211CalNoiseFloor(ah, chan)) {
716572ff6f6SMatthew Dillon /*
717572ff6f6SMatthew Dillon * Delay 5ms before retrying the noise floor
718572ff6f6SMatthew Dillon * just to make sure, as we are in an error
719572ff6f6SMatthew Dillon * condition here.
720572ff6f6SMatthew Dillon */
721572ff6f6SMatthew Dillon OS_DELAY(5000);
722572ff6f6SMatthew Dillon if (!ar5211CalNoiseFloor(ah, chan)) {
723572ff6f6SMatthew Dillon if (!IEEE80211_IS_CHAN_CCK(chan))
724572ff6f6SMatthew Dillon chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
725572ff6f6SMatthew Dillon return AH_FALSE;
726572ff6f6SMatthew Dillon }
727572ff6f6SMatthew Dillon }
728572ff6f6SMatthew Dillon ar5211RequestRfgain(ah);
729572ff6f6SMatthew Dillon }
730572ff6f6SMatthew Dillon return AH_TRUE;
731572ff6f6SMatthew Dillon }
732572ff6f6SMatthew Dillon
733572ff6f6SMatthew Dillon HAL_BOOL
ar5211PerCalibration(struct ath_hal * ah,struct ieee80211_channel * chan,HAL_BOOL * isIQdone)734572ff6f6SMatthew Dillon ar5211PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
735572ff6f6SMatthew Dillon HAL_BOOL *isIQdone)
736572ff6f6SMatthew Dillon {
737572ff6f6SMatthew Dillon return ar5211PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
738572ff6f6SMatthew Dillon }
739572ff6f6SMatthew Dillon
740572ff6f6SMatthew Dillon HAL_BOOL
ar5211ResetCalValid(struct ath_hal * ah,const struct ieee80211_channel * chan)741572ff6f6SMatthew Dillon ar5211ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
742572ff6f6SMatthew Dillon {
743572ff6f6SMatthew Dillon /* XXX */
744572ff6f6SMatthew Dillon return AH_TRUE;
745572ff6f6SMatthew Dillon }
746572ff6f6SMatthew Dillon
747572ff6f6SMatthew Dillon /*
748572ff6f6SMatthew Dillon * Writes the given reset bit mask into the reset register
749572ff6f6SMatthew Dillon */
750572ff6f6SMatthew Dillon static HAL_BOOL
ar5211SetResetReg(struct ath_hal * ah,uint32_t resetMask)751572ff6f6SMatthew Dillon ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask)
752572ff6f6SMatthew Dillon {
753572ff6f6SMatthew Dillon uint32_t mask = resetMask ? resetMask : ~0;
754572ff6f6SMatthew Dillon HAL_BOOL rt;
755572ff6f6SMatthew Dillon
756572ff6f6SMatthew Dillon (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */
757572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RC, resetMask);
758572ff6f6SMatthew Dillon
759572ff6f6SMatthew Dillon /* need to wait at least 128 clocks when reseting PCI before read */
760572ff6f6SMatthew Dillon OS_DELAY(15);
761572ff6f6SMatthew Dillon
762572ff6f6SMatthew Dillon resetMask &= AR_RC_MAC | AR_RC_BB;
763572ff6f6SMatthew Dillon mask &= AR_RC_MAC | AR_RC_BB;
764572ff6f6SMatthew Dillon rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
765572ff6f6SMatthew Dillon if ((resetMask & AR_RC_MAC) == 0) {
766572ff6f6SMatthew Dillon if (isBigEndian()) {
767572ff6f6SMatthew Dillon /*
768572ff6f6SMatthew Dillon * Set CFG, little-endian for descriptor accesses.
769572ff6f6SMatthew Dillon */
770572ff6f6SMatthew Dillon mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD;
771572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_CFG, mask);
772572ff6f6SMatthew Dillon } else
773572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
774572ff6f6SMatthew Dillon }
775572ff6f6SMatthew Dillon return rt;
776572ff6f6SMatthew Dillon }
777572ff6f6SMatthew Dillon
778572ff6f6SMatthew Dillon /*
779572ff6f6SMatthew Dillon * Takes the MHz channel value and sets the Channel value
780572ff6f6SMatthew Dillon *
781572ff6f6SMatthew Dillon * ASSUMES: Writes enabled to analog bus before AGC is active
782572ff6f6SMatthew Dillon * or by disabling the AGC.
783572ff6f6SMatthew Dillon */
784572ff6f6SMatthew Dillon static HAL_BOOL
ar5211SetChannel(struct ath_hal * ah,const struct ieee80211_channel * chan)785572ff6f6SMatthew Dillon ar5211SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
786572ff6f6SMatthew Dillon {
787572ff6f6SMatthew Dillon uint32_t refClk, reg32, data2111;
788572ff6f6SMatthew Dillon int16_t chan5111, chanIEEE;
789572ff6f6SMatthew Dillon
790572ff6f6SMatthew Dillon chanIEEE = chan->ic_ieee;
791572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_2GHZ(chan)) {
792572ff6f6SMatthew Dillon const CHAN_INFO_2GHZ* ci =
793572ff6f6SMatthew Dillon &chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION];
794572ff6f6SMatthew Dillon
795572ff6f6SMatthew Dillon data2111 = ((ath_hal_reverseBits(ci->channelSelect, 8) & 0xff)
796572ff6f6SMatthew Dillon << 5)
797572ff6f6SMatthew Dillon | (ci->refClkSel << 4);
798572ff6f6SMatthew Dillon chan5111 = ci->channel5111;
799572ff6f6SMatthew Dillon } else {
800572ff6f6SMatthew Dillon data2111 = 0;
801572ff6f6SMatthew Dillon chan5111 = chanIEEE;
802572ff6f6SMatthew Dillon }
803572ff6f6SMatthew Dillon
804572ff6f6SMatthew Dillon /* Rest of the code is common for 5 GHz and 2.4 GHz. */
805572ff6f6SMatthew Dillon if (chan5111 >= 145 || (chan5111 & 0x1)) {
806572ff6f6SMatthew Dillon reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xFF;
807572ff6f6SMatthew Dillon refClk = 1;
808572ff6f6SMatthew Dillon } else {
809572ff6f6SMatthew Dillon reg32 = ath_hal_reverseBits(((chan5111 - 24) / 2), 8) & 0xFF;
810572ff6f6SMatthew Dillon refClk = 0;
811572ff6f6SMatthew Dillon }
812572ff6f6SMatthew Dillon
813572ff6f6SMatthew Dillon reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1;
814572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));
815572ff6f6SMatthew Dillon reg32 >>= 8;
816572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));
817572ff6f6SMatthew Dillon
818572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_curchan = chan;
819572ff6f6SMatthew Dillon return AH_TRUE;
820572ff6f6SMatthew Dillon }
821572ff6f6SMatthew Dillon
822572ff6f6SMatthew Dillon static int16_t
ar5211GetNoiseFloor(struct ath_hal * ah)823572ff6f6SMatthew Dillon ar5211GetNoiseFloor(struct ath_hal *ah)
824572ff6f6SMatthew Dillon {
825572ff6f6SMatthew Dillon int16_t nf;
826572ff6f6SMatthew Dillon
827572ff6f6SMatthew Dillon nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
828572ff6f6SMatthew Dillon if (nf & 0x100)
829572ff6f6SMatthew Dillon nf = 0 - ((nf ^ 0x1ff) + 1);
830572ff6f6SMatthew Dillon return nf;
831572ff6f6SMatthew Dillon }
832572ff6f6SMatthew Dillon
833572ff6f6SMatthew Dillon /*
834572ff6f6SMatthew Dillon * Peform the noisefloor calibration for the length of time set
835572ff6f6SMatthew Dillon * in runTime (valid values 1 to 7)
836572ff6f6SMatthew Dillon *
837572ff6f6SMatthew Dillon * Returns: The NF value at the end of the given time (or 0 for failure)
838572ff6f6SMatthew Dillon */
839572ff6f6SMatthew Dillon int16_t
ar5211RunNoiseFloor(struct ath_hal * ah,uint8_t runTime,int16_t startingNF)840572ff6f6SMatthew Dillon ar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF)
841572ff6f6SMatthew Dillon {
842572ff6f6SMatthew Dillon int i, searchTime;
843572ff6f6SMatthew Dillon
844572ff6f6SMatthew Dillon HALASSERT(runTime <= 7);
845572ff6f6SMatthew Dillon
846572ff6f6SMatthew Dillon /* Setup noise floor run time and starting value */
847572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(25),
848572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_PHY(25)) & ~0xFFF) |
849572ff6f6SMatthew Dillon ((runTime << 9) & 0xE00) | (startingNF & 0x1FF));
850572ff6f6SMatthew Dillon /* Calibrate the noise floor */
851572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
852572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
853572ff6f6SMatthew Dillon
854572ff6f6SMatthew Dillon /* Compute the required amount of searchTime needed to finish NF */
855572ff6f6SMatthew Dillon if (runTime == 0) {
856572ff6f6SMatthew Dillon /* 8 search windows * 6.4us each */
857572ff6f6SMatthew Dillon searchTime = 8 * 7;
858572ff6f6SMatthew Dillon } else {
859572ff6f6SMatthew Dillon /* 512 * runtime search windows * 6.4us each */
860572ff6f6SMatthew Dillon searchTime = (runTime * 512) * 7;
861572ff6f6SMatthew Dillon }
862572ff6f6SMatthew Dillon
863572ff6f6SMatthew Dillon /*
864572ff6f6SMatthew Dillon * Do not read noise floor until it has been updated
865572ff6f6SMatthew Dillon *
866572ff6f6SMatthew Dillon * As a guesstimate - we may only get 1/60th the time on
867572ff6f6SMatthew Dillon * the air to see search windows in a heavily congested
868572ff6f6SMatthew Dillon * network (40 us every 2400 us of time)
869572ff6f6SMatthew Dillon */
870572ff6f6SMatthew Dillon for (i = 0; i < 60; i++) {
871572ff6f6SMatthew Dillon if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0)
872572ff6f6SMatthew Dillon break;
873572ff6f6SMatthew Dillon OS_DELAY(searchTime);
874572ff6f6SMatthew Dillon }
875572ff6f6SMatthew Dillon if (i >= 60) {
876572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
877572ff6f6SMatthew Dillon "NF with runTime %d failed to end on channel %d\n",
878572ff6f6SMatthew Dillon runTime, AH_PRIVATE(ah)->ah_curchan->ic_freq);
879572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
880572ff6f6SMatthew Dillon " PHY NF Reg state: 0x%x\n",
881572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
882572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
883572ff6f6SMatthew Dillon " PHY Active Reg state: 0x%x\n",
884572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_ACTIVE));
885572ff6f6SMatthew Dillon return 0;
886572ff6f6SMatthew Dillon }
887572ff6f6SMatthew Dillon
888572ff6f6SMatthew Dillon return ar5211GetNoiseFloor(ah);
889572ff6f6SMatthew Dillon }
890572ff6f6SMatthew Dillon
891572ff6f6SMatthew Dillon static HAL_BOOL
getNoiseFloorThresh(struct ath_hal * ah,const struct ieee80211_channel * chan,int16_t * nft)892572ff6f6SMatthew Dillon getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan,
893572ff6f6SMatthew Dillon int16_t *nft)
894572ff6f6SMatthew Dillon {
895572ff6f6SMatthew Dillon HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
896572ff6f6SMatthew Dillon
897572ff6f6SMatthew Dillon switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
898572ff6f6SMatthew Dillon case IEEE80211_CHAN_A:
899572ff6f6SMatthew Dillon *nft = ee->ee_noiseFloorThresh[0];
900572ff6f6SMatthew Dillon break;
901572ff6f6SMatthew Dillon case IEEE80211_CHAN_B:
902572ff6f6SMatthew Dillon *nft = ee->ee_noiseFloorThresh[1];
903572ff6f6SMatthew Dillon break;
904572ff6f6SMatthew Dillon case IEEE80211_CHAN_PUREG:
905572ff6f6SMatthew Dillon *nft = ee->ee_noiseFloorThresh[2];
906572ff6f6SMatthew Dillon break;
907572ff6f6SMatthew Dillon default:
908572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
909572ff6f6SMatthew Dillon __func__, chan->ic_flags);
910572ff6f6SMatthew Dillon return AH_FALSE;
911572ff6f6SMatthew Dillon }
912572ff6f6SMatthew Dillon return AH_TRUE;
913572ff6f6SMatthew Dillon }
914572ff6f6SMatthew Dillon
915572ff6f6SMatthew Dillon /*
916b14ca477SMatthew Dillon * Read the NF and check it against the noise floor threshold
917572ff6f6SMatthew Dillon *
918572ff6f6SMatthew Dillon * Returns: TRUE if the NF is good
919572ff6f6SMatthew Dillon */
920572ff6f6SMatthew Dillon static HAL_BOOL
ar5211IsNfGood(struct ath_hal * ah,struct ieee80211_channel * chan)921572ff6f6SMatthew Dillon ar5211IsNfGood(struct ath_hal *ah, struct ieee80211_channel *chan)
922572ff6f6SMatthew Dillon {
923572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
924572ff6f6SMatthew Dillon int16_t nf, nfThresh;
925572ff6f6SMatthew Dillon
926572ff6f6SMatthew Dillon if (!getNoiseFloorThresh(ah, chan, &nfThresh))
927572ff6f6SMatthew Dillon return AH_FALSE;
928572ff6f6SMatthew Dillon if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
929572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
930572ff6f6SMatthew Dillon "%s: NF did not complete in calibration window\n", __func__);
931572ff6f6SMatthew Dillon }
932572ff6f6SMatthew Dillon nf = ar5211GetNoiseFloor(ah);
933572ff6f6SMatthew Dillon if (nf > nfThresh) {
934572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
935572ff6f6SMatthew Dillon "%s: noise floor failed; detected %u, threshold %u\n",
936572ff6f6SMatthew Dillon __func__, nf, nfThresh);
937572ff6f6SMatthew Dillon /*
938572ff6f6SMatthew Dillon * NB: Don't discriminate 2.4 vs 5Ghz, if this
939572ff6f6SMatthew Dillon * happens it indicates a problem regardless
940572ff6f6SMatthew Dillon * of the band.
941572ff6f6SMatthew Dillon */
942572ff6f6SMatthew Dillon chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
943572ff6f6SMatthew Dillon }
944572ff6f6SMatthew Dillon ichan->rawNoiseFloor = nf;
945572ff6f6SMatthew Dillon return (nf <= nfThresh);
946572ff6f6SMatthew Dillon }
947572ff6f6SMatthew Dillon
948572ff6f6SMatthew Dillon /*
949572ff6f6SMatthew Dillon * Peform the noisefloor calibration and check for any constant channel
950572ff6f6SMatthew Dillon * interference.
951572ff6f6SMatthew Dillon *
952572ff6f6SMatthew Dillon * NOTE: preAR5211 have a lengthy carrier wave detection process - hence
953572ff6f6SMatthew Dillon * it is if'ed for MKK regulatory domain only.
954572ff6f6SMatthew Dillon *
955572ff6f6SMatthew Dillon * Returns: TRUE for a successful noise floor calibration; else FALSE
956572ff6f6SMatthew Dillon */
957572ff6f6SMatthew Dillon HAL_BOOL
ar5211CalNoiseFloor(struct ath_hal * ah,const struct ieee80211_channel * chan)958572ff6f6SMatthew Dillon ar5211CalNoiseFloor(struct ath_hal *ah, const struct ieee80211_channel *chan)
959572ff6f6SMatthew Dillon {
960572ff6f6SMatthew Dillon #define N(a) (sizeof (a) / sizeof (a[0]))
961572ff6f6SMatthew Dillon /* Check for Carrier Wave interference in MKK regulatory zone */
962572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU &&
963572ff6f6SMatthew Dillon (chan->ic_flags & CHANNEL_NFCREQUIRED)) {
964572ff6f6SMatthew Dillon static const uint8_t runtime[3] = { 0, 2, 7 };
965572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
966572ff6f6SMatthew Dillon int16_t nf, nfThresh;
967572ff6f6SMatthew Dillon int i;
968572ff6f6SMatthew Dillon
969572ff6f6SMatthew Dillon if (!getNoiseFloorThresh(ah, chan, &nfThresh))
970572ff6f6SMatthew Dillon return AH_FALSE;
971572ff6f6SMatthew Dillon /*
972572ff6f6SMatthew Dillon * Run a quick noise floor that will hopefully
973572ff6f6SMatthew Dillon * complete (decrease delay time).
974572ff6f6SMatthew Dillon */
975572ff6f6SMatthew Dillon for (i = 0; i < N(runtime); i++) {
976572ff6f6SMatthew Dillon nf = ar5211RunNoiseFloor(ah, runtime[i], 0);
977572ff6f6SMatthew Dillon if (nf > nfThresh) {
978572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
979572ff6f6SMatthew Dillon "%s: run failed with %u > threshold %u "
980572ff6f6SMatthew Dillon "(runtime %u)\n", __func__,
981572ff6f6SMatthew Dillon nf, nfThresh, runtime[i]);
982572ff6f6SMatthew Dillon ichan->rawNoiseFloor = 0;
983572ff6f6SMatthew Dillon } else
984572ff6f6SMatthew Dillon ichan->rawNoiseFloor = nf;
985572ff6f6SMatthew Dillon }
986572ff6f6SMatthew Dillon return (i <= N(runtime));
987572ff6f6SMatthew Dillon } else {
988572ff6f6SMatthew Dillon /* Calibrate the noise floor */
989572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
990572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_AGC_CONTROL) |
991572ff6f6SMatthew Dillon AR_PHY_AGC_CONTROL_NF);
992572ff6f6SMatthew Dillon }
993572ff6f6SMatthew Dillon return AH_TRUE;
994572ff6f6SMatthew Dillon #undef N
995572ff6f6SMatthew Dillon }
996572ff6f6SMatthew Dillon
997572ff6f6SMatthew Dillon /*
998572ff6f6SMatthew Dillon * Adjust NF based on statistical values for 5GHz frequencies.
999572ff6f6SMatthew Dillon */
1000572ff6f6SMatthew Dillon int16_t
ar5211GetNfAdjust(struct ath_hal * ah,const HAL_CHANNEL_INTERNAL * c)1001572ff6f6SMatthew Dillon ar5211GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
1002572ff6f6SMatthew Dillon {
1003572ff6f6SMatthew Dillon static const struct {
1004572ff6f6SMatthew Dillon uint16_t freqLow;
1005572ff6f6SMatthew Dillon int16_t adjust;
1006572ff6f6SMatthew Dillon } adjust5111[] = {
1007572ff6f6SMatthew Dillon { 5790, 11 }, /* NB: ordered high -> low */
1008572ff6f6SMatthew Dillon { 5730, 10 },
1009572ff6f6SMatthew Dillon { 5690, 9 },
1010572ff6f6SMatthew Dillon { 5660, 8 },
1011572ff6f6SMatthew Dillon { 5610, 7 },
1012572ff6f6SMatthew Dillon { 5530, 5 },
1013572ff6f6SMatthew Dillon { 5450, 4 },
1014572ff6f6SMatthew Dillon { 5379, 2 },
1015572ff6f6SMatthew Dillon { 5209, 0 }, /* XXX? bogus but doesn't matter */
1016572ff6f6SMatthew Dillon { 0, 1 },
1017572ff6f6SMatthew Dillon };
1018572ff6f6SMatthew Dillon int i;
1019572ff6f6SMatthew Dillon
1020572ff6f6SMatthew Dillon for (i = 0; c->channel <= adjust5111[i].freqLow; i++)
1021572ff6f6SMatthew Dillon ;
1022572ff6f6SMatthew Dillon /* NB: placeholder for 5111's less severe requirement */
1023572ff6f6SMatthew Dillon return adjust5111[i].adjust / 3;
1024572ff6f6SMatthew Dillon }
1025572ff6f6SMatthew Dillon
1026572ff6f6SMatthew Dillon /*
1027572ff6f6SMatthew Dillon * Reads EEPROM header info from device structure and programs
1028572ff6f6SMatthew Dillon * analog registers 6 and 7
1029572ff6f6SMatthew Dillon *
1030572ff6f6SMatthew Dillon * REQUIRES: Access to the analog device
1031572ff6f6SMatthew Dillon */
1032572ff6f6SMatthew Dillon static HAL_BOOL
ar5211SetRf6and7(struct ath_hal * ah,const struct ieee80211_channel * chan)1033572ff6f6SMatthew Dillon ar5211SetRf6and7(struct ath_hal *ah, const struct ieee80211_channel *chan)
1034572ff6f6SMatthew Dillon {
1035572ff6f6SMatthew Dillon #define N(a) (sizeof (a) / sizeof (a[0]))
1036572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
1037572ff6f6SMatthew Dillon HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1038572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
1039572ff6f6SMatthew Dillon uint16_t rfXpdGain, rfPloSel, rfPwdXpd;
1040572ff6f6SMatthew Dillon uint16_t tempOB, tempDB;
1041572ff6f6SMatthew Dillon uint16_t freqIndex;
1042572ff6f6SMatthew Dillon int i;
1043572ff6f6SMatthew Dillon
1044572ff6f6SMatthew Dillon freqIndex = IEEE80211_IS_CHAN_2GHZ(chan) ? 2 : 1;
1045572ff6f6SMatthew Dillon
1046572ff6f6SMatthew Dillon /*
1047572ff6f6SMatthew Dillon * TODO: This array mode correspondes with the index used
1048572ff6f6SMatthew Dillon * during the read.
1049572ff6f6SMatthew Dillon * For readability, this should be changed to an enum or #define
1050572ff6f6SMatthew Dillon */
1051572ff6f6SMatthew Dillon switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
1052572ff6f6SMatthew Dillon case IEEE80211_CHAN_A:
1053572ff6f6SMatthew Dillon if (freq > 4000 && freq < 5260) {
1054572ff6f6SMatthew Dillon tempOB = ee->ee_ob1;
1055572ff6f6SMatthew Dillon tempDB = ee->ee_db1;
1056572ff6f6SMatthew Dillon } else if (freq >= 5260 && freq < 5500) {
1057572ff6f6SMatthew Dillon tempOB = ee->ee_ob2;
1058572ff6f6SMatthew Dillon tempDB = ee->ee_db2;
1059572ff6f6SMatthew Dillon } else if (freq >= 5500 && freq < 5725) {
1060572ff6f6SMatthew Dillon tempOB = ee->ee_ob3;
1061572ff6f6SMatthew Dillon tempDB = ee->ee_db3;
1062572ff6f6SMatthew Dillon } else if (freq >= 5725) {
1063572ff6f6SMatthew Dillon tempOB = ee->ee_ob4;
1064572ff6f6SMatthew Dillon tempDB = ee->ee_db4;
1065572ff6f6SMatthew Dillon } else {
1066572ff6f6SMatthew Dillon /* XXX panic?? */
1067572ff6f6SMatthew Dillon tempOB = tempDB = 0;
1068572ff6f6SMatthew Dillon }
1069572ff6f6SMatthew Dillon
1070572ff6f6SMatthew Dillon rfXpdGain = ee->ee_xgain[0];
1071572ff6f6SMatthew Dillon rfPloSel = ee->ee_xpd[0];
1072572ff6f6SMatthew Dillon rfPwdXpd = !ee->ee_xpd[0];
1073572ff6f6SMatthew Dillon
1074572ff6f6SMatthew Dillon ar5211Rf6n7[5][freqIndex] =
1075572ff6f6SMatthew Dillon (ar5211Rf6n7[5][freqIndex] & ~0x10000000) |
1076572ff6f6SMatthew Dillon (ee->ee_cornerCal.pd84<< 28);
1077572ff6f6SMatthew Dillon ar5211Rf6n7[6][freqIndex] =
1078572ff6f6SMatthew Dillon (ar5211Rf6n7[6][freqIndex] & ~0x04000000) |
1079572ff6f6SMatthew Dillon (ee->ee_cornerCal.pd90 << 26);
1080572ff6f6SMatthew Dillon ar5211Rf6n7[21][freqIndex] =
1081572ff6f6SMatthew Dillon (ar5211Rf6n7[21][freqIndex] & ~0x08) |
1082572ff6f6SMatthew Dillon (ee->ee_cornerCal.gSel << 3);
1083572ff6f6SMatthew Dillon break;
1084572ff6f6SMatthew Dillon case IEEE80211_CHAN_B:
1085572ff6f6SMatthew Dillon tempOB = ee->ee_obFor24;
1086572ff6f6SMatthew Dillon tempDB = ee->ee_dbFor24;
1087572ff6f6SMatthew Dillon rfXpdGain = ee->ee_xgain[1];
1088572ff6f6SMatthew Dillon rfPloSel = ee->ee_xpd[1];
1089572ff6f6SMatthew Dillon rfPwdXpd = !ee->ee_xpd[1];
1090572ff6f6SMatthew Dillon break;
1091572ff6f6SMatthew Dillon case IEEE80211_CHAN_PUREG:
1092572ff6f6SMatthew Dillon tempOB = ee->ee_obFor24g;
1093572ff6f6SMatthew Dillon tempDB = ee->ee_dbFor24g;
1094572ff6f6SMatthew Dillon rfXpdGain = ee->ee_xgain[2];
1095572ff6f6SMatthew Dillon rfPloSel = ee->ee_xpd[2];
1096572ff6f6SMatthew Dillon rfPwdXpd = !ee->ee_xpd[2];
1097572ff6f6SMatthew Dillon break;
1098572ff6f6SMatthew Dillon default:
1099572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
1100572ff6f6SMatthew Dillon __func__, chan->ic_flags);
1101572ff6f6SMatthew Dillon return AH_FALSE;
1102572ff6f6SMatthew Dillon }
1103572ff6f6SMatthew Dillon
1104572ff6f6SMatthew Dillon HALASSERT(1 <= tempOB && tempOB <= 5);
1105572ff6f6SMatthew Dillon HALASSERT(1 <= tempDB && tempDB <= 5);
1106572ff6f6SMatthew Dillon
1107572ff6f6SMatthew Dillon /* Set rfXpdGain and rfPwdXpd */
1108572ff6f6SMatthew Dillon ar5211Rf6n7[11][freqIndex] = (ar5211Rf6n7[11][freqIndex] & ~0xC0) |
1109572ff6f6SMatthew Dillon (((ath_hal_reverseBits(rfXpdGain, 4) << 7) | (rfPwdXpd << 6)) & 0xC0);
1110572ff6f6SMatthew Dillon ar5211Rf6n7[12][freqIndex] = (ar5211Rf6n7[12][freqIndex] & ~0x07) |
1111572ff6f6SMatthew Dillon ((ath_hal_reverseBits(rfXpdGain, 4) >> 1) & 0x07);
1112572ff6f6SMatthew Dillon
1113572ff6f6SMatthew Dillon /* Set OB */
1114572ff6f6SMatthew Dillon ar5211Rf6n7[12][freqIndex] = (ar5211Rf6n7[12][freqIndex] & ~0x80) |
1115572ff6f6SMatthew Dillon ((ath_hal_reverseBits(tempOB, 3) << 7) & 0x80);
1116572ff6f6SMatthew Dillon ar5211Rf6n7[13][freqIndex] = (ar5211Rf6n7[13][freqIndex] & ~0x03) |
1117572ff6f6SMatthew Dillon ((ath_hal_reverseBits(tempOB, 3) >> 1) & 0x03);
1118572ff6f6SMatthew Dillon
1119572ff6f6SMatthew Dillon /* Set DB */
1120572ff6f6SMatthew Dillon ar5211Rf6n7[13][freqIndex] = (ar5211Rf6n7[13][freqIndex] & ~0x1C) |
1121572ff6f6SMatthew Dillon ((ath_hal_reverseBits(tempDB, 3) << 2) & 0x1C);
1122572ff6f6SMatthew Dillon
1123572ff6f6SMatthew Dillon /* Set rfPloSel */
1124572ff6f6SMatthew Dillon ar5211Rf6n7[17][freqIndex] = (ar5211Rf6n7[17][freqIndex] & ~0x08) |
1125572ff6f6SMatthew Dillon ((rfPloSel << 3) & 0x08);
1126572ff6f6SMatthew Dillon
1127572ff6f6SMatthew Dillon /* Write the Rf registers 6 & 7 */
1128572ff6f6SMatthew Dillon for (i = 0; i < N(ar5211Rf6n7); i++)
1129572ff6f6SMatthew Dillon OS_REG_WRITE(ah, ar5211Rf6n7[i][0], ar5211Rf6n7[i][freqIndex]);
1130572ff6f6SMatthew Dillon
1131572ff6f6SMatthew Dillon /* Now that we have reprogrammed rfgain value, clear the flag. */
1132572ff6f6SMatthew Dillon ahp->ah_rfgainState = RFGAIN_INACTIVE;
1133572ff6f6SMatthew Dillon
1134572ff6f6SMatthew Dillon return AH_TRUE;
1135572ff6f6SMatthew Dillon #undef N
1136572ff6f6SMatthew Dillon }
1137572ff6f6SMatthew Dillon
1138572ff6f6SMatthew Dillon HAL_BOOL
ar5211SetAntennaSwitchInternal(struct ath_hal * ah,HAL_ANT_SETTING settings,const struct ieee80211_channel * chan)1139572ff6f6SMatthew Dillon ar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
1140572ff6f6SMatthew Dillon const struct ieee80211_channel *chan)
1141572ff6f6SMatthew Dillon {
1142572ff6f6SMatthew Dillon #define ANT_SWITCH_TABLE1 0x9960
1143572ff6f6SMatthew Dillon #define ANT_SWITCH_TABLE2 0x9964
1144572ff6f6SMatthew Dillon HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1145572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
1146572ff6f6SMatthew Dillon uint32_t antSwitchA, antSwitchB;
1147572ff6f6SMatthew Dillon int ix;
1148572ff6f6SMatthew Dillon
1149572ff6f6SMatthew Dillon switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
1150572ff6f6SMatthew Dillon case IEEE80211_CHAN_A: ix = 0; break;
1151572ff6f6SMatthew Dillon case IEEE80211_CHAN_B: ix = 1; break;
1152572ff6f6SMatthew Dillon case IEEE80211_CHAN_PUREG: ix = 2; break;
1153572ff6f6SMatthew Dillon default:
1154572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
1155572ff6f6SMatthew Dillon __func__, chan->ic_flags);
1156572ff6f6SMatthew Dillon return AH_FALSE;
1157572ff6f6SMatthew Dillon }
1158572ff6f6SMatthew Dillon
1159572ff6f6SMatthew Dillon antSwitchA = ee->ee_antennaControl[1][ix]
1160572ff6f6SMatthew Dillon | (ee->ee_antennaControl[2][ix] << 6)
1161572ff6f6SMatthew Dillon | (ee->ee_antennaControl[3][ix] << 12)
1162572ff6f6SMatthew Dillon | (ee->ee_antennaControl[4][ix] << 18)
1163572ff6f6SMatthew Dillon | (ee->ee_antennaControl[5][ix] << 24)
1164572ff6f6SMatthew Dillon ;
1165572ff6f6SMatthew Dillon antSwitchB = ee->ee_antennaControl[6][ix]
1166572ff6f6SMatthew Dillon | (ee->ee_antennaControl[7][ix] << 6)
1167572ff6f6SMatthew Dillon | (ee->ee_antennaControl[8][ix] << 12)
1168572ff6f6SMatthew Dillon | (ee->ee_antennaControl[9][ix] << 18)
1169572ff6f6SMatthew Dillon | (ee->ee_antennaControl[10][ix] << 24)
1170572ff6f6SMatthew Dillon ;
1171572ff6f6SMatthew Dillon /*
1172572ff6f6SMatthew Dillon * For fixed antenna, give the same setting for both switch banks
1173572ff6f6SMatthew Dillon */
1174572ff6f6SMatthew Dillon switch (settings) {
1175572ff6f6SMatthew Dillon case HAL_ANT_FIXED_A:
1176572ff6f6SMatthew Dillon antSwitchB = antSwitchA;
1177572ff6f6SMatthew Dillon break;
1178572ff6f6SMatthew Dillon case HAL_ANT_FIXED_B:
1179572ff6f6SMatthew Dillon antSwitchA = antSwitchB;
1180572ff6f6SMatthew Dillon break;
1181572ff6f6SMatthew Dillon case HAL_ANT_VARIABLE:
1182572ff6f6SMatthew Dillon break;
1183572ff6f6SMatthew Dillon default:
1184572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n",
1185572ff6f6SMatthew Dillon __func__, settings);
1186572ff6f6SMatthew Dillon return AH_FALSE;
1187572ff6f6SMatthew Dillon }
1188572ff6f6SMatthew Dillon ahp->ah_diversityControl = settings;
1189572ff6f6SMatthew Dillon
1190572ff6f6SMatthew Dillon OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA);
1191572ff6f6SMatthew Dillon OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB);
1192572ff6f6SMatthew Dillon
1193572ff6f6SMatthew Dillon return AH_TRUE;
1194572ff6f6SMatthew Dillon #undef ANT_SWITCH_TABLE1
1195572ff6f6SMatthew Dillon #undef ANT_SWITCH_TABLE2
1196572ff6f6SMatthew Dillon }
1197572ff6f6SMatthew Dillon
1198572ff6f6SMatthew Dillon /*
1199572ff6f6SMatthew Dillon * Reads EEPROM header info and programs the device for correct operation
1200572ff6f6SMatthew Dillon * given the channel value
1201572ff6f6SMatthew Dillon */
1202572ff6f6SMatthew Dillon static HAL_BOOL
ar5211SetBoardValues(struct ath_hal * ah,const struct ieee80211_channel * chan)1203572ff6f6SMatthew Dillon ar5211SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
1204572ff6f6SMatthew Dillon {
1205572ff6f6SMatthew Dillon HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1206572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
1207572ff6f6SMatthew Dillon int arrayMode, falseDectectBackoff;
1208572ff6f6SMatthew Dillon
1209572ff6f6SMatthew Dillon switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
1210572ff6f6SMatthew Dillon case IEEE80211_CHAN_A:
1211572ff6f6SMatthew Dillon arrayMode = 0;
1212572ff6f6SMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
1213572ff6f6SMatthew Dillon AR_PHY_FRAME_CTL_TX_CLIP, ee->ee_cornerCal.clip);
1214572ff6f6SMatthew Dillon break;
1215572ff6f6SMatthew Dillon case IEEE80211_CHAN_B:
1216572ff6f6SMatthew Dillon arrayMode = 1;
1217572ff6f6SMatthew Dillon break;
1218572ff6f6SMatthew Dillon case IEEE80211_CHAN_PUREG:
1219572ff6f6SMatthew Dillon arrayMode = 2;
1220572ff6f6SMatthew Dillon break;
1221572ff6f6SMatthew Dillon default:
1222572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
1223572ff6f6SMatthew Dillon __func__, chan->ic_flags);
1224572ff6f6SMatthew Dillon return AH_FALSE;
1225572ff6f6SMatthew Dillon }
1226572ff6f6SMatthew Dillon
1227572ff6f6SMatthew Dillon /* Set the antenna register(s) correctly for the chip revision */
1228572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
1229572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(68),
1230572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 0x3);
1231572ff6f6SMatthew Dillon } else {
1232572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(68),
1233572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFC06) |
1234572ff6f6SMatthew Dillon (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1);
1235572ff6f6SMatthew Dillon
1236572ff6f6SMatthew Dillon ar5211SetAntennaSwitchInternal(ah,
1237572ff6f6SMatthew Dillon ahp->ah_diversityControl, chan);
1238572ff6f6SMatthew Dillon
1239572ff6f6SMatthew Dillon /* Set the Noise Floor Thresh on ar5211 devices */
1240572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2),
1241572ff6f6SMatthew Dillon (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) | (1<<9));
1242572ff6f6SMatthew Dillon }
1243572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2),
1244572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) |
1245572ff6f6SMatthew Dillon ((ee->ee_switchSettling[arrayMode] << 7) & 0x3F80));
1246572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2),
1247572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) |
1248572ff6f6SMatthew Dillon ((ee->ee_txrxAtten[arrayMode] << 12) & 0x3F000));
1249572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2),
1250572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) |
1251572ff6f6SMatthew Dillon ((ee->ee_pgaDesiredSize[arrayMode] << 8) & 0xFF00) |
1252572ff6f6SMatthew Dillon (ee->ee_adcDesiredSize[arrayMode] & 0x00FF));
1253572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2),
1254572ff6f6SMatthew Dillon (ee->ee_txEndToXPAOff[arrayMode] << 24) |
1255572ff6f6SMatthew Dillon (ee->ee_txEndToXPAOff[arrayMode] << 16) |
1256572ff6f6SMatthew Dillon (ee->ee_txFrameToXPAOn[arrayMode] << 8) |
1257572ff6f6SMatthew Dillon ee->ee_txFrameToXPAOn[arrayMode]);
1258572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2),
1259572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) |
1260572ff6f6SMatthew Dillon (ee->ee_txEndToXLNAOn[arrayMode] << 8));
1261572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2),
1262572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) |
1263572ff6f6SMatthew Dillon ((ee->ee_thresh62[arrayMode] << 12) & 0x7F000));
1264572ff6f6SMatthew Dillon
1265572ff6f6SMatthew Dillon #define NO_FALSE_DETECT_BACKOFF 2
1266572ff6f6SMatthew Dillon #define CB22_FALSE_DETECT_BACKOFF 6
1267572ff6f6SMatthew Dillon /*
1268572ff6f6SMatthew Dillon * False detect backoff - suspected 32 MHz spur causes
1269572ff6f6SMatthew Dillon * false detects in OFDM, causing Tx Hangs. Decrease
1270572ff6f6SMatthew Dillon * weak signal sensitivity for this card.
1271572ff6f6SMatthew Dillon */
1272572ff6f6SMatthew Dillon falseDectectBackoff = NO_FALSE_DETECT_BACKOFF;
1273572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_eeversion < AR_EEPROM_VER3_3) {
1274572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&
1275572ff6f6SMatthew Dillon IEEE80211_IS_CHAN_OFDM(chan))
1276572ff6f6SMatthew Dillon falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF;
1277572ff6f6SMatthew Dillon } else {
1278572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
1279572ff6f6SMatthew Dillon uint32_t remainder = freq % 32;
1280572ff6f6SMatthew Dillon
1281572ff6f6SMatthew Dillon if (remainder && (remainder < 10 || remainder > 22))
1282572ff6f6SMatthew Dillon falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode];
1283572ff6f6SMatthew Dillon }
1284572ff6f6SMatthew Dillon OS_REG_WRITE(ah, 0x9924,
1285572ff6f6SMatthew Dillon (OS_REG_READ(ah, 0x9924) & 0xFFFFFF01)
1286572ff6f6SMatthew Dillon | ((falseDectectBackoff << 1) & 0xF7));
1287572ff6f6SMatthew Dillon
1288572ff6f6SMatthew Dillon return AH_TRUE;
1289572ff6f6SMatthew Dillon #undef NO_FALSE_DETECT_BACKOFF
1290572ff6f6SMatthew Dillon #undef CB22_FALSE_DETECT_BACKOFF
1291572ff6f6SMatthew Dillon }
1292572ff6f6SMatthew Dillon
1293572ff6f6SMatthew Dillon /*
1294572ff6f6SMatthew Dillon * Set the limit on the overall output power. Used for dynamic
1295572ff6f6SMatthew Dillon * transmit power control and the like.
1296572ff6f6SMatthew Dillon *
1297572ff6f6SMatthew Dillon * NOTE: The power is passed in is in units of 0.5 dBm.
1298572ff6f6SMatthew Dillon */
1299572ff6f6SMatthew Dillon HAL_BOOL
ar5211SetTxPowerLimit(struct ath_hal * ah,uint32_t limit)1300572ff6f6SMatthew Dillon ar5211SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
1301572ff6f6SMatthew Dillon {
1302572ff6f6SMatthew Dillon
1303572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
1304572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, limit);
1305572ff6f6SMatthew Dillon return AH_TRUE;
1306572ff6f6SMatthew Dillon }
1307572ff6f6SMatthew Dillon
1308572ff6f6SMatthew Dillon /*
1309572ff6f6SMatthew Dillon * Sets the transmit power in the baseband for the given
1310572ff6f6SMatthew Dillon * operating channel and mode.
1311572ff6f6SMatthew Dillon */
1312572ff6f6SMatthew Dillon static HAL_BOOL
ar5211SetTransmitPower(struct ath_hal * ah,const struct ieee80211_channel * chan)1313572ff6f6SMatthew Dillon ar5211SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)
1314572ff6f6SMatthew Dillon {
1315572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
1316572ff6f6SMatthew Dillon HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1317572ff6f6SMatthew Dillon TRGT_POWER_INFO *pi;
1318572ff6f6SMatthew Dillon RD_EDGES_POWER *rep;
1319572ff6f6SMatthew Dillon PCDACS_EEPROM eepromPcdacs;
1320572ff6f6SMatthew Dillon u_int nchan, cfgCtl;
1321572ff6f6SMatthew Dillon int i;
1322572ff6f6SMatthew Dillon
1323572ff6f6SMatthew Dillon /* setup the pcdac struct to point to the correct info, based on mode */
1324572ff6f6SMatthew Dillon switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
1325572ff6f6SMatthew Dillon case IEEE80211_CHAN_A:
1326572ff6f6SMatthew Dillon eepromPcdacs.numChannels = ee->ee_numChannels11a;
1327572ff6f6SMatthew Dillon eepromPcdacs.pChannelList= ee->ee_channels11a;
1328572ff6f6SMatthew Dillon eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;
1329572ff6f6SMatthew Dillon nchan = ee->ee_numTargetPwr_11a;
1330572ff6f6SMatthew Dillon pi = ee->ee_trgtPwr_11a;
1331572ff6f6SMatthew Dillon break;
1332572ff6f6SMatthew Dillon case IEEE80211_CHAN_PUREG:
1333572ff6f6SMatthew Dillon eepromPcdacs.numChannels = ee->ee_numChannels2_4;
1334572ff6f6SMatthew Dillon eepromPcdacs.pChannelList= ee->ee_channels11g;
1335572ff6f6SMatthew Dillon eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;
1336572ff6f6SMatthew Dillon nchan = ee->ee_numTargetPwr_11g;
1337572ff6f6SMatthew Dillon pi = ee->ee_trgtPwr_11g;
1338572ff6f6SMatthew Dillon break;
1339572ff6f6SMatthew Dillon case IEEE80211_CHAN_B:
1340572ff6f6SMatthew Dillon eepromPcdacs.numChannels = ee->ee_numChannels2_4;
1341572ff6f6SMatthew Dillon eepromPcdacs.pChannelList= ee->ee_channels11b;
1342572ff6f6SMatthew Dillon eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;
1343572ff6f6SMatthew Dillon nchan = ee->ee_numTargetPwr_11b;
1344572ff6f6SMatthew Dillon pi = ee->ee_trgtPwr_11b;
1345572ff6f6SMatthew Dillon break;
1346572ff6f6SMatthew Dillon default:
1347572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
1348572ff6f6SMatthew Dillon __func__, chan->ic_flags);
1349572ff6f6SMatthew Dillon return AH_FALSE;
1350572ff6f6SMatthew Dillon }
1351572ff6f6SMatthew Dillon
1352572ff6f6SMatthew Dillon ar5211SetPowerTable(ah, &eepromPcdacs, freq);
1353572ff6f6SMatthew Dillon
1354572ff6f6SMatthew Dillon rep = AH_NULL;
1355572ff6f6SMatthew Dillon /* Match CTL to EEPROM value */
1356572ff6f6SMatthew Dillon cfgCtl = ath_hal_getctl(ah, chan);
1357572ff6f6SMatthew Dillon for (i = 0; i < ee->ee_numCtls; i++)
1358572ff6f6SMatthew Dillon if (ee->ee_ctl[i] != 0 && ee->ee_ctl[i] == cfgCtl) {
1359572ff6f6SMatthew Dillon rep = &ee->ee_rdEdgesPower[i * NUM_EDGES];
1360572ff6f6SMatthew Dillon break;
1361572ff6f6SMatthew Dillon }
1362572ff6f6SMatthew Dillon ar5211SetRateTable(ah, rep, pi, nchan, chan);
1363572ff6f6SMatthew Dillon
1364572ff6f6SMatthew Dillon return AH_TRUE;
1365572ff6f6SMatthew Dillon }
1366572ff6f6SMatthew Dillon
1367572ff6f6SMatthew Dillon /*
1368572ff6f6SMatthew Dillon * Read the transmit power levels from the structures taken
1369572ff6f6SMatthew Dillon * from EEPROM. Interpolate read transmit power values for
1370572ff6f6SMatthew Dillon * this channel. Organize the transmit power values into a
1371572ff6f6SMatthew Dillon * table for writing into the hardware.
1372572ff6f6SMatthew Dillon */
1373572ff6f6SMatthew Dillon void
ar5211SetPowerTable(struct ath_hal * ah,PCDACS_EEPROM * pSrcStruct,uint16_t channel)1374572ff6f6SMatthew Dillon ar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct,
1375572ff6f6SMatthew Dillon uint16_t channel)
1376572ff6f6SMatthew Dillon {
1377572ff6f6SMatthew Dillon static FULL_PCDAC_STRUCT pcdacStruct;
1378572ff6f6SMatthew Dillon static uint16_t pcdacTable[PWR_TABLE_SIZE];
1379572ff6f6SMatthew Dillon
1380572ff6f6SMatthew Dillon uint16_t i, j;
1381572ff6f6SMatthew Dillon uint16_t *pPcdacValues;
1382572ff6f6SMatthew Dillon int16_t *pScaledUpDbm;
1383572ff6f6SMatthew Dillon int16_t minScaledPwr;
1384572ff6f6SMatthew Dillon int16_t maxScaledPwr;
1385572ff6f6SMatthew Dillon int16_t pwr;
1386572ff6f6SMatthew Dillon uint16_t pcdacMin = 0;
1387572ff6f6SMatthew Dillon uint16_t pcdacMax = 63;
1388572ff6f6SMatthew Dillon uint16_t pcdacTableIndex;
1389572ff6f6SMatthew Dillon uint16_t scaledPcdac;
1390572ff6f6SMatthew Dillon uint32_t addr;
1391572ff6f6SMatthew Dillon uint32_t temp32;
1392572ff6f6SMatthew Dillon
1393572ff6f6SMatthew Dillon OS_MEMZERO(&pcdacStruct, sizeof(FULL_PCDAC_STRUCT));
1394572ff6f6SMatthew Dillon OS_MEMZERO(pcdacTable, sizeof(uint16_t) * PWR_TABLE_SIZE);
1395572ff6f6SMatthew Dillon pPcdacValues = pcdacStruct.PcdacValues;
1396572ff6f6SMatthew Dillon pScaledUpDbm = pcdacStruct.PwrValues;
1397572ff6f6SMatthew Dillon
1398572ff6f6SMatthew Dillon /* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */
1399572ff6f6SMatthew Dillon for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++)
1400572ff6f6SMatthew Dillon pPcdacValues[j] = i;
1401572ff6f6SMatthew Dillon
1402572ff6f6SMatthew Dillon pcdacStruct.numPcdacValues = j;
1403572ff6f6SMatthew Dillon pcdacStruct.pcdacMin = PCDAC_START;
1404572ff6f6SMatthew Dillon pcdacStruct.pcdacMax = PCDAC_STOP;
1405572ff6f6SMatthew Dillon
1406572ff6f6SMatthew Dillon /* Fill out the power values for this channel */
1407572ff6f6SMatthew Dillon for (j = 0; j < pcdacStruct.numPcdacValues; j++ )
1408572ff6f6SMatthew Dillon pScaledUpDbm[j] = ar5211GetScaledPower(channel, pPcdacValues[j], pSrcStruct);
1409572ff6f6SMatthew Dillon
1410572ff6f6SMatthew Dillon /* Now scale the pcdac values to fit in the 64 entry power table */
1411572ff6f6SMatthew Dillon minScaledPwr = pScaledUpDbm[0];
1412572ff6f6SMatthew Dillon maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1];
1413572ff6f6SMatthew Dillon
1414572ff6f6SMatthew Dillon /* find minimum and make monotonic */
1415572ff6f6SMatthew Dillon for (j = 0; j < pcdacStruct.numPcdacValues; j++) {
1416572ff6f6SMatthew Dillon if (minScaledPwr >= pScaledUpDbm[j]) {
1417572ff6f6SMatthew Dillon minScaledPwr = pScaledUpDbm[j];
1418572ff6f6SMatthew Dillon pcdacMin = j;
1419572ff6f6SMatthew Dillon }
1420572ff6f6SMatthew Dillon /*
1421572ff6f6SMatthew Dillon * Make the full_hsh monotonically increasing otherwise
1422572ff6f6SMatthew Dillon * interpolation algorithm will get fooled gotta start
1423572ff6f6SMatthew Dillon * working from the top, hence i = 63 - j.
1424572ff6f6SMatthew Dillon */
1425572ff6f6SMatthew Dillon i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j);
1426572ff6f6SMatthew Dillon if (i == 0)
1427572ff6f6SMatthew Dillon break;
1428572ff6f6SMatthew Dillon if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) {
1429572ff6f6SMatthew Dillon /*
1430572ff6f6SMatthew Dillon * It could be a glitch, so make the power for
1431572ff6f6SMatthew Dillon * this pcdac the same as the power from the
1432572ff6f6SMatthew Dillon * next highest pcdac.
1433572ff6f6SMatthew Dillon */
1434572ff6f6SMatthew Dillon pScaledUpDbm[i - 1] = pScaledUpDbm[i];
1435572ff6f6SMatthew Dillon }
1436572ff6f6SMatthew Dillon }
1437572ff6f6SMatthew Dillon
1438572ff6f6SMatthew Dillon for (j = 0; j < pcdacStruct.numPcdacValues; j++)
1439572ff6f6SMatthew Dillon if (maxScaledPwr < pScaledUpDbm[j]) {
1440572ff6f6SMatthew Dillon maxScaledPwr = pScaledUpDbm[j];
1441572ff6f6SMatthew Dillon pcdacMax = j;
1442572ff6f6SMatthew Dillon }
1443572ff6f6SMatthew Dillon
1444572ff6f6SMatthew Dillon /* Find the first power level with a pcdac */
1445*ed183f8cSSascha Wildner pwr = (uint16_t)(rounddown(minScaledPwr - PWR_MIN + PWR_STEP / 2, PWR_STEP) + PWR_MIN);
1446572ff6f6SMatthew Dillon
1447572ff6f6SMatthew Dillon /* Write all the first pcdac entries based off the pcdacMin */
1448572ff6f6SMatthew Dillon pcdacTableIndex = 0;
1449572ff6f6SMatthew Dillon for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++)
1450572ff6f6SMatthew Dillon pcdacTable[pcdacTableIndex++] = pcdacMin;
1451572ff6f6SMatthew Dillon
1452572ff6f6SMatthew Dillon i = 0;
1453572ff6f6SMatthew Dillon while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1]) {
1454572ff6f6SMatthew Dillon pwr += PWR_STEP;
1455572ff6f6SMatthew Dillon /* stop if dbM > max_power_possible */
1456572ff6f6SMatthew Dillon while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
1457572ff6f6SMatthew Dillon (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0)
1458572ff6f6SMatthew Dillon i++;
1459572ff6f6SMatthew Dillon /* scale by 2 and add 1 to enable round up or down as needed */
1460572ff6f6SMatthew Dillon scaledPcdac = (uint16_t)(ar5211GetInterpolatedValue(pwr,
1461572ff6f6SMatthew Dillon pScaledUpDbm[i], pScaledUpDbm[i+1],
1462572ff6f6SMatthew Dillon (uint16_t)(pPcdacValues[i] * 2),
1463572ff6f6SMatthew Dillon (uint16_t)(pPcdacValues[i+1] * 2), 0) + 1);
1464572ff6f6SMatthew Dillon
1465572ff6f6SMatthew Dillon pcdacTable[pcdacTableIndex] = scaledPcdac / 2;
1466572ff6f6SMatthew Dillon if (pcdacTable[pcdacTableIndex] > pcdacMax)
1467572ff6f6SMatthew Dillon pcdacTable[pcdacTableIndex] = pcdacMax;
1468572ff6f6SMatthew Dillon pcdacTableIndex++;
1469572ff6f6SMatthew Dillon }
1470572ff6f6SMatthew Dillon
1471572ff6f6SMatthew Dillon /* Write all the last pcdac entries based off the last valid pcdac */
1472572ff6f6SMatthew Dillon while (pcdacTableIndex < PWR_TABLE_SIZE) {
1473572ff6f6SMatthew Dillon pcdacTable[pcdacTableIndex] = pcdacTable[pcdacTableIndex - 1];
1474572ff6f6SMatthew Dillon pcdacTableIndex++;
1475572ff6f6SMatthew Dillon }
1476572ff6f6SMatthew Dillon
1477572ff6f6SMatthew Dillon /* Finally, write the power values into the baseband power table */
1478572ff6f6SMatthew Dillon addr = AR_PHY_BASE + (608 << 2);
1479572ff6f6SMatthew Dillon for (i = 0; i < 32; i++) {
1480572ff6f6SMatthew Dillon temp32 = 0xffff & ((pcdacTable[2 * i + 1] << 8) | 0xff);
1481572ff6f6SMatthew Dillon temp32 = (temp32 << 16) | (0xffff & ((pcdacTable[2 * i] << 8) | 0xff));
1482572ff6f6SMatthew Dillon OS_REG_WRITE(ah, addr, temp32);
1483572ff6f6SMatthew Dillon addr += 4;
1484572ff6f6SMatthew Dillon }
1485572ff6f6SMatthew Dillon
1486572ff6f6SMatthew Dillon }
1487572ff6f6SMatthew Dillon
1488572ff6f6SMatthew Dillon /*
1489572ff6f6SMatthew Dillon * Set the transmit power in the baseband for the given
1490572ff6f6SMatthew Dillon * operating channel and mode.
1491572ff6f6SMatthew Dillon */
1492572ff6f6SMatthew Dillon static void
ar5211SetRateTable(struct ath_hal * ah,RD_EDGES_POWER * pRdEdgesPower,TRGT_POWER_INFO * pPowerInfo,uint16_t numChannels,const struct ieee80211_channel * chan)1493572ff6f6SMatthew Dillon ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
1494572ff6f6SMatthew Dillon TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels,
1495572ff6f6SMatthew Dillon const struct ieee80211_channel *chan)
1496572ff6f6SMatthew Dillon {
1497572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
1498572ff6f6SMatthew Dillon HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
1499572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
1500572ff6f6SMatthew Dillon static uint16_t ratesArray[NUM_RATES];
1501572ff6f6SMatthew Dillon static const uint16_t tpcScaleReductionTable[5] =
1502572ff6f6SMatthew Dillon { 0, 3, 6, 9, MAX_RATE_POWER };
1503572ff6f6SMatthew Dillon
1504572ff6f6SMatthew Dillon uint16_t *pRatesPower;
1505572ff6f6SMatthew Dillon uint16_t lowerChannel, lowerIndex=0, lowerPower=0;
1506572ff6f6SMatthew Dillon uint16_t upperChannel, upperIndex=0, upperPower=0;
1507572ff6f6SMatthew Dillon uint16_t twiceMaxEdgePower=63;
1508572ff6f6SMatthew Dillon uint16_t twicePower = 0;
1509572ff6f6SMatthew Dillon uint16_t i, numEdges;
1510572ff6f6SMatthew Dillon uint16_t tempChannelList[NUM_EDGES]; /* temp array for holding edge channels */
1511572ff6f6SMatthew Dillon uint16_t twiceMaxRDPower;
1512572ff6f6SMatthew Dillon int16_t scaledPower = 0; /* for gcc -O2 */
1513572ff6f6SMatthew Dillon uint16_t mask = 0x3f;
1514572ff6f6SMatthew Dillon HAL_BOOL paPreDEnable = 0;
1515572ff6f6SMatthew Dillon int8_t twiceAntennaGain, twiceAntennaReduction = 0;
1516572ff6f6SMatthew Dillon
1517572ff6f6SMatthew Dillon pRatesPower = ratesArray;
1518572ff6f6SMatthew Dillon twiceMaxRDPower = chan->ic_maxregpower * 2;
1519572ff6f6SMatthew Dillon
1520572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_5GHZ(chan)) {
1521572ff6f6SMatthew Dillon twiceAntennaGain = ee->ee_antennaGainMax[0];
1522572ff6f6SMatthew Dillon } else {
1523572ff6f6SMatthew Dillon twiceAntennaGain = ee->ee_antennaGainMax[1];
1524572ff6f6SMatthew Dillon }
1525572ff6f6SMatthew Dillon
1526572ff6f6SMatthew Dillon twiceAntennaReduction = ath_hal_getantennareduction(ah, chan, twiceAntennaGain);
1527572ff6f6SMatthew Dillon
1528572ff6f6SMatthew Dillon if (pRdEdgesPower) {
1529572ff6f6SMatthew Dillon /* Get the edge power */
1530572ff6f6SMatthew Dillon for (i = 0; i < NUM_EDGES; i++) {
1531572ff6f6SMatthew Dillon if (pRdEdgesPower[i].rdEdge == 0)
1532572ff6f6SMatthew Dillon break;
1533572ff6f6SMatthew Dillon tempChannelList[i] = pRdEdgesPower[i].rdEdge;
1534572ff6f6SMatthew Dillon }
1535572ff6f6SMatthew Dillon numEdges = i;
1536572ff6f6SMatthew Dillon
1537572ff6f6SMatthew Dillon ar5211GetLowerUpperValues(freq, tempChannelList,
1538572ff6f6SMatthew Dillon numEdges, &lowerChannel, &upperChannel);
1539572ff6f6SMatthew Dillon /* Get the index for this channel */
1540572ff6f6SMatthew Dillon for (i = 0; i < numEdges; i++)
1541572ff6f6SMatthew Dillon if (lowerChannel == tempChannelList[i])
1542572ff6f6SMatthew Dillon break;
1543572ff6f6SMatthew Dillon HALASSERT(i != numEdges);
1544572ff6f6SMatthew Dillon
1545572ff6f6SMatthew Dillon if ((lowerChannel == upperChannel &&
1546572ff6f6SMatthew Dillon lowerChannel == freq) ||
1547572ff6f6SMatthew Dillon pRdEdgesPower[i].flag) {
1548572ff6f6SMatthew Dillon twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower;
1549572ff6f6SMatthew Dillon HALASSERT(twiceMaxEdgePower > 0);
1550572ff6f6SMatthew Dillon }
1551572ff6f6SMatthew Dillon }
1552572ff6f6SMatthew Dillon
1553572ff6f6SMatthew Dillon /* extrapolate the power values for the test Groups */
1554572ff6f6SMatthew Dillon for (i = 0; i < numChannels; i++)
1555572ff6f6SMatthew Dillon tempChannelList[i] = pPowerInfo[i].testChannel;
1556572ff6f6SMatthew Dillon
1557572ff6f6SMatthew Dillon ar5211GetLowerUpperValues(freq, tempChannelList,
1558572ff6f6SMatthew Dillon numChannels, &lowerChannel, &upperChannel);
1559572ff6f6SMatthew Dillon
1560572ff6f6SMatthew Dillon /* get the index for the channel */
1561572ff6f6SMatthew Dillon for (i = 0; i < numChannels; i++) {
1562572ff6f6SMatthew Dillon if (lowerChannel == tempChannelList[i])
1563572ff6f6SMatthew Dillon lowerIndex = i;
1564572ff6f6SMatthew Dillon if (upperChannel == tempChannelList[i]) {
1565572ff6f6SMatthew Dillon upperIndex = i;
1566572ff6f6SMatthew Dillon break;
1567572ff6f6SMatthew Dillon }
1568572ff6f6SMatthew Dillon }
1569572ff6f6SMatthew Dillon
1570572ff6f6SMatthew Dillon for (i = 0; i < NUM_RATES; i++) {
1571572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_OFDM(chan)) {
1572572ff6f6SMatthew Dillon /* power for rates 6,9,12,18,24 is all the same */
1573572ff6f6SMatthew Dillon if (i < 5) {
1574572ff6f6SMatthew Dillon lowerPower = pPowerInfo[lowerIndex].twicePwr6_24;
1575572ff6f6SMatthew Dillon upperPower = pPowerInfo[upperIndex].twicePwr6_24;
1576572ff6f6SMatthew Dillon } else if (i == 5) {
1577572ff6f6SMatthew Dillon lowerPower = pPowerInfo[lowerIndex].twicePwr36;
1578572ff6f6SMatthew Dillon upperPower = pPowerInfo[upperIndex].twicePwr36;
1579572ff6f6SMatthew Dillon } else if (i == 6) {
1580572ff6f6SMatthew Dillon lowerPower = pPowerInfo[lowerIndex].twicePwr48;
1581572ff6f6SMatthew Dillon upperPower = pPowerInfo[upperIndex].twicePwr48;
1582572ff6f6SMatthew Dillon } else if (i == 7) {
1583572ff6f6SMatthew Dillon lowerPower = pPowerInfo[lowerIndex].twicePwr54;
1584572ff6f6SMatthew Dillon upperPower = pPowerInfo[upperIndex].twicePwr54;
1585572ff6f6SMatthew Dillon }
1586572ff6f6SMatthew Dillon } else {
1587572ff6f6SMatthew Dillon switch (i) {
1588572ff6f6SMatthew Dillon case 0:
1589572ff6f6SMatthew Dillon case 1:
1590572ff6f6SMatthew Dillon lowerPower = pPowerInfo[lowerIndex].twicePwr6_24;
1591572ff6f6SMatthew Dillon upperPower = pPowerInfo[upperIndex].twicePwr6_24;
1592572ff6f6SMatthew Dillon break;
1593572ff6f6SMatthew Dillon case 2:
1594572ff6f6SMatthew Dillon case 3:
1595572ff6f6SMatthew Dillon lowerPower = pPowerInfo[lowerIndex].twicePwr36;
1596572ff6f6SMatthew Dillon upperPower = pPowerInfo[upperIndex].twicePwr36;
1597572ff6f6SMatthew Dillon break;
1598572ff6f6SMatthew Dillon case 4:
1599572ff6f6SMatthew Dillon case 5:
1600572ff6f6SMatthew Dillon lowerPower = pPowerInfo[lowerIndex].twicePwr48;
1601572ff6f6SMatthew Dillon upperPower = pPowerInfo[upperIndex].twicePwr48;
1602572ff6f6SMatthew Dillon break;
1603572ff6f6SMatthew Dillon case 6:
1604572ff6f6SMatthew Dillon case 7:
1605572ff6f6SMatthew Dillon lowerPower = pPowerInfo[lowerIndex].twicePwr54;
1606572ff6f6SMatthew Dillon upperPower = pPowerInfo[upperIndex].twicePwr54;
1607572ff6f6SMatthew Dillon break;
1608572ff6f6SMatthew Dillon }
1609572ff6f6SMatthew Dillon }
1610572ff6f6SMatthew Dillon
1611572ff6f6SMatthew Dillon twicePower = ar5211GetInterpolatedValue(freq,
1612572ff6f6SMatthew Dillon lowerChannel, upperChannel, lowerPower, upperPower, 0);
1613572ff6f6SMatthew Dillon
1614572ff6f6SMatthew Dillon /* Reduce power by band edge restrictions */
1615572ff6f6SMatthew Dillon twicePower = AH_MIN(twicePower, twiceMaxEdgePower);
1616572ff6f6SMatthew Dillon
1617572ff6f6SMatthew Dillon /*
1618572ff6f6SMatthew Dillon * If turbo is set, reduce power to keep power
1619572ff6f6SMatthew Dillon * consumption under 2 Watts. Note that we always do
1620572ff6f6SMatthew Dillon * this unless specially configured. Then we limit
1621572ff6f6SMatthew Dillon * power only for non-AP operation.
1622572ff6f6SMatthew Dillon */
1623572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_TURBO(chan) &&
1624572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1
1625572ff6f6SMatthew Dillon #ifdef AH_ENABLE_AP_SUPPORT
1626572ff6f6SMatthew Dillon && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP
1627572ff6f6SMatthew Dillon #endif
1628572ff6f6SMatthew Dillon ) {
1629572ff6f6SMatthew Dillon twicePower = AH_MIN(twicePower, ee->ee_turbo2WMaxPower5);
1630572ff6f6SMatthew Dillon }
1631572ff6f6SMatthew Dillon
1632572ff6f6SMatthew Dillon /* Reduce power by max regulatory domain allowed restrictions */
1633572ff6f6SMatthew Dillon pRatesPower[i] = AH_MIN(twicePower, twiceMaxRDPower - twiceAntennaReduction);
1634572ff6f6SMatthew Dillon
1635572ff6f6SMatthew Dillon /* Use 6 Mb power level for transmit power scaling reduction */
1636572ff6f6SMatthew Dillon /* We don't want to reduce higher rates if its not needed */
1637572ff6f6SMatthew Dillon if (i == 0) {
1638572ff6f6SMatthew Dillon scaledPower = pRatesPower[0] -
1639572ff6f6SMatthew Dillon (tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2);
1640572ff6f6SMatthew Dillon if (scaledPower < 1)
1641572ff6f6SMatthew Dillon scaledPower = 1;
1642572ff6f6SMatthew Dillon }
1643572ff6f6SMatthew Dillon
1644572ff6f6SMatthew Dillon pRatesPower[i] = AH_MIN(pRatesPower[i], scaledPower);
1645572ff6f6SMatthew Dillon }
1646572ff6f6SMatthew Dillon
1647572ff6f6SMatthew Dillon /* Record txPower at Rate 6 for info gathering */
1648572ff6f6SMatthew Dillon ahp->ah_tx6PowerInHalfDbm = pRatesPower[0];
1649572ff6f6SMatthew Dillon
1650572ff6f6SMatthew Dillon #ifdef AH_DEBUG
1651572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET,
1652572ff6f6SMatthew Dillon "%s: final output power setting %d MHz:\n",
1653572ff6f6SMatthew Dillon __func__, chan->ic_freq);
1654572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET,
1655572ff6f6SMatthew Dillon "6 Mb %d dBm, MaxRD: %d dBm, MaxEdge %d dBm\n",
1656572ff6f6SMatthew Dillon scaledPower / 2, twiceMaxRDPower / 2, twiceMaxEdgePower / 2);
1657572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET, "TPC Scale %d dBm - Ant Red %d dBm\n",
1658572ff6f6SMatthew Dillon tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2,
1659572ff6f6SMatthew Dillon twiceAntennaReduction / 2);
1660572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_TURBO(chan) &&
1661572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1)
1662572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET, "Max Turbo %d dBm\n",
1663572ff6f6SMatthew Dillon ee->ee_turbo2WMaxPower5);
1664572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET,
1665572ff6f6SMatthew Dillon " %2d | %2d | %2d | %2d | %2d | %2d | %2d | %2d dBm\n",
1666572ff6f6SMatthew Dillon pRatesPower[0] / 2, pRatesPower[1] / 2, pRatesPower[2] / 2,
1667572ff6f6SMatthew Dillon pRatesPower[3] / 2, pRatesPower[4] / 2, pRatesPower[5] / 2,
1668572ff6f6SMatthew Dillon pRatesPower[6] / 2, pRatesPower[7] / 2);
1669572ff6f6SMatthew Dillon #endif /* AH_DEBUG */
1670572ff6f6SMatthew Dillon
1671572ff6f6SMatthew Dillon /* Write the power table into the hardware */
1672572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1673572ff6f6SMatthew Dillon ((paPreDEnable & 1)<< 30) | ((pRatesPower[3] & mask) << 24) |
1674572ff6f6SMatthew Dillon ((paPreDEnable & 1)<< 22) | ((pRatesPower[2] & mask) << 16) |
1675572ff6f6SMatthew Dillon ((paPreDEnable & 1)<< 14) | ((pRatesPower[1] & mask) << 8) |
1676572ff6f6SMatthew Dillon ((paPreDEnable & 1)<< 6 ) | (pRatesPower[0] & mask));
1677572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1678572ff6f6SMatthew Dillon ((paPreDEnable & 1)<< 30) | ((pRatesPower[7] & mask) << 24) |
1679572ff6f6SMatthew Dillon ((paPreDEnable & 1)<< 22) | ((pRatesPower[6] & mask) << 16) |
1680572ff6f6SMatthew Dillon ((paPreDEnable & 1)<< 14) | ((pRatesPower[5] & mask) << 8) |
1681572ff6f6SMatthew Dillon ((paPreDEnable & 1)<< 6 ) | (pRatesPower[4] & mask));
1682572ff6f6SMatthew Dillon
1683572ff6f6SMatthew Dillon /* set max power to the power value at rate 6 */
1684572ff6f6SMatthew Dillon ar5211SetTxPowerLimit(ah, pRatesPower[0]);
1685572ff6f6SMatthew Dillon
1686572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_maxPowerLevel = pRatesPower[0];
1687572ff6f6SMatthew Dillon }
1688572ff6f6SMatthew Dillon
1689572ff6f6SMatthew Dillon /*
1690572ff6f6SMatthew Dillon * Get or interpolate the pcdac value from the calibrated data
1691572ff6f6SMatthew Dillon */
1692572ff6f6SMatthew Dillon uint16_t
ar5211GetScaledPower(uint16_t channel,uint16_t pcdacValue,const PCDACS_EEPROM * pSrcStruct)1693572ff6f6SMatthew Dillon ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue,
1694572ff6f6SMatthew Dillon const PCDACS_EEPROM *pSrcStruct)
1695572ff6f6SMatthew Dillon {
1696572ff6f6SMatthew Dillon uint16_t powerValue;
1697572ff6f6SMatthew Dillon uint16_t lFreq, rFreq; /* left and right frequency values */
1698572ff6f6SMatthew Dillon uint16_t llPcdac, ulPcdac; /* lower and upper left pcdac values */
1699572ff6f6SMatthew Dillon uint16_t lrPcdac, urPcdac; /* lower and upper right pcdac values */
1700572ff6f6SMatthew Dillon uint16_t lPwr, uPwr; /* lower and upper temp pwr values */
1701572ff6f6SMatthew Dillon uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */
1702572ff6f6SMatthew Dillon
1703572ff6f6SMatthew Dillon if (ar5211FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue))
1704572ff6f6SMatthew Dillon /* value was copied from srcStruct */
1705572ff6f6SMatthew Dillon return powerValue;
1706572ff6f6SMatthew Dillon
1707572ff6f6SMatthew Dillon ar5211GetLowerUpperValues(channel, pSrcStruct->pChannelList,
1708572ff6f6SMatthew Dillon pSrcStruct->numChannels, &lFreq, &rFreq);
1709572ff6f6SMatthew Dillon ar5211GetLowerUpperPcdacs(pcdacValue, lFreq, pSrcStruct,
1710572ff6f6SMatthew Dillon &llPcdac, &ulPcdac);
1711572ff6f6SMatthew Dillon ar5211GetLowerUpperPcdacs(pcdacValue, rFreq, pSrcStruct,
1712572ff6f6SMatthew Dillon &lrPcdac, &urPcdac);
1713572ff6f6SMatthew Dillon
1714572ff6f6SMatthew Dillon /* get the power index for the pcdac value */
171557e09377SMatthew Dillon lPwr = 0; /* avoid gcc warnings */
171657e09377SMatthew Dillon uPwr = 0; /* avoid gcc warnings */
1717572ff6f6SMatthew Dillon ar5211FindValueInList(lFreq, llPcdac, pSrcStruct, &lPwr);
1718572ff6f6SMatthew Dillon ar5211FindValueInList(lFreq, ulPcdac, pSrcStruct, &uPwr);
1719572ff6f6SMatthew Dillon lScaledPwr = ar5211GetInterpolatedValue(pcdacValue,
1720572ff6f6SMatthew Dillon llPcdac, ulPcdac, lPwr, uPwr, 0);
1721572ff6f6SMatthew Dillon
1722572ff6f6SMatthew Dillon ar5211FindValueInList(rFreq, lrPcdac, pSrcStruct, &lPwr);
1723572ff6f6SMatthew Dillon ar5211FindValueInList(rFreq, urPcdac, pSrcStruct, &uPwr);
1724572ff6f6SMatthew Dillon rScaledPwr = ar5211GetInterpolatedValue(pcdacValue,
1725572ff6f6SMatthew Dillon lrPcdac, urPcdac, lPwr, uPwr, 0);
1726572ff6f6SMatthew Dillon
1727572ff6f6SMatthew Dillon return ar5211GetInterpolatedValue(channel, lFreq, rFreq,
1728572ff6f6SMatthew Dillon lScaledPwr, rScaledPwr, 0);
1729572ff6f6SMatthew Dillon }
1730572ff6f6SMatthew Dillon
1731572ff6f6SMatthew Dillon /*
1732572ff6f6SMatthew Dillon * Find the value from the calibrated source data struct
1733572ff6f6SMatthew Dillon */
1734572ff6f6SMatthew Dillon HAL_BOOL
ar5211FindValueInList(uint16_t channel,uint16_t pcdacValue,const PCDACS_EEPROM * pSrcStruct,uint16_t * powerValue)1735572ff6f6SMatthew Dillon ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue,
1736572ff6f6SMatthew Dillon const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue)
1737572ff6f6SMatthew Dillon {
1738572ff6f6SMatthew Dillon const DATA_PER_CHANNEL *pChannelData;
1739572ff6f6SMatthew Dillon const uint16_t *pPcdac;
1740572ff6f6SMatthew Dillon uint16_t i, j;
1741572ff6f6SMatthew Dillon
1742572ff6f6SMatthew Dillon pChannelData = pSrcStruct->pDataPerChannel;
1743572ff6f6SMatthew Dillon for (i = 0; i < pSrcStruct->numChannels; i++ ) {
1744572ff6f6SMatthew Dillon if (pChannelData->channelValue == channel) {
1745572ff6f6SMatthew Dillon pPcdac = pChannelData->PcdacValues;
1746572ff6f6SMatthew Dillon for (j = 0; j < pChannelData->numPcdacValues; j++ ) {
1747572ff6f6SMatthew Dillon if (*pPcdac == pcdacValue) {
1748572ff6f6SMatthew Dillon *powerValue = pChannelData->PwrValues[j];
1749572ff6f6SMatthew Dillon return AH_TRUE;
1750572ff6f6SMatthew Dillon }
1751572ff6f6SMatthew Dillon pPcdac++;
1752572ff6f6SMatthew Dillon }
1753572ff6f6SMatthew Dillon }
1754572ff6f6SMatthew Dillon pChannelData++;
1755572ff6f6SMatthew Dillon }
1756572ff6f6SMatthew Dillon return AH_FALSE;
1757572ff6f6SMatthew Dillon }
1758572ff6f6SMatthew Dillon
1759572ff6f6SMatthew Dillon /*
1760572ff6f6SMatthew Dillon * Returns interpolated or the scaled up interpolated value
1761572ff6f6SMatthew Dillon */
1762572ff6f6SMatthew Dillon uint16_t
ar5211GetInterpolatedValue(uint16_t target,uint16_t srcLeft,uint16_t srcRight,uint16_t targetLeft,uint16_t targetRight,HAL_BOOL scaleUp)1763572ff6f6SMatthew Dillon ar5211GetInterpolatedValue(uint16_t target,
1764572ff6f6SMatthew Dillon uint16_t srcLeft, uint16_t srcRight,
1765572ff6f6SMatthew Dillon uint16_t targetLeft, uint16_t targetRight,
1766572ff6f6SMatthew Dillon HAL_BOOL scaleUp)
1767572ff6f6SMatthew Dillon {
1768572ff6f6SMatthew Dillon uint16_t rv;
1769572ff6f6SMatthew Dillon int16_t lRatio;
1770572ff6f6SMatthew Dillon uint16_t scaleValue = EEP_SCALE;
1771572ff6f6SMatthew Dillon
1772572ff6f6SMatthew Dillon /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */
1773572ff6f6SMatthew Dillon if ((targetLeft * targetRight) == 0)
1774572ff6f6SMatthew Dillon return 0;
1775572ff6f6SMatthew Dillon if (scaleUp)
1776572ff6f6SMatthew Dillon scaleValue = 1;
1777572ff6f6SMatthew Dillon
1778572ff6f6SMatthew Dillon if (srcRight != srcLeft) {
1779572ff6f6SMatthew Dillon /*
1780572ff6f6SMatthew Dillon * Note the ratio always need to be scaled,
1781572ff6f6SMatthew Dillon * since it will be a fraction.
1782572ff6f6SMatthew Dillon */
1783572ff6f6SMatthew Dillon lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft);
1784572ff6f6SMatthew Dillon if (lRatio < 0) {
1785572ff6f6SMatthew Dillon /* Return as Left target if value would be negative */
1786572ff6f6SMatthew Dillon rv = targetLeft * (scaleUp ? EEP_SCALE : 1);
1787572ff6f6SMatthew Dillon } else if (lRatio > EEP_SCALE) {
1788572ff6f6SMatthew Dillon /* Return as Right target if Ratio is greater than 100% (SCALE) */
1789572ff6f6SMatthew Dillon rv = targetRight * (scaleUp ? EEP_SCALE : 1);
1790572ff6f6SMatthew Dillon } else {
1791572ff6f6SMatthew Dillon rv = (lRatio * targetRight + (EEP_SCALE - lRatio) *
1792572ff6f6SMatthew Dillon targetLeft) / scaleValue;
1793572ff6f6SMatthew Dillon }
1794572ff6f6SMatthew Dillon } else {
1795572ff6f6SMatthew Dillon rv = targetLeft;
1796572ff6f6SMatthew Dillon if (scaleUp)
1797572ff6f6SMatthew Dillon rv *= EEP_SCALE;
1798572ff6f6SMatthew Dillon }
1799572ff6f6SMatthew Dillon return rv;
1800572ff6f6SMatthew Dillon }
1801572ff6f6SMatthew Dillon
1802572ff6f6SMatthew Dillon /*
1803572ff6f6SMatthew Dillon * Look for value being within 0.1 of the search values
1804572ff6f6SMatthew Dillon * however, NDIS can't do float calculations, so multiply everything
1805572ff6f6SMatthew Dillon * up by EEP_SCALE so can do integer arithmatic
1806572ff6f6SMatthew Dillon *
1807572ff6f6SMatthew Dillon * INPUT value -value to search for
1808572ff6f6SMatthew Dillon * INPUT pList -ptr to the list to search
1809572ff6f6SMatthew Dillon * INPUT listSize -number of entries in list
1810572ff6f6SMatthew Dillon * OUTPUT pLowerValue -return the lower value
1811572ff6f6SMatthew Dillon * OUTPUT pUpperValue -return the upper value
1812572ff6f6SMatthew Dillon */
1813572ff6f6SMatthew Dillon void
ar5211GetLowerUpperValues(uint16_t value,const uint16_t * pList,uint16_t listSize,uint16_t * pLowerValue,uint16_t * pUpperValue)1814572ff6f6SMatthew Dillon ar5211GetLowerUpperValues(uint16_t value,
1815572ff6f6SMatthew Dillon const uint16_t *pList, uint16_t listSize,
1816572ff6f6SMatthew Dillon uint16_t *pLowerValue, uint16_t *pUpperValue)
1817572ff6f6SMatthew Dillon {
1818572ff6f6SMatthew Dillon const uint16_t listEndValue = *(pList + listSize - 1);
1819572ff6f6SMatthew Dillon uint32_t target = value * EEP_SCALE;
1820572ff6f6SMatthew Dillon int i;
1821572ff6f6SMatthew Dillon
182257e09377SMatthew Dillon *pLowerValue = 0; /* avoid gcc warnings */
182357e09377SMatthew Dillon *pUpperValue = 0; /* avoid gcc warnings */
182457e09377SMatthew Dillon
1825572ff6f6SMatthew Dillon /*
1826572ff6f6SMatthew Dillon * See if value is lower than the first value in the list
1827572ff6f6SMatthew Dillon * if so return first value
1828572ff6f6SMatthew Dillon */
1829572ff6f6SMatthew Dillon if (target < (uint32_t)(*pList * EEP_SCALE - EEP_DELTA)) {
1830572ff6f6SMatthew Dillon *pLowerValue = *pList;
1831572ff6f6SMatthew Dillon *pUpperValue = *pList;
1832572ff6f6SMatthew Dillon return;
1833572ff6f6SMatthew Dillon }
1834572ff6f6SMatthew Dillon
1835572ff6f6SMatthew Dillon /*
1836572ff6f6SMatthew Dillon * See if value is greater than last value in list
1837572ff6f6SMatthew Dillon * if so return last value
1838572ff6f6SMatthew Dillon */
1839572ff6f6SMatthew Dillon if (target > (uint32_t)(listEndValue * EEP_SCALE + EEP_DELTA)) {
1840572ff6f6SMatthew Dillon *pLowerValue = listEndValue;
1841572ff6f6SMatthew Dillon *pUpperValue = listEndValue;
1842572ff6f6SMatthew Dillon return;
1843572ff6f6SMatthew Dillon }
1844572ff6f6SMatthew Dillon
1845572ff6f6SMatthew Dillon /* look for value being near or between 2 values in list */
1846572ff6f6SMatthew Dillon for (i = 0; i < listSize; i++) {
1847572ff6f6SMatthew Dillon /*
1848572ff6f6SMatthew Dillon * If value is close to the current value of the list
1849572ff6f6SMatthew Dillon * then target is not between values, it is one of the values
1850572ff6f6SMatthew Dillon */
1851572ff6f6SMatthew Dillon if (abs(pList[i] * EEP_SCALE - (int32_t) target) < EEP_DELTA) {
1852572ff6f6SMatthew Dillon *pLowerValue = pList[i];
1853572ff6f6SMatthew Dillon *pUpperValue = pList[i];
1854572ff6f6SMatthew Dillon return;
1855572ff6f6SMatthew Dillon }
1856572ff6f6SMatthew Dillon
1857572ff6f6SMatthew Dillon /*
1858572ff6f6SMatthew Dillon * Look for value being between current value and next value
1859572ff6f6SMatthew Dillon * if so return these 2 values
1860572ff6f6SMatthew Dillon */
1861572ff6f6SMatthew Dillon if (target < (uint32_t)(pList[i + 1] * EEP_SCALE - EEP_DELTA)) {
1862572ff6f6SMatthew Dillon *pLowerValue = pList[i];
1863572ff6f6SMatthew Dillon *pUpperValue = pList[i + 1];
1864572ff6f6SMatthew Dillon return;
1865572ff6f6SMatthew Dillon }
1866572ff6f6SMatthew Dillon }
1867572ff6f6SMatthew Dillon }
1868572ff6f6SMatthew Dillon
1869572ff6f6SMatthew Dillon /*
1870572ff6f6SMatthew Dillon * Get the upper and lower pcdac given the channel and the pcdac
1871572ff6f6SMatthew Dillon * used in the search
1872572ff6f6SMatthew Dillon */
1873572ff6f6SMatthew Dillon void
ar5211GetLowerUpperPcdacs(uint16_t pcdac,uint16_t channel,const PCDACS_EEPROM * pSrcStruct,uint16_t * pLowerPcdac,uint16_t * pUpperPcdac)1874572ff6f6SMatthew Dillon ar5211GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
1875572ff6f6SMatthew Dillon const PCDACS_EEPROM *pSrcStruct,
1876572ff6f6SMatthew Dillon uint16_t *pLowerPcdac, uint16_t *pUpperPcdac)
1877572ff6f6SMatthew Dillon {
1878572ff6f6SMatthew Dillon const DATA_PER_CHANNEL *pChannelData;
1879572ff6f6SMatthew Dillon int i;
1880572ff6f6SMatthew Dillon
1881572ff6f6SMatthew Dillon /* Find the channel information */
1882572ff6f6SMatthew Dillon pChannelData = pSrcStruct->pDataPerChannel;
1883572ff6f6SMatthew Dillon for (i = 0; i < pSrcStruct->numChannels; i++) {
1884572ff6f6SMatthew Dillon if (pChannelData->channelValue == channel)
1885572ff6f6SMatthew Dillon break;
1886572ff6f6SMatthew Dillon pChannelData++;
1887572ff6f6SMatthew Dillon }
1888572ff6f6SMatthew Dillon ar5211GetLowerUpperValues(pcdac, pChannelData->PcdacValues,
1889572ff6f6SMatthew Dillon pChannelData->numPcdacValues, pLowerPcdac, pUpperPcdac);
1890572ff6f6SMatthew Dillon }
1891572ff6f6SMatthew Dillon
1892572ff6f6SMatthew Dillon #define DYN_ADJ_UP_MARGIN 15
1893572ff6f6SMatthew Dillon #define DYN_ADJ_LO_MARGIN 20
1894572ff6f6SMatthew Dillon
1895572ff6f6SMatthew Dillon static const GAIN_OPTIMIZATION_LADDER gainLadder = {
1896572ff6f6SMatthew Dillon 9, /* numStepsInLadder */
1897572ff6f6SMatthew Dillon 4, /* defaultStepNum */
1898572ff6f6SMatthew Dillon { { {4, 1, 1, 1}, 6, "FG8"},
1899572ff6f6SMatthew Dillon { {4, 0, 1, 1}, 4, "FG7"},
1900572ff6f6SMatthew Dillon { {3, 1, 1, 1}, 3, "FG6"},
1901572ff6f6SMatthew Dillon { {4, 0, 0, 1}, 1, "FG5"},
1902572ff6f6SMatthew Dillon { {4, 1, 1, 0}, 0, "FG4"}, /* noJack */
1903572ff6f6SMatthew Dillon { {4, 0, 1, 0}, -2, "FG3"}, /* halfJack */
1904572ff6f6SMatthew Dillon { {3, 1, 1, 0}, -3, "FG2"}, /* clip3 */
1905572ff6f6SMatthew Dillon { {4, 0, 0, 0}, -4, "FG1"}, /* noJack */
1906572ff6f6SMatthew Dillon { {2, 1, 1, 0}, -6, "FG0"} /* clip2 */
1907572ff6f6SMatthew Dillon }
1908572ff6f6SMatthew Dillon };
1909572ff6f6SMatthew Dillon
1910572ff6f6SMatthew Dillon /*
1911572ff6f6SMatthew Dillon * Initialize the gain structure to good values
1912572ff6f6SMatthew Dillon */
1913572ff6f6SMatthew Dillon void
ar5211InitializeGainValues(struct ath_hal * ah)1914572ff6f6SMatthew Dillon ar5211InitializeGainValues(struct ath_hal *ah)
1915572ff6f6SMatthew Dillon {
1916572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
1917572ff6f6SMatthew Dillon GAIN_VALUES *gv = &ahp->ah_gainValues;
1918572ff6f6SMatthew Dillon
1919572ff6f6SMatthew Dillon /* initialize gain optimization values */
1920572ff6f6SMatthew Dillon gv->currStepNum = gainLadder.defaultStepNum;
1921572ff6f6SMatthew Dillon gv->currStep = &gainLadder.optStep[gainLadder.defaultStepNum];
1922572ff6f6SMatthew Dillon gv->active = AH_TRUE;
1923572ff6f6SMatthew Dillon gv->loTrig = 20;
1924572ff6f6SMatthew Dillon gv->hiTrig = 35;
1925572ff6f6SMatthew Dillon }
1926572ff6f6SMatthew Dillon
1927572ff6f6SMatthew Dillon static HAL_BOOL
ar5211InvalidGainReadback(struct ath_hal * ah,GAIN_VALUES * gv)1928572ff6f6SMatthew Dillon ar5211InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv)
1929572ff6f6SMatthew Dillon {
1930572ff6f6SMatthew Dillon const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1931572ff6f6SMatthew Dillon uint32_t gStep, g;
1932572ff6f6SMatthew Dillon uint32_t L1, L2, L3, L4;
1933572ff6f6SMatthew Dillon
1934572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_CCK(chan)) {
1935572ff6f6SMatthew Dillon gStep = 0x18;
1936572ff6f6SMatthew Dillon L1 = 0;
1937572ff6f6SMatthew Dillon L2 = gStep + 4;
1938572ff6f6SMatthew Dillon L3 = 0x40;
1939572ff6f6SMatthew Dillon L4 = L3 + 50;
1940572ff6f6SMatthew Dillon
1941572ff6f6SMatthew Dillon gv->loTrig = L1;
1942572ff6f6SMatthew Dillon gv->hiTrig = L4+5;
1943572ff6f6SMatthew Dillon } else {
1944572ff6f6SMatthew Dillon gStep = 0x3f;
1945572ff6f6SMatthew Dillon L1 = 0;
1946572ff6f6SMatthew Dillon L2 = 50;
1947572ff6f6SMatthew Dillon L3 = L1;
1948572ff6f6SMatthew Dillon L4 = L3 + 50;
1949572ff6f6SMatthew Dillon
1950572ff6f6SMatthew Dillon gv->loTrig = L1 + DYN_ADJ_LO_MARGIN;
1951572ff6f6SMatthew Dillon gv->hiTrig = L4 - DYN_ADJ_UP_MARGIN;
1952572ff6f6SMatthew Dillon }
1953572ff6f6SMatthew Dillon g = gv->currGain;
1954572ff6f6SMatthew Dillon
1955572ff6f6SMatthew Dillon return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4));
1956572ff6f6SMatthew Dillon }
1957572ff6f6SMatthew Dillon
1958572ff6f6SMatthew Dillon /*
1959572ff6f6SMatthew Dillon * Enable the probe gain check on the next packet
1960572ff6f6SMatthew Dillon */
1961572ff6f6SMatthew Dillon static void
ar5211RequestRfgain(struct ath_hal * ah)1962572ff6f6SMatthew Dillon ar5211RequestRfgain(struct ath_hal *ah)
1963572ff6f6SMatthew Dillon {
1964572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
1965572ff6f6SMatthew Dillon
1966572ff6f6SMatthew Dillon /* Enable the gain readback probe */
1967572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE,
1968572ff6f6SMatthew Dillon SM(ahp->ah_tx6PowerInHalfDbm, AR_PHY_PAPD_PROBE_POWERTX)
1969572ff6f6SMatthew Dillon | AR_PHY_PAPD_PROBE_NEXT_TX);
1970572ff6f6SMatthew Dillon
1971572ff6f6SMatthew Dillon ahp->ah_rfgainState = HAL_RFGAIN_READ_REQUESTED;
1972572ff6f6SMatthew Dillon }
1973572ff6f6SMatthew Dillon
1974572ff6f6SMatthew Dillon /*
1975572ff6f6SMatthew Dillon * Exported call to check for a recent gain reading and return
1976572ff6f6SMatthew Dillon * the current state of the thermal calibration gain engine.
1977572ff6f6SMatthew Dillon */
1978572ff6f6SMatthew Dillon HAL_RFGAIN
ar5211GetRfgain(struct ath_hal * ah)1979572ff6f6SMatthew Dillon ar5211GetRfgain(struct ath_hal *ah)
1980572ff6f6SMatthew Dillon {
1981572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
1982572ff6f6SMatthew Dillon GAIN_VALUES *gv = &ahp->ah_gainValues;
1983572ff6f6SMatthew Dillon uint32_t rddata;
1984572ff6f6SMatthew Dillon
1985572ff6f6SMatthew Dillon if (!gv->active)
1986572ff6f6SMatthew Dillon return HAL_RFGAIN_INACTIVE;
1987572ff6f6SMatthew Dillon
1988572ff6f6SMatthew Dillon if (ahp->ah_rfgainState == HAL_RFGAIN_READ_REQUESTED) {
1989572ff6f6SMatthew Dillon /* Caller had asked to setup a new reading. Check it. */
1990572ff6f6SMatthew Dillon rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE);
1991572ff6f6SMatthew Dillon
1992572ff6f6SMatthew Dillon if ((rddata & AR_PHY_PAPD_PROBE_NEXT_TX) == 0) {
1993572ff6f6SMatthew Dillon /* bit got cleared, we have a new reading. */
1994572ff6f6SMatthew Dillon gv->currGain = rddata >> AR_PHY_PAPD_PROBE_GAINF_S;
1995572ff6f6SMatthew Dillon /* inactive by default */
1996572ff6f6SMatthew Dillon ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
1997572ff6f6SMatthew Dillon
1998572ff6f6SMatthew Dillon if (!ar5211InvalidGainReadback(ah, gv) &&
1999572ff6f6SMatthew Dillon ar5211IsGainAdjustNeeded(ah, gv) &&
2000572ff6f6SMatthew Dillon ar5211AdjustGain(ah, gv) > 0) {
2001572ff6f6SMatthew Dillon /*
2002572ff6f6SMatthew Dillon * Change needed. Copy ladder info
2003572ff6f6SMatthew Dillon * into eeprom info.
2004572ff6f6SMatthew Dillon */
2005572ff6f6SMatthew Dillon ar5211SetRfgain(ah, gv);
2006572ff6f6SMatthew Dillon ahp->ah_rfgainState = HAL_RFGAIN_NEED_CHANGE;
2007572ff6f6SMatthew Dillon }
2008572ff6f6SMatthew Dillon }
2009572ff6f6SMatthew Dillon }
2010572ff6f6SMatthew Dillon return ahp->ah_rfgainState;
2011572ff6f6SMatthew Dillon }
2012572ff6f6SMatthew Dillon
2013572ff6f6SMatthew Dillon /*
2014572ff6f6SMatthew Dillon * Check to see if our readback gain level sits within the linear
2015572ff6f6SMatthew Dillon * region of our current variable attenuation window
2016572ff6f6SMatthew Dillon */
2017572ff6f6SMatthew Dillon static HAL_BOOL
ar5211IsGainAdjustNeeded(struct ath_hal * ah,const GAIN_VALUES * gv)2018572ff6f6SMatthew Dillon ar5211IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv)
2019572ff6f6SMatthew Dillon {
2020572ff6f6SMatthew Dillon return (gv->currGain <= gv->loTrig || gv->currGain >= gv->hiTrig);
2021572ff6f6SMatthew Dillon }
2022572ff6f6SMatthew Dillon
2023572ff6f6SMatthew Dillon /*
2024572ff6f6SMatthew Dillon * Move the rabbit ears in the correct direction.
2025572ff6f6SMatthew Dillon */
2026572ff6f6SMatthew Dillon static int32_t
ar5211AdjustGain(struct ath_hal * ah,GAIN_VALUES * gv)2027572ff6f6SMatthew Dillon ar5211AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv)
2028572ff6f6SMatthew Dillon {
2029572ff6f6SMatthew Dillon /* return > 0 for valid adjustments. */
2030572ff6f6SMatthew Dillon if (!gv->active)
2031572ff6f6SMatthew Dillon return -1;
2032572ff6f6SMatthew Dillon
2033572ff6f6SMatthew Dillon gv->currStep = &gainLadder.optStep[gv->currStepNum];
2034572ff6f6SMatthew Dillon if (gv->currGain >= gv->hiTrig) {
2035572ff6f6SMatthew Dillon if (gv->currStepNum == 0) {
2036572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM,
2037572ff6f6SMatthew Dillon "%s: Max gain limit.\n", __func__);
2038572ff6f6SMatthew Dillon return -1;
2039572ff6f6SMatthew Dillon }
2040572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM,
2041572ff6f6SMatthew Dillon "%s: Adding gain: currG=%d [%s] --> ",
2042572ff6f6SMatthew Dillon __func__, gv->currGain, gv->currStep->stepName);
2043572ff6f6SMatthew Dillon gv->targetGain = gv->currGain;
2044572ff6f6SMatthew Dillon while (gv->targetGain >= gv->hiTrig && gv->currStepNum > 0) {
2045572ff6f6SMatthew Dillon gv->targetGain -= 2 * (gainLadder.optStep[--(gv->currStepNum)].stepGain -
2046572ff6f6SMatthew Dillon gv->currStep->stepGain);
2047572ff6f6SMatthew Dillon gv->currStep = &gainLadder.optStep[gv->currStepNum];
2048572ff6f6SMatthew Dillon }
2049572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
2050572ff6f6SMatthew Dillon gv->targetGain, gv->currStep->stepName);
2051572ff6f6SMatthew Dillon return 1;
2052572ff6f6SMatthew Dillon }
2053572ff6f6SMatthew Dillon if (gv->currGain <= gv->loTrig) {
2054572ff6f6SMatthew Dillon if (gv->currStepNum == gainLadder.numStepsInLadder-1) {
2055572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM,
2056572ff6f6SMatthew Dillon "%s: Min gain limit.\n", __func__);
2057572ff6f6SMatthew Dillon return -2;
2058572ff6f6SMatthew Dillon }
2059572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM,
2060572ff6f6SMatthew Dillon "%s: Deducting gain: currG=%d [%s] --> ",
2061572ff6f6SMatthew Dillon __func__, gv->currGain, gv->currStep->stepName);
2062572ff6f6SMatthew Dillon gv->targetGain = gv->currGain;
2063572ff6f6SMatthew Dillon while (gv->targetGain <= gv->loTrig &&
2064572ff6f6SMatthew Dillon gv->currStepNum < (gainLadder.numStepsInLadder - 1)) {
2065572ff6f6SMatthew Dillon gv->targetGain -= 2 *
2066572ff6f6SMatthew Dillon (gainLadder.optStep[++(gv->currStepNum)].stepGain - gv->currStep->stepGain);
2067572ff6f6SMatthew Dillon gv->currStep = &gainLadder.optStep[gv->currStepNum];
2068572ff6f6SMatthew Dillon }
2069572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
2070572ff6f6SMatthew Dillon gv->targetGain, gv->currStep->stepName);
2071572ff6f6SMatthew Dillon return 2;
2072572ff6f6SMatthew Dillon }
2073572ff6f6SMatthew Dillon return 0; /* caller didn't call needAdjGain first */
2074572ff6f6SMatthew Dillon }
2075572ff6f6SMatthew Dillon
2076572ff6f6SMatthew Dillon /*
2077572ff6f6SMatthew Dillon * Adjust the 5GHz EEPROM information with the desired calibration values.
2078572ff6f6SMatthew Dillon */
2079572ff6f6SMatthew Dillon static void
ar5211SetRfgain(struct ath_hal * ah,const GAIN_VALUES * gv)2080572ff6f6SMatthew Dillon ar5211SetRfgain(struct ath_hal *ah, const GAIN_VALUES *gv)
2081572ff6f6SMatthew Dillon {
2082572ff6f6SMatthew Dillon HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
2083572ff6f6SMatthew Dillon
2084572ff6f6SMatthew Dillon if (!gv->active)
2085572ff6f6SMatthew Dillon return;
2086572ff6f6SMatthew Dillon ee->ee_cornerCal.clip = gv->currStep->paramVal[0]; /* bb_tx_clip */
2087572ff6f6SMatthew Dillon ee->ee_cornerCal.pd90 = gv->currStep->paramVal[1]; /* rf_pwd_90 */
2088572ff6f6SMatthew Dillon ee->ee_cornerCal.pd84 = gv->currStep->paramVal[2]; /* rf_pwd_84 */
2089572ff6f6SMatthew Dillon ee->ee_cornerCal.gSel = gv->currStep->paramVal[3]; /* rf_rfgainsel */
2090572ff6f6SMatthew Dillon }
2091572ff6f6SMatthew Dillon
2092572ff6f6SMatthew Dillon static void
ar5211SetOperatingMode(struct ath_hal * ah,int opmode)2093572ff6f6SMatthew Dillon ar5211SetOperatingMode(struct ath_hal *ah, int opmode)
2094572ff6f6SMatthew Dillon {
2095572ff6f6SMatthew Dillon struct ath_hal_5211 *ahp = AH5211(ah);
2096572ff6f6SMatthew Dillon uint32_t val;
2097572ff6f6SMatthew Dillon
2098572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;
2099572ff6f6SMatthew Dillon switch (opmode) {
2100572ff6f6SMatthew Dillon case HAL_M_HOSTAP:
2101572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_STA_ID1, val
2102572ff6f6SMatthew Dillon | AR_STA_ID1_STA_AP
2103572ff6f6SMatthew Dillon | AR_STA_ID1_RTS_USE_DEF
2104572ff6f6SMatthew Dillon | ahp->ah_staId1Defaults);
2105572ff6f6SMatthew Dillon break;
2106572ff6f6SMatthew Dillon case HAL_M_IBSS:
2107572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_STA_ID1, val
2108572ff6f6SMatthew Dillon | AR_STA_ID1_ADHOC
2109572ff6f6SMatthew Dillon | AR_STA_ID1_DESC_ANTENNA
2110572ff6f6SMatthew Dillon | ahp->ah_staId1Defaults);
2111572ff6f6SMatthew Dillon break;
2112572ff6f6SMatthew Dillon case HAL_M_STA:
2113572ff6f6SMatthew Dillon case HAL_M_MONITOR:
2114572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_STA_ID1, val
2115572ff6f6SMatthew Dillon | AR_STA_ID1_DEFAULT_ANTENNA
2116572ff6f6SMatthew Dillon | ahp->ah_staId1Defaults);
2117572ff6f6SMatthew Dillon break;
2118572ff6f6SMatthew Dillon }
2119572ff6f6SMatthew Dillon }
2120572ff6f6SMatthew Dillon
2121572ff6f6SMatthew Dillon void
ar5211SetPCUConfig(struct ath_hal * ah)2122572ff6f6SMatthew Dillon ar5211SetPCUConfig(struct ath_hal *ah)
2123572ff6f6SMatthew Dillon {
2124572ff6f6SMatthew Dillon ar5211SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
2125572ff6f6SMatthew Dillon }
2126