1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon #include "opt_ah.h"
20572ff6f6SMatthew Dillon
21572ff6f6SMatthew Dillon #include "ah.h"
22572ff6f6SMatthew Dillon #include "ah_internal.h"
23572ff6f6SMatthew Dillon
24572ff6f6SMatthew Dillon #include "ar5212/ar5212.h"
25572ff6f6SMatthew Dillon #include "ar5212/ar5212reg.h"
26572ff6f6SMatthew Dillon #include "ar5212/ar5212phy.h"
27572ff6f6SMatthew Dillon
28572ff6f6SMatthew Dillon #include "ah_eeprom_v3.h"
29572ff6f6SMatthew Dillon
30572ff6f6SMatthew Dillon #define AH_5212_2316
31572ff6f6SMatthew Dillon #include "ar5212/ar5212.ini"
32572ff6f6SMatthew Dillon
33572ff6f6SMatthew Dillon #define N(a) (sizeof(a)/sizeof(a[0]))
34572ff6f6SMatthew Dillon
35572ff6f6SMatthew Dillon typedef RAW_DATA_STRUCT_2413 RAW_DATA_STRUCT_2316;
36572ff6f6SMatthew Dillon typedef RAW_DATA_PER_CHANNEL_2413 RAW_DATA_PER_CHANNEL_2316;
37572ff6f6SMatthew Dillon #define PWR_TABLE_SIZE_2316 PWR_TABLE_SIZE_2413
38572ff6f6SMatthew Dillon
39572ff6f6SMatthew Dillon struct ar2316State {
40572ff6f6SMatthew Dillon RF_HAL_FUNCS base; /* public state, must be first */
41572ff6f6SMatthew Dillon uint16_t pcdacTable[PWR_TABLE_SIZE_2316];
42572ff6f6SMatthew Dillon
43572ff6f6SMatthew Dillon uint32_t Bank1Data[N(ar5212Bank1_2316)];
44572ff6f6SMatthew Dillon uint32_t Bank2Data[N(ar5212Bank2_2316)];
45572ff6f6SMatthew Dillon uint32_t Bank3Data[N(ar5212Bank3_2316)];
46572ff6f6SMatthew Dillon uint32_t Bank6Data[N(ar5212Bank6_2316)];
47572ff6f6SMatthew Dillon uint32_t Bank7Data[N(ar5212Bank7_2316)];
48572ff6f6SMatthew Dillon
49572ff6f6SMatthew Dillon /*
50572ff6f6SMatthew Dillon * Private state for reduced stack usage.
51572ff6f6SMatthew Dillon */
52572ff6f6SMatthew Dillon /* filled out Vpd table for all pdGains (chanL) */
53572ff6f6SMatthew Dillon uint16_t vpdTable_L[MAX_NUM_PDGAINS_PER_CHANNEL]
54572ff6f6SMatthew Dillon [MAX_PWR_RANGE_IN_HALF_DB];
55572ff6f6SMatthew Dillon /* filled out Vpd table for all pdGains (chanR) */
56572ff6f6SMatthew Dillon uint16_t vpdTable_R[MAX_NUM_PDGAINS_PER_CHANNEL]
57572ff6f6SMatthew Dillon [MAX_PWR_RANGE_IN_HALF_DB];
58572ff6f6SMatthew Dillon /* filled out Vpd table for all pdGains (interpolated) */
59572ff6f6SMatthew Dillon uint16_t vpdTable_I[MAX_NUM_PDGAINS_PER_CHANNEL]
60572ff6f6SMatthew Dillon [MAX_PWR_RANGE_IN_HALF_DB];
61572ff6f6SMatthew Dillon };
62572ff6f6SMatthew Dillon #define AR2316(ah) ((struct ar2316State *) AH5212(ah)->ah_rfHal)
63572ff6f6SMatthew Dillon
64572ff6f6SMatthew Dillon extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
65572ff6f6SMatthew Dillon uint32_t numBits, uint32_t firstBit, uint32_t column);
66572ff6f6SMatthew Dillon
67572ff6f6SMatthew Dillon static void
ar2316WriteRegs(struct ath_hal * ah,u_int modesIndex,u_int freqIndex,int regWrites)68572ff6f6SMatthew Dillon ar2316WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
69572ff6f6SMatthew Dillon int regWrites)
70572ff6f6SMatthew Dillon {
71572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
72572ff6f6SMatthew Dillon
73572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2316, modesIndex, regWrites);
74572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212Common_2316, 1, regWrites);
75572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2316, freqIndex, regWrites);
76572ff6f6SMatthew Dillon
77572ff6f6SMatthew Dillon /* For AP51 */
78572ff6f6SMatthew Dillon if (!ahp->ah_cwCalRequire) {
79572ff6f6SMatthew Dillon OS_REG_WRITE(ah, 0xa358, (OS_REG_READ(ah, 0xa358) & ~0x2));
80572ff6f6SMatthew Dillon } else {
81572ff6f6SMatthew Dillon ahp->ah_cwCalRequire = AH_FALSE;
82572ff6f6SMatthew Dillon }
83572ff6f6SMatthew Dillon }
84572ff6f6SMatthew Dillon
85572ff6f6SMatthew Dillon /*
86572ff6f6SMatthew Dillon * Take the MHz channel value and set the Channel value
87572ff6f6SMatthew Dillon *
88572ff6f6SMatthew Dillon * ASSUMES: Writes enabled to analog bus
89572ff6f6SMatthew Dillon */
90572ff6f6SMatthew Dillon static HAL_BOOL
ar2316SetChannel(struct ath_hal * ah,struct ieee80211_channel * chan)91572ff6f6SMatthew Dillon ar2316SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan)
92572ff6f6SMatthew Dillon {
93572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
94572ff6f6SMatthew Dillon uint32_t channelSel = 0;
95572ff6f6SMatthew Dillon uint32_t bModeSynth = 0;
96572ff6f6SMatthew Dillon uint32_t aModeRefSel = 0;
97572ff6f6SMatthew Dillon uint32_t reg32 = 0;
98572ff6f6SMatthew Dillon
99572ff6f6SMatthew Dillon OS_MARK(ah, AH_MARK_SETCHANNEL, freq);
100572ff6f6SMatthew Dillon
101572ff6f6SMatthew Dillon if (freq < 4800) {
102572ff6f6SMatthew Dillon uint32_t txctl;
103572ff6f6SMatthew Dillon
104572ff6f6SMatthew Dillon if (((freq - 2192) % 5) == 0) {
105572ff6f6SMatthew Dillon channelSel = ((freq - 672) * 2 - 3040)/10;
106572ff6f6SMatthew Dillon bModeSynth = 0;
107572ff6f6SMatthew Dillon } else if (((freq - 2224) % 5) == 0) {
108572ff6f6SMatthew Dillon channelSel = ((freq - 704) * 2 - 3040) / 10;
109572ff6f6SMatthew Dillon bModeSynth = 1;
110572ff6f6SMatthew Dillon } else {
111572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
112572ff6f6SMatthew Dillon "%s: invalid channel %u MHz\n",
113572ff6f6SMatthew Dillon __func__, freq);
114572ff6f6SMatthew Dillon return AH_FALSE;
115572ff6f6SMatthew Dillon }
116572ff6f6SMatthew Dillon
117572ff6f6SMatthew Dillon channelSel = (channelSel << 2) & 0xff;
118572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(channelSel, 8);
119572ff6f6SMatthew Dillon
120572ff6f6SMatthew Dillon txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
121572ff6f6SMatthew Dillon if (freq == 2484) {
122572ff6f6SMatthew Dillon /* Enable channel spreading for channel 14 */
123572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
124572ff6f6SMatthew Dillon txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
125572ff6f6SMatthew Dillon } else {
126572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
127572ff6f6SMatthew Dillon txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
128572ff6f6SMatthew Dillon }
129572ff6f6SMatthew Dillon } else if ((freq % 20) == 0 && freq >= 5120) {
130572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
131572ff6f6SMatthew Dillon ((freq - 4800) / 20 << 2), 8);
132572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(3, 2);
133572ff6f6SMatthew Dillon } else if ((freq % 10) == 0) {
134572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
135572ff6f6SMatthew Dillon ((freq - 4800) / 10 << 1), 8);
136572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(2, 2);
137572ff6f6SMatthew Dillon } else if ((freq % 5) == 0) {
138572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
139572ff6f6SMatthew Dillon (freq - 4800) / 5, 8);
140572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(1, 2);
141572ff6f6SMatthew Dillon } else {
142572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
143572ff6f6SMatthew Dillon __func__, freq);
144572ff6f6SMatthew Dillon return AH_FALSE;
145572ff6f6SMatthew Dillon }
146572ff6f6SMatthew Dillon
147572ff6f6SMatthew Dillon reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
148572ff6f6SMatthew Dillon (1 << 12) | 0x1;
149572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
150572ff6f6SMatthew Dillon
151572ff6f6SMatthew Dillon reg32 >>= 8;
152572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
153572ff6f6SMatthew Dillon
154572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_curchan = chan;
155572ff6f6SMatthew Dillon return AH_TRUE;
156572ff6f6SMatthew Dillon }
157572ff6f6SMatthew Dillon
158572ff6f6SMatthew Dillon /*
159572ff6f6SMatthew Dillon * Reads EEPROM header info from device structure and programs
160572ff6f6SMatthew Dillon * all rf registers
161572ff6f6SMatthew Dillon *
162572ff6f6SMatthew Dillon * REQUIRES: Access to the analog rf device
163572ff6f6SMatthew Dillon */
164572ff6f6SMatthew Dillon static HAL_BOOL
ar2316SetRfRegs(struct ath_hal * ah,const struct ieee80211_channel * chan,uint16_t modesIndex,uint16_t * rfXpdGain)165572ff6f6SMatthew Dillon ar2316SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
166572ff6f6SMatthew Dillon uint16_t modesIndex, uint16_t *rfXpdGain)
167572ff6f6SMatthew Dillon {
168572ff6f6SMatthew Dillon #define RF_BANK_SETUP(_priv, _ix, _col) do { \
169572ff6f6SMatthew Dillon int i; \
170572ff6f6SMatthew Dillon for (i = 0; i < N(ar5212Bank##_ix##_2316); i++) \
171572ff6f6SMatthew Dillon (_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2316[i][_col];\
172572ff6f6SMatthew Dillon } while (0)
173572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
174572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
175572ff6f6SMatthew Dillon uint16_t ob2GHz = 0, db2GHz = 0;
176572ff6f6SMatthew Dillon struct ar2316State *priv = AR2316(ah);
177572ff6f6SMatthew Dillon int regWrites = 0;
178572ff6f6SMatthew Dillon
179572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
180572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags, modesIndex);
181572ff6f6SMatthew Dillon
182572ff6f6SMatthew Dillon HALASSERT(priv != AH_NULL);
183572ff6f6SMatthew Dillon
184572ff6f6SMatthew Dillon /* Setup rf parameters */
185572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_B(chan)) {
186572ff6f6SMatthew Dillon ob2GHz = ee->ee_obFor24;
187572ff6f6SMatthew Dillon db2GHz = ee->ee_dbFor24;
188572ff6f6SMatthew Dillon } else {
189572ff6f6SMatthew Dillon ob2GHz = ee->ee_obFor24g;
190572ff6f6SMatthew Dillon db2GHz = ee->ee_dbFor24g;
191572ff6f6SMatthew Dillon }
192572ff6f6SMatthew Dillon
193572ff6f6SMatthew Dillon /* Bank 1 Write */
194572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 1, 1);
195572ff6f6SMatthew Dillon
196572ff6f6SMatthew Dillon /* Bank 2 Write */
197572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 2, modesIndex);
198572ff6f6SMatthew Dillon
199572ff6f6SMatthew Dillon /* Bank 3 Write */
200572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 3, modesIndex);
201572ff6f6SMatthew Dillon
202572ff6f6SMatthew Dillon /* Bank 6 Write */
203572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 6, modesIndex);
204572ff6f6SMatthew Dillon
205572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 178, 0);
206572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 175, 0);
207572ff6f6SMatthew Dillon
208572ff6f6SMatthew Dillon /* Bank 7 Setup */
209572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 7, modesIndex);
210572ff6f6SMatthew Dillon
211572ff6f6SMatthew Dillon /* Write Analog registers */
212572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank1_2316, priv->Bank1Data, regWrites);
213572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank2_2316, priv->Bank2Data, regWrites);
214572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank3_2316, priv->Bank3Data, regWrites);
215572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank6_2316, priv->Bank6Data, regWrites);
216572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank7_2316, priv->Bank7Data, regWrites);
217572ff6f6SMatthew Dillon
218572ff6f6SMatthew Dillon /* Now that we have reprogrammed rfgain value, clear the flag. */
219572ff6f6SMatthew Dillon ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
220572ff6f6SMatthew Dillon
221572ff6f6SMatthew Dillon return AH_TRUE;
222572ff6f6SMatthew Dillon #undef RF_BANK_SETUP
223572ff6f6SMatthew Dillon }
224572ff6f6SMatthew Dillon
225572ff6f6SMatthew Dillon /*
226572ff6f6SMatthew Dillon * Return a reference to the requested RF Bank.
227572ff6f6SMatthew Dillon */
228572ff6f6SMatthew Dillon static uint32_t *
ar2316GetRfBank(struct ath_hal * ah,int bank)229572ff6f6SMatthew Dillon ar2316GetRfBank(struct ath_hal *ah, int bank)
230572ff6f6SMatthew Dillon {
231572ff6f6SMatthew Dillon struct ar2316State *priv = AR2316(ah);
232572ff6f6SMatthew Dillon
233572ff6f6SMatthew Dillon HALASSERT(priv != AH_NULL);
234572ff6f6SMatthew Dillon switch (bank) {
235572ff6f6SMatthew Dillon case 1: return priv->Bank1Data;
236572ff6f6SMatthew Dillon case 2: return priv->Bank2Data;
237572ff6f6SMatthew Dillon case 3: return priv->Bank3Data;
238572ff6f6SMatthew Dillon case 6: return priv->Bank6Data;
239572ff6f6SMatthew Dillon case 7: return priv->Bank7Data;
240572ff6f6SMatthew Dillon }
241572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
242572ff6f6SMatthew Dillon __func__, bank);
243572ff6f6SMatthew Dillon return AH_NULL;
244572ff6f6SMatthew Dillon }
245572ff6f6SMatthew Dillon
246572ff6f6SMatthew Dillon /*
247572ff6f6SMatthew Dillon * Return indices surrounding the value in sorted integer lists.
248572ff6f6SMatthew Dillon *
249572ff6f6SMatthew Dillon * NB: the input list is assumed to be sorted in ascending order
250572ff6f6SMatthew Dillon */
251572ff6f6SMatthew Dillon static void
GetLowerUpperIndex(int16_t v,const uint16_t * lp,uint16_t listSize,uint32_t * vlo,uint32_t * vhi)252572ff6f6SMatthew Dillon GetLowerUpperIndex(int16_t v, const uint16_t *lp, uint16_t listSize,
253572ff6f6SMatthew Dillon uint32_t *vlo, uint32_t *vhi)
254572ff6f6SMatthew Dillon {
255572ff6f6SMatthew Dillon int16_t target = v;
256572ff6f6SMatthew Dillon const int16_t *ep = lp+listSize;
257572ff6f6SMatthew Dillon const int16_t *tp;
258572ff6f6SMatthew Dillon
259572ff6f6SMatthew Dillon /*
260572ff6f6SMatthew Dillon * Check first and last elements for out-of-bounds conditions.
261572ff6f6SMatthew Dillon */
262572ff6f6SMatthew Dillon if (target < lp[0]) {
263572ff6f6SMatthew Dillon *vlo = *vhi = 0;
264572ff6f6SMatthew Dillon return;
265572ff6f6SMatthew Dillon }
266572ff6f6SMatthew Dillon if (target >= ep[-1]) {
267572ff6f6SMatthew Dillon *vlo = *vhi = listSize - 1;
268572ff6f6SMatthew Dillon return;
269572ff6f6SMatthew Dillon }
270572ff6f6SMatthew Dillon
271572ff6f6SMatthew Dillon /* look for value being near or between 2 values in list */
272572ff6f6SMatthew Dillon for (tp = lp; tp < ep; tp++) {
273572ff6f6SMatthew Dillon /*
274572ff6f6SMatthew Dillon * If value is close to the current value of the list
275572ff6f6SMatthew Dillon * then target is not between values, it is one of the values
276572ff6f6SMatthew Dillon */
277572ff6f6SMatthew Dillon if (*tp == target) {
278572ff6f6SMatthew Dillon *vlo = *vhi = tp - (const int16_t *) lp;
279572ff6f6SMatthew Dillon return;
280572ff6f6SMatthew Dillon }
281572ff6f6SMatthew Dillon /*
282572ff6f6SMatthew Dillon * Look for value being between current value and next value
283572ff6f6SMatthew Dillon * if so return these 2 values
284572ff6f6SMatthew Dillon */
285572ff6f6SMatthew Dillon if (target < tp[1]) {
286572ff6f6SMatthew Dillon *vlo = tp - (const int16_t *) lp;
287572ff6f6SMatthew Dillon *vhi = *vlo + 1;
288572ff6f6SMatthew Dillon return;
289572ff6f6SMatthew Dillon }
290572ff6f6SMatthew Dillon }
291572ff6f6SMatthew Dillon }
292572ff6f6SMatthew Dillon
293572ff6f6SMatthew Dillon /*
294572ff6f6SMatthew Dillon * Fill the Vpdlist for indices Pmax-Pmin
295572ff6f6SMatthew Dillon */
296572ff6f6SMatthew Dillon static HAL_BOOL
ar2316FillVpdTable(uint32_t pdGainIdx,int16_t Pmin,int16_t Pmax,const int16_t * pwrList,const int16_t * VpdList,uint16_t numIntercepts,uint16_t retVpdList[][64])297572ff6f6SMatthew Dillon ar2316FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t Pmax,
298572ff6f6SMatthew Dillon const int16_t *pwrList, const int16_t *VpdList,
299572ff6f6SMatthew Dillon uint16_t numIntercepts, uint16_t retVpdList[][64])
300572ff6f6SMatthew Dillon {
301572ff6f6SMatthew Dillon uint16_t ii, jj, kk;
302572ff6f6SMatthew Dillon int16_t currPwr = (int16_t)(2*Pmin);
303572ff6f6SMatthew Dillon /* since Pmin is pwr*2 and pwrList is 4*pwr */
304572ff6f6SMatthew Dillon uint32_t idxL, idxR;
305572ff6f6SMatthew Dillon
306572ff6f6SMatthew Dillon ii = 0;
307572ff6f6SMatthew Dillon jj = 0;
308572ff6f6SMatthew Dillon
309572ff6f6SMatthew Dillon if (numIntercepts < 2)
310572ff6f6SMatthew Dillon return AH_FALSE;
311572ff6f6SMatthew Dillon
312572ff6f6SMatthew Dillon while (ii <= (uint16_t)(Pmax - Pmin)) {
313572ff6f6SMatthew Dillon GetLowerUpperIndex(currPwr, pwrList, numIntercepts,
314572ff6f6SMatthew Dillon &(idxL), &(idxR));
315572ff6f6SMatthew Dillon if (idxR < 1)
316572ff6f6SMatthew Dillon idxR = 1; /* extrapolate below */
317572ff6f6SMatthew Dillon if (idxL == (uint32_t)(numIntercepts - 1))
318572ff6f6SMatthew Dillon idxL = numIntercepts - 2; /* extrapolate above */
319572ff6f6SMatthew Dillon if (pwrList[idxL] == pwrList[idxR])
320572ff6f6SMatthew Dillon kk = VpdList[idxL];
321572ff6f6SMatthew Dillon else
322572ff6f6SMatthew Dillon kk = (uint16_t)
323572ff6f6SMatthew Dillon (((currPwr - pwrList[idxL])*VpdList[idxR]+
324572ff6f6SMatthew Dillon (pwrList[idxR] - currPwr)*VpdList[idxL])/
325572ff6f6SMatthew Dillon (pwrList[idxR] - pwrList[idxL]));
326572ff6f6SMatthew Dillon retVpdList[pdGainIdx][ii] = kk;
327572ff6f6SMatthew Dillon ii++;
328572ff6f6SMatthew Dillon currPwr += 2; /* half dB steps */
329572ff6f6SMatthew Dillon }
330572ff6f6SMatthew Dillon
331572ff6f6SMatthew Dillon return AH_TRUE;
332572ff6f6SMatthew Dillon }
333572ff6f6SMatthew Dillon
334572ff6f6SMatthew Dillon /*
335572ff6f6SMatthew Dillon * Returns interpolated or the scaled up interpolated value
336572ff6f6SMatthew Dillon */
337572ff6f6SMatthew Dillon static int16_t
interpolate_signed(uint16_t target,uint16_t srcLeft,uint16_t srcRight,int16_t targetLeft,int16_t targetRight)338572ff6f6SMatthew Dillon interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
339572ff6f6SMatthew Dillon int16_t targetLeft, int16_t targetRight)
340572ff6f6SMatthew Dillon {
341572ff6f6SMatthew Dillon int16_t rv;
342572ff6f6SMatthew Dillon
343572ff6f6SMatthew Dillon if (srcRight != srcLeft) {
344572ff6f6SMatthew Dillon rv = ((target - srcLeft)*targetRight +
345572ff6f6SMatthew Dillon (srcRight - target)*targetLeft) / (srcRight - srcLeft);
346572ff6f6SMatthew Dillon } else {
347572ff6f6SMatthew Dillon rv = targetLeft;
348572ff6f6SMatthew Dillon }
349572ff6f6SMatthew Dillon return rv;
350572ff6f6SMatthew Dillon }
351572ff6f6SMatthew Dillon
352572ff6f6SMatthew Dillon /*
353572ff6f6SMatthew Dillon * Uses the data points read from EEPROM to reconstruct the pdadc power table
354572ff6f6SMatthew Dillon * Called by ar2316SetPowerTable()
355572ff6f6SMatthew Dillon */
356572ff6f6SMatthew Dillon static int
ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal * ah,uint16_t channel,const RAW_DATA_STRUCT_2316 * pRawDataset,uint16_t pdGainOverlap_t2,int16_t * pMinCalPower,uint16_t pPdGainBoundaries[],uint16_t pPdGainValues[],uint16_t pPDADCValues[])357572ff6f6SMatthew Dillon ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
358572ff6f6SMatthew Dillon const RAW_DATA_STRUCT_2316 *pRawDataset,
359572ff6f6SMatthew Dillon uint16_t pdGainOverlap_t2,
360572ff6f6SMatthew Dillon int16_t *pMinCalPower, uint16_t pPdGainBoundaries[],
361572ff6f6SMatthew Dillon uint16_t pPdGainValues[], uint16_t pPDADCValues[])
362572ff6f6SMatthew Dillon {
363572ff6f6SMatthew Dillon struct ar2316State *priv = AR2316(ah);
364572ff6f6SMatthew Dillon #define VpdTable_L priv->vpdTable_L
365572ff6f6SMatthew Dillon #define VpdTable_R priv->vpdTable_R
366572ff6f6SMatthew Dillon #define VpdTable_I priv->vpdTable_I
367572ff6f6SMatthew Dillon uint32_t ii, jj, kk;
368572ff6f6SMatthew Dillon int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
369572ff6f6SMatthew Dillon uint32_t idxL, idxR;
370572ff6f6SMatthew Dillon uint32_t numPdGainsUsed = 0;
371572ff6f6SMatthew Dillon /*
372572ff6f6SMatthew Dillon * If desired to support -ve power levels in future, just
373572ff6f6SMatthew Dillon * change pwr_I_0 to signed 5-bits.
374572ff6f6SMatthew Dillon */
375572ff6f6SMatthew Dillon int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
376*b14ca477SMatthew Dillon /* to accommodate -ve power levels later on. */
377572ff6f6SMatthew Dillon int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
378*b14ca477SMatthew Dillon /* to accommodate -ve power levels later on */
379572ff6f6SMatthew Dillon uint16_t numVpd = 0;
380572ff6f6SMatthew Dillon uint16_t Vpd_step;
381572ff6f6SMatthew Dillon int16_t tmpVal ;
382572ff6f6SMatthew Dillon uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;
383572ff6f6SMatthew Dillon
384572ff6f6SMatthew Dillon /* Get upper lower index */
385572ff6f6SMatthew Dillon GetLowerUpperIndex(channel, pRawDataset->pChannels,
386572ff6f6SMatthew Dillon pRawDataset->numChannels, &(idxL), &(idxR));
387572ff6f6SMatthew Dillon
388572ff6f6SMatthew Dillon for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
389572ff6f6SMatthew Dillon jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
390572ff6f6SMatthew Dillon /* work backwards 'cause highest pdGain for lowest power */
391572ff6f6SMatthew Dillon numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;
392572ff6f6SMatthew Dillon if (numVpd > 0) {
393572ff6f6SMatthew Dillon pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;
394572ff6f6SMatthew Dillon Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];
395572ff6f6SMatthew Dillon if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {
396572ff6f6SMatthew Dillon Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];
397572ff6f6SMatthew Dillon }
398572ff6f6SMatthew Dillon Pmin_t2[numPdGainsUsed] = (int16_t)
399572ff6f6SMatthew Dillon (Pmin_t2[numPdGainsUsed] / 2);
400572ff6f6SMatthew Dillon Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];
401572ff6f6SMatthew Dillon if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])
402572ff6f6SMatthew Dillon Pmax_t2[numPdGainsUsed] =
403572ff6f6SMatthew Dillon pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];
404572ff6f6SMatthew Dillon Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);
405572ff6f6SMatthew Dillon ar2316FillVpdTable(
406572ff6f6SMatthew Dillon numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed],
407572ff6f6SMatthew Dillon &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]),
408572ff6f6SMatthew Dillon &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L
409572ff6f6SMatthew Dillon );
410572ff6f6SMatthew Dillon ar2316FillVpdTable(
411572ff6f6SMatthew Dillon numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed],
412572ff6f6SMatthew Dillon &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),
413572ff6f6SMatthew Dillon &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R
414572ff6f6SMatthew Dillon );
415572ff6f6SMatthew Dillon for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {
416572ff6f6SMatthew Dillon VpdTable_I[numPdGainsUsed][kk] =
417572ff6f6SMatthew Dillon interpolate_signed(
418572ff6f6SMatthew Dillon channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],
419572ff6f6SMatthew Dillon (int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);
420572ff6f6SMatthew Dillon }
421572ff6f6SMatthew Dillon /* fill VpdTable_I for this pdGain */
422572ff6f6SMatthew Dillon numPdGainsUsed++;
423572ff6f6SMatthew Dillon }
424572ff6f6SMatthew Dillon /* if this pdGain is used */
425572ff6f6SMatthew Dillon }
426572ff6f6SMatthew Dillon
427572ff6f6SMatthew Dillon *pMinCalPower = Pmin_t2[0];
428572ff6f6SMatthew Dillon kk = 0; /* index for the final table */
429572ff6f6SMatthew Dillon for (ii = 0; ii < numPdGainsUsed; ii++) {
430572ff6f6SMatthew Dillon if (ii == (numPdGainsUsed - 1))
431572ff6f6SMatthew Dillon pPdGainBoundaries[ii] = Pmax_t2[ii] +
432572ff6f6SMatthew Dillon PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;
433572ff6f6SMatthew Dillon else
434572ff6f6SMatthew Dillon pPdGainBoundaries[ii] = (uint16_t)
435572ff6f6SMatthew Dillon ((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );
436572ff6f6SMatthew Dillon if (pPdGainBoundaries[ii] > 63) {
437572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
438572ff6f6SMatthew Dillon "%s: clamp pPdGainBoundaries[%d] %d\n",
439572ff6f6SMatthew Dillon __func__, ii, pPdGainBoundaries[ii]);/*XXX*/
440572ff6f6SMatthew Dillon pPdGainBoundaries[ii] = 63;
441572ff6f6SMatthew Dillon }
442572ff6f6SMatthew Dillon
443572ff6f6SMatthew Dillon /* Find starting index for this pdGain */
444572ff6f6SMatthew Dillon if (ii == 0)
445572ff6f6SMatthew Dillon ss = 0; /* for the first pdGain, start from index 0 */
446572ff6f6SMatthew Dillon else
447572ff6f6SMatthew Dillon ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) -
448572ff6f6SMatthew Dillon pdGainOverlap_t2;
449572ff6f6SMatthew Dillon Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);
450572ff6f6SMatthew Dillon Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
451572ff6f6SMatthew Dillon /*
452572ff6f6SMatthew Dillon *-ve ss indicates need to extrapolate data below for this pdGain
453572ff6f6SMatthew Dillon */
454572ff6f6SMatthew Dillon while (ss < 0) {
455572ff6f6SMatthew Dillon tmpVal = (int16_t)(VpdTable_I[ii][0] + ss*Vpd_step);
456572ff6f6SMatthew Dillon pPDADCValues[kk++] = (uint16_t)((tmpVal < 0) ? 0 : tmpVal);
457572ff6f6SMatthew Dillon ss++;
458572ff6f6SMatthew Dillon }
459572ff6f6SMatthew Dillon
460572ff6f6SMatthew Dillon sizeCurrVpdTable = Pmax_t2[ii] - Pmin_t2[ii];
461572ff6f6SMatthew Dillon tgtIndex = pPdGainBoundaries[ii] + pdGainOverlap_t2 - Pmin_t2[ii];
462572ff6f6SMatthew Dillon maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
463572ff6f6SMatthew Dillon
464572ff6f6SMatthew Dillon while (ss < (int16_t)maxIndex)
465572ff6f6SMatthew Dillon pPDADCValues[kk++] = VpdTable_I[ii][ss++];
466572ff6f6SMatthew Dillon
467572ff6f6SMatthew Dillon Vpd_step = (uint16_t)(VpdTable_I[ii][sizeCurrVpdTable-1] -
468572ff6f6SMatthew Dillon VpdTable_I[ii][sizeCurrVpdTable-2]);
469572ff6f6SMatthew Dillon Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
470572ff6f6SMatthew Dillon /*
471572ff6f6SMatthew Dillon * for last gain, pdGainBoundary == Pmax_t2, so will
472572ff6f6SMatthew Dillon * have to extrapolate
473572ff6f6SMatthew Dillon */
474572ff6f6SMatthew Dillon if (tgtIndex > maxIndex) { /* need to extrapolate above */
475572ff6f6SMatthew Dillon while(ss < (int16_t)tgtIndex) {
476572ff6f6SMatthew Dillon tmpVal = (uint16_t)
477572ff6f6SMatthew Dillon (VpdTable_I[ii][sizeCurrVpdTable-1] +
478572ff6f6SMatthew Dillon (ss-maxIndex)*Vpd_step);
479572ff6f6SMatthew Dillon pPDADCValues[kk++] = (tmpVal > 127) ?
480572ff6f6SMatthew Dillon 127 : tmpVal;
481572ff6f6SMatthew Dillon ss++;
482572ff6f6SMatthew Dillon }
483572ff6f6SMatthew Dillon } /* extrapolated above */
484572ff6f6SMatthew Dillon } /* for all pdGainUsed */
485572ff6f6SMatthew Dillon
486572ff6f6SMatthew Dillon while (ii < MAX_NUM_PDGAINS_PER_CHANNEL) {
487572ff6f6SMatthew Dillon pPdGainBoundaries[ii] = pPdGainBoundaries[ii-1];
488572ff6f6SMatthew Dillon ii++;
489572ff6f6SMatthew Dillon }
490572ff6f6SMatthew Dillon while (kk < 128) {
491572ff6f6SMatthew Dillon pPDADCValues[kk] = pPDADCValues[kk-1];
492572ff6f6SMatthew Dillon kk++;
493572ff6f6SMatthew Dillon }
494572ff6f6SMatthew Dillon
495572ff6f6SMatthew Dillon return numPdGainsUsed;
496572ff6f6SMatthew Dillon #undef VpdTable_L
497572ff6f6SMatthew Dillon #undef VpdTable_R
498572ff6f6SMatthew Dillon #undef VpdTable_I
499572ff6f6SMatthew Dillon }
500572ff6f6SMatthew Dillon
501572ff6f6SMatthew Dillon static HAL_BOOL
ar2316SetPowerTable(struct ath_hal * ah,int16_t * minPower,int16_t * maxPower,const struct ieee80211_channel * chan,uint16_t * rfXpdGain)502572ff6f6SMatthew Dillon ar2316SetPowerTable(struct ath_hal *ah,
503572ff6f6SMatthew Dillon int16_t *minPower, int16_t *maxPower,
504572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
505572ff6f6SMatthew Dillon uint16_t *rfXpdGain)
506572ff6f6SMatthew Dillon {
507572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
508572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
509572ff6f6SMatthew Dillon const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL;
510572ff6f6SMatthew Dillon uint16_t pdGainOverlap_t2;
511572ff6f6SMatthew Dillon int16_t minCalPower2316_t2;
512572ff6f6SMatthew Dillon uint16_t *pdadcValues = ahp->ah_pcdacTable;
513572ff6f6SMatthew Dillon uint16_t gainBoundaries[4];
514572ff6f6SMatthew Dillon uint32_t reg32, regoffset;
515572ff6f6SMatthew Dillon int i, numPdGainsUsed;
516572ff6f6SMatthew Dillon #ifndef AH_USE_INIPDGAIN
517572ff6f6SMatthew Dillon uint32_t tpcrg1;
518572ff6f6SMatthew Dillon #endif
519572ff6f6SMatthew Dillon
520572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
521572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags);
522572ff6f6SMatthew Dillon
523572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
524572ff6f6SMatthew Dillon pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
525572ff6f6SMatthew Dillon else if (IEEE80211_IS_CHAN_B(chan))
526572ff6f6SMatthew Dillon pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
527572ff6f6SMatthew Dillon else {
528572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
529572ff6f6SMatthew Dillon return AH_FALSE;
530572ff6f6SMatthew Dillon }
531572ff6f6SMatthew Dillon
532572ff6f6SMatthew Dillon pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
533572ff6f6SMatthew Dillon AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
534572ff6f6SMatthew Dillon
535572ff6f6SMatthew Dillon numPdGainsUsed = ar2316getGainBoundariesAndPdadcsForPowers(ah,
536572ff6f6SMatthew Dillon chan->channel, pRawDataset, pdGainOverlap_t2,
537572ff6f6SMatthew Dillon &minCalPower2316_t2,gainBoundaries, rfXpdGain, pdadcValues);
538572ff6f6SMatthew Dillon HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
539572ff6f6SMatthew Dillon
540572ff6f6SMatthew Dillon #ifdef AH_USE_INIPDGAIN
541572ff6f6SMatthew Dillon /*
542572ff6f6SMatthew Dillon * Use pd_gains curve from eeprom; Atheros always uses
543572ff6f6SMatthew Dillon * the default curve from the ini file but some vendors
544572ff6f6SMatthew Dillon * (e.g. Zcomax) want to override this curve and not
545572ff6f6SMatthew Dillon * honoring their settings results in tx power 5dBm low.
546572ff6f6SMatthew Dillon */
547572ff6f6SMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
548572ff6f6SMatthew Dillon (pRawDataset->pDataPerChannel[0].numPdGains - 1));
549572ff6f6SMatthew Dillon #else
550572ff6f6SMatthew Dillon tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);
551572ff6f6SMatthew Dillon tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)
552572ff6f6SMatthew Dillon | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
553572ff6f6SMatthew Dillon switch (numPdGainsUsed) {
554572ff6f6SMatthew Dillon case 3:
555572ff6f6SMatthew Dillon tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;
556572ff6f6SMatthew Dillon tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
557572ff6f6SMatthew Dillon /* fall thru... */
558572ff6f6SMatthew Dillon case 2:
559572ff6f6SMatthew Dillon tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;
560572ff6f6SMatthew Dillon tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
561572ff6f6SMatthew Dillon /* fall thru... */
562572ff6f6SMatthew Dillon case 1:
563572ff6f6SMatthew Dillon tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;
564572ff6f6SMatthew Dillon tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
565572ff6f6SMatthew Dillon break;
566572ff6f6SMatthew Dillon }
567572ff6f6SMatthew Dillon #ifdef AH_DEBUG
568572ff6f6SMatthew Dillon if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))
569572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "
570572ff6f6SMatthew Dillon "pd_gains (default 0x%x, calculated 0x%x)\n",
571572ff6f6SMatthew Dillon __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);
572572ff6f6SMatthew Dillon #endif
573572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);
574572ff6f6SMatthew Dillon #endif
575572ff6f6SMatthew Dillon
576572ff6f6SMatthew Dillon /*
577572ff6f6SMatthew Dillon * Note the pdadc table may not start at 0 dBm power, could be
578572ff6f6SMatthew Dillon * negative or greater than 0. Need to offset the power
579572ff6f6SMatthew Dillon * values by the amount of minPower for griffin
580572ff6f6SMatthew Dillon */
581572ff6f6SMatthew Dillon if (minCalPower2316_t2 != 0)
582572ff6f6SMatthew Dillon ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2316_t2);
583572ff6f6SMatthew Dillon else
584572ff6f6SMatthew Dillon ahp->ah_txPowerIndexOffset = 0;
585572ff6f6SMatthew Dillon
586572ff6f6SMatthew Dillon /* Finally, write the power values into the baseband power table */
587572ff6f6SMatthew Dillon regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
588572ff6f6SMatthew Dillon for (i = 0; i < 32; i++) {
589572ff6f6SMatthew Dillon reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) |
590572ff6f6SMatthew Dillon ((pdadcValues[4*i + 1] & 0xFF) << 8) |
591572ff6f6SMatthew Dillon ((pdadcValues[4*i + 2] & 0xFF) << 16) |
592572ff6f6SMatthew Dillon ((pdadcValues[4*i + 3] & 0xFF) << 24) ;
593572ff6f6SMatthew Dillon OS_REG_WRITE(ah, regoffset, reg32);
594572ff6f6SMatthew Dillon regoffset += 4;
595572ff6f6SMatthew Dillon }
596572ff6f6SMatthew Dillon
597572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TPCRG5,
598572ff6f6SMatthew Dillon SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
599572ff6f6SMatthew Dillon SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
600572ff6f6SMatthew Dillon SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
601572ff6f6SMatthew Dillon SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
602572ff6f6SMatthew Dillon SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
603572ff6f6SMatthew Dillon
604572ff6f6SMatthew Dillon return AH_TRUE;
605572ff6f6SMatthew Dillon }
606572ff6f6SMatthew Dillon
607572ff6f6SMatthew Dillon static int16_t
ar2316GetMinPower(struct ath_hal * ah,const RAW_DATA_PER_CHANNEL_2316 * data)608572ff6f6SMatthew Dillon ar2316GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2316 *data)
609572ff6f6SMatthew Dillon {
610572ff6f6SMatthew Dillon uint32_t ii,jj;
611572ff6f6SMatthew Dillon uint16_t Pmin=0,numVpd;
612572ff6f6SMatthew Dillon
613572ff6f6SMatthew Dillon for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
614572ff6f6SMatthew Dillon jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
615572ff6f6SMatthew Dillon /* work backwards 'cause highest pdGain for lowest power */
616572ff6f6SMatthew Dillon numVpd = data->pDataPerPDGain[jj].numVpd;
617572ff6f6SMatthew Dillon if (numVpd > 0) {
618572ff6f6SMatthew Dillon Pmin = data->pDataPerPDGain[jj].pwr_t4[0];
619572ff6f6SMatthew Dillon return(Pmin);
620572ff6f6SMatthew Dillon }
621572ff6f6SMatthew Dillon }
622572ff6f6SMatthew Dillon return(Pmin);
623572ff6f6SMatthew Dillon }
624572ff6f6SMatthew Dillon
625572ff6f6SMatthew Dillon static int16_t
ar2316GetMaxPower(struct ath_hal * ah,const RAW_DATA_PER_CHANNEL_2316 * data)626572ff6f6SMatthew Dillon ar2316GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2316 *data)
627572ff6f6SMatthew Dillon {
628572ff6f6SMatthew Dillon uint32_t ii;
629572ff6f6SMatthew Dillon uint16_t Pmax=0,numVpd;
630572ff6f6SMatthew Dillon
631572ff6f6SMatthew Dillon for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
632572ff6f6SMatthew Dillon /* work forwards cuase lowest pdGain for highest power */
633572ff6f6SMatthew Dillon numVpd = data->pDataPerPDGain[ii].numVpd;
634572ff6f6SMatthew Dillon if (numVpd > 0) {
635572ff6f6SMatthew Dillon Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
636572ff6f6SMatthew Dillon return(Pmax);
637572ff6f6SMatthew Dillon }
638572ff6f6SMatthew Dillon }
639572ff6f6SMatthew Dillon return(Pmax);
640572ff6f6SMatthew Dillon }
641572ff6f6SMatthew Dillon
642572ff6f6SMatthew Dillon static HAL_BOOL
ar2316GetChannelMaxMinPower(struct ath_hal * ah,const struct ieee80211_channel * chan,int16_t * maxPow,int16_t * minPow)643572ff6f6SMatthew Dillon ar2316GetChannelMaxMinPower(struct ath_hal *ah,
644572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
645572ff6f6SMatthew Dillon int16_t *maxPow, int16_t *minPow)
646572ff6f6SMatthew Dillon {
647572ff6f6SMatthew Dillon uint16_t freq = chan->ic_freq; /* NB: never mapped */
648572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
649572ff6f6SMatthew Dillon const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL;
650572ff6f6SMatthew Dillon const RAW_DATA_PER_CHANNEL_2316 *data=AH_NULL;
651572ff6f6SMatthew Dillon uint16_t numChannels;
652572ff6f6SMatthew Dillon int totalD,totalF, totalMin,last, i;
653572ff6f6SMatthew Dillon
654572ff6f6SMatthew Dillon *maxPow = 0;
655572ff6f6SMatthew Dillon
656572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
657572ff6f6SMatthew Dillon pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
658572ff6f6SMatthew Dillon else if (IEEE80211_IS_CHAN_B(chan))
659572ff6f6SMatthew Dillon pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
660572ff6f6SMatthew Dillon else
661572ff6f6SMatthew Dillon return(AH_FALSE);
662572ff6f6SMatthew Dillon
663572ff6f6SMatthew Dillon numChannels = pRawDataset->numChannels;
664572ff6f6SMatthew Dillon data = pRawDataset->pDataPerChannel;
665572ff6f6SMatthew Dillon
666572ff6f6SMatthew Dillon /* Make sure the channel is in the range of the TP values
667572ff6f6SMatthew Dillon * (freq piers)
668572ff6f6SMatthew Dillon */
669572ff6f6SMatthew Dillon if (numChannels < 1)
670572ff6f6SMatthew Dillon return(AH_FALSE);
671572ff6f6SMatthew Dillon
672572ff6f6SMatthew Dillon if ((freq < data[0].channelValue) ||
673572ff6f6SMatthew Dillon (freq > data[numChannels-1].channelValue)) {
674572ff6f6SMatthew Dillon if (freq < data[0].channelValue) {
675572ff6f6SMatthew Dillon *maxPow = ar2316GetMaxPower(ah, &data[0]);
676572ff6f6SMatthew Dillon *minPow = ar2316GetMinPower(ah, &data[0]);
677572ff6f6SMatthew Dillon return(AH_TRUE);
678572ff6f6SMatthew Dillon } else {
679572ff6f6SMatthew Dillon *maxPow = ar2316GetMaxPower(ah, &data[numChannels - 1]);
680572ff6f6SMatthew Dillon *minPow = ar2316GetMinPower(ah, &data[numChannels - 1]);
681572ff6f6SMatthew Dillon return(AH_TRUE);
682572ff6f6SMatthew Dillon }
683572ff6f6SMatthew Dillon }
684572ff6f6SMatthew Dillon
685572ff6f6SMatthew Dillon /* Linearly interpolate the power value now */
686572ff6f6SMatthew Dillon for (last=0,i=0; (i<numChannels) && (freq > data[i].channelValue);
687572ff6f6SMatthew Dillon last = i++);
688572ff6f6SMatthew Dillon totalD = data[i].channelValue - data[last].channelValue;
689572ff6f6SMatthew Dillon if (totalD > 0) {
690572ff6f6SMatthew Dillon totalF = ar2316GetMaxPower(ah, &data[i]) - ar2316GetMaxPower(ah, &data[last]);
691572ff6f6SMatthew Dillon *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) +
692572ff6f6SMatthew Dillon ar2316GetMaxPower(ah, &data[last])*totalD)/totalD);
693572ff6f6SMatthew Dillon totalMin = ar2316GetMinPower(ah, &data[i]) - ar2316GetMinPower(ah, &data[last]);
694572ff6f6SMatthew Dillon *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) +
695572ff6f6SMatthew Dillon ar2316GetMinPower(ah, &data[last])*totalD)/totalD);
696572ff6f6SMatthew Dillon return(AH_TRUE);
697572ff6f6SMatthew Dillon } else {
698572ff6f6SMatthew Dillon if (freq == data[i].channelValue) {
699572ff6f6SMatthew Dillon *maxPow = ar2316GetMaxPower(ah, &data[i]);
700572ff6f6SMatthew Dillon *minPow = ar2316GetMinPower(ah, &data[i]);
701572ff6f6SMatthew Dillon return(AH_TRUE);
702572ff6f6SMatthew Dillon } else
703572ff6f6SMatthew Dillon return(AH_FALSE);
704572ff6f6SMatthew Dillon }
705572ff6f6SMatthew Dillon }
706572ff6f6SMatthew Dillon
707572ff6f6SMatthew Dillon /*
708572ff6f6SMatthew Dillon * Free memory for analog bank scratch buffers
709572ff6f6SMatthew Dillon */
710572ff6f6SMatthew Dillon static void
ar2316RfDetach(struct ath_hal * ah)711572ff6f6SMatthew Dillon ar2316RfDetach(struct ath_hal *ah)
712572ff6f6SMatthew Dillon {
713572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
714572ff6f6SMatthew Dillon
715572ff6f6SMatthew Dillon HALASSERT(ahp->ah_rfHal != AH_NULL);
716572ff6f6SMatthew Dillon ath_hal_free(ahp->ah_rfHal);
717572ff6f6SMatthew Dillon ahp->ah_rfHal = AH_NULL;
718572ff6f6SMatthew Dillon }
719572ff6f6SMatthew Dillon
720572ff6f6SMatthew Dillon /*
721572ff6f6SMatthew Dillon * Allocate memory for private state.
722572ff6f6SMatthew Dillon * Scratch Buffer will be reinitialized every reset so no need to zero now
723572ff6f6SMatthew Dillon */
724572ff6f6SMatthew Dillon static HAL_BOOL
ar2316RfAttach(struct ath_hal * ah,HAL_STATUS * status)725572ff6f6SMatthew Dillon ar2316RfAttach(struct ath_hal *ah, HAL_STATUS *status)
726572ff6f6SMatthew Dillon {
727572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
728572ff6f6SMatthew Dillon struct ar2316State *priv;
729572ff6f6SMatthew Dillon
730572ff6f6SMatthew Dillon HALASSERT(ah->ah_magic == AR5212_MAGIC);
731572ff6f6SMatthew Dillon
732572ff6f6SMatthew Dillon HALASSERT(ahp->ah_rfHal == AH_NULL);
733572ff6f6SMatthew Dillon priv = ath_hal_malloc(sizeof(struct ar2316State));
734572ff6f6SMatthew Dillon if (priv == AH_NULL) {
735572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
736572ff6f6SMatthew Dillon "%s: cannot allocate private state\n", __func__);
737572ff6f6SMatthew Dillon *status = HAL_ENOMEM; /* XXX */
738572ff6f6SMatthew Dillon return AH_FALSE;
739572ff6f6SMatthew Dillon }
740572ff6f6SMatthew Dillon priv->base.rfDetach = ar2316RfDetach;
741572ff6f6SMatthew Dillon priv->base.writeRegs = ar2316WriteRegs;
742572ff6f6SMatthew Dillon priv->base.getRfBank = ar2316GetRfBank;
743572ff6f6SMatthew Dillon priv->base.setChannel = ar2316SetChannel;
744572ff6f6SMatthew Dillon priv->base.setRfRegs = ar2316SetRfRegs;
745572ff6f6SMatthew Dillon priv->base.setPowerTable = ar2316SetPowerTable;
746572ff6f6SMatthew Dillon priv->base.getChannelMaxMinPower = ar2316GetChannelMaxMinPower;
747572ff6f6SMatthew Dillon priv->base.getNfAdjust = ar5212GetNfAdjust;
748572ff6f6SMatthew Dillon
749572ff6f6SMatthew Dillon ahp->ah_pcdacTable = priv->pcdacTable;
750572ff6f6SMatthew Dillon ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
751572ff6f6SMatthew Dillon ahp->ah_rfHal = &priv->base;
752572ff6f6SMatthew Dillon
753572ff6f6SMatthew Dillon ahp->ah_cwCalRequire = AH_TRUE; /* force initial cal */
754572ff6f6SMatthew Dillon
755572ff6f6SMatthew Dillon return AH_TRUE;
756572ff6f6SMatthew Dillon }
757572ff6f6SMatthew Dillon
758572ff6f6SMatthew Dillon static HAL_BOOL
ar2316Probe(struct ath_hal * ah)759572ff6f6SMatthew Dillon ar2316Probe(struct ath_hal *ah)
760572ff6f6SMatthew Dillon {
761572ff6f6SMatthew Dillon return IS_2316(ah);
762572ff6f6SMatthew Dillon }
763572ff6f6SMatthew Dillon AH_RF(RF2316, ar2316Probe, ar2316RfAttach);
764