1572ff6f6SMatthew Dillon /* 2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc. 4572ff6f6SMatthew Dillon * 5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any 6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above 7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies. 8572ff6f6SMatthew Dillon * 9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16572ff6f6SMatthew Dillon * 17572ff6f6SMatthew Dillon * $FreeBSD$ 18572ff6f6SMatthew Dillon */ 19572ff6f6SMatthew Dillon #ifndef _ATH_AR5212_H_ 20572ff6f6SMatthew Dillon #define _ATH_AR5212_H_ 21572ff6f6SMatthew Dillon 22572ff6f6SMatthew Dillon #include "ah_eeprom.h" 23572ff6f6SMatthew Dillon 24572ff6f6SMatthew Dillon #define AR5212_MAGIC 0x19541014 25572ff6f6SMatthew Dillon 26572ff6f6SMatthew Dillon /* DCU Transmit Filter macros */ 27572ff6f6SMatthew Dillon #define CALC_MMR(dcu, idx) \ 28572ff6f6SMatthew Dillon ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 29572ff6f6SMatthew Dillon #define TXBLK_FROM_MMR(mmr) \ 30572ff6f6SMatthew Dillon (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 31572ff6f6SMatthew Dillon #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 32572ff6f6SMatthew Dillon #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 33572ff6f6SMatthew Dillon 34572ff6f6SMatthew Dillon /* MAC register values */ 35572ff6f6SMatthew Dillon 36572ff6f6SMatthew Dillon #define INIT_INTERRUPT_MASK \ 37572ff6f6SMatthew Dillon ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 38572ff6f6SMatthew Dillon AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 39572ff6f6SMatthew Dillon AR_IMR_HIUERR ) 40572ff6f6SMatthew Dillon #define INIT_BEACON_CONTROL \ 41572ff6f6SMatthew Dillon ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 42572ff6f6SMatthew Dillon (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 43572ff6f6SMatthew Dillon 44572ff6f6SMatthew Dillon #define INIT_CONFIG_STATUS 0x00000000 45572ff6f6SMatthew Dillon #define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 46572ff6f6SMatthew Dillon #define INIT_IQCAL_LOG_COUNT_MAX 0xF 47572ff6f6SMatthew Dillon #define INIT_BCON_CNTRL_REG 0x00000000 48572ff6f6SMatthew Dillon 49572ff6f6SMatthew Dillon #define INIT_USEC 40 50572ff6f6SMatthew Dillon #define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 51572ff6f6SMatthew Dillon #define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 52572ff6f6SMatthew Dillon 53572ff6f6SMatthew Dillon #define RX_NON_FULL_RATE_LATENCY 63 54572ff6f6SMatthew Dillon #define TX_HALF_RATE_LATENCY 108 55572ff6f6SMatthew Dillon #define TX_QUARTER_RATE_LATENCY 216 56572ff6f6SMatthew Dillon 57572ff6f6SMatthew Dillon #define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 58572ff6f6SMatthew Dillon #define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 59572ff6f6SMatthew Dillon #define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 60572ff6f6SMatthew Dillon #define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 61572ff6f6SMatthew Dillon #define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 62572ff6f6SMatthew Dillon #define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 63572ff6f6SMatthew Dillon 64572ff6f6SMatthew Dillon #define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 65572ff6f6SMatthew Dillon 66572ff6f6SMatthew Dillon /* Tx frame start to tx data start delay */ 67572ff6f6SMatthew Dillon #define TX_FRAME_D_START_HALF_RATE 0xc 68572ff6f6SMatthew Dillon #define TX_FRAME_D_START_QUARTER_RATE 0xd 69572ff6f6SMatthew Dillon 70572ff6f6SMatthew Dillon /* 71572ff6f6SMatthew Dillon * Various fifo fill before Tx start, in 64-byte units 72572ff6f6SMatthew Dillon * i.e. put the frame in the air while still DMAing 73572ff6f6SMatthew Dillon */ 74572ff6f6SMatthew Dillon #define MIN_TX_FIFO_THRESHOLD 0x1 75572ff6f6SMatthew Dillon #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 76572ff6f6SMatthew Dillon #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 77572ff6f6SMatthew Dillon 78572ff6f6SMatthew Dillon #define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 79572ff6f6SMatthew Dillon 80572ff6f6SMatthew Dillon /* 81572ff6f6SMatthew Dillon * Gain support. 82572ff6f6SMatthew Dillon */ 83572ff6f6SMatthew Dillon #define NUM_CORNER_FIX_BITS 4 84572ff6f6SMatthew Dillon #define NUM_CORNER_FIX_BITS_5112 7 85572ff6f6SMatthew Dillon #define DYN_ADJ_UP_MARGIN 15 86572ff6f6SMatthew Dillon #define DYN_ADJ_LO_MARGIN 20 87572ff6f6SMatthew Dillon #define PHY_PROBE_CCK_CORRECTION 5 88572ff6f6SMatthew Dillon #define CCK_OFDM_GAIN_DELTA 15 89572ff6f6SMatthew Dillon 90572ff6f6SMatthew Dillon enum GAIN_PARAMS { 91572ff6f6SMatthew Dillon GP_TXCLIP, 92572ff6f6SMatthew Dillon GP_PD90, 93572ff6f6SMatthew Dillon GP_PD84, 94572ff6f6SMatthew Dillon GP_GSEL, 95572ff6f6SMatthew Dillon }; 96572ff6f6SMatthew Dillon 97572ff6f6SMatthew Dillon enum GAIN_PARAMS_5112 { 98572ff6f6SMatthew Dillon GP_MIXGAIN_OVR, 99572ff6f6SMatthew Dillon GP_PWD_138, 100572ff6f6SMatthew Dillon GP_PWD_137, 101572ff6f6SMatthew Dillon GP_PWD_136, 102572ff6f6SMatthew Dillon GP_PWD_132, 103572ff6f6SMatthew Dillon GP_PWD_131, 104572ff6f6SMatthew Dillon GP_PWD_130, 105572ff6f6SMatthew Dillon }; 106572ff6f6SMatthew Dillon 107572ff6f6SMatthew Dillon typedef struct _gainOptStep { 108572ff6f6SMatthew Dillon int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 109572ff6f6SMatthew Dillon int32_t stepGain; 110572ff6f6SMatthew Dillon int8_t stepName[16]; 111572ff6f6SMatthew Dillon } GAIN_OPTIMIZATION_STEP; 112572ff6f6SMatthew Dillon 113572ff6f6SMatthew Dillon typedef struct { 114572ff6f6SMatthew Dillon uint32_t numStepsInLadder; 115572ff6f6SMatthew Dillon uint32_t defaultStepNum; 116572ff6f6SMatthew Dillon GAIN_OPTIMIZATION_STEP optStep[10]; 117572ff6f6SMatthew Dillon } GAIN_OPTIMIZATION_LADDER; 118572ff6f6SMatthew Dillon 119572ff6f6SMatthew Dillon typedef struct { 120572ff6f6SMatthew Dillon uint32_t currStepNum; 121572ff6f6SMatthew Dillon uint32_t currGain; 122572ff6f6SMatthew Dillon uint32_t targetGain; 123572ff6f6SMatthew Dillon uint32_t loTrig; 124572ff6f6SMatthew Dillon uint32_t hiTrig; 125572ff6f6SMatthew Dillon uint32_t active; 126572ff6f6SMatthew Dillon const GAIN_OPTIMIZATION_STEP *currStep; 127572ff6f6SMatthew Dillon } GAIN_VALUES; 128572ff6f6SMatthew Dillon 129572ff6f6SMatthew Dillon /* RF HAL structures */ 130572ff6f6SMatthew Dillon typedef struct RfHalFuncs { 131572ff6f6SMatthew Dillon void *priv; /* private state */ 132572ff6f6SMatthew Dillon 133572ff6f6SMatthew Dillon void (*rfDetach)(struct ath_hal *ah); 134572ff6f6SMatthew Dillon void (*writeRegs)(struct ath_hal *, 135572ff6f6SMatthew Dillon u_int modeIndex, u_int freqIndex, int regWrites); 136572ff6f6SMatthew Dillon uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 137572ff6f6SMatthew Dillon HAL_BOOL (*setChannel)(struct ath_hal *, 138572ff6f6SMatthew Dillon const struct ieee80211_channel *); 139572ff6f6SMatthew Dillon HAL_BOOL (*setRfRegs)(struct ath_hal *, 140572ff6f6SMatthew Dillon const struct ieee80211_channel *, uint16_t modesIndex, 141572ff6f6SMatthew Dillon uint16_t *rfXpdGain); 142572ff6f6SMatthew Dillon HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 143572ff6f6SMatthew Dillon int16_t *minPower, int16_t *maxPower, 144572ff6f6SMatthew Dillon const struct ieee80211_channel *, uint16_t *rfXpdGain); 145572ff6f6SMatthew Dillon HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, 146572ff6f6SMatthew Dillon const struct ieee80211_channel *, 147572ff6f6SMatthew Dillon int16_t *maxPow, int16_t *minPow); 148572ff6f6SMatthew Dillon int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 149572ff6f6SMatthew Dillon } RF_HAL_FUNCS; 150572ff6f6SMatthew Dillon 151572ff6f6SMatthew Dillon struct ar5212AniParams { 152572ff6f6SMatthew Dillon int maxNoiseImmunityLevel; /* [0..4] */ 153572ff6f6SMatthew Dillon int totalSizeDesired[5]; 154572ff6f6SMatthew Dillon int coarseHigh[5]; 155572ff6f6SMatthew Dillon int coarseLow[5]; 156572ff6f6SMatthew Dillon int firpwr[5]; 157572ff6f6SMatthew Dillon 158572ff6f6SMatthew Dillon int maxSpurImmunityLevel; /* [0..7] */ 159572ff6f6SMatthew Dillon int cycPwrThr1[8]; 160572ff6f6SMatthew Dillon 161572ff6f6SMatthew Dillon int maxFirstepLevel; /* [0..2] */ 162572ff6f6SMatthew Dillon int firstep[3]; 163572ff6f6SMatthew Dillon 164572ff6f6SMatthew Dillon uint32_t ofdmTrigHigh; 165572ff6f6SMatthew Dillon uint32_t ofdmTrigLow; 166572ff6f6SMatthew Dillon uint32_t cckTrigHigh; 167572ff6f6SMatthew Dillon uint32_t cckTrigLow; 168572ff6f6SMatthew Dillon int32_t rssiThrLow; 169572ff6f6SMatthew Dillon uint32_t rssiThrHigh; 170572ff6f6SMatthew Dillon 171572ff6f6SMatthew Dillon int period; /* update listen period */ 172572ff6f6SMatthew Dillon 173572ff6f6SMatthew Dillon /* NB: intentionally ordered so data exported to user space is first */ 174572ff6f6SMatthew Dillon uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 175572ff6f6SMatthew Dillon uint32_t cckPhyErrBase; /* Base value for cck err counters */ 176572ff6f6SMatthew Dillon }; 177572ff6f6SMatthew Dillon 178572ff6f6SMatthew Dillon /* 179572ff6f6SMatthew Dillon * Per-channel ANI state private to the driver. 180572ff6f6SMatthew Dillon */ 181572ff6f6SMatthew Dillon struct ar5212AniState { 182572ff6f6SMatthew Dillon uint8_t noiseImmunityLevel; 183572ff6f6SMatthew Dillon uint8_t spurImmunityLevel; 184572ff6f6SMatthew Dillon uint8_t firstepLevel; 185572ff6f6SMatthew Dillon uint8_t ofdmWeakSigDetectOff; 186572ff6f6SMatthew Dillon uint8_t cckWeakSigThreshold; 187572ff6f6SMatthew Dillon uint32_t listenTime; 188572ff6f6SMatthew Dillon 189572ff6f6SMatthew Dillon /* NB: intentionally ordered so data exported to user space is first */ 190572ff6f6SMatthew Dillon uint32_t txFrameCount; /* Last txFrameCount */ 191572ff6f6SMatthew Dillon uint32_t rxFrameCount; /* Last rx Frame count */ 192572ff6f6SMatthew Dillon uint32_t cycleCount; /* Last cycleCount 193572ff6f6SMatthew Dillon (to detect wrap-around) */ 194572ff6f6SMatthew Dillon uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 195572ff6f6SMatthew Dillon uint32_t cckPhyErrCount; /* CCK err count since last reset */ 196572ff6f6SMatthew Dillon 197572ff6f6SMatthew Dillon const struct ar5212AniParams *params; 198572ff6f6SMatthew Dillon }; 199572ff6f6SMatthew Dillon 200572ff6f6SMatthew Dillon #define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 201572ff6f6SMatthew Dillon #define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 202572ff6f6SMatthew Dillon 203*b14ca477SMatthew Dillon #if 0 204572ff6f6SMatthew Dillon struct ar5212Stats { 205572ff6f6SMatthew Dillon uint32_t ast_ani_niup; /* ANI increased noise immunity */ 206572ff6f6SMatthew Dillon uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 207572ff6f6SMatthew Dillon uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 208572ff6f6SMatthew Dillon uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 209572ff6f6SMatthew Dillon uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 210572ff6f6SMatthew Dillon uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 211572ff6f6SMatthew Dillon uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 212572ff6f6SMatthew Dillon uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 213572ff6f6SMatthew Dillon uint32_t ast_ani_stepup; /* ANI increased first step level */ 214572ff6f6SMatthew Dillon uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 215572ff6f6SMatthew Dillon uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 216572ff6f6SMatthew Dillon uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 217572ff6f6SMatthew Dillon uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 218572ff6f6SMatthew Dillon uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 219572ff6f6SMatthew Dillon uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 220572ff6f6SMatthew Dillon HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 221572ff6f6SMatthew Dillon HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 222572ff6f6SMatthew Dillon }; 223*b14ca477SMatthew Dillon #endif 224572ff6f6SMatthew Dillon 225572ff6f6SMatthew Dillon /* 226572ff6f6SMatthew Dillon * NF Cal history buffer 227572ff6f6SMatthew Dillon */ 228572ff6f6SMatthew Dillon #define AR5212_CCA_MAX_GOOD_VALUE -95 229572ff6f6SMatthew Dillon #define AR5212_CCA_MAX_HIGH_VALUE -62 230572ff6f6SMatthew Dillon #define AR5212_CCA_MIN_BAD_VALUE -125 231572ff6f6SMatthew Dillon 232572ff6f6SMatthew Dillon #define AR512_NF_CAL_HIST_MAX 5 233572ff6f6SMatthew Dillon 234572ff6f6SMatthew Dillon struct ar5212NfCalHist { 235572ff6f6SMatthew Dillon int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 236572ff6f6SMatthew Dillon int16_t privNF; 237572ff6f6SMatthew Dillon uint8_t currIndex; 238572ff6f6SMatthew Dillon uint8_t first_run; 239572ff6f6SMatthew Dillon uint8_t invalidNFcount; 240572ff6f6SMatthew Dillon }; 241572ff6f6SMatthew Dillon 242572ff6f6SMatthew Dillon struct ath_hal_5212 { 243572ff6f6SMatthew Dillon struct ath_hal_private ah_priv; /* base class */ 244572ff6f6SMatthew Dillon 245572ff6f6SMatthew Dillon /* 246572ff6f6SMatthew Dillon * Per-chip common Initialization data. 247572ff6f6SMatthew Dillon * NB: RF backends have their own ini data. 248572ff6f6SMatthew Dillon */ 249572ff6f6SMatthew Dillon HAL_INI_ARRAY ah_ini_modes; 250572ff6f6SMatthew Dillon HAL_INI_ARRAY ah_ini_common; 251572ff6f6SMatthew Dillon 252572ff6f6SMatthew Dillon GAIN_VALUES ah_gainValues; 253572ff6f6SMatthew Dillon 254572ff6f6SMatthew Dillon uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 255572ff6f6SMatthew Dillon uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 256572ff6f6SMatthew Dillon uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 257572ff6f6SMatthew Dillon uint16_t ah_assocId; 258572ff6f6SMatthew Dillon 259572ff6f6SMatthew Dillon /* 260572ff6f6SMatthew Dillon * Runtime state. 261572ff6f6SMatthew Dillon */ 262572ff6f6SMatthew Dillon uint32_t ah_maskReg; /* copy of AR_IMR */ 263*b14ca477SMatthew Dillon HAL_ANI_STATS ah_stats; /* various statistics */ 264572ff6f6SMatthew Dillon RF_HAL_FUNCS *ah_rfHal; 265572ff6f6SMatthew Dillon uint32_t ah_txDescMask; /* mask for TXDESC */ 266572ff6f6SMatthew Dillon uint32_t ah_txOkInterruptMask; 267572ff6f6SMatthew Dillon uint32_t ah_txErrInterruptMask; 268572ff6f6SMatthew Dillon uint32_t ah_txDescInterruptMask; 269572ff6f6SMatthew Dillon uint32_t ah_txEolInterruptMask; 270572ff6f6SMatthew Dillon uint32_t ah_txUrnInterruptMask; 271572ff6f6SMatthew Dillon HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 272572ff6f6SMatthew Dillon uint32_t ah_intrTxqs; /* tx q interrupt state */ 273572ff6f6SMatthew Dillon /* decomp mask array */ 274572ff6f6SMatthew Dillon uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 275572ff6f6SMatthew Dillon HAL_ANT_SETTING ah_antControl; /* antenna setting */ 276572ff6f6SMatthew Dillon HAL_BOOL ah_diversity; /* fast diversity setting */ 277572ff6f6SMatthew Dillon enum { 278572ff6f6SMatthew Dillon IQ_CAL_INACTIVE, 279572ff6f6SMatthew Dillon IQ_CAL_RUNNING, 280572ff6f6SMatthew Dillon IQ_CAL_DONE 281572ff6f6SMatthew Dillon } ah_bIQCalibration; /* IQ calibrate state */ 282572ff6f6SMatthew Dillon HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 283572ff6f6SMatthew Dillon uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 284572ff6f6SMatthew Dillon uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 285572ff6f6SMatthew Dillon uint32_t ah_miscMode; /* MISC_MODE settings */ 286572ff6f6SMatthew Dillon uint32_t ah_rssiThr; /* RSSI_THR settings */ 287572ff6f6SMatthew Dillon HAL_BOOL ah_cwCalRequire; /* for ap51 */ 288572ff6f6SMatthew Dillon HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 289572ff6f6SMatthew Dillon HAL_BOOL ah_phyPowerOn; /* PHY power state */ 290572ff6f6SMatthew Dillon HAL_BOOL ah_isHb63; /* cached HB63 check */ 291572ff6f6SMatthew Dillon uint32_t ah_macTPC; /* tpc register */ 292572ff6f6SMatthew Dillon uint32_t ah_beaconInterval; /* XXX */ 293572ff6f6SMatthew Dillon enum { 294572ff6f6SMatthew Dillon AUTO_32KHZ, /* use it if 32kHz crystal present */ 295572ff6f6SMatthew Dillon USE_32KHZ, /* do it regardless */ 296572ff6f6SMatthew Dillon DONT_USE_32KHZ, /* don't use it regardless */ 297572ff6f6SMatthew Dillon } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 298572ff6f6SMatthew Dillon uint32_t ah_ofdmTxPower; 299572ff6f6SMatthew Dillon int16_t ah_txPowerIndexOffset; 300572ff6f6SMatthew Dillon /* 301572ff6f6SMatthew Dillon * Noise floor cal histogram support. 302572ff6f6SMatthew Dillon */ 303572ff6f6SMatthew Dillon struct ar5212NfCalHist ah_nfCalHist; 304572ff6f6SMatthew Dillon 305572ff6f6SMatthew Dillon u_int ah_slottime; /* user-specified slot time */ 306572ff6f6SMatthew Dillon u_int ah_acktimeout; /* user-specified ack timeout */ 307572ff6f6SMatthew Dillon u_int ah_ctstimeout; /* user-specified cts timeout */ 308572ff6f6SMatthew Dillon u_int ah_sifstime; /* user-specified sifs time */ 309572ff6f6SMatthew Dillon /* 310572ff6f6SMatthew Dillon * RF Silent handling; setup according to the EEPROM. 311572ff6f6SMatthew Dillon */ 312572ff6f6SMatthew Dillon uint32_t ah_gpioSelect; /* GPIO pin to use */ 313572ff6f6SMatthew Dillon uint32_t ah_polarity; /* polarity to disable RF */ 314572ff6f6SMatthew Dillon uint32_t ah_gpioBit; /* after init, prev value */ 315572ff6f6SMatthew Dillon /* 316572ff6f6SMatthew Dillon * ANI support. 317572ff6f6SMatthew Dillon */ 318572ff6f6SMatthew Dillon uint32_t ah_procPhyErr; /* Process Phy errs */ 319572ff6f6SMatthew Dillon HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 320572ff6f6SMatthew Dillon struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 321572ff6f6SMatthew Dillon struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 322572ff6f6SMatthew Dillon struct ar5212AniState *ah_curani; /* cached last reference */ 323572ff6f6SMatthew Dillon struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */ 324572ff6f6SMatthew Dillon 325572ff6f6SMatthew Dillon /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */ 326572ff6f6SMatthew Dillon HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param); 327572ff6f6SMatthew Dillon 328572ff6f6SMatthew Dillon /* 329572ff6f6SMatthew Dillon * Transmit power state. Note these are maintained 330572ff6f6SMatthew Dillon * here so they can be retrieved by diagnostic tools. 331572ff6f6SMatthew Dillon */ 332572ff6f6SMatthew Dillon uint16_t *ah_pcdacTable; 333572ff6f6SMatthew Dillon u_int ah_pcdacTableSize; 334572ff6f6SMatthew Dillon uint16_t ah_ratesArray[37]; 335572ff6f6SMatthew Dillon 336572ff6f6SMatthew Dillon uint8_t ah_txTrigLev; /* current Tx trigger level */ 337572ff6f6SMatthew Dillon uint8_t ah_maxTxTrigLev; /* max tx trigger level */ 338572ff6f6SMatthew Dillon 339572ff6f6SMatthew Dillon /* 340572ff6f6SMatthew Dillon * Channel Tx, Rx, Rx Clear State 341572ff6f6SMatthew Dillon */ 342572ff6f6SMatthew Dillon uint32_t ah_cycleCount; 343572ff6f6SMatthew Dillon uint32_t ah_ctlBusy; 344572ff6f6SMatthew Dillon uint32_t ah_rxBusy; 345572ff6f6SMatthew Dillon uint32_t ah_txBusy; 346572ff6f6SMatthew Dillon uint32_t ah_rx_chainmask; 347572ff6f6SMatthew Dillon uint32_t ah_tx_chainmask; 348*b14ca477SMatthew Dillon 349*b14ca477SMatthew Dillon /* Used to return ANI statistics to the diagnostic API */ 350*b14ca477SMatthew Dillon HAL_ANI_STATS ext_ani_stats; 351572ff6f6SMatthew Dillon }; 352572ff6f6SMatthew Dillon #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 353572ff6f6SMatthew Dillon 354572ff6f6SMatthew Dillon /* 355572ff6f6SMatthew Dillon * IS_XXXX macros test the MAC version 356572ff6f6SMatthew Dillon * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 357572ff6f6SMatthew Dillon * 358572ff6f6SMatthew Dillon * Some single chip radios have equivalent radio/RF (e.g. 5112) 359572ff6f6SMatthew Dillon * for those use IS_RADXXX_ANY macros. 360572ff6f6SMatthew Dillon */ 361572ff6f6SMatthew Dillon #define IS_2317(ah) \ 362572ff6f6SMatthew Dillon ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 363572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 364572ff6f6SMatthew Dillon #define IS_2316(ah) \ 365572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 366572ff6f6SMatthew Dillon #define IS_2413(ah) \ 367572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 368572ff6f6SMatthew Dillon #define IS_5424(ah) \ 369572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 370572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 371572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 372572ff6f6SMatthew Dillon #define IS_5413(ah) \ 373572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 374572ff6f6SMatthew Dillon #define IS_2425(ah) \ 375572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 376572ff6f6SMatthew Dillon #define IS_2417(ah) \ 377572ff6f6SMatthew Dillon ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 378572ff6f6SMatthew Dillon #define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 379572ff6f6SMatthew Dillon 380572ff6f6SMatthew Dillon #define AH_RADIO_MAJOR(ah) \ 381572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 382572ff6f6SMatthew Dillon #define AH_RADIO_MINOR(ah) \ 383572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 384572ff6f6SMatthew Dillon #define IS_RAD5111(ah) \ 385572ff6f6SMatthew Dillon (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 386572ff6f6SMatthew Dillon AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 387572ff6f6SMatthew Dillon #define IS_RAD5112(ah) \ 388572ff6f6SMatthew Dillon (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 389572ff6f6SMatthew Dillon AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 390572ff6f6SMatthew Dillon /* NB: does not include 5413 as Atheros' IS_5112 macro does */ 391572ff6f6SMatthew Dillon #define IS_RAD5112_ANY(ah) \ 392572ff6f6SMatthew Dillon (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 393572ff6f6SMatthew Dillon AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 394572ff6f6SMatthew Dillon #define IS_RAD5112_REV1(ah) \ 395572ff6f6SMatthew Dillon (IS_RAD5112(ah) && \ 396572ff6f6SMatthew Dillon AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 397572ff6f6SMatthew Dillon #define IS_RADX112_REV2(ah) \ 398572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 399572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 400572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 401572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 402572ff6f6SMatthew Dillon 403572ff6f6SMatthew Dillon #define ar5212RfDetach(ah) do { \ 404572ff6f6SMatthew Dillon if (AH5212(ah)->ah_rfHal != AH_NULL) \ 405572ff6f6SMatthew Dillon AH5212(ah)->ah_rfHal->rfDetach(ah); \ 406572ff6f6SMatthew Dillon } while (0) 407572ff6f6SMatthew Dillon #define ar5212GetRfBank(ah, b) \ 408572ff6f6SMatthew Dillon AH5212(ah)->ah_rfHal->getRfBank(ah, b) 409572ff6f6SMatthew Dillon 410572ff6f6SMatthew Dillon /* 411572ff6f6SMatthew Dillon * Hack macros for Nala/San: 11b is handled 412572ff6f6SMatthew Dillon * using 11g; flip the channel flags to accomplish this. 413572ff6f6SMatthew Dillon */ 414572ff6f6SMatthew Dillon #define SAVE_CCK(_ah, _chan, _flag) do { \ 415572ff6f6SMatthew Dillon if ((IS_2425(_ah) || IS_2417(_ah)) && \ 416572ff6f6SMatthew Dillon (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \ 417572ff6f6SMatthew Dillon (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \ 418572ff6f6SMatthew Dillon (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \ 419572ff6f6SMatthew Dillon (_flag) = AH_TRUE; \ 420572ff6f6SMatthew Dillon } else \ 421572ff6f6SMatthew Dillon (_flag) = AH_FALSE; \ 422572ff6f6SMatthew Dillon } while (0) 423572ff6f6SMatthew Dillon #define RESTORE_CCK(_ah, _chan, _flag) do { \ 424572ff6f6SMatthew Dillon if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \ 425572ff6f6SMatthew Dillon (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \ 426572ff6f6SMatthew Dillon (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \ 427572ff6f6SMatthew Dillon } \ 428572ff6f6SMatthew Dillon } while (0) 429572ff6f6SMatthew Dillon 430572ff6f6SMatthew Dillon struct ath_hal; 431572ff6f6SMatthew Dillon 432572ff6f6SMatthew Dillon extern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 433572ff6f6SMatthew Dillon extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 434572ff6f6SMatthew Dillon HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 435572ff6f6SMatthew Dillon extern void ar5212Detach(struct ath_hal *ah); 436572ff6f6SMatthew Dillon extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 437572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 438572ff6f6SMatthew Dillon uint16_t flags, uint16_t *low, uint16_t *high); 439572ff6f6SMatthew Dillon extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 440572ff6f6SMatthew Dillon 441572ff6f6SMatthew Dillon extern void ar5212SetBeaconTimers(struct ath_hal *ah, 442572ff6f6SMatthew Dillon const HAL_BEACON_TIMERS *); 443572ff6f6SMatthew Dillon extern void ar5212BeaconInit(struct ath_hal *ah, 444572ff6f6SMatthew Dillon uint32_t next_beacon, uint32_t beacon_period); 445572ff6f6SMatthew Dillon extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 446572ff6f6SMatthew Dillon extern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 447572ff6f6SMatthew Dillon const HAL_BEACON_STATE *); 448572ff6f6SMatthew Dillon extern uint64_t ar5212GetNextTBTT(struct ath_hal *); 449572ff6f6SMatthew Dillon 450572ff6f6SMatthew Dillon extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 451572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 452572ff6f6SMatthew Dillon extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 453572ff6f6SMatthew Dillon extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 454572ff6f6SMatthew Dillon 455572ff6f6SMatthew Dillon extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 456572ff6f6SMatthew Dillon extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 457572ff6f6SMatthew Dillon extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 458572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 459572ff6f6SMatthew Dillon uint16_t entry, const uint8_t *mac); 460572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 461572ff6f6SMatthew Dillon const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 462572ff6f6SMatthew Dillon 463572ff6f6SMatthew Dillon extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 464572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 465572ff6f6SMatthew Dillon extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 466572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 467572ff6f6SMatthew Dillon extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 468572ff6f6SMatthew Dillon extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 469572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 470572ff6f6SMatthew Dillon uint16_t regDomain, HAL_STATUS *stats); 471572ff6f6SMatthew Dillon extern u_int ar5212GetWirelessModes(struct ath_hal *ah); 472572ff6f6SMatthew Dillon extern void ar5212EnableRfKill(struct ath_hal *); 473572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio, 474572ff6f6SMatthew Dillon HAL_GPIO_MUX_TYPE); 475572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 476572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 477572ff6f6SMatthew Dillon extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 478572ff6f6SMatthew Dillon extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 479572ff6f6SMatthew Dillon extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 480572ff6f6SMatthew Dillon extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 481572ff6f6SMatthew Dillon uint16_t assocId); 482572ff6f6SMatthew Dillon extern uint32_t ar5212GetTsf32(struct ath_hal *ah); 483572ff6f6SMatthew Dillon extern uint64_t ar5212GetTsf64(struct ath_hal *ah); 484572ff6f6SMatthew Dillon extern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64); 485572ff6f6SMatthew Dillon extern void ar5212ResetTsf(struct ath_hal *ah); 486572ff6f6SMatthew Dillon extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 487572ff6f6SMatthew Dillon extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 488572ff6f6SMatthew Dillon extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 489572ff6f6SMatthew Dillon extern void ar5212EnableMibCounters(struct ath_hal *); 490572ff6f6SMatthew Dillon extern void ar5212DisableMibCounters(struct ath_hal *); 491572ff6f6SMatthew Dillon extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 492572ff6f6SMatthew Dillon extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 493572ff6f6SMatthew Dillon extern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 494572ff6f6SMatthew Dillon extern u_int ar5212GetDefAntenna(struct ath_hal *ah); 495572ff6f6SMatthew Dillon extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 496572ff6f6SMatthew Dillon extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 497572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 498572ff6f6SMatthew Dillon extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 499572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 500572ff6f6SMatthew Dillon extern u_int ar5212GetSifsTime(struct ath_hal *); 501572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 502572ff6f6SMatthew Dillon extern u_int ar5212GetSlotTime(struct ath_hal *); 503572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 504572ff6f6SMatthew Dillon extern u_int ar5212GetAckTimeout(struct ath_hal *); 505572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 506572ff6f6SMatthew Dillon extern u_int ar5212GetAckCTSRate(struct ath_hal *); 507572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 508572ff6f6SMatthew Dillon extern u_int ar5212GetCTSTimeout(struct ath_hal *); 509572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 510572ff6f6SMatthew Dillon void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 511572ff6f6SMatthew Dillon extern void ar5212SetPCUConfig(struct ath_hal *); 512572ff6f6SMatthew Dillon extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 513572ff6f6SMatthew Dillon extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 514572ff6f6SMatthew Dillon extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 515572ff6f6SMatthew Dillon extern int16_t ar5212GetNfAdjust(struct ath_hal *, 516572ff6f6SMatthew Dillon const HAL_CHANNEL_INTERNAL *); 517572ff6f6SMatthew Dillon extern void ar5212SetCompRegs(struct ath_hal *ah); 518572ff6f6SMatthew Dillon extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 519572ff6f6SMatthew Dillon uint32_t, uint32_t *); 520572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 521572ff6f6SMatthew Dillon uint32_t, uint32_t, HAL_STATUS *); 522572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 523572ff6f6SMatthew Dillon const void *args, uint32_t argsize, 524572ff6f6SMatthew Dillon void **result, uint32_t *resultsize); 525572ff6f6SMatthew Dillon extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period, 526572ff6f6SMatthew Dillon uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); 527572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *, 528572ff6f6SMatthew Dillon HAL_SURVEY_SAMPLE *); 529572ff6f6SMatthew Dillon extern void ar5212SetChainMasks(struct ath_hal *, uint32_t, uint32_t); 530572ff6f6SMatthew Dillon 531572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 532572ff6f6SMatthew Dillon int setChip); 533572ff6f6SMatthew Dillon extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 534572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 535572ff6f6SMatthew Dillon 536572ff6f6SMatthew Dillon extern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE); 537572ff6f6SMatthew Dillon extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE); 538572ff6f6SMatthew Dillon extern void ar5212EnableReceive(struct ath_hal *ah); 539572ff6f6SMatthew Dillon extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 540572ff6f6SMatthew Dillon extern void ar5212StartPcuReceive(struct ath_hal *ah); 541572ff6f6SMatthew Dillon extern void ar5212StopPcuReceive(struct ath_hal *ah); 542572ff6f6SMatthew Dillon extern void ar5212SetMulticastFilter(struct ath_hal *ah, 543572ff6f6SMatthew Dillon uint32_t filter0, uint32_t filter1); 544572ff6f6SMatthew Dillon extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 545572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 546572ff6f6SMatthew Dillon extern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 547572ff6f6SMatthew Dillon extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 548572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 549572ff6f6SMatthew Dillon struct ath_desc *, uint32_t size, u_int flags); 550572ff6f6SMatthew Dillon extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 551572ff6f6SMatthew Dillon uint32_t, struct ath_desc *, uint64_t, 552572ff6f6SMatthew Dillon struct ath_rx_status *); 553572ff6f6SMatthew Dillon 554572ff6f6SMatthew Dillon extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 555572ff6f6SMatthew Dillon struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 556*b14ca477SMatthew Dillon HAL_RESET_TYPE, HAL_STATUS *status); 557572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetChannel(struct ath_hal *, 558572ff6f6SMatthew Dillon const struct ieee80211_channel *); 559572ff6f6SMatthew Dillon extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 560572ff6f6SMatthew Dillon extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 561572ff6f6SMatthew Dillon extern HAL_BOOL ar5212Disable(struct ath_hal *ah); 562572ff6f6SMatthew Dillon extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, 563572ff6f6SMatthew Dillon const struct ieee80211_channel *); 564572ff6f6SMatthew Dillon extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, 565572ff6f6SMatthew Dillon struct ieee80211_channel *chan, HAL_BOOL *isIQdone); 566572ff6f6SMatthew Dillon extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, 567572ff6f6SMatthew Dillon struct ieee80211_channel *chan, u_int chainMask, 568572ff6f6SMatthew Dillon HAL_BOOL longCal, HAL_BOOL *isCalDone); 569572ff6f6SMatthew Dillon extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, 570572ff6f6SMatthew Dillon const struct ieee80211_channel *); 571572ff6f6SMatthew Dillon extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 572572ff6f6SMatthew Dillon extern void ar5212InitNfCalHistBuffer(struct ath_hal *); 573572ff6f6SMatthew Dillon extern int16_t ar5212GetNfHistMid(const int16_t calData[]); 574572ff6f6SMatthew Dillon extern void ar5212SetSpurMitigation(struct ath_hal *, 575572ff6f6SMatthew Dillon const struct ieee80211_channel *); 576572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 577572ff6f6SMatthew Dillon HAL_ANT_SETTING settings, const struct ieee80211_channel *); 578572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 579572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 580572ff6f6SMatthew Dillon struct ieee80211_channel *chan); 581572ff6f6SMatthew Dillon extern void ar5212InitializeGainValues(struct ath_hal *); 582572ff6f6SMatthew Dillon extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 583572ff6f6SMatthew Dillon extern void ar5212RequestRfgain(struct ath_hal *); 584572ff6f6SMatthew Dillon 585572ff6f6SMatthew Dillon extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 586572ff6f6SMatthew Dillon HAL_BOOL IncTrigLevel); 587572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 588572ff6f6SMatthew Dillon const HAL_TXQ_INFO *qInfo); 589572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 590572ff6f6SMatthew Dillon HAL_TXQ_INFO *qInfo); 591572ff6f6SMatthew Dillon extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 592572ff6f6SMatthew Dillon const HAL_TXQ_INFO *qInfo); 593572ff6f6SMatthew Dillon extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 594572ff6f6SMatthew Dillon extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 595572ff6f6SMatthew Dillon extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 596572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 597572ff6f6SMatthew Dillon extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 598572ff6f6SMatthew Dillon extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 599572ff6f6SMatthew Dillon extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 600572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 601572ff6f6SMatthew Dillon u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 602572ff6f6SMatthew Dillon u_int txRate0, u_int txTries0, 603572ff6f6SMatthew Dillon u_int keyIx, u_int antMode, u_int flags, 604572ff6f6SMatthew Dillon u_int rtsctsRate, u_int rtsctsDuration, 605572ff6f6SMatthew Dillon u_int compicvLen, u_int compivLen, u_int comp); 606572ff6f6SMatthew Dillon extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 607572ff6f6SMatthew Dillon u_int txRate1, u_int txRetries1, 608572ff6f6SMatthew Dillon u_int txRate2, u_int txRetries2, 609572ff6f6SMatthew Dillon u_int txRate3, u_int txRetries3); 610572ff6f6SMatthew Dillon extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 611572ff6f6SMatthew Dillon HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 612572ff6f6SMatthew Dillon u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 613572ff6f6SMatthew Dillon const struct ath_desc *ds0); 614572ff6f6SMatthew Dillon extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 615572ff6f6SMatthew Dillon struct ath_desc *, struct ath_tx_status *); 616572ff6f6SMatthew Dillon extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 617572ff6f6SMatthew Dillon extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 618572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah, 619572ff6f6SMatthew Dillon const struct ath_desc *ds0, int *rates, int *tries); 620572ff6f6SMatthew Dillon extern void ar5212SetTxDescLink(struct ath_hal *ah, void *ds, 621572ff6f6SMatthew Dillon uint32_t link); 622572ff6f6SMatthew Dillon extern void ar5212GetTxDescLink(struct ath_hal *ah, void *ds, 623572ff6f6SMatthew Dillon uint32_t *link); 624572ff6f6SMatthew Dillon extern void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds, 625572ff6f6SMatthew Dillon uint32_t **linkptr); 626572ff6f6SMatthew Dillon 627572ff6f6SMatthew Dillon extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 628572ff6f6SMatthew Dillon 629572ff6f6SMatthew Dillon extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 630572ff6f6SMatthew Dillon const struct ar5212AniParams *, HAL_BOOL ena); 631572ff6f6SMatthew Dillon extern void ar5212AniDetach(struct ath_hal *); 632572ff6f6SMatthew Dillon extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 633*b14ca477SMatthew Dillon extern HAL_ANI_STATS *ar5212AniGetCurrentStats(struct ath_hal *); 634572ff6f6SMatthew Dillon extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 635572ff6f6SMatthew Dillon extern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 636572ff6f6SMatthew Dillon const struct ar5212AniParams *, const struct ar5212AniParams *); 637572ff6f6SMatthew Dillon struct ath_rx_status; 638572ff6f6SMatthew Dillon extern void ar5212AniPhyErrReport(struct ath_hal *ah, 639572ff6f6SMatthew Dillon const struct ath_rx_status *rs); 640572ff6f6SMatthew Dillon extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 641572ff6f6SMatthew Dillon extern void ar5212RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, 642572ff6f6SMatthew Dillon const struct ieee80211_channel *); 643572ff6f6SMatthew Dillon extern void ar5212AniPoll(struct ath_hal *, const struct ieee80211_channel *); 644572ff6f6SMatthew Dillon extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *, 645572ff6f6SMatthew Dillon HAL_OPMODE, int); 646572ff6f6SMatthew Dillon 647572ff6f6SMatthew Dillon extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); 648572ff6f6SMatthew Dillon extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); 649572ff6f6SMatthew Dillon extern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 650572ff6f6SMatthew Dillon extern HAL_BOOL ar5212GetDfsDefaultThresh(struct ath_hal *ah, 651572ff6f6SMatthew Dillon HAL_PHYERR_PARAM *pe); 652572ff6f6SMatthew Dillon extern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 653572ff6f6SMatthew Dillon extern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah, 654572ff6f6SMatthew Dillon struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, 655572ff6f6SMatthew Dillon HAL_DFS_EVENT *event); 656572ff6f6SMatthew Dillon extern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah); 657572ff6f6SMatthew Dillon extern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah); 658572ff6f6SMatthew Dillon 659572ff6f6SMatthew Dillon #endif /* _ATH_AR5212_H_ */ 660