1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon #include "opt_ah.h"
20572ff6f6SMatthew Dillon
21572ff6f6SMatthew Dillon #include "ah.h"
22572ff6f6SMatthew Dillon #include "ah_internal.h"
23572ff6f6SMatthew Dillon #include "ah_devid.h"
24572ff6f6SMatthew Dillon
25572ff6f6SMatthew Dillon #include "ar5212/ar5212.h"
26572ff6f6SMatthew Dillon #include "ar5212/ar5212reg.h"
27572ff6f6SMatthew Dillon #include "ar5212/ar5212phy.h"
28572ff6f6SMatthew Dillon
29572ff6f6SMatthew Dillon #define AH_5212_COMMON
30572ff6f6SMatthew Dillon #include "ar5212/ar5212.ini"
31572ff6f6SMatthew Dillon
32572ff6f6SMatthew Dillon static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
33572ff6f6SMatthew Dillon HAL_BOOL power_off);
34572ff6f6SMatthew Dillon static void ar5212DisablePCIE(struct ath_hal *ah);
35572ff6f6SMatthew Dillon
36572ff6f6SMatthew Dillon static const struct ath_hal_private ar5212hal = {{
37572ff6f6SMatthew Dillon .ah_magic = AR5212_MAGIC,
38572ff6f6SMatthew Dillon
39572ff6f6SMatthew Dillon .ah_getRateTable = ar5212GetRateTable,
40572ff6f6SMatthew Dillon .ah_detach = ar5212Detach,
41572ff6f6SMatthew Dillon
42572ff6f6SMatthew Dillon /* Reset Functions */
43572ff6f6SMatthew Dillon .ah_reset = ar5212Reset,
44572ff6f6SMatthew Dillon .ah_phyDisable = ar5212PhyDisable,
45572ff6f6SMatthew Dillon .ah_disable = ar5212Disable,
46572ff6f6SMatthew Dillon .ah_configPCIE = ar5212ConfigPCIE,
47572ff6f6SMatthew Dillon .ah_disablePCIE = ar5212DisablePCIE,
48572ff6f6SMatthew Dillon .ah_setPCUConfig = ar5212SetPCUConfig,
49572ff6f6SMatthew Dillon .ah_perCalibration = ar5212PerCalibration,
50572ff6f6SMatthew Dillon .ah_perCalibrationN = ar5212PerCalibrationN,
51572ff6f6SMatthew Dillon .ah_resetCalValid = ar5212ResetCalValid,
52572ff6f6SMatthew Dillon .ah_setTxPowerLimit = ar5212SetTxPowerLimit,
53572ff6f6SMatthew Dillon .ah_getChanNoise = ath_hal_getChanNoise,
54572ff6f6SMatthew Dillon
55572ff6f6SMatthew Dillon /* Transmit functions */
56572ff6f6SMatthew Dillon .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel,
57572ff6f6SMatthew Dillon .ah_setupTxQueue = ar5212SetupTxQueue,
58572ff6f6SMatthew Dillon .ah_setTxQueueProps = ar5212SetTxQueueProps,
59572ff6f6SMatthew Dillon .ah_getTxQueueProps = ar5212GetTxQueueProps,
60572ff6f6SMatthew Dillon .ah_releaseTxQueue = ar5212ReleaseTxQueue,
61572ff6f6SMatthew Dillon .ah_resetTxQueue = ar5212ResetTxQueue,
62572ff6f6SMatthew Dillon .ah_getTxDP = ar5212GetTxDP,
63572ff6f6SMatthew Dillon .ah_setTxDP = ar5212SetTxDP,
64572ff6f6SMatthew Dillon .ah_numTxPending = ar5212NumTxPending,
65572ff6f6SMatthew Dillon .ah_startTxDma = ar5212StartTxDma,
66572ff6f6SMatthew Dillon .ah_stopTxDma = ar5212StopTxDma,
67572ff6f6SMatthew Dillon .ah_setupTxDesc = ar5212SetupTxDesc,
68572ff6f6SMatthew Dillon .ah_setupXTxDesc = ar5212SetupXTxDesc,
69572ff6f6SMatthew Dillon .ah_fillTxDesc = ar5212FillTxDesc,
70572ff6f6SMatthew Dillon .ah_procTxDesc = ar5212ProcTxDesc,
71572ff6f6SMatthew Dillon .ah_getTxIntrQueue = ar5212GetTxIntrQueue,
72572ff6f6SMatthew Dillon .ah_reqTxIntrDesc = ar5212IntrReqTxDesc,
73572ff6f6SMatthew Dillon .ah_getTxCompletionRates = ar5212GetTxCompletionRates,
74572ff6f6SMatthew Dillon .ah_setTxDescLink = ar5212SetTxDescLink,
75572ff6f6SMatthew Dillon .ah_getTxDescLink = ar5212GetTxDescLink,
76572ff6f6SMatthew Dillon .ah_getTxDescLinkPtr = ar5212GetTxDescLinkPtr,
77572ff6f6SMatthew Dillon
78572ff6f6SMatthew Dillon /* RX Functions */
79572ff6f6SMatthew Dillon .ah_getRxDP = ar5212GetRxDP,
80572ff6f6SMatthew Dillon .ah_setRxDP = ar5212SetRxDP,
81572ff6f6SMatthew Dillon .ah_enableReceive = ar5212EnableReceive,
82572ff6f6SMatthew Dillon .ah_stopDmaReceive = ar5212StopDmaReceive,
83572ff6f6SMatthew Dillon .ah_startPcuReceive = ar5212StartPcuReceive,
84572ff6f6SMatthew Dillon .ah_stopPcuReceive = ar5212StopPcuReceive,
85572ff6f6SMatthew Dillon .ah_setMulticastFilter = ar5212SetMulticastFilter,
86572ff6f6SMatthew Dillon .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex,
87572ff6f6SMatthew Dillon .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex,
88572ff6f6SMatthew Dillon .ah_getRxFilter = ar5212GetRxFilter,
89572ff6f6SMatthew Dillon .ah_setRxFilter = ar5212SetRxFilter,
90572ff6f6SMatthew Dillon .ah_setupRxDesc = ar5212SetupRxDesc,
91572ff6f6SMatthew Dillon .ah_procRxDesc = ar5212ProcRxDesc,
92572ff6f6SMatthew Dillon .ah_rxMonitor = ar5212RxMonitor,
93572ff6f6SMatthew Dillon .ah_aniPoll = ar5212AniPoll,
94572ff6f6SMatthew Dillon .ah_procMibEvent = ar5212ProcessMibIntr,
95572ff6f6SMatthew Dillon
96572ff6f6SMatthew Dillon /* Misc Functions */
97572ff6f6SMatthew Dillon .ah_getCapability = ar5212GetCapability,
98572ff6f6SMatthew Dillon .ah_setCapability = ar5212SetCapability,
99572ff6f6SMatthew Dillon .ah_getDiagState = ar5212GetDiagState,
100572ff6f6SMatthew Dillon .ah_getMacAddress = ar5212GetMacAddress,
101572ff6f6SMatthew Dillon .ah_setMacAddress = ar5212SetMacAddress,
102572ff6f6SMatthew Dillon .ah_getBssIdMask = ar5212GetBssIdMask,
103572ff6f6SMatthew Dillon .ah_setBssIdMask = ar5212SetBssIdMask,
104572ff6f6SMatthew Dillon .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain,
105572ff6f6SMatthew Dillon .ah_setLedState = ar5212SetLedState,
106572ff6f6SMatthew Dillon .ah_writeAssocid = ar5212WriteAssocid,
107572ff6f6SMatthew Dillon .ah_gpioCfgInput = ar5212GpioCfgInput,
108572ff6f6SMatthew Dillon .ah_gpioCfgOutput = ar5212GpioCfgOutput,
109572ff6f6SMatthew Dillon .ah_gpioGet = ar5212GpioGet,
110572ff6f6SMatthew Dillon .ah_gpioSet = ar5212GpioSet,
111572ff6f6SMatthew Dillon .ah_gpioSetIntr = ar5212GpioSetIntr,
112572ff6f6SMatthew Dillon .ah_getTsf32 = ar5212GetTsf32,
113572ff6f6SMatthew Dillon .ah_getTsf64 = ar5212GetTsf64,
114572ff6f6SMatthew Dillon .ah_setTsf64 = ar5212SetTsf64,
115572ff6f6SMatthew Dillon .ah_resetTsf = ar5212ResetTsf,
116572ff6f6SMatthew Dillon .ah_detectCardPresent = ar5212DetectCardPresent,
117572ff6f6SMatthew Dillon .ah_updateMibCounters = ar5212UpdateMibCounters,
118572ff6f6SMatthew Dillon .ah_getRfGain = ar5212GetRfgain,
119572ff6f6SMatthew Dillon .ah_getDefAntenna = ar5212GetDefAntenna,
120572ff6f6SMatthew Dillon .ah_setDefAntenna = ar5212SetDefAntenna,
121572ff6f6SMatthew Dillon .ah_getAntennaSwitch = ar5212GetAntennaSwitch,
122572ff6f6SMatthew Dillon .ah_setAntennaSwitch = ar5212SetAntennaSwitch,
123572ff6f6SMatthew Dillon .ah_setSifsTime = ar5212SetSifsTime,
124572ff6f6SMatthew Dillon .ah_getSifsTime = ar5212GetSifsTime,
125572ff6f6SMatthew Dillon .ah_setSlotTime = ar5212SetSlotTime,
126572ff6f6SMatthew Dillon .ah_getSlotTime = ar5212GetSlotTime,
127572ff6f6SMatthew Dillon .ah_setAckTimeout = ar5212SetAckTimeout,
128572ff6f6SMatthew Dillon .ah_getAckTimeout = ar5212GetAckTimeout,
129572ff6f6SMatthew Dillon .ah_setAckCTSRate = ar5212SetAckCTSRate,
130572ff6f6SMatthew Dillon .ah_getAckCTSRate = ar5212GetAckCTSRate,
131572ff6f6SMatthew Dillon .ah_setCTSTimeout = ar5212SetCTSTimeout,
132572ff6f6SMatthew Dillon .ah_getCTSTimeout = ar5212GetCTSTimeout,
133572ff6f6SMatthew Dillon .ah_setDecompMask = ar5212SetDecompMask,
134572ff6f6SMatthew Dillon .ah_setCoverageClass = ar5212SetCoverageClass,
135572ff6f6SMatthew Dillon .ah_setQuiet = ar5212SetQuiet,
136572ff6f6SMatthew Dillon .ah_getMibCycleCounts = ar5212GetMibCycleCounts,
137572ff6f6SMatthew Dillon .ah_setChainMasks = ar5212SetChainMasks,
138572ff6f6SMatthew Dillon
139572ff6f6SMatthew Dillon /* DFS Functions */
140572ff6f6SMatthew Dillon .ah_enableDfs = ar5212EnableDfs,
141572ff6f6SMatthew Dillon .ah_getDfsThresh = ar5212GetDfsThresh,
142572ff6f6SMatthew Dillon .ah_getDfsDefaultThresh = ar5212GetDfsDefaultThresh,
143572ff6f6SMatthew Dillon .ah_procRadarEvent = ar5212ProcessRadarEvent,
144572ff6f6SMatthew Dillon .ah_isFastClockEnabled = ar5212IsFastClockEnabled,
145572ff6f6SMatthew Dillon .ah_get11nExtBusy = ar5212Get11nExtBusy,
146572ff6f6SMatthew Dillon
147572ff6f6SMatthew Dillon /* Key Cache Functions */
148572ff6f6SMatthew Dillon .ah_getKeyCacheSize = ar5212GetKeyCacheSize,
149572ff6f6SMatthew Dillon .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry,
150572ff6f6SMatthew Dillon .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid,
151572ff6f6SMatthew Dillon .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry,
152572ff6f6SMatthew Dillon .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac,
153572ff6f6SMatthew Dillon
154572ff6f6SMatthew Dillon /* Power Management Functions */
155572ff6f6SMatthew Dillon .ah_setPowerMode = ar5212SetPowerMode,
156572ff6f6SMatthew Dillon .ah_getPowerMode = ar5212GetPowerMode,
157572ff6f6SMatthew Dillon
158572ff6f6SMatthew Dillon /* Beacon Functions */
159572ff6f6SMatthew Dillon .ah_setBeaconTimers = ar5212SetBeaconTimers,
160572ff6f6SMatthew Dillon .ah_beaconInit = ar5212BeaconInit,
161572ff6f6SMatthew Dillon .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers,
162572ff6f6SMatthew Dillon .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers,
163572ff6f6SMatthew Dillon .ah_getNextTBTT = ar5212GetNextTBTT,
164572ff6f6SMatthew Dillon
165572ff6f6SMatthew Dillon /* Interrupt Functions */
166572ff6f6SMatthew Dillon .ah_isInterruptPending = ar5212IsInterruptPending,
167572ff6f6SMatthew Dillon .ah_getPendingInterrupts = ar5212GetPendingInterrupts,
168572ff6f6SMatthew Dillon .ah_getInterrupts = ar5212GetInterrupts,
169572ff6f6SMatthew Dillon .ah_setInterrupts = ar5212SetInterrupts },
170572ff6f6SMatthew Dillon
171572ff6f6SMatthew Dillon .ah_getChannelEdges = ar5212GetChannelEdges,
172572ff6f6SMatthew Dillon .ah_getWirelessModes = ar5212GetWirelessModes,
173572ff6f6SMatthew Dillon .ah_eepromRead = ar5212EepromRead,
174572ff6f6SMatthew Dillon #ifdef AH_SUPPORT_WRITE_EEPROM
175572ff6f6SMatthew Dillon .ah_eepromWrite = ar5212EepromWrite,
176572ff6f6SMatthew Dillon #endif
177572ff6f6SMatthew Dillon .ah_getChipPowerLimits = ar5212GetChipPowerLimits,
178572ff6f6SMatthew Dillon };
179572ff6f6SMatthew Dillon
180572ff6f6SMatthew Dillon uint32_t
ar5212GetRadioRev(struct ath_hal * ah)181572ff6f6SMatthew Dillon ar5212GetRadioRev(struct ath_hal *ah)
182572ff6f6SMatthew Dillon {
183572ff6f6SMatthew Dillon uint32_t val;
184572ff6f6SMatthew Dillon int i;
185572ff6f6SMatthew Dillon
186572ff6f6SMatthew Dillon /* Read Radio Chip Rev Extract */
187572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
188572ff6f6SMatthew Dillon for (i = 0; i < 8; i++)
189572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
190572ff6f6SMatthew Dillon val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
191572ff6f6SMatthew Dillon val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
192572ff6f6SMatthew Dillon return ath_hal_reverseBits(val, 8);
193572ff6f6SMatthew Dillon }
194572ff6f6SMatthew Dillon
195572ff6f6SMatthew Dillon static void
ar5212AniSetup(struct ath_hal * ah)196572ff6f6SMatthew Dillon ar5212AniSetup(struct ath_hal *ah)
197572ff6f6SMatthew Dillon {
198572ff6f6SMatthew Dillon static const struct ar5212AniParams aniparams = {
199572ff6f6SMatthew Dillon .maxNoiseImmunityLevel = 4, /* levels 0..4 */
200572ff6f6SMatthew Dillon .totalSizeDesired = { -55, -55, -55, -55, -62 },
201572ff6f6SMatthew Dillon .coarseHigh = { -14, -14, -14, -14, -12 },
202572ff6f6SMatthew Dillon .coarseLow = { -64, -64, -64, -64, -70 },
203572ff6f6SMatthew Dillon .firpwr = { -78, -78, -78, -78, -80 },
204572ff6f6SMatthew Dillon .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */
205572ff6f6SMatthew Dillon .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
206572ff6f6SMatthew Dillon .maxFirstepLevel = 2, /* levels 0..2 */
207572ff6f6SMatthew Dillon .firstep = { 0, 4, 8 },
208572ff6f6SMatthew Dillon .ofdmTrigHigh = 500,
209572ff6f6SMatthew Dillon .ofdmTrigLow = 200,
210572ff6f6SMatthew Dillon .cckTrigHigh = 200,
211572ff6f6SMatthew Dillon .cckTrigLow = 100,
212572ff6f6SMatthew Dillon .rssiThrHigh = 40,
213572ff6f6SMatthew Dillon .rssiThrLow = 7,
214572ff6f6SMatthew Dillon .period = 100,
215572ff6f6SMatthew Dillon };
216572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
217572ff6f6SMatthew Dillon struct ar5212AniParams tmp;
218572ff6f6SMatthew Dillon OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
219572ff6f6SMatthew Dillon tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */
220572ff6f6SMatthew Dillon ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
221572ff6f6SMatthew Dillon } else
222572ff6f6SMatthew Dillon ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
223572ff6f6SMatthew Dillon
224572ff6f6SMatthew Dillon /* Set overridable ANI methods */
225572ff6f6SMatthew Dillon AH5212(ah)->ah_aniControl = ar5212AniControl;
226572ff6f6SMatthew Dillon }
227572ff6f6SMatthew Dillon
228572ff6f6SMatthew Dillon /*
229572ff6f6SMatthew Dillon * Attach for an AR5212 part.
230572ff6f6SMatthew Dillon */
231572ff6f6SMatthew Dillon void
ar5212InitState(struct ath_hal_5212 * ahp,uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,HAL_STATUS * status)232572ff6f6SMatthew Dillon ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
233572ff6f6SMatthew Dillon HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
234572ff6f6SMatthew Dillon {
235572ff6f6SMatthew Dillon #define N(a) (sizeof(a)/sizeof(a[0]))
236572ff6f6SMatthew Dillon static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
237572ff6f6SMatthew Dillon { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
238572ff6f6SMatthew Dillon struct ath_hal *ah;
239572ff6f6SMatthew Dillon
240572ff6f6SMatthew Dillon ah = &ahp->ah_priv.h;
241572ff6f6SMatthew Dillon /* set initial values */
242572ff6f6SMatthew Dillon OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private));
243572ff6f6SMatthew Dillon ah->ah_sc = sc;
244572ff6f6SMatthew Dillon ah->ah_st = st;
245572ff6f6SMatthew Dillon ah->ah_sh = sh;
246572ff6f6SMatthew Dillon
247572ff6f6SMatthew Dillon ah->ah_devid = devid; /* NB: for alq */
248572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_devid = devid;
249572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */
250572ff6f6SMatthew Dillon
251572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
252572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */
253572ff6f6SMatthew Dillon
254572ff6f6SMatthew Dillon ahp->ah_antControl = HAL_ANT_VARIABLE;
255572ff6f6SMatthew Dillon ahp->ah_diversity = AH_TRUE;
256572ff6f6SMatthew Dillon ahp->ah_bIQCalibration = AH_FALSE;
257572ff6f6SMatthew Dillon /*
258572ff6f6SMatthew Dillon * Enable MIC handling.
259572ff6f6SMatthew Dillon */
260572ff6f6SMatthew Dillon ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
261572ff6f6SMatthew Dillon ahp->ah_rssiThr = INIT_RSSI_THR;
262572ff6f6SMatthew Dillon ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */
263572ff6f6SMatthew Dillon ahp->ah_phyPowerOn = AH_FALSE;
264572ff6f6SMatthew Dillon ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK)
265572ff6f6SMatthew Dillon | SM(MAX_RATE_POWER, AR_TPC_CTS)
266572ff6f6SMatthew Dillon | SM(MAX_RATE_POWER, AR_TPC_CHIRP);
267572ff6f6SMatthew Dillon ahp->ah_beaconInterval = 100; /* XXX [20..1000] */
268572ff6f6SMatthew Dillon ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */
269572ff6f6SMatthew Dillon ahp->ah_slottime = (u_int) -1;
270572ff6f6SMatthew Dillon ahp->ah_acktimeout = (u_int) -1;
271572ff6f6SMatthew Dillon ahp->ah_ctstimeout = (u_int) -1;
272572ff6f6SMatthew Dillon ahp->ah_sifstime = (u_int) -1;
273*3a05fd2aSSascha Wildner ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD;
274*3a05fd2aSSascha Wildner ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD;
275572ff6f6SMatthew Dillon
276572ff6f6SMatthew Dillon OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
277572ff6f6SMatthew Dillon #undef N
278572ff6f6SMatthew Dillon }
279572ff6f6SMatthew Dillon
280572ff6f6SMatthew Dillon /*
281572ff6f6SMatthew Dillon * Validate MAC version and revision.
282572ff6f6SMatthew Dillon */
283572ff6f6SMatthew Dillon static HAL_BOOL
ar5212IsMacSupported(uint8_t macVersion,uint8_t macRev)284572ff6f6SMatthew Dillon ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
285572ff6f6SMatthew Dillon {
286572ff6f6SMatthew Dillon #define N(a) (sizeof(a)/sizeof(a[0]))
287572ff6f6SMatthew Dillon static const struct {
288572ff6f6SMatthew Dillon uint8_t version;
289572ff6f6SMatthew Dillon uint8_t revMin, revMax;
290572ff6f6SMatthew Dillon } macs[] = {
291572ff6f6SMatthew Dillon { AR_SREV_VERSION_VENICE,
292572ff6f6SMatthew Dillon AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
293572ff6f6SMatthew Dillon { AR_SREV_VERSION_GRIFFIN,
294572ff6f6SMatthew Dillon AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
295572ff6f6SMatthew Dillon { AR_SREV_5413,
296572ff6f6SMatthew Dillon AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
297572ff6f6SMatthew Dillon { AR_SREV_5424,
298572ff6f6SMatthew Dillon AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
299572ff6f6SMatthew Dillon { AR_SREV_2425,
300572ff6f6SMatthew Dillon AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
301572ff6f6SMatthew Dillon { AR_SREV_2417,
302572ff6f6SMatthew Dillon AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
303572ff6f6SMatthew Dillon };
304572ff6f6SMatthew Dillon int i;
305572ff6f6SMatthew Dillon
306572ff6f6SMatthew Dillon for (i = 0; i < N(macs); i++)
307572ff6f6SMatthew Dillon if (macs[i].version == macVersion &&
308572ff6f6SMatthew Dillon macs[i].revMin <= macRev && macRev <= macs[i].revMax)
309572ff6f6SMatthew Dillon return AH_TRUE;
310572ff6f6SMatthew Dillon return AH_FALSE;
311572ff6f6SMatthew Dillon #undef N
312572ff6f6SMatthew Dillon }
313572ff6f6SMatthew Dillon
314572ff6f6SMatthew Dillon /*
315572ff6f6SMatthew Dillon * Attach for an AR5212 part.
316572ff6f6SMatthew Dillon */
317572ff6f6SMatthew Dillon static struct ath_hal *
ar5212Attach(uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,uint16_t * eepromdata,HAL_OPS_CONFIG * ah_config,HAL_STATUS * status)318572ff6f6SMatthew Dillon ar5212Attach(uint16_t devid, HAL_SOFTC sc,
319572ff6f6SMatthew Dillon HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
320848b370cSMatthew Dillon HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
321572ff6f6SMatthew Dillon {
322572ff6f6SMatthew Dillon #define AH_EEPROM_PROTECT(ah) \
323572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
324572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp;
325572ff6f6SMatthew Dillon struct ath_hal *ah;
326572ff6f6SMatthew Dillon struct ath_hal_rf *rf;
327572ff6f6SMatthew Dillon uint32_t val;
328572ff6f6SMatthew Dillon uint16_t eeval;
329572ff6f6SMatthew Dillon HAL_STATUS ecode;
330572ff6f6SMatthew Dillon
331572ff6f6SMatthew Dillon HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
332572ff6f6SMatthew Dillon __func__, sc, (void*) st, (void*) sh);
333572ff6f6SMatthew Dillon
334572ff6f6SMatthew Dillon /* NB: memory is returned zero'd */
335572ff6f6SMatthew Dillon ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
336572ff6f6SMatthew Dillon if (ahp == AH_NULL) {
337572ff6f6SMatthew Dillon HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
338572ff6f6SMatthew Dillon "%s: cannot allocate memory for state block\n", __func__);
339572ff6f6SMatthew Dillon *status = HAL_ENOMEM;
340572ff6f6SMatthew Dillon return AH_NULL;
341572ff6f6SMatthew Dillon }
342572ff6f6SMatthew Dillon ar5212InitState(ahp, devid, sc, st, sh, status);
343572ff6f6SMatthew Dillon ah = &ahp->ah_priv.h;
344572ff6f6SMatthew Dillon
345572ff6f6SMatthew Dillon if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
346572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
347572ff6f6SMatthew Dillon __func__);
348572ff6f6SMatthew Dillon ecode = HAL_EIO;
349572ff6f6SMatthew Dillon goto bad;
350572ff6f6SMatthew Dillon }
351572ff6f6SMatthew Dillon /* Read Revisions from Chips before taking out of reset */
352572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
353572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
354572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
355572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah);
356572ff6f6SMatthew Dillon
357572ff6f6SMatthew Dillon if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
358572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
359572ff6f6SMatthew Dillon "%s: Mac Chip Rev 0x%02x.%x not supported\n" ,
360572ff6f6SMatthew Dillon __func__, AH_PRIVATE(ah)->ah_macVersion,
361572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev);
362572ff6f6SMatthew Dillon ecode = HAL_ENOTSUPP;
363572ff6f6SMatthew Dillon goto bad;
364572ff6f6SMatthew Dillon }
365572ff6f6SMatthew Dillon
366572ff6f6SMatthew Dillon /* setup common ini data; rf backends handle remainder */
367572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
368572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
369572ff6f6SMatthew Dillon
370572ff6f6SMatthew Dillon if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */
371572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
372572ff6f6SMatthew Dillon ecode = HAL_EIO;
373572ff6f6SMatthew Dillon goto bad;
374572ff6f6SMatthew Dillon }
375572ff6f6SMatthew Dillon
376572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
377572ff6f6SMatthew Dillon
378572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_ispcie) {
379572ff6f6SMatthew Dillon /* XXX: build flag to disable this? */
380572ff6f6SMatthew Dillon ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);
381572ff6f6SMatthew Dillon }
382572ff6f6SMatthew Dillon
383572ff6f6SMatthew Dillon if (!ar5212ChipTest(ah)) {
384572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
385572ff6f6SMatthew Dillon __func__);
386572ff6f6SMatthew Dillon ecode = HAL_ESELFTEST;
387572ff6f6SMatthew Dillon goto bad;
388572ff6f6SMatthew Dillon }
389572ff6f6SMatthew Dillon
390572ff6f6SMatthew Dillon /* Enable PCI core retry fix in software for Hainan and up */
391572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
392572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
393572ff6f6SMatthew Dillon
394572ff6f6SMatthew Dillon /*
395572ff6f6SMatthew Dillon * Set correct Baseband to analog shift
396572ff6f6SMatthew Dillon * setting to access analog chips.
397572ff6f6SMatthew Dillon */
398572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
399572ff6f6SMatthew Dillon
400572ff6f6SMatthew Dillon /* Read Radio Chip Rev Extract */
401572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
402572ff6f6SMatthew Dillon
403572ff6f6SMatthew Dillon rf = ath_hal_rfprobe(ah, &ecode);
404572ff6f6SMatthew Dillon if (rf == AH_NULL)
405572ff6f6SMatthew Dillon goto bad;
406572ff6f6SMatthew Dillon
407572ff6f6SMatthew Dillon /* NB: silently accept anything in release code per Atheros */
408572ff6f6SMatthew Dillon switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
409572ff6f6SMatthew Dillon case AR_RAD5111_SREV_MAJOR:
410572ff6f6SMatthew Dillon case AR_RAD5112_SREV_MAJOR:
411572ff6f6SMatthew Dillon case AR_RAD2112_SREV_MAJOR:
412572ff6f6SMatthew Dillon case AR_RAD2111_SREV_MAJOR:
413572ff6f6SMatthew Dillon case AR_RAD2413_SREV_MAJOR:
414572ff6f6SMatthew Dillon case AR_RAD5413_SREV_MAJOR:
415572ff6f6SMatthew Dillon case AR_RAD5424_SREV_MAJOR:
416572ff6f6SMatthew Dillon break;
417572ff6f6SMatthew Dillon default:
418572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
419572ff6f6SMatthew Dillon /*
420572ff6f6SMatthew Dillon * When RF_Silent is used, the
421572ff6f6SMatthew Dillon * analog chip is reset. So when the system boots
422572ff6f6SMatthew Dillon * up with the radio switch off we cannot determine
423572ff6f6SMatthew Dillon * the RF chip rev. To workaround this check the
424572ff6f6SMatthew Dillon * mac+phy revs and if Hainan, set the radio rev
425572ff6f6SMatthew Dillon * to Derby.
426572ff6f6SMatthew Dillon */
427572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
428572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
429572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
430572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
431572ff6f6SMatthew Dillon break;
432572ff6f6SMatthew Dillon }
433572ff6f6SMatthew Dillon if (IS_2413(ah)) { /* Griffin */
434572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev =
435572ff6f6SMatthew Dillon AR_RAD2413_SREV_MAJOR | 0x1;
436572ff6f6SMatthew Dillon break;
437572ff6f6SMatthew Dillon }
438572ff6f6SMatthew Dillon if (IS_5413(ah)) { /* Eagle */
439572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev =
440572ff6f6SMatthew Dillon AR_RAD5413_SREV_MAJOR | 0x2;
441572ff6f6SMatthew Dillon break;
442572ff6f6SMatthew Dillon }
443572ff6f6SMatthew Dillon if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */
444572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev =
445572ff6f6SMatthew Dillon AR_RAD5424_SREV_MAJOR | 0x2;
446572ff6f6SMatthew Dillon break;
447572ff6f6SMatthew Dillon }
448572ff6f6SMatthew Dillon }
449572ff6f6SMatthew Dillon #ifdef AH_DEBUG
450572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
451572ff6f6SMatthew Dillon "%s: 5G Radio Chip Rev 0x%02X is not supported by "
452572ff6f6SMatthew Dillon "this driver\n",
453572ff6f6SMatthew Dillon __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
454572ff6f6SMatthew Dillon ecode = HAL_ENOTSUPP;
455572ff6f6SMatthew Dillon goto bad;
456572ff6f6SMatthew Dillon #endif
457572ff6f6SMatthew Dillon }
458572ff6f6SMatthew Dillon if (IS_RAD5112_REV1(ah)) {
459572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
460572ff6f6SMatthew Dillon "%s: 5112 Rev 1 is not supported by this "
461572ff6f6SMatthew Dillon "driver (analog5GhzRev 0x%x)\n", __func__,
462572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev);
463572ff6f6SMatthew Dillon ecode = HAL_ENOTSUPP;
464572ff6f6SMatthew Dillon goto bad;
465572ff6f6SMatthew Dillon }
466572ff6f6SMatthew Dillon
467572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_PCICFG);
468572ff6f6SMatthew Dillon val = MS(val, AR_PCICFG_EEPROM_SIZE);
469572ff6f6SMatthew Dillon if (val == 0) {
470572ff6f6SMatthew Dillon if (!AH_PRIVATE(ah)->ah_ispcie) {
471572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
472572ff6f6SMatthew Dillon "%s: unsupported EEPROM size %u (0x%x) found\n",
473572ff6f6SMatthew Dillon __func__, val, val);
474572ff6f6SMatthew Dillon ecode = HAL_EESIZE;
475572ff6f6SMatthew Dillon goto bad;
476572ff6f6SMatthew Dillon }
477572ff6f6SMatthew Dillon /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
478572ff6f6SMatthew Dillon } else if (val != AR_PCICFG_EEPROM_SIZE_16K) {
479572ff6f6SMatthew Dillon if (AR_PCICFG_EEPROM_SIZE_FAILED == val) {
480572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
481572ff6f6SMatthew Dillon "%s: unsupported EEPROM size %u (0x%x) found\n",
482572ff6f6SMatthew Dillon __func__, val, val);
483572ff6f6SMatthew Dillon ecode = HAL_EESIZE;
484572ff6f6SMatthew Dillon goto bad;
485572ff6f6SMatthew Dillon }
486572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
487572ff6f6SMatthew Dillon "%s: EEPROM size = %d. Must be %d (16k).\n",
488572ff6f6SMatthew Dillon __func__, val, AR_PCICFG_EEPROM_SIZE_16K);
489572ff6f6SMatthew Dillon ecode = HAL_EESIZE;
490572ff6f6SMatthew Dillon goto bad;
491572ff6f6SMatthew Dillon }
492572ff6f6SMatthew Dillon ecode = ath_hal_legacyEepromAttach(ah);
493572ff6f6SMatthew Dillon if (ecode != HAL_OK) {
494572ff6f6SMatthew Dillon goto bad;
495572ff6f6SMatthew Dillon }
496572ff6f6SMatthew Dillon ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
497572ff6f6SMatthew Dillon
498572ff6f6SMatthew Dillon /*
499572ff6f6SMatthew Dillon * If Bmode and AR5212, verify 2.4 analog exists
500572ff6f6SMatthew Dillon */
501572ff6f6SMatthew Dillon if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
502572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
503572ff6f6SMatthew Dillon /*
504572ff6f6SMatthew Dillon * Set correct Baseband to analog shift
505572ff6f6SMatthew Dillon * setting to access analog chips.
506572ff6f6SMatthew Dillon */
507572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
508572ff6f6SMatthew Dillon OS_DELAY(2000);
509572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
510572ff6f6SMatthew Dillon
511572ff6f6SMatthew Dillon /* Set baseband for 5GHz chip */
512572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
513572ff6f6SMatthew Dillon OS_DELAY(2000);
514572ff6f6SMatthew Dillon if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
515572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
516572ff6f6SMatthew Dillon "%s: 2G Radio Chip Rev 0x%02X is not "
517572ff6f6SMatthew Dillon "supported by this driver\n", __func__,
518572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog2GhzRev);
519572ff6f6SMatthew Dillon ecode = HAL_ENOTSUPP;
520572ff6f6SMatthew Dillon goto bad;
521572ff6f6SMatthew Dillon }
522572ff6f6SMatthew Dillon }
523572ff6f6SMatthew Dillon
524572ff6f6SMatthew Dillon ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
525572ff6f6SMatthew Dillon if (ecode != HAL_OK) {
526572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
527572ff6f6SMatthew Dillon "%s: cannot read regulatory domain from EEPROM\n",
528572ff6f6SMatthew Dillon __func__);
529572ff6f6SMatthew Dillon goto bad;
530572ff6f6SMatthew Dillon }
531572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_currentRD = eeval;
532572ff6f6SMatthew Dillon /* XXX record serial number */
533572ff6f6SMatthew Dillon
534572ff6f6SMatthew Dillon /*
535572ff6f6SMatthew Dillon * Got everything we need now to setup the capabilities.
536572ff6f6SMatthew Dillon */
537572ff6f6SMatthew Dillon if (!ar5212FillCapabilityInfo(ah)) {
538572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
539572ff6f6SMatthew Dillon "%s: failed ar5212FillCapabilityInfo\n", __func__);
540572ff6f6SMatthew Dillon ecode = HAL_EEREAD;
541572ff6f6SMatthew Dillon goto bad;
542572ff6f6SMatthew Dillon }
543572ff6f6SMatthew Dillon
544572ff6f6SMatthew Dillon if (!rf->attach(ah, &ecode)) {
545572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
546572ff6f6SMatthew Dillon __func__, ecode);
547572ff6f6SMatthew Dillon goto bad;
548572ff6f6SMatthew Dillon }
549572ff6f6SMatthew Dillon /*
550572ff6f6SMatthew Dillon * Set noise floor adjust method; we arrange a
551572ff6f6SMatthew Dillon * direct call instead of thunking.
552572ff6f6SMatthew Dillon */
553572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
554572ff6f6SMatthew Dillon
555572ff6f6SMatthew Dillon /* Initialize gain ladder thermal calibration structure */
556572ff6f6SMatthew Dillon ar5212InitializeGainValues(ah);
557572ff6f6SMatthew Dillon
558572ff6f6SMatthew Dillon ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
559572ff6f6SMatthew Dillon if (ecode != HAL_OK) {
560572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
561572ff6f6SMatthew Dillon "%s: error getting mac address from EEPROM\n", __func__);
562572ff6f6SMatthew Dillon goto bad;
563572ff6f6SMatthew Dillon }
564572ff6f6SMatthew Dillon
565572ff6f6SMatthew Dillon ar5212AniSetup(ah);
566572ff6f6SMatthew Dillon /* Setup of Radar/AR structures happens in ath_hal_initchannels*/
567572ff6f6SMatthew Dillon ar5212InitNfCalHistBuffer(ah);
568572ff6f6SMatthew Dillon
569572ff6f6SMatthew Dillon /* XXX EAR stuff goes here */
570572ff6f6SMatthew Dillon
571572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
572572ff6f6SMatthew Dillon
573572ff6f6SMatthew Dillon return ah;
574572ff6f6SMatthew Dillon
575572ff6f6SMatthew Dillon bad:
576572ff6f6SMatthew Dillon if (ahp)
577572ff6f6SMatthew Dillon ar5212Detach((struct ath_hal *) ahp);
578572ff6f6SMatthew Dillon if (status)
579572ff6f6SMatthew Dillon *status = ecode;
580572ff6f6SMatthew Dillon return AH_NULL;
581572ff6f6SMatthew Dillon #undef AH_EEPROM_PROTECT
582572ff6f6SMatthew Dillon }
583572ff6f6SMatthew Dillon
584572ff6f6SMatthew Dillon void
ar5212Detach(struct ath_hal * ah)585572ff6f6SMatthew Dillon ar5212Detach(struct ath_hal *ah)
586572ff6f6SMatthew Dillon {
587572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
588572ff6f6SMatthew Dillon
589572ff6f6SMatthew Dillon HALASSERT(ah != AH_NULL);
590572ff6f6SMatthew Dillon HALASSERT(ah->ah_magic == AR5212_MAGIC);
591572ff6f6SMatthew Dillon
592572ff6f6SMatthew Dillon ar5212AniDetach(ah);
593572ff6f6SMatthew Dillon ar5212RfDetach(ah);
594572ff6f6SMatthew Dillon ar5212Disable(ah);
595572ff6f6SMatthew Dillon ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
596572ff6f6SMatthew Dillon
597572ff6f6SMatthew Dillon ath_hal_eepromDetach(ah);
598572ff6f6SMatthew Dillon ath_hal_free(ah);
599572ff6f6SMatthew Dillon }
600572ff6f6SMatthew Dillon
601572ff6f6SMatthew Dillon HAL_BOOL
ar5212ChipTest(struct ath_hal * ah)602572ff6f6SMatthew Dillon ar5212ChipTest(struct ath_hal *ah)
603572ff6f6SMatthew Dillon {
604572ff6f6SMatthew Dillon uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
605572ff6f6SMatthew Dillon uint32_t regHold[2];
606572ff6f6SMatthew Dillon uint32_t patternData[4] =
607572ff6f6SMatthew Dillon { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
608572ff6f6SMatthew Dillon int i, j;
609572ff6f6SMatthew Dillon
610572ff6f6SMatthew Dillon /* Test PHY & MAC registers */
611572ff6f6SMatthew Dillon for (i = 0; i < 2; i++) {
612572ff6f6SMatthew Dillon uint32_t addr = regAddr[i];
613572ff6f6SMatthew Dillon uint32_t wrData, rdData;
614572ff6f6SMatthew Dillon
615572ff6f6SMatthew Dillon regHold[i] = OS_REG_READ(ah, addr);
616572ff6f6SMatthew Dillon for (j = 0; j < 0x100; j++) {
617572ff6f6SMatthew Dillon wrData = (j << 16) | j;
618572ff6f6SMatthew Dillon OS_REG_WRITE(ah, addr, wrData);
619572ff6f6SMatthew Dillon rdData = OS_REG_READ(ah, addr);
620572ff6f6SMatthew Dillon if (rdData != wrData) {
621572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
622572ff6f6SMatthew Dillon "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
623572ff6f6SMatthew Dillon __func__, addr, wrData, rdData);
624572ff6f6SMatthew Dillon return AH_FALSE;
625572ff6f6SMatthew Dillon }
626572ff6f6SMatthew Dillon }
627572ff6f6SMatthew Dillon for (j = 0; j < 4; j++) {
628572ff6f6SMatthew Dillon wrData = patternData[j];
629572ff6f6SMatthew Dillon OS_REG_WRITE(ah, addr, wrData);
630572ff6f6SMatthew Dillon rdData = OS_REG_READ(ah, addr);
631572ff6f6SMatthew Dillon if (wrData != rdData) {
632572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
633572ff6f6SMatthew Dillon "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
634572ff6f6SMatthew Dillon __func__, addr, wrData, rdData);
635572ff6f6SMatthew Dillon return AH_FALSE;
636572ff6f6SMatthew Dillon }
637572ff6f6SMatthew Dillon }
638572ff6f6SMatthew Dillon OS_REG_WRITE(ah, regAddr[i], regHold[i]);
639572ff6f6SMatthew Dillon }
640572ff6f6SMatthew Dillon OS_DELAY(100);
641572ff6f6SMatthew Dillon return AH_TRUE;
642572ff6f6SMatthew Dillon }
643572ff6f6SMatthew Dillon
644572ff6f6SMatthew Dillon /*
645572ff6f6SMatthew Dillon * Store the channel edges for the requested operational mode
646572ff6f6SMatthew Dillon */
647572ff6f6SMatthew Dillon HAL_BOOL
ar5212GetChannelEdges(struct ath_hal * ah,uint16_t flags,uint16_t * low,uint16_t * high)648572ff6f6SMatthew Dillon ar5212GetChannelEdges(struct ath_hal *ah,
649572ff6f6SMatthew Dillon uint16_t flags, uint16_t *low, uint16_t *high)
650572ff6f6SMatthew Dillon {
651572ff6f6SMatthew Dillon if (flags & IEEE80211_CHAN_5GHZ) {
652572ff6f6SMatthew Dillon *low = 4915;
653572ff6f6SMatthew Dillon *high = 6100;
654572ff6f6SMatthew Dillon return AH_TRUE;
655572ff6f6SMatthew Dillon }
656572ff6f6SMatthew Dillon if ((flags & IEEE80211_CHAN_2GHZ) &&
657572ff6f6SMatthew Dillon (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
658572ff6f6SMatthew Dillon ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
659572ff6f6SMatthew Dillon *low = 2312;
660572ff6f6SMatthew Dillon *high = 2732;
661572ff6f6SMatthew Dillon return AH_TRUE;
662572ff6f6SMatthew Dillon }
663572ff6f6SMatthew Dillon return AH_FALSE;
664572ff6f6SMatthew Dillon }
665572ff6f6SMatthew Dillon
666572ff6f6SMatthew Dillon /*
667572ff6f6SMatthew Dillon * Disable PLL when in L0s as well as receiver clock when in L1.
668572ff6f6SMatthew Dillon * This power saving option must be enabled through the Serdes.
669572ff6f6SMatthew Dillon *
670572ff6f6SMatthew Dillon * Programming the Serdes must go through the same 288 bit serial shift
671572ff6f6SMatthew Dillon * register as the other analog registers. Hence the 9 writes.
672572ff6f6SMatthew Dillon *
673572ff6f6SMatthew Dillon * XXX Clean up the magic numbers.
674572ff6f6SMatthew Dillon */
675572ff6f6SMatthew Dillon static void
ar5212ConfigPCIE(struct ath_hal * ah,HAL_BOOL restore,HAL_BOOL power_off)676572ff6f6SMatthew Dillon ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
677572ff6f6SMatthew Dillon {
678572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
679572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
680572ff6f6SMatthew Dillon
681572ff6f6SMatthew Dillon /* RX shut off when elecidle is asserted */
682572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
683572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
684572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
685572ff6f6SMatthew Dillon
686572ff6f6SMatthew Dillon /* Shut off PLL and CLKREQ active in L1 */
687572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
688572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
689572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
690572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
691572ff6f6SMatthew Dillon
692572ff6f6SMatthew Dillon /* Load the new settings */
693572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
694572ff6f6SMatthew Dillon }
695572ff6f6SMatthew Dillon
696572ff6f6SMatthew Dillon static void
ar5212DisablePCIE(struct ath_hal * ah)697572ff6f6SMatthew Dillon ar5212DisablePCIE(struct ath_hal *ah)
698572ff6f6SMatthew Dillon {
699572ff6f6SMatthew Dillon /* NB: fill in for 9100 */
700572ff6f6SMatthew Dillon }
701572ff6f6SMatthew Dillon
702572ff6f6SMatthew Dillon /*
703572ff6f6SMatthew Dillon * Fill all software cached or static hardware state information.
704572ff6f6SMatthew Dillon * Return failure if capabilities are to come from EEPROM and
705572ff6f6SMatthew Dillon * cannot be read.
706572ff6f6SMatthew Dillon */
707572ff6f6SMatthew Dillon HAL_BOOL
ar5212FillCapabilityInfo(struct ath_hal * ah)708572ff6f6SMatthew Dillon ar5212FillCapabilityInfo(struct ath_hal *ah)
709572ff6f6SMatthew Dillon {
710572ff6f6SMatthew Dillon #define AR_KEYTABLE_SIZE 128
711572ff6f6SMatthew Dillon #define IS_GRIFFIN_LITE(ah) \
712572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
713572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
714572ff6f6SMatthew Dillon #define IS_COBRA(ah) \
715572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
716572ff6f6SMatthew Dillon #define IS_2112(ah) \
717572ff6f6SMatthew Dillon ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
718572ff6f6SMatthew Dillon
719572ff6f6SMatthew Dillon struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
720572ff6f6SMatthew Dillon HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
721572ff6f6SMatthew Dillon uint16_t capField, val;
722572ff6f6SMatthew Dillon
723572ff6f6SMatthew Dillon /* Read the capability EEPROM location */
724572ff6f6SMatthew Dillon if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
725572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
726572ff6f6SMatthew Dillon "%s: unable to read caps from eeprom\n", __func__);
727572ff6f6SMatthew Dillon return AH_FALSE;
728572ff6f6SMatthew Dillon }
729572ff6f6SMatthew Dillon if (IS_2112(ah))
730572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
731572ff6f6SMatthew Dillon if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
732572ff6f6SMatthew Dillon /*
733572ff6f6SMatthew Dillon * For griffin-lite cards with unprogrammed capabilities.
734572ff6f6SMatthew Dillon */
735572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
736572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
737572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
738572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
739572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ATTACH,
740572ff6f6SMatthew Dillon "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n",
741572ff6f6SMatthew Dillon __func__, capField);
742572ff6f6SMatthew Dillon }
743572ff6f6SMatthew Dillon
744572ff6f6SMatthew Dillon /* Modify reg domain on newer cards that need to work with older sw */
745572ff6f6SMatthew Dillon if (ahpriv->ah_opmode != HAL_M_HOSTAP &&
746572ff6f6SMatthew Dillon ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
747572ff6f6SMatthew Dillon if (ahpriv->ah_currentRD == 0x64 ||
748572ff6f6SMatthew Dillon ahpriv->ah_currentRD == 0x65)
749572ff6f6SMatthew Dillon ahpriv->ah_currentRD += 5;
750572ff6f6SMatthew Dillon else if (ahpriv->ah_currentRD == 0x41)
751572ff6f6SMatthew Dillon ahpriv->ah_currentRD = 0x43;
752572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
753572ff6f6SMatthew Dillon __func__, ahpriv->ah_currentRD);
754572ff6f6SMatthew Dillon }
755572ff6f6SMatthew Dillon
756572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
757572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
758572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ATTACH,
759572ff6f6SMatthew Dillon "%s: enable Bmode and disable turbo for Swan/Nala\n",
760572ff6f6SMatthew Dillon __func__);
761572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
762572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
763572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
764572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
765572ff6f6SMatthew Dillon ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
766572ff6f6SMatthew Dillon }
767572ff6f6SMatthew Dillon
768572ff6f6SMatthew Dillon /* Construct wireless mode from EEPROM */
769572ff6f6SMatthew Dillon pCap->halWirelessModes = 0;
770572ff6f6SMatthew Dillon if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
771572ff6f6SMatthew Dillon pCap->halWirelessModes |= HAL_MODE_11A;
772572ff6f6SMatthew Dillon if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
773572ff6f6SMatthew Dillon pCap->halWirelessModes |= HAL_MODE_TURBO;
774572ff6f6SMatthew Dillon }
775572ff6f6SMatthew Dillon if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
776572ff6f6SMatthew Dillon pCap->halWirelessModes |= HAL_MODE_11B;
777572ff6f6SMatthew Dillon if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
778572ff6f6SMatthew Dillon ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
779572ff6f6SMatthew Dillon pCap->halWirelessModes |= HAL_MODE_11G;
780572ff6f6SMatthew Dillon if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
781572ff6f6SMatthew Dillon pCap->halWirelessModes |= HAL_MODE_108G;
782572ff6f6SMatthew Dillon }
783572ff6f6SMatthew Dillon
784572ff6f6SMatthew Dillon pCap->halLow2GhzChan = 2312;
785572ff6f6SMatthew Dillon /* XXX 2417 too? */
786572ff6f6SMatthew Dillon if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))
787572ff6f6SMatthew Dillon pCap->halHigh2GhzChan = 2500;
788572ff6f6SMatthew Dillon else
789572ff6f6SMatthew Dillon pCap->halHigh2GhzChan = 2732;
790572ff6f6SMatthew Dillon
791572ff6f6SMatthew Dillon /*
792572ff6f6SMatthew Dillon * For AR5111 version < 4, the lowest centre frequency supported is
793572ff6f6SMatthew Dillon * 5130MHz. For AR5111 version 4, the 4.9GHz channels are supported
794572ff6f6SMatthew Dillon * but only in 10MHz increments.
795572ff6f6SMatthew Dillon *
796572ff6f6SMatthew Dillon * In addition, the programming method is wrong - it uses the IEEE
797572ff6f6SMatthew Dillon * channel number to calculate the frequency, rather than the
798572ff6f6SMatthew Dillon * channel centre. Since half/quarter rates re-use some of the
799572ff6f6SMatthew Dillon * 5GHz channel IEEE numbers, this will result in a badly programmed
800572ff6f6SMatthew Dillon * synth.
801572ff6f6SMatthew Dillon *
802572ff6f6SMatthew Dillon * Until the relevant support is written, just limit lower frequency
803572ff6f6SMatthew Dillon * support for AR5111 so things aren't incorrectly programmed.
804572ff6f6SMatthew Dillon *
805572ff6f6SMatthew Dillon * XXX It's also possible this code doesn't correctly limit the
806572ff6f6SMatthew Dillon * centre frequencies of potential channels; this is very important
807572ff6f6SMatthew Dillon * for half/quarter rate!
808572ff6f6SMatthew Dillon */
809572ff6f6SMatthew Dillon if (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR) {
810572ff6f6SMatthew Dillon pCap->halLow5GhzChan = 5120; /* XXX lowest centre = 5130MHz */
811572ff6f6SMatthew Dillon } else {
812572ff6f6SMatthew Dillon pCap->halLow5GhzChan = 4915;
813572ff6f6SMatthew Dillon }
814572ff6f6SMatthew Dillon pCap->halHigh5GhzChan = 6100;
815572ff6f6SMatthew Dillon
816572ff6f6SMatthew Dillon pCap->halCipherCkipSupport = AH_FALSE;
817572ff6f6SMatthew Dillon pCap->halCipherTkipSupport = AH_TRUE;
818572ff6f6SMatthew Dillon pCap->halCipherAesCcmSupport =
819572ff6f6SMatthew Dillon (ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
820572ff6f6SMatthew Dillon ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
821572ff6f6SMatthew Dillon ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
822572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
823572ff6f6SMatthew Dillon
824572ff6f6SMatthew Dillon pCap->halMicCkipSupport = AH_FALSE;
825572ff6f6SMatthew Dillon pCap->halMicTkipSupport = AH_TRUE;
826572ff6f6SMatthew Dillon pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
827572ff6f6SMatthew Dillon /*
828572ff6f6SMatthew Dillon * Starting with Griffin TX+RX mic keys can be combined
829572ff6f6SMatthew Dillon * in one key cache slot.
830572ff6f6SMatthew Dillon */
831572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
832572ff6f6SMatthew Dillon pCap->halTkipMicTxRxKeySupport = AH_TRUE;
833572ff6f6SMatthew Dillon else
834572ff6f6SMatthew Dillon pCap->halTkipMicTxRxKeySupport = AH_FALSE;
835572ff6f6SMatthew Dillon pCap->halChanSpreadSupport = AH_TRUE;
836572ff6f6SMatthew Dillon pCap->halSleepAfterBeaconBroken = AH_TRUE;
837572ff6f6SMatthew Dillon
838572ff6f6SMatthew Dillon if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
839572ff6f6SMatthew Dillon pCap->halCompressSupport =
840572ff6f6SMatthew Dillon ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
841572ff6f6SMatthew Dillon (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
842572ff6f6SMatthew Dillon pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
843572ff6f6SMatthew Dillon pCap->halFastFramesSupport =
844572ff6f6SMatthew Dillon ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
845572ff6f6SMatthew Dillon (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
846572ff6f6SMatthew Dillon pCap->halChapTuningSupport = AH_TRUE;
847572ff6f6SMatthew Dillon pCap->halTurboPrimeSupport = AH_TRUE;
848572ff6f6SMatthew Dillon }
849572ff6f6SMatthew Dillon pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
850572ff6f6SMatthew Dillon
851572ff6f6SMatthew Dillon pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
852572ff6f6SMatthew Dillon pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */
853572ff6f6SMatthew Dillon pCap->halNumTxMaps = 1; /* Single TX ptr per descr */
854572ff6f6SMatthew Dillon pCap->halVEOLSupport = AH_TRUE;
855572ff6f6SMatthew Dillon pCap->halBssIdMaskSupport = AH_TRUE;
856572ff6f6SMatthew Dillon pCap->halMcastKeySrchSupport = AH_TRUE;
857572ff6f6SMatthew Dillon if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE &&
858572ff6f6SMatthew Dillon ahpriv->ah_macRev == 8) ||
859572ff6f6SMatthew Dillon ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE)
860572ff6f6SMatthew Dillon pCap->halTsfAddSupport = AH_TRUE;
861572ff6f6SMatthew Dillon
862572ff6f6SMatthew Dillon if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
863572ff6f6SMatthew Dillon pCap->halTotalQueues = val;
864572ff6f6SMatthew Dillon else
865572ff6f6SMatthew Dillon pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
866572ff6f6SMatthew Dillon
867572ff6f6SMatthew Dillon if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
868572ff6f6SMatthew Dillon pCap->halKeyCacheSize = val;
869572ff6f6SMatthew Dillon else
870572ff6f6SMatthew Dillon pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
871572ff6f6SMatthew Dillon
872572ff6f6SMatthew Dillon pCap->halChanHalfRate = AH_TRUE;
873572ff6f6SMatthew Dillon pCap->halChanQuarterRate = AH_TRUE;
874572ff6f6SMatthew Dillon
875572ff6f6SMatthew Dillon /*
876572ff6f6SMatthew Dillon * RSSI uses the combined field; some 11n NICs may use
877572ff6f6SMatthew Dillon * the control chain RSSI.
878572ff6f6SMatthew Dillon */
879572ff6f6SMatthew Dillon pCap->halUseCombinedRadarRssi = AH_TRUE;
880572ff6f6SMatthew Dillon
881572ff6f6SMatthew Dillon if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
882572ff6f6SMatthew Dillon ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
883572ff6f6SMatthew Dillon /* NB: enabled by default */
884572ff6f6SMatthew Dillon ahpriv->ah_rfkillEnabled = AH_TRUE;
885572ff6f6SMatthew Dillon pCap->halRfSilentSupport = AH_TRUE;
886572ff6f6SMatthew Dillon }
887572ff6f6SMatthew Dillon
888572ff6f6SMatthew Dillon /* NB: this is a guess, no one seems to know the answer */
889572ff6f6SMatthew Dillon ahpriv->ah_rxornIsFatal =
890572ff6f6SMatthew Dillon (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
891572ff6f6SMatthew Dillon
892572ff6f6SMatthew Dillon /* enable features that first appeared in Hainan */
893572ff6f6SMatthew Dillon if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
894572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
895572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {
896572ff6f6SMatthew Dillon /* h/w phy counters */
897572ff6f6SMatthew Dillon pCap->halHwPhyCounterSupport = AH_TRUE;
898572ff6f6SMatthew Dillon /* bssid match disable */
899572ff6f6SMatthew Dillon pCap->halBssidMatchSupport = AH_TRUE;
900572ff6f6SMatthew Dillon }
901572ff6f6SMatthew Dillon
902572ff6f6SMatthew Dillon pCap->halTstampPrecision = 15;
903572ff6f6SMatthew Dillon pCap->halIntrMask = HAL_INT_COMMON
904572ff6f6SMatthew Dillon | HAL_INT_RX
905572ff6f6SMatthew Dillon | HAL_INT_TX
906572ff6f6SMatthew Dillon | HAL_INT_FATAL
907572ff6f6SMatthew Dillon | HAL_INT_BNR
908572ff6f6SMatthew Dillon | HAL_INT_BMISC
909572ff6f6SMatthew Dillon ;
910572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
911572ff6f6SMatthew Dillon pCap->halIntrMask &= ~HAL_INT_TBTT;
912572ff6f6SMatthew Dillon
913572ff6f6SMatthew Dillon pCap->hal4kbSplitTransSupport = AH_TRUE;
914572ff6f6SMatthew Dillon pCap->halHasRxSelfLinkedTail = AH_TRUE;
915572ff6f6SMatthew Dillon
916572ff6f6SMatthew Dillon return AH_TRUE;
917572ff6f6SMatthew Dillon #undef IS_COBRA
918572ff6f6SMatthew Dillon #undef IS_GRIFFIN_LITE
919572ff6f6SMatthew Dillon #undef AR_KEYTABLE_SIZE
920572ff6f6SMatthew Dillon }
921572ff6f6SMatthew Dillon
922572ff6f6SMatthew Dillon static const char*
ar5212Probe(uint16_t vendorid,uint16_t devid)923572ff6f6SMatthew Dillon ar5212Probe(uint16_t vendorid, uint16_t devid)
924572ff6f6SMatthew Dillon {
925572ff6f6SMatthew Dillon if (vendorid == ATHEROS_VENDOR_ID ||
926572ff6f6SMatthew Dillon vendorid == ATHEROS_3COM_VENDOR_ID ||
927572ff6f6SMatthew Dillon vendorid == ATHEROS_3COM2_VENDOR_ID) {
928572ff6f6SMatthew Dillon switch (devid) {
929572ff6f6SMatthew Dillon case AR5212_FPGA:
930572ff6f6SMatthew Dillon return "Atheros 5212 (FPGA)";
931572ff6f6SMatthew Dillon case AR5212_DEVID:
932572ff6f6SMatthew Dillon case AR5212_DEVID_IBM:
933572ff6f6SMatthew Dillon case AR5212_DEFAULT:
934572ff6f6SMatthew Dillon return "Atheros 5212";
935572ff6f6SMatthew Dillon case AR5212_AR2413:
936572ff6f6SMatthew Dillon return "Atheros 2413";
937572ff6f6SMatthew Dillon case AR5212_AR2417:
938572ff6f6SMatthew Dillon return "Atheros 2417";
939572ff6f6SMatthew Dillon case AR5212_AR5413:
940572ff6f6SMatthew Dillon return "Atheros 5413";
941572ff6f6SMatthew Dillon case AR5212_AR5424:
942572ff6f6SMatthew Dillon return "Atheros 5424/2424";
943572ff6f6SMatthew Dillon }
944572ff6f6SMatthew Dillon }
945572ff6f6SMatthew Dillon return AH_NULL;
946572ff6f6SMatthew Dillon }
947572ff6f6SMatthew Dillon AH_CHIP(AR5212, ar5212Probe, ar5212Attach);
948