1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5212/ar5212.h" 25 #include "ar5212/ar5212reg.h" 26 #include "ar5212/ar5212phy.h" 27 28 29 /* 30 * Checks to see if an interrupt is pending on our NIC 31 * 32 * Returns: TRUE if an interrupt is pending 33 * FALSE if not 34 */ 35 HAL_BOOL 36 ar5212IsInterruptPending(struct ath_hal *ah) 37 { 38 /* 39 * Some platforms trigger our ISR before applying power to 40 * the card, so make sure the INTPEND is really 1, not 0xffffffff. 41 */ 42 return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE); 43 } 44 45 /* 46 * Reads the Interrupt Status Register value from the NIC, thus deasserting 47 * the interrupt line, and returns both the masked and unmasked mapped ISR 48 * values. The value returned is mapped to abstract the hw-specific bit 49 * locations in the Interrupt Status Register. 50 * 51 * Returns: A hardware-abstracted bitmap of all non-masked-out 52 * interrupts pending, as well as an unmasked value 53 */ 54 HAL_BOOL 55 ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 56 { 57 uint32_t isr, isr0, isr1; 58 uint32_t mask2; 59 struct ath_hal_5212 *ahp = AH5212(ah); 60 61 isr = OS_REG_READ(ah, AR_ISR); 62 mask2 = 0; 63 if (isr & AR_ISR_BCNMISC) { 64 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 65 if (isr2 & AR_ISR_S2_TIM) 66 mask2 |= HAL_INT_TIM; 67 if (isr2 & AR_ISR_S2_DTIM) 68 mask2 |= HAL_INT_DTIM; 69 if (isr2 & AR_ISR_S2_DTIMSYNC) 70 mask2 |= HAL_INT_DTIMSYNC; 71 if (isr2 & AR_ISR_S2_CABEND) 72 mask2 |= HAL_INT_CABEND; 73 if (isr2 & AR_ISR_S2_TBTT) 74 mask2 |= HAL_INT_TBTT; 75 } 76 isr = OS_REG_READ(ah, AR_ISR_RAC); 77 if (isr == 0xffffffff) { 78 *masked = 0; 79 return AH_FALSE; 80 } 81 82 *masked = isr & HAL_INT_COMMON; 83 84 if (isr & AR_ISR_HIUERR) 85 *masked |= HAL_INT_FATAL; 86 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 87 *masked |= HAL_INT_RX; 88 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { 89 *masked |= HAL_INT_TX; 90 isr0 = OS_REG_READ(ah, AR_ISR_S0_S); 91 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 92 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 93 isr1 = OS_REG_READ(ah, AR_ISR_S1_S); 94 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 95 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 96 } 97 98 /* 99 * Receive overrun is usually non-fatal on Oahu/Spirit. 100 * BUT on some parts rx could fail and the chip must be reset. 101 * So we force a hardware reset in all cases. 102 */ 103 if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) { 104 HALDEBUG(ah, HAL_DEBUG_ANY, 105 "%s: receive FIFO overrun interrupt\n", __func__); 106 *masked |= HAL_INT_FATAL; 107 } 108 *masked |= mask2; 109 110 /* 111 * On fatal errors collect ISR state for debugging. 112 */ 113 if (*masked & HAL_INT_FATAL) { 114 AH_PRIVATE(ah)->ah_fatalState[0] = isr; 115 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S); 116 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S); 117 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S); 118 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S); 119 AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S); 120 HALDEBUG(ah, HAL_DEBUG_ANY, 121 "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n", 122 __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]); 123 } 124 return AH_TRUE; 125 } 126 127 HAL_INT 128 ar5212GetInterrupts(struct ath_hal *ah) 129 { 130 return AH5212(ah)->ah_maskReg; 131 } 132 133 /* 134 * Atomically enables NIC interrupts. Interrupts are passed in 135 * via the enumerated bitmask in ints. 136 */ 137 HAL_INT 138 ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints) 139 { 140 struct ath_hal_5212 *ahp = AH5212(ah); 141 uint32_t omask = ahp->ah_maskReg; 142 uint32_t mask, mask2; 143 144 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 145 __func__, omask, ints); 146 147 if (omask & HAL_INT_GLOBAL) { 148 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 149 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 150 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */ 151 } 152 153 mask = ints & HAL_INT_COMMON; 154 mask2 = 0; 155 if (ints & HAL_INT_TX) { 156 if (ahp->ah_txOkInterruptMask) 157 mask |= AR_IMR_TXOK; 158 if (ahp->ah_txErrInterruptMask) 159 mask |= AR_IMR_TXERR; 160 if (ahp->ah_txDescInterruptMask) 161 mask |= AR_IMR_TXDESC; 162 if (ahp->ah_txEolInterruptMask) 163 mask |= AR_IMR_TXEOL; 164 } 165 if (ints & HAL_INT_RX) 166 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 167 if (ints & (HAL_INT_BMISC)) { 168 mask |= AR_IMR_BCNMISC; 169 if (ints & HAL_INT_TIM) 170 mask2 |= AR_IMR_S2_TIM; 171 if (ints & HAL_INT_DTIM) 172 mask2 |= AR_IMR_S2_DTIM; 173 if (ints & HAL_INT_DTIMSYNC) 174 mask2 |= AR_IMR_S2_DTIMSYNC; 175 if (ints & HAL_INT_CABEND) 176 mask2 |= AR_IMR_S2_CABEND; 177 if (ints & HAL_INT_TBTT) 178 mask2 |= AR_IMR_S2_TBTT; 179 } 180 if (ints & HAL_INT_FATAL) { 181 /* 182 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2 183 * so enabling HIUERR enables delivery. 184 */ 185 mask |= AR_IMR_HIUERR; 186 } 187 188 /* Write the new IMR and store off our SW copy. */ 189 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 190 OS_REG_WRITE(ah, AR_IMR, mask); 191 OS_REG_WRITE(ah, AR_IMR_S2, 192 (OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2); 193 ahp->ah_maskReg = ints; 194 195 /* Re-enable interrupts if they were enabled before. */ 196 if (ints & HAL_INT_GLOBAL) { 197 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 198 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 199 } 200 return omask; 201 } 202