1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon  * Copyright (c) 2002-2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon  *
5572ff6f6SMatthew Dillon  * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon  * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon  * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon  *
9572ff6f6SMatthew Dillon  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon  *
17572ff6f6SMatthew Dillon  * $FreeBSD$
18572ff6f6SMatthew Dillon  */
19572ff6f6SMatthew Dillon #include "opt_ah.h"
20572ff6f6SMatthew Dillon 
21572ff6f6SMatthew Dillon #include "ah.h"
22572ff6f6SMatthew Dillon #include "ah_internal.h"
23572ff6f6SMatthew Dillon 
24572ff6f6SMatthew Dillon #include "ar5416/ar5416.h"
25572ff6f6SMatthew Dillon #include "ar5416/ar5416reg.h"
26572ff6f6SMatthew Dillon #include "ar5416/ar5416phy.h"
27572ff6f6SMatthew Dillon 
28572ff6f6SMatthew Dillon #define TU_TO_USEC(_tu)		((_tu) << 10)
29572ff6f6SMatthew Dillon #define	ONE_EIGHTH_TU_TO_USEC(_tu8)	((_tu8) << 7)
30572ff6f6SMatthew Dillon 
31572ff6f6SMatthew Dillon /*
32572ff6f6SMatthew Dillon  * Return the hardware NextTBTT in TSF
33572ff6f6SMatthew Dillon  */
34572ff6f6SMatthew Dillon uint64_t
ar5416GetNextTBTT(struct ath_hal * ah)35572ff6f6SMatthew Dillon ar5416GetNextTBTT(struct ath_hal *ah)
36572ff6f6SMatthew Dillon {
37572ff6f6SMatthew Dillon 	return OS_REG_READ(ah, AR_NEXT_TBTT);
38572ff6f6SMatthew Dillon }
39572ff6f6SMatthew Dillon 
40572ff6f6SMatthew Dillon /*
41572ff6f6SMatthew Dillon  * Initialize all of the hardware registers used to
42572ff6f6SMatthew Dillon  * send beacons.  Note that for station operation the
43572ff6f6SMatthew Dillon  * driver calls ar5416SetStaBeaconTimers instead.
44572ff6f6SMatthew Dillon  */
45572ff6f6SMatthew Dillon void
ar5416SetBeaconTimers(struct ath_hal * ah,const HAL_BEACON_TIMERS * bt)46572ff6f6SMatthew Dillon ar5416SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
47572ff6f6SMatthew Dillon {
48572ff6f6SMatthew Dillon 	uint32_t bperiod;
49572ff6f6SMatthew Dillon 	struct ath_hal_5212 *ahp = AH5212(ah);
50572ff6f6SMatthew Dillon 
51572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bt->bt_nexttbtt));
52572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NEXT_DBA, ONE_EIGHTH_TU_TO_USEC(bt->bt_nextdba));
53572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NEXT_SWBA, ONE_EIGHTH_TU_TO_USEC(bt->bt_nextswba));
54572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NEXT_NDP, TU_TO_USEC(bt->bt_nextatim));
55572ff6f6SMatthew Dillon 
56572ff6f6SMatthew Dillon 	bperiod = TU_TO_USEC(bt->bt_intval & HAL_BEACON_PERIOD);
57572ff6f6SMatthew Dillon 	ahp->ah_beaconInterval = bt->bt_intval & HAL_BEACON_PERIOD;
58572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, bperiod);
59572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_DBA_PERIOD, bperiod);
60572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod);
61572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod);
62572ff6f6SMatthew Dillon 
63572ff6f6SMatthew Dillon 	/*
64572ff6f6SMatthew Dillon 	 * Reset TSF if required.
65572ff6f6SMatthew Dillon 	 */
66572ff6f6SMatthew Dillon 	if (bt->bt_intval & AR_BEACON_RESET_TSF)
67572ff6f6SMatthew Dillon 		ar5416ResetTsf(ah);
68572ff6f6SMatthew Dillon 
69572ff6f6SMatthew Dillon 	/* enable timers */
70572ff6f6SMatthew Dillon 	/* NB: flags == 0 handled specially for backwards compatibility */
71572ff6f6SMatthew Dillon 	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
72572ff6f6SMatthew Dillon 	    bt->bt_flags != 0 ? bt->bt_flags :
73572ff6f6SMatthew Dillon 		AR_TIMER_MODE_TBTT | AR_TIMER_MODE_DBA | AR_TIMER_MODE_SWBA);
74572ff6f6SMatthew Dillon }
75572ff6f6SMatthew Dillon 
76572ff6f6SMatthew Dillon /*
77572ff6f6SMatthew Dillon  * Initializes all of the hardware registers used to
78572ff6f6SMatthew Dillon  * send beacons.  Note that for station operation the
79572ff6f6SMatthew Dillon  * driver calls ar5212SetStaBeaconTimers instead.
80572ff6f6SMatthew Dillon  */
81572ff6f6SMatthew Dillon void
ar5416BeaconInit(struct ath_hal * ah,uint32_t next_beacon,uint32_t beacon_period)82572ff6f6SMatthew Dillon ar5416BeaconInit(struct ath_hal *ah,
83572ff6f6SMatthew Dillon 	uint32_t next_beacon, uint32_t beacon_period)
84572ff6f6SMatthew Dillon {
85572ff6f6SMatthew Dillon 	HAL_BEACON_TIMERS bt;
86572ff6f6SMatthew Dillon 
87*57e09377SMatthew Dillon 	bzero(&bt, sizeof(bt));	/* avoid gcc warnings */
88572ff6f6SMatthew Dillon 	bt.bt_nexttbtt = next_beacon;
89572ff6f6SMatthew Dillon 	/*
90572ff6f6SMatthew Dillon 	 * TIMER1: in AP/adhoc mode this controls the DMA beacon
91572ff6f6SMatthew Dillon 	 * alert timer; otherwise it controls the next wakeup time.
92572ff6f6SMatthew Dillon 	 * TIMER2: in AP mode, it controls the SBA beacon alert
93572ff6f6SMatthew Dillon 	 * interrupt; otherwise it sets the start of the next CFP.
94572ff6f6SMatthew Dillon 	 */
95572ff6f6SMatthew Dillon 	bt.bt_flags = 0;
96572ff6f6SMatthew Dillon 	switch (AH_PRIVATE(ah)->ah_opmode) {
97572ff6f6SMatthew Dillon 	case HAL_M_STA:
98572ff6f6SMatthew Dillon 	case HAL_M_MONITOR:
99572ff6f6SMatthew Dillon 		bt.bt_nextdba = 0xffff;
100572ff6f6SMatthew Dillon 		bt.bt_nextswba = 0x7ffff;
101572ff6f6SMatthew Dillon 		bt.bt_flags |= AR_TIMER_MODE_TBTT;
102572ff6f6SMatthew Dillon 		break;
103572ff6f6SMatthew Dillon 	case HAL_M_IBSS:
104572ff6f6SMatthew Dillon 		OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ATIM_TXPOLICY);
105572ff6f6SMatthew Dillon 		bt.bt_flags |= AR_TIMER_MODE_NDP;
106572ff6f6SMatthew Dillon 		/* fall thru... */
107572ff6f6SMatthew Dillon 	case HAL_M_HOSTAP:
108572ff6f6SMatthew Dillon 		bt.bt_nextdba = (next_beacon -
109572ff6f6SMatthew Dillon 		    ah->ah_config.ah_dma_beacon_response_time) << 3;	/* 1/8 TU */
110572ff6f6SMatthew Dillon 		bt.bt_nextswba = (next_beacon -
111572ff6f6SMatthew Dillon 		    ah->ah_config.ah_sw_beacon_response_time) << 3;	/* 1/8 TU */
112572ff6f6SMatthew Dillon 		bt.bt_flags |= AR_TIMER_MODE_TBTT
113572ff6f6SMatthew Dillon 			    |  AR_TIMER_MODE_DBA
114572ff6f6SMatthew Dillon 			    |  AR_TIMER_MODE_SWBA;
115572ff6f6SMatthew Dillon 		break;
116572ff6f6SMatthew Dillon 	}
117572ff6f6SMatthew Dillon 	/*
118572ff6f6SMatthew Dillon 	 * Set the ATIM window
119572ff6f6SMatthew Dillon 	 * Our hardware does not support an ATIM window of 0
120572ff6f6SMatthew Dillon 	 * (beacons will not work).  If the ATIM windows is 0,
121572ff6f6SMatthew Dillon 	 * force it to 1.
122572ff6f6SMatthew Dillon 	 */
123572ff6f6SMatthew Dillon 	bt.bt_nextatim = next_beacon + 1;
124572ff6f6SMatthew Dillon 	bt.bt_intval = beacon_period &
125572ff6f6SMatthew Dillon 		(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
126572ff6f6SMatthew Dillon 	ar5416SetBeaconTimers(ah, &bt);
127572ff6f6SMatthew Dillon }
128572ff6f6SMatthew Dillon 
129572ff6f6SMatthew Dillon #define AR_BEACON_PERIOD_MAX	0xffff
130572ff6f6SMatthew Dillon 
131572ff6f6SMatthew Dillon void
ar5416ResetStaBeaconTimers(struct ath_hal * ah)132572ff6f6SMatthew Dillon ar5416ResetStaBeaconTimers(struct ath_hal *ah)
133572ff6f6SMatthew Dillon {
134572ff6f6SMatthew Dillon 	uint32_t val;
135572ff6f6SMatthew Dillon 
136572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NEXT_TBTT, 0);		/* no beacons */
137572ff6f6SMatthew Dillon 	val = OS_REG_READ(ah, AR_STA_ID1);
138572ff6f6SMatthew Dillon 	val |= AR_STA_ID1_PWR_SAV;		/* XXX */
139572ff6f6SMatthew Dillon 	/* tell the h/w that the associated AP is not PCF capable */
140572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_STA_ID1,
141572ff6f6SMatthew Dillon 		val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
142572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, AR_BEACON_PERIOD_MAX);
143572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_DBA_PERIOD, AR_BEACON_PERIOD_MAX);
144572ff6f6SMatthew Dillon }
145572ff6f6SMatthew Dillon 
146572ff6f6SMatthew Dillon /*
147572ff6f6SMatthew Dillon  * Set all the beacon related bits on the h/w for stations
148572ff6f6SMatthew Dillon  * i.e. initializes the corresponding h/w timers;
149572ff6f6SMatthew Dillon  * also tells the h/w whether to anticipate PCF beacons
150572ff6f6SMatthew Dillon  */
151572ff6f6SMatthew Dillon void
ar5416SetStaBeaconTimers(struct ath_hal * ah,const HAL_BEACON_STATE * bs)152572ff6f6SMatthew Dillon ar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
153572ff6f6SMatthew Dillon {
154572ff6f6SMatthew Dillon 	uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
155572ff6f6SMatthew Dillon 
156572ff6f6SMatthew Dillon 	HALASSERT(bs->bs_intval != 0);
157572ff6f6SMatthew Dillon 
158572ff6f6SMatthew Dillon 	/* NB: no cfp setting since h/w automatically takes care */
159572ff6f6SMatthew Dillon 
160572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bs->bs_nexttbtt));
161572ff6f6SMatthew Dillon 
162572ff6f6SMatthew Dillon 	/*
163572ff6f6SMatthew Dillon 	 * Start the beacon timers by setting the BEACON register
164572ff6f6SMatthew Dillon 	 * to the beacon interval; no need to write tim offset since
165572ff6f6SMatthew Dillon 	 * h/w parses IEs.
166572ff6f6SMatthew Dillon 	 */
167572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD,
168572ff6f6SMatthew Dillon 			 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
169572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_DBA_PERIOD,
170572ff6f6SMatthew Dillon 			 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
171572ff6f6SMatthew Dillon 
172572ff6f6SMatthew Dillon 	/*
173572ff6f6SMatthew Dillon 	 * Configure the BMISS interrupt.  Note that we
174572ff6f6SMatthew Dillon 	 * assume the caller blocks interrupts while enabling
175572ff6f6SMatthew Dillon 	 * the threshold.
176572ff6f6SMatthew Dillon 	 */
177572ff6f6SMatthew Dillon 	HALASSERT(bs->bs_bmissthreshold <=
178572ff6f6SMatthew Dillon 		(AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S));
179572ff6f6SMatthew Dillon 	OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
180572ff6f6SMatthew Dillon 		AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
181572ff6f6SMatthew Dillon 
182572ff6f6SMatthew Dillon 	/*
183572ff6f6SMatthew Dillon 	 * Program the sleep registers to correlate with the beacon setup.
184572ff6f6SMatthew Dillon 	 */
185572ff6f6SMatthew Dillon 
186572ff6f6SMatthew Dillon 	/*
187572ff6f6SMatthew Dillon 	 * Oahu beacons timers on the station were used for power
188572ff6f6SMatthew Dillon 	 * save operation (waking up in anticipation of a beacon)
189572ff6f6SMatthew Dillon 	 * and any CFP function; Venice does sleep/power-save timers
190572ff6f6SMatthew Dillon 	 * differently - so this is the right place to set them up;
191572ff6f6SMatthew Dillon 	 * don't think the beacon timers are used by venice sta hw
192572ff6f6SMatthew Dillon 	 * for any useful purpose anymore
193572ff6f6SMatthew Dillon 	 * Setup venice's sleep related timers
194572ff6f6SMatthew Dillon 	 * Current implementation assumes sw processing of beacons -
195572ff6f6SMatthew Dillon 	 *   assuming an interrupt is generated every beacon which
196572ff6f6SMatthew Dillon 	 *   causes the hardware to become awake until the sw tells
197572ff6f6SMatthew Dillon 	 *   it to go to sleep again; beacon timeout is to allow for
198572ff6f6SMatthew Dillon 	 *   beacon jitter; cab timeout is max time to wait for cab
199572ff6f6SMatthew Dillon 	 *   after seeing the last DTIM or MORE CAB bit
200572ff6f6SMatthew Dillon 	 */
201d98a0bcfSMatthew Dillon 
202d98a0bcfSMatthew Dillon /*
203d98a0bcfSMatthew Dillon  * I've bumped these to 30TU for now.
204d98a0bcfSMatthew Dillon  *
205d98a0bcfSMatthew Dillon  * Some APs (AR933x/AR934x?) in 2GHz especially seem to not always
206d98a0bcfSMatthew Dillon  * transmit beacon frames at exactly the right times and with it set
207d98a0bcfSMatthew Dillon  * to 10TU, the NIC starts not waking up at the right times to hear
208d98a0bcfSMatthew Dillon  * these slightly-larger-jitering beacons.  It also never recovers
209d98a0bcfSMatthew Dillon  * from that (it doesn't resync? I'm not sure.)
210d98a0bcfSMatthew Dillon  *
211d98a0bcfSMatthew Dillon  * So for now bump this to 30TU.  Ideally we'd cap this based on
212d98a0bcfSMatthew Dillon  * the beacon interval so the sum of CAB+BEACON timeouts never
213d98a0bcfSMatthew Dillon  * exceeded the beacon interval.
214d98a0bcfSMatthew Dillon  *
215d98a0bcfSMatthew Dillon  * Now, since we're doing all the math in the ath(4) driver in TU
216d98a0bcfSMatthew Dillon  * rather than TSF, we may be seeing the result of dumb rounding
217d98a0bcfSMatthew Dillon  * errors causing the jitter to actually be a much bigger problem.
218d98a0bcfSMatthew Dillon  * I'll have to investigate that with a fine tooth comb.
219d98a0bcfSMatthew Dillon  */
220572ff6f6SMatthew Dillon #define CAB_TIMEOUT_VAL     10 /* in TU */
221572ff6f6SMatthew Dillon #define BEACON_TIMEOUT_VAL  10 /* in TU */
222572ff6f6SMatthew Dillon #define SLEEP_SLOP          3  /* in TU */
223572ff6f6SMatthew Dillon 
224572ff6f6SMatthew Dillon 	/*
225572ff6f6SMatthew Dillon 	 * For max powersave mode we may want to sleep for longer than a
226572ff6f6SMatthew Dillon 	 * beacon period and not want to receive all beacons; modify the
227572ff6f6SMatthew Dillon 	 * timers accordingly; make sure to align the next TIM to the
228572ff6f6SMatthew Dillon 	 * next DTIM if we decide to wake for DTIMs only
229572ff6f6SMatthew Dillon 	 */
230572ff6f6SMatthew Dillon 	beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
231572ff6f6SMatthew Dillon 	HALASSERT(beaconintval != 0);
232572ff6f6SMatthew Dillon 	if (bs->bs_sleepduration > beaconintval) {
233572ff6f6SMatthew Dillon 		HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
234572ff6f6SMatthew Dillon 				bs->bs_sleepduration);
235572ff6f6SMatthew Dillon 		beaconintval = bs->bs_sleepduration;
236572ff6f6SMatthew Dillon 	}
237572ff6f6SMatthew Dillon 	dtimperiod = bs->bs_dtimperiod;
238572ff6f6SMatthew Dillon 	if (bs->bs_sleepduration > dtimperiod) {
239572ff6f6SMatthew Dillon 		HALASSERT(dtimperiod == 0 ||
240572ff6f6SMatthew Dillon 			roundup(bs->bs_sleepduration, dtimperiod) ==
241572ff6f6SMatthew Dillon 				bs->bs_sleepduration);
242572ff6f6SMatthew Dillon 		dtimperiod = bs->bs_sleepduration;
243572ff6f6SMatthew Dillon 	}
244572ff6f6SMatthew Dillon 	HALASSERT(beaconintval <= dtimperiod);
245572ff6f6SMatthew Dillon 	if (beaconintval == dtimperiod)
246572ff6f6SMatthew Dillon 		nextTbtt = bs->bs_nextdtim;
247572ff6f6SMatthew Dillon 	else
248572ff6f6SMatthew Dillon 		nextTbtt = bs->bs_nexttbtt;
249572ff6f6SMatthew Dillon 	nextdtim = bs->bs_nextdtim;
250572ff6f6SMatthew Dillon 
251572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NEXT_DTIM,
252572ff6f6SMatthew Dillon 		TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
253572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
254572ff6f6SMatthew Dillon 
255572ff6f6SMatthew Dillon 	/* cab timeout is now in 1/8 TU */
256572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR5416_SLEEP1,
257572ff6f6SMatthew Dillon 		SM((CAB_TIMEOUT_VAL << 3), AR5416_SLEEP1_CAB_TIMEOUT)
258572ff6f6SMatthew Dillon 		| AR5416_SLEEP1_ASSUME_DTIM);
259572ff6f6SMatthew Dillon 
260572ff6f6SMatthew Dillon 	/* XXX autosleep? Use min beacon timeout; check ath9k -adrian */
261572ff6f6SMatthew Dillon 	/* beacon timeout is now in 1/8 TU */
262572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR5416_SLEEP2,
263572ff6f6SMatthew Dillon 		SM((BEACON_TIMEOUT_VAL << 3), AR5416_SLEEP2_BEACON_TIMEOUT));
264572ff6f6SMatthew Dillon 
265572ff6f6SMatthew Dillon 	/* TIM_PERIOD and DTIM_PERIOD are now in uS. */
266572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
267572ff6f6SMatthew Dillon 	OS_REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
268572ff6f6SMatthew Dillon 
269572ff6f6SMatthew Dillon 	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
270572ff6f6SMatthew Dillon 	     AR_TIMER_MODE_TBTT | AR_TIMER_MODE_TIM | AR_TIMER_MODE_DTIM);
271d98a0bcfSMatthew Dillon 
272d98a0bcfSMatthew Dillon #define	HAL_TSFOOR_THRESHOLD	0x00004240 /* TSF OOR threshold (16k us) */
273d98a0bcfSMatthew Dillon 
274d98a0bcfSMatthew Dillon 	/* TSF out of range threshold */
275d98a0bcfSMatthew Dillon //	OS_REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
276d98a0bcfSMatthew Dillon 	OS_REG_WRITE(ah, AR_TSFOOR_THRESHOLD, HAL_TSFOOR_THRESHOLD);
277d98a0bcfSMatthew Dillon 
278572ff6f6SMatthew Dillon 	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
279572ff6f6SMatthew Dillon 	    __func__, bs->bs_nextdtim);
280572ff6f6SMatthew Dillon 	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
281572ff6f6SMatthew Dillon 	    __func__, nextTbtt);
282572ff6f6SMatthew Dillon 	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
283572ff6f6SMatthew Dillon 	    __func__, beaconintval);
284572ff6f6SMatthew Dillon 	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
285572ff6f6SMatthew Dillon 	    __func__, dtimperiod);
286572ff6f6SMatthew Dillon #undef CAB_TIMEOUT_VAL
287572ff6f6SMatthew Dillon #undef BEACON_TIMEOUT_VAL
288572ff6f6SMatthew Dillon #undef SLEEP_SLOP
289572ff6f6SMatthew Dillon }
290