1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon #include "opt_ah.h"
20572ff6f6SMatthew Dillon
21572ff6f6SMatthew Dillon #include "ah.h"
22572ff6f6SMatthew Dillon #include "ah_internal.h"
23572ff6f6SMatthew Dillon #include "ah_devid.h"
24572ff6f6SMatthew Dillon
25572ff6f6SMatthew Dillon #include "ah_eeprom_v14.h"
26572ff6f6SMatthew Dillon
27572ff6f6SMatthew Dillon #include "ar5212/ar5212.h" /* for NF cal related declarations */
28572ff6f6SMatthew Dillon
29572ff6f6SMatthew Dillon #include "ar5416/ar5416.h"
30572ff6f6SMatthew Dillon #include "ar5416/ar5416reg.h"
31572ff6f6SMatthew Dillon #include "ar5416/ar5416phy.h"
32572ff6f6SMatthew Dillon
33572ff6f6SMatthew Dillon /* Owl specific stuff */
34572ff6f6SMatthew Dillon #define NUM_NOISEFLOOR_READINGS 6 /* 3 chains * (ctl + ext) */
35572ff6f6SMatthew Dillon
36572ff6f6SMatthew Dillon static void ar5416StartNFCal(struct ath_hal *ah);
37572ff6f6SMatthew Dillon static void ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *);
38572ff6f6SMatthew Dillon static int16_t ar5416GetNf(struct ath_hal *, struct ieee80211_channel *);
39572ff6f6SMatthew Dillon
40572ff6f6SMatthew Dillon static uint16_t ar5416GetDefaultNF(struct ath_hal *ah, const struct ieee80211_channel *chan);
41572ff6f6SMatthew Dillon static void ar5416SanitizeNF(struct ath_hal *ah, int16_t *nf);
42572ff6f6SMatthew Dillon
43572ff6f6SMatthew Dillon /*
44572ff6f6SMatthew Dillon * Determine if calibration is supported by device and channel flags
45572ff6f6SMatthew Dillon */
46572ff6f6SMatthew Dillon
47572ff6f6SMatthew Dillon /*
48572ff6f6SMatthew Dillon * ADC GAIN/DC offset calibration is for calibrating two ADCs that
49572ff6f6SMatthew Dillon * are acting as one by interleaving incoming symbols. This isn't
50572ff6f6SMatthew Dillon * relevant for 2.4GHz 20MHz wide modes because, as far as I can tell,
51572ff6f6SMatthew Dillon * the secondary ADC is never enabled. It is enabled however for
52572ff6f6SMatthew Dillon * 5GHz modes.
53572ff6f6SMatthew Dillon *
54572ff6f6SMatthew Dillon * It hasn't been confirmed whether doing this calibration is needed
55572ff6f6SMatthew Dillon * at all in the above modes and/or whether it's actually harmful.
56572ff6f6SMatthew Dillon * So for now, let's leave it enabled and just remember to get
57572ff6f6SMatthew Dillon * confirmation that it needs to be clarified.
58572ff6f6SMatthew Dillon *
59572ff6f6SMatthew Dillon * See US Patent No: US 7,541,952 B1:
60572ff6f6SMatthew Dillon * " Method and Apparatus for Offset and Gain Compensation for
61572ff6f6SMatthew Dillon * Analog-to-Digital Converters."
62572ff6f6SMatthew Dillon */
63572ff6f6SMatthew Dillon static OS_INLINE HAL_BOOL
ar5416IsCalSupp(struct ath_hal * ah,const struct ieee80211_channel * chan,HAL_CAL_TYPE calType)64572ff6f6SMatthew Dillon ar5416IsCalSupp(struct ath_hal *ah, const struct ieee80211_channel *chan,
65572ff6f6SMatthew Dillon HAL_CAL_TYPE calType)
66572ff6f6SMatthew Dillon {
67572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
68572ff6f6SMatthew Dillon
69572ff6f6SMatthew Dillon switch (calType & cal->suppCals) {
70572ff6f6SMatthew Dillon case IQ_MISMATCH_CAL:
71572ff6f6SMatthew Dillon /* Run IQ Mismatch for non-CCK only */
72572ff6f6SMatthew Dillon return !IEEE80211_IS_CHAN_B(chan);
73572ff6f6SMatthew Dillon case ADC_GAIN_CAL:
74572ff6f6SMatthew Dillon case ADC_DC_CAL:
75572ff6f6SMatthew Dillon /*
76572ff6f6SMatthew Dillon * Run ADC Gain Cal for either 5ghz any or 2ghz HT40.
77572ff6f6SMatthew Dillon *
78572ff6f6SMatthew Dillon * Don't run ADC calibrations for 5ghz fast clock mode
79572ff6f6SMatthew Dillon * in HT20 - only one ADC is used.
80572ff6f6SMatthew Dillon */
81572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_HT20(chan) &&
82572ff6f6SMatthew Dillon (IS_5GHZ_FAST_CLOCK_EN(ah, chan)))
83572ff6f6SMatthew Dillon return AH_FALSE;
84572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_5GHZ(chan))
85572ff6f6SMatthew Dillon return AH_TRUE;
86572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_HT40(chan))
87572ff6f6SMatthew Dillon return AH_TRUE;
88572ff6f6SMatthew Dillon return AH_FALSE;
89572ff6f6SMatthew Dillon }
90572ff6f6SMatthew Dillon return AH_FALSE;
91572ff6f6SMatthew Dillon }
92572ff6f6SMatthew Dillon
93572ff6f6SMatthew Dillon /*
94572ff6f6SMatthew Dillon * Setup HW to collect samples used for current cal
95572ff6f6SMatthew Dillon */
96572ff6f6SMatthew Dillon static void
ar5416SetupMeasurement(struct ath_hal * ah,HAL_CAL_LIST * currCal)97572ff6f6SMatthew Dillon ar5416SetupMeasurement(struct ath_hal *ah, HAL_CAL_LIST *currCal)
98572ff6f6SMatthew Dillon {
99572ff6f6SMatthew Dillon /* Start calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
100572ff6f6SMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
101572ff6f6SMatthew Dillon AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
102572ff6f6SMatthew Dillon currCal->calData->calCountMax);
103572ff6f6SMatthew Dillon
104572ff6f6SMatthew Dillon /* Select calibration to run */
105572ff6f6SMatthew Dillon switch (currCal->calData->calType) {
106572ff6f6SMatthew Dillon case IQ_MISMATCH_CAL:
107572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
108572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
109572ff6f6SMatthew Dillon "%s: start IQ Mismatch calibration\n", __func__);
110572ff6f6SMatthew Dillon break;
111572ff6f6SMatthew Dillon case ADC_GAIN_CAL:
112572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
113572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
114572ff6f6SMatthew Dillon "%s: start ADC Gain calibration\n", __func__);
115572ff6f6SMatthew Dillon break;
116572ff6f6SMatthew Dillon case ADC_DC_CAL:
117572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
118572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
119572ff6f6SMatthew Dillon "%s: start ADC DC calibration\n", __func__);
120572ff6f6SMatthew Dillon break;
121572ff6f6SMatthew Dillon case ADC_DC_INIT_CAL:
122572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
123572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
124572ff6f6SMatthew Dillon "%s: start Init ADC DC calibration\n", __func__);
125572ff6f6SMatthew Dillon break;
126572ff6f6SMatthew Dillon }
127572ff6f6SMatthew Dillon /* Kick-off cal */
128572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL);
129572ff6f6SMatthew Dillon }
130572ff6f6SMatthew Dillon
131572ff6f6SMatthew Dillon /*
132572ff6f6SMatthew Dillon * Initialize shared data structures and prepare a cal to be run.
133572ff6f6SMatthew Dillon */
134572ff6f6SMatthew Dillon static void
ar5416ResetMeasurement(struct ath_hal * ah,HAL_CAL_LIST * currCal)135572ff6f6SMatthew Dillon ar5416ResetMeasurement(struct ath_hal *ah, HAL_CAL_LIST *currCal)
136572ff6f6SMatthew Dillon {
137572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
138572ff6f6SMatthew Dillon
139572ff6f6SMatthew Dillon /* Reset data structures shared between different calibrations */
140572ff6f6SMatthew Dillon OS_MEMZERO(cal->caldata, sizeof(cal->caldata));
141572ff6f6SMatthew Dillon cal->calSamples = 0;
142572ff6f6SMatthew Dillon
143572ff6f6SMatthew Dillon /* Setup HW for new calibration */
144572ff6f6SMatthew Dillon ar5416SetupMeasurement(ah, currCal);
145572ff6f6SMatthew Dillon
146572ff6f6SMatthew Dillon /* Change SW state to RUNNING for this calibration */
147572ff6f6SMatthew Dillon currCal->calState = CAL_RUNNING;
148572ff6f6SMatthew Dillon }
149572ff6f6SMatthew Dillon
150572ff6f6SMatthew Dillon #if 0
151572ff6f6SMatthew Dillon /*
152572ff6f6SMatthew Dillon * Run non-periodic calibrations.
153572ff6f6SMatthew Dillon */
154572ff6f6SMatthew Dillon static HAL_BOOL
155572ff6f6SMatthew Dillon ar5416RunInitCals(struct ath_hal *ah, int init_cal_count)
156572ff6f6SMatthew Dillon {
157572ff6f6SMatthew Dillon struct ath_hal_5416 *ahp = AH5416(ah);
158572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
159572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL ichan; /* XXX bogus */
160572ff6f6SMatthew Dillon HAL_CAL_LIST *curCal = ahp->ah_cal_curr;
161572ff6f6SMatthew Dillon HAL_BOOL isCalDone;
162572ff6f6SMatthew Dillon int i;
163572ff6f6SMatthew Dillon
164572ff6f6SMatthew Dillon if (curCal == AH_NULL)
165572ff6f6SMatthew Dillon return AH_FALSE;
166572ff6f6SMatthew Dillon
167572ff6f6SMatthew Dillon ichan.calValid = 0;
168572ff6f6SMatthew Dillon for (i = 0; i < init_cal_count; i++) {
169572ff6f6SMatthew Dillon /* Reset this Cal */
170572ff6f6SMatthew Dillon ar5416ResetMeasurement(ah, curCal);
171572ff6f6SMatthew Dillon /* Poll for offset calibration complete */
172572ff6f6SMatthew Dillon if (!ath_hal_wait(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
173572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
174572ff6f6SMatthew Dillon "%s: Cal %d failed to finish in 100ms.\n",
175572ff6f6SMatthew Dillon __func__, curCal->calData->calType);
176572ff6f6SMatthew Dillon /* Re-initialize list pointers for periodic cals */
177572ff6f6SMatthew Dillon cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;
178572ff6f6SMatthew Dillon return AH_FALSE;
179572ff6f6SMatthew Dillon }
180572ff6f6SMatthew Dillon /* Run this cal */
181572ff6f6SMatthew Dillon ar5416DoCalibration(ah, &ichan, ahp->ah_rxchainmask,
182572ff6f6SMatthew Dillon curCal, &isCalDone);
183572ff6f6SMatthew Dillon if (!isCalDone)
184572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
185572ff6f6SMatthew Dillon "%s: init cal %d did not complete.\n",
186572ff6f6SMatthew Dillon __func__, curCal->calData->calType);
187572ff6f6SMatthew Dillon if (curCal->calNext != AH_NULL)
188572ff6f6SMatthew Dillon curCal = curCal->calNext;
189572ff6f6SMatthew Dillon }
190572ff6f6SMatthew Dillon
191572ff6f6SMatthew Dillon /* Re-initialize list pointers for periodic cals */
192572ff6f6SMatthew Dillon cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;
193572ff6f6SMatthew Dillon return AH_TRUE;
194572ff6f6SMatthew Dillon }
195572ff6f6SMatthew Dillon #endif
196572ff6f6SMatthew Dillon
197572ff6f6SMatthew Dillon
198572ff6f6SMatthew Dillon /*
199572ff6f6SMatthew Dillon * AGC calibration for the AR5416, AR9130, AR9160, AR9280.
200572ff6f6SMatthew Dillon */
201572ff6f6SMatthew Dillon HAL_BOOL
ar5416InitCalHardware(struct ath_hal * ah,const struct ieee80211_channel * chan)202572ff6f6SMatthew Dillon ar5416InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan)
203572ff6f6SMatthew Dillon {
204572ff6f6SMatthew Dillon
205572ff6f6SMatthew Dillon if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
206572ff6f6SMatthew Dillon /* Disable ADC */
207572ff6f6SMatthew Dillon OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
208572ff6f6SMatthew Dillon AR_PHY_ADC_CTL_OFF_PWDADC);
209572ff6f6SMatthew Dillon
210572ff6f6SMatthew Dillon /* Enable Rx Filter Cal */
211572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
212572ff6f6SMatthew Dillon AR_PHY_AGC_CONTROL_FLTR_CAL);
213572ff6f6SMatthew Dillon }
214572ff6f6SMatthew Dillon
215572ff6f6SMatthew Dillon /* Calibrate the AGC */
216572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
217572ff6f6SMatthew Dillon
218572ff6f6SMatthew Dillon /* Poll for offset calibration complete */
219572ff6f6SMatthew Dillon if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
220572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
221572ff6f6SMatthew Dillon "%s: offset calibration did not complete in 1ms; "
222572ff6f6SMatthew Dillon "noisy environment?\n", __func__);
223572ff6f6SMatthew Dillon return AH_FALSE;
224572ff6f6SMatthew Dillon }
225572ff6f6SMatthew Dillon
226572ff6f6SMatthew Dillon if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
227572ff6f6SMatthew Dillon /* Enable ADC */
228572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL,
229572ff6f6SMatthew Dillon AR_PHY_ADC_CTL_OFF_PWDADC);
230572ff6f6SMatthew Dillon
231572ff6f6SMatthew Dillon /* Disable Rx Filter Cal */
232572ff6f6SMatthew Dillon OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
233572ff6f6SMatthew Dillon AR_PHY_AGC_CONTROL_FLTR_CAL);
234572ff6f6SMatthew Dillon }
235572ff6f6SMatthew Dillon
236572ff6f6SMatthew Dillon return AH_TRUE;
237572ff6f6SMatthew Dillon }
238572ff6f6SMatthew Dillon
239572ff6f6SMatthew Dillon /*
240572ff6f6SMatthew Dillon * Initialize Calibration infrastructure.
241572ff6f6SMatthew Dillon */
242572ff6f6SMatthew Dillon #define MAX_CAL_CHECK 32
243572ff6f6SMatthew Dillon HAL_BOOL
ar5416InitCal(struct ath_hal * ah,const struct ieee80211_channel * chan)244572ff6f6SMatthew Dillon ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan)
245572ff6f6SMatthew Dillon {
246572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
247572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ichan;
248572ff6f6SMatthew Dillon
249572ff6f6SMatthew Dillon ichan = ath_hal_checkchannel(ah, chan);
250572ff6f6SMatthew Dillon HALASSERT(ichan != AH_NULL);
251572ff6f6SMatthew Dillon
252572ff6f6SMatthew Dillon /* Do initial chipset-specific calibration */
253572ff6f6SMatthew Dillon if (! AH5416(ah)->ah_cal_initcal(ah, chan)) {
254572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
255572ff6f6SMatthew Dillon "%s: initial chipset calibration did "
256572ff6f6SMatthew Dillon "not complete in time; noisy environment?\n", __func__);
257572ff6f6SMatthew Dillon return AH_FALSE;
258572ff6f6SMatthew Dillon }
259572ff6f6SMatthew Dillon
260572ff6f6SMatthew Dillon /* If there's PA Cal, do it */
261572ff6f6SMatthew Dillon if (AH5416(ah)->ah_cal_pacal)
262572ff6f6SMatthew Dillon AH5416(ah)->ah_cal_pacal(ah, AH_TRUE);
263572ff6f6SMatthew Dillon
264572ff6f6SMatthew Dillon /*
265572ff6f6SMatthew Dillon * Do NF calibration after DC offset and other CALs.
266572ff6f6SMatthew Dillon * Per system engineers, noise floor value can sometimes be 20 dB
267572ff6f6SMatthew Dillon * higher than normal value if DC offset and noise floor cal are
268572ff6f6SMatthew Dillon * triggered at the same time.
269572ff6f6SMatthew Dillon */
270572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
271572ff6f6SMatthew Dillon
272572ff6f6SMatthew Dillon /*
273572ff6f6SMatthew Dillon * This may take a while to run; make sure subsequent
274572ff6f6SMatthew Dillon * calibration routines check that this has completed
275572ff6f6SMatthew Dillon * before reading the value and triggering a subsequent
276572ff6f6SMatthew Dillon * calibration.
277572ff6f6SMatthew Dillon */
278572ff6f6SMatthew Dillon
279572ff6f6SMatthew Dillon /* Initialize list pointers */
280572ff6f6SMatthew Dillon cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;
281572ff6f6SMatthew Dillon
282572ff6f6SMatthew Dillon /*
283572ff6f6SMatthew Dillon * Enable IQ, ADC Gain, ADC DC Offset Cals
284572ff6f6SMatthew Dillon */
285572ff6f6SMatthew Dillon if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah)) {
286572ff6f6SMatthew Dillon /* Setup all non-periodic, init time only calibrations */
287572ff6f6SMatthew Dillon /* XXX: Init DC Offset not working yet */
288572ff6f6SMatthew Dillon #if 0
289572ff6f6SMatthew Dillon if (ar5416IsCalSupp(ah, chan, ADC_DC_INIT_CAL)) {
290572ff6f6SMatthew Dillon INIT_CAL(&cal->adcDcCalInitData);
291572ff6f6SMatthew Dillon INSERT_CAL(cal, &cal->adcDcCalInitData);
292572ff6f6SMatthew Dillon }
293572ff6f6SMatthew Dillon /* Initialize current pointer to first element in list */
294572ff6f6SMatthew Dillon cal->cal_curr = cal->cal_list;
295572ff6f6SMatthew Dillon
296572ff6f6SMatthew Dillon if (cal->ah_cal_curr != AH_NULL && !ar5416RunInitCals(ah, 0))
297572ff6f6SMatthew Dillon return AH_FALSE;
298572ff6f6SMatthew Dillon #endif
299572ff6f6SMatthew Dillon }
300572ff6f6SMatthew Dillon
301572ff6f6SMatthew Dillon /* If Cals are supported, add them to list via INIT/INSERT_CAL */
302572ff6f6SMatthew Dillon if (ar5416IsCalSupp(ah, chan, ADC_GAIN_CAL)) {
303572ff6f6SMatthew Dillon INIT_CAL(&cal->adcGainCalData);
304572ff6f6SMatthew Dillon INSERT_CAL(cal, &cal->adcGainCalData);
305572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
306572ff6f6SMatthew Dillon "%s: enable ADC Gain Calibration.\n", __func__);
307572ff6f6SMatthew Dillon }
308572ff6f6SMatthew Dillon if (ar5416IsCalSupp(ah, chan, ADC_DC_CAL)) {
309572ff6f6SMatthew Dillon INIT_CAL(&cal->adcDcCalData);
310572ff6f6SMatthew Dillon INSERT_CAL(cal, &cal->adcDcCalData);
311572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
312572ff6f6SMatthew Dillon "%s: enable ADC DC Calibration.\n", __func__);
313572ff6f6SMatthew Dillon }
314572ff6f6SMatthew Dillon if (ar5416IsCalSupp(ah, chan, IQ_MISMATCH_CAL)) {
315572ff6f6SMatthew Dillon INIT_CAL(&cal->iqCalData);
316572ff6f6SMatthew Dillon INSERT_CAL(cal, &cal->iqCalData);
317572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
318572ff6f6SMatthew Dillon "%s: enable IQ Calibration.\n", __func__);
319572ff6f6SMatthew Dillon }
320572ff6f6SMatthew Dillon /* Initialize current pointer to first element in list */
321572ff6f6SMatthew Dillon cal->cal_curr = cal->cal_list;
322572ff6f6SMatthew Dillon
323572ff6f6SMatthew Dillon /* Kick off measurements for the first cal */
324572ff6f6SMatthew Dillon if (cal->cal_curr != AH_NULL)
325572ff6f6SMatthew Dillon ar5416ResetMeasurement(ah, cal->cal_curr);
326572ff6f6SMatthew Dillon
327572ff6f6SMatthew Dillon /* Mark all calibrations on this channel as being invalid */
328572ff6f6SMatthew Dillon ichan->calValid = 0;
329572ff6f6SMatthew Dillon
330572ff6f6SMatthew Dillon return AH_TRUE;
331572ff6f6SMatthew Dillon #undef MAX_CAL_CHECK
332572ff6f6SMatthew Dillon }
333572ff6f6SMatthew Dillon
334572ff6f6SMatthew Dillon /*
335572ff6f6SMatthew Dillon * Entry point for upper layers to restart current cal.
336572ff6f6SMatthew Dillon * Reset the calibration valid bit in channel.
337572ff6f6SMatthew Dillon */
338572ff6f6SMatthew Dillon HAL_BOOL
ar5416ResetCalValid(struct ath_hal * ah,const struct ieee80211_channel * chan)339572ff6f6SMatthew Dillon ar5416ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
340572ff6f6SMatthew Dillon {
341572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
342572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
343572ff6f6SMatthew Dillon HAL_CAL_LIST *currCal = cal->cal_curr;
344572ff6f6SMatthew Dillon
345572ff6f6SMatthew Dillon if (!AR_SREV_SOWL_10_OR_LATER(ah))
346572ff6f6SMatthew Dillon return AH_FALSE;
347572ff6f6SMatthew Dillon if (currCal == AH_NULL)
348572ff6f6SMatthew Dillon return AH_FALSE;
349572ff6f6SMatthew Dillon if (ichan == AH_NULL) {
350572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
351572ff6f6SMatthew Dillon "%s: invalid channel %u/0x%x; no mapping\n",
352572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags);
353572ff6f6SMatthew Dillon return AH_FALSE;
354572ff6f6SMatthew Dillon }
355572ff6f6SMatthew Dillon /*
356572ff6f6SMatthew Dillon * Expected that this calibration has run before, post-reset.
357572ff6f6SMatthew Dillon * Current state should be done
358572ff6f6SMatthew Dillon */
359572ff6f6SMatthew Dillon if (currCal->calState != CAL_DONE) {
360572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
361572ff6f6SMatthew Dillon "%s: Calibration state incorrect, %d\n",
362572ff6f6SMatthew Dillon __func__, currCal->calState);
363572ff6f6SMatthew Dillon return AH_FALSE;
364572ff6f6SMatthew Dillon }
365572ff6f6SMatthew Dillon
366572ff6f6SMatthew Dillon /* Verify Cal is supported on this channel */
367572ff6f6SMatthew Dillon if (!ar5416IsCalSupp(ah, chan, currCal->calData->calType))
368572ff6f6SMatthew Dillon return AH_FALSE;
369572ff6f6SMatthew Dillon
370572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
371572ff6f6SMatthew Dillon "%s: Resetting Cal %d state for channel %u/0x%x\n",
372572ff6f6SMatthew Dillon __func__, currCal->calData->calType, chan->ic_freq,
373572ff6f6SMatthew Dillon chan->ic_flags);
374572ff6f6SMatthew Dillon
375572ff6f6SMatthew Dillon /* Disable cal validity in channel */
376572ff6f6SMatthew Dillon ichan->calValid &= ~currCal->calData->calType;
377572ff6f6SMatthew Dillon currCal->calState = CAL_WAITING;
378572ff6f6SMatthew Dillon
379572ff6f6SMatthew Dillon return AH_TRUE;
380572ff6f6SMatthew Dillon }
381572ff6f6SMatthew Dillon
382572ff6f6SMatthew Dillon /*
383572ff6f6SMatthew Dillon * Recalibrate the lower PHY chips to account for temperature/environment
384572ff6f6SMatthew Dillon * changes.
385572ff6f6SMatthew Dillon */
386572ff6f6SMatthew Dillon static void
ar5416DoCalibration(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * ichan,uint8_t rxchainmask,HAL_CAL_LIST * currCal,HAL_BOOL * isCalDone)387572ff6f6SMatthew Dillon ar5416DoCalibration(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan,
388572ff6f6SMatthew Dillon uint8_t rxchainmask, HAL_CAL_LIST *currCal, HAL_BOOL *isCalDone)
389572ff6f6SMatthew Dillon {
390572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
391572ff6f6SMatthew Dillon
392572ff6f6SMatthew Dillon /* Cal is assumed not done until explicitly set below */
393572ff6f6SMatthew Dillon *isCalDone = AH_FALSE;
394572ff6f6SMatthew Dillon
395572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
396572ff6f6SMatthew Dillon "%s: %s Calibration, state %d, calValid 0x%x\n",
397572ff6f6SMatthew Dillon __func__, currCal->calData->calName, currCal->calState,
398572ff6f6SMatthew Dillon ichan->calValid);
399572ff6f6SMatthew Dillon
400572ff6f6SMatthew Dillon /* Calibration in progress. */
401572ff6f6SMatthew Dillon if (currCal->calState == CAL_RUNNING) {
402572ff6f6SMatthew Dillon /* Check to see if it has finished. */
403572ff6f6SMatthew Dillon if (!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_CAL)) {
404572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
405572ff6f6SMatthew Dillon "%s: sample %d of %d finished\n",
406572ff6f6SMatthew Dillon __func__, cal->calSamples,
407572ff6f6SMatthew Dillon currCal->calData->calNumSamples);
408572ff6f6SMatthew Dillon /*
409572ff6f6SMatthew Dillon * Collect measurements for active chains.
410572ff6f6SMatthew Dillon */
411572ff6f6SMatthew Dillon currCal->calData->calCollect(ah);
412572ff6f6SMatthew Dillon if (++cal->calSamples >= currCal->calData->calNumSamples) {
413572ff6f6SMatthew Dillon int i, numChains = 0;
414572ff6f6SMatthew Dillon for (i = 0; i < AR5416_MAX_CHAINS; i++) {
415572ff6f6SMatthew Dillon if (rxchainmask & (1 << i))
416572ff6f6SMatthew Dillon numChains++;
417572ff6f6SMatthew Dillon }
418572ff6f6SMatthew Dillon /*
419572ff6f6SMatthew Dillon * Process accumulated data
420572ff6f6SMatthew Dillon */
421572ff6f6SMatthew Dillon currCal->calData->calPostProc(ah, numChains);
422572ff6f6SMatthew Dillon
423572ff6f6SMatthew Dillon /* Calibration has finished. */
424572ff6f6SMatthew Dillon ichan->calValid |= currCal->calData->calType;
425572ff6f6SMatthew Dillon currCal->calState = CAL_DONE;
426572ff6f6SMatthew Dillon *isCalDone = AH_TRUE;
427572ff6f6SMatthew Dillon } else {
428572ff6f6SMatthew Dillon /*
429572ff6f6SMatthew Dillon * Set-up to collect of another sub-sample.
430572ff6f6SMatthew Dillon */
431572ff6f6SMatthew Dillon ar5416SetupMeasurement(ah, currCal);
432572ff6f6SMatthew Dillon }
433572ff6f6SMatthew Dillon }
434572ff6f6SMatthew Dillon } else if (!(ichan->calValid & currCal->calData->calType)) {
435572ff6f6SMatthew Dillon /* If current cal is marked invalid in channel, kick it off */
436572ff6f6SMatthew Dillon ar5416ResetMeasurement(ah, currCal);
437572ff6f6SMatthew Dillon }
438572ff6f6SMatthew Dillon }
439572ff6f6SMatthew Dillon
440572ff6f6SMatthew Dillon /*
441572ff6f6SMatthew Dillon * Internal interface to schedule periodic calibration work.
442572ff6f6SMatthew Dillon */
443572ff6f6SMatthew Dillon HAL_BOOL
ar5416PerCalibrationN(struct ath_hal * ah,struct ieee80211_channel * chan,u_int rxchainmask,HAL_BOOL longcal,HAL_BOOL * isCalDone)444572ff6f6SMatthew Dillon ar5416PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
445572ff6f6SMatthew Dillon u_int rxchainmask, HAL_BOOL longcal, HAL_BOOL *isCalDone)
446572ff6f6SMatthew Dillon {
447572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
448572ff6f6SMatthew Dillon HAL_CAL_LIST *currCal = cal->cal_curr;
449572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ichan;
450572ff6f6SMatthew Dillon int r;
451572ff6f6SMatthew Dillon
452572ff6f6SMatthew Dillon OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);
453572ff6f6SMatthew Dillon
454572ff6f6SMatthew Dillon *isCalDone = AH_TRUE;
455572ff6f6SMatthew Dillon
456572ff6f6SMatthew Dillon /*
457572ff6f6SMatthew Dillon * Since ath_hal calls the PerCal method with rxchainmask=0x1;
458572ff6f6SMatthew Dillon * override it with the current chainmask. The upper levels currently
459572ff6f6SMatthew Dillon * doesn't know about the chainmask.
460572ff6f6SMatthew Dillon */
461572ff6f6SMatthew Dillon rxchainmask = AH5416(ah)->ah_rx_chainmask;
462572ff6f6SMatthew Dillon
463572ff6f6SMatthew Dillon /* Invalid channel check */
464572ff6f6SMatthew Dillon ichan = ath_hal_checkchannel(ah, chan);
465572ff6f6SMatthew Dillon if (ichan == AH_NULL) {
466572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
467572ff6f6SMatthew Dillon "%s: invalid channel %u/0x%x; no mapping\n",
468572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags);
469572ff6f6SMatthew Dillon return AH_FALSE;
470572ff6f6SMatthew Dillon }
471572ff6f6SMatthew Dillon
472572ff6f6SMatthew Dillon /*
473572ff6f6SMatthew Dillon * For given calibration:
474572ff6f6SMatthew Dillon * 1. Call generic cal routine
475572ff6f6SMatthew Dillon * 2. When this cal is done (isCalDone) if we have more cals waiting
476572ff6f6SMatthew Dillon * (eg after reset), mask this to upper layers by not propagating
477572ff6f6SMatthew Dillon * isCalDone if it is set to TRUE.
478572ff6f6SMatthew Dillon * Instead, change isCalDone to FALSE and setup the waiting cal(s)
479572ff6f6SMatthew Dillon * to be run.
480572ff6f6SMatthew Dillon */
481572ff6f6SMatthew Dillon if (currCal != AH_NULL &&
482572ff6f6SMatthew Dillon (currCal->calState == CAL_RUNNING ||
483572ff6f6SMatthew Dillon currCal->calState == CAL_WAITING)) {
484572ff6f6SMatthew Dillon ar5416DoCalibration(ah, ichan, rxchainmask, currCal, isCalDone);
485572ff6f6SMatthew Dillon if (*isCalDone == AH_TRUE) {
486572ff6f6SMatthew Dillon cal->cal_curr = currCal = currCal->calNext;
487572ff6f6SMatthew Dillon if (currCal->calState == CAL_WAITING) {
488572ff6f6SMatthew Dillon *isCalDone = AH_FALSE;
489572ff6f6SMatthew Dillon ar5416ResetMeasurement(ah, currCal);
490572ff6f6SMatthew Dillon }
491572ff6f6SMatthew Dillon }
492572ff6f6SMatthew Dillon }
493572ff6f6SMatthew Dillon
494572ff6f6SMatthew Dillon /* Do NF cal only at longer intervals */
495572ff6f6SMatthew Dillon if (longcal) {
496572ff6f6SMatthew Dillon /* Do PA calibration if the chipset supports */
497572ff6f6SMatthew Dillon if (AH5416(ah)->ah_cal_pacal)
498572ff6f6SMatthew Dillon AH5416(ah)->ah_cal_pacal(ah, AH_FALSE);
499572ff6f6SMatthew Dillon
500572ff6f6SMatthew Dillon /* Do open-loop temperature compensation if the chipset needs it */
501572ff6f6SMatthew Dillon if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))
502572ff6f6SMatthew Dillon AH5416(ah)->ah_olcTempCompensation(ah);
503572ff6f6SMatthew Dillon
504572ff6f6SMatthew Dillon /*
505572ff6f6SMatthew Dillon * Get the value from the previous NF cal
506572ff6f6SMatthew Dillon * and update the history buffer.
507572ff6f6SMatthew Dillon */
508572ff6f6SMatthew Dillon r = ar5416GetNf(ah, chan);
509572ff6f6SMatthew Dillon if (r == 0 || r == -1) {
510572ff6f6SMatthew Dillon /* NF calibration result isn't valid */
511572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: NF calibration"
512572ff6f6SMatthew Dillon " didn't finish; delaying CCA\n", __func__);
513572ff6f6SMatthew Dillon } else {
514572ff6f6SMatthew Dillon /*
515572ff6f6SMatthew Dillon * NF calibration result is valid.
516572ff6f6SMatthew Dillon *
517572ff6f6SMatthew Dillon * Load the NF from history buffer of the current channel.
518572ff6f6SMatthew Dillon * NF is slow time-variant, so it is OK to use a
519572ff6f6SMatthew Dillon * historical value.
520572ff6f6SMatthew Dillon */
521572ff6f6SMatthew Dillon ar5416LoadNF(ah, AH_PRIVATE(ah)->ah_curchan);
522572ff6f6SMatthew Dillon
523572ff6f6SMatthew Dillon /* start NF calibration, without updating BB NF register*/
524572ff6f6SMatthew Dillon ar5416StartNFCal(ah);
525572ff6f6SMatthew Dillon }
526572ff6f6SMatthew Dillon }
527572ff6f6SMatthew Dillon return AH_TRUE;
528572ff6f6SMatthew Dillon }
529572ff6f6SMatthew Dillon
530572ff6f6SMatthew Dillon /*
531572ff6f6SMatthew Dillon * Recalibrate the lower PHY chips to account for temperature/environment
532572ff6f6SMatthew Dillon * changes.
533572ff6f6SMatthew Dillon */
534572ff6f6SMatthew Dillon HAL_BOOL
ar5416PerCalibration(struct ath_hal * ah,struct ieee80211_channel * chan,HAL_BOOL * isIQdone)535572ff6f6SMatthew Dillon ar5416PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
536572ff6f6SMatthew Dillon HAL_BOOL *isIQdone)
537572ff6f6SMatthew Dillon {
538572ff6f6SMatthew Dillon struct ath_hal_5416 *ahp = AH5416(ah);
539572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
540572ff6f6SMatthew Dillon HAL_CAL_LIST *curCal = cal->cal_curr;
541572ff6f6SMatthew Dillon
542572ff6f6SMatthew Dillon if (curCal != AH_NULL && curCal->calData->calType == IQ_MISMATCH_CAL) {
543572ff6f6SMatthew Dillon return ar5416PerCalibrationN(ah, chan, ahp->ah_rx_chainmask,
544572ff6f6SMatthew Dillon AH_TRUE, isIQdone);
545572ff6f6SMatthew Dillon } else {
546572ff6f6SMatthew Dillon HAL_BOOL isCalDone;
547572ff6f6SMatthew Dillon
548572ff6f6SMatthew Dillon *isIQdone = AH_FALSE;
549572ff6f6SMatthew Dillon return ar5416PerCalibrationN(ah, chan, ahp->ah_rx_chainmask,
550572ff6f6SMatthew Dillon AH_TRUE, &isCalDone);
551572ff6f6SMatthew Dillon }
552572ff6f6SMatthew Dillon }
553572ff6f6SMatthew Dillon
554572ff6f6SMatthew Dillon static HAL_BOOL
ar5416GetEepromNoiseFloorThresh(struct ath_hal * ah,const struct ieee80211_channel * chan,int16_t * nft)555572ff6f6SMatthew Dillon ar5416GetEepromNoiseFloorThresh(struct ath_hal *ah,
556572ff6f6SMatthew Dillon const struct ieee80211_channel *chan, int16_t *nft)
557572ff6f6SMatthew Dillon {
558572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_5GHZ(chan)) {
559572ff6f6SMatthew Dillon ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_5, nft);
560572ff6f6SMatthew Dillon return AH_TRUE;
561572ff6f6SMatthew Dillon }
562572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_2GHZ(chan)) {
563572ff6f6SMatthew Dillon ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_2, nft);
564572ff6f6SMatthew Dillon return AH_TRUE;
565572ff6f6SMatthew Dillon }
566572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
567572ff6f6SMatthew Dillon __func__, chan->ic_flags);
568572ff6f6SMatthew Dillon return AH_FALSE;
569572ff6f6SMatthew Dillon }
570572ff6f6SMatthew Dillon
571572ff6f6SMatthew Dillon static void
ar5416StartNFCal(struct ath_hal * ah)572572ff6f6SMatthew Dillon ar5416StartNFCal(struct ath_hal *ah)
573572ff6f6SMatthew Dillon {
574572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
575572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
576572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
577572ff6f6SMatthew Dillon }
578572ff6f6SMatthew Dillon
579572ff6f6SMatthew Dillon static void
ar5416LoadNF(struct ath_hal * ah,const struct ieee80211_channel * chan)580572ff6f6SMatthew Dillon ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
581572ff6f6SMatthew Dillon {
582572ff6f6SMatthew Dillon static const uint32_t ar5416_cca_regs[] = {
583572ff6f6SMatthew Dillon AR_PHY_CCA,
584572ff6f6SMatthew Dillon AR_PHY_CH1_CCA,
585572ff6f6SMatthew Dillon AR_PHY_CH2_CCA,
586572ff6f6SMatthew Dillon AR_PHY_EXT_CCA,
587572ff6f6SMatthew Dillon AR_PHY_CH1_EXT_CCA,
588572ff6f6SMatthew Dillon AR_PHY_CH2_EXT_CCA
589572ff6f6SMatthew Dillon };
590572ff6f6SMatthew Dillon struct ar5212NfCalHist *h;
591572ff6f6SMatthew Dillon int i;
592572ff6f6SMatthew Dillon int32_t val;
593572ff6f6SMatthew Dillon uint8_t chainmask;
594572ff6f6SMatthew Dillon int16_t default_nf = ar5416GetDefaultNF(ah, chan);
595572ff6f6SMatthew Dillon
596572ff6f6SMatthew Dillon /*
597572ff6f6SMatthew Dillon * Force NF calibration for all chains.
598572ff6f6SMatthew Dillon */
599572ff6f6SMatthew Dillon if (AR_SREV_KITE(ah)) {
600572ff6f6SMatthew Dillon /* Kite has only one chain */
601572ff6f6SMatthew Dillon chainmask = 0x9;
602572ff6f6SMatthew Dillon } else if (AR_SREV_MERLIN(ah) || AR_SREV_KIWI(ah)) {
603572ff6f6SMatthew Dillon /* Merlin/Kiwi has only two chains */
604572ff6f6SMatthew Dillon chainmask = 0x1B;
605572ff6f6SMatthew Dillon } else {
606572ff6f6SMatthew Dillon chainmask = 0x3F;
607572ff6f6SMatthew Dillon }
608572ff6f6SMatthew Dillon
609572ff6f6SMatthew Dillon /*
610572ff6f6SMatthew Dillon * Write filtered NF values into maxCCApwr register parameter
611572ff6f6SMatthew Dillon * so we can load below.
612572ff6f6SMatthew Dillon */
613572ff6f6SMatthew Dillon h = AH5416(ah)->ah_cal.nfCalHist;
614572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: ");
615572ff6f6SMatthew Dillon for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
616572ff6f6SMatthew Dillon
617572ff6f6SMatthew Dillon /* Don't write to EXT radio CCA registers unless in HT/40 mode */
618572ff6f6SMatthew Dillon /* XXX this check should really be cleaner! */
619572ff6f6SMatthew Dillon if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))
620572ff6f6SMatthew Dillon continue;
621572ff6f6SMatthew Dillon
622572ff6f6SMatthew Dillon if (chainmask & (1 << i)) {
623572ff6f6SMatthew Dillon int16_t nf_val;
624572ff6f6SMatthew Dillon
625572ff6f6SMatthew Dillon if (h)
626572ff6f6SMatthew Dillon nf_val = h[i].privNF;
627572ff6f6SMatthew Dillon else
628572ff6f6SMatthew Dillon nf_val = default_nf;
629572ff6f6SMatthew Dillon
630572ff6f6SMatthew Dillon val = OS_REG_READ(ah, ar5416_cca_regs[i]);
631572ff6f6SMatthew Dillon val &= 0xFFFFFE00;
632572ff6f6SMatthew Dillon val |= (((uint32_t) nf_val << 1) & 0x1ff);
633572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL, "[%d: %d]", i, nf_val);
634572ff6f6SMatthew Dillon OS_REG_WRITE(ah, ar5416_cca_regs[i], val);
635572ff6f6SMatthew Dillon }
636572ff6f6SMatthew Dillon }
637572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL, "\n");
638572ff6f6SMatthew Dillon
639572ff6f6SMatthew Dillon /* Load software filtered NF value into baseband internal minCCApwr variable. */
640572ff6f6SMatthew Dillon OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
641572ff6f6SMatthew Dillon OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
642572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
643572ff6f6SMatthew Dillon
644572ff6f6SMatthew Dillon /* Wait for load to complete, should be fast, a few 10s of us. */
645572ff6f6SMatthew Dillon if (! ar5212WaitNFCalComplete(ah, 1000)) {
646572ff6f6SMatthew Dillon /*
647572ff6f6SMatthew Dillon * We timed out waiting for the noisefloor to load, probably due to an
648572ff6f6SMatthew Dillon * in-progress rx. Simply return here and allow the load plenty of time
649572ff6f6SMatthew Dillon * to complete before the next calibration interval. We need to avoid
650572ff6f6SMatthew Dillon * trying to load -50 (which happens below) while the previous load is
651572ff6f6SMatthew Dillon * still in progress as this can cause rx deafness. Instead by returning
652572ff6f6SMatthew Dillon * here, the baseband nf cal will just be capped by our present
653572ff6f6SMatthew Dillon * noisefloor until the next calibration timer.
654572ff6f6SMatthew Dillon */
655572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "Timeout while waiting for "
656572ff6f6SMatthew Dillon "nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
657572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
658572ff6f6SMatthew Dillon return;
659572ff6f6SMatthew Dillon }
660572ff6f6SMatthew Dillon
661572ff6f6SMatthew Dillon /*
662572ff6f6SMatthew Dillon * Restore maxCCAPower register parameter again so that we're not capped
663572ff6f6SMatthew Dillon * by the median we just loaded. This will be initial (and max) value
664572ff6f6SMatthew Dillon * of next noise floor calibration the baseband does.
665572ff6f6SMatthew Dillon */
66643d0447fSSascha Wildner for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
667572ff6f6SMatthew Dillon
668572ff6f6SMatthew Dillon /* Don't write to EXT radio CCA registers unless in HT/40 mode */
669572ff6f6SMatthew Dillon /* XXX this check should really be cleaner! */
670572ff6f6SMatthew Dillon if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))
671572ff6f6SMatthew Dillon continue;
672572ff6f6SMatthew Dillon
673572ff6f6SMatthew Dillon if (chainmask & (1 << i)) {
674572ff6f6SMatthew Dillon val = OS_REG_READ(ah, ar5416_cca_regs[i]);
675572ff6f6SMatthew Dillon val &= 0xFFFFFE00;
676572ff6f6SMatthew Dillon val |= (((uint32_t)(-50) << 1) & 0x1ff);
677572ff6f6SMatthew Dillon OS_REG_WRITE(ah, ar5416_cca_regs[i], val);
678572ff6f6SMatthew Dillon }
679572ff6f6SMatthew Dillon }
68043d0447fSSascha Wildner }
681572ff6f6SMatthew Dillon
682572ff6f6SMatthew Dillon /*
683572ff6f6SMatthew Dillon * This just initialises the "good" values for AR5416 which
684572ff6f6SMatthew Dillon * may not be right; it'lll be overridden by ar5416SanitizeNF()
685572ff6f6SMatthew Dillon * to nominal values.
686572ff6f6SMatthew Dillon */
687572ff6f6SMatthew Dillon void
ar5416InitNfHistBuff(struct ar5212NfCalHist * h)688572ff6f6SMatthew Dillon ar5416InitNfHistBuff(struct ar5212NfCalHist *h)
689572ff6f6SMatthew Dillon {
690572ff6f6SMatthew Dillon int i, j;
691572ff6f6SMatthew Dillon
692572ff6f6SMatthew Dillon for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
693572ff6f6SMatthew Dillon h[i].currIndex = 0;
694572ff6f6SMatthew Dillon h[i].privNF = AR5416_CCA_MAX_GOOD_VALUE;
695572ff6f6SMatthew Dillon h[i].invalidNFcount = AR512_NF_CAL_HIST_MAX;
696572ff6f6SMatthew Dillon for (j = 0; j < AR512_NF_CAL_HIST_MAX; j ++)
697572ff6f6SMatthew Dillon h[i].nfCalBuffer[j] = AR5416_CCA_MAX_GOOD_VALUE;
698572ff6f6SMatthew Dillon }
699572ff6f6SMatthew Dillon }
700572ff6f6SMatthew Dillon
701572ff6f6SMatthew Dillon /*
702572ff6f6SMatthew Dillon * Update the noise floor buffer as a ring buffer
703572ff6f6SMatthew Dillon */
704572ff6f6SMatthew Dillon static void
ar5416UpdateNFHistBuff(struct ath_hal * ah,struct ar5212NfCalHist * h,int16_t * nfarray)705572ff6f6SMatthew Dillon ar5416UpdateNFHistBuff(struct ath_hal *ah, struct ar5212NfCalHist *h,
706572ff6f6SMatthew Dillon int16_t *nfarray)
707572ff6f6SMatthew Dillon {
708572ff6f6SMatthew Dillon int i;
709572ff6f6SMatthew Dillon
710572ff6f6SMatthew Dillon /* XXX TODO: don't record nfarray[] entries for inactive chains */
711572ff6f6SMatthew Dillon for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
712572ff6f6SMatthew Dillon h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
713572ff6f6SMatthew Dillon
714572ff6f6SMatthew Dillon if (++h[i].currIndex >= AR512_NF_CAL_HIST_MAX)
715572ff6f6SMatthew Dillon h[i].currIndex = 0;
716572ff6f6SMatthew Dillon if (h[i].invalidNFcount > 0) {
717572ff6f6SMatthew Dillon if (nfarray[i] < AR5416_CCA_MIN_BAD_VALUE ||
718572ff6f6SMatthew Dillon nfarray[i] > AR5416_CCA_MAX_HIGH_VALUE) {
719572ff6f6SMatthew Dillon h[i].invalidNFcount = AR512_NF_CAL_HIST_MAX;
720572ff6f6SMatthew Dillon } else {
721572ff6f6SMatthew Dillon h[i].invalidNFcount--;
722572ff6f6SMatthew Dillon h[i].privNF = nfarray[i];
723572ff6f6SMatthew Dillon }
724572ff6f6SMatthew Dillon } else {
725572ff6f6SMatthew Dillon h[i].privNF = ar5212GetNfHistMid(h[i].nfCalBuffer);
726572ff6f6SMatthew Dillon }
727572ff6f6SMatthew Dillon }
728572ff6f6SMatthew Dillon }
729572ff6f6SMatthew Dillon
730572ff6f6SMatthew Dillon static uint16_t
ar5416GetDefaultNF(struct ath_hal * ah,const struct ieee80211_channel * chan)731572ff6f6SMatthew Dillon ar5416GetDefaultNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
732572ff6f6SMatthew Dillon {
733572ff6f6SMatthew Dillon struct ar5416NfLimits *limit;
734572ff6f6SMatthew Dillon
735572ff6f6SMatthew Dillon if (!chan || IEEE80211_IS_CHAN_2GHZ(chan))
736572ff6f6SMatthew Dillon limit = &AH5416(ah)->nf_2g;
737572ff6f6SMatthew Dillon else
738572ff6f6SMatthew Dillon limit = &AH5416(ah)->nf_5g;
739572ff6f6SMatthew Dillon
740572ff6f6SMatthew Dillon return limit->nominal;
741572ff6f6SMatthew Dillon }
742572ff6f6SMatthew Dillon
743572ff6f6SMatthew Dillon static void
ar5416SanitizeNF(struct ath_hal * ah,int16_t * nf)744572ff6f6SMatthew Dillon ar5416SanitizeNF(struct ath_hal *ah, int16_t *nf)
745572ff6f6SMatthew Dillon {
746572ff6f6SMatthew Dillon
747572ff6f6SMatthew Dillon struct ar5416NfLimits *limit;
748572ff6f6SMatthew Dillon int i;
749572ff6f6SMatthew Dillon
750572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan))
751572ff6f6SMatthew Dillon limit = &AH5416(ah)->nf_2g;
752572ff6f6SMatthew Dillon else
753572ff6f6SMatthew Dillon limit = &AH5416(ah)->nf_5g;
754572ff6f6SMatthew Dillon
755572ff6f6SMatthew Dillon for (i = 0; i < AR5416_NUM_NF_READINGS; i++) {
756572ff6f6SMatthew Dillon if (!nf[i])
757572ff6f6SMatthew Dillon continue;
758572ff6f6SMatthew Dillon
759572ff6f6SMatthew Dillon if (nf[i] > limit->max) {
760572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
761572ff6f6SMatthew Dillon "NF[%d] (%d) > MAX (%d), correcting to MAX\n",
762572ff6f6SMatthew Dillon i, nf[i], limit->max);
763572ff6f6SMatthew Dillon nf[i] = limit->max;
764572ff6f6SMatthew Dillon } else if (nf[i] < limit->min) {
765572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
766572ff6f6SMatthew Dillon "NF[%d] (%d) < MIN (%d), correcting to NOM\n",
767572ff6f6SMatthew Dillon i, nf[i], limit->min);
768572ff6f6SMatthew Dillon nf[i] = limit->nominal;
769572ff6f6SMatthew Dillon }
770572ff6f6SMatthew Dillon }
771572ff6f6SMatthew Dillon }
772572ff6f6SMatthew Dillon
773572ff6f6SMatthew Dillon
774572ff6f6SMatthew Dillon /*
775*b14ca477SMatthew Dillon * Read the NF and check it against the noise floor threshold
776572ff6f6SMatthew Dillon *
777572ff6f6SMatthew Dillon * Return 0 if the NF calibration hadn't finished, 0 if it was
778572ff6f6SMatthew Dillon * invalid, or > 0 for a valid NF reading.
779572ff6f6SMatthew Dillon */
780572ff6f6SMatthew Dillon static int16_t
ar5416GetNf(struct ath_hal * ah,struct ieee80211_channel * chan)781572ff6f6SMatthew Dillon ar5416GetNf(struct ath_hal *ah, struct ieee80211_channel *chan)
782572ff6f6SMatthew Dillon {
783572ff6f6SMatthew Dillon int16_t nf, nfThresh;
784572ff6f6SMatthew Dillon int i;
785572ff6f6SMatthew Dillon int retval = 0;
786572ff6f6SMatthew Dillon
787572ff6f6SMatthew Dillon if (ar5212IsNFCalInProgress(ah)) {
788572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
789572ff6f6SMatthew Dillon "%s: NF didn't complete in calibration window\n", __func__);
790572ff6f6SMatthew Dillon nf = 0;
791572ff6f6SMatthew Dillon retval = -1; /* NF didn't finish */
792572ff6f6SMatthew Dillon } else {
793572ff6f6SMatthew Dillon /* Finished NF cal, check against threshold */
794572ff6f6SMatthew Dillon int16_t nfarray[NUM_NOISEFLOOR_READINGS] = { 0 };
795572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
796572ff6f6SMatthew Dillon
797572ff6f6SMatthew Dillon /* TODO - enhance for multiple chains and ext ch */
798572ff6f6SMatthew Dillon ath_hal_getNoiseFloor(ah, nfarray);
799572ff6f6SMatthew Dillon nf = nfarray[0];
800572ff6f6SMatthew Dillon ar5416SanitizeNF(ah, nfarray);
801572ff6f6SMatthew Dillon if (ar5416GetEepromNoiseFloorThresh(ah, chan, &nfThresh)) {
802572ff6f6SMatthew Dillon if (nf > nfThresh) {
803572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
804572ff6f6SMatthew Dillon "%s: noise floor failed detected; "
805572ff6f6SMatthew Dillon "detected %d, threshold %d\n", __func__,
806572ff6f6SMatthew Dillon nf, nfThresh);
807572ff6f6SMatthew Dillon /*
808572ff6f6SMatthew Dillon * NB: Don't discriminate 2.4 vs 5Ghz, if this
809572ff6f6SMatthew Dillon * happens it indicates a problem regardless
810572ff6f6SMatthew Dillon * of the band.
811572ff6f6SMatthew Dillon */
812572ff6f6SMatthew Dillon chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
813572ff6f6SMatthew Dillon nf = 0;
814572ff6f6SMatthew Dillon retval = 0;
815572ff6f6SMatthew Dillon }
816572ff6f6SMatthew Dillon } else {
817572ff6f6SMatthew Dillon nf = 0;
818572ff6f6SMatthew Dillon retval = 0;
819572ff6f6SMatthew Dillon }
820572ff6f6SMatthew Dillon /* Update MIMO channel statistics, regardless of validity or not (for now) */
821572ff6f6SMatthew Dillon for (i = 0; i < 3; i++) {
822572ff6f6SMatthew Dillon ichan->noiseFloorCtl[i] = nfarray[i];
823572ff6f6SMatthew Dillon ichan->noiseFloorExt[i] = nfarray[i + 3];
824572ff6f6SMatthew Dillon }
825572ff6f6SMatthew Dillon ichan->privFlags |= CHANNEL_MIMO_NF_VALID;
826572ff6f6SMatthew Dillon
827572ff6f6SMatthew Dillon ar5416UpdateNFHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist, nfarray);
828572ff6f6SMatthew Dillon ichan->rawNoiseFloor = nf;
829572ff6f6SMatthew Dillon retval = nf;
830572ff6f6SMatthew Dillon }
831572ff6f6SMatthew Dillon return retval;
832572ff6f6SMatthew Dillon }
833