1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4*572ff6f6SMatthew Dillon *
5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8*572ff6f6SMatthew Dillon *
9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*572ff6f6SMatthew Dillon *
17*572ff6f6SMatthew Dillon * $FreeBSD$
18*572ff6f6SMatthew Dillon */
19*572ff6f6SMatthew Dillon #include "opt_ah.h"
20*572ff6f6SMatthew Dillon
21*572ff6f6SMatthew Dillon #include "ah.h"
22*572ff6f6SMatthew Dillon #include "ah_internal.h"
23*572ff6f6SMatthew Dillon #include "ah_devid.h"
24*572ff6f6SMatthew Dillon
25*572ff6f6SMatthew Dillon #include "ar5416/ar5416.h"
26*572ff6f6SMatthew Dillon #include "ar5416/ar5416reg.h"
27*572ff6f6SMatthew Dillon #include "ar5416/ar5416phy.h"
28*572ff6f6SMatthew Dillon
29*572ff6f6SMatthew Dillon /* Adc DC Offset Cal aliases */
30*572ff6f6SMatthew Dillon #define totalAdcDcOffsetIOddPhase(i) caldata[0][i].s
31*572ff6f6SMatthew Dillon #define totalAdcDcOffsetIEvenPhase(i) caldata[1][i].s
32*572ff6f6SMatthew Dillon #define totalAdcDcOffsetQOddPhase(i) caldata[2][i].s
33*572ff6f6SMatthew Dillon #define totalAdcDcOffsetQEvenPhase(i) caldata[3][i].s
34*572ff6f6SMatthew Dillon
35*572ff6f6SMatthew Dillon void
ar5416AdcDcCalCollect(struct ath_hal * ah)36*572ff6f6SMatthew Dillon ar5416AdcDcCalCollect(struct ath_hal *ah)
37*572ff6f6SMatthew Dillon {
38*572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
39*572ff6f6SMatthew Dillon int i;
40*572ff6f6SMatthew Dillon
41*572ff6f6SMatthew Dillon for (i = 0; i < AR5416_MAX_CHAINS; i++) {
42*572ff6f6SMatthew Dillon cal->totalAdcDcOffsetIOddPhase(i) += (int32_t)
43*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
44*572ff6f6SMatthew Dillon cal->totalAdcDcOffsetIEvenPhase(i) += (int32_t)
45*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
46*572ff6f6SMatthew Dillon cal->totalAdcDcOffsetQOddPhase(i) += (int32_t)
47*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
48*572ff6f6SMatthew Dillon cal->totalAdcDcOffsetQEvenPhase(i) += (int32_t)
49*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
50*572ff6f6SMatthew Dillon
51*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
52*572ff6f6SMatthew Dillon "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
53*572ff6f6SMatthew Dillon cal->calSamples, i,
54*572ff6f6SMatthew Dillon cal->totalAdcDcOffsetIOddPhase(i),
55*572ff6f6SMatthew Dillon cal->totalAdcDcOffsetIEvenPhase(i),
56*572ff6f6SMatthew Dillon cal->totalAdcDcOffsetQOddPhase(i),
57*572ff6f6SMatthew Dillon cal->totalAdcDcOffsetQEvenPhase(i));
58*572ff6f6SMatthew Dillon }
59*572ff6f6SMatthew Dillon }
60*572ff6f6SMatthew Dillon
61*572ff6f6SMatthew Dillon void
ar5416AdcDcCalibration(struct ath_hal * ah,uint8_t numChains)62*572ff6f6SMatthew Dillon ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains)
63*572ff6f6SMatthew Dillon {
64*572ff6f6SMatthew Dillon struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
65*572ff6f6SMatthew Dillon const HAL_PERCAL_DATA *calData = cal->cal_curr->calData;
66*572ff6f6SMatthew Dillon uint32_t numSamples;
67*572ff6f6SMatthew Dillon int i;
68*572ff6f6SMatthew Dillon
69*572ff6f6SMatthew Dillon numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
70*572ff6f6SMatthew Dillon for (i = 0; i < numChains; i++) {
71*572ff6f6SMatthew Dillon uint32_t iOddMeasOffset = cal->totalAdcDcOffsetIOddPhase(i);
72*572ff6f6SMatthew Dillon uint32_t iEvenMeasOffset = cal->totalAdcDcOffsetIEvenPhase(i);
73*572ff6f6SMatthew Dillon int32_t qOddMeasOffset = cal->totalAdcDcOffsetQOddPhase(i);
74*572ff6f6SMatthew Dillon int32_t qEvenMeasOffset = cal->totalAdcDcOffsetQEvenPhase(i);
75*572ff6f6SMatthew Dillon int32_t qDcMismatch, iDcMismatch;
76*572ff6f6SMatthew Dillon uint32_t val;
77*572ff6f6SMatthew Dillon
78*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
79*572ff6f6SMatthew Dillon "Starting ADC DC Offset Cal for Chain %d\n", i);
80*572ff6f6SMatthew Dillon
81*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_i = %d\n",
82*572ff6f6SMatthew Dillon iOddMeasOffset);
83*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_i = %d\n",
84*572ff6f6SMatthew Dillon iEvenMeasOffset);
85*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_q = %d\n",
86*572ff6f6SMatthew Dillon qOddMeasOffset);
87*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_q = %d\n",
88*572ff6f6SMatthew Dillon qEvenMeasOffset);
89*572ff6f6SMatthew Dillon
90*572ff6f6SMatthew Dillon HALASSERT(numSamples);
91*572ff6f6SMatthew Dillon
92*572ff6f6SMatthew Dillon iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
93*572ff6f6SMatthew Dillon numSamples) & 0x1ff;
94*572ff6f6SMatthew Dillon qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
95*572ff6f6SMatthew Dillon numSamples) & 0x1ff;
96*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
97*572ff6f6SMatthew Dillon " dc_offset_mismatch_i = 0x%08x\n", iDcMismatch);
98*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
99*572ff6f6SMatthew Dillon " dc_offset_mismatch_q = 0x%08x\n", qDcMismatch);
100*572ff6f6SMatthew Dillon
101*572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
102*572ff6f6SMatthew Dillon val &= 0xc0000fff;
103*572ff6f6SMatthew Dillon val |= (qDcMismatch << 12) | (iDcMismatch << 21);
104*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
105*572ff6f6SMatthew Dillon
106*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PERCAL,
107*572ff6f6SMatthew Dillon "ADC DC Offset Cal done for Chain %d\n", i);
108*572ff6f6SMatthew Dillon }
109*572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
110*572ff6f6SMatthew Dillon AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
111*572ff6f6SMatthew Dillon }
112