1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27 #include "ar9002/ar9280.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar9002/ar9280v1.ini" 32 #include "ar9002/ar9280v2.ini" 33 #include "ar9002/ar9280_olc.h" 34 35 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37 .calNumSamples = MIN_CAL_SAMPLES, 38 .calCountMax = PER_MAX_LOG_COUNT, 39 .calCollect = ar5416IQCalCollect, 40 .calPostProc = ar5416IQCalibration 41 }; 42 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44 .calNumSamples = MIN_CAL_SAMPLES, 45 .calCountMax = PER_MAX_LOG_COUNT, 46 .calCollect = ar5416AdcGainCalCollect, 47 .calPostProc = ar5416AdcGainCalibration 48 }; 49 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50 .calName = "ADC DC", .calType = ADC_DC_CAL, 51 .calNumSamples = MIN_CAL_SAMPLES, 52 .calCountMax = PER_MAX_LOG_COUNT, 53 .calCollect = ar5416AdcDcCalCollect, 54 .calPostProc = ar5416AdcDcCalibration 55 }; 56 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58 .calNumSamples = MIN_CAL_SAMPLES, 59 .calCountMax = INIT_LOG_COUNT, 60 .calCollect = ar5416AdcDcCalCollect, 61 .calPostProc = ar5416AdcDcCalibration 62 }; 63 64 static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 65 HAL_BOOL power_off); 66 static void ar9280DisablePCIE(struct ath_hal *ah); 67 static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 68 static void ar9280WriteIni(struct ath_hal *ah, 69 const struct ieee80211_channel *chan); 70 71 static void 72 ar9280AniSetup(struct ath_hal *ah) 73 { 74 /* 75 * These are the parameters from the AR5416 ANI code; 76 * they likely need quite a bit of adjustment for the 77 * AR9280. 78 */ 79 static const struct ar5212AniParams aniparams = { 80 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 81 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 82 .coarseHigh = { -14, -14, -14, -14, -12 }, 83 .coarseLow = { -64, -64, -64, -64, -70 }, 84 .firpwr = { -78, -78, -78, -78, -80 }, 85 .maxSpurImmunityLevel = 7, 86 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 87 .maxFirstepLevel = 2, /* levels 0..2 */ 88 .firstep = { 0, 4, 8 }, 89 .ofdmTrigHigh = 500, 90 .ofdmTrigLow = 200, 91 .cckTrigHigh = 200, 92 .cckTrigLow = 100, 93 .rssiThrHigh = 40, 94 .rssiThrLow = 7, 95 .period = 100, 96 }; 97 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 98 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 99 100 /* NB: ANI is not enabled yet */ 101 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 102 } 103 104 void 105 ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 106 { 107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 108 109 if (AR_SREV_MERLIN_20(ah) && 110 chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 111 /* 112 * PLL WAR for Merlin 2.0/2.1 113 * When doing fast clock, set PLL to 0x142c 114 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 115 */ 116 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 117 if (IEEE80211_IS_CHAN_HALF(chan)) 118 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 119 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 120 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 121 } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 122 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 123 if (chan != AH_NULL) { 124 if (IEEE80211_IS_CHAN_HALF(chan)) 125 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 126 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 127 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 128 if (IEEE80211_IS_CHAN_5GHZ(chan)) 129 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 130 else 131 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 132 } else 133 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 134 } 135 136 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 137 OS_DELAY(RTC_PLL_SETTLE_DELAY); 138 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 139 } 140 141 /* XXX shouldn't be here! */ 142 #define EEP_MINOR(_ah) \ 143 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 144 145 /* 146 * Attach for an AR9280 part. 147 */ 148 static struct ath_hal * 149 ar9280Attach(uint16_t devid, HAL_SOFTC sc, 150 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 151 HAL_OPS_CONFIG *ah_config, 152 HAL_STATUS *status) 153 { 154 struct ath_hal_9280 *ahp9280; 155 struct ath_hal_5212 *ahp; 156 struct ath_hal *ah; 157 uint32_t val; 158 HAL_STATUS ecode; 159 HAL_BOOL rfStatus; 160 int8_t pwr_table_offset; 161 uint8_t pwr; 162 163 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 164 __func__, sc, (void*) st, (void*) sh); 165 166 /* NB: memory is returned zero'd */ 167 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 168 if (ahp9280 == AH_NULL) { 169 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 170 "%s: cannot allocate memory for state block\n", __func__); 171 *status = HAL_ENOMEM; 172 return AH_NULL; 173 } 174 ahp = AH5212(ahp9280); 175 ah = &ahp->ah_priv.h; 176 177 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 178 179 /* 180 * Use the "local" EEPROM data given to us by the higher layers. 181 * This is a private copy out of system flash. The Linux ath9k 182 * commit for the initial AR9130 support mentions MMIO flash 183 * access is "unreliable." -adrian 184 */ 185 if (eepromdata != AH_NULL) { 186 AH_PRIVATE((ah))->ah_eepromRead = ath_hal_EepromDataRead; 187 AH_PRIVATE((ah))->ah_eepromWrite = NULL; 188 ah->ah_eepromdata = eepromdata; 189 } 190 191 /* XXX override with 9280 specific state */ 192 /* override 5416 methods for our needs */ 193 AH5416(ah)->ah_initPLL = ar9280InitPLL; 194 195 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 196 ah->ah_configPCIE = ar9280ConfigPCIE; 197 ah->ah_disablePCIE = ar9280DisablePCIE; 198 199 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 200 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 201 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 202 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 203 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 204 205 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 206 AH5416(ah)->ah_writeIni = ar9280WriteIni; 207 AH5416(ah)->ah_olcInit = ar9280olcInit; 208 AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 209 AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 210 211 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 212 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 213 214 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 215 /* reset chip */ 216 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 217 __func__); 218 ecode = HAL_EIO; 219 goto bad; 220 } 221 222 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 223 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 224 __func__); 225 ecode = HAL_EIO; 226 goto bad; 227 } 228 /* Read Revisions from Chips before taking out of reset */ 229 val = OS_REG_READ(ah, AR_SREV); 230 HALDEBUG(ah, HAL_DEBUG_ATTACH, 231 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 232 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 233 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 234 /* NB: include chip type to differentiate from pre-Sowl versions */ 235 AH_PRIVATE(ah)->ah_macVersion = 236 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 237 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 238 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 239 240 /* setup common ini data; rf backends handle remainder */ 241 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 242 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 243 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 244 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 245 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 246 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 247 ar9280Modes_fast_clock_v2, 3); 248 } else { 249 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 250 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 251 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 252 ar9280PciePhy_v1, 2); 253 } 254 ar5416AttachPCIE(ah); 255 256 ecode = ath_hal_v14EepromAttach(ah); 257 if (ecode != HAL_OK) 258 goto bad; 259 260 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 261 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 262 ecode = HAL_EIO; 263 goto bad; 264 } 265 266 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 267 268 if (!ar5212ChipTest(ah)) { 269 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 270 __func__); 271 ecode = HAL_ESELFTEST; 272 goto bad; 273 } 274 275 /* 276 * Set correct Baseband to analog shift 277 * setting to access analog chips. 278 */ 279 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 280 281 /* Read Radio Chip Rev Extract */ 282 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 283 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 284 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 285 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 286 break; 287 default: 288 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 289 AH_PRIVATE(ah)->ah_analog5GhzRev = 290 AR_RAD5133_SREV_MAJOR; 291 break; 292 } 293 #ifdef AH_DEBUG 294 HALDEBUG(ah, HAL_DEBUG_ANY, 295 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 296 "this driver\n", __func__, 297 AH_PRIVATE(ah)->ah_analog5GhzRev); 298 ecode = HAL_ENOTSUPP; 299 goto bad; 300 #endif 301 } 302 rfStatus = ar9280RfAttach(ah, &ecode); 303 if (!rfStatus) { 304 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 305 __func__, ecode); 306 goto bad; 307 } 308 309 /* Enable fixup for AR_AN_TOP2 if necessary */ 310 /* 311 * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 312 * by the EEPROM version. 313 * 314 * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 315 * the abstracted EEPROM access layer. 316 */ 317 ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 318 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 319 kprintf("[ath] enabling AN_TOP2_FIXUP\n"); 320 AH5416(ah)->ah_need_an_top2_fixup = 1; 321 } 322 323 /* 324 * Check whether the power table offset isn't the default. 325 * This can occur with eeprom minor V21 or greater on Merlin. 326 */ 327 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 328 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 329 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 330 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 331 332 /* XXX check for >= minor ver 17 */ 333 if (AR_SREV_MERLIN_20(ah)) { 334 /* setup rxgain table */ 335 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 336 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 337 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 338 ar9280Modes_backoff_13db_rxgain_v2, 6); 339 break; 340 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 341 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 342 ar9280Modes_backoff_23db_rxgain_v2, 6); 343 break; 344 case AR5416_EEP_RXGAIN_ORIG: 345 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 346 ar9280Modes_original_rxgain_v2, 6); 347 break; 348 default: 349 HALASSERT(AH_FALSE); 350 goto bad; /* XXX ? try to continue */ 351 } 352 } 353 354 /* XXX check for >= minor ver 19 */ 355 if (AR_SREV_MERLIN_20(ah)) { 356 /* setp txgain table */ 357 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 358 case AR5416_EEP_TXGAIN_HIGH_POWER: 359 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 360 ar9280Modes_high_power_tx_gain_v2, 6); 361 break; 362 case AR5416_EEP_TXGAIN_ORIG: 363 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 364 ar9280Modes_original_tx_gain_v2, 6); 365 break; 366 default: 367 HALASSERT(AH_FALSE); 368 goto bad; /* XXX ? try to continue */ 369 } 370 } 371 372 /* 373 * Got everything we need now to setup the capabilities. 374 */ 375 if (!ar9280FillCapabilityInfo(ah)) { 376 ecode = HAL_EEREAD; 377 goto bad; 378 } 379 380 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 381 if (ecode != HAL_OK) { 382 HALDEBUG(ah, HAL_DEBUG_ANY, 383 "%s: error getting mac address from EEPROM\n", __func__); 384 goto bad; 385 } 386 /* XXX How about the serial number ? */ 387 /* Read Reg Domain */ 388 AH_PRIVATE(ah)->ah_currentRD = 389 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 390 AH_PRIVATE(ah)->ah_currentRDext = 391 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 392 393 /* 394 * ah_miscMode is populated by ar5416FillCapabilityInfo() 395 * starting from griffin. Set here to make sure that 396 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 397 * placed into hardware. 398 */ 399 if (ahp->ah_miscMode != 0) 400 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 401 402 ar9280AniSetup(ah); /* Anti Noise Immunity */ 403 404 /* Setup noise floor min/max/nominal values */ 405 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 406 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 407 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 408 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 409 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 410 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 411 412 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 413 414 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 415 416 return ah; 417 bad: 418 if (ah != AH_NULL) 419 ah->ah_detach(ah); 420 if (status) 421 *status = ecode; 422 return AH_NULL; 423 } 424 425 static void 426 ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 427 { 428 uint32_t val; 429 430 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 431 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 432 OS_DELAY(1000); 433 } 434 435 436 /* 437 * Set PCIe workaround bits 438 * 439 * NOTE: 440 * 441 * In Merlin and Kite, bit 14 in WA register (disable L1) should only 442 * be set when device enters D3 and be cleared when device comes back 443 * to D0. 444 */ 445 if (power_off) { /* Power-off */ 446 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 447 448 val = OS_REG_READ(ah, AR_WA); 449 450 /* 451 * Disable bit 6 and 7 before entering D3 to prevent 452 * system hang. 453 */ 454 val &= ~(AR_WA_BIT6 | AR_WA_BIT7); 455 456 /* 457 * XXX Not sure, is specified in the reference HAL. 458 */ 459 val |= AR_WA_BIT22; 460 461 /* 462 * See above: set AR_WA_D3_L1_DISABLE when entering D3 state. 463 * 464 * XXX The reference HAL does it this way - it only sets 465 * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT, 466 * which it (currently) isn't. So the following statement 467 * is currently a NOP. 468 */ 469 if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE) 470 val |= AR_WA_D3_L1_DISABLE; 471 472 OS_REG_WRITE(ah, AR_WA, val); 473 } else { /* Power-on */ 474 val = AR9280_WA_DEFAULT; 475 476 /* 477 * See note above: make sure L1_DISABLE is not set. 478 */ 479 val &= (~AR_WA_D3_L1_DISABLE); 480 OS_REG_WRITE(ah, AR_WA, val); 481 482 /* set bit 19 to allow forcing of pcie core into L1 state */ 483 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 484 } 485 } 486 487 static void 488 ar9280DisablePCIE(struct ath_hal *ah) 489 { 490 } 491 492 static void 493 ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 494 { 495 u_int modesIndex, freqIndex; 496 int regWrites = 0; 497 int i; 498 const HAL_INI_ARRAY *ia; 499 500 /* Setup the indices for the next set of register array writes */ 501 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 502 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 503 freqIndex = 2; 504 if (IEEE80211_IS_CHAN_HT40(chan)) 505 modesIndex = 3; 506 else if (IEEE80211_IS_CHAN_108G(chan)) 507 modesIndex = 5; 508 else 509 modesIndex = 4; 510 } else { 511 freqIndex = 1; 512 if (IEEE80211_IS_CHAN_HT40(chan) || 513 IEEE80211_IS_CHAN_TURBO(chan)) 514 modesIndex = 2; 515 else 516 modesIndex = 1; 517 } 518 519 /* Set correct Baseband to analog shift setting to access analog chips. */ 520 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 521 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 522 523 /* 524 * This is unwound because at the moment, there's a requirement 525 * for Merlin (and later, perhaps) to have a specific bit fixed 526 * in the AR_AN_TOP2 register before writing it. 527 */ 528 ia = &AH5212(ah)->ah_ini_modes; 529 #if 0 530 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 531 modesIndex, regWrites); 532 #endif 533 HALASSERT(modesIndex < ia->cols); 534 for (i = 0; i < ia->rows; i++) { 535 uint32_t reg = HAL_INI_VAL(ia, i, 0); 536 uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 537 538 if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 539 val &= ~AR_AN_TOP2_PWDCLKIND; 540 541 OS_REG_WRITE(ah, reg, val); 542 543 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 544 if (reg >= 0x7800 && reg < 0x7900) 545 OS_DELAY(100); 546 547 DMA_YIELD(regWrites); 548 } 549 550 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 551 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 552 modesIndex, regWrites); 553 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 554 modesIndex, regWrites); 555 } 556 /* XXX Merlin 100us delay for shift registers */ 557 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 558 1, regWrites); 559 560 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 561 /* 5GHz channels w/ Fast Clock use different modal values */ 562 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 563 modesIndex, regWrites); 564 } 565 } 566 567 #define AR_BASE_FREQ_2GHZ 2300 568 #define AR_BASE_FREQ_5GHZ 4900 569 #define AR_SPUR_FEEQ_BOUND_HT40 19 570 #define AR_SPUR_FEEQ_BOUND_HT20 10 571 572 void 573 ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 574 { 575 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 576 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 577 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 578 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 579 static int inc[4] = { 0, 100, 0, 0 }; 580 581 int bb_spur = AR_NO_SPUR; 582 int freq; 583 int bin, cur_bin; 584 int bb_spur_off, spur_subchannel_sd; 585 int spur_freq_sd; 586 int spur_delta_phase; 587 int denominator; 588 int upper, lower, cur_vit_mask; 589 int tmp, newVal; 590 int i; 591 CHAN_CENTERS centers; 592 593 int8_t mask_m[123]; 594 int8_t mask_p[123]; 595 int8_t mask_amt; 596 int tmp_mask; 597 int cur_bb_spur; 598 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 599 600 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 601 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 602 603 ar5416GetChannelCenters(ah, chan, ¢ers); 604 freq = centers.synth_center; 605 606 /* 607 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 608 * otherwise spur is out-of-band and can be ignored. 609 */ 610 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 611 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 612 /* Get actual spur freq in MHz from EEPROM read value */ 613 if (is2GHz) { 614 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 615 } else { 616 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 617 } 618 619 if (AR_NO_SPUR == cur_bb_spur) 620 break; 621 cur_bb_spur = cur_bb_spur - freq; 622 623 if (IEEE80211_IS_CHAN_HT40(chan)) { 624 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 625 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 626 bb_spur = cur_bb_spur; 627 break; 628 } 629 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 630 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 631 bb_spur = cur_bb_spur; 632 break; 633 } 634 } 635 636 if (AR_NO_SPUR == bb_spur) { 637 #if 1 638 /* 639 * MRC CCK can interfere with beacon detection and cause deaf/mute. 640 * Disable MRC CCK for now. 641 */ 642 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 643 #else 644 /* Enable MRC CCK if no spur is found in this channel. */ 645 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 646 #endif 647 return; 648 } else { 649 /* 650 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 651 * is found in this channel. 652 */ 653 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 654 } 655 656 bin = bb_spur * 320; 657 658 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 659 660 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 661 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 662 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 663 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 664 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 665 666 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 667 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 668 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 669 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 670 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 671 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 672 673 /* Pick control or extn channel to cancel the spur */ 674 if (IEEE80211_IS_CHAN_HT40(chan)) { 675 if (bb_spur < 0) { 676 spur_subchannel_sd = 1; 677 bb_spur_off = bb_spur + 10; 678 } else { 679 spur_subchannel_sd = 0; 680 bb_spur_off = bb_spur - 10; 681 } 682 } else { 683 spur_subchannel_sd = 0; 684 bb_spur_off = bb_spur; 685 } 686 687 /* 688 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 689 * /80 for dyn2040. 690 */ 691 if (IEEE80211_IS_CHAN_HT40(chan)) 692 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 693 else 694 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 695 696 /* 697 * in 11A mode the denominator of spur_freq_sd should be 40 and 698 * it should be 44 in 11G 699 */ 700 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 701 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 702 703 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 704 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 705 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 706 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 707 708 /* Choose to cancel between control and extension channels */ 709 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 710 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 711 712 /* 713 * ============================================ 714 * Set Pilot and Channel Masks 715 * 716 * pilot mask 1 [31:0] = +6..-26, no 0 bin 717 * pilot mask 2 [19:0] = +26..+7 718 * 719 * channel mask 1 [31:0] = +6..-26, no 0 bin 720 * channel mask 2 [19:0] = +26..+7 721 */ 722 cur_bin = -6000; 723 upper = bin + 100; 724 lower = bin - 100; 725 726 for (i = 0; i < 4; i++) { 727 int pilot_mask = 0; 728 int chan_mask = 0; 729 int bp = 0; 730 for (bp = 0; bp < 30; bp++) { 731 if ((cur_bin > lower) && (cur_bin < upper)) { 732 pilot_mask = pilot_mask | 0x1 << bp; 733 chan_mask = chan_mask | 0x1 << bp; 734 } 735 cur_bin += 100; 736 } 737 cur_bin += inc[i]; 738 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 739 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 740 } 741 742 /* ================================================= 743 * viterbi mask 1 based on channel magnitude 744 * four levels 0-3 745 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 746 * [1 2 2 1] for -9.6 or [1 2 1] for +16 747 * - enable_mask_ppm, all bins move with freq 748 * 749 * - mask_select, 8 bits for rates (reg 67,0x990c) 750 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 751 * choose which mask to use mask or mask2 752 */ 753 754 /* 755 * viterbi mask 2 2nd set for per data rate puncturing 756 * four levels 0-3 757 * - mask_select, 8 bits for rates (reg 67) 758 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 759 * [1 2 2 1] for -9.6 or [1 2 1] for +16 760 */ 761 cur_vit_mask = 6100; 762 upper = bin + 120; 763 lower = bin - 120; 764 765 for (i = 0; i < 123; i++) { 766 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 767 if ((abs(cur_vit_mask - bin)) < 75) { 768 mask_amt = 1; 769 } else { 770 mask_amt = 0; 771 } 772 if (cur_vit_mask < 0) { 773 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 774 } else { 775 mask_p[cur_vit_mask / 100] = mask_amt; 776 } 777 } 778 cur_vit_mask -= 100; 779 } 780 781 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 782 | (mask_m[48] << 26) | (mask_m[49] << 24) 783 | (mask_m[50] << 22) | (mask_m[51] << 20) 784 | (mask_m[52] << 18) | (mask_m[53] << 16) 785 | (mask_m[54] << 14) | (mask_m[55] << 12) 786 | (mask_m[56] << 10) | (mask_m[57] << 8) 787 | (mask_m[58] << 6) | (mask_m[59] << 4) 788 | (mask_m[60] << 2) | (mask_m[61] << 0); 789 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 790 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 791 792 tmp_mask = (mask_m[31] << 28) 793 | (mask_m[32] << 26) | (mask_m[33] << 24) 794 | (mask_m[34] << 22) | (mask_m[35] << 20) 795 | (mask_m[36] << 18) | (mask_m[37] << 16) 796 | (mask_m[48] << 14) | (mask_m[39] << 12) 797 | (mask_m[40] << 10) | (mask_m[41] << 8) 798 | (mask_m[42] << 6) | (mask_m[43] << 4) 799 | (mask_m[44] << 2) | (mask_m[45] << 0); 800 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 801 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 802 803 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 804 | (mask_m[18] << 26) | (mask_m[18] << 24) 805 | (mask_m[20] << 22) | (mask_m[20] << 20) 806 | (mask_m[22] << 18) | (mask_m[22] << 16) 807 | (mask_m[24] << 14) | (mask_m[24] << 12) 808 | (mask_m[25] << 10) | (mask_m[26] << 8) 809 | (mask_m[27] << 6) | (mask_m[28] << 4) 810 | (mask_m[29] << 2) | (mask_m[30] << 0); 811 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 812 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 813 814 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 815 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 816 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 817 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 818 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 819 | (mask_m[10] << 10) | (mask_m[11] << 8) 820 | (mask_m[12] << 6) | (mask_m[13] << 4) 821 | (mask_m[14] << 2) | (mask_m[15] << 0); 822 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 823 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 824 825 tmp_mask = (mask_p[15] << 28) 826 | (mask_p[14] << 26) | (mask_p[13] << 24) 827 | (mask_p[12] << 22) | (mask_p[11] << 20) 828 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 829 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 830 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 831 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 832 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 833 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 834 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 835 836 tmp_mask = (mask_p[30] << 28) 837 | (mask_p[29] << 26) | (mask_p[28] << 24) 838 | (mask_p[27] << 22) | (mask_p[26] << 20) 839 | (mask_p[25] << 18) | (mask_p[24] << 16) 840 | (mask_p[23] << 14) | (mask_p[22] << 12) 841 | (mask_p[21] << 10) | (mask_p[20] << 8) 842 | (mask_p[19] << 6) | (mask_p[18] << 4) 843 | (mask_p[17] << 2) | (mask_p[16] << 0); 844 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 845 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 846 847 tmp_mask = (mask_p[45] << 28) 848 | (mask_p[44] << 26) | (mask_p[43] << 24) 849 | (mask_p[42] << 22) | (mask_p[41] << 20) 850 | (mask_p[40] << 18) | (mask_p[39] << 16) 851 | (mask_p[38] << 14) | (mask_p[37] << 12) 852 | (mask_p[36] << 10) | (mask_p[35] << 8) 853 | (mask_p[34] << 6) | (mask_p[33] << 4) 854 | (mask_p[32] << 2) | (mask_p[31] << 0); 855 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 856 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 857 858 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 859 | (mask_p[59] << 26) | (mask_p[58] << 24) 860 | (mask_p[57] << 22) | (mask_p[56] << 20) 861 | (mask_p[55] << 18) | (mask_p[54] << 16) 862 | (mask_p[53] << 14) | (mask_p[52] << 12) 863 | (mask_p[51] << 10) | (mask_p[50] << 8) 864 | (mask_p[49] << 6) | (mask_p[48] << 4) 865 | (mask_p[47] << 2) | (mask_p[46] << 0); 866 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 867 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 868 } 869 870 /* 871 * Fill all software cached or static hardware state information. 872 * Return failure if capabilities are to come from EEPROM and 873 * cannot be read. 874 */ 875 static HAL_BOOL 876 ar9280FillCapabilityInfo(struct ath_hal *ah) 877 { 878 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 879 880 if (!ar5416FillCapabilityInfo(ah)) 881 return AH_FALSE; 882 pCap->halNumGpioPins = 10; 883 pCap->halWowSupport = AH_TRUE; 884 pCap->halWowMatchPatternExact = AH_TRUE; 885 #if 0 886 pCap->halWowMatchPatternDword = AH_TRUE; 887 #endif 888 pCap->halCSTSupport = AH_TRUE; 889 pCap->halRifsRxSupport = AH_TRUE; 890 pCap->halRifsTxSupport = AH_TRUE; 891 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 892 pCap->halExtChanDfsSupport = AH_TRUE; 893 pCap->halUseCombinedRadarRssi = AH_TRUE; 894 #if 0 895 /* XXX bluetooth */ 896 pCap->halBtCoexSupport = AH_TRUE; 897 #endif 898 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 899 pCap->hal4kbSplitTransSupport = AH_FALSE; 900 /* Disable this so Block-ACK works correctly */ 901 pCap->halHasRxSelfLinkedTail = AH_FALSE; 902 pCap->halMbssidAggrSupport = AH_TRUE; 903 pCap->hal4AddrAggrSupport = AH_TRUE; 904 pCap->halSpectralScanSupport = AH_TRUE; 905 906 if (AR_SREV_MERLIN_20(ah)) { 907 pCap->halPSPollBroken = AH_FALSE; 908 /* 909 * This just enables the support; it doesn't 910 * state 5ghz fast clock will always be used. 911 */ 912 pCap->halSupportsFastClock5GHz = AH_TRUE; 913 } 914 pCap->halRxStbcSupport = 1; 915 pCap->halTxStbcSupport = 1; 916 pCap->halEnhancedDfsSupport = AH_TRUE; 917 918 return AH_TRUE; 919 } 920 921 /* 922 * This has been disabled - having the HAL flip chainmasks on/off 923 * when attempting to implement 11n disrupts things. For now, just 924 * leave this flipped off and worry about implementing TX diversity 925 * for legacy and MCS0-7 when 11n is fully functioning. 926 */ 927 HAL_BOOL 928 ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 929 { 930 #define ANTENNA0_CHAINMASK 0x1 931 #define ANTENNA1_CHAINMASK 0x2 932 #if 0 933 struct ath_hal_5416 *ahp = AH5416(ah); 934 935 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 936 switch (settings) { 937 case HAL_ANT_FIXED_A: 938 /* Enable first antenna only */ 939 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 940 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 941 break; 942 case HAL_ANT_FIXED_B: 943 /* Enable second antenna only, after checking capability */ 944 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 945 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 946 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 947 break; 948 case HAL_ANT_VARIABLE: 949 /* Restore original chainmask settings */ 950 /* XXX */ 951 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 952 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 953 break; 954 } 955 956 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 957 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 958 959 #endif 960 return AH_TRUE; 961 #undef ANTENNA0_CHAINMASK 962 #undef ANTENNA1_CHAINMASK 963 } 964 965 static const char* 966 ar9280Probe(uint16_t vendorid, uint16_t devid) 967 { 968 if (vendorid == ATHEROS_VENDOR_ID) { 969 if (devid == AR9280_DEVID_PCI) 970 return "Atheros 9220"; 971 if (devid == AR9280_DEVID_PCIE) 972 return "Atheros 9280"; 973 } 974 return AH_NULL; 975 } 976 AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 977