1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon #include "opt_ah.h"
20572ff6f6SMatthew Dillon
21572ff6f6SMatthew Dillon #include "ah.h"
22572ff6f6SMatthew Dillon #include "ah_internal.h"
23572ff6f6SMatthew Dillon #include "ah_devid.h"
24572ff6f6SMatthew Dillon
25572ff6f6SMatthew Dillon #include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
26572ff6f6SMatthew Dillon
27572ff6f6SMatthew Dillon #include "ar9002/ar9280.h"
28572ff6f6SMatthew Dillon #include "ar9002/ar9285.h"
29572ff6f6SMatthew Dillon #include "ar5416/ar5416reg.h"
30572ff6f6SMatthew Dillon #include "ar5416/ar5416phy.h"
31572ff6f6SMatthew Dillon
32572ff6f6SMatthew Dillon #include "ar9002/ar9285.ini"
33572ff6f6SMatthew Dillon #include "ar9002/ar9285v2.ini"
34572ff6f6SMatthew Dillon #include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */
35572ff6f6SMatthew Dillon
36572ff6f6SMatthew Dillon #include "ar9002/ar9285_cal.h"
37572ff6f6SMatthew Dillon #include "ar9002/ar9285_phy.h"
38572ff6f6SMatthew Dillon #include "ar9002/ar9285_diversity.h"
39572ff6f6SMatthew Dillon
40572ff6f6SMatthew Dillon static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
41572ff6f6SMatthew Dillon .calName = "IQ", .calType = IQ_MISMATCH_CAL,
42572ff6f6SMatthew Dillon .calNumSamples = MIN_CAL_SAMPLES,
43572ff6f6SMatthew Dillon .calCountMax = PER_MAX_LOG_COUNT,
44572ff6f6SMatthew Dillon .calCollect = ar5416IQCalCollect,
45572ff6f6SMatthew Dillon .calPostProc = ar5416IQCalibration
46572ff6f6SMatthew Dillon };
47572ff6f6SMatthew Dillon static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
48572ff6f6SMatthew Dillon .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
49572ff6f6SMatthew Dillon .calNumSamples = MIN_CAL_SAMPLES,
50572ff6f6SMatthew Dillon .calCountMax = PER_MIN_LOG_COUNT,
51572ff6f6SMatthew Dillon .calCollect = ar5416AdcGainCalCollect,
52572ff6f6SMatthew Dillon .calPostProc = ar5416AdcGainCalibration
53572ff6f6SMatthew Dillon };
54572ff6f6SMatthew Dillon static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
55572ff6f6SMatthew Dillon .calName = "ADC DC", .calType = ADC_DC_CAL,
56572ff6f6SMatthew Dillon .calNumSamples = MIN_CAL_SAMPLES,
57572ff6f6SMatthew Dillon .calCountMax = PER_MIN_LOG_COUNT,
58572ff6f6SMatthew Dillon .calCollect = ar5416AdcDcCalCollect,
59572ff6f6SMatthew Dillon .calPostProc = ar5416AdcDcCalibration
60572ff6f6SMatthew Dillon };
61572ff6f6SMatthew Dillon static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
62572ff6f6SMatthew Dillon .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
63572ff6f6SMatthew Dillon .calNumSamples = MIN_CAL_SAMPLES,
64572ff6f6SMatthew Dillon .calCountMax = INIT_LOG_COUNT,
65572ff6f6SMatthew Dillon .calCollect = ar5416AdcDcCalCollect,
66572ff6f6SMatthew Dillon .calPostProc = ar5416AdcDcCalibration
67572ff6f6SMatthew Dillon };
68572ff6f6SMatthew Dillon
69572ff6f6SMatthew Dillon static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
70572ff6f6SMatthew Dillon HAL_BOOL power_off);
71572ff6f6SMatthew Dillon static void ar9285DisablePCIE(struct ath_hal *ah);
72572ff6f6SMatthew Dillon static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
73572ff6f6SMatthew Dillon static void ar9285WriteIni(struct ath_hal *ah,
74572ff6f6SMatthew Dillon const struct ieee80211_channel *chan);
75572ff6f6SMatthew Dillon
76572ff6f6SMatthew Dillon static void
ar9285AniSetup(struct ath_hal * ah)77572ff6f6SMatthew Dillon ar9285AniSetup(struct ath_hal *ah)
78572ff6f6SMatthew Dillon {
79572ff6f6SMatthew Dillon /*
80572ff6f6SMatthew Dillon * These are the parameters from the AR5416 ANI code;
81572ff6f6SMatthew Dillon * they likely need quite a bit of adjustment for the
82572ff6f6SMatthew Dillon * AR9285.
83572ff6f6SMatthew Dillon */
84572ff6f6SMatthew Dillon static const struct ar5212AniParams aniparams = {
85572ff6f6SMatthew Dillon .maxNoiseImmunityLevel = 4, /* levels 0..4 */
86572ff6f6SMatthew Dillon .totalSizeDesired = { -55, -55, -55, -55, -62 },
87572ff6f6SMatthew Dillon .coarseHigh = { -14, -14, -14, -14, -12 },
88572ff6f6SMatthew Dillon .coarseLow = { -64, -64, -64, -64, -70 },
89572ff6f6SMatthew Dillon .firpwr = { -78, -78, -78, -78, -80 },
90572ff6f6SMatthew Dillon .maxSpurImmunityLevel = 7,
91572ff6f6SMatthew Dillon .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
92572ff6f6SMatthew Dillon .maxFirstepLevel = 2, /* levels 0..2 */
93572ff6f6SMatthew Dillon .firstep = { 0, 4, 8 },
94572ff6f6SMatthew Dillon .ofdmTrigHigh = 500,
95572ff6f6SMatthew Dillon .ofdmTrigLow = 200,
96572ff6f6SMatthew Dillon .cckTrigHigh = 200,
97572ff6f6SMatthew Dillon .cckTrigLow = 100,
98572ff6f6SMatthew Dillon .rssiThrHigh = 40,
99572ff6f6SMatthew Dillon .rssiThrLow = 7,
100572ff6f6SMatthew Dillon .period = 100,
101572ff6f6SMatthew Dillon };
102572ff6f6SMatthew Dillon /* NB: disable ANI noise immmunity for reliable RIFS rx */
103572ff6f6SMatthew Dillon AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
104572ff6f6SMatthew Dillon
105572ff6f6SMatthew Dillon ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
106572ff6f6SMatthew Dillon }
107572ff6f6SMatthew Dillon
108572ff6f6SMatthew Dillon static const char * ar9285_lna_conf[] = {
109572ff6f6SMatthew Dillon "LNA1-LNA2",
110572ff6f6SMatthew Dillon "LNA2",
111572ff6f6SMatthew Dillon "LNA1",
112572ff6f6SMatthew Dillon "LNA1+LNA2",
113572ff6f6SMatthew Dillon };
114572ff6f6SMatthew Dillon
115572ff6f6SMatthew Dillon static void
ar9285_eeprom_print_diversity_settings(struct ath_hal * ah)116572ff6f6SMatthew Dillon ar9285_eeprom_print_diversity_settings(struct ath_hal *ah)
117572ff6f6SMatthew Dillon {
118572ff6f6SMatthew Dillon const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
119572ff6f6SMatthew Dillon const MODAL_EEP4K_HEADER *pModal = &ee->ee_base.modalHeader;
120572ff6f6SMatthew Dillon
121572ff6f6SMatthew Dillon ath_hal_printf(ah, "[ath] AR9285 Main LNA config: %s\n",
122572ff6f6SMatthew Dillon ar9285_lna_conf[(pModal->antdiv_ctl2 >> 2) & 0x3]);
123572ff6f6SMatthew Dillon ath_hal_printf(ah, "[ath] AR9285 Alt LNA config: %s\n",
124572ff6f6SMatthew Dillon ar9285_lna_conf[pModal->antdiv_ctl2 & 0x3]);
125572ff6f6SMatthew Dillon ath_hal_printf(ah, "[ath] LNA diversity %s, Diversity %s\n",
126572ff6f6SMatthew Dillon ((pModal->antdiv_ctl1 & 0x1) ? "enabled" : "disabled"),
127572ff6f6SMatthew Dillon ((pModal->antdiv_ctl1 & 0x8) ? "enabled" : "disabled"));
128572ff6f6SMatthew Dillon }
129572ff6f6SMatthew Dillon
130572ff6f6SMatthew Dillon /*
131572ff6f6SMatthew Dillon * Attach for an AR9285 part.
132572ff6f6SMatthew Dillon */
133572ff6f6SMatthew Dillon static struct ath_hal *
ar9285Attach(uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,uint16_t * eepromdata,HAL_OPS_CONFIG * ah_config,HAL_STATUS * status)134572ff6f6SMatthew Dillon ar9285Attach(uint16_t devid, HAL_SOFTC sc,
135572ff6f6SMatthew Dillon HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
136*848b370cSMatthew Dillon HAL_OPS_CONFIG *ah_config,
137572ff6f6SMatthew Dillon HAL_STATUS *status)
138572ff6f6SMatthew Dillon {
139572ff6f6SMatthew Dillon struct ath_hal_9285 *ahp9285;
140572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp;
141572ff6f6SMatthew Dillon struct ath_hal *ah;
142572ff6f6SMatthew Dillon uint32_t val;
143572ff6f6SMatthew Dillon HAL_STATUS ecode;
144572ff6f6SMatthew Dillon HAL_BOOL rfStatus;
145572ff6f6SMatthew Dillon
146572ff6f6SMatthew Dillon HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
147572ff6f6SMatthew Dillon __func__, sc, (void*) st, (void*) sh);
148572ff6f6SMatthew Dillon
149572ff6f6SMatthew Dillon /* NB: memory is returned zero'd */
150572ff6f6SMatthew Dillon ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
151572ff6f6SMatthew Dillon if (ahp9285 == AH_NULL) {
152572ff6f6SMatthew Dillon HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
153572ff6f6SMatthew Dillon "%s: cannot allocate memory for state block\n", __func__);
154572ff6f6SMatthew Dillon *status = HAL_ENOMEM;
155572ff6f6SMatthew Dillon return AH_NULL;
156572ff6f6SMatthew Dillon }
157572ff6f6SMatthew Dillon ahp = AH5212(ahp9285);
158572ff6f6SMatthew Dillon ah = &ahp->ah_priv.h;
159572ff6f6SMatthew Dillon
160572ff6f6SMatthew Dillon ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
161572ff6f6SMatthew Dillon
162572ff6f6SMatthew Dillon /*
163572ff6f6SMatthew Dillon * Use the "local" EEPROM data given to us by the higher layers.
164572ff6f6SMatthew Dillon * This is a private copy out of system flash. The Linux ath9k
165572ff6f6SMatthew Dillon * commit for the initial AR9130 support mentions MMIO flash
166572ff6f6SMatthew Dillon * access is "unreliable." -adrian
167572ff6f6SMatthew Dillon */
168572ff6f6SMatthew Dillon if (eepromdata != AH_NULL) {
169572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
170572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_eepromWrite = NULL;
171572ff6f6SMatthew Dillon ah->ah_eepromdata = eepromdata;
172572ff6f6SMatthew Dillon }
173572ff6f6SMatthew Dillon
174572ff6f6SMatthew Dillon /* override with 9285 specific state */
175572ff6f6SMatthew Dillon AH5416(ah)->ah_initPLL = ar9280InitPLL;
176572ff6f6SMatthew Dillon AH5416(ah)->ah_btCoexSetDiversity = ar9285BTCoexAntennaDiversity;
177572ff6f6SMatthew Dillon
178572ff6f6SMatthew Dillon ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
179572ff6f6SMatthew Dillon ah->ah_configPCIE = ar9285ConfigPCIE;
180572ff6f6SMatthew Dillon ah->ah_disablePCIE = ar9285DisablePCIE;
181572ff6f6SMatthew Dillon ah->ah_setTxPower = ar9285SetTransmitPower;
182572ff6f6SMatthew Dillon ah->ah_setBoardValues = ar9285SetBoardValues;
183572ff6f6SMatthew Dillon ah->ah_btCoexSetParameter = ar9285BTCoexSetParameter;
184572ff6f6SMatthew Dillon ah->ah_divLnaConfGet = ar9285_antdiv_comb_conf_get;
185572ff6f6SMatthew Dillon ah->ah_divLnaConfSet = ar9285_antdiv_comb_conf_set;
186572ff6f6SMatthew Dillon
187572ff6f6SMatthew Dillon AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
188572ff6f6SMatthew Dillon AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
189572ff6f6SMatthew Dillon AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
190572ff6f6SMatthew Dillon AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
191572ff6f6SMatthew Dillon AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
192572ff6f6SMatthew Dillon
193572ff6f6SMatthew Dillon AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
194572ff6f6SMatthew Dillon AH5416(ah)->ah_writeIni = ar9285WriteIni;
195572ff6f6SMatthew Dillon AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
196572ff6f6SMatthew Dillon AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
197572ff6f6SMatthew Dillon
198572ff6f6SMatthew Dillon ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
199572ff6f6SMatthew Dillon
200572ff6f6SMatthew Dillon if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
201572ff6f6SMatthew Dillon /* reset chip */
202572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
203572ff6f6SMatthew Dillon __func__);
204572ff6f6SMatthew Dillon ecode = HAL_EIO;
205572ff6f6SMatthew Dillon goto bad;
206572ff6f6SMatthew Dillon }
207572ff6f6SMatthew Dillon
208572ff6f6SMatthew Dillon if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
209572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
210572ff6f6SMatthew Dillon __func__);
211572ff6f6SMatthew Dillon ecode = HAL_EIO;
212572ff6f6SMatthew Dillon goto bad;
213572ff6f6SMatthew Dillon }
214572ff6f6SMatthew Dillon /* Read Revisions from Chips before taking out of reset */
215572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_SREV);
216572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ATTACH,
217572ff6f6SMatthew Dillon "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
218572ff6f6SMatthew Dillon __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
219572ff6f6SMatthew Dillon MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
220572ff6f6SMatthew Dillon /* NB: include chip type to differentiate from pre-Sowl versions */
221572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macVersion =
222572ff6f6SMatthew Dillon (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
223572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
224572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
225572ff6f6SMatthew Dillon
226572ff6f6SMatthew Dillon /* setup common ini data; rf backends handle remainder */
227572ff6f6SMatthew Dillon if (AR_SREV_KITE_12_OR_LATER(ah)) {
228572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
229572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
230572ff6f6SMatthew Dillon HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
231572ff6f6SMatthew Dillon ar9285PciePhy_clkreq_always_on_L1_v2, 2);
232572ff6f6SMatthew Dillon } else {
233572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
234572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
235572ff6f6SMatthew Dillon HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
236572ff6f6SMatthew Dillon ar9285PciePhy_clkreq_always_on_L1, 2);
237572ff6f6SMatthew Dillon }
238572ff6f6SMatthew Dillon ar5416AttachPCIE(ah);
239572ff6f6SMatthew Dillon
240572ff6f6SMatthew Dillon /* Attach methods that require MAC version/revision info */
241572ff6f6SMatthew Dillon if (AR_SREV_KITE_12_OR_LATER(ah))
242572ff6f6SMatthew Dillon AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
243572ff6f6SMatthew Dillon if (AR_SREV_KITE_11_OR_LATER(ah))
244572ff6f6SMatthew Dillon AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
245572ff6f6SMatthew Dillon
246572ff6f6SMatthew Dillon ecode = ath_hal_v4kEepromAttach(ah);
247572ff6f6SMatthew Dillon if (ecode != HAL_OK)
248572ff6f6SMatthew Dillon goto bad;
249572ff6f6SMatthew Dillon
250572ff6f6SMatthew Dillon if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
251572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
252572ff6f6SMatthew Dillon __func__);
253572ff6f6SMatthew Dillon ecode = HAL_EIO;
254572ff6f6SMatthew Dillon goto bad;
255572ff6f6SMatthew Dillon }
256572ff6f6SMatthew Dillon
257572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
258572ff6f6SMatthew Dillon
259572ff6f6SMatthew Dillon if (!ar5212ChipTest(ah)) {
260572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
261572ff6f6SMatthew Dillon __func__);
262572ff6f6SMatthew Dillon ecode = HAL_ESELFTEST;
263572ff6f6SMatthew Dillon goto bad;
264572ff6f6SMatthew Dillon }
265572ff6f6SMatthew Dillon
266572ff6f6SMatthew Dillon /*
267572ff6f6SMatthew Dillon * Set correct Baseband to analog shift
268572ff6f6SMatthew Dillon * setting to access analog chips.
269572ff6f6SMatthew Dillon */
270572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
271572ff6f6SMatthew Dillon
272572ff6f6SMatthew Dillon /* Read Radio Chip Rev Extract */
273572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
274572ff6f6SMatthew Dillon switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
275572ff6f6SMatthew Dillon case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
276572ff6f6SMatthew Dillon case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
277572ff6f6SMatthew Dillon break;
278572ff6f6SMatthew Dillon default:
279572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
280572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev =
281572ff6f6SMatthew Dillon AR_RAD5133_SREV_MAJOR;
282572ff6f6SMatthew Dillon break;
283572ff6f6SMatthew Dillon }
284572ff6f6SMatthew Dillon #ifdef AH_DEBUG
285572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
286572ff6f6SMatthew Dillon "%s: 5G Radio Chip Rev 0x%02X is not supported by "
287572ff6f6SMatthew Dillon "this driver\n", __func__,
288572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_analog5GhzRev);
289572ff6f6SMatthew Dillon ecode = HAL_ENOTSUPP;
290572ff6f6SMatthew Dillon goto bad;
291572ff6f6SMatthew Dillon #endif
292572ff6f6SMatthew Dillon }
293572ff6f6SMatthew Dillon rfStatus = ar9285RfAttach(ah, &ecode);
294572ff6f6SMatthew Dillon if (!rfStatus) {
295572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
296572ff6f6SMatthew Dillon __func__, ecode);
297572ff6f6SMatthew Dillon goto bad;
298572ff6f6SMatthew Dillon }
299572ff6f6SMatthew Dillon
300572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
301572ff6f6SMatthew Dillon 6);
302572ff6f6SMatthew Dillon
303572ff6f6SMatthew Dillon if (AR_SREV_9285E_20(ah))
304572ff6f6SMatthew Dillon ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
305572ff6f6SMatthew Dillon
306572ff6f6SMatthew Dillon /* setup txgain table */
307572ff6f6SMatthew Dillon switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
308572ff6f6SMatthew Dillon case AR5416_EEP_TXGAIN_HIGH_POWER:
309572ff6f6SMatthew Dillon if (AR_SREV_9285E_20(ah))
310572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp9285->ah_ini_txgain,
311572ff6f6SMatthew Dillon ar9285Modes_XE2_0_high_power, 6);
312572ff6f6SMatthew Dillon else
313572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp9285->ah_ini_txgain,
314572ff6f6SMatthew Dillon ar9285Modes_high_power_tx_gain_v2, 6);
315572ff6f6SMatthew Dillon break;
316572ff6f6SMatthew Dillon case AR5416_EEP_TXGAIN_ORIG:
317572ff6f6SMatthew Dillon if (AR_SREV_9285E_20(ah))
318572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp9285->ah_ini_txgain,
319572ff6f6SMatthew Dillon ar9285Modes_XE2_0_normal_power, 6);
320572ff6f6SMatthew Dillon else
321572ff6f6SMatthew Dillon HAL_INI_INIT(&ahp9285->ah_ini_txgain,
322572ff6f6SMatthew Dillon ar9285Modes_original_tx_gain_v2, 6);
323572ff6f6SMatthew Dillon break;
324572ff6f6SMatthew Dillon default:
325572ff6f6SMatthew Dillon HALASSERT(AH_FALSE);
326572ff6f6SMatthew Dillon goto bad; /* XXX ? try to continue */
327572ff6f6SMatthew Dillon }
328572ff6f6SMatthew Dillon
329572ff6f6SMatthew Dillon /*
330572ff6f6SMatthew Dillon * Got everything we need now to setup the capabilities.
331572ff6f6SMatthew Dillon */
332572ff6f6SMatthew Dillon if (!ar9285FillCapabilityInfo(ah)) {
333572ff6f6SMatthew Dillon ecode = HAL_EEREAD;
334572ff6f6SMatthew Dillon goto bad;
335572ff6f6SMatthew Dillon }
336572ff6f6SMatthew Dillon
337572ff6f6SMatthew Dillon /*
338572ff6f6SMatthew Dillon * Print out the EEPROM antenna configuration mapping.
339572ff6f6SMatthew Dillon * Some devices have a hard-coded LNA configuration profile;
340572ff6f6SMatthew Dillon * others enable diversity.
341572ff6f6SMatthew Dillon */
342572ff6f6SMatthew Dillon ar9285_eeprom_print_diversity_settings(ah);
343572ff6f6SMatthew Dillon
344572ff6f6SMatthew Dillon /* Print out whether the EEPROM settings enable AR9285 diversity */
345572ff6f6SMatthew Dillon if (ar9285_check_div_comb(ah)) {
346572ff6f6SMatthew Dillon ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
347572ff6f6SMatthew Dillon }
348572ff6f6SMatthew Dillon
349572ff6f6SMatthew Dillon /* Disable 11n for the AR2427 */
350572ff6f6SMatthew Dillon if (devid == AR2427_DEVID_PCIE)
351572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
352572ff6f6SMatthew Dillon
353572ff6f6SMatthew Dillon ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
354572ff6f6SMatthew Dillon if (ecode != HAL_OK) {
355572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
356572ff6f6SMatthew Dillon "%s: error getting mac address from EEPROM\n", __func__);
357572ff6f6SMatthew Dillon goto bad;
358572ff6f6SMatthew Dillon }
359572ff6f6SMatthew Dillon /* XXX How about the serial number ? */
360572ff6f6SMatthew Dillon /* Read Reg Domain */
361572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_currentRD =
362572ff6f6SMatthew Dillon ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
363572ff6f6SMatthew Dillon /*
364572ff6f6SMatthew Dillon * For Kite and later chipsets, the following bits are not
365572ff6f6SMatthew Dillon * programmed in EEPROM and so are set as enabled always.
366572ff6f6SMatthew Dillon */
367572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
368572ff6f6SMatthew Dillon
369572ff6f6SMatthew Dillon /*
370572ff6f6SMatthew Dillon * ah_miscMode is populated by ar5416FillCapabilityInfo()
371572ff6f6SMatthew Dillon * starting from griffin. Set here to make sure that
372572ff6f6SMatthew Dillon * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
373572ff6f6SMatthew Dillon * placed into hardware.
374572ff6f6SMatthew Dillon */
375572ff6f6SMatthew Dillon if (ahp->ah_miscMode != 0)
376572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
377572ff6f6SMatthew Dillon
378572ff6f6SMatthew Dillon ar9285AniSetup(ah); /* Anti Noise Immunity */
379572ff6f6SMatthew Dillon
380572ff6f6SMatthew Dillon /* Setup noise floor min/max/nominal values */
381572ff6f6SMatthew Dillon AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
382572ff6f6SMatthew Dillon AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
383572ff6f6SMatthew Dillon AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
384572ff6f6SMatthew Dillon /* XXX no 5ghz values? */
385572ff6f6SMatthew Dillon
386572ff6f6SMatthew Dillon ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
387572ff6f6SMatthew Dillon
388572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
389572ff6f6SMatthew Dillon
390572ff6f6SMatthew Dillon return ah;
391572ff6f6SMatthew Dillon bad:
392572ff6f6SMatthew Dillon if (ah != AH_NULL)
393572ff6f6SMatthew Dillon ah->ah_detach(ah);
394572ff6f6SMatthew Dillon if (status)
395572ff6f6SMatthew Dillon *status = ecode;
396572ff6f6SMatthew Dillon return AH_NULL;
397572ff6f6SMatthew Dillon }
398572ff6f6SMatthew Dillon
399572ff6f6SMatthew Dillon static void
ar9285ConfigPCIE(struct ath_hal * ah,HAL_BOOL restore,HAL_BOOL power_off)400572ff6f6SMatthew Dillon ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
401572ff6f6SMatthew Dillon {
402572ff6f6SMatthew Dillon uint32_t val;
403572ff6f6SMatthew Dillon
404572ff6f6SMatthew Dillon /*
405572ff6f6SMatthew Dillon * This workaround needs some integration work with the HAL
406572ff6f6SMatthew Dillon * config parameters and the if_ath_pci.c glue.
407572ff6f6SMatthew Dillon * Specifically, read the value of the PCI register 0x70c
408572ff6f6SMatthew Dillon * (4 byte PCI config space register) and store it in ath_hal_war70c.
409572ff6f6SMatthew Dillon * Then if it's non-zero, the below WAR would override register
410572ff6f6SMatthew Dillon * 0x570c upon suspend/resume.
411572ff6f6SMatthew Dillon */
412572ff6f6SMatthew Dillon #if 0
413572ff6f6SMatthew Dillon if (AR_SREV_9285E_20(ah)) {
414572ff6f6SMatthew Dillon val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
415572ff6f6SMatthew Dillon if (val) {
416572ff6f6SMatthew Dillon val &= 0xffff00ff;
417572ff6f6SMatthew Dillon val |= 0x6f00;
418572ff6f6SMatthew Dillon OS_REG_WRITE(ah, 0x570c, val);
419572ff6f6SMatthew Dillon }
420572ff6f6SMatthew Dillon }
421572ff6f6SMatthew Dillon #endif
422572ff6f6SMatthew Dillon
423572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
424572ff6f6SMatthew Dillon ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
425572ff6f6SMatthew Dillon OS_DELAY(1000);
426572ff6f6SMatthew Dillon }
427572ff6f6SMatthew Dillon
428572ff6f6SMatthew Dillon /*
429572ff6f6SMatthew Dillon * Set PCIe workaround bits
430572ff6f6SMatthew Dillon *
431572ff6f6SMatthew Dillon * NOTE:
432572ff6f6SMatthew Dillon *
433572ff6f6SMatthew Dillon * In Merlin and Kite, bit 14 in WA register (disable L1) should only
434572ff6f6SMatthew Dillon * be set when device enters D3 and be cleared when device comes back
435572ff6f6SMatthew Dillon * to D0.
436572ff6f6SMatthew Dillon */
437572ff6f6SMatthew Dillon if (power_off) { /* Power-off */
438572ff6f6SMatthew Dillon OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
439572ff6f6SMatthew Dillon
440572ff6f6SMatthew Dillon val = OS_REG_READ(ah, AR_WA);
441572ff6f6SMatthew Dillon
442572ff6f6SMatthew Dillon /*
443572ff6f6SMatthew Dillon * Disable bit 6 and 7 before entering D3 to prevent
444572ff6f6SMatthew Dillon * system hang.
445572ff6f6SMatthew Dillon */
446572ff6f6SMatthew Dillon val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
447572ff6f6SMatthew Dillon
448572ff6f6SMatthew Dillon /*
449572ff6f6SMatthew Dillon * See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
450572ff6f6SMatthew Dillon *
451572ff6f6SMatthew Dillon * XXX The reference HAL does it this way - it only sets
452572ff6f6SMatthew Dillon * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
453572ff6f6SMatthew Dillon * which it (currently) isn't. So the following statement
454572ff6f6SMatthew Dillon * is currently a NOP.
455572ff6f6SMatthew Dillon */
456572ff6f6SMatthew Dillon if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
457572ff6f6SMatthew Dillon val |= AR_WA_D3_L1_DISABLE;
458572ff6f6SMatthew Dillon
459572ff6f6SMatthew Dillon if (AR_SREV_9285E_20(ah))
460572ff6f6SMatthew Dillon val |= AR_WA_BIT23;
461572ff6f6SMatthew Dillon
462572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_WA, val);
463572ff6f6SMatthew Dillon } else { /* Power-on */
464572ff6f6SMatthew Dillon val = AR9285_WA_DEFAULT;
465572ff6f6SMatthew Dillon /*
466572ff6f6SMatthew Dillon * See note above: make sure L1_DISABLE is not set.
467572ff6f6SMatthew Dillon */
468572ff6f6SMatthew Dillon val &= (~AR_WA_D3_L1_DISABLE);
469572ff6f6SMatthew Dillon
470572ff6f6SMatthew Dillon /* Software workaroud for ASPM system hang. */
471572ff6f6SMatthew Dillon val |= (AR_WA_BIT6 | AR_WA_BIT7);
472572ff6f6SMatthew Dillon
473572ff6f6SMatthew Dillon if (AR_SREV_9285E_20(ah))
474572ff6f6SMatthew Dillon val |= AR_WA_BIT23;
475572ff6f6SMatthew Dillon
476572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_WA, val);
477572ff6f6SMatthew Dillon
478572ff6f6SMatthew Dillon /* set bit 19 to allow forcing of pcie core into L1 state */
479572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
480572ff6f6SMatthew Dillon }
481572ff6f6SMatthew Dillon }
482572ff6f6SMatthew Dillon
483572ff6f6SMatthew Dillon static void
ar9285DisablePCIE(struct ath_hal * ah)484572ff6f6SMatthew Dillon ar9285DisablePCIE(struct ath_hal *ah)
485572ff6f6SMatthew Dillon {
486572ff6f6SMatthew Dillon }
487572ff6f6SMatthew Dillon
488572ff6f6SMatthew Dillon static void
ar9285WriteIni(struct ath_hal * ah,const struct ieee80211_channel * chan)489572ff6f6SMatthew Dillon ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
490572ff6f6SMatthew Dillon {
491572ff6f6SMatthew Dillon u_int modesIndex, freqIndex;
492572ff6f6SMatthew Dillon int regWrites = 0;
493572ff6f6SMatthew Dillon
494572ff6f6SMatthew Dillon /* Setup the indices for the next set of register array writes */
495572ff6f6SMatthew Dillon /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
496572ff6f6SMatthew Dillon freqIndex = 2;
497572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_HT40(chan))
498572ff6f6SMatthew Dillon modesIndex = 3;
499572ff6f6SMatthew Dillon else if (IEEE80211_IS_CHAN_108G(chan))
500572ff6f6SMatthew Dillon modesIndex = 5;
501572ff6f6SMatthew Dillon else
502572ff6f6SMatthew Dillon modesIndex = 4;
503572ff6f6SMatthew Dillon
504572ff6f6SMatthew Dillon /* Set correct Baseband to analog shift setting to access analog chips. */
505572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
506572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
507572ff6f6SMatthew Dillon regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
508572ff6f6SMatthew Dillon modesIndex, regWrites);
509572ff6f6SMatthew Dillon if (AR_SREV_KITE_12_OR_LATER(ah)) {
510572ff6f6SMatthew Dillon regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
511572ff6f6SMatthew Dillon modesIndex, regWrites);
512572ff6f6SMatthew Dillon }
513572ff6f6SMatthew Dillon regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
514572ff6f6SMatthew Dillon 1, regWrites);
515572ff6f6SMatthew Dillon }
516572ff6f6SMatthew Dillon
517572ff6f6SMatthew Dillon /*
518572ff6f6SMatthew Dillon * Fill all software cached or static hardware state information.
519572ff6f6SMatthew Dillon * Return failure if capabilities are to come from EEPROM and
520572ff6f6SMatthew Dillon * cannot be read.
521572ff6f6SMatthew Dillon */
522572ff6f6SMatthew Dillon static HAL_BOOL
ar9285FillCapabilityInfo(struct ath_hal * ah)523572ff6f6SMatthew Dillon ar9285FillCapabilityInfo(struct ath_hal *ah)
524572ff6f6SMatthew Dillon {
525572ff6f6SMatthew Dillon HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
526572ff6f6SMatthew Dillon
527572ff6f6SMatthew Dillon if (!ar5416FillCapabilityInfo(ah))
528572ff6f6SMatthew Dillon return AH_FALSE;
529572ff6f6SMatthew Dillon pCap->halNumGpioPins = 12;
530572ff6f6SMatthew Dillon pCap->halWowSupport = AH_TRUE;
531572ff6f6SMatthew Dillon pCap->halWowMatchPatternExact = AH_TRUE;
532572ff6f6SMatthew Dillon #if 0
533572ff6f6SMatthew Dillon pCap->halWowMatchPatternDword = AH_TRUE;
534572ff6f6SMatthew Dillon #endif
535572ff6f6SMatthew Dillon /* AR9285 has 2 antennas but is a 1x1 stream device */
536572ff6f6SMatthew Dillon pCap->halTxStreams = 1;
537572ff6f6SMatthew Dillon pCap->halRxStreams = 1;
538572ff6f6SMatthew Dillon
539572ff6f6SMatthew Dillon if (ar9285_check_div_comb(ah))
540572ff6f6SMatthew Dillon pCap->halAntDivCombSupport = AH_TRUE;
541572ff6f6SMatthew Dillon
542572ff6f6SMatthew Dillon pCap->halCSTSupport = AH_TRUE;
543572ff6f6SMatthew Dillon pCap->halRifsRxSupport = AH_TRUE;
544572ff6f6SMatthew Dillon pCap->halRifsTxSupport = AH_TRUE;
545572ff6f6SMatthew Dillon pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
546572ff6f6SMatthew Dillon pCap->halExtChanDfsSupport = AH_TRUE;
547572ff6f6SMatthew Dillon pCap->halUseCombinedRadarRssi = AH_TRUE;
548572ff6f6SMatthew Dillon #if 1
549572ff6f6SMatthew Dillon /* XXX bluetooth */
550572ff6f6SMatthew Dillon pCap->halBtCoexSupport = AH_TRUE;
551572ff6f6SMatthew Dillon #endif
552572ff6f6SMatthew Dillon pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
553572ff6f6SMatthew Dillon pCap->hal4kbSplitTransSupport = AH_FALSE;
554572ff6f6SMatthew Dillon /* Disable this so Block-ACK works correctly */
555572ff6f6SMatthew Dillon pCap->halHasRxSelfLinkedTail = AH_FALSE;
556572ff6f6SMatthew Dillon pCap->halMbssidAggrSupport = AH_TRUE;
557572ff6f6SMatthew Dillon pCap->hal4AddrAggrSupport = AH_TRUE;
558572ff6f6SMatthew Dillon pCap->halSpectralScanSupport = AH_TRUE;
559572ff6f6SMatthew Dillon pCap->halRxUsingLnaMixing = AH_TRUE;
560572ff6f6SMatthew Dillon
561572ff6f6SMatthew Dillon if (AR_SREV_KITE_12_OR_LATER(ah))
562572ff6f6SMatthew Dillon pCap->halPSPollBroken = AH_FALSE;
563572ff6f6SMatthew Dillon
564572ff6f6SMatthew Dillon /* Only RX STBC supported */
565572ff6f6SMatthew Dillon pCap->halRxStbcSupport = 1;
566572ff6f6SMatthew Dillon pCap->halTxStbcSupport = 0;
567572ff6f6SMatthew Dillon
568572ff6f6SMatthew Dillon return AH_TRUE;
569572ff6f6SMatthew Dillon }
570572ff6f6SMatthew Dillon
571572ff6f6SMatthew Dillon static const char*
ar9285Probe(uint16_t vendorid,uint16_t devid)572572ff6f6SMatthew Dillon ar9285Probe(uint16_t vendorid, uint16_t devid)
573572ff6f6SMatthew Dillon {
574572ff6f6SMatthew Dillon if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
575572ff6f6SMatthew Dillon return "Atheros 9285";
576572ff6f6SMatthew Dillon if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE))
577572ff6f6SMatthew Dillon return "Atheros 2427";
578572ff6f6SMatthew Dillon
579572ff6f6SMatthew Dillon return AH_NULL;
580572ff6f6SMatthew Dillon }
581572ff6f6SMatthew Dillon AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
582