1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 #include <sys/interrupt.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/rman.h> 45 46 #include <net/if.h> 47 #include <net/ifq_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <net/bpf.h> 54 55 #include <net/if_types.h> 56 #include <net/vlan/if_vlan_var.h> 57 58 #include <netinet/in_systm.h> 59 #include <netinet/in.h> 60 #include <netinet/ip.h> 61 62 #include <bus/pci/pcireg.h> 63 #include <bus/pci/pcivar.h> 64 #include "pcidevs.h" 65 66 #include <dev/netif/mii_layer/mii.h> 67 #include <dev/netif/mii_layer/miivar.h> 68 69 #include <dev/netif/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 73 74 /* "controller miibus0" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78 79 static struct bfe_type bfe_devs[] = { 80 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 81 "Broadcom BCM4401 Fast Ethernet" }, 82 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 83 "Broadcom BCM4401-B0 Fast Ethernet" }, 84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402, 85 "Broadcom BCM4402 Fast Ethernet" }, 86 { 0, 0, NULL } 87 }; 88 89 static int bfe_probe(device_t); 90 static int bfe_attach(device_t); 91 static int bfe_detach(device_t); 92 static void bfe_intr(void *); 93 static void bfe_start(struct ifnet *, struct ifaltq_subque *); 94 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 95 static void bfe_init(void *); 96 static void bfe_stop(struct bfe_softc *); 97 static void bfe_watchdog(struct ifnet *); 98 static void bfe_shutdown(device_t); 99 static void bfe_tick(void *); 100 static void bfe_txeof(struct bfe_softc *); 101 static void bfe_rxeof(struct bfe_softc *); 102 static void bfe_set_rx_mode(struct bfe_softc *); 103 static int bfe_list_rx_init(struct bfe_softc *); 104 static int bfe_newbuf(struct bfe_softc *, int, int); 105 static void bfe_setup_rxdesc(struct bfe_softc *, int); 106 static void bfe_rx_ring_free(struct bfe_softc *); 107 108 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 109 static int bfe_ifmedia_upd(struct ifnet *); 110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 111 static int bfe_miibus_readreg(device_t, int, int); 112 static int bfe_miibus_writereg(device_t, int, int, int); 113 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 114 u_long, const int); 115 static void bfe_get_config(struct bfe_softc *sc); 116 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 117 static void bfe_stats_update(struct bfe_softc *); 118 static void bfe_clear_stats (struct bfe_softc *); 119 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 120 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 121 static int bfe_resetphy(struct bfe_softc *); 122 static int bfe_setupphy(struct bfe_softc *); 123 static void bfe_chip_reset(struct bfe_softc *); 124 static void bfe_chip_halt(struct bfe_softc *); 125 static void bfe_core_reset(struct bfe_softc *); 126 static void bfe_core_disable(struct bfe_softc *); 127 static int bfe_dma_alloc(device_t); 128 static void bfe_dma_free(struct bfe_softc *); 129 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 130 131 static device_method_t bfe_methods[] = { 132 /* Device interface */ 133 DEVMETHOD(device_probe, bfe_probe), 134 DEVMETHOD(device_attach, bfe_attach), 135 DEVMETHOD(device_detach, bfe_detach), 136 DEVMETHOD(device_shutdown, bfe_shutdown), 137 138 /* bus interface */ 139 DEVMETHOD(bus_print_child, bus_generic_print_child), 140 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 141 142 /* MII interface */ 143 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 144 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 145 146 DEVMETHOD_END 147 }; 148 149 static driver_t bfe_driver = { 150 "bfe", 151 bfe_methods, 152 sizeof(struct bfe_softc) 153 }; 154 155 static devclass_t bfe_devclass; 156 157 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, NULL, NULL); 158 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, NULL, NULL); 159 160 /* 161 * Probe for a Broadcom 4401 chip. 162 */ 163 static int 164 bfe_probe(device_t dev) 165 { 166 struct bfe_type *t; 167 uint16_t vendor, product; 168 169 vendor = pci_get_vendor(dev); 170 product = pci_get_device(dev); 171 172 for (t = bfe_devs; t->bfe_name != NULL; t++) { 173 if (vendor == t->bfe_vid && product == t->bfe_did) { 174 device_set_desc(dev, t->bfe_name); 175 return(0); 176 } 177 } 178 179 return(ENXIO); 180 } 181 182 static int 183 bfe_dma_alloc(device_t dev) 184 { 185 struct bfe_softc *sc = device_get_softc(dev); 186 bus_dmamem_t dmem; 187 int error, i, tx_pos = 0, rx_pos = 0; 188 189 /* 190 * Parent tag. Apparently the chip cannot handle any DMA address 191 * greater than BFE_BUS_SPACE_MAXADDR (1GB). 192 */ 193 error = bus_dma_tag_create(NULL, /* parent */ 194 1, 0, /* alignment, boundary */ 195 BFE_BUS_SPACE_MAXADDR, /* lowaddr */ 196 BUS_SPACE_MAXADDR, /* highaddr */ 197 NULL, NULL, /* filter, filterarg */ 198 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 199 0, /* num of segments */ 200 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 201 0, /* flags */ 202 &sc->bfe_parent_tag); 203 if (error) { 204 device_printf(dev, "could not allocate parent dma tag\n"); 205 return(error); 206 } 207 208 /* Allocate TX ring */ 209 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0, 210 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 211 BFE_TX_LIST_SIZE, 212 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 213 if (error) { 214 device_printf(dev, "could not allocate TX list\n"); 215 return(error); 216 } 217 sc->bfe_tx_tag = dmem.dmem_tag; 218 sc->bfe_tx_map = dmem.dmem_map; 219 sc->bfe_tx_list = dmem.dmem_addr; 220 sc->bfe_tx_dma = dmem.dmem_busaddr; 221 222 /* Allocate RX ring */ 223 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0, 224 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 225 BFE_RX_LIST_SIZE, 226 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 227 if (error) { 228 device_printf(dev, "could not allocate RX list\n"); 229 return(error); 230 } 231 sc->bfe_rx_tag = dmem.dmem_tag; 232 sc->bfe_rx_map = dmem.dmem_map; 233 sc->bfe_rx_list = dmem.dmem_addr; 234 sc->bfe_rx_dma = dmem.dmem_busaddr; 235 236 /* Tag for RX mbufs */ 237 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0, 238 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 239 NULL, NULL, 240 MCLBYTES, 1, MCLBYTES, 241 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 242 &sc->bfe_rxbuf_tag); 243 if (error) { 244 device_printf(dev, "could not allocate dma tag for RX mbufs\n"); 245 return(error); 246 } 247 248 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK, 249 &sc->bfe_rx_tmpmap); 250 if (error) { 251 device_printf(dev, "could not create RX mbuf tmp map\n"); 252 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 253 sc->bfe_rxbuf_tag = NULL; 254 return error; 255 } 256 257 /* Allocate dma maps for RX list */ 258 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 259 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK, 260 &sc->bfe_rx_ring[i].bfe_map); 261 if (error) { 262 rx_pos = i; 263 device_printf(dev, "cannot create DMA map for RX\n"); 264 goto ring_fail; 265 } 266 } 267 rx_pos = BFE_RX_LIST_CNT; 268 269 /* Tag for TX mbufs */ 270 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0, 271 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 272 NULL, NULL, 273 MCLBYTES, BFE_MAXSEGS, MCLBYTES, 274 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 275 &sc->bfe_txbuf_tag); 276 if (error) { 277 device_printf(dev, "could not allocate dma tag for TX mbufs\n"); 278 return(error); 279 } 280 281 /* Allocate dmamaps for TX list */ 282 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 283 error = bus_dmamap_create(sc->bfe_txbuf_tag, BUS_DMA_WAITOK, 284 &sc->bfe_tx_ring[i].bfe_map); 285 if (error) { 286 tx_pos = i; 287 device_printf(dev, "cannot create DMA map for TX\n"); 288 goto ring_fail; 289 } 290 } 291 292 return(0); 293 294 ring_fail: 295 if (sc->bfe_rxbuf_tag != NULL) { 296 for (i = 0; i < rx_pos; ++i) { 297 bus_dmamap_destroy(sc->bfe_rxbuf_tag, 298 sc->bfe_rx_ring[i].bfe_map); 299 } 300 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap); 301 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 302 sc->bfe_rxbuf_tag = NULL; 303 } 304 305 if (sc->bfe_txbuf_tag != NULL) { 306 for (i = 0; i < tx_pos; ++i) { 307 bus_dmamap_destroy(sc->bfe_txbuf_tag, 308 sc->bfe_tx_ring[i].bfe_map); 309 } 310 bus_dma_tag_destroy(sc->bfe_txbuf_tag); 311 sc->bfe_txbuf_tag = NULL; 312 } 313 return error; 314 } 315 316 static int 317 bfe_attach(device_t dev) 318 { 319 struct ifnet *ifp; 320 struct bfe_softc *sc; 321 int error = 0, rid; 322 323 sc = device_get_softc(dev); 324 325 sc->bfe_dev = dev; 326 callout_init(&sc->bfe_stat_timer); 327 328 #ifndef BURN_BRIDGES 329 /* 330 * Handle power management nonsense. 331 */ 332 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 333 uint32_t membase, irq; 334 335 /* Save important PCI config data. */ 336 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 337 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 338 339 /* Reset the power state. */ 340 device_printf(dev, "chip is in D%d power mode" 341 " -- setting to D0\n", pci_get_powerstate(dev)); 342 343 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 344 345 /* Restore PCI config data. */ 346 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 347 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 348 } 349 #endif /* !BURN_BRIDGE */ 350 351 /* 352 * Map control/status registers. 353 */ 354 pci_enable_busmaster(dev); 355 356 rid = BFE_PCI_MEMLO; 357 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 358 RF_ACTIVE); 359 if (sc->bfe_res == NULL) { 360 device_printf(dev, "couldn't map memory\n"); 361 return ENXIO; 362 } 363 364 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 365 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 366 367 /* Allocate interrupt */ 368 rid = 0; 369 370 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 371 RF_SHAREABLE | RF_ACTIVE); 372 if (sc->bfe_irq == NULL) { 373 device_printf(dev, "couldn't map interrupt\n"); 374 error = ENXIO; 375 goto fail; 376 } 377 378 error = bfe_dma_alloc(dev); 379 if (error != 0) { 380 device_printf(dev, "failed to allocate DMA resources\n"); 381 goto fail; 382 } 383 384 /* Set up ifnet structure */ 385 ifp = &sc->arpcom.ac_if; 386 ifp->if_softc = sc; 387 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 389 ifp->if_ioctl = bfe_ioctl; 390 ifp->if_start = bfe_start; 391 ifp->if_watchdog = bfe_watchdog; 392 ifp->if_init = bfe_init; 393 ifp->if_mtu = ETHERMTU; 394 ifp->if_baudrate = 100000000; 395 ifp->if_capabilities |= IFCAP_VLAN_MTU; 396 ifp->if_capenable |= IFCAP_VLAN_MTU; 397 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 398 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 399 ifq_set_ready(&ifp->if_snd); 400 401 bfe_get_config(sc); 402 403 /* Reset the chip and turn on the PHY */ 404 bfe_chip_reset(sc); 405 406 if (mii_phy_probe(dev, &sc->bfe_miibus, 407 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 408 device_printf(dev, "MII without any PHY!\n"); 409 error = ENXIO; 410 goto fail; 411 } 412 413 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 414 415 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bfe_irq)); 416 417 /* 418 * Hook interrupt last to avoid having to lock softc 419 */ 420 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE, 421 bfe_intr, sc, &sc->bfe_intrhand, 422 sc->arpcom.ac_if.if_serializer); 423 424 if (error) { 425 ether_ifdetach(ifp); 426 device_printf(dev, "couldn't set up irq\n"); 427 goto fail; 428 } 429 return 0; 430 fail: 431 bfe_detach(dev); 432 return(error); 433 } 434 435 static int 436 bfe_detach(device_t dev) 437 { 438 struct bfe_softc *sc = device_get_softc(dev); 439 struct ifnet *ifp = &sc->arpcom.ac_if; 440 441 if (device_is_attached(dev)) { 442 lwkt_serialize_enter(ifp->if_serializer); 443 bfe_stop(sc); 444 bfe_chip_reset(sc); 445 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 446 lwkt_serialize_exit(ifp->if_serializer); 447 448 ether_ifdetach(ifp); 449 } 450 if (sc->bfe_miibus != NULL) 451 device_delete_child(dev, sc->bfe_miibus); 452 bus_generic_detach(dev); 453 454 if (sc->bfe_irq != NULL) 455 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 456 457 if (sc->bfe_res != NULL) { 458 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 459 sc->bfe_res); 460 } 461 bfe_dma_free(sc); 462 463 return(0); 464 } 465 466 /* 467 * Stop all chip I/O so that the kernel's probe routines don't 468 * get confused by errant DMAs when rebooting. 469 */ 470 static void 471 bfe_shutdown(device_t dev) 472 { 473 struct bfe_softc *sc = device_get_softc(dev); 474 struct ifnet *ifp = &sc->arpcom.ac_if; 475 476 lwkt_serialize_enter(ifp->if_serializer); 477 bfe_stop(sc); 478 lwkt_serialize_exit(ifp->if_serializer); 479 } 480 481 static int 482 bfe_miibus_readreg(device_t dev, int phy, int reg) 483 { 484 struct bfe_softc *sc; 485 uint32_t ret; 486 487 sc = device_get_softc(dev); 488 if (phy != sc->bfe_phyaddr) 489 return(0); 490 bfe_readphy(sc, reg, &ret); 491 492 return(ret); 493 } 494 495 static int 496 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 497 { 498 struct bfe_softc *sc; 499 500 sc = device_get_softc(dev); 501 if (phy != sc->bfe_phyaddr) 502 return(0); 503 bfe_writephy(sc, reg, val); 504 505 return(0); 506 } 507 508 static void 509 bfe_tx_ring_free(struct bfe_softc *sc) 510 { 511 int i; 512 513 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 514 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 515 bus_dmamap_unload(sc->bfe_txbuf_tag, 516 sc->bfe_tx_ring[i].bfe_map); 517 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 518 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 519 } 520 } 521 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 522 } 523 524 static void 525 bfe_rx_ring_free(struct bfe_softc *sc) 526 { 527 int i; 528 529 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 530 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 531 bus_dmamap_unload(sc->bfe_rxbuf_tag, 532 sc->bfe_rx_ring[i].bfe_map); 533 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 534 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 535 } 536 } 537 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 538 } 539 540 static int 541 bfe_list_rx_init(struct bfe_softc *sc) 542 { 543 int i, error; 544 545 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 546 error = bfe_newbuf(sc, i, 1); 547 if (error) 548 return(error); 549 } 550 551 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 552 553 sc->bfe_rx_cons = 0; 554 555 return(0); 556 } 557 558 static int 559 bfe_newbuf(struct bfe_softc *sc, int c, int init) 560 { 561 struct bfe_data *r; 562 bus_dmamap_t map; 563 bus_dma_segment_t seg; 564 struct mbuf *m; 565 int error, nsegs; 566 567 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 568 if (m == NULL) 569 return ENOBUFS; 570 m->m_len = m->m_pkthdr.len = MCLBYTES; 571 572 error = bus_dmamap_load_mbuf_segment(sc->bfe_rxbuf_tag, 573 sc->bfe_rx_tmpmap, m, 574 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 575 if (error) { 576 m_freem(m); 577 if (init) 578 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 579 return error; 580 } 581 582 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT); 583 r = &sc->bfe_rx_ring[c]; 584 585 if (r->bfe_mbuf != NULL) 586 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map); 587 588 map = r->bfe_map; 589 r->bfe_map = sc->bfe_rx_tmpmap; 590 sc->bfe_rx_tmpmap = map; 591 592 r->bfe_mbuf = m; 593 r->bfe_paddr = seg.ds_addr; 594 595 bfe_setup_rxdesc(sc, c); 596 return 0; 597 } 598 599 static void 600 bfe_setup_rxdesc(struct bfe_softc *sc, int c) 601 { 602 struct bfe_rxheader *rx_header; 603 struct mbuf *m; 604 struct bfe_desc *d; 605 struct bfe_data *r; 606 uint32_t ctrl; 607 608 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT); 609 r = &sc->bfe_rx_ring[c]; 610 d = &sc->bfe_rx_list[c]; 611 612 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0); 613 614 m = r->bfe_mbuf; 615 rx_header = mtod(m, struct bfe_rxheader *); 616 rx_header->len = 0; 617 rx_header->flags = 0; 618 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 619 620 ctrl = ETHER_MAX_LEN + 32; 621 if (c == BFE_RX_LIST_CNT - 1) 622 ctrl |= BFE_DESC_EOT; 623 624 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA; 625 d->bfe_ctrl = ctrl; 626 } 627 628 static void 629 bfe_get_config(struct bfe_softc *sc) 630 { 631 uint8_t eeprom[128]; 632 633 bfe_read_eeprom(sc, eeprom); 634 635 sc->arpcom.ac_enaddr[0] = eeprom[79]; 636 sc->arpcom.ac_enaddr[1] = eeprom[78]; 637 sc->arpcom.ac_enaddr[2] = eeprom[81]; 638 sc->arpcom.ac_enaddr[3] = eeprom[80]; 639 sc->arpcom.ac_enaddr[4] = eeprom[83]; 640 sc->arpcom.ac_enaddr[5] = eeprom[82]; 641 642 sc->bfe_phyaddr = eeprom[90] & 0x1f; 643 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 644 645 sc->bfe_core_unit = 0; 646 sc->bfe_dma_offset = BFE_PCI_DMA; 647 } 648 649 static void 650 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 651 { 652 uint32_t bar_orig, val; 653 654 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 655 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 656 657 val = CSR_READ_4(sc, BFE_SBINTVEC); 658 val |= cores; 659 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 660 661 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 662 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 663 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 664 665 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 666 } 667 668 static void 669 bfe_clear_stats(struct bfe_softc *sc) 670 { 671 u_long reg; 672 673 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 674 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 675 CSR_READ_4(sc, reg); 676 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 677 CSR_READ_4(sc, reg); 678 } 679 680 static int 681 bfe_resetphy(struct bfe_softc *sc) 682 { 683 uint32_t val; 684 685 bfe_writephy(sc, 0, BMCR_RESET); 686 DELAY(100); 687 bfe_readphy(sc, 0, &val); 688 if (val & BMCR_RESET) { 689 if_printf(&sc->arpcom.ac_if, 690 "PHY Reset would not complete.\n"); 691 return(ENXIO); 692 } 693 return(0); 694 } 695 696 static void 697 bfe_chip_halt(struct bfe_softc *sc) 698 { 699 /* disable interrupts - not that it actually does..*/ 700 CSR_WRITE_4(sc, BFE_IMASK, 0); 701 CSR_READ_4(sc, BFE_IMASK); 702 703 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 704 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 705 706 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 707 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 708 DELAY(10); 709 } 710 711 static void 712 bfe_chip_reset(struct bfe_softc *sc) 713 { 714 uint32_t val; 715 716 /* Set the interrupt vector for the enet core */ 717 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 718 719 /* is core up? */ 720 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 721 if (val == BFE_CLOCK) { 722 /* It is, so shut it down */ 723 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 724 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 725 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 726 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 727 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 728 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 729 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 730 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 731 sc->bfe_rx_cons = 0; 732 } 733 734 bfe_core_reset(sc); 735 bfe_clear_stats(sc); 736 737 /* 738 * We want the phy registers to be accessible even when 739 * the driver is "downed" so initialize MDC preamble, frequency, 740 * and whether internal or external phy here. 741 */ 742 743 /* 4402 has 62.5Mhz SB clock and internal phy */ 744 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 745 746 /* Internal or external PHY? */ 747 val = CSR_READ_4(sc, BFE_DEVCTRL); 748 if (!(val & BFE_IPP)) 749 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 750 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 751 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 752 DELAY(100); 753 } 754 755 /* Enable CRC32 generation and set proper LED modes */ 756 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 757 758 /* Reset or clear powerdown control bit */ 759 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 760 761 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 762 BFE_LAZY_FC_MASK)); 763 764 /* 765 * We don't want lazy interrupts, so just send them at the end of a 766 * frame, please 767 */ 768 BFE_OR(sc, BFE_RCV_LAZY, 0); 769 770 /* Set max lengths, accounting for VLAN tags */ 771 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 772 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 773 774 /* Set watermark XXX - magic */ 775 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 776 777 /* 778 * Initialise DMA channels - not forgetting dma addresses need to be 779 * added to BFE_PCI_DMA 780 */ 781 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 782 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 783 784 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 785 BFE_RX_CTRL_ENABLE); 786 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 787 788 bfe_resetphy(sc); 789 bfe_setupphy(sc); 790 } 791 792 static void 793 bfe_core_disable(struct bfe_softc *sc) 794 { 795 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 796 return; 797 798 /* 799 * Set reject, wait for it set, then wait for the core to stop being busy 800 * Then set reset and reject and enable the clocks 801 */ 802 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 803 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 804 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 806 BFE_RESET)); 807 CSR_READ_4(sc, BFE_SBTMSLOW); 808 DELAY(10); 809 /* Leave reset and reject set */ 810 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 811 DELAY(10); 812 } 813 814 static void 815 bfe_core_reset(struct bfe_softc *sc) 816 { 817 uint32_t val; 818 819 /* Disable the core */ 820 bfe_core_disable(sc); 821 822 /* and bring it back up */ 823 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 824 CSR_READ_4(sc, BFE_SBTMSLOW); 825 DELAY(10); 826 827 /* Chip bug, clear SERR, IB and TO if they are set. */ 828 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 829 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 830 val = CSR_READ_4(sc, BFE_SBIMSTATE); 831 if (val & (BFE_IBE | BFE_TO)) 832 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 833 834 /* Clear reset and allow it to move through the core */ 835 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 836 CSR_READ_4(sc, BFE_SBTMSLOW); 837 DELAY(10); 838 839 /* Leave the clock set */ 840 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 841 CSR_READ_4(sc, BFE_SBTMSLOW); 842 DELAY(10); 843 } 844 845 static void 846 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 847 { 848 uint32_t val; 849 850 val = ((uint32_t) data[2]) << 24; 851 val |= ((uint32_t) data[3]) << 16; 852 val |= ((uint32_t) data[4]) << 8; 853 val |= ((uint32_t) data[5]); 854 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 855 val = (BFE_CAM_HI_VALID | 856 (((uint32_t) data[0]) << 8) | 857 (((uint32_t) data[1]))); 858 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 859 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 860 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 861 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 862 } 863 864 static void 865 bfe_set_rx_mode(struct bfe_softc *sc) 866 { 867 struct ifnet *ifp = &sc->arpcom.ac_if; 868 struct ifmultiaddr *ifma; 869 uint32_t val; 870 int i = 0; 871 872 val = CSR_READ_4(sc, BFE_RXCONF); 873 874 if (ifp->if_flags & IFF_PROMISC) 875 val |= BFE_RXCONF_PROMISC; 876 else 877 val &= ~BFE_RXCONF_PROMISC; 878 879 if (ifp->if_flags & IFF_BROADCAST) 880 val &= ~BFE_RXCONF_DBCAST; 881 else 882 val |= BFE_RXCONF_DBCAST; 883 884 885 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 886 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 887 888 if (ifp->if_flags & IFF_ALLMULTI) { 889 val |= BFE_RXCONF_ALLMULTI; 890 } else { 891 val &= ~BFE_RXCONF_ALLMULTI; 892 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 893 if (ifma->ifma_addr->sa_family != AF_LINK) 894 continue; 895 bfe_cam_write(sc, 896 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 897 } 898 } 899 900 CSR_WRITE_4(sc, BFE_RXCONF, val); 901 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 902 } 903 904 static void 905 bfe_dma_free(struct bfe_softc *sc) 906 { 907 int i; 908 909 if (sc->bfe_tx_tag != NULL) { 910 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 911 if (sc->bfe_tx_list != NULL) { 912 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 913 sc->bfe_tx_map); 914 sc->bfe_tx_list = NULL; 915 } 916 bus_dma_tag_destroy(sc->bfe_tx_tag); 917 sc->bfe_tx_tag = NULL; 918 } 919 920 if (sc->bfe_rx_tag != NULL) { 921 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 922 if (sc->bfe_rx_list != NULL) { 923 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 924 sc->bfe_rx_map); 925 sc->bfe_rx_list = NULL; 926 } 927 bus_dma_tag_destroy(sc->bfe_rx_tag); 928 sc->bfe_rx_tag = NULL; 929 } 930 931 if (sc->bfe_txbuf_tag != NULL) { 932 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 933 bus_dmamap_destroy(sc->bfe_txbuf_tag, 934 sc->bfe_tx_ring[i].bfe_map); 935 } 936 bus_dma_tag_destroy(sc->bfe_txbuf_tag); 937 sc->bfe_txbuf_tag = NULL; 938 } 939 940 if (sc->bfe_rxbuf_tag != NULL) { 941 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 942 bus_dmamap_destroy(sc->bfe_rxbuf_tag, 943 sc->bfe_rx_ring[i].bfe_map); 944 } 945 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap); 946 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 947 sc->bfe_rxbuf_tag = NULL; 948 } 949 950 if (sc->bfe_parent_tag != NULL) { 951 bus_dma_tag_destroy(sc->bfe_parent_tag); 952 sc->bfe_parent_tag = NULL; 953 } 954 } 955 956 static void 957 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 958 { 959 long i; 960 uint16_t *ptr = (uint16_t *)data; 961 962 for (i = 0; i < 128; i += 2) 963 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 964 } 965 966 static int 967 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 968 u_long timeout, const int clear) 969 { 970 u_long i; 971 972 for (i = 0; i < timeout; i++) { 973 uint32_t val = CSR_READ_4(sc, reg); 974 975 if (clear && !(val & bit)) 976 break; 977 if (!clear && (val & bit)) 978 break; 979 DELAY(10); 980 } 981 if (i == timeout) { 982 if_printf(&sc->arpcom.ac_if, 983 "BUG! Timeout waiting for bit %08x of register " 984 "%x to %s.\n", bit, reg, 985 (clear ? "clear" : "set")); 986 return -1; 987 } 988 return 0; 989 } 990 991 static int 992 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 993 { 994 int err; 995 996 /* Clear MII ISR */ 997 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 998 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 999 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1000 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1001 (reg << BFE_MDIO_RA_SHIFT) | 1002 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1003 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1004 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1005 return(err); 1006 } 1007 1008 static int 1009 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1010 { 1011 int status; 1012 1013 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1014 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1015 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1016 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1017 (reg << BFE_MDIO_RA_SHIFT) | 1018 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1019 (val & BFE_MDIO_DATA_DATA))); 1020 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1021 1022 return status; 1023 } 1024 1025 /* 1026 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1027 * twice 1028 */ 1029 static int 1030 bfe_setupphy(struct bfe_softc *sc) 1031 { 1032 uint32_t val; 1033 1034 /* Enable activity LED */ 1035 bfe_readphy(sc, 26, &val); 1036 bfe_writephy(sc, 26, val & 0x7fff); 1037 bfe_readphy(sc, 26, &val); 1038 1039 /* Enable traffic meter LED mode */ 1040 bfe_readphy(sc, 27, &val); 1041 bfe_writephy(sc, 27, val | (1 << 6)); 1042 1043 return(0); 1044 } 1045 1046 static void 1047 bfe_stats_update(struct bfe_softc *sc) 1048 { 1049 u_long reg; 1050 uint32_t *val; 1051 1052 val = &sc->bfe_hwstats.tx_good_octets; 1053 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1054 *val++ += CSR_READ_4(sc, reg); 1055 val = &sc->bfe_hwstats.rx_good_octets; 1056 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1057 *val++ += CSR_READ_4(sc, reg); 1058 } 1059 1060 static void 1061 bfe_txeof(struct bfe_softc *sc) 1062 { 1063 struct ifnet *ifp = &sc->arpcom.ac_if; 1064 uint32_t i, chipidx; 1065 1066 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1067 chipidx /= sizeof(struct bfe_desc); 1068 1069 i = sc->bfe_tx_cons; 1070 1071 /* Go through the mbufs and free those that have been transmitted */ 1072 while (i != chipidx) { 1073 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1074 1075 if (r->bfe_mbuf != NULL) { 1076 IFNET_STAT_INC(ifp, opackets, 1); 1077 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map); 1078 m_freem(r->bfe_mbuf); 1079 r->bfe_mbuf = NULL; 1080 } 1081 1082 KKASSERT(sc->bfe_tx_cnt > 0); 1083 sc->bfe_tx_cnt--; 1084 BFE_INC(i, BFE_TX_LIST_CNT); 1085 } 1086 1087 if (i != sc->bfe_tx_cons) { 1088 sc->bfe_tx_cons = i; 1089 1090 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT) 1091 ifq_clr_oactive(&ifp->if_snd); 1092 } 1093 if (sc->bfe_tx_cnt == 0) 1094 ifp->if_timer = 0; 1095 } 1096 1097 /* Pass a received packet up the stack */ 1098 static void 1099 bfe_rxeof(struct bfe_softc *sc) 1100 { 1101 struct ifnet *ifp = &sc->arpcom.ac_if; 1102 struct mbuf *m; 1103 struct bfe_rxheader *rxheader; 1104 struct bfe_data *r; 1105 uint32_t cons, status, current, len, flags; 1106 1107 cons = sc->bfe_rx_cons; 1108 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1109 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1110 1111 while (current != cons) { 1112 r = &sc->bfe_rx_ring[cons]; 1113 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, 1114 BUS_DMASYNC_POSTREAD); 1115 1116 KKASSERT(r->bfe_mbuf != NULL); 1117 m = r->bfe_mbuf; 1118 rxheader = mtod(m, struct bfe_rxheader*); 1119 len = rxheader->len - ETHER_CRC_LEN; 1120 flags = rxheader->flags; 1121 1122 /* flag an error and try again */ 1123 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) { 1124 IFNET_STAT_INC(ifp, ierrors, 1); 1125 if (flags & BFE_RX_FLAG_SERR) 1126 IFNET_STAT_INC(ifp, collisions, 1); 1127 1128 bfe_setup_rxdesc(sc, cons); 1129 BFE_INC(cons, BFE_RX_LIST_CNT); 1130 continue; 1131 } 1132 1133 /* Go past the rx header */ 1134 if (bfe_newbuf(sc, cons, 0) != 0) { 1135 bfe_setup_rxdesc(sc, cons); 1136 IFNET_STAT_INC(ifp, ierrors, 1); 1137 BFE_INC(cons, BFE_RX_LIST_CNT); 1138 continue; 1139 } 1140 1141 m_adj(m, BFE_RX_OFFSET); 1142 m->m_len = m->m_pkthdr.len = len; 1143 1144 IFNET_STAT_INC(ifp, ipackets, 1); 1145 m->m_pkthdr.rcvif = ifp; 1146 1147 ifp->if_input(ifp, m, NULL, -1); 1148 BFE_INC(cons, BFE_RX_LIST_CNT); 1149 } 1150 1151 sc->bfe_rx_cons = cons; 1152 } 1153 1154 static void 1155 bfe_intr(void *xsc) 1156 { 1157 struct bfe_softc *sc = xsc; 1158 struct ifnet *ifp = &sc->arpcom.ac_if; 1159 uint32_t istat, imask, flag; 1160 1161 istat = CSR_READ_4(sc, BFE_ISTAT); 1162 imask = CSR_READ_4(sc, BFE_IMASK); 1163 1164 /* 1165 * Defer unsolicited interrupts - This is necessary because setting the 1166 * chips interrupt mask register to 0 doesn't actually stop the 1167 * interrupts 1168 */ 1169 istat &= imask; 1170 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1171 CSR_READ_4(sc, BFE_ISTAT); 1172 1173 /* not expecting this interrupt, disregard it */ 1174 if (istat == 0) { 1175 return; 1176 } 1177 1178 if (istat & BFE_ISTAT_ERRORS) { 1179 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1180 if (flag & BFE_STAT_EMASK) 1181 IFNET_STAT_INC(ifp, oerrors, 1); 1182 1183 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1184 if (flag & BFE_RX_FLAG_ERRORS) 1185 IFNET_STAT_INC(ifp, ierrors, 1); 1186 1187 ifp->if_flags &= ~IFF_RUNNING; 1188 bfe_init(sc); 1189 } 1190 1191 /* A packet was received */ 1192 if (istat & BFE_ISTAT_RX) 1193 bfe_rxeof(sc); 1194 1195 /* A packet was sent */ 1196 if (istat & BFE_ISTAT_TX) 1197 bfe_txeof(sc); 1198 1199 /* We have packets pending, fire them out */ 1200 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1201 if_devstart(ifp); 1202 } 1203 1204 static int 1205 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1206 { 1207 bus_dma_segment_t segs[BFE_MAXSEGS]; 1208 bus_dmamap_t map; 1209 int i, first_idx, last_idx, cur, error, maxsegs, nsegs; 1210 1211 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT); 1212 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC; 1213 if (maxsegs > BFE_MAXSEGS) 1214 maxsegs = BFE_MAXSEGS; 1215 1216 first_idx = *txidx; 1217 map = sc->bfe_tx_ring[first_idx].bfe_map; 1218 1219 error = bus_dmamap_load_mbuf_defrag(sc->bfe_txbuf_tag, map, m_head, 1220 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1221 if (error) 1222 goto fail; 1223 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE); 1224 1225 last_idx = -1; 1226 cur = first_idx; 1227 for (i = 0; i < nsegs; ++i) { 1228 struct bfe_desc *d; 1229 uint32_t ctrl; 1230 1231 ctrl = BFE_DESC_LEN & segs[i].ds_len; 1232 ctrl |= BFE_DESC_IOC; /* always interrupt */ 1233 if (cur == BFE_TX_LIST_CNT - 1) { 1234 /* 1235 * Tell the chip to wrap to the 1236 * start of the descriptor list. 1237 */ 1238 ctrl |= BFE_DESC_EOT; 1239 } 1240 1241 d = &sc->bfe_tx_list[cur]; 1242 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA; 1243 d->bfe_ctrl = ctrl; 1244 1245 last_idx = cur; 1246 BFE_INC(cur, BFE_TX_LIST_CNT); 1247 } 1248 KKASSERT(last_idx >= 0); 1249 1250 /* End of the frame */ 1251 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF; 1252 1253 /* 1254 * Set start of the frame on the first fragment, 1255 * _after_ all of the fragments are setup. 1256 */ 1257 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF; 1258 1259 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map; 1260 sc->bfe_tx_ring[last_idx].bfe_map = map; 1261 sc->bfe_tx_ring[last_idx].bfe_mbuf = *m_head; 1262 1263 *txidx = cur; 1264 sc->bfe_tx_cnt += nsegs; 1265 return 0; 1266 fail: 1267 m_freem(*m_head); 1268 *m_head = NULL; 1269 return error; 1270 } 1271 1272 /* 1273 * Set up to transmit a packet 1274 */ 1275 static void 1276 bfe_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1277 { 1278 struct bfe_softc *sc = ifp->if_softc; 1279 struct mbuf *m_head = NULL; 1280 int idx, need_trans; 1281 1282 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1283 ASSERT_SERIALIZED(ifp->if_serializer); 1284 1285 /* 1286 * Not much point trying to send if the link is down 1287 * or we have nothing to send. 1288 */ 1289 if (!sc->bfe_link) { 1290 ifq_purge(&ifp->if_snd); 1291 return; 1292 } 1293 1294 if (ifq_is_oactive(&ifp->if_snd)) 1295 return; 1296 1297 idx = sc->bfe_tx_prod; 1298 1299 need_trans = 0; 1300 while (!ifq_is_empty(&ifp->if_snd)) { 1301 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) { 1302 ifq_set_oactive(&ifp->if_snd); 1303 break; 1304 } 1305 1306 m_head = ifq_dequeue(&ifp->if_snd); 1307 if (m_head == NULL) 1308 break; 1309 1310 /* 1311 * Pack the data into the tx ring. If we don't have 1312 * enough room, let the chip drain the ring. 1313 */ 1314 if (bfe_encap(sc, &m_head, &idx)) { 1315 /* m_head is freed by re_encap(), if we reach here */ 1316 IFNET_STAT_INC(ifp, oerrors, 1); 1317 1318 if (sc->bfe_tx_cnt > 0) { 1319 ifq_set_oactive(&ifp->if_snd); 1320 break; 1321 } else { 1322 /* 1323 * ifq_set_oactive could not be called under 1324 * this situation, since except up/down, 1325 * nothing will call ifq_clr_oactive. 1326 * 1327 * Let's just keep draining the ifq ... 1328 */ 1329 continue; 1330 } 1331 } 1332 need_trans = 1; 1333 1334 /* 1335 * If there's a BPF listener, bounce a copy of this frame 1336 * to him. 1337 */ 1338 BPF_MTAP(ifp, m_head); 1339 } 1340 1341 if (!need_trans) 1342 return; 1343 1344 sc->bfe_tx_prod = idx; 1345 1346 /* Transmit - twice due to apparent hardware bug */ 1347 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1348 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1349 1350 /* 1351 * Set a timeout in case the chip goes out to lunch. 1352 */ 1353 ifp->if_timer = 5; 1354 } 1355 1356 static void 1357 bfe_init(void *xsc) 1358 { 1359 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1360 struct ifnet *ifp = &sc->arpcom.ac_if; 1361 1362 ASSERT_SERIALIZED(ifp->if_serializer); 1363 1364 if (ifp->if_flags & IFF_RUNNING) 1365 return; 1366 1367 bfe_stop(sc); 1368 bfe_chip_reset(sc); 1369 1370 if (bfe_list_rx_init(sc) == ENOBUFS) { 1371 if_printf(ifp, "bfe_init failed. " 1372 " Not enough memory for list buffers\n"); 1373 bfe_stop(sc); 1374 return; 1375 } 1376 1377 bfe_set_rx_mode(sc); 1378 1379 /* Enable the chip and core */ 1380 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1381 /* Enable interrupts */ 1382 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1383 1384 bfe_ifmedia_upd(ifp); 1385 ifp->if_flags |= IFF_RUNNING; 1386 ifq_clr_oactive(&ifp->if_snd); 1387 1388 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1389 } 1390 1391 /* 1392 * Set media options. 1393 */ 1394 static int 1395 bfe_ifmedia_upd(struct ifnet *ifp) 1396 { 1397 struct bfe_softc *sc = ifp->if_softc; 1398 struct mii_data *mii; 1399 1400 ASSERT_SERIALIZED(ifp->if_serializer); 1401 1402 mii = device_get_softc(sc->bfe_miibus); 1403 sc->bfe_link = 0; 1404 if (mii->mii_instance) { 1405 struct mii_softc *miisc; 1406 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1407 miisc = LIST_NEXT(miisc, mii_list)) 1408 mii_phy_reset(miisc); 1409 } 1410 mii_mediachg(mii); 1411 1412 bfe_setupphy(sc); 1413 1414 return(0); 1415 } 1416 1417 /* 1418 * Report current media status. 1419 */ 1420 static void 1421 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1422 { 1423 struct bfe_softc *sc = ifp->if_softc; 1424 struct mii_data *mii; 1425 1426 ASSERT_SERIALIZED(ifp->if_serializer); 1427 1428 mii = device_get_softc(sc->bfe_miibus); 1429 mii_pollstat(mii); 1430 ifmr->ifm_active = mii->mii_media_active; 1431 ifmr->ifm_status = mii->mii_media_status; 1432 } 1433 1434 static int 1435 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1436 { 1437 struct bfe_softc *sc = ifp->if_softc; 1438 struct ifreq *ifr = (struct ifreq *) data; 1439 struct mii_data *mii; 1440 int error = 0; 1441 1442 ASSERT_SERIALIZED(ifp->if_serializer); 1443 1444 switch (command) { 1445 case SIOCSIFFLAGS: 1446 if (ifp->if_flags & IFF_UP) 1447 if (ifp->if_flags & IFF_RUNNING) 1448 bfe_set_rx_mode(sc); 1449 else 1450 bfe_init(sc); 1451 else if (ifp->if_flags & IFF_RUNNING) 1452 bfe_stop(sc); 1453 break; 1454 case SIOCADDMULTI: 1455 case SIOCDELMULTI: 1456 if (ifp->if_flags & IFF_RUNNING) 1457 bfe_set_rx_mode(sc); 1458 break; 1459 case SIOCGIFMEDIA: 1460 case SIOCSIFMEDIA: 1461 mii = device_get_softc(sc->bfe_miibus); 1462 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1463 command); 1464 break; 1465 default: 1466 error = ether_ioctl(ifp, command, data); 1467 break; 1468 } 1469 return error; 1470 } 1471 1472 static void 1473 bfe_watchdog(struct ifnet *ifp) 1474 { 1475 struct bfe_softc *sc = ifp->if_softc; 1476 1477 ASSERT_SERIALIZED(ifp->if_serializer); 1478 1479 if_printf(ifp, "watchdog timeout -- resetting\n"); 1480 1481 ifp->if_flags &= ~IFF_RUNNING; 1482 bfe_init(sc); 1483 1484 IFNET_STAT_INC(ifp, oerrors, 1); 1485 } 1486 1487 static void 1488 bfe_tick(void *xsc) 1489 { 1490 struct bfe_softc *sc = xsc; 1491 struct mii_data *mii; 1492 struct ifnet *ifp = &sc->arpcom.ac_if; 1493 1494 mii = device_get_softc(sc->bfe_miibus); 1495 1496 lwkt_serialize_enter(ifp->if_serializer); 1497 1498 bfe_stats_update(sc); 1499 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1500 1501 if (sc->bfe_link == 0) { 1502 mii_tick(mii); 1503 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1504 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1505 sc->bfe_link++; 1506 } 1507 if (!sc->bfe_link) 1508 sc->bfe_link++; 1509 } 1510 lwkt_serialize_exit(ifp->if_serializer); 1511 } 1512 1513 /* 1514 * Stop the adapter and free any mbufs allocated to the 1515 * RX and TX lists. 1516 */ 1517 static void 1518 bfe_stop(struct bfe_softc *sc) 1519 { 1520 struct ifnet *ifp = &sc->arpcom.ac_if; 1521 1522 ASSERT_SERIALIZED(ifp->if_serializer); 1523 1524 callout_stop(&sc->bfe_stat_timer); 1525 1526 bfe_chip_halt(sc); 1527 bfe_tx_ring_free(sc); 1528 bfe_rx_ring_free(sc); 1529 1530 ifp->if_flags &= ~IFF_RUNNING; 1531 ifq_clr_oactive(&ifp->if_snd); 1532 } 1533