1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.8 2004/09/14 22:21:43 joerg Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/ethernet.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 52 #include <net/if_types.h> 53 #include <net/vlan/if_vlan_var.h> 54 55 #include <netinet/in_systm.h> 56 #include <netinet/in.h> 57 #include <netinet/ip.h> 58 59 #include <machine/bus_memio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include <bus/pci/pcireg.h> 66 #include <bus/pci/pcivar.h> 67 #include <bus/pci/pcidevs.h> 68 69 #include <dev/netif/mii_layer/mii.h> 70 #include <dev/netif/mii_layer/miivar.h> 71 72 #include "if_bfereg.h" 73 74 MODULE_DEPEND(bfe, pci, 1, 1, 1); 75 MODULE_DEPEND(bfe, ether, 1, 1, 1); 76 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 77 78 /* "controller miibus0" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 81 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82 83 static struct bfe_type bfe_devs[] = { 84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 85 "Broadcom BCM4401 Fast Ethernet" }, 86 { 0, 0, NULL } 87 }; 88 89 static int bfe_probe(device_t); 90 static int bfe_attach(device_t); 91 static int bfe_detach(device_t); 92 static void bfe_release_resources(struct bfe_softc *); 93 static void bfe_intr(void *); 94 static void bfe_start(struct ifnet *); 95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 96 static void bfe_init(void *); 97 static void bfe_stop(struct bfe_softc *); 98 static void bfe_watchdog(struct ifnet *); 99 static void bfe_shutdown(device_t); 100 static void bfe_tick(void *); 101 static void bfe_txeof(struct bfe_softc *); 102 static void bfe_rxeof(struct bfe_softc *); 103 static void bfe_set_rx_mode(struct bfe_softc *); 104 static int bfe_list_rx_init(struct bfe_softc *); 105 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 106 static void bfe_rx_ring_free(struct bfe_softc *); 107 108 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 109 static int bfe_ifmedia_upd(struct ifnet *); 110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 111 static int bfe_miibus_readreg(device_t, int, int); 112 static int bfe_miibus_writereg(device_t, int, int, int); 113 static void bfe_miibus_statchg(device_t); 114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 115 u_long, const int); 116 static void bfe_get_config(struct bfe_softc *sc); 117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 118 static void bfe_stats_update(struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 122 static int bfe_resetphy(struct bfe_softc *); 123 static int bfe_setupphy(struct bfe_softc *); 124 static void bfe_chip_reset(struct bfe_softc *); 125 static void bfe_chip_halt(struct bfe_softc *); 126 static void bfe_core_reset(struct bfe_softc *); 127 static void bfe_core_disable(struct bfe_softc *); 128 static int bfe_dma_alloc(device_t); 129 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 130 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 131 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 132 133 static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148 149 { 0, 0 } 150 }; 151 152 static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156 }; 157 158 static devclass_t bfe_devclass; 159 160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163 /* 164 * Probe for a Broadcom 4401 chip. 165 */ 166 static int 167 bfe_probe(device_t dev) 168 { 169 struct bfe_type *t; 170 struct bfe_softc *sc; 171 172 t = bfe_devs; 173 174 sc = device_get_softc(dev); 175 bzero(sc, sizeof(struct bfe_softc)); 176 sc->bfe_unit = device_get_unit(dev); 177 sc->bfe_dev = dev; 178 179 while (t->bfe_name != NULL) { 180 if ((pci_get_vendor(dev) == t->bfe_vid) && 181 (pci_get_device(dev) == t->bfe_did)) { 182 device_set_desc_copy(dev, t->bfe_name); 183 return(0); 184 } 185 t++; 186 } 187 188 return(ENXIO); 189 } 190 191 static int 192 bfe_dma_alloc(device_t dev) 193 { 194 struct bfe_softc *sc; 195 int error, i; 196 197 sc = device_get_softc(dev); 198 199 /* parent tag */ 200 error = bus_dma_tag_create(NULL, /* parent */ 201 PAGE_SIZE, 0, /* alignment, boundary */ 202 BUS_SPACE_MAXADDR, /* lowaddr */ 203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 204 NULL, NULL, /* filter, filterarg */ 205 MAXBSIZE, /* maxsize */ 206 BUS_SPACE_UNRESTRICTED, /* num of segments */ 207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 208 BUS_DMA_ALLOCNOW, /* flags */ 209 &sc->bfe_parent_tag); 210 211 if (error) { 212 device_printf(dev, "could not allocate dma tag\n"); 213 return(ENOMEM); 214 } 215 216 217 /* tag for TX ring */ 218 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE, 219 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 220 NULL, NULL, BFE_TX_LIST_SIZE, 1, 221 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag); 222 223 if (error) { 224 device_printf(dev, "could not allocate dma tag\n"); 225 return(ENOMEM); 226 } 227 228 /* tag for RX ring */ 229 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE, 230 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 231 NULL, NULL, BFE_RX_LIST_SIZE, 1, 232 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag); 233 234 if (error) { 235 device_printf(dev, "could not allocate dma tag\n"); 236 return(ENOMEM); 237 } 238 239 /* tag for mbufs */ 240 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 242 1, BUS_SPACE_MAXSIZE_32BIT, 0, 243 &sc->bfe_tag); 244 245 if (error) { 246 device_printf(dev, "could not allocate dma tag\n"); 247 return(ENOMEM); 248 } 249 250 /* pre allocate dmamaps for RX list */ 251 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 252 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map); 253 if (error) { 254 device_printf(dev, "cannot create DMA map for RX\n"); 255 return(ENOMEM); 256 } 257 } 258 259 /* pre allocate dmamaps for TX list */ 260 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map); 262 if (error) { 263 device_printf(dev, "cannot create DMA map for TX\n"); 264 return(ENOMEM); 265 } 266 } 267 268 /* Alloc dma for rx ring */ 269 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 270 BUS_DMA_WAITOK, &sc->bfe_rx_map); 271 272 if (error) 273 return(ENOMEM); 274 275 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 276 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 277 sc->bfe_rx_list, sizeof(struct bfe_desc), 278 bfe_dma_map, &sc->bfe_rx_dma, 0); 279 280 if (error) 281 return(ENOMEM); 282 283 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 284 285 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 286 BUS_DMA_WAITOK, &sc->bfe_tx_map); 287 if (error) 288 return(ENOMEM); 289 290 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 291 sc->bfe_tx_list, sizeof(struct bfe_desc), 292 bfe_dma_map, &sc->bfe_tx_dma, 0); 293 if (error) 294 return(ENOMEM); 295 296 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 297 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 298 299 return(0); 300 } 301 302 static int 303 bfe_attach(device_t dev) 304 { 305 struct ifnet *ifp; 306 struct bfe_softc *sc; 307 int unit, error = 0, rid; 308 309 sc = device_get_softc(dev); 310 311 unit = device_get_unit(dev); 312 sc->bfe_dev = dev; 313 sc->bfe_unit = unit; 314 callout_init(&sc->bfe_stat_timer); 315 316 /* 317 * Handle power management nonsense. 318 */ 319 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 320 uint32_t membase, irq; 321 322 /* Save important PCI config data. */ 323 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 324 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 325 326 /* Reset the power state. */ 327 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 328 sc->bfe_unit, pci_get_powerstate(dev)); 329 330 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 331 332 /* Restore PCI config data. */ 333 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 334 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 335 } 336 337 /* 338 * Map control/status registers. 339 */ 340 pci_enable_busmaster(dev); 341 342 rid = BFE_PCI_MEMLO; 343 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, 344 RF_ACTIVE); 345 if (sc->bfe_res == NULL) { 346 printf ("bfe%d: couldn't map memory\n", unit); 347 error = ENXIO; 348 goto fail; 349 } 350 351 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 352 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 353 354 /* Allocate interrupt */ 355 rid = 0; 356 357 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 358 RF_SHAREABLE | RF_ACTIVE); 359 if (sc->bfe_irq == NULL) { 360 printf("bfe%d: couldn't map interrupt\n", unit); 361 error = ENXIO; 362 goto fail; 363 } 364 365 if (bfe_dma_alloc(dev)) { 366 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit); 367 bfe_release_resources(sc); 368 error = ENXIO; 369 goto fail; 370 } 371 372 /* Set up ifnet structure */ 373 ifp = &sc->arpcom.ac_if; 374 ifp->if_softc = sc; 375 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 377 ifp->if_ioctl = bfe_ioctl; 378 ifp->if_start = bfe_start; 379 ifp->if_watchdog = bfe_watchdog; 380 ifp->if_init = bfe_init; 381 ifp->if_mtu = ETHERMTU; 382 ifp->if_baudrate = 10000000; 383 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 384 385 bfe_get_config(sc); 386 387 /* Reset the chip and turn on the PHY */ 388 bfe_chip_reset(sc); 389 390 if (mii_phy_probe(dev, &sc->bfe_miibus, 391 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 392 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 393 error = ENXIO; 394 goto fail; 395 } 396 397 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 398 399 /* 400 * Hook interrupt last to avoid having to lock softc 401 */ 402 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 403 bfe_intr, sc, &sc->bfe_intrhand); 404 405 if (error) { 406 bfe_release_resources(sc); 407 printf("bfe%d: couldn't set up irq\n", unit); 408 goto fail; 409 } 410 fail: 411 if (error) 412 bfe_release_resources(sc); 413 return(error); 414 } 415 416 static int 417 bfe_detach(device_t dev) 418 { 419 struct bfe_softc *sc; 420 struct ifnet *ifp; 421 int s; 422 423 sc = device_get_softc(dev); 424 425 s = splimp(); 426 427 ifp = &sc->arpcom.ac_if; 428 429 if (device_is_attached(dev)) { 430 bfe_stop(sc); 431 ether_ifdetach(ifp); 432 } 433 434 bfe_chip_reset(sc); 435 436 bus_generic_detach(dev); 437 if (sc->bfe_miibus != NULL) 438 device_delete_child(dev, sc->bfe_miibus); 439 440 bfe_release_resources(sc); 441 splx(s); 442 443 return(0); 444 } 445 446 /* 447 * Stop all chip I/O so that the kernel's probe routines don't 448 * get confused by errant DMAs when rebooting. 449 */ 450 static void 451 bfe_shutdown(device_t dev) 452 { 453 struct bfe_softc *sc; 454 int s; 455 456 sc = device_get_softc(dev); 457 458 s = splimp(); 459 bfe_stop(sc); 460 splx(s); 461 462 return; 463 } 464 465 static int 466 bfe_miibus_readreg(device_t dev, int phy, int reg) 467 { 468 struct bfe_softc *sc; 469 uint32_t ret; 470 471 sc = device_get_softc(dev); 472 if (phy != sc->bfe_phyaddr) 473 return(0); 474 bfe_readphy(sc, reg, &ret); 475 476 return(ret); 477 } 478 479 static int 480 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 481 { 482 struct bfe_softc *sc; 483 484 sc = device_get_softc(dev); 485 if (phy != sc->bfe_phyaddr) 486 return(0); 487 bfe_writephy(sc, reg, val); 488 489 return(0); 490 } 491 492 static void 493 bfe_miibus_statchg(device_t dev) 494 { 495 return; 496 } 497 498 static void 499 bfe_tx_ring_free(struct bfe_softc *sc) 500 { 501 int i; 502 503 for (i = 0; i < BFE_TX_LIST_CNT; i++) 504 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 505 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 506 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 507 bus_dmamap_unload(sc->bfe_tag, 508 sc->bfe_tx_ring[i].bfe_map); 509 bus_dmamap_destroy(sc->bfe_tag, 510 sc->bfe_tx_ring[i].bfe_map); 511 } 512 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 513 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 514 } 515 516 static void 517 bfe_rx_ring_free(struct bfe_softc *sc) 518 { 519 int i; 520 521 for (i = 0; i < BFE_RX_LIST_CNT; i++) 522 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 523 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 524 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 525 bus_dmamap_unload(sc->bfe_tag, 526 sc->bfe_rx_ring[i].bfe_map); 527 bus_dmamap_destroy(sc->bfe_tag, 528 sc->bfe_rx_ring[i].bfe_map); 529 } 530 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 531 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 532 } 533 534 535 static int 536 bfe_list_rx_init(struct bfe_softc *sc) 537 { 538 int i; 539 540 for (i = 0; i < BFE_RX_LIST_CNT; i++) 541 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 542 return(ENOBUFS); 543 544 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 545 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 546 547 sc->bfe_rx_cons = 0; 548 549 return(0); 550 } 551 552 static int 553 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 554 { 555 struct bfe_rxheader *rx_header; 556 struct bfe_desc *d; 557 struct bfe_data *r; 558 uint32_t ctrl; 559 560 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 561 return(EINVAL); 562 563 if (m == NULL) { 564 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 565 if (m == NULL) 566 return(ENOBUFS); 567 m->m_len = m->m_pkthdr.len = MCLBYTES; 568 } 569 else 570 m->m_data = m->m_ext.ext_buf; 571 572 rx_header = mtod(m, struct bfe_rxheader *); 573 rx_header->len = 0; 574 rx_header->flags = 0; 575 576 /* Map the mbuf into DMA */ 577 sc->bfe_rx_cnt = c; 578 d = &sc->bfe_rx_list[c]; 579 r = &sc->bfe_rx_ring[c]; 580 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 581 MCLBYTES, bfe_dma_map_desc, d, 0); 582 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 583 584 ctrl = ETHER_MAX_LEN + 32; 585 586 if(c == BFE_RX_LIST_CNT - 1) 587 ctrl |= BFE_DESC_EOT; 588 589 d->bfe_ctrl = ctrl; 590 r->bfe_mbuf = m; 591 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 592 return(0); 593 } 594 595 static void 596 bfe_get_config(struct bfe_softc *sc) 597 { 598 uint8_t eeprom[128]; 599 600 bfe_read_eeprom(sc, eeprom); 601 602 sc->arpcom.ac_enaddr[0] = eeprom[79]; 603 sc->arpcom.ac_enaddr[1] = eeprom[78]; 604 sc->arpcom.ac_enaddr[2] = eeprom[81]; 605 sc->arpcom.ac_enaddr[3] = eeprom[80]; 606 sc->arpcom.ac_enaddr[4] = eeprom[83]; 607 sc->arpcom.ac_enaddr[5] = eeprom[82]; 608 609 sc->bfe_phyaddr = eeprom[90] & 0x1f; 610 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 611 612 sc->bfe_core_unit = 0; 613 sc->bfe_dma_offset = BFE_PCI_DMA; 614 } 615 616 static void 617 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 618 { 619 uint32_t bar_orig, pci_rev, val; 620 621 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 622 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 623 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 624 625 val = CSR_READ_4(sc, BFE_SBINTVEC); 626 val |= cores; 627 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 628 629 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 630 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 631 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 632 633 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 634 } 635 636 static void 637 bfe_clear_stats(struct bfe_softc *sc) 638 { 639 u_long reg; 640 int s; 641 642 s = splimp(); 643 644 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 645 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 646 CSR_READ_4(sc, reg); 647 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 648 CSR_READ_4(sc, reg); 649 650 splx(s); 651 } 652 653 static int 654 bfe_resetphy(struct bfe_softc *sc) 655 { 656 uint32_t val; 657 int s; 658 659 s = splimp(); 660 bfe_writephy(sc, 0, BMCR_RESET); 661 DELAY(100); 662 bfe_readphy(sc, 0, &val); 663 if (val & BMCR_RESET) { 664 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 665 splx(s); 666 return(ENXIO); 667 } 668 splx(s); 669 return(0); 670 } 671 672 static void 673 bfe_chip_halt(struct bfe_softc *sc) 674 { 675 int s; 676 677 s = splimp(); 678 /* disable interrupts - not that it actually does..*/ 679 CSR_WRITE_4(sc, BFE_IMASK, 0); 680 CSR_READ_4(sc, BFE_IMASK); 681 682 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 683 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 684 685 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 686 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 687 DELAY(10); 688 689 splx(s); 690 } 691 692 static void 693 bfe_chip_reset(struct bfe_softc *sc) 694 { 695 uint32_t val; 696 int s; 697 698 s = splimp(); 699 700 /* Set the interrupt vector for the enet core */ 701 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 702 703 /* is core up? */ 704 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 705 if (val == BFE_CLOCK) { 706 /* It is, so shut it down */ 707 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 708 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 709 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 711 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 712 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 713 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 714 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 715 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 716 } 717 718 bfe_core_reset(sc); 719 bfe_clear_stats(sc); 720 721 /* 722 * We want the phy registers to be accessible even when 723 * the driver is "downed" so initialize MDC preamble, frequency, 724 * and whether internal or external phy here. 725 */ 726 727 /* 4402 has 62.5Mhz SB clock and internal phy */ 728 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 729 730 /* Internal or external PHY? */ 731 val = CSR_READ_4(sc, BFE_DEVCTRL); 732 if (!(val & BFE_IPP)) 733 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 734 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 735 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 736 DELAY(100); 737 } 738 739 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); 740 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 741 BFE_LAZY_FC_MASK)); 742 743 /* 744 * We don't want lazy interrupts, so just send them at the end of a 745 * frame, please 746 */ 747 BFE_OR(sc, BFE_RCV_LAZY, 0); 748 749 /* Set max lengths, accounting for VLAN tags */ 750 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 751 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 752 753 /* Set watermark XXX - magic */ 754 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 755 756 /* 757 * Initialise DMA channels - not forgetting dma addresses need to be 758 * added to BFE_PCI_DMA 759 */ 760 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 761 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 762 763 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 764 BFE_RX_CTRL_ENABLE); 765 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 766 767 bfe_resetphy(sc); 768 bfe_setupphy(sc); 769 770 splx(s); 771 } 772 773 static void 774 bfe_core_disable(struct bfe_softc *sc) 775 { 776 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 777 return; 778 779 /* 780 * Set reject, wait for it set, then wait for the core to stop being busy 781 * Then set reset and reject and enable the clocks 782 */ 783 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 784 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 785 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 786 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 787 BFE_RESET)); 788 CSR_READ_4(sc, BFE_SBTMSLOW); 789 DELAY(10); 790 /* Leave reset and reject set */ 791 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 792 DELAY(10); 793 } 794 795 static void 796 bfe_core_reset(struct bfe_softc *sc) 797 { 798 uint32_t val; 799 800 /* Disable the core */ 801 bfe_core_disable(sc); 802 803 /* and bring it back up */ 804 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 805 CSR_READ_4(sc, BFE_SBTMSLOW); 806 DELAY(10); 807 808 /* Chip bug, clear SERR, IB and TO if they are set. */ 809 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 810 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 811 val = CSR_READ_4(sc, BFE_SBIMSTATE); 812 if (val & (BFE_IBE | BFE_TO)) 813 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 814 815 /* Clear reset and allow it to move through the core */ 816 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 817 CSR_READ_4(sc, BFE_SBTMSLOW); 818 DELAY(10); 819 820 /* Leave the clock set */ 821 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 822 CSR_READ_4(sc, BFE_SBTMSLOW); 823 DELAY(10); 824 } 825 826 static void 827 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 828 { 829 uint32_t val; 830 831 val = ((uint32_t) data[2]) << 24; 832 val |= ((uint32_t) data[3]) << 16; 833 val |= ((uint32_t) data[4]) << 8; 834 val |= ((uint32_t) data[5]); 835 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 836 val = (BFE_CAM_HI_VALID | 837 (((uint32_t) data[0]) << 8) | 838 (((uint32_t) data[1]))); 839 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 840 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 841 (index << BFE_CAM_INDEX_SHIFT))); 842 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 843 } 844 845 static void 846 bfe_set_rx_mode(struct bfe_softc *sc) 847 { 848 struct ifnet *ifp = &sc->arpcom.ac_if; 849 uint32_t val; 850 int i = 0; 851 852 val = CSR_READ_4(sc, BFE_RXCONF); 853 854 if (ifp->if_flags & IFF_PROMISC) 855 val |= BFE_RXCONF_PROMISC; 856 else 857 val &= ~BFE_RXCONF_PROMISC; 858 859 if (ifp->if_flags & IFF_BROADCAST) 860 val &= ~BFE_RXCONF_DBCAST; 861 else 862 val |= BFE_RXCONF_DBCAST; 863 864 865 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 866 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 867 868 CSR_WRITE_4(sc, BFE_RXCONF, val); 869 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 870 } 871 872 static void 873 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 874 { 875 uint32_t *ptr; 876 877 ptr = arg; 878 *ptr = segs->ds_addr; 879 } 880 881 static void 882 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 883 { 884 struct bfe_desc *d; 885 886 d = arg; 887 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 888 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 889 } 890 891 static void 892 bfe_release_resources(struct bfe_softc *sc) 893 { 894 device_t dev; 895 int i; 896 897 dev = sc->bfe_dev; 898 899 if (sc->bfe_intrhand != NULL) 900 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 901 902 if (sc->bfe_irq != NULL) 903 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 904 905 if (sc->bfe_res != NULL) 906 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 907 908 if (sc->bfe_tx_tag != NULL) { 909 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 910 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map); 911 bus_dma_tag_destroy(sc->bfe_tx_tag); 912 sc->bfe_tx_tag = NULL; 913 } 914 915 if (sc->bfe_rx_tag != NULL) { 916 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 917 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map); 918 bus_dma_tag_destroy(sc->bfe_rx_tag); 919 sc->bfe_rx_tag = NULL; 920 } 921 922 if (sc->bfe_tag != NULL) { 923 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 924 bus_dmamap_destroy(sc->bfe_tag, 925 sc->bfe_tx_ring[i].bfe_map); 926 } 927 bus_dma_tag_destroy(sc->bfe_tag); 928 sc->bfe_tag = NULL; 929 } 930 931 if (sc->bfe_parent_tag != NULL) 932 bus_dma_tag_destroy(sc->bfe_parent_tag); 933 } 934 935 static void 936 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 937 { 938 long i; 939 uint16_t *ptr = (uint16_t *)data; 940 941 for (i = 0; i < 128; i += 2) 942 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 943 } 944 945 static int 946 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 947 u_long timeout, const int clear) 948 { 949 u_long i; 950 951 for (i = 0; i < timeout; i++) { 952 uint32_t val = CSR_READ_4(sc, reg); 953 954 if (clear && !(val & bit)) 955 break; 956 if (!clear && (val & bit)) 957 break; 958 DELAY(10); 959 } 960 if (i == timeout) { 961 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 962 "%x to %s.\n", sc->bfe_unit, bit, reg, 963 (clear ? "clear" : "set")); 964 return -1; 965 } 966 return 0; 967 } 968 969 static int 970 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 971 { 972 int err; 973 int s; 974 975 s = splimp(); 976 /* Clear MII ISR */ 977 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 978 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 979 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 980 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 981 (reg << BFE_MDIO_RA_SHIFT) | 982 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 983 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 984 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 985 986 splx(s); 987 return(err); 988 } 989 990 static int 991 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 992 { 993 int status; 994 int s; 995 996 s = splimp(); 997 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 998 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 999 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1000 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1001 (reg << BFE_MDIO_RA_SHIFT) | 1002 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1003 (val & BFE_MDIO_DATA_DATA))); 1004 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1005 1006 splx(s); 1007 1008 return status; 1009 } 1010 1011 /* 1012 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1013 * twice 1014 */ 1015 static int 1016 bfe_setupphy(struct bfe_softc *sc) 1017 { 1018 uint32_t val; 1019 int s; 1020 1021 s = splimp(); 1022 1023 /* Enable activity LED */ 1024 bfe_readphy(sc, 26, &val); 1025 bfe_writephy(sc, 26, val & 0x7fff); 1026 bfe_readphy(sc, 26, &val); 1027 1028 /* Enable traffic meter LED mode */ 1029 bfe_readphy(sc, 27, &val); 1030 bfe_writephy(sc, 27, val | (1 << 6)); 1031 1032 splx(s); 1033 return(0); 1034 } 1035 1036 static void 1037 bfe_stats_update(struct bfe_softc *sc) 1038 { 1039 u_long reg; 1040 uint32_t *val; 1041 1042 val = &sc->bfe_hwstats.tx_good_octets; 1043 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1044 *val++ += CSR_READ_4(sc, reg); 1045 val = &sc->bfe_hwstats.rx_good_octets; 1046 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1047 *val++ += CSR_READ_4(sc, reg); 1048 } 1049 1050 static void 1051 bfe_txeof(struct bfe_softc *sc) 1052 { 1053 struct ifnet *ifp; 1054 int s; 1055 uint32_t i, chipidx; 1056 1057 s = splimp(); 1058 1059 ifp = &sc->arpcom.ac_if; 1060 1061 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1062 chipidx /= sizeof(struct bfe_desc); 1063 1064 i = sc->bfe_tx_cons; 1065 /* Go through the mbufs and free those that have been transmitted */ 1066 while (i != chipidx) { 1067 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1068 if (r->bfe_mbuf != NULL) { 1069 ifp->if_opackets++; 1070 m_freem(r->bfe_mbuf); 1071 r->bfe_mbuf = NULL; 1072 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1073 } 1074 sc->bfe_tx_cnt--; 1075 BFE_INC(i, BFE_TX_LIST_CNT); 1076 } 1077 1078 if (i != sc->bfe_tx_cons) { 1079 /* we freed up some mbufs */ 1080 sc->bfe_tx_cons = i; 1081 ifp->if_flags &= ~IFF_OACTIVE; 1082 } 1083 if (sc->bfe_tx_cnt == 0) 1084 ifp->if_timer = 0; 1085 else 1086 ifp->if_timer = 5; 1087 1088 splx(s); 1089 } 1090 1091 /* Pass a received packet up the stack */ 1092 static void 1093 bfe_rxeof(struct bfe_softc *sc) 1094 { 1095 struct mbuf *m; 1096 struct ifnet *ifp; 1097 struct bfe_rxheader *rxheader; 1098 struct bfe_data *r; 1099 uint32_t cons, status, current, len, flags; 1100 int s; 1101 1102 s = splimp(); 1103 cons = sc->bfe_rx_cons; 1104 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1105 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1106 1107 ifp = &sc->arpcom.ac_if; 1108 1109 while (current != cons) { 1110 r = &sc->bfe_rx_ring[cons]; 1111 m = r->bfe_mbuf; 1112 rxheader = mtod(m, struct bfe_rxheader*); 1113 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1114 len = rxheader->len; 1115 r->bfe_mbuf = NULL; 1116 1117 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1118 flags = rxheader->flags; 1119 1120 len -= ETHER_CRC_LEN; 1121 1122 /* flag an error and try again */ 1123 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1124 ifp->if_ierrors++; 1125 if (flags & BFE_RX_FLAG_SERR) 1126 ifp->if_collisions++; 1127 bfe_list_newbuf(sc, cons, m); 1128 BFE_INC(cons, BFE_RX_LIST_CNT); 1129 continue; 1130 } 1131 1132 /* Go past the rx header */ 1133 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1134 bfe_list_newbuf(sc, cons, m); 1135 BFE_INC(cons, BFE_RX_LIST_CNT); 1136 ifp->if_ierrors++; 1137 continue; 1138 } 1139 1140 m_adj(m, BFE_RX_OFFSET); 1141 m->m_len = m->m_pkthdr.len = len; 1142 1143 ifp->if_ipackets++; 1144 m->m_pkthdr.rcvif = ifp; 1145 1146 (*ifp->if_input)(ifp, m); 1147 BFE_INC(cons, BFE_RX_LIST_CNT); 1148 } 1149 sc->bfe_rx_cons = cons; 1150 splx(s); 1151 } 1152 1153 static void 1154 bfe_intr(void *xsc) 1155 { 1156 struct bfe_softc *sc = xsc; 1157 struct ifnet *ifp; 1158 uint32_t istat, imask, flag; 1159 int s; 1160 1161 ifp = &sc->arpcom.ac_if; 1162 1163 s = splimp(); 1164 1165 istat = CSR_READ_4(sc, BFE_ISTAT); 1166 imask = CSR_READ_4(sc, BFE_IMASK); 1167 1168 /* 1169 * Defer unsolicited interrupts - This is necessary because setting the 1170 * chips interrupt mask register to 0 doesn't actually stop the 1171 * interrupts 1172 */ 1173 istat &= imask; 1174 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1175 CSR_READ_4(sc, BFE_ISTAT); 1176 1177 /* not expecting this interrupt, disregard it */ 1178 if (istat == 0) { 1179 splx(s); 1180 return; 1181 } 1182 1183 if (istat & BFE_ISTAT_ERRORS) { 1184 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1185 if (flag & BFE_STAT_EMASK) 1186 ifp->if_oerrors++; 1187 1188 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1189 if (flag & BFE_RX_FLAG_ERRORS) 1190 ifp->if_ierrors++; 1191 1192 ifp->if_flags &= ~IFF_RUNNING; 1193 bfe_init(sc); 1194 } 1195 1196 /* A packet was received */ 1197 if (istat & BFE_ISTAT_RX) 1198 bfe_rxeof(sc); 1199 1200 /* A packet was sent */ 1201 if (istat & BFE_ISTAT_TX) 1202 bfe_txeof(sc); 1203 1204 /* We have packets pending, fire them out */ 1205 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1206 bfe_start(ifp); 1207 1208 splx(s); 1209 } 1210 1211 static int 1212 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1213 { 1214 struct bfe_desc *d = NULL; 1215 struct bfe_data *r = NULL; 1216 struct mbuf *m; 1217 uint32_t frag, cur, cnt = 0; 1218 1219 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1220 return(ENOBUFS); 1221 1222 /* 1223 * Start packing the mbufs in this chain into 1224 * the fragment pointers. Stop when we run out 1225 * of fragments or hit the end of the mbuf chain. 1226 */ 1227 m = m_head; 1228 cur = frag = *txidx; 1229 cnt = 0; 1230 1231 for (m = m_head; m != NULL; m = m->m_next) { 1232 if (m->m_len != 0) { 1233 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1234 return(ENOBUFS); 1235 1236 d = &sc->bfe_tx_list[cur]; 1237 r = &sc->bfe_tx_ring[cur]; 1238 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1239 /* always intterupt on completion */ 1240 d->bfe_ctrl |= BFE_DESC_IOC; 1241 if (cnt == 0) 1242 /* Set start of frame */ 1243 d->bfe_ctrl |= BFE_DESC_SOF; 1244 if (cur == BFE_TX_LIST_CNT - 1) 1245 /* 1246 * Tell the chip to wrap to the start of the 1247 *descriptor list 1248 */ 1249 d->bfe_ctrl |= BFE_DESC_EOT; 1250 1251 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), 1252 m->m_len, bfe_dma_map_desc, d, 0); 1253 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1254 BUS_DMASYNC_PREREAD); 1255 1256 frag = cur; 1257 BFE_INC(cur, BFE_TX_LIST_CNT); 1258 cnt++; 1259 } 1260 } 1261 1262 if (m != NULL) 1263 return(ENOBUFS); 1264 1265 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1266 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1267 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1268 1269 *txidx = cur; 1270 sc->bfe_tx_cnt += cnt; 1271 return(0); 1272 } 1273 1274 /* 1275 * Set up to transmit a packet 1276 */ 1277 static void 1278 bfe_start(struct ifnet *ifp) 1279 { 1280 struct bfe_softc *sc; 1281 struct mbuf *m_head = NULL; 1282 int idx; 1283 int s; 1284 1285 sc = ifp->if_softc; 1286 idx = sc->bfe_tx_prod; 1287 1288 s = splimp(); 1289 1290 /* 1291 * not much point trying to send if the link is down or we have nothing to 1292 * send 1293 */ 1294 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1295 splx(s); 1296 return; 1297 } 1298 1299 if (ifp->if_flags & IFF_OACTIVE) { 1300 splx(s); 1301 return; 1302 } 1303 1304 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1305 IF_DEQUEUE(&ifp->if_snd, m_head); 1306 if (m_head == NULL) 1307 break; 1308 1309 /* 1310 * Pack the data into the tx ring. If we dont have enough room, let 1311 * the chip drain the ring 1312 */ 1313 if (bfe_encap(sc, m_head, &idx)) { 1314 IF_PREPEND(&ifp->if_snd, m_head); 1315 ifp->if_flags |= IFF_OACTIVE; 1316 break; 1317 } 1318 1319 /* 1320 * If there's a BPF listener, bounce a copy of this frame 1321 * to him. 1322 */ 1323 BPF_MTAP(ifp, m_head); 1324 } 1325 1326 sc->bfe_tx_prod = idx; 1327 /* Transmit - twice due to apparent hardware bug */ 1328 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1329 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1330 1331 /* 1332 * Set a timeout in case the chip goes out to lunch. 1333 */ 1334 ifp->if_timer = 5; 1335 splx(s); 1336 } 1337 1338 static void 1339 bfe_init(void *xsc) 1340 { 1341 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1342 struct ifnet *ifp = &sc->arpcom.ac_if; 1343 int s; 1344 1345 s = splimp(); 1346 1347 if (ifp->if_flags & IFF_RUNNING) { 1348 splx(s); 1349 return; 1350 } 1351 1352 bfe_stop(sc); 1353 bfe_chip_reset(sc); 1354 1355 if (bfe_list_rx_init(sc) == ENOBUFS) { 1356 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n", 1357 sc->bfe_unit); 1358 bfe_stop(sc); 1359 return; 1360 } 1361 1362 bfe_set_rx_mode(sc); 1363 1364 /* Enable the chip and core */ 1365 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1366 /* Enable interrupts */ 1367 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1368 1369 bfe_ifmedia_upd(ifp); 1370 ifp->if_flags |= IFF_RUNNING; 1371 ifp->if_flags &= ~IFF_OACTIVE; 1372 1373 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1374 splx(s); 1375 } 1376 1377 /* 1378 * Set media options. 1379 */ 1380 static int 1381 bfe_ifmedia_upd(struct ifnet *ifp) 1382 { 1383 struct bfe_softc *sc; 1384 struct mii_data *mii; 1385 int s; 1386 1387 sc = ifp->if_softc; 1388 1389 s = splimp(); 1390 1391 mii = device_get_softc(sc->bfe_miibus); 1392 sc->bfe_link = 0; 1393 if (mii->mii_instance) { 1394 struct mii_softc *miisc; 1395 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1396 miisc = LIST_NEXT(miisc, mii_list)) 1397 mii_phy_reset(miisc); 1398 } 1399 mii_mediachg(mii); 1400 1401 splx(s); 1402 return(0); 1403 } 1404 1405 /* 1406 * Report current media status. 1407 */ 1408 static void 1409 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1410 { 1411 struct bfe_softc *sc = ifp->if_softc; 1412 struct mii_data *mii; 1413 int s; 1414 1415 s = splimp(); 1416 1417 mii = device_get_softc(sc->bfe_miibus); 1418 mii_pollstat(mii); 1419 ifmr->ifm_active = mii->mii_media_active; 1420 ifmr->ifm_status = mii->mii_media_status; 1421 1422 splx(s); 1423 } 1424 1425 static int 1426 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1427 { 1428 struct bfe_softc *sc = ifp->if_softc; 1429 struct ifreq *ifr = (struct ifreq *) data; 1430 struct mii_data *mii; 1431 int error = 0; 1432 int s; 1433 1434 s = splimp(); 1435 1436 switch (command) { 1437 case SIOCSIFFLAGS: 1438 if (ifp->if_flags & IFF_UP) 1439 if (ifp->if_flags & IFF_RUNNING) 1440 bfe_set_rx_mode(sc); 1441 else 1442 bfe_init(sc); 1443 else if (ifp->if_flags & IFF_RUNNING) 1444 bfe_stop(sc); 1445 break; 1446 case SIOCADDMULTI: 1447 case SIOCDELMULTI: 1448 if (ifp->if_flags & IFF_RUNNING) 1449 bfe_set_rx_mode(sc); 1450 break; 1451 case SIOCGIFMEDIA: 1452 case SIOCSIFMEDIA: 1453 mii = device_get_softc(sc->bfe_miibus); 1454 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1455 command); 1456 break; 1457 case SIOCSIFADDR: 1458 case SIOCGIFADDR: 1459 case SIOCSIFMTU: 1460 error = ether_ioctl(ifp, command, data); 1461 break; 1462 1463 default: 1464 error = EINVAL; 1465 break; 1466 } 1467 1468 splx(s); 1469 return error; 1470 } 1471 1472 static void 1473 bfe_watchdog(struct ifnet *ifp) 1474 { 1475 struct bfe_softc *sc; 1476 int s; 1477 1478 sc = ifp->if_softc; 1479 1480 s = splimp(); 1481 1482 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1483 1484 ifp->if_flags &= ~IFF_RUNNING; 1485 bfe_init(sc); 1486 1487 ifp->if_oerrors++; 1488 1489 splx(s); 1490 } 1491 1492 static void 1493 bfe_tick(void *xsc) 1494 { 1495 struct bfe_softc *sc = xsc; 1496 struct mii_data *mii; 1497 int s; 1498 1499 if (sc == NULL) 1500 return; 1501 1502 s = splimp(); 1503 1504 mii = device_get_softc(sc->bfe_miibus); 1505 1506 bfe_stats_update(sc); 1507 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1508 1509 if (sc->bfe_link) { 1510 splx(s); 1511 return; 1512 } 1513 1514 mii_tick(mii); 1515 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1516 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1517 sc->bfe_link++; 1518 1519 if (!sc->bfe_link) 1520 sc->bfe_link++; 1521 1522 splx(s); 1523 } 1524 1525 /* 1526 * Stop the adapter and free any mbufs allocated to the 1527 * RX and TX lists. 1528 */ 1529 static void 1530 bfe_stop(struct bfe_softc *sc) 1531 { 1532 struct ifnet *ifp; 1533 int s; 1534 1535 s = splimp(); 1536 1537 callout_stop(&sc->bfe_stat_timer); 1538 1539 ifp = &sc->arpcom.ac_if; 1540 1541 bfe_chip_halt(sc); 1542 bfe_tx_ring_free(sc); 1543 bfe_rx_ring_free(sc); 1544 1545 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1546 1547 splx(s); 1548 } 1549