1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.23 2005/08/10 15:18:52 joerg Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/thread2.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <net/bpf.h> 53 54 #include <net/if_types.h> 55 #include <net/vlan/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 61 #include <machine/bus_memio.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 #include <bus/pci/pcidevs.h> 70 71 #include <dev/netif/mii_layer/mii.h> 72 #include <dev/netif/mii_layer/miivar.h> 73 74 #include "if_bfereg.h" 75 76 MODULE_DEPEND(bfe, pci, 1, 1, 1); 77 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 78 79 /* "controller miibus0" required. See GENERIC if you get errors here. */ 80 #include "miibus_if.h" 81 82 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 83 84 static struct bfe_type bfe_devs[] = { 85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 86 "Broadcom BCM4401 Fast Ethernet" }, 87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 88 "Broadcom BCM4401-B0 Fast Ethernet" }, 89 { 0, 0, NULL } 90 }; 91 92 static int bfe_probe(device_t); 93 static int bfe_attach(device_t); 94 static int bfe_detach(device_t); 95 static void bfe_intr(void *); 96 static void bfe_start(struct ifnet *); 97 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 98 static void bfe_init(void *); 99 static void bfe_stop(struct bfe_softc *); 100 static void bfe_watchdog(struct ifnet *); 101 static void bfe_shutdown(device_t); 102 static void bfe_tick(void *); 103 static void bfe_txeof(struct bfe_softc *); 104 static void bfe_rxeof(struct bfe_softc *); 105 static void bfe_set_rx_mode(struct bfe_softc *); 106 static int bfe_list_rx_init(struct bfe_softc *); 107 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free(struct bfe_softc *); 109 110 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 111 static int bfe_ifmedia_upd(struct ifnet *); 112 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg(device_t, int, int); 114 static int bfe_miibus_writereg(device_t, int, int, int); 115 static void bfe_miibus_statchg(device_t); 116 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 117 u_long, const int); 118 static void bfe_get_config(struct bfe_softc *sc); 119 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 120 static void bfe_stats_update(struct bfe_softc *); 121 static void bfe_clear_stats (struct bfe_softc *); 122 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 123 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 124 static int bfe_resetphy(struct bfe_softc *); 125 static int bfe_setupphy(struct bfe_softc *); 126 static void bfe_chip_reset(struct bfe_softc *); 127 static void bfe_chip_halt(struct bfe_softc *); 128 static void bfe_core_reset(struct bfe_softc *); 129 static void bfe_core_disable(struct bfe_softc *); 130 static int bfe_dma_alloc(device_t); 131 static void bfe_dma_free(struct bfe_softc *); 132 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 133 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 134 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 135 136 static device_method_t bfe_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, bfe_probe), 139 DEVMETHOD(device_attach, bfe_attach), 140 DEVMETHOD(device_detach, bfe_detach), 141 DEVMETHOD(device_shutdown, bfe_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 149 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 150 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 151 152 { 0, 0 } 153 }; 154 155 static driver_t bfe_driver = { 156 "bfe", 157 bfe_methods, 158 sizeof(struct bfe_softc) 159 }; 160 161 static devclass_t bfe_devclass; 162 163 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 164 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 165 166 /* 167 * Probe for a Broadcom 4401 chip. 168 */ 169 static int 170 bfe_probe(device_t dev) 171 { 172 struct bfe_type *t; 173 uint16_t vendor, product; 174 175 vendor = pci_get_vendor(dev); 176 product = pci_get_device(dev); 177 178 for (t = bfe_devs; t->bfe_name != NULL; t++) { 179 if (vendor == t->bfe_vid && product == t->bfe_did) { 180 device_set_desc(dev, t->bfe_name); 181 return(0); 182 } 183 } 184 185 return(ENXIO); 186 } 187 188 static int 189 bfe_dma_alloc(device_t dev) 190 { 191 struct bfe_softc *sc; 192 int error, i, tx_pos, rx_pos; 193 194 sc = device_get_softc(dev); 195 196 /* parent tag */ 197 error = bus_dma_tag_create(NULL, /* parent */ 198 PAGE_SIZE, 0, /* alignment, boundary */ 199 BUS_SPACE_MAXADDR, /* lowaddr */ 200 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 201 NULL, NULL, /* filter, filterarg */ 202 MAXBSIZE, /* maxsize */ 203 BUS_SPACE_UNRESTRICTED, /* num of segments */ 204 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 205 BUS_DMA_ALLOCNOW, /* flags */ 206 &sc->bfe_parent_tag); 207 208 if (error) { 209 device_printf(dev, "could not allocate parent dma tag\n"); 210 return(error); 211 } 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE, 215 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 216 NULL, NULL, BFE_TX_LIST_SIZE, 1, 217 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag); 218 219 if (error) { 220 device_printf(dev, "could not allocate dma tag for TX list\n"); 221 return(error); 222 } 223 224 /* tag for RX ring */ 225 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE, 226 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 227 NULL, NULL, BFE_RX_LIST_SIZE, 1, 228 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag); 229 230 if (error) { 231 device_printf(dev, "could not allocate dma tag for RX list\n"); 232 return(error); 233 } 234 235 /* tag for mbufs */ 236 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 238 1, BUS_SPACE_MAXSIZE_32BIT, 0, 239 &sc->bfe_tag); 240 241 if (error) { 242 device_printf(dev, "could not allocate dma tag for mbufs\n"); 243 return(error); 244 } 245 246 rx_pos = tx_pos = 0; 247 248 /* pre allocate dmamaps for RX list */ 249 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 250 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map); 251 if (error) { 252 rx_pos = i; 253 device_printf(dev, "cannot create DMA map for RX\n"); 254 goto ring_fail; 255 } 256 } 257 rx_pos = BFE_RX_LIST_CNT; 258 259 /* pre allocate dmamaps for TX list */ 260 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map); 262 if (error) { 263 tx_pos = i; 264 device_printf(dev, "cannot create DMA map for TX\n"); 265 goto ring_fail; 266 } 267 } 268 269 /* Alloc dma for rx ring */ 270 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 271 BUS_DMA_WAITOK, &sc->bfe_rx_map); 272 273 if (error) { 274 device_printf(dev, "cannot allocate DMA mem for RX\n"); 275 return(error); 276 } 277 278 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 279 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 280 sc->bfe_rx_list, sizeof(struct bfe_desc), 281 bfe_dma_map, &sc->bfe_rx_dma, 0); 282 283 if (error) { 284 device_printf(dev, "cannot load DMA map for RX\n"); 285 return(error); 286 } 287 288 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 289 290 /* Alloc dma for tx ring */ 291 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 292 BUS_DMA_WAITOK, &sc->bfe_tx_map); 293 if (error) { 294 device_printf(dev, "cannot allocate DMA mem for TX\n"); 295 return(error); 296 } 297 298 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 299 sc->bfe_tx_list, sizeof(struct bfe_desc), 300 bfe_dma_map, &sc->bfe_tx_dma, 0); 301 if (error) { 302 device_printf(dev, "cannot load DMA map for TX\n"); 303 return(error); 304 } 305 306 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 307 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 308 309 return(0); 310 311 ring_fail: 312 for (i = 0; i < rx_pos; ++i) 313 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map); 314 for (i = 0; i < tx_pos; ++i) 315 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 316 317 bus_dma_tag_destroy(sc->bfe_tag); 318 sc->bfe_tag = NULL; 319 return error; 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp; 326 struct bfe_softc *sc; 327 int error = 0, rid; 328 329 sc = device_get_softc(dev); 330 331 sc->bfe_dev = dev; 332 callout_init(&sc->bfe_stat_timer); 333 334 /* 335 * Handle power management nonsense. 336 */ 337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 338 uint32_t membase, irq; 339 340 /* Save important PCI config data. */ 341 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 342 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 343 344 /* Reset the power state. */ 345 device_printf(dev, "chip is in D%d power mode" 346 " -- setting to D0\n", pci_get_powerstate(dev)); 347 348 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 349 350 /* Restore PCI config data. */ 351 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 352 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 353 } 354 355 /* 356 * Map control/status registers. 357 */ 358 pci_enable_busmaster(dev); 359 360 rid = BFE_PCI_MEMLO; 361 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 362 RF_ACTIVE); 363 if (sc->bfe_res == NULL) { 364 device_printf(dev, "couldn't map memory\n"); 365 return ENXIO; 366 } 367 368 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 369 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 370 371 /* Allocate interrupt */ 372 rid = 0; 373 374 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 375 RF_SHAREABLE | RF_ACTIVE); 376 if (sc->bfe_irq == NULL) { 377 device_printf(dev, "couldn't map interrupt\n"); 378 error = ENXIO; 379 goto fail; 380 } 381 382 error = bfe_dma_alloc(dev); 383 if (error != 0) { 384 device_printf(dev, "failed to allocate DMA resources\n"); 385 goto fail; 386 } 387 388 /* Set up ifnet structure */ 389 ifp = &sc->arpcom.ac_if; 390 ifp->if_softc = sc; 391 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 393 ifp->if_ioctl = bfe_ioctl; 394 ifp->if_start = bfe_start; 395 ifp->if_watchdog = bfe_watchdog; 396 ifp->if_init = bfe_init; 397 ifp->if_mtu = ETHERMTU; 398 ifp->if_baudrate = 100000000; 399 ifp->if_capabilities |= IFCAP_VLAN_MTU; 400 ifp->if_capenable |= IFCAP_VLAN_MTU; 401 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 402 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 403 ifq_set_ready(&ifp->if_snd); 404 405 bfe_get_config(sc); 406 407 /* Reset the chip and turn on the PHY */ 408 bfe_chip_reset(sc); 409 410 if (mii_phy_probe(dev, &sc->bfe_miibus, 411 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 412 device_printf(dev, "MII without any PHY!\n"); 413 error = ENXIO; 414 goto fail; 415 } 416 417 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 418 419 /* 420 * Hook interrupt last to avoid having to lock softc 421 */ 422 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 423 bfe_intr, sc, &sc->bfe_intrhand, NULL); 424 425 if (error) { 426 ether_ifdetach(ifp); 427 device_printf(dev, "couldn't set up irq\n"); 428 goto fail; 429 } 430 return 0; 431 fail: 432 bfe_detach(dev); 433 return(error); 434 } 435 436 static int 437 bfe_detach(device_t dev) 438 { 439 struct bfe_softc *sc = device_get_softc(dev); 440 struct ifnet *ifp = &sc->arpcom.ac_if; 441 442 crit_enter(); 443 444 if (device_is_attached(dev)) { 445 bfe_stop(sc); 446 ether_ifdetach(ifp); 447 bfe_chip_reset(sc); 448 } 449 if (sc->bfe_miibus != NULL) 450 device_delete_child(dev, sc->bfe_miibus); 451 bus_generic_detach(dev); 452 453 if (sc->bfe_intrhand != NULL) 454 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 455 456 crit_exit(); 457 458 if (sc->bfe_irq != NULL) 459 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 460 461 if (sc->bfe_res != NULL) { 462 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 463 sc->bfe_res); 464 } 465 466 bfe_dma_free(sc); 467 return(0); 468 } 469 470 /* 471 * Stop all chip I/O so that the kernel's probe routines don't 472 * get confused by errant DMAs when rebooting. 473 */ 474 static void 475 bfe_shutdown(device_t dev) 476 { 477 struct bfe_softc *sc = device_get_softc(dev); 478 479 crit_enter(); 480 481 bfe_stop(sc); 482 483 crit_exit(); 484 } 485 486 static int 487 bfe_miibus_readreg(device_t dev, int phy, int reg) 488 { 489 struct bfe_softc *sc; 490 uint32_t ret; 491 492 sc = device_get_softc(dev); 493 if (phy != sc->bfe_phyaddr) 494 return(0); 495 bfe_readphy(sc, reg, &ret); 496 497 return(ret); 498 } 499 500 static int 501 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 502 { 503 struct bfe_softc *sc; 504 505 sc = device_get_softc(dev); 506 if (phy != sc->bfe_phyaddr) 507 return(0); 508 bfe_writephy(sc, reg, val); 509 510 return(0); 511 } 512 513 static void 514 bfe_miibus_statchg(device_t dev) 515 { 516 return; 517 } 518 519 static void 520 bfe_tx_ring_free(struct bfe_softc *sc) 521 { 522 int i; 523 524 for (i = 0; i < BFE_TX_LIST_CNT; i++) 525 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 526 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 527 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 528 bus_dmamap_unload(sc->bfe_tag, 529 sc->bfe_tx_ring[i].bfe_map); 530 } 531 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 532 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 533 } 534 535 static void 536 bfe_rx_ring_free(struct bfe_softc *sc) 537 { 538 int i; 539 540 for (i = 0; i < BFE_RX_LIST_CNT; i++) 541 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 542 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 543 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 544 bus_dmamap_unload(sc->bfe_tag, 545 sc->bfe_rx_ring[i].bfe_map); 546 } 547 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 548 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 549 } 550 551 552 static int 553 bfe_list_rx_init(struct bfe_softc *sc) 554 { 555 int i; 556 557 for (i = 0; i < BFE_RX_LIST_CNT; i++) 558 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 559 return(ENOBUFS); 560 561 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 562 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 563 564 sc->bfe_rx_cons = 0; 565 566 return(0); 567 } 568 569 static int 570 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 571 { 572 struct bfe_rxheader *rx_header; 573 struct bfe_desc *d; 574 struct bfe_data *r; 575 uint32_t ctrl; 576 577 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 578 return(EINVAL); 579 580 if (m == NULL) { 581 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 582 if (m == NULL) 583 return(ENOBUFS); 584 m->m_len = m->m_pkthdr.len = MCLBYTES; 585 } 586 else 587 m->m_data = m->m_ext.ext_buf; 588 589 rx_header = mtod(m, struct bfe_rxheader *); 590 rx_header->len = 0; 591 rx_header->flags = 0; 592 593 /* Map the mbuf into DMA */ 594 sc->bfe_rx_cnt = c; 595 d = &sc->bfe_rx_list[c]; 596 r = &sc->bfe_rx_ring[c]; 597 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 598 MCLBYTES, bfe_dma_map_desc, d, 0); 599 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 600 601 ctrl = ETHER_MAX_LEN + 32; 602 603 if(c == BFE_RX_LIST_CNT - 1) 604 ctrl |= BFE_DESC_EOT; 605 606 d->bfe_ctrl = ctrl; 607 r->bfe_mbuf = m; 608 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 609 return(0); 610 } 611 612 static void 613 bfe_get_config(struct bfe_softc *sc) 614 { 615 uint8_t eeprom[128]; 616 617 bfe_read_eeprom(sc, eeprom); 618 619 sc->arpcom.ac_enaddr[0] = eeprom[79]; 620 sc->arpcom.ac_enaddr[1] = eeprom[78]; 621 sc->arpcom.ac_enaddr[2] = eeprom[81]; 622 sc->arpcom.ac_enaddr[3] = eeprom[80]; 623 sc->arpcom.ac_enaddr[4] = eeprom[83]; 624 sc->arpcom.ac_enaddr[5] = eeprom[82]; 625 626 sc->bfe_phyaddr = eeprom[90] & 0x1f; 627 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 628 629 sc->bfe_core_unit = 0; 630 sc->bfe_dma_offset = BFE_PCI_DMA; 631 } 632 633 static void 634 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 635 { 636 uint32_t bar_orig, pci_rev, val; 637 638 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 639 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 640 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 641 642 val = CSR_READ_4(sc, BFE_SBINTVEC); 643 val |= cores; 644 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 645 646 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 647 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 648 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 649 650 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 651 } 652 653 static void 654 bfe_clear_stats(struct bfe_softc *sc) 655 { 656 u_long reg; 657 658 crit_enter(); 659 660 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 661 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 662 CSR_READ_4(sc, reg); 663 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 664 CSR_READ_4(sc, reg); 665 666 crit_exit(); 667 } 668 669 static int 670 bfe_resetphy(struct bfe_softc *sc) 671 { 672 uint32_t val; 673 674 crit_enter(); 675 676 bfe_writephy(sc, 0, BMCR_RESET); 677 DELAY(100); 678 bfe_readphy(sc, 0, &val); 679 if (val & BMCR_RESET) { 680 crit_exit(); 681 if_printf(&sc->arpcom.ac_if, 682 "PHY Reset would not complete.\n"); 683 return(ENXIO); 684 } 685 686 crit_exit(); 687 return(0); 688 } 689 690 static void 691 bfe_chip_halt(struct bfe_softc *sc) 692 { 693 crit_enter(); 694 695 /* disable interrupts - not that it actually does..*/ 696 CSR_WRITE_4(sc, BFE_IMASK, 0); 697 CSR_READ_4(sc, BFE_IMASK); 698 699 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 700 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 701 702 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 703 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 704 DELAY(10); 705 706 crit_exit(); 707 } 708 709 static void 710 bfe_chip_reset(struct bfe_softc *sc) 711 { 712 uint32_t val; 713 714 crit_enter(); 715 716 /* Set the interrupt vector for the enet core */ 717 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 718 719 /* is core up? */ 720 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 721 if (val == BFE_CLOCK) { 722 /* It is, so shut it down */ 723 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 724 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 725 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 726 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 727 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 728 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 729 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 730 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 731 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 732 } 733 734 bfe_core_reset(sc); 735 bfe_clear_stats(sc); 736 737 /* 738 * We want the phy registers to be accessible even when 739 * the driver is "downed" so initialize MDC preamble, frequency, 740 * and whether internal or external phy here. 741 */ 742 743 /* 4402 has 62.5Mhz SB clock and internal phy */ 744 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 745 746 /* Internal or external PHY? */ 747 val = CSR_READ_4(sc, BFE_DEVCTRL); 748 if (!(val & BFE_IPP)) 749 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 750 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 751 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 752 DELAY(100); 753 } 754 755 /* Enable CRC32 generation and set proper LED modes */ 756 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 757 758 /* Reset or clear powerdown control bit */ 759 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 760 761 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 762 BFE_LAZY_FC_MASK)); 763 764 /* 765 * We don't want lazy interrupts, so just send them at the end of a 766 * frame, please 767 */ 768 BFE_OR(sc, BFE_RCV_LAZY, 0); 769 770 /* Set max lengths, accounting for VLAN tags */ 771 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 772 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 773 774 /* Set watermark XXX - magic */ 775 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 776 777 /* 778 * Initialise DMA channels - not forgetting dma addresses need to be 779 * added to BFE_PCI_DMA 780 */ 781 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 782 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 783 784 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 785 BFE_RX_CTRL_ENABLE); 786 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 787 788 bfe_resetphy(sc); 789 bfe_setupphy(sc); 790 791 crit_exit(); 792 } 793 794 static void 795 bfe_core_disable(struct bfe_softc *sc) 796 { 797 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 798 return; 799 800 /* 801 * Set reject, wait for it set, then wait for the core to stop being busy 802 * Then set reset and reject and enable the clocks 803 */ 804 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 805 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 806 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 807 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 808 BFE_RESET)); 809 CSR_READ_4(sc, BFE_SBTMSLOW); 810 DELAY(10); 811 /* Leave reset and reject set */ 812 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 813 DELAY(10); 814 } 815 816 static void 817 bfe_core_reset(struct bfe_softc *sc) 818 { 819 uint32_t val; 820 821 /* Disable the core */ 822 bfe_core_disable(sc); 823 824 /* and bring it back up */ 825 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 826 CSR_READ_4(sc, BFE_SBTMSLOW); 827 DELAY(10); 828 829 /* Chip bug, clear SERR, IB and TO if they are set. */ 830 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 831 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 832 val = CSR_READ_4(sc, BFE_SBIMSTATE); 833 if (val & (BFE_IBE | BFE_TO)) 834 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 835 836 /* Clear reset and allow it to move through the core */ 837 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 838 CSR_READ_4(sc, BFE_SBTMSLOW); 839 DELAY(10); 840 841 /* Leave the clock set */ 842 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 843 CSR_READ_4(sc, BFE_SBTMSLOW); 844 DELAY(10); 845 } 846 847 static void 848 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 849 { 850 uint32_t val; 851 852 val = ((uint32_t) data[2]) << 24; 853 val |= ((uint32_t) data[3]) << 16; 854 val |= ((uint32_t) data[4]) << 8; 855 val |= ((uint32_t) data[5]); 856 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 857 val = (BFE_CAM_HI_VALID | 858 (((uint32_t) data[0]) << 8) | 859 (((uint32_t) data[1]))); 860 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 861 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 862 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 863 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 864 } 865 866 static void 867 bfe_set_rx_mode(struct bfe_softc *sc) 868 { 869 struct ifnet *ifp = &sc->arpcom.ac_if; 870 struct ifmultiaddr *ifma; 871 uint32_t val; 872 int i = 0; 873 874 val = CSR_READ_4(sc, BFE_RXCONF); 875 876 if (ifp->if_flags & IFF_PROMISC) 877 val |= BFE_RXCONF_PROMISC; 878 else 879 val &= ~BFE_RXCONF_PROMISC; 880 881 if (ifp->if_flags & IFF_BROADCAST) 882 val &= ~BFE_RXCONF_DBCAST; 883 else 884 val |= BFE_RXCONF_DBCAST; 885 886 887 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 888 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 889 890 if (ifp->if_flags & IFF_ALLMULTI) { 891 val |= BFE_RXCONF_ALLMULTI; 892 } else { 893 val &= ~BFE_RXCONF_ALLMULTI; 894 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 895 if (ifma->ifma_addr->sa_family != AF_LINK) 896 continue; 897 bfe_cam_write(sc, 898 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 899 } 900 } 901 902 CSR_WRITE_4(sc, BFE_RXCONF, val); 903 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 904 } 905 906 static void 907 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 908 { 909 uint32_t *ptr; 910 911 ptr = arg; 912 *ptr = segs->ds_addr; 913 } 914 915 static void 916 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 917 { 918 struct bfe_desc *d; 919 920 d = arg; 921 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 922 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 923 } 924 925 static void 926 bfe_dma_free(struct bfe_softc *sc) 927 { 928 if (sc->bfe_tx_tag != NULL) { 929 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 930 if (sc->bfe_tx_list != NULL) { 931 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 932 sc->bfe_tx_map); 933 sc->bfe_tx_list = NULL; 934 } 935 bus_dma_tag_destroy(sc->bfe_tx_tag); 936 sc->bfe_tx_tag = NULL; 937 } 938 939 if (sc->bfe_rx_tag != NULL) { 940 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 941 if (sc->bfe_rx_list != NULL) { 942 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 943 sc->bfe_rx_map); 944 sc->bfe_rx_list = NULL; 945 } 946 bus_dma_tag_destroy(sc->bfe_rx_tag); 947 sc->bfe_rx_tag = NULL; 948 } 949 950 if (sc->bfe_tag != NULL) { 951 int i; 952 953 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 954 bus_dmamap_destroy(sc->bfe_tag, 955 sc->bfe_tx_ring[i].bfe_map); 956 } 957 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 958 bus_dmamap_destroy(sc->bfe_tag, 959 sc->bfe_rx_ring[i].bfe_map); 960 } 961 962 bus_dma_tag_destroy(sc->bfe_tag); 963 sc->bfe_tag = NULL; 964 } 965 966 if (sc->bfe_parent_tag != NULL) { 967 bus_dma_tag_destroy(sc->bfe_parent_tag); 968 sc->bfe_parent_tag = NULL; 969 } 970 } 971 972 static void 973 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 974 { 975 long i; 976 uint16_t *ptr = (uint16_t *)data; 977 978 for (i = 0; i < 128; i += 2) 979 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 980 } 981 982 static int 983 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 984 u_long timeout, const int clear) 985 { 986 u_long i; 987 988 for (i = 0; i < timeout; i++) { 989 uint32_t val = CSR_READ_4(sc, reg); 990 991 if (clear && !(val & bit)) 992 break; 993 if (!clear && (val & bit)) 994 break; 995 DELAY(10); 996 } 997 if (i == timeout) { 998 if_printf(&sc->arpcom.ac_if, 999 "BUG! Timeout waiting for bit %08x of register " 1000 "%x to %s.\n", bit, reg, 1001 (clear ? "clear" : "set")); 1002 return -1; 1003 } 1004 return 0; 1005 } 1006 1007 static int 1008 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 1009 { 1010 int err; 1011 1012 crit_enter(); 1013 1014 /* Clear MII ISR */ 1015 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1016 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1017 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1018 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1019 (reg << BFE_MDIO_RA_SHIFT) | 1020 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1021 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1022 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1023 1024 crit_exit(); 1025 return(err); 1026 } 1027 1028 static int 1029 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1030 { 1031 int status; 1032 1033 crit_enter(); 1034 1035 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1036 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1037 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1038 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1039 (reg << BFE_MDIO_RA_SHIFT) | 1040 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1041 (val & BFE_MDIO_DATA_DATA))); 1042 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1043 1044 crit_exit(); 1045 1046 return status; 1047 } 1048 1049 /* 1050 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1051 * twice 1052 */ 1053 static int 1054 bfe_setupphy(struct bfe_softc *sc) 1055 { 1056 uint32_t val; 1057 1058 crit_enter(); 1059 1060 /* Enable activity LED */ 1061 bfe_readphy(sc, 26, &val); 1062 bfe_writephy(sc, 26, val & 0x7fff); 1063 bfe_readphy(sc, 26, &val); 1064 1065 /* Enable traffic meter LED mode */ 1066 bfe_readphy(sc, 27, &val); 1067 bfe_writephy(sc, 27, val | (1 << 6)); 1068 1069 crit_exit(); 1070 return(0); 1071 } 1072 1073 static void 1074 bfe_stats_update(struct bfe_softc *sc) 1075 { 1076 u_long reg; 1077 uint32_t *val; 1078 1079 val = &sc->bfe_hwstats.tx_good_octets; 1080 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1081 *val++ += CSR_READ_4(sc, reg); 1082 val = &sc->bfe_hwstats.rx_good_octets; 1083 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1084 *val++ += CSR_READ_4(sc, reg); 1085 } 1086 1087 static void 1088 bfe_txeof(struct bfe_softc *sc) 1089 { 1090 struct ifnet *ifp = &sc->arpcom.ac_if; 1091 uint32_t i, chipidx; 1092 1093 crit_enter(); 1094 1095 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1096 chipidx /= sizeof(struct bfe_desc); 1097 1098 i = sc->bfe_tx_cons; 1099 /* Go through the mbufs and free those that have been transmitted */ 1100 while (i != chipidx) { 1101 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1102 if (r->bfe_mbuf != NULL) { 1103 ifp->if_opackets++; 1104 m_freem(r->bfe_mbuf); 1105 r->bfe_mbuf = NULL; 1106 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1107 } 1108 sc->bfe_tx_cnt--; 1109 BFE_INC(i, BFE_TX_LIST_CNT); 1110 } 1111 1112 if (i != sc->bfe_tx_cons) { 1113 /* we freed up some mbufs */ 1114 sc->bfe_tx_cons = i; 1115 ifp->if_flags &= ~IFF_OACTIVE; 1116 } 1117 if (sc->bfe_tx_cnt == 0) 1118 ifp->if_timer = 0; 1119 else 1120 ifp->if_timer = 5; 1121 1122 crit_exit(); 1123 } 1124 1125 /* Pass a received packet up the stack */ 1126 static void 1127 bfe_rxeof(struct bfe_softc *sc) 1128 { 1129 struct ifnet *ifp = &sc->arpcom.ac_if; 1130 struct mbuf *m; 1131 struct bfe_rxheader *rxheader; 1132 struct bfe_data *r; 1133 uint32_t cons, status, current, len, flags; 1134 1135 crit_enter(); 1136 1137 cons = sc->bfe_rx_cons; 1138 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1139 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1140 1141 while (current != cons) { 1142 r = &sc->bfe_rx_ring[cons]; 1143 m = r->bfe_mbuf; 1144 rxheader = mtod(m, struct bfe_rxheader*); 1145 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1146 len = rxheader->len; 1147 r->bfe_mbuf = NULL; 1148 1149 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1150 flags = rxheader->flags; 1151 1152 len -= ETHER_CRC_LEN; 1153 1154 /* flag an error and try again */ 1155 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1156 ifp->if_ierrors++; 1157 if (flags & BFE_RX_FLAG_SERR) 1158 ifp->if_collisions++; 1159 bfe_list_newbuf(sc, cons, m); 1160 BFE_INC(cons, BFE_RX_LIST_CNT); 1161 continue; 1162 } 1163 1164 /* Go past the rx header */ 1165 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1166 bfe_list_newbuf(sc, cons, m); 1167 BFE_INC(cons, BFE_RX_LIST_CNT); 1168 ifp->if_ierrors++; 1169 continue; 1170 } 1171 1172 m_adj(m, BFE_RX_OFFSET); 1173 m->m_len = m->m_pkthdr.len = len; 1174 1175 ifp->if_ipackets++; 1176 m->m_pkthdr.rcvif = ifp; 1177 1178 (*ifp->if_input)(ifp, m); 1179 BFE_INC(cons, BFE_RX_LIST_CNT); 1180 } 1181 sc->bfe_rx_cons = cons; 1182 1183 crit_exit(); 1184 } 1185 1186 static void 1187 bfe_intr(void *xsc) 1188 { 1189 struct bfe_softc *sc = xsc; 1190 struct ifnet *ifp = &sc->arpcom.ac_if; 1191 uint32_t istat, imask, flag; 1192 1193 crit_enter(); 1194 1195 istat = CSR_READ_4(sc, BFE_ISTAT); 1196 imask = CSR_READ_4(sc, BFE_IMASK); 1197 1198 /* 1199 * Defer unsolicited interrupts - This is necessary because setting the 1200 * chips interrupt mask register to 0 doesn't actually stop the 1201 * interrupts 1202 */ 1203 istat &= imask; 1204 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1205 CSR_READ_4(sc, BFE_ISTAT); 1206 1207 /* not expecting this interrupt, disregard it */ 1208 if (istat == 0) { 1209 crit_exit(); 1210 return; 1211 } 1212 1213 if (istat & BFE_ISTAT_ERRORS) { 1214 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1215 if (flag & BFE_STAT_EMASK) 1216 ifp->if_oerrors++; 1217 1218 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1219 if (flag & BFE_RX_FLAG_ERRORS) 1220 ifp->if_ierrors++; 1221 1222 ifp->if_flags &= ~IFF_RUNNING; 1223 bfe_init(sc); 1224 } 1225 1226 /* A packet was received */ 1227 if (istat & BFE_ISTAT_RX) 1228 bfe_rxeof(sc); 1229 1230 /* A packet was sent */ 1231 if (istat & BFE_ISTAT_TX) 1232 bfe_txeof(sc); 1233 1234 /* We have packets pending, fire them out */ 1235 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1236 bfe_start(ifp); 1237 1238 crit_exit(); 1239 } 1240 1241 static int 1242 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1243 { 1244 struct bfe_desc *d = NULL; 1245 struct bfe_data *r = NULL; 1246 struct mbuf *m; 1247 uint32_t frag, cur, cnt = 0; 1248 1249 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1250 return(ENOBUFS); 1251 1252 /* 1253 * Start packing the mbufs in this chain into 1254 * the fragment pointers. Stop when we run out 1255 * of fragments or hit the end of the mbuf chain. 1256 */ 1257 m = m_head; 1258 cur = frag = *txidx; 1259 cnt = 0; 1260 1261 for (m = m_head; m != NULL; m = m->m_next) { 1262 if (m->m_len != 0) { 1263 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1264 return(ENOBUFS); 1265 1266 d = &sc->bfe_tx_list[cur]; 1267 r = &sc->bfe_tx_ring[cur]; 1268 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1269 /* always intterupt on completion */ 1270 d->bfe_ctrl |= BFE_DESC_IOC; 1271 if (cnt == 0) 1272 /* Set start of frame */ 1273 d->bfe_ctrl |= BFE_DESC_SOF; 1274 if (cur == BFE_TX_LIST_CNT - 1) 1275 /* 1276 * Tell the chip to wrap to the start of the 1277 *descriptor list 1278 */ 1279 d->bfe_ctrl |= BFE_DESC_EOT; 1280 1281 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), 1282 m->m_len, bfe_dma_map_desc, d, 0); 1283 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1284 BUS_DMASYNC_PREREAD); 1285 1286 frag = cur; 1287 BFE_INC(cur, BFE_TX_LIST_CNT); 1288 cnt++; 1289 } 1290 } 1291 1292 if (m != NULL) 1293 return(ENOBUFS); 1294 1295 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1296 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1297 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1298 1299 *txidx = cur; 1300 sc->bfe_tx_cnt += cnt; 1301 return(0); 1302 } 1303 1304 /* 1305 * Set up to transmit a packet 1306 */ 1307 static void 1308 bfe_start(struct ifnet *ifp) 1309 { 1310 struct bfe_softc *sc = ifp->if_softc; 1311 struct mbuf *m_head = NULL; 1312 int idx, need_trans; 1313 1314 crit_enter(); 1315 1316 /* 1317 * Not much point trying to send if the link is down 1318 * or we have nothing to send. 1319 */ 1320 if (!sc->bfe_link) { 1321 crit_exit(); 1322 return; 1323 } 1324 1325 if (ifp->if_flags & IFF_OACTIVE) { 1326 crit_exit(); 1327 return; 1328 } 1329 1330 idx = sc->bfe_tx_prod; 1331 1332 need_trans = 0; 1333 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1334 m_head = ifq_poll(&ifp->if_snd); 1335 if (m_head == NULL) 1336 break; 1337 1338 /* 1339 * Pack the data into the tx ring. If we don't have 1340 * enough room, let the chip drain the ring. 1341 */ 1342 if (bfe_encap(sc, m_head, &idx)) { 1343 ifp->if_flags |= IFF_OACTIVE; 1344 break; 1345 } 1346 m_head = ifq_dequeue(&ifp->if_snd); 1347 need_trans = 1; 1348 1349 /* 1350 * If there's a BPF listener, bounce a copy of this frame 1351 * to him. 1352 */ 1353 BPF_MTAP(ifp, m_head); 1354 } 1355 1356 if (!need_trans) { 1357 crit_exit(); 1358 return; 1359 } 1360 1361 sc->bfe_tx_prod = idx; 1362 /* Transmit - twice due to apparent hardware bug */ 1363 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1364 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1365 1366 /* 1367 * Set a timeout in case the chip goes out to lunch. 1368 */ 1369 ifp->if_timer = 5; 1370 1371 crit_exit(); 1372 } 1373 1374 static void 1375 bfe_init(void *xsc) 1376 { 1377 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1378 struct ifnet *ifp = &sc->arpcom.ac_if; 1379 1380 crit_enter(); 1381 1382 if (ifp->if_flags & IFF_RUNNING) { 1383 crit_exit(); 1384 return; 1385 } 1386 1387 bfe_stop(sc); 1388 bfe_chip_reset(sc); 1389 1390 if (bfe_list_rx_init(sc) == ENOBUFS) { 1391 if_printf(ifp, "bfe_init failed. " 1392 " Not enough memory for list buffers\n"); 1393 bfe_stop(sc); 1394 crit_exit(); 1395 return; 1396 } 1397 1398 bfe_set_rx_mode(sc); 1399 1400 /* Enable the chip and core */ 1401 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1402 /* Enable interrupts */ 1403 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1404 1405 bfe_ifmedia_upd(ifp); 1406 ifp->if_flags |= IFF_RUNNING; 1407 ifp->if_flags &= ~IFF_OACTIVE; 1408 1409 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1410 crit_exit(); 1411 } 1412 1413 /* 1414 * Set media options. 1415 */ 1416 static int 1417 bfe_ifmedia_upd(struct ifnet *ifp) 1418 { 1419 struct bfe_softc *sc = ifp->if_softc; 1420 struct mii_data *mii; 1421 1422 crit_enter(); 1423 1424 mii = device_get_softc(sc->bfe_miibus); 1425 sc->bfe_link = 0; 1426 if (mii->mii_instance) { 1427 struct mii_softc *miisc; 1428 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1429 miisc = LIST_NEXT(miisc, mii_list)) 1430 mii_phy_reset(miisc); 1431 } 1432 mii_mediachg(mii); 1433 1434 crit_exit(); 1435 return(0); 1436 } 1437 1438 /* 1439 * Report current media status. 1440 */ 1441 static void 1442 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1443 { 1444 struct bfe_softc *sc = ifp->if_softc; 1445 struct mii_data *mii; 1446 1447 crit_enter(); 1448 1449 mii = device_get_softc(sc->bfe_miibus); 1450 mii_pollstat(mii); 1451 ifmr->ifm_active = mii->mii_media_active; 1452 ifmr->ifm_status = mii->mii_media_status; 1453 1454 crit_exit(); 1455 } 1456 1457 static int 1458 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1459 { 1460 struct bfe_softc *sc = ifp->if_softc; 1461 struct ifreq *ifr = (struct ifreq *) data; 1462 struct mii_data *mii; 1463 int error = 0; 1464 1465 crit_enter(); 1466 1467 switch (command) { 1468 case SIOCSIFFLAGS: 1469 if (ifp->if_flags & IFF_UP) 1470 if (ifp->if_flags & IFF_RUNNING) 1471 bfe_set_rx_mode(sc); 1472 else 1473 bfe_init(sc); 1474 else if (ifp->if_flags & IFF_RUNNING) 1475 bfe_stop(sc); 1476 break; 1477 case SIOCADDMULTI: 1478 case SIOCDELMULTI: 1479 if (ifp->if_flags & IFF_RUNNING) 1480 bfe_set_rx_mode(sc); 1481 break; 1482 case SIOCGIFMEDIA: 1483 case SIOCSIFMEDIA: 1484 mii = device_get_softc(sc->bfe_miibus); 1485 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1486 command); 1487 break; 1488 default: 1489 error = ether_ioctl(ifp, command, data); 1490 break; 1491 } 1492 1493 crit_exit(); 1494 1495 return error; 1496 } 1497 1498 static void 1499 bfe_watchdog(struct ifnet *ifp) 1500 { 1501 struct bfe_softc *sc = ifp->if_softc; 1502 1503 if_printf(ifp, "watchdog timeout -- resetting\n"); 1504 1505 crit_enter(); 1506 1507 ifp->if_flags &= ~IFF_RUNNING; 1508 bfe_init(sc); 1509 1510 ifp->if_oerrors++; 1511 1512 crit_exit(); 1513 } 1514 1515 static void 1516 bfe_tick(void *xsc) 1517 { 1518 struct bfe_softc *sc = xsc; 1519 struct mii_data *mii; 1520 1521 crit_enter(); 1522 1523 mii = device_get_softc(sc->bfe_miibus); 1524 1525 bfe_stats_update(sc); 1526 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1527 1528 if (sc->bfe_link) { 1529 crit_exit(); 1530 return; 1531 } 1532 1533 mii_tick(mii); 1534 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1535 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1536 sc->bfe_link++; 1537 1538 if (!sc->bfe_link) 1539 sc->bfe_link++; 1540 1541 crit_exit(); 1542 } 1543 1544 /* 1545 * Stop the adapter and free any mbufs allocated to the 1546 * RX and TX lists. 1547 */ 1548 static void 1549 bfe_stop(struct bfe_softc *sc) 1550 { 1551 struct ifnet *ifp = &sc->arpcom.ac_if; 1552 1553 crit_enter(); 1554 1555 callout_stop(&sc->bfe_stat_timer); 1556 1557 bfe_chip_halt(sc); 1558 bfe_tx_ring_free(sc); 1559 bfe_rx_ring_free(sc); 1560 1561 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1562 1563 crit_exit(); 1564 } 1565