1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.32 2008/03/23 09:44:36 sephe Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/rman.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 54 #include <net/bpf.h> 55 56 #include <net/if_types.h> 57 #include <net/vlan/if_vlan_var.h> 58 59 #include <netinet/in_systm.h> 60 #include <netinet/in.h> 61 #include <netinet/ip.h> 62 63 #include <bus/pci/pcireg.h> 64 #include <bus/pci/pcivar.h> 65 #include <bus/pci/pcidevs.h> 66 67 #include <dev/netif/mii_layer/mii.h> 68 #include <dev/netif/mii_layer/miivar.h> 69 70 #include <dev/netif/bfe/if_bfereg.h> 71 72 MODULE_DEPEND(bfe, pci, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "controller miibus0" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402, 86 "Broadcom BCM4402 Fast Ethernet" }, 87 { 0, 0, NULL } 88 }; 89 90 static int bfe_probe(device_t); 91 static int bfe_attach(device_t); 92 static int bfe_detach(device_t); 93 static void bfe_intr(void *); 94 static void bfe_start(struct ifnet *); 95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 96 static void bfe_init(void *); 97 static void bfe_stop(struct bfe_softc *); 98 static void bfe_watchdog(struct ifnet *); 99 static void bfe_shutdown(device_t); 100 static void bfe_tick(void *); 101 static void bfe_txeof(struct bfe_softc *); 102 static void bfe_rxeof(struct bfe_softc *); 103 static void bfe_set_rx_mode(struct bfe_softc *); 104 static int bfe_list_rx_init(struct bfe_softc *); 105 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 106 static void bfe_rx_ring_free(struct bfe_softc *); 107 108 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 109 static int bfe_ifmedia_upd(struct ifnet *); 110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 111 static int bfe_miibus_readreg(device_t, int, int); 112 static int bfe_miibus_writereg(device_t, int, int, int); 113 static void bfe_miibus_statchg(device_t); 114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 115 u_long, const int); 116 static void bfe_get_config(struct bfe_softc *sc); 117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 118 static void bfe_stats_update(struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 122 static int bfe_resetphy(struct bfe_softc *); 123 static int bfe_setupphy(struct bfe_softc *); 124 static void bfe_chip_reset(struct bfe_softc *); 125 static void bfe_chip_halt(struct bfe_softc *); 126 static void bfe_core_reset(struct bfe_softc *); 127 static void bfe_core_disable(struct bfe_softc *); 128 static int bfe_dma_alloc(device_t); 129 static void bfe_dma_free(struct bfe_softc *); 130 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 uint16_t vendor, product; 172 173 vendor = pci_get_vendor(dev); 174 product = pci_get_device(dev); 175 176 for (t = bfe_devs; t->bfe_name != NULL; t++) { 177 if (vendor == t->bfe_vid && product == t->bfe_did) { 178 device_set_desc(dev, t->bfe_name); 179 return(0); 180 } 181 } 182 183 return(ENXIO); 184 } 185 186 static int 187 bfe_dma_alloc(device_t dev) 188 { 189 struct bfe_softc *sc = device_get_softc(dev); 190 int error, i, tx_pos, rx_pos; 191 192 /* 193 * parent tag. Apparently the chip cannot handle any DMA address 194 * greater than 1GB. 195 */ 196 error = bus_dma_tag_create(NULL, /* parent */ 197 4096, 0, /* alignment, boundary */ 198 0x3FFFFFFF, /* lowaddr */ 199 BUS_SPACE_MAXADDR, /* highaddr */ 200 NULL, NULL, /* filter, filterarg */ 201 MAXBSIZE, /* maxsize */ 202 BUS_SPACE_UNRESTRICTED, /* num of segments */ 203 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 204 0, /* flags */ 205 &sc->bfe_parent_tag); 206 if (error) { 207 device_printf(dev, "could not allocate parent dma tag\n"); 208 return(error); 209 } 210 211 /* tag for TX ring */ 212 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0, 213 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 214 NULL, NULL, 215 BFE_TX_LIST_SIZE, 1, 216 BUS_SPACE_MAXSIZE_32BIT, 217 0, &sc->bfe_tx_tag); 218 if (error) { 219 device_printf(dev, "could not allocate dma tag for TX list\n"); 220 return(error); 221 } 222 223 /* tag for RX ring */ 224 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0, 225 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 226 NULL, NULL, 227 BFE_RX_LIST_SIZE, 1, 228 BUS_SPACE_MAXSIZE_32BIT, 229 0, &sc->bfe_rx_tag); 230 if (error) { 231 device_printf(dev, "could not allocate dma tag for RX list\n"); 232 return(error); 233 } 234 235 /* tag for mbufs */ 236 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 238 NULL, NULL, 239 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT, 240 BUS_DMA_ALLOCNOW, &sc->bfe_tag); 241 if (error) { 242 device_printf(dev, "could not allocate dma tag for mbufs\n"); 243 return(error); 244 } 245 246 rx_pos = tx_pos = 0; 247 248 /* pre allocate dmamaps for RX list */ 249 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 250 error = bus_dmamap_create(sc->bfe_tag, 0, 251 &sc->bfe_rx_ring[i].bfe_map); 252 if (error) { 253 rx_pos = i; 254 device_printf(dev, "cannot create DMA map for RX\n"); 255 goto ring_fail; 256 } 257 } 258 rx_pos = BFE_RX_LIST_CNT; 259 260 /* pre allocate dmamaps for TX list */ 261 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 262 error = bus_dmamap_create(sc->bfe_tag, 0, 263 &sc->bfe_tx_ring[i].bfe_map); 264 if (error) { 265 tx_pos = i; 266 device_printf(dev, "cannot create DMA map for TX\n"); 267 goto ring_fail; 268 } 269 } 270 271 /* Alloc dma for rx ring */ 272 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 273 BUS_DMA_WAITOK | BUS_DMA_ZERO, 274 &sc->bfe_rx_map); 275 if (error) { 276 device_printf(dev, "cannot allocate DMA mem for RX\n"); 277 return(error); 278 } 279 280 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 281 sc->bfe_rx_list, sizeof(struct bfe_desc), 282 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK); 283 if (error) { 284 device_printf(dev, "cannot load DMA map for RX\n"); 285 return(error); 286 } 287 288 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 289 290 /* Alloc dma for tx ring */ 291 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 292 BUS_DMA_WAITOK | BUS_DMA_ZERO, 293 &sc->bfe_tx_map); 294 if (error) { 295 device_printf(dev, "cannot allocate DMA mem for TX\n"); 296 return(error); 297 } 298 299 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 300 sc->bfe_tx_list, sizeof(struct bfe_desc), 301 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK); 302 if (error) { 303 device_printf(dev, "cannot load DMA map for TX\n"); 304 return(error); 305 } 306 307 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 308 309 return(0); 310 311 ring_fail: 312 for (i = 0; i < rx_pos; ++i) 313 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map); 314 for (i = 0; i < tx_pos; ++i) 315 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 316 317 bus_dma_tag_destroy(sc->bfe_tag); 318 sc->bfe_tag = NULL; 319 return error; 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp; 326 struct bfe_softc *sc; 327 int error = 0, rid; 328 329 sc = device_get_softc(dev); 330 331 sc->bfe_dev = dev; 332 callout_init(&sc->bfe_stat_timer); 333 334 /* 335 * Handle power management nonsense. 336 */ 337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 338 uint32_t membase, irq; 339 340 /* Save important PCI config data. */ 341 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 342 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 343 344 /* Reset the power state. */ 345 device_printf(dev, "chip is in D%d power mode" 346 " -- setting to D0\n", pci_get_powerstate(dev)); 347 348 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 349 350 /* Restore PCI config data. */ 351 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 352 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 353 } 354 355 /* 356 * Map control/status registers. 357 */ 358 pci_enable_busmaster(dev); 359 360 rid = BFE_PCI_MEMLO; 361 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 362 RF_ACTIVE); 363 if (sc->bfe_res == NULL) { 364 device_printf(dev, "couldn't map memory\n"); 365 return ENXIO; 366 } 367 368 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 369 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 370 371 /* Allocate interrupt */ 372 rid = 0; 373 374 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 375 RF_SHAREABLE | RF_ACTIVE); 376 if (sc->bfe_irq == NULL) { 377 device_printf(dev, "couldn't map interrupt\n"); 378 error = ENXIO; 379 goto fail; 380 } 381 382 error = bfe_dma_alloc(dev); 383 if (error != 0) { 384 device_printf(dev, "failed to allocate DMA resources\n"); 385 goto fail; 386 } 387 388 /* Set up ifnet structure */ 389 ifp = &sc->arpcom.ac_if; 390 ifp->if_softc = sc; 391 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 393 ifp->if_ioctl = bfe_ioctl; 394 ifp->if_start = bfe_start; 395 ifp->if_watchdog = bfe_watchdog; 396 ifp->if_init = bfe_init; 397 ifp->if_mtu = ETHERMTU; 398 ifp->if_baudrate = 100000000; 399 ifp->if_capabilities |= IFCAP_VLAN_MTU; 400 ifp->if_capenable |= IFCAP_VLAN_MTU; 401 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 402 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 403 ifq_set_ready(&ifp->if_snd); 404 405 bfe_get_config(sc); 406 407 /* Reset the chip and turn on the PHY */ 408 bfe_chip_reset(sc); 409 410 if (mii_phy_probe(dev, &sc->bfe_miibus, 411 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 412 device_printf(dev, "MII without any PHY!\n"); 413 error = ENXIO; 414 goto fail; 415 } 416 417 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 418 419 /* 420 * Hook interrupt last to avoid having to lock softc 421 */ 422 error = bus_setup_intr(dev, sc->bfe_irq, INTR_NETSAFE, 423 bfe_intr, sc, &sc->bfe_intrhand, 424 sc->arpcom.ac_if.if_serializer); 425 426 if (error) { 427 ether_ifdetach(ifp); 428 device_printf(dev, "couldn't set up irq\n"); 429 goto fail; 430 } 431 return 0; 432 fail: 433 bfe_detach(dev); 434 return(error); 435 } 436 437 static int 438 bfe_detach(device_t dev) 439 { 440 struct bfe_softc *sc = device_get_softc(dev); 441 struct ifnet *ifp = &sc->arpcom.ac_if; 442 443 if (device_is_attached(dev)) { 444 lwkt_serialize_enter(ifp->if_serializer); 445 bfe_stop(sc); 446 bfe_chip_reset(sc); 447 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 448 lwkt_serialize_exit(ifp->if_serializer); 449 450 ether_ifdetach(ifp); 451 } 452 if (sc->bfe_miibus != NULL) 453 device_delete_child(dev, sc->bfe_miibus); 454 bus_generic_detach(dev); 455 456 if (sc->bfe_irq != NULL) 457 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 458 459 if (sc->bfe_res != NULL) { 460 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 461 sc->bfe_res); 462 } 463 bfe_dma_free(sc); 464 465 return(0); 466 } 467 468 /* 469 * Stop all chip I/O so that the kernel's probe routines don't 470 * get confused by errant DMAs when rebooting. 471 */ 472 static void 473 bfe_shutdown(device_t dev) 474 { 475 struct bfe_softc *sc = device_get_softc(dev); 476 struct ifnet *ifp = &sc->arpcom.ac_if; 477 478 lwkt_serialize_enter(ifp->if_serializer); 479 bfe_stop(sc); 480 lwkt_serialize_exit(ifp->if_serializer); 481 } 482 483 static int 484 bfe_miibus_readreg(device_t dev, int phy, int reg) 485 { 486 struct bfe_softc *sc; 487 uint32_t ret; 488 489 sc = device_get_softc(dev); 490 if (phy != sc->bfe_phyaddr) 491 return(0); 492 bfe_readphy(sc, reg, &ret); 493 494 return(ret); 495 } 496 497 static int 498 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 499 { 500 struct bfe_softc *sc; 501 502 sc = device_get_softc(dev); 503 if (phy != sc->bfe_phyaddr) 504 return(0); 505 bfe_writephy(sc, reg, val); 506 507 return(0); 508 } 509 510 static void 511 bfe_miibus_statchg(device_t dev) 512 { 513 return; 514 } 515 516 static void 517 bfe_tx_ring_free(struct bfe_softc *sc) 518 { 519 int i; 520 521 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 522 bus_dmamap_unload(sc->bfe_tag, 523 sc->bfe_tx_ring[i].bfe_map); 524 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 525 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 526 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 527 } 528 } 529 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 530 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 531 } 532 533 static void 534 bfe_rx_ring_free(struct bfe_softc *sc) 535 { 536 int i; 537 538 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 539 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 540 bus_dmamap_unload(sc->bfe_tag, 541 sc->bfe_rx_ring[i].bfe_map); 542 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 543 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 544 } 545 } 546 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 547 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 548 } 549 550 static int 551 bfe_list_rx_init(struct bfe_softc *sc) 552 { 553 int i; 554 555 for (i = 0; i < BFE_RX_LIST_CNT; i++) 556 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 557 return(ENOBUFS); 558 559 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 560 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 561 562 sc->bfe_rx_cons = 0; 563 564 return(0); 565 } 566 567 static int 568 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 569 { 570 struct bfe_rxheader *rx_header; 571 struct bfe_desc *d; 572 struct bfe_data *r; 573 uint32_t ctrl; 574 575 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 576 return(EINVAL); 577 578 if (m == NULL) { 579 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 580 if (m == NULL) 581 return(ENOBUFS); 582 m->m_len = m->m_pkthdr.len = MCLBYTES; 583 } 584 else 585 m->m_data = m->m_ext.ext_buf; 586 587 rx_header = mtod(m, struct bfe_rxheader *); 588 rx_header->len = 0; 589 rx_header->flags = 0; 590 591 /* Map the mbuf into DMA */ 592 sc->bfe_rx_cnt = c; 593 d = &sc->bfe_rx_list[c]; 594 r = &sc->bfe_rx_ring[c]; 595 /* XXX error? */ 596 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 597 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 598 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 599 600 ctrl = ETHER_MAX_LEN + 32; 601 602 if(c == BFE_RX_LIST_CNT - 1) 603 ctrl |= BFE_DESC_EOT; 604 605 d->bfe_ctrl = ctrl; 606 r->bfe_mbuf = m; 607 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 608 return(0); 609 } 610 611 static void 612 bfe_get_config(struct bfe_softc *sc) 613 { 614 uint8_t eeprom[128]; 615 616 bfe_read_eeprom(sc, eeprom); 617 618 sc->arpcom.ac_enaddr[0] = eeprom[79]; 619 sc->arpcom.ac_enaddr[1] = eeprom[78]; 620 sc->arpcom.ac_enaddr[2] = eeprom[81]; 621 sc->arpcom.ac_enaddr[3] = eeprom[80]; 622 sc->arpcom.ac_enaddr[4] = eeprom[83]; 623 sc->arpcom.ac_enaddr[5] = eeprom[82]; 624 625 sc->bfe_phyaddr = eeprom[90] & 0x1f; 626 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 627 628 sc->bfe_core_unit = 0; 629 sc->bfe_dma_offset = BFE_PCI_DMA; 630 } 631 632 static void 633 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 634 { 635 uint32_t bar_orig, pci_rev, val; 636 637 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 638 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 639 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 640 641 val = CSR_READ_4(sc, BFE_SBINTVEC); 642 val |= cores; 643 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 644 645 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 646 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 647 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 648 649 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 650 } 651 652 static void 653 bfe_clear_stats(struct bfe_softc *sc) 654 { 655 u_long reg; 656 657 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 658 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 659 CSR_READ_4(sc, reg); 660 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 661 CSR_READ_4(sc, reg); 662 } 663 664 static int 665 bfe_resetphy(struct bfe_softc *sc) 666 { 667 uint32_t val; 668 669 bfe_writephy(sc, 0, BMCR_RESET); 670 DELAY(100); 671 bfe_readphy(sc, 0, &val); 672 if (val & BMCR_RESET) { 673 if_printf(&sc->arpcom.ac_if, 674 "PHY Reset would not complete.\n"); 675 return(ENXIO); 676 } 677 return(0); 678 } 679 680 static void 681 bfe_chip_halt(struct bfe_softc *sc) 682 { 683 /* disable interrupts - not that it actually does..*/ 684 CSR_WRITE_4(sc, BFE_IMASK, 0); 685 CSR_READ_4(sc, BFE_IMASK); 686 687 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 688 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 689 690 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 691 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 692 DELAY(10); 693 } 694 695 static void 696 bfe_chip_reset(struct bfe_softc *sc) 697 { 698 uint32_t val; 699 700 /* Set the interrupt vector for the enet core */ 701 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 702 703 /* is core up? */ 704 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 705 if (val == BFE_CLOCK) { 706 /* It is, so shut it down */ 707 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 708 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 709 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 711 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 712 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 713 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 714 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 715 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 716 } 717 718 bfe_core_reset(sc); 719 bfe_clear_stats(sc); 720 721 /* 722 * We want the phy registers to be accessible even when 723 * the driver is "downed" so initialize MDC preamble, frequency, 724 * and whether internal or external phy here. 725 */ 726 727 /* 4402 has 62.5Mhz SB clock and internal phy */ 728 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 729 730 /* Internal or external PHY? */ 731 val = CSR_READ_4(sc, BFE_DEVCTRL); 732 if (!(val & BFE_IPP)) 733 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 734 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 735 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 736 DELAY(100); 737 } 738 739 /* Enable CRC32 generation and set proper LED modes */ 740 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 741 742 /* Reset or clear powerdown control bit */ 743 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 744 745 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 746 BFE_LAZY_FC_MASK)); 747 748 /* 749 * We don't want lazy interrupts, so just send them at the end of a 750 * frame, please 751 */ 752 BFE_OR(sc, BFE_RCV_LAZY, 0); 753 754 /* Set max lengths, accounting for VLAN tags */ 755 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 756 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 757 758 /* Set watermark XXX - magic */ 759 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 760 761 /* 762 * Initialise DMA channels - not forgetting dma addresses need to be 763 * added to BFE_PCI_DMA 764 */ 765 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 766 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 767 768 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 769 BFE_RX_CTRL_ENABLE); 770 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 771 772 bfe_resetphy(sc); 773 bfe_setupphy(sc); 774 } 775 776 static void 777 bfe_core_disable(struct bfe_softc *sc) 778 { 779 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 780 return; 781 782 /* 783 * Set reject, wait for it set, then wait for the core to stop being busy 784 * Then set reset and reject and enable the clocks 785 */ 786 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 787 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 788 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 789 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 790 BFE_RESET)); 791 CSR_READ_4(sc, BFE_SBTMSLOW); 792 DELAY(10); 793 /* Leave reset and reject set */ 794 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 795 DELAY(10); 796 } 797 798 static void 799 bfe_core_reset(struct bfe_softc *sc) 800 { 801 uint32_t val; 802 803 /* Disable the core */ 804 bfe_core_disable(sc); 805 806 /* and bring it back up */ 807 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 808 CSR_READ_4(sc, BFE_SBTMSLOW); 809 DELAY(10); 810 811 /* Chip bug, clear SERR, IB and TO if they are set. */ 812 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 813 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 814 val = CSR_READ_4(sc, BFE_SBIMSTATE); 815 if (val & (BFE_IBE | BFE_TO)) 816 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 817 818 /* Clear reset and allow it to move through the core */ 819 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 820 CSR_READ_4(sc, BFE_SBTMSLOW); 821 DELAY(10); 822 823 /* Leave the clock set */ 824 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 825 CSR_READ_4(sc, BFE_SBTMSLOW); 826 DELAY(10); 827 } 828 829 static void 830 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 831 { 832 uint32_t val; 833 834 val = ((uint32_t) data[2]) << 24; 835 val |= ((uint32_t) data[3]) << 16; 836 val |= ((uint32_t) data[4]) << 8; 837 val |= ((uint32_t) data[5]); 838 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 839 val = (BFE_CAM_HI_VALID | 840 (((uint32_t) data[0]) << 8) | 841 (((uint32_t) data[1]))); 842 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 843 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 844 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 845 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 846 } 847 848 static void 849 bfe_set_rx_mode(struct bfe_softc *sc) 850 { 851 struct ifnet *ifp = &sc->arpcom.ac_if; 852 struct ifmultiaddr *ifma; 853 uint32_t val; 854 int i = 0; 855 856 val = CSR_READ_4(sc, BFE_RXCONF); 857 858 if (ifp->if_flags & IFF_PROMISC) 859 val |= BFE_RXCONF_PROMISC; 860 else 861 val &= ~BFE_RXCONF_PROMISC; 862 863 if (ifp->if_flags & IFF_BROADCAST) 864 val &= ~BFE_RXCONF_DBCAST; 865 else 866 val |= BFE_RXCONF_DBCAST; 867 868 869 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 870 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 871 872 if (ifp->if_flags & IFF_ALLMULTI) { 873 val |= BFE_RXCONF_ALLMULTI; 874 } else { 875 val &= ~BFE_RXCONF_ALLMULTI; 876 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 877 if (ifma->ifma_addr->sa_family != AF_LINK) 878 continue; 879 bfe_cam_write(sc, 880 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 881 } 882 } 883 884 CSR_WRITE_4(sc, BFE_RXCONF, val); 885 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 886 } 887 888 static void 889 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 890 { 891 uint32_t *ptr; 892 893 ptr = arg; 894 *ptr = segs->ds_addr; 895 } 896 897 static void 898 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 899 { 900 struct bfe_desc *d; 901 902 d = arg; 903 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 904 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 905 } 906 907 static void 908 bfe_dma_free(struct bfe_softc *sc) 909 { 910 if (sc->bfe_tx_tag != NULL) { 911 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 912 if (sc->bfe_tx_list != NULL) { 913 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 914 sc->bfe_tx_map); 915 sc->bfe_tx_list = NULL; 916 } 917 bus_dma_tag_destroy(sc->bfe_tx_tag); 918 sc->bfe_tx_tag = NULL; 919 } 920 921 if (sc->bfe_rx_tag != NULL) { 922 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 923 if (sc->bfe_rx_list != NULL) { 924 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 925 sc->bfe_rx_map); 926 sc->bfe_rx_list = NULL; 927 } 928 bus_dma_tag_destroy(sc->bfe_rx_tag); 929 sc->bfe_rx_tag = NULL; 930 } 931 932 if (sc->bfe_tag != NULL) { 933 int i; 934 935 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 936 bus_dmamap_destroy(sc->bfe_tag, 937 sc->bfe_tx_ring[i].bfe_map); 938 } 939 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 940 bus_dmamap_destroy(sc->bfe_tag, 941 sc->bfe_rx_ring[i].bfe_map); 942 } 943 944 bus_dma_tag_destroy(sc->bfe_tag); 945 sc->bfe_tag = NULL; 946 } 947 948 if (sc->bfe_parent_tag != NULL) { 949 bus_dma_tag_destroy(sc->bfe_parent_tag); 950 sc->bfe_parent_tag = NULL; 951 } 952 } 953 954 static void 955 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 956 { 957 long i; 958 uint16_t *ptr = (uint16_t *)data; 959 960 for (i = 0; i < 128; i += 2) 961 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 962 } 963 964 static int 965 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 966 u_long timeout, const int clear) 967 { 968 u_long i; 969 970 for (i = 0; i < timeout; i++) { 971 uint32_t val = CSR_READ_4(sc, reg); 972 973 if (clear && !(val & bit)) 974 break; 975 if (!clear && (val & bit)) 976 break; 977 DELAY(10); 978 } 979 if (i == timeout) { 980 if_printf(&sc->arpcom.ac_if, 981 "BUG! Timeout waiting for bit %08x of register " 982 "%x to %s.\n", bit, reg, 983 (clear ? "clear" : "set")); 984 return -1; 985 } 986 return 0; 987 } 988 989 static int 990 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 991 { 992 int err; 993 994 /* Clear MII ISR */ 995 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 996 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 997 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 998 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 999 (reg << BFE_MDIO_RA_SHIFT) | 1000 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1001 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1002 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1003 return(err); 1004 } 1005 1006 static int 1007 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1008 { 1009 int status; 1010 1011 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1012 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1013 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1014 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1015 (reg << BFE_MDIO_RA_SHIFT) | 1016 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1017 (val & BFE_MDIO_DATA_DATA))); 1018 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1019 1020 return status; 1021 } 1022 1023 /* 1024 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1025 * twice 1026 */ 1027 static int 1028 bfe_setupphy(struct bfe_softc *sc) 1029 { 1030 uint32_t val; 1031 1032 /* Enable activity LED */ 1033 bfe_readphy(sc, 26, &val); 1034 bfe_writephy(sc, 26, val & 0x7fff); 1035 bfe_readphy(sc, 26, &val); 1036 1037 /* Enable traffic meter LED mode */ 1038 bfe_readphy(sc, 27, &val); 1039 bfe_writephy(sc, 27, val | (1 << 6)); 1040 1041 return(0); 1042 } 1043 1044 static void 1045 bfe_stats_update(struct bfe_softc *sc) 1046 { 1047 u_long reg; 1048 uint32_t *val; 1049 1050 val = &sc->bfe_hwstats.tx_good_octets; 1051 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1052 *val++ += CSR_READ_4(sc, reg); 1053 val = &sc->bfe_hwstats.rx_good_octets; 1054 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1055 *val++ += CSR_READ_4(sc, reg); 1056 } 1057 1058 static void 1059 bfe_txeof(struct bfe_softc *sc) 1060 { 1061 struct ifnet *ifp = &sc->arpcom.ac_if; 1062 uint32_t i, chipidx; 1063 1064 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1065 chipidx /= sizeof(struct bfe_desc); 1066 1067 i = sc->bfe_tx_cons; 1068 /* Go through the mbufs and free those that have been transmitted */ 1069 while (i != chipidx) { 1070 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1071 1072 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1073 if (r->bfe_mbuf != NULL) { 1074 ifp->if_opackets++; 1075 m_freem(r->bfe_mbuf); 1076 r->bfe_mbuf = NULL; 1077 } 1078 sc->bfe_tx_cnt--; 1079 BFE_INC(i, BFE_TX_LIST_CNT); 1080 } 1081 1082 if (i != sc->bfe_tx_cons) { 1083 /* we freed up some mbufs */ 1084 sc->bfe_tx_cons = i; 1085 ifp->if_flags &= ~IFF_OACTIVE; 1086 } 1087 if (sc->bfe_tx_cnt == 0) 1088 ifp->if_timer = 0; 1089 else 1090 ifp->if_timer = 5; 1091 } 1092 1093 /* Pass a received packet up the stack */ 1094 static void 1095 bfe_rxeof(struct bfe_softc *sc) 1096 { 1097 struct ifnet *ifp = &sc->arpcom.ac_if; 1098 struct mbuf *m; 1099 struct bfe_rxheader *rxheader; 1100 struct bfe_data *r; 1101 uint32_t cons, status, current, len, flags; 1102 1103 cons = sc->bfe_rx_cons; 1104 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1105 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1106 1107 while (current != cons) { 1108 r = &sc->bfe_rx_ring[cons]; 1109 m = r->bfe_mbuf; 1110 rxheader = mtod(m, struct bfe_rxheader*); 1111 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1112 len = rxheader->len; 1113 r->bfe_mbuf = NULL; 1114 1115 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1116 flags = rxheader->flags; 1117 1118 len -= ETHER_CRC_LEN; 1119 1120 /* flag an error and try again */ 1121 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1122 ifp->if_ierrors++; 1123 if (flags & BFE_RX_FLAG_SERR) 1124 ifp->if_collisions++; 1125 bfe_list_newbuf(sc, cons, m); 1126 BFE_INC(cons, BFE_RX_LIST_CNT); 1127 continue; 1128 } 1129 1130 /* Go past the rx header */ 1131 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1132 bfe_list_newbuf(sc, cons, m); 1133 BFE_INC(cons, BFE_RX_LIST_CNT); 1134 ifp->if_ierrors++; 1135 continue; 1136 } 1137 1138 m_adj(m, BFE_RX_OFFSET); 1139 m->m_len = m->m_pkthdr.len = len; 1140 1141 ifp->if_ipackets++; 1142 m->m_pkthdr.rcvif = ifp; 1143 1144 ifp->if_input(ifp, m); 1145 BFE_INC(cons, BFE_RX_LIST_CNT); 1146 } 1147 sc->bfe_rx_cons = cons; 1148 } 1149 1150 static void 1151 bfe_intr(void *xsc) 1152 { 1153 struct bfe_softc *sc = xsc; 1154 struct ifnet *ifp = &sc->arpcom.ac_if; 1155 uint32_t istat, imask, flag; 1156 1157 istat = CSR_READ_4(sc, BFE_ISTAT); 1158 imask = CSR_READ_4(sc, BFE_IMASK); 1159 1160 /* 1161 * Defer unsolicited interrupts - This is necessary because setting the 1162 * chips interrupt mask register to 0 doesn't actually stop the 1163 * interrupts 1164 */ 1165 istat &= imask; 1166 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1167 CSR_READ_4(sc, BFE_ISTAT); 1168 1169 /* not expecting this interrupt, disregard it */ 1170 if (istat == 0) { 1171 return; 1172 } 1173 1174 if (istat & BFE_ISTAT_ERRORS) { 1175 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1176 if (flag & BFE_STAT_EMASK) 1177 ifp->if_oerrors++; 1178 1179 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1180 if (flag & BFE_RX_FLAG_ERRORS) 1181 ifp->if_ierrors++; 1182 1183 ifp->if_flags &= ~IFF_RUNNING; 1184 bfe_init(sc); 1185 } 1186 1187 /* A packet was received */ 1188 if (istat & BFE_ISTAT_RX) 1189 bfe_rxeof(sc); 1190 1191 /* A packet was sent */ 1192 if (istat & BFE_ISTAT_TX) 1193 bfe_txeof(sc); 1194 1195 /* We have packets pending, fire them out */ 1196 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1197 bfe_start(ifp); 1198 } 1199 1200 static int 1201 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1202 { 1203 struct bfe_desc *d = NULL; 1204 struct bfe_data *r = NULL; 1205 struct mbuf *m; 1206 uint32_t frag, cur, cnt = 0; 1207 int error, chainlen = 0; 1208 1209 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt)); 1210 1211 /* 1212 * Count the number of frags in this chain to see if 1213 * we need to m_defrag. Since the descriptor list is shared 1214 * by all packets, we'll m_defrag long chains so that they 1215 * do not use up the entire list, even if they would fit. 1216 */ 1217 for (m = *m_head; m != NULL; m = m->m_next) 1218 chainlen++; 1219 1220 if (chainlen > (BFE_TX_LIST_CNT / 4) || 1221 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) { 1222 m = m_defrag(*m_head, MB_DONTWAIT); 1223 if (m == NULL) { 1224 m_freem(*m_head); 1225 return (ENOBUFS); 1226 } 1227 *m_head = m; 1228 } 1229 1230 /* 1231 * Start packing the mbufs in this chain into 1232 * the fragment pointers. Stop when we run out 1233 * of fragments or hit the end of the mbuf chain. 1234 */ 1235 cur = frag = *txidx; 1236 cnt = 0; 1237 1238 for (m = *m_head; m != NULL; m = m->m_next) { 1239 if (m->m_len != 0) { 1240 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt)); 1241 1242 d = &sc->bfe_tx_list[cur]; 1243 r = &sc->bfe_tx_ring[cur]; 1244 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1245 /* always intterupt on completion */ 1246 d->bfe_ctrl |= BFE_DESC_IOC; 1247 if (cnt == 0) { 1248 /* Set start of frame */ 1249 d->bfe_ctrl |= BFE_DESC_SOF; 1250 } 1251 if (cur == BFE_TX_LIST_CNT - 1) { 1252 /* 1253 * Tell the chip to wrap to the start of the 1254 * descriptor list 1255 */ 1256 d->bfe_ctrl |= BFE_DESC_EOT; 1257 } 1258 1259 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, 1260 mtod(m, void *), m->m_len, 1261 bfe_dma_map_desc, d, 1262 BUS_DMA_NOWAIT); 1263 if (error) { 1264 /* XXX This should be a fatal error. */ 1265 if_printf(&sc->arpcom.ac_if, 1266 "%s bus_dmamap_load failed: %d", 1267 __func__, error); 1268 m_freem(*m_head); 1269 return (ENOBUFS); 1270 } 1271 1272 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1273 BUS_DMASYNC_PREWRITE); 1274 1275 frag = cur; 1276 BFE_INC(cur, BFE_TX_LIST_CNT); 1277 cnt++; 1278 } 1279 } 1280 1281 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1282 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1283 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1284 1285 *txidx = cur; 1286 sc->bfe_tx_cnt += cnt; 1287 return(0); 1288 } 1289 1290 /* 1291 * Set up to transmit a packet 1292 */ 1293 static void 1294 bfe_start(struct ifnet *ifp) 1295 { 1296 struct bfe_softc *sc = ifp->if_softc; 1297 struct mbuf *m_head = NULL; 1298 int idx, need_trans; 1299 1300 /* 1301 * Not much point trying to send if the link is down 1302 * or we have nothing to send. 1303 */ 1304 if (!sc->bfe_link) 1305 return; 1306 1307 if (ifp->if_flags & IFF_OACTIVE) 1308 return; 1309 1310 idx = sc->bfe_tx_prod; 1311 1312 need_trans = 0; 1313 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1314 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) { 1315 ifp->if_flags |= IFF_OACTIVE; 1316 break; 1317 } 1318 1319 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1320 if (m_head == NULL) 1321 break; 1322 1323 /* 1324 * Pack the data into the tx ring. If we don't have 1325 * enough room, let the chip drain the ring. 1326 */ 1327 if (bfe_encap(sc, &m_head, &idx)) { 1328 ifp->if_flags |= IFF_OACTIVE; 1329 break; 1330 } 1331 need_trans = 1; 1332 1333 /* 1334 * If there's a BPF listener, bounce a copy of this frame 1335 * to him. 1336 */ 1337 BPF_MTAP(ifp, m_head); 1338 } 1339 1340 if (!need_trans) 1341 return; 1342 1343 sc->bfe_tx_prod = idx; 1344 /* Transmit - twice due to apparent hardware bug */ 1345 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1346 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1347 1348 /* 1349 * Set a timeout in case the chip goes out to lunch. 1350 */ 1351 ifp->if_timer = 5; 1352 } 1353 1354 static void 1355 bfe_init(void *xsc) 1356 { 1357 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1358 struct ifnet *ifp = &sc->arpcom.ac_if; 1359 1360 if (ifp->if_flags & IFF_RUNNING) 1361 return; 1362 1363 bfe_stop(sc); 1364 bfe_chip_reset(sc); 1365 1366 if (bfe_list_rx_init(sc) == ENOBUFS) { 1367 if_printf(ifp, "bfe_init failed. " 1368 " Not enough memory for list buffers\n"); 1369 bfe_stop(sc); 1370 return; 1371 } 1372 1373 bfe_set_rx_mode(sc); 1374 1375 /* Enable the chip and core */ 1376 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1377 /* Enable interrupts */ 1378 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1379 1380 bfe_ifmedia_upd(ifp); 1381 ifp->if_flags |= IFF_RUNNING; 1382 ifp->if_flags &= ~IFF_OACTIVE; 1383 1384 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1385 } 1386 1387 /* 1388 * Set media options. 1389 */ 1390 static int 1391 bfe_ifmedia_upd(struct ifnet *ifp) 1392 { 1393 struct bfe_softc *sc = ifp->if_softc; 1394 struct mii_data *mii; 1395 1396 mii = device_get_softc(sc->bfe_miibus); 1397 sc->bfe_link = 0; 1398 if (mii->mii_instance) { 1399 struct mii_softc *miisc; 1400 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1401 miisc = LIST_NEXT(miisc, mii_list)) 1402 mii_phy_reset(miisc); 1403 } 1404 mii_mediachg(mii); 1405 1406 bfe_setupphy(sc); 1407 1408 return(0); 1409 } 1410 1411 /* 1412 * Report current media status. 1413 */ 1414 static void 1415 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1416 { 1417 struct bfe_softc *sc = ifp->if_softc; 1418 struct mii_data *mii; 1419 1420 mii = device_get_softc(sc->bfe_miibus); 1421 mii_pollstat(mii); 1422 ifmr->ifm_active = mii->mii_media_active; 1423 ifmr->ifm_status = mii->mii_media_status; 1424 } 1425 1426 static int 1427 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1428 { 1429 struct bfe_softc *sc = ifp->if_softc; 1430 struct ifreq *ifr = (struct ifreq *) data; 1431 struct mii_data *mii; 1432 int error = 0; 1433 1434 switch (command) { 1435 case SIOCSIFFLAGS: 1436 if (ifp->if_flags & IFF_UP) 1437 if (ifp->if_flags & IFF_RUNNING) 1438 bfe_set_rx_mode(sc); 1439 else 1440 bfe_init(sc); 1441 else if (ifp->if_flags & IFF_RUNNING) 1442 bfe_stop(sc); 1443 break; 1444 case SIOCADDMULTI: 1445 case SIOCDELMULTI: 1446 if (ifp->if_flags & IFF_RUNNING) 1447 bfe_set_rx_mode(sc); 1448 break; 1449 case SIOCGIFMEDIA: 1450 case SIOCSIFMEDIA: 1451 mii = device_get_softc(sc->bfe_miibus); 1452 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1453 command); 1454 break; 1455 default: 1456 error = ether_ioctl(ifp, command, data); 1457 break; 1458 } 1459 return error; 1460 } 1461 1462 static void 1463 bfe_watchdog(struct ifnet *ifp) 1464 { 1465 struct bfe_softc *sc = ifp->if_softc; 1466 1467 if_printf(ifp, "watchdog timeout -- resetting\n"); 1468 1469 ifp->if_flags &= ~IFF_RUNNING; 1470 bfe_init(sc); 1471 1472 ifp->if_oerrors++; 1473 } 1474 1475 static void 1476 bfe_tick(void *xsc) 1477 { 1478 struct bfe_softc *sc = xsc; 1479 struct mii_data *mii; 1480 struct ifnet *ifp = &sc->arpcom.ac_if; 1481 1482 mii = device_get_softc(sc->bfe_miibus); 1483 1484 lwkt_serialize_enter(ifp->if_serializer); 1485 1486 bfe_stats_update(sc); 1487 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1488 1489 if (sc->bfe_link == NULL) { 1490 mii_tick(mii); 1491 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1492 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1493 sc->bfe_link++; 1494 } 1495 if (!sc->bfe_link) 1496 sc->bfe_link++; 1497 } 1498 lwkt_serialize_exit(ifp->if_serializer); 1499 } 1500 1501 /* 1502 * Stop the adapter and free any mbufs allocated to the 1503 * RX and TX lists. 1504 */ 1505 static void 1506 bfe_stop(struct bfe_softc *sc) 1507 { 1508 struct ifnet *ifp = &sc->arpcom.ac_if; 1509 1510 callout_stop(&sc->bfe_stat_timer); 1511 1512 bfe_chip_halt(sc); 1513 bfe_tx_ring_free(sc); 1514 bfe_rx_ring_free(sc); 1515 1516 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1517 } 1518