1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 #include <sys/interrupt.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/rman.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 54 #include <net/bpf.h> 55 56 #include <net/if_types.h> 57 #include <net/vlan/if_vlan_var.h> 58 59 #include <netinet/in_systm.h> 60 #include <netinet/in.h> 61 #include <netinet/ip.h> 62 63 #include <bus/pci/pcireg.h> 64 #include <bus/pci/pcivar.h> 65 #include <bus/pci/pcidevs.h> 66 67 #include <dev/netif/mii_layer/mii.h> 68 #include <dev/netif/mii_layer/miivar.h> 69 70 #include <dev/netif/bfe/if_bfereg.h> 71 72 MODULE_DEPEND(bfe, pci, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "controller miibus0" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402, 86 "Broadcom BCM4402 Fast Ethernet" }, 87 { 0, 0, NULL } 88 }; 89 90 static int bfe_probe(device_t); 91 static int bfe_attach(device_t); 92 static int bfe_detach(device_t); 93 static void bfe_intr(void *); 94 static void bfe_start(struct ifnet *); 95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 96 static void bfe_init(void *); 97 static void bfe_stop(struct bfe_softc *); 98 static void bfe_watchdog(struct ifnet *); 99 static void bfe_shutdown(device_t); 100 static void bfe_tick(void *); 101 static void bfe_txeof(struct bfe_softc *); 102 static void bfe_rxeof(struct bfe_softc *); 103 static void bfe_set_rx_mode(struct bfe_softc *); 104 static int bfe_list_rx_init(struct bfe_softc *); 105 static int bfe_newbuf(struct bfe_softc *, int, int); 106 static void bfe_setup_rxdesc(struct bfe_softc *, int); 107 static void bfe_rx_ring_free(struct bfe_softc *); 108 109 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 110 static int bfe_ifmedia_upd(struct ifnet *); 111 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg(device_t, int, int); 113 static int bfe_miibus_writereg(device_t, int, int, int); 114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 115 u_long, const int); 116 static void bfe_get_config(struct bfe_softc *sc); 117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 118 static void bfe_stats_update(struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 122 static int bfe_resetphy(struct bfe_softc *); 123 static int bfe_setupphy(struct bfe_softc *); 124 static void bfe_chip_reset(struct bfe_softc *); 125 static void bfe_chip_halt(struct bfe_softc *); 126 static void bfe_core_reset(struct bfe_softc *); 127 static void bfe_core_disable(struct bfe_softc *); 128 static int bfe_dma_alloc(device_t); 129 static void bfe_dma_free(struct bfe_softc *); 130 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 131 132 static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 139 /* bus interface */ 140 DEVMETHOD(bus_print_child, bus_generic_print_child), 141 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142 143 /* MII interface */ 144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146 147 { 0, 0 } 148 }; 149 150 static driver_t bfe_driver = { 151 "bfe", 152 bfe_methods, 153 sizeof(struct bfe_softc) 154 }; 155 156 static devclass_t bfe_devclass; 157 158 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, NULL, NULL); 159 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, NULL, NULL); 160 161 /* 162 * Probe for a Broadcom 4401 chip. 163 */ 164 static int 165 bfe_probe(device_t dev) 166 { 167 struct bfe_type *t; 168 uint16_t vendor, product; 169 170 vendor = pci_get_vendor(dev); 171 product = pci_get_device(dev); 172 173 for (t = bfe_devs; t->bfe_name != NULL; t++) { 174 if (vendor == t->bfe_vid && product == t->bfe_did) { 175 device_set_desc(dev, t->bfe_name); 176 return(0); 177 } 178 } 179 180 return(ENXIO); 181 } 182 183 static int 184 bfe_dma_alloc(device_t dev) 185 { 186 struct bfe_softc *sc = device_get_softc(dev); 187 bus_dmamem_t dmem; 188 int error, i, tx_pos = 0, rx_pos = 0; 189 190 /* 191 * Parent tag. Apparently the chip cannot handle any DMA address 192 * greater than BFE_BUS_SPACE_MAXADDR (1GB). 193 */ 194 error = bus_dma_tag_create(NULL, /* parent */ 195 1, 0, /* alignment, boundary */ 196 BFE_BUS_SPACE_MAXADDR, /* lowaddr */ 197 BUS_SPACE_MAXADDR, /* highaddr */ 198 NULL, NULL, /* filter, filterarg */ 199 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 200 0, /* num of segments */ 201 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 202 0, /* flags */ 203 &sc->bfe_parent_tag); 204 if (error) { 205 device_printf(dev, "could not allocate parent dma tag\n"); 206 return(error); 207 } 208 209 /* Allocate TX ring */ 210 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0, 211 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 212 BFE_TX_LIST_SIZE, 213 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 214 if (error) { 215 device_printf(dev, "could not allocate TX list\n"); 216 return(error); 217 } 218 sc->bfe_tx_tag = dmem.dmem_tag; 219 sc->bfe_tx_map = dmem.dmem_map; 220 sc->bfe_tx_list = dmem.dmem_addr; 221 sc->bfe_tx_dma = dmem.dmem_busaddr; 222 223 /* Allocate RX ring */ 224 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0, 225 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 226 BFE_RX_LIST_SIZE, 227 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 228 if (error) { 229 device_printf(dev, "could not allocate RX list\n"); 230 return(error); 231 } 232 sc->bfe_rx_tag = dmem.dmem_tag; 233 sc->bfe_rx_map = dmem.dmem_map; 234 sc->bfe_rx_list = dmem.dmem_addr; 235 sc->bfe_rx_dma = dmem.dmem_busaddr; 236 237 /* Tag for RX mbufs */ 238 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0, 239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 240 NULL, NULL, 241 MCLBYTES, 1, MCLBYTES, 242 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 243 &sc->bfe_rxbuf_tag); 244 if (error) { 245 device_printf(dev, "could not allocate dma tag for RX mbufs\n"); 246 return(error); 247 } 248 249 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK, 250 &sc->bfe_rx_tmpmap); 251 if (error) { 252 device_printf(dev, "could not create RX mbuf tmp map\n"); 253 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 254 sc->bfe_rxbuf_tag = NULL; 255 return error; 256 } 257 258 /* Allocate dma maps for RX list */ 259 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 260 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK, 261 &sc->bfe_rx_ring[i].bfe_map); 262 if (error) { 263 rx_pos = i; 264 device_printf(dev, "cannot create DMA map for RX\n"); 265 goto ring_fail; 266 } 267 } 268 rx_pos = BFE_RX_LIST_CNT; 269 270 /* Tag for TX mbufs */ 271 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0, 272 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 273 NULL, NULL, 274 MCLBYTES, BFE_MAXSEGS, MCLBYTES, 275 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 276 &sc->bfe_txbuf_tag); 277 if (error) { 278 device_printf(dev, "could not allocate dma tag for TX mbufs\n"); 279 return(error); 280 } 281 282 /* Allocate dmamaps for TX list */ 283 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 284 error = bus_dmamap_create(sc->bfe_txbuf_tag, BUS_DMA_WAITOK, 285 &sc->bfe_tx_ring[i].bfe_map); 286 if (error) { 287 tx_pos = i; 288 device_printf(dev, "cannot create DMA map for TX\n"); 289 goto ring_fail; 290 } 291 } 292 293 return(0); 294 295 ring_fail: 296 if (sc->bfe_rxbuf_tag != NULL) { 297 for (i = 0; i < rx_pos; ++i) { 298 bus_dmamap_destroy(sc->bfe_rxbuf_tag, 299 sc->bfe_rx_ring[i].bfe_map); 300 } 301 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap); 302 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 303 sc->bfe_rxbuf_tag = NULL; 304 } 305 306 if (sc->bfe_txbuf_tag != NULL) { 307 for (i = 0; i < tx_pos; ++i) { 308 bus_dmamap_destroy(sc->bfe_txbuf_tag, 309 sc->bfe_tx_ring[i].bfe_map); 310 } 311 bus_dma_tag_destroy(sc->bfe_txbuf_tag); 312 sc->bfe_txbuf_tag = NULL; 313 } 314 return error; 315 } 316 317 static int 318 bfe_attach(device_t dev) 319 { 320 struct ifnet *ifp; 321 struct bfe_softc *sc; 322 int error = 0, rid; 323 324 sc = device_get_softc(dev); 325 326 sc->bfe_dev = dev; 327 callout_init(&sc->bfe_stat_timer); 328 329 #ifndef BURN_BRIDGES 330 /* 331 * Handle power management nonsense. 332 */ 333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 334 uint32_t membase, irq; 335 336 /* Save important PCI config data. */ 337 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 338 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 339 340 /* Reset the power state. */ 341 device_printf(dev, "chip is in D%d power mode" 342 " -- setting to D0\n", pci_get_powerstate(dev)); 343 344 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 345 346 /* Restore PCI config data. */ 347 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 348 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 349 } 350 #endif /* !BURN_BRIDGE */ 351 352 /* 353 * Map control/status registers. 354 */ 355 pci_enable_busmaster(dev); 356 357 rid = BFE_PCI_MEMLO; 358 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 359 RF_ACTIVE); 360 if (sc->bfe_res == NULL) { 361 device_printf(dev, "couldn't map memory\n"); 362 return ENXIO; 363 } 364 365 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 366 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 367 368 /* Allocate interrupt */ 369 rid = 0; 370 371 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 372 RF_SHAREABLE | RF_ACTIVE); 373 if (sc->bfe_irq == NULL) { 374 device_printf(dev, "couldn't map interrupt\n"); 375 error = ENXIO; 376 goto fail; 377 } 378 379 error = bfe_dma_alloc(dev); 380 if (error != 0) { 381 device_printf(dev, "failed to allocate DMA resources\n"); 382 goto fail; 383 } 384 385 /* Set up ifnet structure */ 386 ifp = &sc->arpcom.ac_if; 387 ifp->if_softc = sc; 388 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 389 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 390 ifp->if_ioctl = bfe_ioctl; 391 ifp->if_start = bfe_start; 392 ifp->if_watchdog = bfe_watchdog; 393 ifp->if_init = bfe_init; 394 ifp->if_mtu = ETHERMTU; 395 ifp->if_baudrate = 100000000; 396 ifp->if_capabilities |= IFCAP_VLAN_MTU; 397 ifp->if_capenable |= IFCAP_VLAN_MTU; 398 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 399 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 400 ifq_set_ready(&ifp->if_snd); 401 402 bfe_get_config(sc); 403 404 /* Reset the chip and turn on the PHY */ 405 bfe_chip_reset(sc); 406 407 if (mii_phy_probe(dev, &sc->bfe_miibus, 408 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 409 device_printf(dev, "MII without any PHY!\n"); 410 error = ENXIO; 411 goto fail; 412 } 413 414 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 415 416 /* 417 * Hook interrupt last to avoid having to lock softc 418 */ 419 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE, 420 bfe_intr, sc, &sc->bfe_intrhand, 421 sc->arpcom.ac_if.if_serializer); 422 423 if (error) { 424 ether_ifdetach(ifp); 425 device_printf(dev, "couldn't set up irq\n"); 426 goto fail; 427 } 428 429 ifp->if_cpuid = rman_get_cpuid(sc->bfe_irq); 430 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 431 return 0; 432 fail: 433 bfe_detach(dev); 434 return(error); 435 } 436 437 static int 438 bfe_detach(device_t dev) 439 { 440 struct bfe_softc *sc = device_get_softc(dev); 441 struct ifnet *ifp = &sc->arpcom.ac_if; 442 443 if (device_is_attached(dev)) { 444 lwkt_serialize_enter(ifp->if_serializer); 445 bfe_stop(sc); 446 bfe_chip_reset(sc); 447 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 448 lwkt_serialize_exit(ifp->if_serializer); 449 450 ether_ifdetach(ifp); 451 } 452 if (sc->bfe_miibus != NULL) 453 device_delete_child(dev, sc->bfe_miibus); 454 bus_generic_detach(dev); 455 456 if (sc->bfe_irq != NULL) 457 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 458 459 if (sc->bfe_res != NULL) { 460 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 461 sc->bfe_res); 462 } 463 bfe_dma_free(sc); 464 465 return(0); 466 } 467 468 /* 469 * Stop all chip I/O so that the kernel's probe routines don't 470 * get confused by errant DMAs when rebooting. 471 */ 472 static void 473 bfe_shutdown(device_t dev) 474 { 475 struct bfe_softc *sc = device_get_softc(dev); 476 struct ifnet *ifp = &sc->arpcom.ac_if; 477 478 lwkt_serialize_enter(ifp->if_serializer); 479 bfe_stop(sc); 480 lwkt_serialize_exit(ifp->if_serializer); 481 } 482 483 static int 484 bfe_miibus_readreg(device_t dev, int phy, int reg) 485 { 486 struct bfe_softc *sc; 487 uint32_t ret; 488 489 sc = device_get_softc(dev); 490 if (phy != sc->bfe_phyaddr) 491 return(0); 492 bfe_readphy(sc, reg, &ret); 493 494 return(ret); 495 } 496 497 static int 498 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 499 { 500 struct bfe_softc *sc; 501 502 sc = device_get_softc(dev); 503 if (phy != sc->bfe_phyaddr) 504 return(0); 505 bfe_writephy(sc, reg, val); 506 507 return(0); 508 } 509 510 static void 511 bfe_tx_ring_free(struct bfe_softc *sc) 512 { 513 int i; 514 515 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 516 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 517 bus_dmamap_unload(sc->bfe_txbuf_tag, 518 sc->bfe_tx_ring[i].bfe_map); 519 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 520 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 521 } 522 } 523 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 524 } 525 526 static void 527 bfe_rx_ring_free(struct bfe_softc *sc) 528 { 529 int i; 530 531 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 532 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 533 bus_dmamap_unload(sc->bfe_rxbuf_tag, 534 sc->bfe_rx_ring[i].bfe_map); 535 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 536 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 537 } 538 } 539 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 540 } 541 542 static int 543 bfe_list_rx_init(struct bfe_softc *sc) 544 { 545 int i, error; 546 547 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 548 error = bfe_newbuf(sc, i, 1); 549 if (error) 550 return(error); 551 } 552 553 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 554 555 sc->bfe_rx_cons = 0; 556 557 return(0); 558 } 559 560 static int 561 bfe_newbuf(struct bfe_softc *sc, int c, int init) 562 { 563 struct bfe_data *r; 564 bus_dmamap_t map; 565 bus_dma_segment_t seg; 566 struct mbuf *m; 567 int error, nsegs; 568 569 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 570 if (m == NULL) 571 return ENOBUFS; 572 m->m_len = m->m_pkthdr.len = MCLBYTES; 573 574 error = bus_dmamap_load_mbuf_segment(sc->bfe_rxbuf_tag, 575 sc->bfe_rx_tmpmap, m, 576 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 577 if (error) { 578 m_freem(m); 579 if (init) 580 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 581 return error; 582 } 583 584 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT); 585 r = &sc->bfe_rx_ring[c]; 586 587 if (r->bfe_mbuf != NULL) 588 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map); 589 590 map = r->bfe_map; 591 r->bfe_map = sc->bfe_rx_tmpmap; 592 sc->bfe_rx_tmpmap = map; 593 594 r->bfe_mbuf = m; 595 r->bfe_paddr = seg.ds_addr; 596 597 bfe_setup_rxdesc(sc, c); 598 return 0; 599 } 600 601 static void 602 bfe_setup_rxdesc(struct bfe_softc *sc, int c) 603 { 604 struct bfe_rxheader *rx_header; 605 struct mbuf *m; 606 struct bfe_desc *d; 607 struct bfe_data *r; 608 uint32_t ctrl; 609 610 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT); 611 r = &sc->bfe_rx_ring[c]; 612 d = &sc->bfe_rx_list[c]; 613 614 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0); 615 616 m = r->bfe_mbuf; 617 rx_header = mtod(m, struct bfe_rxheader *); 618 rx_header->len = 0; 619 rx_header->flags = 0; 620 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 621 622 ctrl = ETHER_MAX_LEN + 32; 623 if (c == BFE_RX_LIST_CNT - 1) 624 ctrl |= BFE_DESC_EOT; 625 626 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA; 627 d->bfe_ctrl = ctrl; 628 } 629 630 static void 631 bfe_get_config(struct bfe_softc *sc) 632 { 633 uint8_t eeprom[128]; 634 635 bfe_read_eeprom(sc, eeprom); 636 637 sc->arpcom.ac_enaddr[0] = eeprom[79]; 638 sc->arpcom.ac_enaddr[1] = eeprom[78]; 639 sc->arpcom.ac_enaddr[2] = eeprom[81]; 640 sc->arpcom.ac_enaddr[3] = eeprom[80]; 641 sc->arpcom.ac_enaddr[4] = eeprom[83]; 642 sc->arpcom.ac_enaddr[5] = eeprom[82]; 643 644 sc->bfe_phyaddr = eeprom[90] & 0x1f; 645 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 646 647 sc->bfe_core_unit = 0; 648 sc->bfe_dma_offset = BFE_PCI_DMA; 649 } 650 651 static void 652 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 653 { 654 uint32_t bar_orig, pci_rev, val; 655 656 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 657 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 658 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 659 660 val = CSR_READ_4(sc, BFE_SBINTVEC); 661 val |= cores; 662 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 663 664 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 665 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 666 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 667 668 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 669 } 670 671 static void 672 bfe_clear_stats(struct bfe_softc *sc) 673 { 674 u_long reg; 675 676 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 677 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 678 CSR_READ_4(sc, reg); 679 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 680 CSR_READ_4(sc, reg); 681 } 682 683 static int 684 bfe_resetphy(struct bfe_softc *sc) 685 { 686 uint32_t val; 687 688 bfe_writephy(sc, 0, BMCR_RESET); 689 DELAY(100); 690 bfe_readphy(sc, 0, &val); 691 if (val & BMCR_RESET) { 692 if_printf(&sc->arpcom.ac_if, 693 "PHY Reset would not complete.\n"); 694 return(ENXIO); 695 } 696 return(0); 697 } 698 699 static void 700 bfe_chip_halt(struct bfe_softc *sc) 701 { 702 /* disable interrupts - not that it actually does..*/ 703 CSR_WRITE_4(sc, BFE_IMASK, 0); 704 CSR_READ_4(sc, BFE_IMASK); 705 706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 708 709 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 711 DELAY(10); 712 } 713 714 static void 715 bfe_chip_reset(struct bfe_softc *sc) 716 { 717 uint32_t val; 718 719 /* Set the interrupt vector for the enet core */ 720 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 721 722 /* is core up? */ 723 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 724 if (val == BFE_CLOCK) { 725 /* It is, so shut it down */ 726 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 727 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 728 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 729 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 730 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 731 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 732 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 733 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 734 sc->bfe_rx_cons = 0; 735 } 736 737 bfe_core_reset(sc); 738 bfe_clear_stats(sc); 739 740 /* 741 * We want the phy registers to be accessible even when 742 * the driver is "downed" so initialize MDC preamble, frequency, 743 * and whether internal or external phy here. 744 */ 745 746 /* 4402 has 62.5Mhz SB clock and internal phy */ 747 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 748 749 /* Internal or external PHY? */ 750 val = CSR_READ_4(sc, BFE_DEVCTRL); 751 if (!(val & BFE_IPP)) 752 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 753 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 754 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 755 DELAY(100); 756 } 757 758 /* Enable CRC32 generation and set proper LED modes */ 759 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 760 761 /* Reset or clear powerdown control bit */ 762 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 763 764 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 765 BFE_LAZY_FC_MASK)); 766 767 /* 768 * We don't want lazy interrupts, so just send them at the end of a 769 * frame, please 770 */ 771 BFE_OR(sc, BFE_RCV_LAZY, 0); 772 773 /* Set max lengths, accounting for VLAN tags */ 774 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 775 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 776 777 /* Set watermark XXX - magic */ 778 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 779 780 /* 781 * Initialise DMA channels - not forgetting dma addresses need to be 782 * added to BFE_PCI_DMA 783 */ 784 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 785 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 786 787 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 788 BFE_RX_CTRL_ENABLE); 789 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 790 791 bfe_resetphy(sc); 792 bfe_setupphy(sc); 793 } 794 795 static void 796 bfe_core_disable(struct bfe_softc *sc) 797 { 798 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 799 return; 800 801 /* 802 * Set reject, wait for it set, then wait for the core to stop being busy 803 * Then set reset and reject and enable the clocks 804 */ 805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 806 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 807 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 808 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 809 BFE_RESET)); 810 CSR_READ_4(sc, BFE_SBTMSLOW); 811 DELAY(10); 812 /* Leave reset and reject set */ 813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 814 DELAY(10); 815 } 816 817 static void 818 bfe_core_reset(struct bfe_softc *sc) 819 { 820 uint32_t val; 821 822 /* Disable the core */ 823 bfe_core_disable(sc); 824 825 /* and bring it back up */ 826 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 827 CSR_READ_4(sc, BFE_SBTMSLOW); 828 DELAY(10); 829 830 /* Chip bug, clear SERR, IB and TO if they are set. */ 831 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 832 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 833 val = CSR_READ_4(sc, BFE_SBIMSTATE); 834 if (val & (BFE_IBE | BFE_TO)) 835 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 836 837 /* Clear reset and allow it to move through the core */ 838 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 839 CSR_READ_4(sc, BFE_SBTMSLOW); 840 DELAY(10); 841 842 /* Leave the clock set */ 843 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 844 CSR_READ_4(sc, BFE_SBTMSLOW); 845 DELAY(10); 846 } 847 848 static void 849 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 850 { 851 uint32_t val; 852 853 val = ((uint32_t) data[2]) << 24; 854 val |= ((uint32_t) data[3]) << 16; 855 val |= ((uint32_t) data[4]) << 8; 856 val |= ((uint32_t) data[5]); 857 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 858 val = (BFE_CAM_HI_VALID | 859 (((uint32_t) data[0]) << 8) | 860 (((uint32_t) data[1]))); 861 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 862 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 863 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 864 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 865 } 866 867 static void 868 bfe_set_rx_mode(struct bfe_softc *sc) 869 { 870 struct ifnet *ifp = &sc->arpcom.ac_if; 871 struct ifmultiaddr *ifma; 872 uint32_t val; 873 int i = 0; 874 875 val = CSR_READ_4(sc, BFE_RXCONF); 876 877 if (ifp->if_flags & IFF_PROMISC) 878 val |= BFE_RXCONF_PROMISC; 879 else 880 val &= ~BFE_RXCONF_PROMISC; 881 882 if (ifp->if_flags & IFF_BROADCAST) 883 val &= ~BFE_RXCONF_DBCAST; 884 else 885 val |= BFE_RXCONF_DBCAST; 886 887 888 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 889 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 890 891 if (ifp->if_flags & IFF_ALLMULTI) { 892 val |= BFE_RXCONF_ALLMULTI; 893 } else { 894 val &= ~BFE_RXCONF_ALLMULTI; 895 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 896 if (ifma->ifma_addr->sa_family != AF_LINK) 897 continue; 898 bfe_cam_write(sc, 899 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 900 } 901 } 902 903 CSR_WRITE_4(sc, BFE_RXCONF, val); 904 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 905 } 906 907 static void 908 bfe_dma_free(struct bfe_softc *sc) 909 { 910 int i; 911 912 if (sc->bfe_tx_tag != NULL) { 913 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 914 if (sc->bfe_tx_list != NULL) { 915 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 916 sc->bfe_tx_map); 917 sc->bfe_tx_list = NULL; 918 } 919 bus_dma_tag_destroy(sc->bfe_tx_tag); 920 sc->bfe_tx_tag = NULL; 921 } 922 923 if (sc->bfe_rx_tag != NULL) { 924 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 925 if (sc->bfe_rx_list != NULL) { 926 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 927 sc->bfe_rx_map); 928 sc->bfe_rx_list = NULL; 929 } 930 bus_dma_tag_destroy(sc->bfe_rx_tag); 931 sc->bfe_rx_tag = NULL; 932 } 933 934 if (sc->bfe_txbuf_tag != NULL) { 935 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 936 bus_dmamap_destroy(sc->bfe_txbuf_tag, 937 sc->bfe_tx_ring[i].bfe_map); 938 } 939 bus_dma_tag_destroy(sc->bfe_txbuf_tag); 940 sc->bfe_txbuf_tag = NULL; 941 } 942 943 if (sc->bfe_rxbuf_tag != NULL) { 944 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 945 bus_dmamap_destroy(sc->bfe_rxbuf_tag, 946 sc->bfe_rx_ring[i].bfe_map); 947 } 948 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap); 949 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 950 sc->bfe_rxbuf_tag = NULL; 951 } 952 953 if (sc->bfe_parent_tag != NULL) { 954 bus_dma_tag_destroy(sc->bfe_parent_tag); 955 sc->bfe_parent_tag = NULL; 956 } 957 } 958 959 static void 960 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 961 { 962 long i; 963 uint16_t *ptr = (uint16_t *)data; 964 965 for (i = 0; i < 128; i += 2) 966 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 967 } 968 969 static int 970 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 971 u_long timeout, const int clear) 972 { 973 u_long i; 974 975 for (i = 0; i < timeout; i++) { 976 uint32_t val = CSR_READ_4(sc, reg); 977 978 if (clear && !(val & bit)) 979 break; 980 if (!clear && (val & bit)) 981 break; 982 DELAY(10); 983 } 984 if (i == timeout) { 985 if_printf(&sc->arpcom.ac_if, 986 "BUG! Timeout waiting for bit %08x of register " 987 "%x to %s.\n", bit, reg, 988 (clear ? "clear" : "set")); 989 return -1; 990 } 991 return 0; 992 } 993 994 static int 995 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 996 { 997 int err; 998 999 /* Clear MII ISR */ 1000 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1001 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1002 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1003 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1004 (reg << BFE_MDIO_RA_SHIFT) | 1005 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1006 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1007 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1008 return(err); 1009 } 1010 1011 static int 1012 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1013 { 1014 int status; 1015 1016 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1017 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1018 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1019 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1020 (reg << BFE_MDIO_RA_SHIFT) | 1021 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1022 (val & BFE_MDIO_DATA_DATA))); 1023 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1024 1025 return status; 1026 } 1027 1028 /* 1029 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1030 * twice 1031 */ 1032 static int 1033 bfe_setupphy(struct bfe_softc *sc) 1034 { 1035 uint32_t val; 1036 1037 /* Enable activity LED */ 1038 bfe_readphy(sc, 26, &val); 1039 bfe_writephy(sc, 26, val & 0x7fff); 1040 bfe_readphy(sc, 26, &val); 1041 1042 /* Enable traffic meter LED mode */ 1043 bfe_readphy(sc, 27, &val); 1044 bfe_writephy(sc, 27, val | (1 << 6)); 1045 1046 return(0); 1047 } 1048 1049 static void 1050 bfe_stats_update(struct bfe_softc *sc) 1051 { 1052 u_long reg; 1053 uint32_t *val; 1054 1055 val = &sc->bfe_hwstats.tx_good_octets; 1056 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1057 *val++ += CSR_READ_4(sc, reg); 1058 val = &sc->bfe_hwstats.rx_good_octets; 1059 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1060 *val++ += CSR_READ_4(sc, reg); 1061 } 1062 1063 static void 1064 bfe_txeof(struct bfe_softc *sc) 1065 { 1066 struct ifnet *ifp = &sc->arpcom.ac_if; 1067 uint32_t i, chipidx; 1068 1069 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1070 chipidx /= sizeof(struct bfe_desc); 1071 1072 i = sc->bfe_tx_cons; 1073 1074 /* Go through the mbufs and free those that have been transmitted */ 1075 while (i != chipidx) { 1076 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1077 1078 if (r->bfe_mbuf != NULL) { 1079 ifp->if_opackets++; 1080 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map); 1081 m_freem(r->bfe_mbuf); 1082 r->bfe_mbuf = NULL; 1083 } 1084 1085 KKASSERT(sc->bfe_tx_cnt > 0); 1086 sc->bfe_tx_cnt--; 1087 BFE_INC(i, BFE_TX_LIST_CNT); 1088 } 1089 1090 if (i != sc->bfe_tx_cons) { 1091 sc->bfe_tx_cons = i; 1092 1093 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT) 1094 ifp->if_flags &= ~IFF_OACTIVE; 1095 } 1096 if (sc->bfe_tx_cnt == 0) 1097 ifp->if_timer = 0; 1098 } 1099 1100 /* Pass a received packet up the stack */ 1101 static void 1102 bfe_rxeof(struct bfe_softc *sc) 1103 { 1104 struct ifnet *ifp = &sc->arpcom.ac_if; 1105 struct mbuf *m; 1106 struct bfe_rxheader *rxheader; 1107 struct bfe_data *r; 1108 uint32_t cons, status, current, len, flags; 1109 struct mbuf_chain chain[MAXCPU]; 1110 1111 cons = sc->bfe_rx_cons; 1112 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1113 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1114 1115 ether_input_chain_init(chain); 1116 1117 while (current != cons) { 1118 r = &sc->bfe_rx_ring[cons]; 1119 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, 1120 BUS_DMASYNC_POSTREAD); 1121 1122 KKASSERT(r->bfe_mbuf != NULL); 1123 m = r->bfe_mbuf; 1124 rxheader = mtod(m, struct bfe_rxheader*); 1125 len = rxheader->len - ETHER_CRC_LEN; 1126 flags = rxheader->flags; 1127 1128 /* flag an error and try again */ 1129 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) { 1130 ifp->if_ierrors++; 1131 if (flags & BFE_RX_FLAG_SERR) 1132 ifp->if_collisions++; 1133 1134 bfe_setup_rxdesc(sc, cons); 1135 BFE_INC(cons, BFE_RX_LIST_CNT); 1136 continue; 1137 } 1138 1139 /* Go past the rx header */ 1140 if (bfe_newbuf(sc, cons, 0) != 0) { 1141 bfe_setup_rxdesc(sc, cons); 1142 ifp->if_ierrors++; 1143 BFE_INC(cons, BFE_RX_LIST_CNT); 1144 continue; 1145 } 1146 1147 m_adj(m, BFE_RX_OFFSET); 1148 m->m_len = m->m_pkthdr.len = len; 1149 1150 ifp->if_ipackets++; 1151 m->m_pkthdr.rcvif = ifp; 1152 1153 ether_input_chain(ifp, m, NULL, chain); 1154 BFE_INC(cons, BFE_RX_LIST_CNT); 1155 } 1156 1157 ether_input_dispatch(chain); 1158 1159 sc->bfe_rx_cons = cons; 1160 } 1161 1162 static void 1163 bfe_intr(void *xsc) 1164 { 1165 struct bfe_softc *sc = xsc; 1166 struct ifnet *ifp = &sc->arpcom.ac_if; 1167 uint32_t istat, imask, flag; 1168 1169 istat = CSR_READ_4(sc, BFE_ISTAT); 1170 imask = CSR_READ_4(sc, BFE_IMASK); 1171 1172 /* 1173 * Defer unsolicited interrupts - This is necessary because setting the 1174 * chips interrupt mask register to 0 doesn't actually stop the 1175 * interrupts 1176 */ 1177 istat &= imask; 1178 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1179 CSR_READ_4(sc, BFE_ISTAT); 1180 1181 /* not expecting this interrupt, disregard it */ 1182 if (istat == 0) { 1183 return; 1184 } 1185 1186 if (istat & BFE_ISTAT_ERRORS) { 1187 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1188 if (flag & BFE_STAT_EMASK) 1189 ifp->if_oerrors++; 1190 1191 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1192 if (flag & BFE_RX_FLAG_ERRORS) 1193 ifp->if_ierrors++; 1194 1195 ifp->if_flags &= ~IFF_RUNNING; 1196 bfe_init(sc); 1197 } 1198 1199 /* A packet was received */ 1200 if (istat & BFE_ISTAT_RX) 1201 bfe_rxeof(sc); 1202 1203 /* A packet was sent */ 1204 if (istat & BFE_ISTAT_TX) 1205 bfe_txeof(sc); 1206 1207 /* We have packets pending, fire them out */ 1208 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1209 if_devstart(ifp); 1210 } 1211 1212 static int 1213 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1214 { 1215 bus_dma_segment_t segs[BFE_MAXSEGS]; 1216 bus_dmamap_t map; 1217 int i, first_idx, last_idx, cur, error, maxsegs, nsegs; 1218 1219 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT); 1220 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC; 1221 if (maxsegs > BFE_MAXSEGS) 1222 maxsegs = BFE_MAXSEGS; 1223 1224 first_idx = *txidx; 1225 map = sc->bfe_tx_ring[first_idx].bfe_map; 1226 1227 error = bus_dmamap_load_mbuf_defrag(sc->bfe_txbuf_tag, map, m_head, 1228 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1229 if (error) 1230 goto fail; 1231 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE); 1232 1233 last_idx = -1; 1234 cur = first_idx; 1235 for (i = 0; i < nsegs; ++i) { 1236 struct bfe_desc *d; 1237 uint32_t ctrl; 1238 1239 ctrl = BFE_DESC_LEN & segs[i].ds_len; 1240 ctrl |= BFE_DESC_IOC; /* always interrupt */ 1241 if (cur == BFE_TX_LIST_CNT - 1) { 1242 /* 1243 * Tell the chip to wrap to the 1244 * start of the descriptor list. 1245 */ 1246 ctrl |= BFE_DESC_EOT; 1247 } 1248 1249 d = &sc->bfe_tx_list[cur]; 1250 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA; 1251 d->bfe_ctrl = ctrl; 1252 1253 last_idx = cur; 1254 BFE_INC(cur, BFE_TX_LIST_CNT); 1255 } 1256 KKASSERT(last_idx >= 0); 1257 1258 /* End of the frame */ 1259 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF; 1260 1261 /* 1262 * Set start of the frame on the first fragment, 1263 * _after_ all of the fragments are setup. 1264 */ 1265 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF; 1266 1267 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map; 1268 sc->bfe_tx_ring[last_idx].bfe_map = map; 1269 sc->bfe_tx_ring[last_idx].bfe_mbuf = *m_head; 1270 1271 *txidx = cur; 1272 sc->bfe_tx_cnt += nsegs; 1273 return 0; 1274 fail: 1275 m_freem(*m_head); 1276 *m_head = NULL; 1277 return error; 1278 } 1279 1280 /* 1281 * Set up to transmit a packet 1282 */ 1283 static void 1284 bfe_start(struct ifnet *ifp) 1285 { 1286 struct bfe_softc *sc = ifp->if_softc; 1287 struct mbuf *m_head = NULL; 1288 int idx, need_trans; 1289 1290 ASSERT_SERIALIZED(ifp->if_serializer); 1291 1292 /* 1293 * Not much point trying to send if the link is down 1294 * or we have nothing to send. 1295 */ 1296 if (!sc->bfe_link) { 1297 ifq_purge(&ifp->if_snd); 1298 return; 1299 } 1300 1301 if (ifp->if_flags & IFF_OACTIVE) 1302 return; 1303 1304 idx = sc->bfe_tx_prod; 1305 1306 need_trans = 0; 1307 while (!ifq_is_empty(&ifp->if_snd)) { 1308 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) { 1309 ifp->if_flags |= IFF_OACTIVE; 1310 break; 1311 } 1312 1313 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1314 if (m_head == NULL) 1315 break; 1316 1317 /* 1318 * Pack the data into the tx ring. If we don't have 1319 * enough room, let the chip drain the ring. 1320 */ 1321 if (bfe_encap(sc, &m_head, &idx)) { 1322 /* m_head is freed by re_encap(), if we reach here */ 1323 ifp->if_oerrors++; 1324 1325 if (sc->bfe_tx_cnt > 0) { 1326 ifp->if_flags |= IFF_OACTIVE; 1327 break; 1328 } else { 1329 /* 1330 * IFF_OACTIVE could not be set under 1331 * this situation, since except up/down, 1332 * nothing will clear IFF_OACTIVE. 1333 * 1334 * Let's just keep draining the ifq ... 1335 */ 1336 continue; 1337 } 1338 } 1339 need_trans = 1; 1340 1341 /* 1342 * If there's a BPF listener, bounce a copy of this frame 1343 * to him. 1344 */ 1345 BPF_MTAP(ifp, m_head); 1346 } 1347 1348 if (!need_trans) 1349 return; 1350 1351 sc->bfe_tx_prod = idx; 1352 1353 /* Transmit - twice due to apparent hardware bug */ 1354 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1355 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1356 1357 /* 1358 * Set a timeout in case the chip goes out to lunch. 1359 */ 1360 ifp->if_timer = 5; 1361 } 1362 1363 static void 1364 bfe_init(void *xsc) 1365 { 1366 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1367 struct ifnet *ifp = &sc->arpcom.ac_if; 1368 1369 ASSERT_SERIALIZED(ifp->if_serializer); 1370 1371 if (ifp->if_flags & IFF_RUNNING) 1372 return; 1373 1374 bfe_stop(sc); 1375 bfe_chip_reset(sc); 1376 1377 if (bfe_list_rx_init(sc) == ENOBUFS) { 1378 if_printf(ifp, "bfe_init failed. " 1379 " Not enough memory for list buffers\n"); 1380 bfe_stop(sc); 1381 return; 1382 } 1383 1384 bfe_set_rx_mode(sc); 1385 1386 /* Enable the chip and core */ 1387 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1388 /* Enable interrupts */ 1389 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1390 1391 bfe_ifmedia_upd(ifp); 1392 ifp->if_flags |= IFF_RUNNING; 1393 ifp->if_flags &= ~IFF_OACTIVE; 1394 1395 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1396 } 1397 1398 /* 1399 * Set media options. 1400 */ 1401 static int 1402 bfe_ifmedia_upd(struct ifnet *ifp) 1403 { 1404 struct bfe_softc *sc = ifp->if_softc; 1405 struct mii_data *mii; 1406 1407 ASSERT_SERIALIZED(ifp->if_serializer); 1408 1409 mii = device_get_softc(sc->bfe_miibus); 1410 sc->bfe_link = 0; 1411 if (mii->mii_instance) { 1412 struct mii_softc *miisc; 1413 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1414 miisc = LIST_NEXT(miisc, mii_list)) 1415 mii_phy_reset(miisc); 1416 } 1417 mii_mediachg(mii); 1418 1419 bfe_setupphy(sc); 1420 1421 return(0); 1422 } 1423 1424 /* 1425 * Report current media status. 1426 */ 1427 static void 1428 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1429 { 1430 struct bfe_softc *sc = ifp->if_softc; 1431 struct mii_data *mii; 1432 1433 ASSERT_SERIALIZED(ifp->if_serializer); 1434 1435 mii = device_get_softc(sc->bfe_miibus); 1436 mii_pollstat(mii); 1437 ifmr->ifm_active = mii->mii_media_active; 1438 ifmr->ifm_status = mii->mii_media_status; 1439 } 1440 1441 static int 1442 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1443 { 1444 struct bfe_softc *sc = ifp->if_softc; 1445 struct ifreq *ifr = (struct ifreq *) data; 1446 struct mii_data *mii; 1447 int error = 0; 1448 1449 ASSERT_SERIALIZED(ifp->if_serializer); 1450 1451 switch (command) { 1452 case SIOCSIFFLAGS: 1453 if (ifp->if_flags & IFF_UP) 1454 if (ifp->if_flags & IFF_RUNNING) 1455 bfe_set_rx_mode(sc); 1456 else 1457 bfe_init(sc); 1458 else if (ifp->if_flags & IFF_RUNNING) 1459 bfe_stop(sc); 1460 break; 1461 case SIOCADDMULTI: 1462 case SIOCDELMULTI: 1463 if (ifp->if_flags & IFF_RUNNING) 1464 bfe_set_rx_mode(sc); 1465 break; 1466 case SIOCGIFMEDIA: 1467 case SIOCSIFMEDIA: 1468 mii = device_get_softc(sc->bfe_miibus); 1469 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1470 command); 1471 break; 1472 default: 1473 error = ether_ioctl(ifp, command, data); 1474 break; 1475 } 1476 return error; 1477 } 1478 1479 static void 1480 bfe_watchdog(struct ifnet *ifp) 1481 { 1482 struct bfe_softc *sc = ifp->if_softc; 1483 1484 ASSERT_SERIALIZED(ifp->if_serializer); 1485 1486 if_printf(ifp, "watchdog timeout -- resetting\n"); 1487 1488 ifp->if_flags &= ~IFF_RUNNING; 1489 bfe_init(sc); 1490 1491 ifp->if_oerrors++; 1492 } 1493 1494 static void 1495 bfe_tick(void *xsc) 1496 { 1497 struct bfe_softc *sc = xsc; 1498 struct mii_data *mii; 1499 struct ifnet *ifp = &sc->arpcom.ac_if; 1500 1501 mii = device_get_softc(sc->bfe_miibus); 1502 1503 lwkt_serialize_enter(ifp->if_serializer); 1504 1505 bfe_stats_update(sc); 1506 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1507 1508 if (sc->bfe_link == 0) { 1509 mii_tick(mii); 1510 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1511 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1512 sc->bfe_link++; 1513 } 1514 if (!sc->bfe_link) 1515 sc->bfe_link++; 1516 } 1517 lwkt_serialize_exit(ifp->if_serializer); 1518 } 1519 1520 /* 1521 * Stop the adapter and free any mbufs allocated to the 1522 * RX and TX lists. 1523 */ 1524 static void 1525 bfe_stop(struct bfe_softc *sc) 1526 { 1527 struct ifnet *ifp = &sc->arpcom.ac_if; 1528 1529 ASSERT_SERIALIZED(ifp->if_serializer); 1530 1531 callout_stop(&sc->bfe_stat_timer); 1532 1533 bfe_chip_halt(sc); 1534 bfe_tx_ring_free(sc); 1535 bfe_rx_ring_free(sc); 1536 1537 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1538 } 1539