1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 #include <sys/interrupt.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/rman.h> 45 46 #include <net/if.h> 47 #include <net/ifq_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <net/bpf.h> 54 55 #include <net/if_types.h> 56 #include <net/vlan/if_vlan_var.h> 57 58 #include <netinet/in_systm.h> 59 #include <netinet/in.h> 60 #include <netinet/ip.h> 61 62 #include <bus/pci/pcireg.h> 63 #include <bus/pci/pcivar.h> 64 #include "pcidevs.h" 65 66 #include <dev/netif/mii_layer/mii.h> 67 #include <dev/netif/mii_layer/miivar.h> 68 69 #include <dev/netif/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 73 74 /* "controller miibus0" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78 79 static struct bfe_type bfe_devs[] = { 80 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 81 "Broadcom BCM4401 Fast Ethernet" }, 82 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 83 "Broadcom BCM4401-B0 Fast Ethernet" }, 84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402, 85 "Broadcom BCM4402 Fast Ethernet" }, 86 { 0, 0, NULL } 87 }; 88 89 static int bfe_probe(device_t); 90 static int bfe_attach(device_t); 91 static int bfe_detach(device_t); 92 static void bfe_intr(void *); 93 static void bfe_start(struct ifnet *, struct ifaltq_subque *); 94 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 95 static void bfe_init(void *); 96 static void bfe_stop(struct bfe_softc *); 97 static void bfe_watchdog(struct ifnet *); 98 static void bfe_shutdown(device_t); 99 static void bfe_tick(void *); 100 static void bfe_txeof(struct bfe_softc *); 101 static void bfe_rxeof(struct bfe_softc *); 102 static void bfe_set_rx_mode(struct bfe_softc *); 103 static int bfe_list_rx_init(struct bfe_softc *); 104 static int bfe_newbuf(struct bfe_softc *, int, int); 105 static void bfe_setup_rxdesc(struct bfe_softc *, int); 106 static void bfe_rx_ring_free(struct bfe_softc *); 107 108 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 109 static int bfe_ifmedia_upd(struct ifnet *); 110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 111 static int bfe_miibus_readreg(device_t, int, int); 112 static int bfe_miibus_writereg(device_t, int, int, int); 113 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 114 u_long, const int); 115 static void bfe_get_config(struct bfe_softc *sc); 116 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 117 static void bfe_stats_update(struct bfe_softc *); 118 static void bfe_clear_stats (struct bfe_softc *); 119 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 120 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 121 static int bfe_resetphy(struct bfe_softc *); 122 static int bfe_setupphy(struct bfe_softc *); 123 static void bfe_chip_reset(struct bfe_softc *); 124 static void bfe_chip_halt(struct bfe_softc *); 125 static void bfe_core_reset(struct bfe_softc *); 126 static void bfe_core_disable(struct bfe_softc *); 127 static int bfe_dma_alloc(device_t); 128 static void bfe_dma_free(struct bfe_softc *); 129 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 130 131 static device_method_t bfe_methods[] = { 132 /* Device interface */ 133 DEVMETHOD(device_probe, bfe_probe), 134 DEVMETHOD(device_attach, bfe_attach), 135 DEVMETHOD(device_detach, bfe_detach), 136 DEVMETHOD(device_shutdown, bfe_shutdown), 137 138 /* bus interface */ 139 DEVMETHOD(bus_print_child, bus_generic_print_child), 140 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 141 142 /* MII interface */ 143 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 144 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 145 146 DEVMETHOD_END 147 }; 148 149 static driver_t bfe_driver = { 150 "bfe", 151 bfe_methods, 152 sizeof(struct bfe_softc) 153 }; 154 155 static devclass_t bfe_devclass; 156 157 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, NULL, NULL); 158 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, NULL, NULL); 159 160 /* 161 * Probe for a Broadcom 4401 chip. 162 */ 163 static int 164 bfe_probe(device_t dev) 165 { 166 struct bfe_type *t; 167 uint16_t vendor, product; 168 169 vendor = pci_get_vendor(dev); 170 product = pci_get_device(dev); 171 172 for (t = bfe_devs; t->bfe_name != NULL; t++) { 173 if (vendor == t->bfe_vid && product == t->bfe_did) { 174 device_set_desc(dev, t->bfe_name); 175 return(0); 176 } 177 } 178 179 return(ENXIO); 180 } 181 182 static int 183 bfe_dma_alloc(device_t dev) 184 { 185 struct bfe_softc *sc = device_get_softc(dev); 186 bus_dmamem_t dmem; 187 int error, i, tx_pos = 0, rx_pos = 0; 188 189 /* 190 * Parent tag. Apparently the chip cannot handle any DMA address 191 * greater than BFE_BUS_SPACE_MAXADDR (1GB). 192 */ 193 error = bus_dma_tag_create(NULL, /* parent */ 194 1, 0, /* alignment, boundary */ 195 BFE_BUS_SPACE_MAXADDR, /* lowaddr */ 196 BUS_SPACE_MAXADDR, /* highaddr */ 197 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 198 0, /* num of segments */ 199 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 200 0, /* flags */ 201 &sc->bfe_parent_tag); 202 if (error) { 203 device_printf(dev, "could not allocate parent dma tag\n"); 204 return(error); 205 } 206 207 /* Allocate TX ring */ 208 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0, 209 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 210 BFE_TX_LIST_SIZE, 211 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 212 if (error) { 213 device_printf(dev, "could not allocate TX list\n"); 214 return(error); 215 } 216 sc->bfe_tx_tag = dmem.dmem_tag; 217 sc->bfe_tx_map = dmem.dmem_map; 218 sc->bfe_tx_list = dmem.dmem_addr; 219 sc->bfe_tx_dma = dmem.dmem_busaddr; 220 221 /* Allocate RX ring */ 222 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0, 223 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 224 BFE_RX_LIST_SIZE, 225 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 226 if (error) { 227 device_printf(dev, "could not allocate RX list\n"); 228 return(error); 229 } 230 sc->bfe_rx_tag = dmem.dmem_tag; 231 sc->bfe_rx_map = dmem.dmem_map; 232 sc->bfe_rx_list = dmem.dmem_addr; 233 sc->bfe_rx_dma = dmem.dmem_busaddr; 234 235 /* Tag for RX mbufs */ 236 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 238 MCLBYTES, 1, MCLBYTES, 239 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 240 &sc->bfe_rxbuf_tag); 241 if (error) { 242 device_printf(dev, "could not allocate dma tag for RX mbufs\n"); 243 return(error); 244 } 245 246 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK, 247 &sc->bfe_rx_tmpmap); 248 if (error) { 249 device_printf(dev, "could not create RX mbuf tmp map\n"); 250 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 251 sc->bfe_rxbuf_tag = NULL; 252 return error; 253 } 254 255 /* Allocate dma maps for RX list */ 256 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 257 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK, 258 &sc->bfe_rx_ring[i].bfe_map); 259 if (error) { 260 rx_pos = i; 261 device_printf(dev, "cannot create DMA map for RX\n"); 262 goto ring_fail; 263 } 264 } 265 rx_pos = BFE_RX_LIST_CNT; 266 267 /* Tag for TX mbufs */ 268 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0, 269 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 270 MCLBYTES, BFE_MAXSEGS, MCLBYTES, 271 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 272 &sc->bfe_txbuf_tag); 273 if (error) { 274 device_printf(dev, "could not allocate dma tag for TX mbufs\n"); 275 return(error); 276 } 277 278 /* Allocate dmamaps for TX list */ 279 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 280 error = bus_dmamap_create(sc->bfe_txbuf_tag, BUS_DMA_WAITOK, 281 &sc->bfe_tx_ring[i].bfe_map); 282 if (error) { 283 tx_pos = i; 284 device_printf(dev, "cannot create DMA map for TX\n"); 285 goto ring_fail; 286 } 287 } 288 289 return(0); 290 291 ring_fail: 292 if (sc->bfe_rxbuf_tag != NULL) { 293 for (i = 0; i < rx_pos; ++i) { 294 bus_dmamap_destroy(sc->bfe_rxbuf_tag, 295 sc->bfe_rx_ring[i].bfe_map); 296 } 297 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap); 298 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 299 sc->bfe_rxbuf_tag = NULL; 300 } 301 302 if (sc->bfe_txbuf_tag != NULL) { 303 for (i = 0; i < tx_pos; ++i) { 304 bus_dmamap_destroy(sc->bfe_txbuf_tag, 305 sc->bfe_tx_ring[i].bfe_map); 306 } 307 bus_dma_tag_destroy(sc->bfe_txbuf_tag); 308 sc->bfe_txbuf_tag = NULL; 309 } 310 return error; 311 } 312 313 static int 314 bfe_attach(device_t dev) 315 { 316 struct ifnet *ifp; 317 struct bfe_softc *sc; 318 int error = 0, rid; 319 320 sc = device_get_softc(dev); 321 322 sc->bfe_dev = dev; 323 callout_init(&sc->bfe_stat_timer); 324 325 #ifndef BURN_BRIDGES 326 /* 327 * Handle power management nonsense. 328 */ 329 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 330 uint32_t membase, irq; 331 332 /* Save important PCI config data. */ 333 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 334 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 335 336 /* Reset the power state. */ 337 device_printf(dev, "chip is in D%d power mode" 338 " -- setting to D0\n", pci_get_powerstate(dev)); 339 340 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 341 342 /* Restore PCI config data. */ 343 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 344 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 345 } 346 #endif /* !BURN_BRIDGE */ 347 348 /* 349 * Map control/status registers. 350 */ 351 pci_enable_busmaster(dev); 352 353 rid = BFE_PCI_MEMLO; 354 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 355 RF_ACTIVE); 356 if (sc->bfe_res == NULL) { 357 device_printf(dev, "couldn't map memory\n"); 358 return ENXIO; 359 } 360 361 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 362 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 363 364 /* Allocate interrupt */ 365 rid = 0; 366 367 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 368 RF_SHAREABLE | RF_ACTIVE); 369 if (sc->bfe_irq == NULL) { 370 device_printf(dev, "couldn't map interrupt\n"); 371 error = ENXIO; 372 goto fail; 373 } 374 375 error = bfe_dma_alloc(dev); 376 if (error != 0) { 377 device_printf(dev, "failed to allocate DMA resources\n"); 378 goto fail; 379 } 380 381 /* Set up ifnet structure */ 382 ifp = &sc->arpcom.ac_if; 383 ifp->if_softc = sc; 384 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = bfe_ioctl; 387 ifp->if_start = bfe_start; 388 ifp->if_watchdog = bfe_watchdog; 389 ifp->if_init = bfe_init; 390 ifp->if_mtu = ETHERMTU; 391 ifp->if_baudrate = 100000000; 392 ifp->if_capabilities |= IFCAP_VLAN_MTU; 393 ifp->if_capenable |= IFCAP_VLAN_MTU; 394 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 395 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 396 ifq_set_ready(&ifp->if_snd); 397 398 bfe_get_config(sc); 399 400 /* Reset the chip and turn on the PHY */ 401 bfe_chip_reset(sc); 402 403 if (mii_phy_probe(dev, &sc->bfe_miibus, 404 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 405 device_printf(dev, "MII without any PHY!\n"); 406 error = ENXIO; 407 goto fail; 408 } 409 410 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 411 412 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bfe_irq)); 413 414 /* 415 * Hook interrupt last to avoid having to lock softc 416 */ 417 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE, 418 bfe_intr, sc, &sc->bfe_intrhand, 419 sc->arpcom.ac_if.if_serializer); 420 421 if (error) { 422 ether_ifdetach(ifp); 423 device_printf(dev, "couldn't set up irq\n"); 424 goto fail; 425 } 426 return 0; 427 fail: 428 bfe_detach(dev); 429 return(error); 430 } 431 432 static int 433 bfe_detach(device_t dev) 434 { 435 struct bfe_softc *sc = device_get_softc(dev); 436 struct ifnet *ifp = &sc->arpcom.ac_if; 437 438 if (device_is_attached(dev)) { 439 lwkt_serialize_enter(ifp->if_serializer); 440 bfe_stop(sc); 441 bfe_chip_reset(sc); 442 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 443 lwkt_serialize_exit(ifp->if_serializer); 444 445 ether_ifdetach(ifp); 446 } 447 if (sc->bfe_miibus != NULL) 448 device_delete_child(dev, sc->bfe_miibus); 449 bus_generic_detach(dev); 450 451 if (sc->bfe_irq != NULL) 452 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 453 454 if (sc->bfe_res != NULL) { 455 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 456 sc->bfe_res); 457 } 458 bfe_dma_free(sc); 459 460 return(0); 461 } 462 463 /* 464 * Stop all chip I/O so that the kernel's probe routines don't 465 * get confused by errant DMAs when rebooting. 466 */ 467 static void 468 bfe_shutdown(device_t dev) 469 { 470 struct bfe_softc *sc = device_get_softc(dev); 471 struct ifnet *ifp = &sc->arpcom.ac_if; 472 473 lwkt_serialize_enter(ifp->if_serializer); 474 bfe_stop(sc); 475 lwkt_serialize_exit(ifp->if_serializer); 476 } 477 478 static int 479 bfe_miibus_readreg(device_t dev, int phy, int reg) 480 { 481 struct bfe_softc *sc; 482 uint32_t ret; 483 484 sc = device_get_softc(dev); 485 if (phy != sc->bfe_phyaddr) 486 return(0); 487 bfe_readphy(sc, reg, &ret); 488 489 return(ret); 490 } 491 492 static int 493 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 494 { 495 struct bfe_softc *sc; 496 497 sc = device_get_softc(dev); 498 if (phy != sc->bfe_phyaddr) 499 return(0); 500 bfe_writephy(sc, reg, val); 501 502 return(0); 503 } 504 505 static void 506 bfe_tx_ring_free(struct bfe_softc *sc) 507 { 508 int i; 509 510 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 511 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 512 bus_dmamap_unload(sc->bfe_txbuf_tag, 513 sc->bfe_tx_ring[i].bfe_map); 514 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 515 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 516 } 517 } 518 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 519 } 520 521 static void 522 bfe_rx_ring_free(struct bfe_softc *sc) 523 { 524 int i; 525 526 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 527 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 528 bus_dmamap_unload(sc->bfe_rxbuf_tag, 529 sc->bfe_rx_ring[i].bfe_map); 530 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 531 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 532 } 533 } 534 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 535 } 536 537 static int 538 bfe_list_rx_init(struct bfe_softc *sc) 539 { 540 int i, error; 541 542 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 543 error = bfe_newbuf(sc, i, 1); 544 if (error) 545 return(error); 546 } 547 548 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 549 550 sc->bfe_rx_cons = 0; 551 552 return(0); 553 } 554 555 static int 556 bfe_newbuf(struct bfe_softc *sc, int c, int init) 557 { 558 struct bfe_data *r; 559 bus_dmamap_t map; 560 bus_dma_segment_t seg; 561 struct mbuf *m; 562 int error, nsegs; 563 564 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 565 if (m == NULL) 566 return ENOBUFS; 567 m->m_len = m->m_pkthdr.len = MCLBYTES; 568 569 error = bus_dmamap_load_mbuf_segment(sc->bfe_rxbuf_tag, 570 sc->bfe_rx_tmpmap, m, 571 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 572 if (error) { 573 m_freem(m); 574 if (init) 575 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 576 return error; 577 } 578 579 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT); 580 r = &sc->bfe_rx_ring[c]; 581 582 if (r->bfe_mbuf != NULL) 583 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map); 584 585 map = r->bfe_map; 586 r->bfe_map = sc->bfe_rx_tmpmap; 587 sc->bfe_rx_tmpmap = map; 588 589 r->bfe_mbuf = m; 590 r->bfe_paddr = seg.ds_addr; 591 592 bfe_setup_rxdesc(sc, c); 593 return 0; 594 } 595 596 static void 597 bfe_setup_rxdesc(struct bfe_softc *sc, int c) 598 { 599 struct bfe_rxheader *rx_header; 600 struct mbuf *m; 601 struct bfe_desc *d; 602 struct bfe_data *r; 603 uint32_t ctrl; 604 605 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT); 606 r = &sc->bfe_rx_ring[c]; 607 d = &sc->bfe_rx_list[c]; 608 609 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0); 610 611 m = r->bfe_mbuf; 612 rx_header = mtod(m, struct bfe_rxheader *); 613 rx_header->len = 0; 614 rx_header->flags = 0; 615 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 616 617 ctrl = ETHER_MAX_LEN + 32; 618 if (c == BFE_RX_LIST_CNT - 1) 619 ctrl |= BFE_DESC_EOT; 620 621 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA; 622 d->bfe_ctrl = ctrl; 623 } 624 625 static void 626 bfe_get_config(struct bfe_softc *sc) 627 { 628 uint8_t eeprom[128]; 629 630 bfe_read_eeprom(sc, eeprom); 631 632 sc->arpcom.ac_enaddr[0] = eeprom[79]; 633 sc->arpcom.ac_enaddr[1] = eeprom[78]; 634 sc->arpcom.ac_enaddr[2] = eeprom[81]; 635 sc->arpcom.ac_enaddr[3] = eeprom[80]; 636 sc->arpcom.ac_enaddr[4] = eeprom[83]; 637 sc->arpcom.ac_enaddr[5] = eeprom[82]; 638 639 sc->bfe_phyaddr = eeprom[90] & 0x1f; 640 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 641 642 sc->bfe_core_unit = 0; 643 sc->bfe_dma_offset = BFE_PCI_DMA; 644 } 645 646 static void 647 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 648 { 649 uint32_t bar_orig, val; 650 651 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 652 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 653 654 val = CSR_READ_4(sc, BFE_SBINTVEC); 655 val |= cores; 656 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 657 658 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 659 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 660 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 661 662 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 663 } 664 665 static void 666 bfe_clear_stats(struct bfe_softc *sc) 667 { 668 u_long reg; 669 670 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 671 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 672 CSR_READ_4(sc, reg); 673 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 674 CSR_READ_4(sc, reg); 675 } 676 677 static int 678 bfe_resetphy(struct bfe_softc *sc) 679 { 680 uint32_t val; 681 682 bfe_writephy(sc, 0, BMCR_RESET); 683 DELAY(100); 684 bfe_readphy(sc, 0, &val); 685 if (val & BMCR_RESET) { 686 if_printf(&sc->arpcom.ac_if, 687 "PHY Reset would not complete.\n"); 688 return(ENXIO); 689 } 690 return(0); 691 } 692 693 static void 694 bfe_chip_halt(struct bfe_softc *sc) 695 { 696 /* disable interrupts - not that it actually does..*/ 697 CSR_WRITE_4(sc, BFE_IMASK, 0); 698 CSR_READ_4(sc, BFE_IMASK); 699 700 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 701 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 702 703 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 704 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 705 DELAY(10); 706 } 707 708 static void 709 bfe_chip_reset(struct bfe_softc *sc) 710 { 711 uint32_t val; 712 713 /* Set the interrupt vector for the enet core */ 714 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 715 716 /* is core up? */ 717 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 718 if (val == BFE_CLOCK) { 719 /* It is, so shut it down */ 720 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 721 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 722 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 723 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 724 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 725 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 726 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 727 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 728 sc->bfe_rx_cons = 0; 729 } 730 731 bfe_core_reset(sc); 732 bfe_clear_stats(sc); 733 734 /* 735 * We want the phy registers to be accessible even when 736 * the driver is "downed" so initialize MDC preamble, frequency, 737 * and whether internal or external phy here. 738 */ 739 740 /* 4402 has 62.5Mhz SB clock and internal phy */ 741 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 742 743 /* Internal or external PHY? */ 744 val = CSR_READ_4(sc, BFE_DEVCTRL); 745 if (!(val & BFE_IPP)) 746 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 747 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 748 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 749 DELAY(100); 750 } 751 752 /* Enable CRC32 generation and set proper LED modes */ 753 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 754 755 /* Reset or clear powerdown control bit */ 756 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 757 758 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 759 BFE_LAZY_FC_MASK)); 760 761 /* 762 * We don't want lazy interrupts, so just send them at the end of a 763 * frame, please 764 */ 765 BFE_OR(sc, BFE_RCV_LAZY, 0); 766 767 /* Set max lengths, accounting for VLAN tags */ 768 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 769 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 770 771 /* Set watermark XXX - magic */ 772 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 773 774 /* 775 * Initialise DMA channels - not forgetting dma addresses need to be 776 * added to BFE_PCI_DMA 777 */ 778 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 779 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 780 781 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 782 BFE_RX_CTRL_ENABLE); 783 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 784 785 bfe_resetphy(sc); 786 bfe_setupphy(sc); 787 } 788 789 static void 790 bfe_core_disable(struct bfe_softc *sc) 791 { 792 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 793 return; 794 795 /* 796 * Set reject, wait for it set, then wait for the core to stop being busy 797 * Then set reset and reject and enable the clocks 798 */ 799 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 800 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 801 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 802 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 803 BFE_RESET)); 804 CSR_READ_4(sc, BFE_SBTMSLOW); 805 DELAY(10); 806 /* Leave reset and reject set */ 807 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 808 DELAY(10); 809 } 810 811 static void 812 bfe_core_reset(struct bfe_softc *sc) 813 { 814 uint32_t val; 815 816 /* Disable the core */ 817 bfe_core_disable(sc); 818 819 /* and bring it back up */ 820 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 821 CSR_READ_4(sc, BFE_SBTMSLOW); 822 DELAY(10); 823 824 /* Chip bug, clear SERR, IB and TO if they are set. */ 825 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 826 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 827 val = CSR_READ_4(sc, BFE_SBIMSTATE); 828 if (val & (BFE_IBE | BFE_TO)) 829 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 830 831 /* Clear reset and allow it to move through the core */ 832 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 833 CSR_READ_4(sc, BFE_SBTMSLOW); 834 DELAY(10); 835 836 /* Leave the clock set */ 837 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 838 CSR_READ_4(sc, BFE_SBTMSLOW); 839 DELAY(10); 840 } 841 842 static void 843 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 844 { 845 uint32_t val; 846 847 val = ((uint32_t) data[2]) << 24; 848 val |= ((uint32_t) data[3]) << 16; 849 val |= ((uint32_t) data[4]) << 8; 850 val |= ((uint32_t) data[5]); 851 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 852 val = (BFE_CAM_HI_VALID | 853 (((uint32_t) data[0]) << 8) | 854 (((uint32_t) data[1]))); 855 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 856 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 857 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 858 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 859 } 860 861 static void 862 bfe_set_rx_mode(struct bfe_softc *sc) 863 { 864 struct ifnet *ifp = &sc->arpcom.ac_if; 865 struct ifmultiaddr *ifma; 866 uint32_t val; 867 int i = 0; 868 869 val = CSR_READ_4(sc, BFE_RXCONF); 870 871 if (ifp->if_flags & IFF_PROMISC) 872 val |= BFE_RXCONF_PROMISC; 873 else 874 val &= ~BFE_RXCONF_PROMISC; 875 876 if (ifp->if_flags & IFF_BROADCAST) 877 val &= ~BFE_RXCONF_DBCAST; 878 else 879 val |= BFE_RXCONF_DBCAST; 880 881 882 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 883 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 884 885 if (ifp->if_flags & IFF_ALLMULTI) { 886 val |= BFE_RXCONF_ALLMULTI; 887 } else { 888 val &= ~BFE_RXCONF_ALLMULTI; 889 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 890 if (ifma->ifma_addr->sa_family != AF_LINK) 891 continue; 892 bfe_cam_write(sc, 893 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 894 } 895 } 896 897 CSR_WRITE_4(sc, BFE_RXCONF, val); 898 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 899 } 900 901 static void 902 bfe_dma_free(struct bfe_softc *sc) 903 { 904 int i; 905 906 if (sc->bfe_tx_tag != NULL) { 907 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 908 if (sc->bfe_tx_list != NULL) { 909 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 910 sc->bfe_tx_map); 911 sc->bfe_tx_list = NULL; 912 } 913 bus_dma_tag_destroy(sc->bfe_tx_tag); 914 sc->bfe_tx_tag = NULL; 915 } 916 917 if (sc->bfe_rx_tag != NULL) { 918 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 919 if (sc->bfe_rx_list != NULL) { 920 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 921 sc->bfe_rx_map); 922 sc->bfe_rx_list = NULL; 923 } 924 bus_dma_tag_destroy(sc->bfe_rx_tag); 925 sc->bfe_rx_tag = NULL; 926 } 927 928 if (sc->bfe_txbuf_tag != NULL) { 929 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 930 bus_dmamap_destroy(sc->bfe_txbuf_tag, 931 sc->bfe_tx_ring[i].bfe_map); 932 } 933 bus_dma_tag_destroy(sc->bfe_txbuf_tag); 934 sc->bfe_txbuf_tag = NULL; 935 } 936 937 if (sc->bfe_rxbuf_tag != NULL) { 938 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 939 bus_dmamap_destroy(sc->bfe_rxbuf_tag, 940 sc->bfe_rx_ring[i].bfe_map); 941 } 942 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap); 943 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 944 sc->bfe_rxbuf_tag = NULL; 945 } 946 947 if (sc->bfe_parent_tag != NULL) { 948 bus_dma_tag_destroy(sc->bfe_parent_tag); 949 sc->bfe_parent_tag = NULL; 950 } 951 } 952 953 static void 954 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 955 { 956 long i; 957 uint16_t *ptr = (uint16_t *)data; 958 959 for (i = 0; i < 128; i += 2) 960 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 961 } 962 963 static int 964 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 965 u_long timeout, const int clear) 966 { 967 u_long i; 968 969 for (i = 0; i < timeout; i++) { 970 uint32_t val = CSR_READ_4(sc, reg); 971 972 if (clear && !(val & bit)) 973 break; 974 if (!clear && (val & bit)) 975 break; 976 DELAY(10); 977 } 978 if (i == timeout) { 979 if_printf(&sc->arpcom.ac_if, 980 "BUG! Timeout waiting for bit %08x of register " 981 "%x to %s.\n", bit, reg, 982 (clear ? "clear" : "set")); 983 return -1; 984 } 985 return 0; 986 } 987 988 static int 989 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 990 { 991 int err; 992 993 /* Clear MII ISR */ 994 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 995 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 996 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 997 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 998 (reg << BFE_MDIO_RA_SHIFT) | 999 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1000 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1001 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1002 return(err); 1003 } 1004 1005 static int 1006 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1007 { 1008 int status; 1009 1010 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1011 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1012 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1013 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1014 (reg << BFE_MDIO_RA_SHIFT) | 1015 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1016 (val & BFE_MDIO_DATA_DATA))); 1017 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1018 1019 return status; 1020 } 1021 1022 /* 1023 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1024 * twice 1025 */ 1026 static int 1027 bfe_setupphy(struct bfe_softc *sc) 1028 { 1029 uint32_t val; 1030 1031 /* Enable activity LED */ 1032 bfe_readphy(sc, 26, &val); 1033 bfe_writephy(sc, 26, val & 0x7fff); 1034 bfe_readphy(sc, 26, &val); 1035 1036 /* Enable traffic meter LED mode */ 1037 bfe_readphy(sc, 27, &val); 1038 bfe_writephy(sc, 27, val | (1 << 6)); 1039 1040 return(0); 1041 } 1042 1043 static void 1044 bfe_stats_update(struct bfe_softc *sc) 1045 { 1046 u_long reg; 1047 uint32_t *val; 1048 1049 val = &sc->bfe_hwstats.tx_good_octets; 1050 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1051 *val++ += CSR_READ_4(sc, reg); 1052 val = &sc->bfe_hwstats.rx_good_octets; 1053 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1054 *val++ += CSR_READ_4(sc, reg); 1055 } 1056 1057 static void 1058 bfe_txeof(struct bfe_softc *sc) 1059 { 1060 struct ifnet *ifp = &sc->arpcom.ac_if; 1061 uint32_t i, chipidx; 1062 1063 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1064 chipidx /= sizeof(struct bfe_desc); 1065 1066 i = sc->bfe_tx_cons; 1067 1068 /* Go through the mbufs and free those that have been transmitted */ 1069 while (i != chipidx) { 1070 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1071 1072 if (r->bfe_mbuf != NULL) { 1073 IFNET_STAT_INC(ifp, opackets, 1); 1074 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map); 1075 m_freem(r->bfe_mbuf); 1076 r->bfe_mbuf = NULL; 1077 } 1078 1079 KKASSERT(sc->bfe_tx_cnt > 0); 1080 sc->bfe_tx_cnt--; 1081 BFE_INC(i, BFE_TX_LIST_CNT); 1082 } 1083 1084 if (i != sc->bfe_tx_cons) { 1085 sc->bfe_tx_cons = i; 1086 1087 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT) 1088 ifq_clr_oactive(&ifp->if_snd); 1089 } 1090 if (sc->bfe_tx_cnt == 0) 1091 ifp->if_timer = 0; 1092 } 1093 1094 /* Pass a received packet up the stack */ 1095 static void 1096 bfe_rxeof(struct bfe_softc *sc) 1097 { 1098 struct ifnet *ifp = &sc->arpcom.ac_if; 1099 struct mbuf *m; 1100 struct bfe_rxheader *rxheader; 1101 struct bfe_data *r; 1102 uint32_t cons, status, current, len, flags; 1103 1104 cons = sc->bfe_rx_cons; 1105 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1106 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1107 1108 while (current != cons) { 1109 r = &sc->bfe_rx_ring[cons]; 1110 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, 1111 BUS_DMASYNC_POSTREAD); 1112 1113 KKASSERT(r->bfe_mbuf != NULL); 1114 m = r->bfe_mbuf; 1115 rxheader = mtod(m, struct bfe_rxheader*); 1116 len = rxheader->len - ETHER_CRC_LEN; 1117 flags = rxheader->flags; 1118 1119 /* flag an error and try again */ 1120 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) { 1121 IFNET_STAT_INC(ifp, ierrors, 1); 1122 if (flags & BFE_RX_FLAG_SERR) 1123 IFNET_STAT_INC(ifp, collisions, 1); 1124 1125 bfe_setup_rxdesc(sc, cons); 1126 BFE_INC(cons, BFE_RX_LIST_CNT); 1127 continue; 1128 } 1129 1130 /* Go past the rx header */ 1131 if (bfe_newbuf(sc, cons, 0) != 0) { 1132 bfe_setup_rxdesc(sc, cons); 1133 IFNET_STAT_INC(ifp, ierrors, 1); 1134 BFE_INC(cons, BFE_RX_LIST_CNT); 1135 continue; 1136 } 1137 1138 m_adj(m, BFE_RX_OFFSET); 1139 m->m_len = m->m_pkthdr.len = len; 1140 1141 IFNET_STAT_INC(ifp, ipackets, 1); 1142 m->m_pkthdr.rcvif = ifp; 1143 1144 ifp->if_input(ifp, m, NULL, -1); 1145 BFE_INC(cons, BFE_RX_LIST_CNT); 1146 } 1147 1148 sc->bfe_rx_cons = cons; 1149 } 1150 1151 static void 1152 bfe_intr(void *xsc) 1153 { 1154 struct bfe_softc *sc = xsc; 1155 struct ifnet *ifp = &sc->arpcom.ac_if; 1156 uint32_t istat, imask, flag; 1157 1158 istat = CSR_READ_4(sc, BFE_ISTAT); 1159 imask = CSR_READ_4(sc, BFE_IMASK); 1160 1161 /* 1162 * Defer unsolicited interrupts - This is necessary because setting the 1163 * chips interrupt mask register to 0 doesn't actually stop the 1164 * interrupts 1165 */ 1166 istat &= imask; 1167 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1168 CSR_READ_4(sc, BFE_ISTAT); 1169 1170 /* not expecting this interrupt, disregard it */ 1171 if (istat == 0) { 1172 return; 1173 } 1174 1175 if (istat & BFE_ISTAT_ERRORS) { 1176 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1177 if (flag & BFE_STAT_EMASK) 1178 IFNET_STAT_INC(ifp, oerrors, 1); 1179 1180 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1181 if (flag & BFE_RX_FLAG_ERRORS) 1182 IFNET_STAT_INC(ifp, ierrors, 1); 1183 1184 ifp->if_flags &= ~IFF_RUNNING; 1185 bfe_init(sc); 1186 } 1187 1188 /* A packet was received */ 1189 if (istat & BFE_ISTAT_RX) 1190 bfe_rxeof(sc); 1191 1192 /* A packet was sent */ 1193 if (istat & BFE_ISTAT_TX) 1194 bfe_txeof(sc); 1195 1196 /* We have packets pending, fire them out */ 1197 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1198 if_devstart(ifp); 1199 } 1200 1201 static int 1202 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1203 { 1204 bus_dma_segment_t segs[BFE_MAXSEGS]; 1205 bus_dmamap_t map; 1206 int i, first_idx, last_idx, cur, error, maxsegs, nsegs; 1207 1208 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT); 1209 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC; 1210 if (maxsegs > BFE_MAXSEGS) 1211 maxsegs = BFE_MAXSEGS; 1212 1213 first_idx = *txidx; 1214 map = sc->bfe_tx_ring[first_idx].bfe_map; 1215 1216 error = bus_dmamap_load_mbuf_defrag(sc->bfe_txbuf_tag, map, m_head, 1217 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1218 if (error) 1219 goto fail; 1220 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE); 1221 1222 last_idx = -1; 1223 cur = first_idx; 1224 for (i = 0; i < nsegs; ++i) { 1225 struct bfe_desc *d; 1226 uint32_t ctrl; 1227 1228 ctrl = BFE_DESC_LEN & segs[i].ds_len; 1229 ctrl |= BFE_DESC_IOC; /* always interrupt */ 1230 if (cur == BFE_TX_LIST_CNT - 1) { 1231 /* 1232 * Tell the chip to wrap to the 1233 * start of the descriptor list. 1234 */ 1235 ctrl |= BFE_DESC_EOT; 1236 } 1237 1238 d = &sc->bfe_tx_list[cur]; 1239 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA; 1240 d->bfe_ctrl = ctrl; 1241 1242 last_idx = cur; 1243 BFE_INC(cur, BFE_TX_LIST_CNT); 1244 } 1245 KKASSERT(last_idx >= 0); 1246 1247 /* End of the frame */ 1248 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF; 1249 1250 /* 1251 * Set start of the frame on the first fragment, 1252 * _after_ all of the fragments are setup. 1253 */ 1254 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF; 1255 1256 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map; 1257 sc->bfe_tx_ring[last_idx].bfe_map = map; 1258 sc->bfe_tx_ring[last_idx].bfe_mbuf = *m_head; 1259 1260 *txidx = cur; 1261 sc->bfe_tx_cnt += nsegs; 1262 return 0; 1263 fail: 1264 m_freem(*m_head); 1265 *m_head = NULL; 1266 return error; 1267 } 1268 1269 /* 1270 * Set up to transmit a packet 1271 */ 1272 static void 1273 bfe_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1274 { 1275 struct bfe_softc *sc = ifp->if_softc; 1276 struct mbuf *m_head = NULL; 1277 int idx, need_trans; 1278 1279 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1280 ASSERT_SERIALIZED(ifp->if_serializer); 1281 1282 /* 1283 * Not much point trying to send if the link is down 1284 * or we have nothing to send. 1285 */ 1286 if (!sc->bfe_link) { 1287 ifq_purge(&ifp->if_snd); 1288 return; 1289 } 1290 1291 if (ifq_is_oactive(&ifp->if_snd)) 1292 return; 1293 1294 idx = sc->bfe_tx_prod; 1295 1296 need_trans = 0; 1297 while (!ifq_is_empty(&ifp->if_snd)) { 1298 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) { 1299 ifq_set_oactive(&ifp->if_snd); 1300 break; 1301 } 1302 1303 m_head = ifq_dequeue(&ifp->if_snd); 1304 if (m_head == NULL) 1305 break; 1306 1307 /* 1308 * Pack the data into the tx ring. If we don't have 1309 * enough room, let the chip drain the ring. 1310 */ 1311 if (bfe_encap(sc, &m_head, &idx)) { 1312 /* m_head is freed by re_encap(), if we reach here */ 1313 IFNET_STAT_INC(ifp, oerrors, 1); 1314 1315 if (sc->bfe_tx_cnt > 0) { 1316 ifq_set_oactive(&ifp->if_snd); 1317 break; 1318 } else { 1319 /* 1320 * ifq_set_oactive could not be called under 1321 * this situation, since except up/down, 1322 * nothing will call ifq_clr_oactive. 1323 * 1324 * Let's just keep draining the ifq ... 1325 */ 1326 continue; 1327 } 1328 } 1329 need_trans = 1; 1330 1331 /* 1332 * If there's a BPF listener, bounce a copy of this frame 1333 * to him. 1334 */ 1335 BPF_MTAP(ifp, m_head); 1336 } 1337 1338 if (!need_trans) 1339 return; 1340 1341 sc->bfe_tx_prod = idx; 1342 1343 /* Transmit - twice due to apparent hardware bug */ 1344 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1345 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1346 1347 /* 1348 * Set a timeout in case the chip goes out to lunch. 1349 */ 1350 ifp->if_timer = 5; 1351 } 1352 1353 static void 1354 bfe_init(void *xsc) 1355 { 1356 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1357 struct ifnet *ifp = &sc->arpcom.ac_if; 1358 1359 ASSERT_SERIALIZED(ifp->if_serializer); 1360 1361 if (ifp->if_flags & IFF_RUNNING) 1362 return; 1363 1364 bfe_stop(sc); 1365 bfe_chip_reset(sc); 1366 1367 if (bfe_list_rx_init(sc) == ENOBUFS) { 1368 if_printf(ifp, "bfe_init failed. " 1369 " Not enough memory for list buffers\n"); 1370 bfe_stop(sc); 1371 return; 1372 } 1373 1374 bfe_set_rx_mode(sc); 1375 1376 /* Enable the chip and core */ 1377 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1378 /* Enable interrupts */ 1379 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1380 1381 bfe_ifmedia_upd(ifp); 1382 ifp->if_flags |= IFF_RUNNING; 1383 ifq_clr_oactive(&ifp->if_snd); 1384 1385 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1386 } 1387 1388 /* 1389 * Set media options. 1390 */ 1391 static int 1392 bfe_ifmedia_upd(struct ifnet *ifp) 1393 { 1394 struct bfe_softc *sc = ifp->if_softc; 1395 struct mii_data *mii; 1396 1397 ASSERT_SERIALIZED(ifp->if_serializer); 1398 1399 mii = device_get_softc(sc->bfe_miibus); 1400 sc->bfe_link = 0; 1401 if (mii->mii_instance) { 1402 struct mii_softc *miisc; 1403 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1404 miisc = LIST_NEXT(miisc, mii_list)) 1405 mii_phy_reset(miisc); 1406 } 1407 mii_mediachg(mii); 1408 1409 bfe_setupphy(sc); 1410 1411 return(0); 1412 } 1413 1414 /* 1415 * Report current media status. 1416 */ 1417 static void 1418 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1419 { 1420 struct bfe_softc *sc = ifp->if_softc; 1421 struct mii_data *mii; 1422 1423 ASSERT_SERIALIZED(ifp->if_serializer); 1424 1425 mii = device_get_softc(sc->bfe_miibus); 1426 mii_pollstat(mii); 1427 ifmr->ifm_active = mii->mii_media_active; 1428 ifmr->ifm_status = mii->mii_media_status; 1429 } 1430 1431 static int 1432 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1433 { 1434 struct bfe_softc *sc = ifp->if_softc; 1435 struct ifreq *ifr = (struct ifreq *) data; 1436 struct mii_data *mii; 1437 int error = 0; 1438 1439 ASSERT_SERIALIZED(ifp->if_serializer); 1440 1441 switch (command) { 1442 case SIOCSIFFLAGS: 1443 if (ifp->if_flags & IFF_UP) 1444 if (ifp->if_flags & IFF_RUNNING) 1445 bfe_set_rx_mode(sc); 1446 else 1447 bfe_init(sc); 1448 else if (ifp->if_flags & IFF_RUNNING) 1449 bfe_stop(sc); 1450 break; 1451 case SIOCADDMULTI: 1452 case SIOCDELMULTI: 1453 if (ifp->if_flags & IFF_RUNNING) 1454 bfe_set_rx_mode(sc); 1455 break; 1456 case SIOCGIFMEDIA: 1457 case SIOCSIFMEDIA: 1458 mii = device_get_softc(sc->bfe_miibus); 1459 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1460 command); 1461 break; 1462 default: 1463 error = ether_ioctl(ifp, command, data); 1464 break; 1465 } 1466 return error; 1467 } 1468 1469 static void 1470 bfe_watchdog(struct ifnet *ifp) 1471 { 1472 struct bfe_softc *sc = ifp->if_softc; 1473 1474 ASSERT_SERIALIZED(ifp->if_serializer); 1475 1476 if_printf(ifp, "watchdog timeout -- resetting\n"); 1477 1478 ifp->if_flags &= ~IFF_RUNNING; 1479 bfe_init(sc); 1480 1481 IFNET_STAT_INC(ifp, oerrors, 1); 1482 } 1483 1484 static void 1485 bfe_tick(void *xsc) 1486 { 1487 struct bfe_softc *sc = xsc; 1488 struct mii_data *mii; 1489 struct ifnet *ifp = &sc->arpcom.ac_if; 1490 1491 mii = device_get_softc(sc->bfe_miibus); 1492 1493 lwkt_serialize_enter(ifp->if_serializer); 1494 1495 bfe_stats_update(sc); 1496 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1497 1498 if (sc->bfe_link == 0) { 1499 mii_tick(mii); 1500 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1501 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1502 sc->bfe_link++; 1503 } 1504 if (!sc->bfe_link) 1505 sc->bfe_link++; 1506 } 1507 lwkt_serialize_exit(ifp->if_serializer); 1508 } 1509 1510 /* 1511 * Stop the adapter and free any mbufs allocated to the 1512 * RX and TX lists. 1513 */ 1514 static void 1515 bfe_stop(struct bfe_softc *sc) 1516 { 1517 struct ifnet *ifp = &sc->arpcom.ac_if; 1518 1519 ASSERT_SERIALIZED(ifp->if_serializer); 1520 1521 callout_stop(&sc->bfe_stat_timer); 1522 1523 bfe_chip_halt(sc); 1524 bfe_tx_ring_free(sc); 1525 bfe_rx_ring_free(sc); 1526 1527 ifp->if_flags &= ~IFF_RUNNING; 1528 ifq_clr_oactive(&ifp->if_snd); 1529 } 1530