1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.31 2007/07/14 08:01:24 sephe Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/rman.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 54 #include <net/bpf.h> 55 56 #include <net/if_types.h> 57 #include <net/vlan/if_vlan_var.h> 58 59 #include <netinet/in_systm.h> 60 #include <netinet/in.h> 61 #include <netinet/ip.h> 62 63 #include <bus/pci/pcireg.h> 64 #include <bus/pci/pcivar.h> 65 #include <bus/pci/pcidevs.h> 66 67 #include <dev/netif/mii_layer/mii.h> 68 #include <dev/netif/mii_layer/miivar.h> 69 70 #include "if_bfereg.h" 71 72 MODULE_DEPEND(bfe, pci, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "controller miibus0" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe(device_t); 89 static int bfe_attach(device_t); 90 static int bfe_detach(device_t); 91 static void bfe_intr(void *); 92 static void bfe_start(struct ifnet *); 93 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 94 static void bfe_init(void *); 95 static void bfe_stop(struct bfe_softc *); 96 static void bfe_watchdog(struct ifnet *); 97 static void bfe_shutdown(device_t); 98 static void bfe_tick(void *); 99 static void bfe_txeof(struct bfe_softc *); 100 static void bfe_rxeof(struct bfe_softc *); 101 static void bfe_set_rx_mode(struct bfe_softc *); 102 static int bfe_list_rx_init(struct bfe_softc *); 103 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 104 static void bfe_rx_ring_free(struct bfe_softc *); 105 106 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 107 static int bfe_ifmedia_upd(struct ifnet *); 108 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 static int bfe_miibus_readreg(device_t, int, int); 110 static int bfe_miibus_writereg(device_t, int, int, int); 111 static void bfe_miibus_statchg(device_t); 112 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 113 u_long, const int); 114 static void bfe_get_config(struct bfe_softc *sc); 115 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 116 static void bfe_stats_update(struct bfe_softc *); 117 static void bfe_clear_stats (struct bfe_softc *); 118 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 119 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 120 static int bfe_resetphy(struct bfe_softc *); 121 static int bfe_setupphy(struct bfe_softc *); 122 static void bfe_chip_reset(struct bfe_softc *); 123 static void bfe_chip_halt(struct bfe_softc *); 124 static void bfe_core_reset(struct bfe_softc *); 125 static void bfe_core_disable(struct bfe_softc *); 126 static int bfe_dma_alloc(device_t); 127 static void bfe_dma_free(struct bfe_softc *); 128 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 129 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 130 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 131 132 static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 139 /* bus interface */ 140 DEVMETHOD(bus_print_child, bus_generic_print_child), 141 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142 143 /* MII interface */ 144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 147 148 { 0, 0 } 149 }; 150 151 static driver_t bfe_driver = { 152 "bfe", 153 bfe_methods, 154 sizeof(struct bfe_softc) 155 }; 156 157 static devclass_t bfe_devclass; 158 159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 160 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 161 162 /* 163 * Probe for a Broadcom 4401 chip. 164 */ 165 static int 166 bfe_probe(device_t dev) 167 { 168 struct bfe_type *t; 169 uint16_t vendor, product; 170 171 vendor = pci_get_vendor(dev); 172 product = pci_get_device(dev); 173 174 for (t = bfe_devs; t->bfe_name != NULL; t++) { 175 if (vendor == t->bfe_vid && product == t->bfe_did) { 176 device_set_desc(dev, t->bfe_name); 177 return(0); 178 } 179 } 180 181 return(ENXIO); 182 } 183 184 static int 185 bfe_dma_alloc(device_t dev) 186 { 187 struct bfe_softc *sc = device_get_softc(dev); 188 int error, i, tx_pos, rx_pos; 189 190 /* 191 * parent tag. Apparently the chip cannot handle any DMA address 192 * greater than 1GB. 193 */ 194 error = bus_dma_tag_create(NULL, /* parent */ 195 4096, 0, /* alignment, boundary */ 196 0x3FFFFFFF, /* lowaddr */ 197 BUS_SPACE_MAXADDR, /* highaddr */ 198 NULL, NULL, /* filter, filterarg */ 199 MAXBSIZE, /* maxsize */ 200 BUS_SPACE_UNRESTRICTED, /* num of segments */ 201 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 202 0, /* flags */ 203 &sc->bfe_parent_tag); 204 if (error) { 205 device_printf(dev, "could not allocate parent dma tag\n"); 206 return(error); 207 } 208 209 /* tag for TX ring */ 210 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0, 211 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 212 NULL, NULL, 213 BFE_TX_LIST_SIZE, 1, 214 BUS_SPACE_MAXSIZE_32BIT, 215 0, &sc->bfe_tx_tag); 216 if (error) { 217 device_printf(dev, "could not allocate dma tag for TX list\n"); 218 return(error); 219 } 220 221 /* tag for RX ring */ 222 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0, 223 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 224 NULL, NULL, 225 BFE_RX_LIST_SIZE, 1, 226 BUS_SPACE_MAXSIZE_32BIT, 227 0, &sc->bfe_rx_tag); 228 if (error) { 229 device_printf(dev, "could not allocate dma tag for RX list\n"); 230 return(error); 231 } 232 233 /* tag for mbufs */ 234 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 235 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 236 NULL, NULL, 237 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT, 238 BUS_DMA_ALLOCNOW, &sc->bfe_tag); 239 if (error) { 240 device_printf(dev, "could not allocate dma tag for mbufs\n"); 241 return(error); 242 } 243 244 rx_pos = tx_pos = 0; 245 246 /* pre allocate dmamaps for RX list */ 247 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 248 error = bus_dmamap_create(sc->bfe_tag, 0, 249 &sc->bfe_rx_ring[i].bfe_map); 250 if (error) { 251 rx_pos = i; 252 device_printf(dev, "cannot create DMA map for RX\n"); 253 goto ring_fail; 254 } 255 } 256 rx_pos = BFE_RX_LIST_CNT; 257 258 /* pre allocate dmamaps for TX list */ 259 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 260 error = bus_dmamap_create(sc->bfe_tag, 0, 261 &sc->bfe_tx_ring[i].bfe_map); 262 if (error) { 263 tx_pos = i; 264 device_printf(dev, "cannot create DMA map for TX\n"); 265 goto ring_fail; 266 } 267 } 268 269 /* Alloc dma for rx ring */ 270 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 271 BUS_DMA_WAITOK | BUS_DMA_ZERO, 272 &sc->bfe_rx_map); 273 if (error) { 274 device_printf(dev, "cannot allocate DMA mem for RX\n"); 275 return(error); 276 } 277 278 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 279 sc->bfe_rx_list, sizeof(struct bfe_desc), 280 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK); 281 if (error) { 282 device_printf(dev, "cannot load DMA map for RX\n"); 283 return(error); 284 } 285 286 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 287 288 /* Alloc dma for tx ring */ 289 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 290 BUS_DMA_WAITOK | BUS_DMA_ZERO, 291 &sc->bfe_tx_map); 292 if (error) { 293 device_printf(dev, "cannot allocate DMA mem for TX\n"); 294 return(error); 295 } 296 297 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 298 sc->bfe_tx_list, sizeof(struct bfe_desc), 299 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK); 300 if (error) { 301 device_printf(dev, "cannot load DMA map for TX\n"); 302 return(error); 303 } 304 305 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 306 307 return(0); 308 309 ring_fail: 310 for (i = 0; i < rx_pos; ++i) 311 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map); 312 for (i = 0; i < tx_pos; ++i) 313 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 314 315 bus_dma_tag_destroy(sc->bfe_tag); 316 sc->bfe_tag = NULL; 317 return error; 318 } 319 320 static int 321 bfe_attach(device_t dev) 322 { 323 struct ifnet *ifp; 324 struct bfe_softc *sc; 325 int error = 0, rid; 326 327 sc = device_get_softc(dev); 328 329 sc->bfe_dev = dev; 330 callout_init(&sc->bfe_stat_timer); 331 332 /* 333 * Handle power management nonsense. 334 */ 335 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 336 uint32_t membase, irq; 337 338 /* Save important PCI config data. */ 339 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 340 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 341 342 /* Reset the power state. */ 343 device_printf(dev, "chip is in D%d power mode" 344 " -- setting to D0\n", pci_get_powerstate(dev)); 345 346 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 347 348 /* Restore PCI config data. */ 349 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 350 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 351 } 352 353 /* 354 * Map control/status registers. 355 */ 356 pci_enable_busmaster(dev); 357 358 rid = BFE_PCI_MEMLO; 359 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 360 RF_ACTIVE); 361 if (sc->bfe_res == NULL) { 362 device_printf(dev, "couldn't map memory\n"); 363 return ENXIO; 364 } 365 366 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 367 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 368 369 /* Allocate interrupt */ 370 rid = 0; 371 372 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 373 RF_SHAREABLE | RF_ACTIVE); 374 if (sc->bfe_irq == NULL) { 375 device_printf(dev, "couldn't map interrupt\n"); 376 error = ENXIO; 377 goto fail; 378 } 379 380 error = bfe_dma_alloc(dev); 381 if (error != 0) { 382 device_printf(dev, "failed to allocate DMA resources\n"); 383 goto fail; 384 } 385 386 /* Set up ifnet structure */ 387 ifp = &sc->arpcom.ac_if; 388 ifp->if_softc = sc; 389 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 390 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 391 ifp->if_ioctl = bfe_ioctl; 392 ifp->if_start = bfe_start; 393 ifp->if_watchdog = bfe_watchdog; 394 ifp->if_init = bfe_init; 395 ifp->if_mtu = ETHERMTU; 396 ifp->if_baudrate = 100000000; 397 ifp->if_capabilities |= IFCAP_VLAN_MTU; 398 ifp->if_capenable |= IFCAP_VLAN_MTU; 399 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 400 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 401 ifq_set_ready(&ifp->if_snd); 402 403 bfe_get_config(sc); 404 405 /* Reset the chip and turn on the PHY */ 406 bfe_chip_reset(sc); 407 408 if (mii_phy_probe(dev, &sc->bfe_miibus, 409 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 410 device_printf(dev, "MII without any PHY!\n"); 411 error = ENXIO; 412 goto fail; 413 } 414 415 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 416 417 /* 418 * Hook interrupt last to avoid having to lock softc 419 */ 420 error = bus_setup_intr(dev, sc->bfe_irq, INTR_NETSAFE, 421 bfe_intr, sc, &sc->bfe_intrhand, 422 sc->arpcom.ac_if.if_serializer); 423 424 if (error) { 425 ether_ifdetach(ifp); 426 device_printf(dev, "couldn't set up irq\n"); 427 goto fail; 428 } 429 return 0; 430 fail: 431 bfe_detach(dev); 432 return(error); 433 } 434 435 static int 436 bfe_detach(device_t dev) 437 { 438 struct bfe_softc *sc = device_get_softc(dev); 439 struct ifnet *ifp = &sc->arpcom.ac_if; 440 441 if (device_is_attached(dev)) { 442 lwkt_serialize_enter(ifp->if_serializer); 443 bfe_stop(sc); 444 bfe_chip_reset(sc); 445 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 446 lwkt_serialize_exit(ifp->if_serializer); 447 448 ether_ifdetach(ifp); 449 } 450 if (sc->bfe_miibus != NULL) 451 device_delete_child(dev, sc->bfe_miibus); 452 bus_generic_detach(dev); 453 454 if (sc->bfe_irq != NULL) 455 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 456 457 if (sc->bfe_res != NULL) { 458 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 459 sc->bfe_res); 460 } 461 bfe_dma_free(sc); 462 463 return(0); 464 } 465 466 /* 467 * Stop all chip I/O so that the kernel's probe routines don't 468 * get confused by errant DMAs when rebooting. 469 */ 470 static void 471 bfe_shutdown(device_t dev) 472 { 473 struct bfe_softc *sc = device_get_softc(dev); 474 struct ifnet *ifp = &sc->arpcom.ac_if; 475 476 lwkt_serialize_enter(ifp->if_serializer); 477 bfe_stop(sc); 478 lwkt_serialize_exit(ifp->if_serializer); 479 } 480 481 static int 482 bfe_miibus_readreg(device_t dev, int phy, int reg) 483 { 484 struct bfe_softc *sc; 485 uint32_t ret; 486 487 sc = device_get_softc(dev); 488 if (phy != sc->bfe_phyaddr) 489 return(0); 490 bfe_readphy(sc, reg, &ret); 491 492 return(ret); 493 } 494 495 static int 496 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 497 { 498 struct bfe_softc *sc; 499 500 sc = device_get_softc(dev); 501 if (phy != sc->bfe_phyaddr) 502 return(0); 503 bfe_writephy(sc, reg, val); 504 505 return(0); 506 } 507 508 static void 509 bfe_miibus_statchg(device_t dev) 510 { 511 return; 512 } 513 514 static void 515 bfe_tx_ring_free(struct bfe_softc *sc) 516 { 517 int i; 518 519 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 520 bus_dmamap_unload(sc->bfe_tag, 521 sc->bfe_tx_ring[i].bfe_map); 522 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 523 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 524 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 525 } 526 } 527 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 528 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 529 } 530 531 static void 532 bfe_rx_ring_free(struct bfe_softc *sc) 533 { 534 int i; 535 536 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 537 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 538 bus_dmamap_unload(sc->bfe_tag, 539 sc->bfe_rx_ring[i].bfe_map); 540 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 541 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 542 } 543 } 544 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 545 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 546 } 547 548 static int 549 bfe_list_rx_init(struct bfe_softc *sc) 550 { 551 int i; 552 553 for (i = 0; i < BFE_RX_LIST_CNT; i++) 554 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 555 return(ENOBUFS); 556 557 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 558 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 559 560 sc->bfe_rx_cons = 0; 561 562 return(0); 563 } 564 565 static int 566 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 567 { 568 struct bfe_rxheader *rx_header; 569 struct bfe_desc *d; 570 struct bfe_data *r; 571 uint32_t ctrl; 572 573 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 574 return(EINVAL); 575 576 if (m == NULL) { 577 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 578 if (m == NULL) 579 return(ENOBUFS); 580 m->m_len = m->m_pkthdr.len = MCLBYTES; 581 } 582 else 583 m->m_data = m->m_ext.ext_buf; 584 585 rx_header = mtod(m, struct bfe_rxheader *); 586 rx_header->len = 0; 587 rx_header->flags = 0; 588 589 /* Map the mbuf into DMA */ 590 sc->bfe_rx_cnt = c; 591 d = &sc->bfe_rx_list[c]; 592 r = &sc->bfe_rx_ring[c]; 593 /* XXX error? */ 594 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 595 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 596 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 597 598 ctrl = ETHER_MAX_LEN + 32; 599 600 if(c == BFE_RX_LIST_CNT - 1) 601 ctrl |= BFE_DESC_EOT; 602 603 d->bfe_ctrl = ctrl; 604 r->bfe_mbuf = m; 605 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 606 return(0); 607 } 608 609 static void 610 bfe_get_config(struct bfe_softc *sc) 611 { 612 uint8_t eeprom[128]; 613 614 bfe_read_eeprom(sc, eeprom); 615 616 sc->arpcom.ac_enaddr[0] = eeprom[79]; 617 sc->arpcom.ac_enaddr[1] = eeprom[78]; 618 sc->arpcom.ac_enaddr[2] = eeprom[81]; 619 sc->arpcom.ac_enaddr[3] = eeprom[80]; 620 sc->arpcom.ac_enaddr[4] = eeprom[83]; 621 sc->arpcom.ac_enaddr[5] = eeprom[82]; 622 623 sc->bfe_phyaddr = eeprom[90] & 0x1f; 624 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 625 626 sc->bfe_core_unit = 0; 627 sc->bfe_dma_offset = BFE_PCI_DMA; 628 } 629 630 static void 631 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 632 { 633 uint32_t bar_orig, pci_rev, val; 634 635 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 636 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 637 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 638 639 val = CSR_READ_4(sc, BFE_SBINTVEC); 640 val |= cores; 641 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 642 643 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 644 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 645 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 646 647 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 648 } 649 650 static void 651 bfe_clear_stats(struct bfe_softc *sc) 652 { 653 u_long reg; 654 655 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 656 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 657 CSR_READ_4(sc, reg); 658 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 659 CSR_READ_4(sc, reg); 660 } 661 662 static int 663 bfe_resetphy(struct bfe_softc *sc) 664 { 665 uint32_t val; 666 667 bfe_writephy(sc, 0, BMCR_RESET); 668 DELAY(100); 669 bfe_readphy(sc, 0, &val); 670 if (val & BMCR_RESET) { 671 if_printf(&sc->arpcom.ac_if, 672 "PHY Reset would not complete.\n"); 673 return(ENXIO); 674 } 675 return(0); 676 } 677 678 static void 679 bfe_chip_halt(struct bfe_softc *sc) 680 { 681 /* disable interrupts - not that it actually does..*/ 682 CSR_WRITE_4(sc, BFE_IMASK, 0); 683 CSR_READ_4(sc, BFE_IMASK); 684 685 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 686 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 687 688 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 689 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 690 DELAY(10); 691 } 692 693 static void 694 bfe_chip_reset(struct bfe_softc *sc) 695 { 696 uint32_t val; 697 698 /* Set the interrupt vector for the enet core */ 699 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 700 701 /* is core up? */ 702 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 703 if (val == BFE_CLOCK) { 704 /* It is, so shut it down */ 705 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 708 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 709 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 710 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 711 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 712 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 713 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 714 } 715 716 bfe_core_reset(sc); 717 bfe_clear_stats(sc); 718 719 /* 720 * We want the phy registers to be accessible even when 721 * the driver is "downed" so initialize MDC preamble, frequency, 722 * and whether internal or external phy here. 723 */ 724 725 /* 4402 has 62.5Mhz SB clock and internal phy */ 726 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 727 728 /* Internal or external PHY? */ 729 val = CSR_READ_4(sc, BFE_DEVCTRL); 730 if (!(val & BFE_IPP)) 731 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 732 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 733 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 734 DELAY(100); 735 } 736 737 /* Enable CRC32 generation and set proper LED modes */ 738 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 739 740 /* Reset or clear powerdown control bit */ 741 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 742 743 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 744 BFE_LAZY_FC_MASK)); 745 746 /* 747 * We don't want lazy interrupts, so just send them at the end of a 748 * frame, please 749 */ 750 BFE_OR(sc, BFE_RCV_LAZY, 0); 751 752 /* Set max lengths, accounting for VLAN tags */ 753 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 754 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 755 756 /* Set watermark XXX - magic */ 757 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 758 759 /* 760 * Initialise DMA channels - not forgetting dma addresses need to be 761 * added to BFE_PCI_DMA 762 */ 763 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 764 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 765 766 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 767 BFE_RX_CTRL_ENABLE); 768 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 769 770 bfe_resetphy(sc); 771 bfe_setupphy(sc); 772 } 773 774 static void 775 bfe_core_disable(struct bfe_softc *sc) 776 { 777 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 778 return; 779 780 /* 781 * Set reject, wait for it set, then wait for the core to stop being busy 782 * Then set reset and reject and enable the clocks 783 */ 784 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 785 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 786 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 787 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 788 BFE_RESET)); 789 CSR_READ_4(sc, BFE_SBTMSLOW); 790 DELAY(10); 791 /* Leave reset and reject set */ 792 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 793 DELAY(10); 794 } 795 796 static void 797 bfe_core_reset(struct bfe_softc *sc) 798 { 799 uint32_t val; 800 801 /* Disable the core */ 802 bfe_core_disable(sc); 803 804 /* and bring it back up */ 805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 806 CSR_READ_4(sc, BFE_SBTMSLOW); 807 DELAY(10); 808 809 /* Chip bug, clear SERR, IB and TO if they are set. */ 810 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 811 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 812 val = CSR_READ_4(sc, BFE_SBIMSTATE); 813 if (val & (BFE_IBE | BFE_TO)) 814 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 815 816 /* Clear reset and allow it to move through the core */ 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 818 CSR_READ_4(sc, BFE_SBTMSLOW); 819 DELAY(10); 820 821 /* Leave the clock set */ 822 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 823 CSR_READ_4(sc, BFE_SBTMSLOW); 824 DELAY(10); 825 } 826 827 static void 828 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 829 { 830 uint32_t val; 831 832 val = ((uint32_t) data[2]) << 24; 833 val |= ((uint32_t) data[3]) << 16; 834 val |= ((uint32_t) data[4]) << 8; 835 val |= ((uint32_t) data[5]); 836 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 837 val = (BFE_CAM_HI_VALID | 838 (((uint32_t) data[0]) << 8) | 839 (((uint32_t) data[1]))); 840 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 841 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 842 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 843 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 844 } 845 846 static void 847 bfe_set_rx_mode(struct bfe_softc *sc) 848 { 849 struct ifnet *ifp = &sc->arpcom.ac_if; 850 struct ifmultiaddr *ifma; 851 uint32_t val; 852 int i = 0; 853 854 val = CSR_READ_4(sc, BFE_RXCONF); 855 856 if (ifp->if_flags & IFF_PROMISC) 857 val |= BFE_RXCONF_PROMISC; 858 else 859 val &= ~BFE_RXCONF_PROMISC; 860 861 if (ifp->if_flags & IFF_BROADCAST) 862 val &= ~BFE_RXCONF_DBCAST; 863 else 864 val |= BFE_RXCONF_DBCAST; 865 866 867 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 868 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 869 870 if (ifp->if_flags & IFF_ALLMULTI) { 871 val |= BFE_RXCONF_ALLMULTI; 872 } else { 873 val &= ~BFE_RXCONF_ALLMULTI; 874 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 875 if (ifma->ifma_addr->sa_family != AF_LINK) 876 continue; 877 bfe_cam_write(sc, 878 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 879 } 880 } 881 882 CSR_WRITE_4(sc, BFE_RXCONF, val); 883 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 884 } 885 886 static void 887 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 888 { 889 uint32_t *ptr; 890 891 ptr = arg; 892 *ptr = segs->ds_addr; 893 } 894 895 static void 896 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 897 { 898 struct bfe_desc *d; 899 900 d = arg; 901 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 902 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 903 } 904 905 static void 906 bfe_dma_free(struct bfe_softc *sc) 907 { 908 if (sc->bfe_tx_tag != NULL) { 909 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 910 if (sc->bfe_tx_list != NULL) { 911 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 912 sc->bfe_tx_map); 913 sc->bfe_tx_list = NULL; 914 } 915 bus_dma_tag_destroy(sc->bfe_tx_tag); 916 sc->bfe_tx_tag = NULL; 917 } 918 919 if (sc->bfe_rx_tag != NULL) { 920 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 921 if (sc->bfe_rx_list != NULL) { 922 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 923 sc->bfe_rx_map); 924 sc->bfe_rx_list = NULL; 925 } 926 bus_dma_tag_destroy(sc->bfe_rx_tag); 927 sc->bfe_rx_tag = NULL; 928 } 929 930 if (sc->bfe_tag != NULL) { 931 int i; 932 933 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 934 bus_dmamap_destroy(sc->bfe_tag, 935 sc->bfe_tx_ring[i].bfe_map); 936 } 937 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 938 bus_dmamap_destroy(sc->bfe_tag, 939 sc->bfe_rx_ring[i].bfe_map); 940 } 941 942 bus_dma_tag_destroy(sc->bfe_tag); 943 sc->bfe_tag = NULL; 944 } 945 946 if (sc->bfe_parent_tag != NULL) { 947 bus_dma_tag_destroy(sc->bfe_parent_tag); 948 sc->bfe_parent_tag = NULL; 949 } 950 } 951 952 static void 953 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 954 { 955 long i; 956 uint16_t *ptr = (uint16_t *)data; 957 958 for (i = 0; i < 128; i += 2) 959 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 960 } 961 962 static int 963 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 964 u_long timeout, const int clear) 965 { 966 u_long i; 967 968 for (i = 0; i < timeout; i++) { 969 uint32_t val = CSR_READ_4(sc, reg); 970 971 if (clear && !(val & bit)) 972 break; 973 if (!clear && (val & bit)) 974 break; 975 DELAY(10); 976 } 977 if (i == timeout) { 978 if_printf(&sc->arpcom.ac_if, 979 "BUG! Timeout waiting for bit %08x of register " 980 "%x to %s.\n", bit, reg, 981 (clear ? "clear" : "set")); 982 return -1; 983 } 984 return 0; 985 } 986 987 static int 988 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 989 { 990 int err; 991 992 /* Clear MII ISR */ 993 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 994 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 995 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 996 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 997 (reg << BFE_MDIO_RA_SHIFT) | 998 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 999 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1000 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1001 return(err); 1002 } 1003 1004 static int 1005 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1006 { 1007 int status; 1008 1009 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1010 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1011 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1012 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1013 (reg << BFE_MDIO_RA_SHIFT) | 1014 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1015 (val & BFE_MDIO_DATA_DATA))); 1016 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1017 1018 return status; 1019 } 1020 1021 /* 1022 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1023 * twice 1024 */ 1025 static int 1026 bfe_setupphy(struct bfe_softc *sc) 1027 { 1028 uint32_t val; 1029 1030 /* Enable activity LED */ 1031 bfe_readphy(sc, 26, &val); 1032 bfe_writephy(sc, 26, val & 0x7fff); 1033 bfe_readphy(sc, 26, &val); 1034 1035 /* Enable traffic meter LED mode */ 1036 bfe_readphy(sc, 27, &val); 1037 bfe_writephy(sc, 27, val | (1 << 6)); 1038 1039 return(0); 1040 } 1041 1042 static void 1043 bfe_stats_update(struct bfe_softc *sc) 1044 { 1045 u_long reg; 1046 uint32_t *val; 1047 1048 val = &sc->bfe_hwstats.tx_good_octets; 1049 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1050 *val++ += CSR_READ_4(sc, reg); 1051 val = &sc->bfe_hwstats.rx_good_octets; 1052 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1053 *val++ += CSR_READ_4(sc, reg); 1054 } 1055 1056 static void 1057 bfe_txeof(struct bfe_softc *sc) 1058 { 1059 struct ifnet *ifp = &sc->arpcom.ac_if; 1060 uint32_t i, chipidx; 1061 1062 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1063 chipidx /= sizeof(struct bfe_desc); 1064 1065 i = sc->bfe_tx_cons; 1066 /* Go through the mbufs and free those that have been transmitted */ 1067 while (i != chipidx) { 1068 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1069 1070 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1071 if (r->bfe_mbuf != NULL) { 1072 ifp->if_opackets++; 1073 m_freem(r->bfe_mbuf); 1074 r->bfe_mbuf = NULL; 1075 } 1076 sc->bfe_tx_cnt--; 1077 BFE_INC(i, BFE_TX_LIST_CNT); 1078 } 1079 1080 if (i != sc->bfe_tx_cons) { 1081 /* we freed up some mbufs */ 1082 sc->bfe_tx_cons = i; 1083 ifp->if_flags &= ~IFF_OACTIVE; 1084 } 1085 if (sc->bfe_tx_cnt == 0) 1086 ifp->if_timer = 0; 1087 else 1088 ifp->if_timer = 5; 1089 } 1090 1091 /* Pass a received packet up the stack */ 1092 static void 1093 bfe_rxeof(struct bfe_softc *sc) 1094 { 1095 struct ifnet *ifp = &sc->arpcom.ac_if; 1096 struct mbuf *m; 1097 struct bfe_rxheader *rxheader; 1098 struct bfe_data *r; 1099 uint32_t cons, status, current, len, flags; 1100 1101 cons = sc->bfe_rx_cons; 1102 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1103 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1104 1105 while (current != cons) { 1106 r = &sc->bfe_rx_ring[cons]; 1107 m = r->bfe_mbuf; 1108 rxheader = mtod(m, struct bfe_rxheader*); 1109 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1110 len = rxheader->len; 1111 r->bfe_mbuf = NULL; 1112 1113 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1114 flags = rxheader->flags; 1115 1116 len -= ETHER_CRC_LEN; 1117 1118 /* flag an error and try again */ 1119 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1120 ifp->if_ierrors++; 1121 if (flags & BFE_RX_FLAG_SERR) 1122 ifp->if_collisions++; 1123 bfe_list_newbuf(sc, cons, m); 1124 BFE_INC(cons, BFE_RX_LIST_CNT); 1125 continue; 1126 } 1127 1128 /* Go past the rx header */ 1129 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1130 bfe_list_newbuf(sc, cons, m); 1131 BFE_INC(cons, BFE_RX_LIST_CNT); 1132 ifp->if_ierrors++; 1133 continue; 1134 } 1135 1136 m_adj(m, BFE_RX_OFFSET); 1137 m->m_len = m->m_pkthdr.len = len; 1138 1139 ifp->if_ipackets++; 1140 m->m_pkthdr.rcvif = ifp; 1141 1142 ifp->if_input(ifp, m); 1143 BFE_INC(cons, BFE_RX_LIST_CNT); 1144 } 1145 sc->bfe_rx_cons = cons; 1146 } 1147 1148 static void 1149 bfe_intr(void *xsc) 1150 { 1151 struct bfe_softc *sc = xsc; 1152 struct ifnet *ifp = &sc->arpcom.ac_if; 1153 uint32_t istat, imask, flag; 1154 1155 istat = CSR_READ_4(sc, BFE_ISTAT); 1156 imask = CSR_READ_4(sc, BFE_IMASK); 1157 1158 /* 1159 * Defer unsolicited interrupts - This is necessary because setting the 1160 * chips interrupt mask register to 0 doesn't actually stop the 1161 * interrupts 1162 */ 1163 istat &= imask; 1164 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1165 CSR_READ_4(sc, BFE_ISTAT); 1166 1167 /* not expecting this interrupt, disregard it */ 1168 if (istat == 0) { 1169 return; 1170 } 1171 1172 if (istat & BFE_ISTAT_ERRORS) { 1173 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1174 if (flag & BFE_STAT_EMASK) 1175 ifp->if_oerrors++; 1176 1177 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1178 if (flag & BFE_RX_FLAG_ERRORS) 1179 ifp->if_ierrors++; 1180 1181 ifp->if_flags &= ~IFF_RUNNING; 1182 bfe_init(sc); 1183 } 1184 1185 /* A packet was received */ 1186 if (istat & BFE_ISTAT_RX) 1187 bfe_rxeof(sc); 1188 1189 /* A packet was sent */ 1190 if (istat & BFE_ISTAT_TX) 1191 bfe_txeof(sc); 1192 1193 /* We have packets pending, fire them out */ 1194 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1195 bfe_start(ifp); 1196 } 1197 1198 static int 1199 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1200 { 1201 struct bfe_desc *d = NULL; 1202 struct bfe_data *r = NULL; 1203 struct mbuf *m; 1204 uint32_t frag, cur, cnt = 0; 1205 int error, chainlen = 0; 1206 1207 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt)); 1208 1209 /* 1210 * Count the number of frags in this chain to see if 1211 * we need to m_defrag. Since the descriptor list is shared 1212 * by all packets, we'll m_defrag long chains so that they 1213 * do not use up the entire list, even if they would fit. 1214 */ 1215 for (m = *m_head; m != NULL; m = m->m_next) 1216 chainlen++; 1217 1218 if (chainlen > (BFE_TX_LIST_CNT / 4) || 1219 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) { 1220 m = m_defrag(*m_head, MB_DONTWAIT); 1221 if (m == NULL) { 1222 m_freem(*m_head); 1223 return (ENOBUFS); 1224 } 1225 *m_head = m; 1226 } 1227 1228 /* 1229 * Start packing the mbufs in this chain into 1230 * the fragment pointers. Stop when we run out 1231 * of fragments or hit the end of the mbuf chain. 1232 */ 1233 cur = frag = *txidx; 1234 cnt = 0; 1235 1236 for (m = *m_head; m != NULL; m = m->m_next) { 1237 if (m->m_len != 0) { 1238 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt)); 1239 1240 d = &sc->bfe_tx_list[cur]; 1241 r = &sc->bfe_tx_ring[cur]; 1242 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1243 /* always intterupt on completion */ 1244 d->bfe_ctrl |= BFE_DESC_IOC; 1245 if (cnt == 0) { 1246 /* Set start of frame */ 1247 d->bfe_ctrl |= BFE_DESC_SOF; 1248 } 1249 if (cur == BFE_TX_LIST_CNT - 1) { 1250 /* 1251 * Tell the chip to wrap to the start of the 1252 * descriptor list 1253 */ 1254 d->bfe_ctrl |= BFE_DESC_EOT; 1255 } 1256 1257 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, 1258 mtod(m, void *), m->m_len, 1259 bfe_dma_map_desc, d, 1260 BUS_DMA_NOWAIT); 1261 if (error) { 1262 /* XXX This should be a fatal error. */ 1263 if_printf(&sc->arpcom.ac_if, 1264 "%s bus_dmamap_load failed: %d", 1265 __func__, error); 1266 m_freem(*m_head); 1267 return (ENOBUFS); 1268 } 1269 1270 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1271 BUS_DMASYNC_PREWRITE); 1272 1273 frag = cur; 1274 BFE_INC(cur, BFE_TX_LIST_CNT); 1275 cnt++; 1276 } 1277 } 1278 1279 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1280 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1281 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1282 1283 *txidx = cur; 1284 sc->bfe_tx_cnt += cnt; 1285 return(0); 1286 } 1287 1288 /* 1289 * Set up to transmit a packet 1290 */ 1291 static void 1292 bfe_start(struct ifnet *ifp) 1293 { 1294 struct bfe_softc *sc = ifp->if_softc; 1295 struct mbuf *m_head = NULL; 1296 int idx, need_trans; 1297 1298 /* 1299 * Not much point trying to send if the link is down 1300 * or we have nothing to send. 1301 */ 1302 if (!sc->bfe_link) 1303 return; 1304 1305 if (ifp->if_flags & IFF_OACTIVE) 1306 return; 1307 1308 idx = sc->bfe_tx_prod; 1309 1310 need_trans = 0; 1311 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1312 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) { 1313 ifp->if_flags |= IFF_OACTIVE; 1314 break; 1315 } 1316 1317 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1318 if (m_head == NULL) 1319 break; 1320 1321 /* 1322 * Pack the data into the tx ring. If we don't have 1323 * enough room, let the chip drain the ring. 1324 */ 1325 if (bfe_encap(sc, &m_head, &idx)) { 1326 ifp->if_flags |= IFF_OACTIVE; 1327 break; 1328 } 1329 need_trans = 1; 1330 1331 /* 1332 * If there's a BPF listener, bounce a copy of this frame 1333 * to him. 1334 */ 1335 BPF_MTAP(ifp, m_head); 1336 } 1337 1338 if (!need_trans) 1339 return; 1340 1341 sc->bfe_tx_prod = idx; 1342 /* Transmit - twice due to apparent hardware bug */ 1343 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1344 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1345 1346 /* 1347 * Set a timeout in case the chip goes out to lunch. 1348 */ 1349 ifp->if_timer = 5; 1350 } 1351 1352 static void 1353 bfe_init(void *xsc) 1354 { 1355 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1356 struct ifnet *ifp = &sc->arpcom.ac_if; 1357 1358 if (ifp->if_flags & IFF_RUNNING) 1359 return; 1360 1361 bfe_stop(sc); 1362 bfe_chip_reset(sc); 1363 1364 if (bfe_list_rx_init(sc) == ENOBUFS) { 1365 if_printf(ifp, "bfe_init failed. " 1366 " Not enough memory for list buffers\n"); 1367 bfe_stop(sc); 1368 return; 1369 } 1370 1371 bfe_set_rx_mode(sc); 1372 1373 /* Enable the chip and core */ 1374 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1375 /* Enable interrupts */ 1376 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1377 1378 bfe_ifmedia_upd(ifp); 1379 ifp->if_flags |= IFF_RUNNING; 1380 ifp->if_flags &= ~IFF_OACTIVE; 1381 1382 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1383 } 1384 1385 /* 1386 * Set media options. 1387 */ 1388 static int 1389 bfe_ifmedia_upd(struct ifnet *ifp) 1390 { 1391 struct bfe_softc *sc = ifp->if_softc; 1392 struct mii_data *mii; 1393 1394 mii = device_get_softc(sc->bfe_miibus); 1395 sc->bfe_link = 0; 1396 if (mii->mii_instance) { 1397 struct mii_softc *miisc; 1398 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1399 miisc = LIST_NEXT(miisc, mii_list)) 1400 mii_phy_reset(miisc); 1401 } 1402 mii_mediachg(mii); 1403 1404 bfe_setupphy(sc); 1405 1406 return(0); 1407 } 1408 1409 /* 1410 * Report current media status. 1411 */ 1412 static void 1413 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1414 { 1415 struct bfe_softc *sc = ifp->if_softc; 1416 struct mii_data *mii; 1417 1418 mii = device_get_softc(sc->bfe_miibus); 1419 mii_pollstat(mii); 1420 ifmr->ifm_active = mii->mii_media_active; 1421 ifmr->ifm_status = mii->mii_media_status; 1422 } 1423 1424 static int 1425 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1426 { 1427 struct bfe_softc *sc = ifp->if_softc; 1428 struct ifreq *ifr = (struct ifreq *) data; 1429 struct mii_data *mii; 1430 int error = 0; 1431 1432 switch (command) { 1433 case SIOCSIFFLAGS: 1434 if (ifp->if_flags & IFF_UP) 1435 if (ifp->if_flags & IFF_RUNNING) 1436 bfe_set_rx_mode(sc); 1437 else 1438 bfe_init(sc); 1439 else if (ifp->if_flags & IFF_RUNNING) 1440 bfe_stop(sc); 1441 break; 1442 case SIOCADDMULTI: 1443 case SIOCDELMULTI: 1444 if (ifp->if_flags & IFF_RUNNING) 1445 bfe_set_rx_mode(sc); 1446 break; 1447 case SIOCGIFMEDIA: 1448 case SIOCSIFMEDIA: 1449 mii = device_get_softc(sc->bfe_miibus); 1450 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1451 command); 1452 break; 1453 default: 1454 error = ether_ioctl(ifp, command, data); 1455 break; 1456 } 1457 return error; 1458 } 1459 1460 static void 1461 bfe_watchdog(struct ifnet *ifp) 1462 { 1463 struct bfe_softc *sc = ifp->if_softc; 1464 1465 if_printf(ifp, "watchdog timeout -- resetting\n"); 1466 1467 ifp->if_flags &= ~IFF_RUNNING; 1468 bfe_init(sc); 1469 1470 ifp->if_oerrors++; 1471 } 1472 1473 static void 1474 bfe_tick(void *xsc) 1475 { 1476 struct bfe_softc *sc = xsc; 1477 struct mii_data *mii; 1478 struct ifnet *ifp = &sc->arpcom.ac_if; 1479 1480 mii = device_get_softc(sc->bfe_miibus); 1481 1482 lwkt_serialize_enter(ifp->if_serializer); 1483 1484 bfe_stats_update(sc); 1485 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1486 1487 if (sc->bfe_link == NULL) { 1488 mii_tick(mii); 1489 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1490 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1491 sc->bfe_link++; 1492 } 1493 if (!sc->bfe_link) 1494 sc->bfe_link++; 1495 } 1496 lwkt_serialize_exit(ifp->if_serializer); 1497 } 1498 1499 /* 1500 * Stop the adapter and free any mbufs allocated to the 1501 * RX and TX lists. 1502 */ 1503 static void 1504 bfe_stop(struct bfe_softc *sc) 1505 { 1506 struct ifnet *ifp = &sc->arpcom.ac_if; 1507 1508 callout_stop(&sc->bfe_stat_timer); 1509 1510 bfe_chip_halt(sc); 1511 bfe_tx_ring_free(sc); 1512 bfe_rx_ring_free(sc); 1513 1514 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1515 } 1516