1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.38 2008/08/17 04:32:32 sephe Exp $ 33 */ 34 #include "opt_ethernet.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/interrupt.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/queue.h> 45 #include <sys/bus.h> 46 #include <sys/rman.h> 47 #include <sys/thread2.h> 48 49 #include <net/if.h> 50 #include <net/ifq_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 56 #include <net/bpf.h> 57 58 #include <net/if_types.h> 59 #include <net/vlan/if_vlan_var.h> 60 61 #include <netinet/in_systm.h> 62 #include <netinet/in.h> 63 #include <netinet/ip.h> 64 65 #include <bus/pci/pcireg.h> 66 #include <bus/pci/pcivar.h> 67 #include <bus/pci/pcidevs.h> 68 69 #include <dev/netif/mii_layer/mii.h> 70 #include <dev/netif/mii_layer/miivar.h> 71 72 #include <dev/netif/bfe/if_bfereg.h> 73 74 MODULE_DEPEND(bfe, pci, 1, 1, 1); 75 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 76 77 /* "controller miibus0" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 80 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 81 82 static struct bfe_type bfe_devs[] = { 83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 84 "Broadcom BCM4401 Fast Ethernet" }, 85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 86 "Broadcom BCM4401-B0 Fast Ethernet" }, 87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402, 88 "Broadcom BCM4402 Fast Ethernet" }, 89 { 0, 0, NULL } 90 }; 91 92 static int bfe_probe(device_t); 93 static int bfe_attach(device_t); 94 static int bfe_detach(device_t); 95 static void bfe_intr(void *); 96 static void bfe_start(struct ifnet *); 97 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 98 static void bfe_init(void *); 99 static void bfe_stop(struct bfe_softc *); 100 static void bfe_watchdog(struct ifnet *); 101 static void bfe_shutdown(device_t); 102 static void bfe_tick(void *); 103 static void bfe_txeof(struct bfe_softc *); 104 static void bfe_rxeof(struct bfe_softc *); 105 static void bfe_set_rx_mode(struct bfe_softc *); 106 static int bfe_list_rx_init(struct bfe_softc *); 107 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free(struct bfe_softc *); 109 110 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 111 static int bfe_ifmedia_upd(struct ifnet *); 112 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg(device_t, int, int); 114 static int bfe_miibus_writereg(device_t, int, int, int); 115 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 116 u_long, const int); 117 static void bfe_get_config(struct bfe_softc *sc); 118 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 119 static void bfe_stats_update(struct bfe_softc *); 120 static void bfe_clear_stats (struct bfe_softc *); 121 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 122 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 123 static int bfe_resetphy(struct bfe_softc *); 124 static int bfe_setupphy(struct bfe_softc *); 125 static void bfe_chip_reset(struct bfe_softc *); 126 static void bfe_chip_halt(struct bfe_softc *); 127 static void bfe_core_reset(struct bfe_softc *); 128 static void bfe_core_disable(struct bfe_softc *); 129 static int bfe_dma_alloc(device_t); 130 static void bfe_dma_free(struct bfe_softc *); 131 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 132 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 133 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 134 135 static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 148 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 uint16_t vendor, product; 172 173 vendor = pci_get_vendor(dev); 174 product = pci_get_device(dev); 175 176 for (t = bfe_devs; t->bfe_name != NULL; t++) { 177 if (vendor == t->bfe_vid && product == t->bfe_did) { 178 device_set_desc(dev, t->bfe_name); 179 return(0); 180 } 181 } 182 183 return(ENXIO); 184 } 185 186 static int 187 bfe_dma_alloc(device_t dev) 188 { 189 struct bfe_softc *sc = device_get_softc(dev); 190 int error, i, tx_pos, rx_pos; 191 192 /* 193 * parent tag. Apparently the chip cannot handle any DMA address 194 * greater than 1GB. 195 */ 196 error = bus_dma_tag_create(NULL, /* parent */ 197 4096, 0, /* alignment, boundary */ 198 0x3FFFFFFF, /* lowaddr */ 199 BUS_SPACE_MAXADDR, /* highaddr */ 200 NULL, NULL, /* filter, filterarg */ 201 MAXBSIZE, /* maxsize */ 202 BUS_SPACE_UNRESTRICTED, /* num of segments */ 203 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 204 0, /* flags */ 205 &sc->bfe_parent_tag); 206 if (error) { 207 device_printf(dev, "could not allocate parent dma tag\n"); 208 return(error); 209 } 210 211 /* tag for TX ring */ 212 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0, 213 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 214 NULL, NULL, 215 BFE_TX_LIST_SIZE, 1, 216 BUS_SPACE_MAXSIZE_32BIT, 217 0, &sc->bfe_tx_tag); 218 if (error) { 219 device_printf(dev, "could not allocate dma tag for TX list\n"); 220 return(error); 221 } 222 223 /* tag for RX ring */ 224 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0, 225 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 226 NULL, NULL, 227 BFE_RX_LIST_SIZE, 1, 228 BUS_SPACE_MAXSIZE_32BIT, 229 0, &sc->bfe_rx_tag); 230 if (error) { 231 device_printf(dev, "could not allocate dma tag for RX list\n"); 232 return(error); 233 } 234 235 /* tag for mbufs */ 236 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 238 NULL, NULL, 239 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT, 240 BUS_DMA_ALLOCNOW, &sc->bfe_tag); 241 if (error) { 242 device_printf(dev, "could not allocate dma tag for mbufs\n"); 243 return(error); 244 } 245 246 rx_pos = tx_pos = 0; 247 248 /* pre allocate dmamaps for RX list */ 249 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 250 error = bus_dmamap_create(sc->bfe_tag, 0, 251 &sc->bfe_rx_ring[i].bfe_map); 252 if (error) { 253 rx_pos = i; 254 device_printf(dev, "cannot create DMA map for RX\n"); 255 goto ring_fail; 256 } 257 } 258 rx_pos = BFE_RX_LIST_CNT; 259 260 /* pre allocate dmamaps for TX list */ 261 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 262 error = bus_dmamap_create(sc->bfe_tag, 0, 263 &sc->bfe_tx_ring[i].bfe_map); 264 if (error) { 265 tx_pos = i; 266 device_printf(dev, "cannot create DMA map for TX\n"); 267 goto ring_fail; 268 } 269 } 270 271 /* Alloc dma for rx ring */ 272 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 273 BUS_DMA_WAITOK | BUS_DMA_ZERO, 274 &sc->bfe_rx_map); 275 if (error) { 276 device_printf(dev, "cannot allocate DMA mem for RX\n"); 277 return(error); 278 } 279 280 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 281 sc->bfe_rx_list, sizeof(struct bfe_desc), 282 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK); 283 if (error) { 284 device_printf(dev, "cannot load DMA map for RX\n"); 285 return(error); 286 } 287 288 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 289 290 /* Alloc dma for tx ring */ 291 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 292 BUS_DMA_WAITOK | BUS_DMA_ZERO, 293 &sc->bfe_tx_map); 294 if (error) { 295 device_printf(dev, "cannot allocate DMA mem for TX\n"); 296 return(error); 297 } 298 299 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 300 sc->bfe_tx_list, sizeof(struct bfe_desc), 301 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK); 302 if (error) { 303 device_printf(dev, "cannot load DMA map for TX\n"); 304 return(error); 305 } 306 307 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 308 309 return(0); 310 311 ring_fail: 312 for (i = 0; i < rx_pos; ++i) 313 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map); 314 for (i = 0; i < tx_pos; ++i) 315 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 316 317 bus_dma_tag_destroy(sc->bfe_tag); 318 sc->bfe_tag = NULL; 319 return error; 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp; 326 struct bfe_softc *sc; 327 int error = 0, rid; 328 329 sc = device_get_softc(dev); 330 331 sc->bfe_dev = dev; 332 callout_init(&sc->bfe_stat_timer); 333 334 #ifndef BURN_BRIDGES 335 /* 336 * Handle power management nonsense. 337 */ 338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 339 uint32_t membase, irq; 340 341 /* Save important PCI config data. */ 342 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 343 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 344 345 /* Reset the power state. */ 346 device_printf(dev, "chip is in D%d power mode" 347 " -- setting to D0\n", pci_get_powerstate(dev)); 348 349 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 350 351 /* Restore PCI config data. */ 352 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 353 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 354 } 355 #endif /* !BURN_BRIDGE */ 356 357 /* 358 * Map control/status registers. 359 */ 360 pci_enable_busmaster(dev); 361 362 rid = BFE_PCI_MEMLO; 363 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 364 RF_ACTIVE); 365 if (sc->bfe_res == NULL) { 366 device_printf(dev, "couldn't map memory\n"); 367 return ENXIO; 368 } 369 370 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 371 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 372 373 /* Allocate interrupt */ 374 rid = 0; 375 376 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 377 RF_SHAREABLE | RF_ACTIVE); 378 if (sc->bfe_irq == NULL) { 379 device_printf(dev, "couldn't map interrupt\n"); 380 error = ENXIO; 381 goto fail; 382 } 383 384 error = bfe_dma_alloc(dev); 385 if (error != 0) { 386 device_printf(dev, "failed to allocate DMA resources\n"); 387 goto fail; 388 } 389 390 /* Set up ifnet structure */ 391 ifp = &sc->arpcom.ac_if; 392 ifp->if_softc = sc; 393 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 394 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 395 ifp->if_ioctl = bfe_ioctl; 396 ifp->if_start = bfe_start; 397 ifp->if_watchdog = bfe_watchdog; 398 ifp->if_init = bfe_init; 399 ifp->if_mtu = ETHERMTU; 400 ifp->if_baudrate = 100000000; 401 ifp->if_capabilities |= IFCAP_VLAN_MTU; 402 ifp->if_capenable |= IFCAP_VLAN_MTU; 403 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 404 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 405 ifq_set_ready(&ifp->if_snd); 406 407 bfe_get_config(sc); 408 409 /* Reset the chip and turn on the PHY */ 410 bfe_chip_reset(sc); 411 412 if (mii_phy_probe(dev, &sc->bfe_miibus, 413 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 414 device_printf(dev, "MII without any PHY!\n"); 415 error = ENXIO; 416 goto fail; 417 } 418 419 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 420 421 /* 422 * Hook interrupt last to avoid having to lock softc 423 */ 424 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE, 425 bfe_intr, sc, &sc->bfe_intrhand, 426 sc->arpcom.ac_if.if_serializer); 427 428 if (error) { 429 ether_ifdetach(ifp); 430 device_printf(dev, "couldn't set up irq\n"); 431 goto fail; 432 } 433 434 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq)); 435 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 436 return 0; 437 fail: 438 bfe_detach(dev); 439 return(error); 440 } 441 442 static int 443 bfe_detach(device_t dev) 444 { 445 struct bfe_softc *sc = device_get_softc(dev); 446 struct ifnet *ifp = &sc->arpcom.ac_if; 447 448 if (device_is_attached(dev)) { 449 lwkt_serialize_enter(ifp->if_serializer); 450 bfe_stop(sc); 451 bfe_chip_reset(sc); 452 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 453 lwkt_serialize_exit(ifp->if_serializer); 454 455 ether_ifdetach(ifp); 456 } 457 if (sc->bfe_miibus != NULL) 458 device_delete_child(dev, sc->bfe_miibus); 459 bus_generic_detach(dev); 460 461 if (sc->bfe_irq != NULL) 462 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 463 464 if (sc->bfe_res != NULL) { 465 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 466 sc->bfe_res); 467 } 468 bfe_dma_free(sc); 469 470 return(0); 471 } 472 473 /* 474 * Stop all chip I/O so that the kernel's probe routines don't 475 * get confused by errant DMAs when rebooting. 476 */ 477 static void 478 bfe_shutdown(device_t dev) 479 { 480 struct bfe_softc *sc = device_get_softc(dev); 481 struct ifnet *ifp = &sc->arpcom.ac_if; 482 483 lwkt_serialize_enter(ifp->if_serializer); 484 bfe_stop(sc); 485 lwkt_serialize_exit(ifp->if_serializer); 486 } 487 488 static int 489 bfe_miibus_readreg(device_t dev, int phy, int reg) 490 { 491 struct bfe_softc *sc; 492 uint32_t ret; 493 494 sc = device_get_softc(dev); 495 if (phy != sc->bfe_phyaddr) 496 return(0); 497 bfe_readphy(sc, reg, &ret); 498 499 return(ret); 500 } 501 502 static int 503 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 504 { 505 struct bfe_softc *sc; 506 507 sc = device_get_softc(dev); 508 if (phy != sc->bfe_phyaddr) 509 return(0); 510 bfe_writephy(sc, reg, val); 511 512 return(0); 513 } 514 515 static void 516 bfe_tx_ring_free(struct bfe_softc *sc) 517 { 518 int i; 519 520 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 521 bus_dmamap_unload(sc->bfe_tag, 522 sc->bfe_tx_ring[i].bfe_map); 523 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 524 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 525 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 526 } 527 } 528 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 529 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 530 } 531 532 static void 533 bfe_rx_ring_free(struct bfe_softc *sc) 534 { 535 int i; 536 537 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 538 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 539 bus_dmamap_unload(sc->bfe_tag, 540 sc->bfe_rx_ring[i].bfe_map); 541 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 542 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 543 } 544 } 545 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 546 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 547 } 548 549 static int 550 bfe_list_rx_init(struct bfe_softc *sc) 551 { 552 int i; 553 554 for (i = 0; i < BFE_RX_LIST_CNT; i++) 555 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 556 return(ENOBUFS); 557 558 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 559 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 560 561 sc->bfe_rx_cons = 0; 562 563 return(0); 564 } 565 566 static int 567 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 568 { 569 struct bfe_rxheader *rx_header; 570 struct bfe_desc *d; 571 struct bfe_data *r; 572 uint32_t ctrl; 573 574 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 575 return(EINVAL); 576 577 if (m == NULL) { 578 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 579 if (m == NULL) 580 return(ENOBUFS); 581 m->m_len = m->m_pkthdr.len = MCLBYTES; 582 } 583 else 584 m->m_data = m->m_ext.ext_buf; 585 586 rx_header = mtod(m, struct bfe_rxheader *); 587 rx_header->len = 0; 588 rx_header->flags = 0; 589 590 /* Map the mbuf into DMA */ 591 sc->bfe_rx_cnt = c; 592 d = &sc->bfe_rx_list[c]; 593 r = &sc->bfe_rx_ring[c]; 594 /* XXX error? */ 595 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 596 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 597 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 598 599 ctrl = ETHER_MAX_LEN + 32; 600 601 if(c == BFE_RX_LIST_CNT - 1) 602 ctrl |= BFE_DESC_EOT; 603 604 d->bfe_ctrl = ctrl; 605 r->bfe_mbuf = m; 606 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 607 return(0); 608 } 609 610 static void 611 bfe_get_config(struct bfe_softc *sc) 612 { 613 uint8_t eeprom[128]; 614 615 bfe_read_eeprom(sc, eeprom); 616 617 sc->arpcom.ac_enaddr[0] = eeprom[79]; 618 sc->arpcom.ac_enaddr[1] = eeprom[78]; 619 sc->arpcom.ac_enaddr[2] = eeprom[81]; 620 sc->arpcom.ac_enaddr[3] = eeprom[80]; 621 sc->arpcom.ac_enaddr[4] = eeprom[83]; 622 sc->arpcom.ac_enaddr[5] = eeprom[82]; 623 624 sc->bfe_phyaddr = eeprom[90] & 0x1f; 625 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 626 627 sc->bfe_core_unit = 0; 628 sc->bfe_dma_offset = BFE_PCI_DMA; 629 } 630 631 static void 632 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 633 { 634 uint32_t bar_orig, pci_rev, val; 635 636 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 637 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 638 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 639 640 val = CSR_READ_4(sc, BFE_SBINTVEC); 641 val |= cores; 642 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 643 644 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 645 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 646 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 647 648 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 649 } 650 651 static void 652 bfe_clear_stats(struct bfe_softc *sc) 653 { 654 u_long reg; 655 656 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 657 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 658 CSR_READ_4(sc, reg); 659 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 660 CSR_READ_4(sc, reg); 661 } 662 663 static int 664 bfe_resetphy(struct bfe_softc *sc) 665 { 666 uint32_t val; 667 668 bfe_writephy(sc, 0, BMCR_RESET); 669 DELAY(100); 670 bfe_readphy(sc, 0, &val); 671 if (val & BMCR_RESET) { 672 if_printf(&sc->arpcom.ac_if, 673 "PHY Reset would not complete.\n"); 674 return(ENXIO); 675 } 676 return(0); 677 } 678 679 static void 680 bfe_chip_halt(struct bfe_softc *sc) 681 { 682 /* disable interrupts - not that it actually does..*/ 683 CSR_WRITE_4(sc, BFE_IMASK, 0); 684 CSR_READ_4(sc, BFE_IMASK); 685 686 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 687 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 688 689 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 690 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 691 DELAY(10); 692 } 693 694 static void 695 bfe_chip_reset(struct bfe_softc *sc) 696 { 697 uint32_t val; 698 699 /* Set the interrupt vector for the enet core */ 700 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 701 702 /* is core up? */ 703 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 704 if (val == BFE_CLOCK) { 705 /* It is, so shut it down */ 706 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 707 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 708 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 709 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 710 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 711 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 712 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 713 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 714 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 715 } 716 717 bfe_core_reset(sc); 718 bfe_clear_stats(sc); 719 720 /* 721 * We want the phy registers to be accessible even when 722 * the driver is "downed" so initialize MDC preamble, frequency, 723 * and whether internal or external phy here. 724 */ 725 726 /* 4402 has 62.5Mhz SB clock and internal phy */ 727 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 728 729 /* Internal or external PHY? */ 730 val = CSR_READ_4(sc, BFE_DEVCTRL); 731 if (!(val & BFE_IPP)) 732 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 733 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 734 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 735 DELAY(100); 736 } 737 738 /* Enable CRC32 generation and set proper LED modes */ 739 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 740 741 /* Reset or clear powerdown control bit */ 742 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 743 744 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 745 BFE_LAZY_FC_MASK)); 746 747 /* 748 * We don't want lazy interrupts, so just send them at the end of a 749 * frame, please 750 */ 751 BFE_OR(sc, BFE_RCV_LAZY, 0); 752 753 /* Set max lengths, accounting for VLAN tags */ 754 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 755 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 756 757 /* Set watermark XXX - magic */ 758 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 759 760 /* 761 * Initialise DMA channels - not forgetting dma addresses need to be 762 * added to BFE_PCI_DMA 763 */ 764 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 765 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 766 767 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 768 BFE_RX_CTRL_ENABLE); 769 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 770 771 bfe_resetphy(sc); 772 bfe_setupphy(sc); 773 } 774 775 static void 776 bfe_core_disable(struct bfe_softc *sc) 777 { 778 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 779 return; 780 781 /* 782 * Set reject, wait for it set, then wait for the core to stop being busy 783 * Then set reset and reject and enable the clocks 784 */ 785 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 786 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 787 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 788 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 789 BFE_RESET)); 790 CSR_READ_4(sc, BFE_SBTMSLOW); 791 DELAY(10); 792 /* Leave reset and reject set */ 793 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 794 DELAY(10); 795 } 796 797 static void 798 bfe_core_reset(struct bfe_softc *sc) 799 { 800 uint32_t val; 801 802 /* Disable the core */ 803 bfe_core_disable(sc); 804 805 /* and bring it back up */ 806 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 807 CSR_READ_4(sc, BFE_SBTMSLOW); 808 DELAY(10); 809 810 /* Chip bug, clear SERR, IB and TO if they are set. */ 811 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 812 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 813 val = CSR_READ_4(sc, BFE_SBIMSTATE); 814 if (val & (BFE_IBE | BFE_TO)) 815 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 816 817 /* Clear reset and allow it to move through the core */ 818 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 819 CSR_READ_4(sc, BFE_SBTMSLOW); 820 DELAY(10); 821 822 /* Leave the clock set */ 823 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 824 CSR_READ_4(sc, BFE_SBTMSLOW); 825 DELAY(10); 826 } 827 828 static void 829 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 830 { 831 uint32_t val; 832 833 val = ((uint32_t) data[2]) << 24; 834 val |= ((uint32_t) data[3]) << 16; 835 val |= ((uint32_t) data[4]) << 8; 836 val |= ((uint32_t) data[5]); 837 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 838 val = (BFE_CAM_HI_VALID | 839 (((uint32_t) data[0]) << 8) | 840 (((uint32_t) data[1]))); 841 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 842 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 843 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 844 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 845 } 846 847 static void 848 bfe_set_rx_mode(struct bfe_softc *sc) 849 { 850 struct ifnet *ifp = &sc->arpcom.ac_if; 851 struct ifmultiaddr *ifma; 852 uint32_t val; 853 int i = 0; 854 855 val = CSR_READ_4(sc, BFE_RXCONF); 856 857 if (ifp->if_flags & IFF_PROMISC) 858 val |= BFE_RXCONF_PROMISC; 859 else 860 val &= ~BFE_RXCONF_PROMISC; 861 862 if (ifp->if_flags & IFF_BROADCAST) 863 val &= ~BFE_RXCONF_DBCAST; 864 else 865 val |= BFE_RXCONF_DBCAST; 866 867 868 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 869 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 870 871 if (ifp->if_flags & IFF_ALLMULTI) { 872 val |= BFE_RXCONF_ALLMULTI; 873 } else { 874 val &= ~BFE_RXCONF_ALLMULTI; 875 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 876 if (ifma->ifma_addr->sa_family != AF_LINK) 877 continue; 878 bfe_cam_write(sc, 879 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 880 } 881 } 882 883 CSR_WRITE_4(sc, BFE_RXCONF, val); 884 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 885 } 886 887 static void 888 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 889 { 890 uint32_t *ptr; 891 892 ptr = arg; 893 *ptr = segs->ds_addr; 894 } 895 896 static void 897 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 898 { 899 struct bfe_desc *d; 900 901 d = arg; 902 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 903 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 904 } 905 906 static void 907 bfe_dma_free(struct bfe_softc *sc) 908 { 909 if (sc->bfe_tx_tag != NULL) { 910 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 911 if (sc->bfe_tx_list != NULL) { 912 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 913 sc->bfe_tx_map); 914 sc->bfe_tx_list = NULL; 915 } 916 bus_dma_tag_destroy(sc->bfe_tx_tag); 917 sc->bfe_tx_tag = NULL; 918 } 919 920 if (sc->bfe_rx_tag != NULL) { 921 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 922 if (sc->bfe_rx_list != NULL) { 923 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 924 sc->bfe_rx_map); 925 sc->bfe_rx_list = NULL; 926 } 927 bus_dma_tag_destroy(sc->bfe_rx_tag); 928 sc->bfe_rx_tag = NULL; 929 } 930 931 if (sc->bfe_tag != NULL) { 932 int i; 933 934 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 935 bus_dmamap_destroy(sc->bfe_tag, 936 sc->bfe_tx_ring[i].bfe_map); 937 } 938 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 939 bus_dmamap_destroy(sc->bfe_tag, 940 sc->bfe_rx_ring[i].bfe_map); 941 } 942 943 bus_dma_tag_destroy(sc->bfe_tag); 944 sc->bfe_tag = NULL; 945 } 946 947 if (sc->bfe_parent_tag != NULL) { 948 bus_dma_tag_destroy(sc->bfe_parent_tag); 949 sc->bfe_parent_tag = NULL; 950 } 951 } 952 953 static void 954 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 955 { 956 long i; 957 uint16_t *ptr = (uint16_t *)data; 958 959 for (i = 0; i < 128; i += 2) 960 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 961 } 962 963 static int 964 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 965 u_long timeout, const int clear) 966 { 967 u_long i; 968 969 for (i = 0; i < timeout; i++) { 970 uint32_t val = CSR_READ_4(sc, reg); 971 972 if (clear && !(val & bit)) 973 break; 974 if (!clear && (val & bit)) 975 break; 976 DELAY(10); 977 } 978 if (i == timeout) { 979 if_printf(&sc->arpcom.ac_if, 980 "BUG! Timeout waiting for bit %08x of register " 981 "%x to %s.\n", bit, reg, 982 (clear ? "clear" : "set")); 983 return -1; 984 } 985 return 0; 986 } 987 988 static int 989 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 990 { 991 int err; 992 993 /* Clear MII ISR */ 994 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 995 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 996 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 997 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 998 (reg << BFE_MDIO_RA_SHIFT) | 999 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1000 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1001 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1002 return(err); 1003 } 1004 1005 static int 1006 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1007 { 1008 int status; 1009 1010 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1011 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1012 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1013 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1014 (reg << BFE_MDIO_RA_SHIFT) | 1015 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1016 (val & BFE_MDIO_DATA_DATA))); 1017 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1018 1019 return status; 1020 } 1021 1022 /* 1023 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1024 * twice 1025 */ 1026 static int 1027 bfe_setupphy(struct bfe_softc *sc) 1028 { 1029 uint32_t val; 1030 1031 /* Enable activity LED */ 1032 bfe_readphy(sc, 26, &val); 1033 bfe_writephy(sc, 26, val & 0x7fff); 1034 bfe_readphy(sc, 26, &val); 1035 1036 /* Enable traffic meter LED mode */ 1037 bfe_readphy(sc, 27, &val); 1038 bfe_writephy(sc, 27, val | (1 << 6)); 1039 1040 return(0); 1041 } 1042 1043 static void 1044 bfe_stats_update(struct bfe_softc *sc) 1045 { 1046 u_long reg; 1047 uint32_t *val; 1048 1049 val = &sc->bfe_hwstats.tx_good_octets; 1050 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1051 *val++ += CSR_READ_4(sc, reg); 1052 val = &sc->bfe_hwstats.rx_good_octets; 1053 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1054 *val++ += CSR_READ_4(sc, reg); 1055 } 1056 1057 static void 1058 bfe_txeof(struct bfe_softc *sc) 1059 { 1060 struct ifnet *ifp = &sc->arpcom.ac_if; 1061 uint32_t i, chipidx; 1062 1063 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1064 chipidx /= sizeof(struct bfe_desc); 1065 1066 i = sc->bfe_tx_cons; 1067 /* Go through the mbufs and free those that have been transmitted */ 1068 while (i != chipidx) { 1069 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1070 1071 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1072 if (r->bfe_mbuf != NULL) { 1073 ifp->if_opackets++; 1074 m_freem(r->bfe_mbuf); 1075 r->bfe_mbuf = NULL; 1076 } 1077 sc->bfe_tx_cnt--; 1078 BFE_INC(i, BFE_TX_LIST_CNT); 1079 } 1080 1081 if (i != sc->bfe_tx_cons) { 1082 /* we freed up some mbufs */ 1083 sc->bfe_tx_cons = i; 1084 ifp->if_flags &= ~IFF_OACTIVE; 1085 } 1086 if (sc->bfe_tx_cnt == 0) 1087 ifp->if_timer = 0; 1088 else 1089 ifp->if_timer = 5; 1090 } 1091 1092 /* Pass a received packet up the stack */ 1093 static void 1094 bfe_rxeof(struct bfe_softc *sc) 1095 { 1096 struct ifnet *ifp = &sc->arpcom.ac_if; 1097 struct mbuf *m; 1098 struct bfe_rxheader *rxheader; 1099 struct bfe_data *r; 1100 uint32_t cons, status, current, len, flags; 1101 #ifdef ETHER_INPUT_CHAIN 1102 struct mbuf_chain chain[MAXCPU]; 1103 #endif 1104 1105 cons = sc->bfe_rx_cons; 1106 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1107 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1108 1109 #ifdef ETHER_INPUT_CHAIN 1110 ether_input_chain_init(chain); 1111 #endif 1112 1113 while (current != cons) { 1114 r = &sc->bfe_rx_ring[cons]; 1115 m = r->bfe_mbuf; 1116 rxheader = mtod(m, struct bfe_rxheader*); 1117 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1118 len = rxheader->len; 1119 r->bfe_mbuf = NULL; 1120 1121 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1122 flags = rxheader->flags; 1123 1124 len -= ETHER_CRC_LEN; 1125 1126 /* flag an error and try again */ 1127 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1128 ifp->if_ierrors++; 1129 if (flags & BFE_RX_FLAG_SERR) 1130 ifp->if_collisions++; 1131 bfe_list_newbuf(sc, cons, m); 1132 BFE_INC(cons, BFE_RX_LIST_CNT); 1133 continue; 1134 } 1135 1136 /* Go past the rx header */ 1137 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1138 bfe_list_newbuf(sc, cons, m); 1139 BFE_INC(cons, BFE_RX_LIST_CNT); 1140 ifp->if_ierrors++; 1141 continue; 1142 } 1143 1144 m_adj(m, BFE_RX_OFFSET); 1145 m->m_len = m->m_pkthdr.len = len; 1146 1147 ifp->if_ipackets++; 1148 m->m_pkthdr.rcvif = ifp; 1149 1150 #ifdef ETHER_INPUT_CHAIN 1151 ether_input_chain2(ifp, m, chain); 1152 #else 1153 ifp->if_input(ifp, m); 1154 #endif 1155 BFE_INC(cons, BFE_RX_LIST_CNT); 1156 } 1157 1158 #ifdef ETHER_INPUT_CHAIN 1159 ether_input_dispatch(chain); 1160 #endif 1161 1162 sc->bfe_rx_cons = cons; 1163 } 1164 1165 static void 1166 bfe_intr(void *xsc) 1167 { 1168 struct bfe_softc *sc = xsc; 1169 struct ifnet *ifp = &sc->arpcom.ac_if; 1170 uint32_t istat, imask, flag; 1171 1172 istat = CSR_READ_4(sc, BFE_ISTAT); 1173 imask = CSR_READ_4(sc, BFE_IMASK); 1174 1175 /* 1176 * Defer unsolicited interrupts - This is necessary because setting the 1177 * chips interrupt mask register to 0 doesn't actually stop the 1178 * interrupts 1179 */ 1180 istat &= imask; 1181 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1182 CSR_READ_4(sc, BFE_ISTAT); 1183 1184 /* not expecting this interrupt, disregard it */ 1185 if (istat == 0) { 1186 return; 1187 } 1188 1189 if (istat & BFE_ISTAT_ERRORS) { 1190 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1191 if (flag & BFE_STAT_EMASK) 1192 ifp->if_oerrors++; 1193 1194 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1195 if (flag & BFE_RX_FLAG_ERRORS) 1196 ifp->if_ierrors++; 1197 1198 ifp->if_flags &= ~IFF_RUNNING; 1199 bfe_init(sc); 1200 } 1201 1202 /* A packet was received */ 1203 if (istat & BFE_ISTAT_RX) 1204 bfe_rxeof(sc); 1205 1206 /* A packet was sent */ 1207 if (istat & BFE_ISTAT_TX) 1208 bfe_txeof(sc); 1209 1210 /* We have packets pending, fire them out */ 1211 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1212 if_devstart(ifp); 1213 } 1214 1215 static int 1216 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1217 { 1218 struct bfe_desc *d = NULL; 1219 struct bfe_data *r = NULL; 1220 struct mbuf *m; 1221 uint32_t frag, cur, cnt = 0; 1222 int error, chainlen = 0; 1223 1224 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt)); 1225 1226 /* 1227 * Count the number of frags in this chain to see if 1228 * we need to m_defrag. Since the descriptor list is shared 1229 * by all packets, we'll m_defrag long chains so that they 1230 * do not use up the entire list, even if they would fit. 1231 */ 1232 for (m = *m_head; m != NULL; m = m->m_next) 1233 chainlen++; 1234 1235 if (chainlen > (BFE_TX_LIST_CNT / 4) || 1236 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) { 1237 m = m_defrag(*m_head, MB_DONTWAIT); 1238 if (m == NULL) { 1239 m_freem(*m_head); 1240 return (ENOBUFS); 1241 } 1242 *m_head = m; 1243 } 1244 1245 /* 1246 * Start packing the mbufs in this chain into 1247 * the fragment pointers. Stop when we run out 1248 * of fragments or hit the end of the mbuf chain. 1249 */ 1250 cur = frag = *txidx; 1251 cnt = 0; 1252 1253 for (m = *m_head; m != NULL; m = m->m_next) { 1254 if (m->m_len != 0) { 1255 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt)); 1256 1257 d = &sc->bfe_tx_list[cur]; 1258 r = &sc->bfe_tx_ring[cur]; 1259 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1260 /* always intterupt on completion */ 1261 d->bfe_ctrl |= BFE_DESC_IOC; 1262 if (cnt == 0) { 1263 /* Set start of frame */ 1264 d->bfe_ctrl |= BFE_DESC_SOF; 1265 } 1266 if (cur == BFE_TX_LIST_CNT - 1) { 1267 /* 1268 * Tell the chip to wrap to the start of the 1269 * descriptor list 1270 */ 1271 d->bfe_ctrl |= BFE_DESC_EOT; 1272 } 1273 1274 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, 1275 mtod(m, void *), m->m_len, 1276 bfe_dma_map_desc, d, 1277 BUS_DMA_NOWAIT); 1278 if (error) { 1279 /* XXX This should be a fatal error. */ 1280 if_printf(&sc->arpcom.ac_if, 1281 "%s bus_dmamap_load failed: %d", 1282 __func__, error); 1283 m_freem(*m_head); 1284 return (ENOBUFS); 1285 } 1286 1287 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1288 BUS_DMASYNC_PREWRITE); 1289 1290 frag = cur; 1291 BFE_INC(cur, BFE_TX_LIST_CNT); 1292 cnt++; 1293 } 1294 } 1295 1296 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1297 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1298 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1299 1300 *txidx = cur; 1301 sc->bfe_tx_cnt += cnt; 1302 return(0); 1303 } 1304 1305 /* 1306 * Set up to transmit a packet 1307 */ 1308 static void 1309 bfe_start(struct ifnet *ifp) 1310 { 1311 struct bfe_softc *sc = ifp->if_softc; 1312 struct mbuf *m_head = NULL; 1313 int idx, need_trans; 1314 1315 ASSERT_SERIALIZED(ifp->if_serializer); 1316 1317 /* 1318 * Not much point trying to send if the link is down 1319 * or we have nothing to send. 1320 */ 1321 if (!sc->bfe_link) { 1322 ifq_purge(&ifp->if_snd); 1323 return; 1324 } 1325 1326 if (ifp->if_flags & IFF_OACTIVE) 1327 return; 1328 1329 idx = sc->bfe_tx_prod; 1330 1331 need_trans = 0; 1332 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1333 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) { 1334 ifp->if_flags |= IFF_OACTIVE; 1335 break; 1336 } 1337 1338 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1339 if (m_head == NULL) 1340 break; 1341 1342 /* 1343 * Pack the data into the tx ring. If we don't have 1344 * enough room, let the chip drain the ring. 1345 */ 1346 if (bfe_encap(sc, &m_head, &idx)) { 1347 ifp->if_flags |= IFF_OACTIVE; 1348 break; 1349 } 1350 need_trans = 1; 1351 1352 /* 1353 * If there's a BPF listener, bounce a copy of this frame 1354 * to him. 1355 */ 1356 BPF_MTAP(ifp, m_head); 1357 } 1358 1359 if (!need_trans) 1360 return; 1361 1362 sc->bfe_tx_prod = idx; 1363 /* Transmit - twice due to apparent hardware bug */ 1364 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1365 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1366 1367 /* 1368 * Set a timeout in case the chip goes out to lunch. 1369 */ 1370 ifp->if_timer = 5; 1371 } 1372 1373 static void 1374 bfe_init(void *xsc) 1375 { 1376 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1377 struct ifnet *ifp = &sc->arpcom.ac_if; 1378 1379 ASSERT_SERIALIZED(ifp->if_serializer); 1380 1381 if (ifp->if_flags & IFF_RUNNING) 1382 return; 1383 1384 bfe_stop(sc); 1385 bfe_chip_reset(sc); 1386 1387 if (bfe_list_rx_init(sc) == ENOBUFS) { 1388 if_printf(ifp, "bfe_init failed. " 1389 " Not enough memory for list buffers\n"); 1390 bfe_stop(sc); 1391 return; 1392 } 1393 1394 bfe_set_rx_mode(sc); 1395 1396 /* Enable the chip and core */ 1397 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1398 /* Enable interrupts */ 1399 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1400 1401 bfe_ifmedia_upd(ifp); 1402 ifp->if_flags |= IFF_RUNNING; 1403 ifp->if_flags &= ~IFF_OACTIVE; 1404 1405 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1406 } 1407 1408 /* 1409 * Set media options. 1410 */ 1411 static int 1412 bfe_ifmedia_upd(struct ifnet *ifp) 1413 { 1414 struct bfe_softc *sc = ifp->if_softc; 1415 struct mii_data *mii; 1416 1417 ASSERT_SERIALIZED(ifp->if_serializer); 1418 1419 mii = device_get_softc(sc->bfe_miibus); 1420 sc->bfe_link = 0; 1421 if (mii->mii_instance) { 1422 struct mii_softc *miisc; 1423 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1424 miisc = LIST_NEXT(miisc, mii_list)) 1425 mii_phy_reset(miisc); 1426 } 1427 mii_mediachg(mii); 1428 1429 bfe_setupphy(sc); 1430 1431 return(0); 1432 } 1433 1434 /* 1435 * Report current media status. 1436 */ 1437 static void 1438 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1439 { 1440 struct bfe_softc *sc = ifp->if_softc; 1441 struct mii_data *mii; 1442 1443 ASSERT_SERIALIZED(ifp->if_serializer); 1444 1445 mii = device_get_softc(sc->bfe_miibus); 1446 mii_pollstat(mii); 1447 ifmr->ifm_active = mii->mii_media_active; 1448 ifmr->ifm_status = mii->mii_media_status; 1449 } 1450 1451 static int 1452 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1453 { 1454 struct bfe_softc *sc = ifp->if_softc; 1455 struct ifreq *ifr = (struct ifreq *) data; 1456 struct mii_data *mii; 1457 int error = 0; 1458 1459 ASSERT_SERIALIZED(ifp->if_serializer); 1460 1461 switch (command) { 1462 case SIOCSIFFLAGS: 1463 if (ifp->if_flags & IFF_UP) 1464 if (ifp->if_flags & IFF_RUNNING) 1465 bfe_set_rx_mode(sc); 1466 else 1467 bfe_init(sc); 1468 else if (ifp->if_flags & IFF_RUNNING) 1469 bfe_stop(sc); 1470 break; 1471 case SIOCADDMULTI: 1472 case SIOCDELMULTI: 1473 if (ifp->if_flags & IFF_RUNNING) 1474 bfe_set_rx_mode(sc); 1475 break; 1476 case SIOCGIFMEDIA: 1477 case SIOCSIFMEDIA: 1478 mii = device_get_softc(sc->bfe_miibus); 1479 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1480 command); 1481 break; 1482 default: 1483 error = ether_ioctl(ifp, command, data); 1484 break; 1485 } 1486 return error; 1487 } 1488 1489 static void 1490 bfe_watchdog(struct ifnet *ifp) 1491 { 1492 struct bfe_softc *sc = ifp->if_softc; 1493 1494 ASSERT_SERIALIZED(ifp->if_serializer); 1495 1496 if_printf(ifp, "watchdog timeout -- resetting\n"); 1497 1498 ifp->if_flags &= ~IFF_RUNNING; 1499 bfe_init(sc); 1500 1501 ifp->if_oerrors++; 1502 } 1503 1504 static void 1505 bfe_tick(void *xsc) 1506 { 1507 struct bfe_softc *sc = xsc; 1508 struct mii_data *mii; 1509 struct ifnet *ifp = &sc->arpcom.ac_if; 1510 1511 mii = device_get_softc(sc->bfe_miibus); 1512 1513 lwkt_serialize_enter(ifp->if_serializer); 1514 1515 bfe_stats_update(sc); 1516 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1517 1518 if (sc->bfe_link == 0) { 1519 mii_tick(mii); 1520 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1521 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1522 sc->bfe_link++; 1523 } 1524 if (!sc->bfe_link) 1525 sc->bfe_link++; 1526 } 1527 lwkt_serialize_exit(ifp->if_serializer); 1528 } 1529 1530 /* 1531 * Stop the adapter and free any mbufs allocated to the 1532 * RX and TX lists. 1533 */ 1534 static void 1535 bfe_stop(struct bfe_softc *sc) 1536 { 1537 struct ifnet *ifp = &sc->arpcom.ac_if; 1538 1539 ASSERT_SERIALIZED(ifp->if_serializer); 1540 1541 callout_stop(&sc->bfe_stat_timer); 1542 1543 bfe_chip_halt(sc); 1544 bfe_tx_ring_free(sc); 1545 bfe_rx_ring_free(sc); 1546 1547 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1548 } 1549