1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.46 2005/08/22 18:29:52 joerg Exp $ 35 * 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include "opt_bge.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/sockio.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 #include <sys/queue.h> 85 #include <sys/thread2.h> 86 87 #include <net/if.h> 88 #include <net/ifq_var.h> 89 #include <net/if_arp.h> 90 #include <net/ethernet.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 94 #include <net/bpf.h> 95 96 #include <net/if_types.h> 97 #include <net/vlan/if_vlan_var.h> 98 99 #include <netinet/in_systm.h> 100 #include <netinet/in.h> 101 #include <netinet/ip.h> 102 103 #include <vm/vm.h> /* for vtophys */ 104 #include <vm/pmap.h> /* for vtophys */ 105 #include <machine/resource.h> 106 #include <sys/bus.h> 107 #include <sys/rman.h> 108 109 #include <dev/netif/mii_layer/mii.h> 110 #include <dev/netif/mii_layer/miivar.h> 111 #include <dev/netif/mii_layer/miidevs.h> 112 #include <dev/netif/mii_layer/brgphyreg.h> 113 114 #include <bus/pci/pcidevs.h> 115 #include <bus/pci/pcireg.h> 116 #include <bus/pci/pcivar.h> 117 118 #include "if_bgereg.h" 119 120 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 121 122 /* "controller miibus0" required. See GENERIC if you get errors here. */ 123 #include "miibus_if.h" 124 125 /* 126 * Various supported device vendors/types and their names. Note: the 127 * spec seems to indicate that the hardware still has Alteon's vendor 128 * ID burned into it, though it will always be overriden by the vendor 129 * ID in the EEPROM. Just to be safe, we cover all possibilities. 130 */ 131 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 132 133 static struct bge_type bge_devs[] = { 134 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 135 "Alteon BCM5700 Gigabit Ethernet" }, 136 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701, 137 "Alteon BCM5701 Gigabit Ethernet" }, 138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700, 139 "Broadcom BCM5700 Gigabit Ethernet" }, 140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701, 141 "Broadcom BCM5701 Gigabit Ethernet" }, 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X, 143 "Broadcom BCM5702X Gigabit Ethernet" }, 144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT, 145 "Broadcom BCM5702 Gigabit Ethernet" }, 146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X, 147 "Broadcom BCM5703X Gigabit Ethernet" }, 148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3, 149 "Broadcom BCM5703 Gigabit Ethernet" }, 150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C, 151 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S, 153 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705, 155 "Broadcom BCM5705 Gigabit Ethernet" }, 156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K, 157 "Broadcom BCM5705K Gigabit Ethernet" }, 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M, 159 "Broadcom BCM5705M Gigabit Ethernet" }, 160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 161 "Broadcom BCM5705M Gigabit Ethernet" }, 162 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5714C, 163 "Broadcom BCM5714C Gigabit Ethernet" }, 164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721, 165 "Broadcom BCM5721 Gigabit Ethernet" }, 166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750, 167 "Broadcom BCM5750 Gigabit Ethernet" }, 168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M, 169 "Broadcom BCM5750M Gigabit Ethernet" }, 170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751, 171 "Broadcom BCM5751 Gigabit Ethernet" }, 172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M, 173 "Broadcom BCM5751M Gigabit Ethernet" }, 174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782, 175 "Broadcom BCM5782 Gigabit Ethernet" }, 176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788, 177 "Broadcom BCM5788 Gigabit Ethernet" }, 178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789, 179 "Broadcom BCM5789 Gigabit Ethernet" }, 180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901, 181 "Broadcom BCM5901 Fast Ethernet" }, 182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2, 183 "Broadcom BCM5901A2 Fast Ethernet" }, 184 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 185 "SysKonnect Gigabit Ethernet" }, 186 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000, 187 "Altima AC1000 Gigabit Ethernet" }, 188 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001, 189 "Altima AC1002 Gigabit Ethernet" }, 190 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100, 191 "Altima AC9100 Gigabit Ethernet" }, 192 { 0, 0, NULL } 193 }; 194 195 static int bge_probe(device_t); 196 static int bge_attach(device_t); 197 static int bge_detach(device_t); 198 static void bge_release_resources(struct bge_softc *); 199 static void bge_txeof(struct bge_softc *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static void bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 210 static void bge_init(void *); 211 static void bge_stop(struct bge_softc *); 212 static void bge_watchdog(struct ifnet *); 213 static void bge_shutdown(device_t); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *); 218 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t); 219 220 static void bge_setmulti(struct bge_softc *); 221 222 static void bge_handle_events(struct bge_softc *); 223 static int bge_alloc_jumbo_mem(struct bge_softc *); 224 static void bge_free_jumbo_mem(struct bge_softc *); 225 static struct bge_jslot 226 *bge_jalloc(struct bge_softc *); 227 static void bge_jfree(void *); 228 static void bge_jref(void *); 229 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 230 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 231 static int bge_init_rx_ring_std(struct bge_softc *); 232 static void bge_free_rx_ring_std(struct bge_softc *); 233 static int bge_init_rx_ring_jumbo(struct bge_softc *); 234 static void bge_free_rx_ring_jumbo(struct bge_softc *); 235 static void bge_free_tx_ring(struct bge_softc *); 236 static int bge_init_tx_ring(struct bge_softc *); 237 238 static int bge_chipinit(struct bge_softc *); 239 static int bge_blockinit(struct bge_softc *); 240 241 #ifdef notdef 242 static uint8_t bge_vpd_readbyte(struct bge_softc *, uint32_t); 243 static void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t); 244 static void bge_vpd_read(struct bge_softc *); 245 #endif 246 247 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t); 248 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t); 249 #ifdef notdef 250 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t); 251 #endif 252 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t); 253 254 static int bge_miibus_readreg(device_t, int, int); 255 static int bge_miibus_writereg(device_t, int, int, int); 256 static void bge_miibus_statchg(device_t); 257 258 static void bge_reset(struct bge_softc *); 259 260 static device_method_t bge_methods[] = { 261 /* Device interface */ 262 DEVMETHOD(device_probe, bge_probe), 263 DEVMETHOD(device_attach, bge_attach), 264 DEVMETHOD(device_detach, bge_detach), 265 DEVMETHOD(device_shutdown, bge_shutdown), 266 267 /* bus interface */ 268 DEVMETHOD(bus_print_child, bus_generic_print_child), 269 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 270 271 /* MII interface */ 272 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 273 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 274 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 275 276 { 0, 0 } 277 }; 278 279 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc)); 280 static devclass_t bge_devclass; 281 282 DECLARE_DUMMY_MODULE(if_bge); 283 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 284 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 285 286 static uint32_t 287 bge_readmem_ind(struct bge_softc *sc, uint32_t off) 288 { 289 device_t dev = sc->bge_dev; 290 291 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 292 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 293 } 294 295 static void 296 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 297 { 298 device_t dev = sc->bge_dev; 299 300 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 301 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 302 } 303 304 #ifdef notdef 305 static uint32_t 306 bge_readreg_ind(struct bge_softc *sc, uin32_t off) 307 { 308 device_t dev = sc->bge_dev; 309 310 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 311 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 312 } 313 #endif 314 315 static void 316 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 317 { 318 device_t dev = sc->bge_dev; 319 320 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 321 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 322 } 323 324 #ifdef notdef 325 static uint8_t 326 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr) 327 { 328 device_t dev = sc->bge_dev; 329 uint32_t val; 330 int i; 331 332 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 333 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 334 DELAY(10); 335 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 336 break; 337 } 338 339 if (i == BGE_TIMEOUT) { 340 device_printf(sc->bge_dev, "VPD read timed out\n"); 341 return(0); 342 } 343 344 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 345 346 return((val >> ((addr % 4) * 8)) & 0xFF); 347 } 348 349 static void 350 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr) 351 { 352 size_t i; 353 uint8_t *ptr; 354 355 ptr = (uint8_t *)res; 356 for (i = 0; i < sizeof(struct vpd_res); i++) 357 ptr[i] = bge_vpd_readbyte(sc, i + addr); 358 359 return; 360 } 361 362 static void 363 bge_vpd_read(struct bge_softc *sc) 364 { 365 int pos = 0, i; 366 struct vpd_res res; 367 368 if (sc->bge_vpd_prodname != NULL) 369 free(sc->bge_vpd_prodname, M_DEVBUF); 370 if (sc->bge_vpd_readonly != NULL) 371 free(sc->bge_vpd_readonly, M_DEVBUF); 372 sc->bge_vpd_prodname = NULL; 373 sc->bge_vpd_readonly = NULL; 374 375 bge_vpd_read_res(sc, &res, pos); 376 377 if (res.vr_id != VPD_RES_ID) { 378 device_printf(sc->bge_dev, 379 "bad VPD resource id: expected %x got %x\n", 380 VPD_RES_ID, res.vr_id); 381 return; 382 } 383 384 pos += sizeof(res); 385 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 386 for (i = 0; i < res.vr_len; i++) 387 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 388 sc->bge_vpd_prodname[i] = '\0'; 389 pos += i; 390 391 bge_vpd_read_res(sc, &res, pos); 392 393 if (res.vr_id != VPD_RES_READ) { 394 device_printf(sc->bge_dev, 395 "bad VPD resource id: expected %x got %x\n", 396 VPD_RES_READ, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 402 for (i = 0; i < res.vr_len + 1; i++) 403 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 404 } 405 #endif 406 407 /* 408 * Read a byte of data stored in the EEPROM at address 'addr.' The 409 * BCM570x supports both the traditional bitbang interface and an 410 * auto access interface for reading the EEPROM. We use the auto 411 * access method. 412 */ 413 static uint8_t 414 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest) 415 { 416 int i; 417 uint32_t byte = 0; 418 419 /* 420 * Enable use of auto EEPROM access so we can avoid 421 * having to use the bitbang method. 422 */ 423 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 424 425 /* Reset the EEPROM, load the clock period. */ 426 CSR_WRITE_4(sc, BGE_EE_ADDR, 427 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 428 DELAY(20); 429 430 /* Issue the read EEPROM command. */ 431 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 432 433 /* Wait for completion */ 434 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 435 DELAY(10); 436 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 437 break; 438 } 439 440 if (i == BGE_TIMEOUT) { 441 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n"); 442 return(0); 443 } 444 445 /* Get result. */ 446 byte = CSR_READ_4(sc, BGE_EE_DATA); 447 448 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 449 450 return(0); 451 } 452 453 /* 454 * Read a sequence of bytes from the EEPROM. 455 */ 456 static int 457 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len) 458 { 459 size_t i; 460 int err; 461 uint8_t byte; 462 463 for (byte = 0, err = 0, i = 0; i < len; i++) { 464 err = bge_eeprom_getbyte(sc, off + i, &byte); 465 if (err) 466 break; 467 *(dest + i) = byte; 468 } 469 470 return(err ? 1 : 0); 471 } 472 473 static int 474 bge_miibus_readreg(device_t dev, int phy, int reg) 475 { 476 struct bge_softc *sc; 477 struct ifnet *ifp; 478 uint32_t val, autopoll; 479 int i; 480 481 sc = device_get_softc(dev); 482 ifp = &sc->arpcom.ac_if; 483 484 /* 485 * Broadcom's own driver always assumes the internal 486 * PHY is at GMII address 1. On some chips, the PHY responds 487 * to accesses at all addresses, which could cause us to 488 * bogusly attach the PHY 32 times at probe type. Always 489 * restricting the lookup to address 1 is simpler than 490 * trying to figure out which chips revisions should be 491 * special-cased. 492 */ 493 if (phy != 1) 494 return(0); 495 496 /* Reading with autopolling on may trigger PCI errors */ 497 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 498 if (autopoll & BGE_MIMODE_AUTOPOLL) { 499 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 500 DELAY(40); 501 } 502 503 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 504 BGE_MIPHY(phy)|BGE_MIREG(reg)); 505 506 for (i = 0; i < BGE_TIMEOUT; i++) { 507 val = CSR_READ_4(sc, BGE_MI_COMM); 508 if (!(val & BGE_MICOMM_BUSY)) 509 break; 510 } 511 512 if (i == BGE_TIMEOUT) { 513 if_printf(ifp, "PHY read timed out\n"); 514 val = 0; 515 goto done; 516 } 517 518 val = CSR_READ_4(sc, BGE_MI_COMM); 519 520 done: 521 if (autopoll & BGE_MIMODE_AUTOPOLL) { 522 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 523 DELAY(40); 524 } 525 526 if (val & BGE_MICOMM_READFAIL) 527 return(0); 528 529 return(val & 0xFFFF); 530 } 531 532 static int 533 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 534 { 535 struct bge_softc *sc; 536 uint32_t autopoll; 537 int i; 538 539 sc = device_get_softc(dev); 540 541 /* Reading with autopolling on may trigger PCI errors */ 542 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 543 if (autopoll & BGE_MIMODE_AUTOPOLL) { 544 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 545 DELAY(40); 546 } 547 548 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 549 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 550 551 for (i = 0; i < BGE_TIMEOUT; i++) { 552 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 553 break; 554 } 555 556 if (autopoll & BGE_MIMODE_AUTOPOLL) { 557 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 558 DELAY(40); 559 } 560 561 if (i == BGE_TIMEOUT) { 562 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n"); 563 return(0); 564 } 565 566 return(0); 567 } 568 569 static void 570 bge_miibus_statchg(device_t dev) 571 { 572 struct bge_softc *sc; 573 struct mii_data *mii; 574 575 sc = device_get_softc(dev); 576 mii = device_get_softc(sc->bge_miibus); 577 578 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 579 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 580 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 581 } else { 582 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 583 } 584 585 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 586 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 587 } else { 588 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 589 } 590 } 591 592 /* 593 * Handle events that have triggered interrupts. 594 */ 595 static void 596 bge_handle_events(struct bge_softc *sc) 597 { 598 } 599 600 /* 601 * Memory management for jumbo frames. 602 */ 603 static int 604 bge_alloc_jumbo_mem(struct bge_softc *sc) 605 { 606 struct bge_jslot *entry; 607 caddr_t ptr; 608 int i; 609 610 /* Grab a big chunk o' storage. */ 611 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 612 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 613 614 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 615 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n"); 616 return(ENOBUFS); 617 } 618 619 SLIST_INIT(&sc->bge_jfree_listhead); 620 621 /* 622 * Now divide it up into 9K pieces and save the addresses 623 * in an array. Note that we play an evil trick here by using 624 * the first few bytes in the buffer to hold the the address 625 * of the softc structure for this interface. This is because 626 * bge_jfree() needs it, but it is called by the mbuf management 627 * code which will not pass it to us explicitly. 628 */ 629 ptr = sc->bge_cdata.bge_jumbo_buf; 630 for (i = 0; i < BGE_JSLOTS; i++) { 631 entry = &sc->bge_cdata.bge_jslots[i]; 632 entry->bge_sc = sc; 633 entry->bge_buf = ptr; 634 entry->bge_inuse = 0; 635 entry->bge_slot = i; 636 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link); 637 ptr += BGE_JLEN; 638 } 639 640 return(0); 641 } 642 643 static void 644 bge_free_jumbo_mem(struct bge_softc *sc) 645 { 646 if (sc->bge_cdata.bge_jumbo_buf) 647 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 648 } 649 650 /* 651 * Allocate a jumbo buffer. 652 */ 653 static struct bge_jslot * 654 bge_jalloc(struct bge_softc *sc) 655 { 656 struct bge_jslot *entry; 657 658 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 659 660 if (entry == NULL) { 661 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 662 return(NULL); 663 } 664 665 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link); 666 entry->bge_inuse = 1; 667 return(entry); 668 } 669 670 /* 671 * Adjust usage count on a jumbo buffer. 672 */ 673 static void 674 bge_jref(void *arg) 675 { 676 struct bge_jslot *entry = (struct bge_jslot *)arg; 677 struct bge_softc *sc = entry->bge_sc; 678 679 if (sc == NULL) 680 panic("bge_jref: can't find softc pointer!"); 681 682 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) 683 panic("bge_jref: asked to reference buffer " 684 "that we don't manage!"); 685 else if (entry->bge_inuse == 0) 686 panic("bge_jref: buffer already free!"); 687 else 688 entry->bge_inuse++; 689 } 690 691 /* 692 * Release a jumbo buffer. 693 */ 694 static void 695 bge_jfree(void *arg) 696 { 697 struct bge_jslot *entry = (struct bge_jslot *)arg; 698 struct bge_softc *sc = entry->bge_sc; 699 700 if (sc == NULL) 701 panic("bge_jfree: can't find softc pointer!"); 702 703 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) 704 panic("bge_jfree: asked to free buffer that we don't manage!"); 705 else if (entry->bge_inuse == 0) 706 panic("bge_jfree: buffer already free!"); 707 else if (--entry->bge_inuse == 0) 708 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link); 709 } 710 711 712 /* 713 * Intialize a standard receive ring descriptor. 714 */ 715 static int 716 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 717 { 718 struct mbuf *m_new = NULL; 719 struct bge_rx_bd *r; 720 721 if (m == NULL) { 722 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 723 if (m_new == NULL) 724 return (ENOBUFS); 725 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 726 } else { 727 m_new = m; 728 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 729 m_new->m_data = m_new->m_ext.ext_buf; 730 } 731 732 if (!sc->bge_rx_alignment_bug) 733 m_adj(m_new, ETHER_ALIGN); 734 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 735 r = &sc->bge_rdata->bge_rx_std_ring[i]; 736 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 737 r->bge_flags = BGE_RXBDFLAG_END; 738 r->bge_len = m_new->m_len; 739 r->bge_idx = i; 740 741 return(0); 742 } 743 744 /* 745 * Initialize a jumbo receive ring descriptor. This allocates 746 * a jumbo buffer from the pool managed internally by the driver. 747 */ 748 static int 749 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 750 { 751 struct mbuf *m_new = NULL; 752 struct bge_rx_bd *r; 753 754 if (m == NULL) { 755 struct bge_jslot *buf; 756 757 /* Allocate the mbuf. */ 758 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 759 if (m_new == NULL) 760 return(ENOBUFS); 761 762 /* Allocate the jumbo buffer */ 763 buf = bge_jalloc(sc); 764 if (buf == NULL) { 765 m_freem(m_new); 766 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed " 767 "-- packet dropped!\n"); 768 return(ENOBUFS); 769 } 770 771 /* Attach the buffer to the mbuf. */ 772 m_new->m_ext.ext_arg = buf; 773 m_new->m_ext.ext_buf = buf->bge_buf; 774 m_new->m_ext.ext_free = bge_jfree; 775 m_new->m_ext.ext_ref = bge_jref; 776 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 777 778 m_new->m_data = m_new->m_ext.ext_buf; 779 m_new->m_flags |= M_EXT; 780 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 781 } else { 782 m_new = m; 783 m_new->m_data = m_new->m_ext.ext_buf; 784 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 785 } 786 787 if (!sc->bge_rx_alignment_bug) 788 m_adj(m_new, ETHER_ALIGN); 789 /* Set up the descriptor. */ 790 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 791 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 792 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 793 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 794 r->bge_len = m_new->m_len; 795 r->bge_idx = i; 796 797 return(0); 798 } 799 800 /* 801 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 802 * that's 1MB or memory, which is a lot. For now, we fill only the first 803 * 256 ring entries and hope that our CPU is fast enough to keep up with 804 * the NIC. 805 */ 806 static int 807 bge_init_rx_ring_std(struct bge_softc *sc) 808 { 809 int i; 810 811 for (i = 0; i < BGE_SSLOTS; i++) { 812 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 813 return(ENOBUFS); 814 }; 815 816 sc->bge_std = i - 1; 817 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 818 819 return(0); 820 } 821 822 static void 823 bge_free_rx_ring_std(struct bge_softc *sc) 824 { 825 int i; 826 827 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 828 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 829 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 830 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 831 } 832 bzero(&sc->bge_rdata->bge_rx_std_ring[i], 833 sizeof(struct bge_rx_bd)); 834 } 835 } 836 837 static int 838 bge_init_rx_ring_jumbo(struct bge_softc *sc) 839 { 840 int i; 841 struct bge_rcb *rcb; 842 843 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 844 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 845 return(ENOBUFS); 846 }; 847 848 sc->bge_jumbo = i - 1; 849 850 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 851 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 852 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 853 854 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 855 856 return(0); 857 } 858 859 static void 860 bge_free_rx_ring_jumbo(struct bge_softc *sc) 861 { 862 int i; 863 864 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 865 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 866 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 867 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 868 } 869 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i], 870 sizeof(struct bge_rx_bd)); 871 } 872 } 873 874 static void 875 bge_free_tx_ring(struct bge_softc *sc) 876 { 877 int i; 878 879 if (sc->bge_rdata->bge_tx_ring == NULL) 880 return; 881 882 for (i = 0; i < BGE_TX_RING_CNT; i++) { 883 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 884 m_freem(sc->bge_cdata.bge_tx_chain[i]); 885 sc->bge_cdata.bge_tx_chain[i] = NULL; 886 } 887 bzero(&sc->bge_rdata->bge_tx_ring[i], 888 sizeof(struct bge_tx_bd)); 889 } 890 } 891 892 static int 893 bge_init_tx_ring(struct bge_softc *sc) 894 { 895 sc->bge_txcnt = 0; 896 sc->bge_tx_saved_considx = 0; 897 898 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 899 /* 5700 b2 errata */ 900 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 901 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 902 903 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 904 /* 5700 b2 errata */ 905 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 906 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 907 908 return(0); 909 } 910 911 static void 912 bge_setmulti(struct bge_softc *sc) 913 { 914 struct ifnet *ifp; 915 struct ifmultiaddr *ifma; 916 uint32_t hashes[4] = { 0, 0, 0, 0 }; 917 int h, i; 918 919 ifp = &sc->arpcom.ac_if; 920 921 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 922 for (i = 0; i < 4; i++) 923 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 924 return; 925 } 926 927 /* First, zot all the existing filters. */ 928 for (i = 0; i < 4; i++) 929 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 930 931 /* Now program new ones. */ 932 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 933 if (ifma->ifma_addr->sa_family != AF_LINK) 934 continue; 935 h = ether_crc32_le( 936 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 937 ETHER_ADDR_LEN) & 0x7f; 938 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 939 } 940 941 for (i = 0; i < 4; i++) 942 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 943 } 944 945 /* 946 * Do endian, PCI and DMA initialization. Also check the on-board ROM 947 * self-test results. 948 */ 949 static int 950 bge_chipinit(struct bge_softc *sc) 951 { 952 int i; 953 uint32_t dma_rw_ctl; 954 955 /* Set endianness before we access any non-PCI registers. */ 956 #if BYTE_ORDER == BIG_ENDIAN 957 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 958 BGE_BIGENDIAN_INIT, 4); 959 #else 960 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 961 BGE_LITTLEENDIAN_INIT, 4); 962 #endif 963 964 /* 965 * Check the 'ROM failed' bit on the RX CPU to see if 966 * self-tests passed. 967 */ 968 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 969 if_printf(&sc->arpcom.ac_if, 970 "RX CPU self-diagnostics failed!\n"); 971 return(ENODEV); 972 } 973 974 /* Clear the MAC control register */ 975 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 976 977 /* 978 * Clear the MAC statistics block in the NIC's 979 * internal memory. 980 */ 981 for (i = BGE_STATS_BLOCK; 982 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 983 BGE_MEMWIN_WRITE(sc, i, 0); 984 985 for (i = BGE_STATUS_BLOCK; 986 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 987 BGE_MEMWIN_WRITE(sc, i, 0); 988 989 /* Set up the PCI DMA control register. */ 990 if (sc->bge_pcie) { 991 /* PCI Express */ 992 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 993 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 994 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 995 } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 996 BGE_PCISTATE_PCI_BUSMODE) { 997 /* Conventional PCI bus */ 998 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 999 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1000 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1001 (0x0F); 1002 } else { 1003 /* PCI-X bus */ 1004 /* 1005 * The 5704 uses a different encoding of read/write 1006 * watermarks. 1007 */ 1008 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1009 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1010 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1011 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1012 else 1013 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1014 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1015 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1016 (0x0F); 1017 1018 /* 1019 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1020 * for hardware bugs. 1021 */ 1022 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1023 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1024 uint32_t tmp; 1025 1026 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1027 if (tmp == 0x6 || tmp == 0x7) 1028 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1029 } 1030 } 1031 1032 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1033 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1034 sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1035 sc->bge_asicrev == BGE_ASICREV_BCM5750) 1036 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1037 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1038 1039 /* 1040 * Set up general mode register. 1041 */ 1042 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1043 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1044 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1045 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1046 1047 /* 1048 * Disable memory write invalidate. Apparently it is not supported 1049 * properly by these devices. 1050 */ 1051 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1052 1053 /* Set the timer prescaler (always 66Mhz) */ 1054 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1055 1056 return(0); 1057 } 1058 1059 static int 1060 bge_blockinit(struct bge_softc *sc) 1061 { 1062 struct bge_rcb *rcb; 1063 volatile struct bge_rcb *vrcb; 1064 int i; 1065 1066 /* 1067 * Initialize the memory window pointer register so that 1068 * we can access the first 32K of internal NIC RAM. This will 1069 * allow us to set up the TX send ring RCBs and the RX return 1070 * ring RCBs, plus other things which live in NIC memory. 1071 */ 1072 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1073 1074 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1075 1076 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1077 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1078 /* Configure mbuf memory pool */ 1079 if (sc->bge_extram) { 1080 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1081 BGE_EXT_SSRAM); 1082 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1083 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1084 else 1085 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1086 } else { 1087 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1088 BGE_BUFFPOOL_1); 1089 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1090 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1091 else 1092 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1093 } 1094 1095 /* Configure DMA resource pool */ 1096 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1097 BGE_DMA_DESCRIPTORS); 1098 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1099 } 1100 1101 /* Configure mbuf pool watermarks */ 1102 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1103 sc->bge_asicrev == BGE_ASICREV_BCM5750) { 1104 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1105 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1106 } else { 1107 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1108 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1109 } 1110 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1111 1112 /* Configure DMA resource watermarks */ 1113 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1114 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1115 1116 /* Enable buffer manager */ 1117 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1118 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1119 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1120 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1121 1122 /* Poll for buffer manager start indication */ 1123 for (i = 0; i < BGE_TIMEOUT; i++) { 1124 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1125 break; 1126 DELAY(10); 1127 } 1128 1129 if (i == BGE_TIMEOUT) { 1130 if_printf(&sc->arpcom.ac_if, 1131 "buffer manager failed to start\n"); 1132 return(ENXIO); 1133 } 1134 } 1135 1136 /* Enable flow-through queues */ 1137 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1138 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1139 1140 /* Wait until queue initialization is complete */ 1141 for (i = 0; i < BGE_TIMEOUT; i++) { 1142 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1143 break; 1144 DELAY(10); 1145 } 1146 1147 if (i == BGE_TIMEOUT) { 1148 if_printf(&sc->arpcom.ac_if, 1149 "flow-through queue init failed\n"); 1150 return(ENXIO); 1151 } 1152 1153 /* Initialize the standard RX ring control block */ 1154 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1155 BGE_HOSTADDR(rcb->bge_hostaddr, 1156 vtophys(&sc->bge_rdata->bge_rx_std_ring)); 1157 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1158 sc->bge_asicrev == BGE_ASICREV_BCM5750) 1159 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1160 else 1161 rcb->bge_maxlen_flags = 1162 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1163 if (sc->bge_extram) 1164 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1165 else 1166 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1167 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1168 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1169 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1170 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1171 1172 /* 1173 * Initialize the jumbo RX ring control block 1174 * We set the 'ring disabled' bit in the flags 1175 * field until we're actually ready to start 1176 * using this ring (i.e. once we set the MTU 1177 * high enough to require it). 1178 */ 1179 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1180 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1181 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1182 BGE_HOSTADDR(rcb->bge_hostaddr, 1183 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring)); 1184 rcb->bge_maxlen_flags = 1185 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1186 BGE_RCB_FLAG_RING_DISABLED); 1187 if (sc->bge_extram) 1188 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1189 else 1190 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1191 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1192 rcb->bge_hostaddr.bge_addr_hi); 1193 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1194 rcb->bge_hostaddr.bge_addr_lo); 1195 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1196 rcb->bge_maxlen_flags); 1197 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1198 1199 /* Set up dummy disabled mini ring RCB */ 1200 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1201 rcb->bge_maxlen_flags = 1202 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1203 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1204 rcb->bge_maxlen_flags); 1205 } 1206 1207 /* 1208 * Set the BD ring replentish thresholds. The recommended 1209 * values are 1/8th the number of descriptors allocated to 1210 * each ring. 1211 */ 1212 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1213 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1214 1215 /* 1216 * Disable all unused send rings by setting the 'ring disabled' 1217 * bit in the flags field of all the TX send ring control blocks. 1218 * These are located in NIC memory. 1219 */ 1220 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1221 BGE_SEND_RING_RCB); 1222 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1223 vrcb->bge_maxlen_flags = 1224 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1225 vrcb->bge_nicaddr = 0; 1226 vrcb++; 1227 } 1228 1229 /* Configure TX RCB 0 (we use only the first ring) */ 1230 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1231 BGE_SEND_RING_RCB); 1232 vrcb->bge_hostaddr.bge_addr_hi = 0; 1233 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring)); 1234 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1235 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1236 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1237 vrcb->bge_maxlen_flags = 1238 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1239 1240 /* Disable all unused RX return rings */ 1241 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1242 BGE_RX_RETURN_RING_RCB); 1243 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1244 vrcb->bge_hostaddr.bge_addr_hi = 0; 1245 vrcb->bge_hostaddr.bge_addr_lo = 0; 1246 vrcb->bge_maxlen_flags = 1247 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1248 BGE_RCB_FLAG_RING_DISABLED); 1249 vrcb->bge_nicaddr = 0; 1250 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1251 (i * (sizeof(uint64_t))), 0); 1252 vrcb++; 1253 } 1254 1255 /* Initialize RX ring indexes */ 1256 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1257 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1258 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1259 1260 /* 1261 * Set up RX return ring 0 1262 * Note that the NIC address for RX return rings is 0x00000000. 1263 * The return rings live entirely within the host, so the 1264 * nicaddr field in the RCB isn't used. 1265 */ 1266 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1267 BGE_RX_RETURN_RING_RCB); 1268 vrcb->bge_hostaddr.bge_addr_hi = 0; 1269 BGE_HOSTADDR(vrcb->bge_hostaddr, 1270 vtophys(&sc->bge_rdata->bge_rx_return_ring)); 1271 vrcb->bge_nicaddr = 0x00000000; 1272 vrcb->bge_maxlen_flags = 1273 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1274 1275 /* Set random backoff seed for TX */ 1276 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1277 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1278 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1279 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1280 BGE_TX_BACKOFF_SEED_MASK); 1281 1282 /* Set inter-packet gap */ 1283 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1284 1285 /* 1286 * Specify which ring to use for packets that don't match 1287 * any RX rules. 1288 */ 1289 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1290 1291 /* 1292 * Configure number of RX lists. One interrupt distribution 1293 * list, sixteen active lists, one bad frames class. 1294 */ 1295 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1296 1297 /* Inialize RX list placement stats mask. */ 1298 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1299 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1300 1301 /* Disable host coalescing until we get it set up */ 1302 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1303 1304 /* Poll to make sure it's shut down. */ 1305 for (i = 0; i < BGE_TIMEOUT; i++) { 1306 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1307 break; 1308 DELAY(10); 1309 } 1310 1311 if (i == BGE_TIMEOUT) { 1312 if_printf(&sc->arpcom.ac_if, 1313 "host coalescing engine failed to idle\n"); 1314 return(ENXIO); 1315 } 1316 1317 /* Set up host coalescing defaults */ 1318 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1319 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1320 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1321 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1322 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1323 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1324 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1325 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1326 } 1327 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1328 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1329 1330 /* Set up address of statistics block */ 1331 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1332 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1333 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1334 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1335 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1336 1337 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1338 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1339 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1340 } 1341 1342 /* Set up address of status block */ 1343 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1344 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1345 vtophys(&sc->bge_rdata->bge_status_block)); 1346 1347 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1348 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1349 1350 /* Turn on host coalescing state machine */ 1351 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1352 1353 /* Turn on RX BD completion state machine and enable attentions */ 1354 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1355 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1356 1357 /* Turn on RX list placement state machine */ 1358 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1359 1360 /* Turn on RX list selector state machine. */ 1361 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1362 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1363 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1364 1365 /* Turn on DMA, clear stats */ 1366 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1367 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1368 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1369 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1370 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1371 1372 /* Set misc. local control, enable interrupts on attentions */ 1373 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1374 1375 #ifdef notdef 1376 /* Assert GPIO pins for PHY reset */ 1377 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1378 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1379 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1380 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1381 #endif 1382 1383 /* Turn on DMA completion state machine */ 1384 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1385 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1386 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1387 1388 /* Turn on write DMA state machine */ 1389 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1390 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1391 1392 /* Turn on read DMA state machine */ 1393 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1394 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1395 1396 /* Turn on RX data completion state machine */ 1397 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1398 1399 /* Turn on RX BD initiator state machine */ 1400 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1401 1402 /* Turn on RX data and RX BD initiator state machine */ 1403 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1404 1405 /* Turn on Mbuf cluster free state machine */ 1406 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1407 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1408 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1409 1410 /* Turn on send BD completion state machine */ 1411 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1412 1413 /* Turn on send data completion state machine */ 1414 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1415 1416 /* Turn on send data initiator state machine */ 1417 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1418 1419 /* Turn on send BD initiator state machine */ 1420 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1421 1422 /* Turn on send BD selector state machine */ 1423 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1424 1425 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1426 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1427 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1428 1429 /* ack/clear link change events */ 1430 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1431 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1432 BGE_MACSTAT_LINK_CHANGED); 1433 1434 /* Enable PHY auto polling (for MII/GMII only) */ 1435 if (sc->bge_tbi) { 1436 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1437 } else { 1438 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1439 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1440 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1441 BGE_EVTENB_MI_INTERRUPT); 1442 } 1443 1444 /* Enable link state change attentions. */ 1445 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1446 1447 return(0); 1448 } 1449 1450 /* 1451 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1452 * against our list and return its name if we find a match. Note 1453 * that since the Broadcom controller contains VPD support, we 1454 * can get the device name string from the controller itself instead 1455 * of the compiled-in string. This is a little slow, but it guarantees 1456 * we'll always announce the right product name. 1457 */ 1458 static int 1459 bge_probe(device_t dev) 1460 { 1461 struct bge_softc *sc; 1462 struct bge_type *t; 1463 char *descbuf; 1464 uint16_t product, vendor; 1465 1466 product = pci_get_device(dev); 1467 vendor = pci_get_vendor(dev); 1468 1469 for (t = bge_devs; t->bge_name != NULL; t++) { 1470 if (vendor == t->bge_vid && product == t->bge_did) 1471 break; 1472 } 1473 1474 if (t->bge_name == NULL) 1475 return(ENXIO); 1476 1477 sc = device_get_softc(dev); 1478 #ifdef notdef 1479 sc->bge_dev = dev; 1480 1481 bge_vpd_read(sc); 1482 device_set_desc(dev, sc->bge_vpd_prodname); 1483 #endif 1484 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK); 1485 snprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name, 1486 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1487 device_set_desc_copy(dev, descbuf); 1488 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) 1489 sc->bge_no_3_led = 1; 1490 free(descbuf, M_TEMP); 1491 return(0); 1492 } 1493 1494 static int 1495 bge_attach(device_t dev) 1496 { 1497 struct ifnet *ifp; 1498 struct bge_softc *sc; 1499 uint32_t hwcfg = 0; 1500 uint32_t mac_addr = 0; 1501 int error = 0, rid; 1502 uint8_t ether_addr[ETHER_ADDR_LEN]; 1503 1504 sc = device_get_softc(dev); 1505 sc->bge_dev = dev; 1506 callout_init(&sc->bge_stat_timer); 1507 1508 /* 1509 * Map control/status registers. 1510 */ 1511 pci_enable_busmaster(dev); 1512 1513 rid = BGE_PCI_BAR0; 1514 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1515 RF_ACTIVE); 1516 1517 if (sc->bge_res == NULL) { 1518 device_printf(dev, "couldn't map memory\n"); 1519 error = ENXIO; 1520 return(error); 1521 } 1522 1523 sc->bge_btag = rman_get_bustag(sc->bge_res); 1524 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1525 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1526 1527 /* Allocate interrupt */ 1528 rid = 0; 1529 1530 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1531 RF_SHAREABLE | RF_ACTIVE); 1532 1533 if (sc->bge_irq == NULL) { 1534 device_printf(dev, "couldn't map interrupt\n"); 1535 error = ENXIO; 1536 goto fail; 1537 } 1538 1539 /* Save ASIC rev. */ 1540 sc->bge_chipid = 1541 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1542 BGE_PCIMISCCTL_ASICREV; 1543 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1544 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1545 1546 /* 1547 * Treat the 5714 like the 5750 until we have more info 1548 * on this chip. 1549 */ 1550 if (sc->bge_asicrev == BGE_ASICREV_BCM5714) 1551 sc->bge_asicrev = BGE_ASICREV_BCM5750; 1552 1553 /* 1554 * XXX: Broadcom Linux driver. Not in specs or eratta. 1555 * PCI-Express? 1556 */ 1557 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 1558 uint32_t v; 1559 1560 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4); 1561 if (((v >> 8) & 0xff) == BGE_PCIE_MSI_CAPID) { 1562 v = pci_read_config(dev, BGE_PCIE_MSI_CAPID, 4); 1563 if ((v & 0xff) == BGE_PCIE_MSI_CAPID_VAL) 1564 sc->bge_pcie = 1; 1565 } 1566 } 1567 1568 ifp = &sc->arpcom.ac_if; 1569 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1570 1571 /* Try to reset the chip. */ 1572 bge_reset(sc); 1573 1574 if (bge_chipinit(sc)) { 1575 device_printf(dev, "chip initialization failed\n"); 1576 error = ENXIO; 1577 goto fail; 1578 } 1579 1580 /* 1581 * Get station address from the EEPROM. 1582 */ 1583 mac_addr = bge_readmem_ind(sc, 0x0c14); 1584 if ((mac_addr >> 16) == 0x484b) { 1585 ether_addr[0] = (uint8_t)(mac_addr >> 8); 1586 ether_addr[1] = (uint8_t)mac_addr; 1587 mac_addr = bge_readmem_ind(sc, 0x0c18); 1588 ether_addr[2] = (uint8_t)(mac_addr >> 24); 1589 ether_addr[3] = (uint8_t)(mac_addr >> 16); 1590 ether_addr[4] = (uint8_t)(mac_addr >> 8); 1591 ether_addr[5] = (uint8_t)mac_addr; 1592 } else if (bge_read_eeprom(sc, ether_addr, 1593 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1594 device_printf(dev, "failed to read station address\n"); 1595 error = ENXIO; 1596 goto fail; 1597 } 1598 1599 /* Allocate the general information block and ring buffers. */ 1600 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1601 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1602 1603 if (sc->bge_rdata == NULL) { 1604 error = ENXIO; 1605 device_printf(dev, "no memory for list buffers!\n"); 1606 goto fail; 1607 } 1608 1609 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1610 1611 /* 1612 * Try to allocate memory for jumbo buffers. 1613 * The 5705/5750 does not appear to support jumbo frames. 1614 */ 1615 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1616 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1617 if (bge_alloc_jumbo_mem(sc)) { 1618 device_printf(dev, "jumbo buffer allocation failed\n"); 1619 error = ENXIO; 1620 goto fail; 1621 } 1622 } 1623 1624 /* Set default tuneable values. */ 1625 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1626 sc->bge_rx_coal_ticks = 150; 1627 sc->bge_tx_coal_ticks = 150; 1628 sc->bge_rx_max_coal_bds = 64; 1629 sc->bge_tx_max_coal_bds = 128; 1630 1631 /* 5705/5750 limits RX return ring to 512 entries. */ 1632 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1633 sc->bge_asicrev == BGE_ASICREV_BCM5750) 1634 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1635 else 1636 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1637 1638 /* Set up ifnet structure */ 1639 ifp->if_softc = sc; 1640 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1641 ifp->if_ioctl = bge_ioctl; 1642 ifp->if_start = bge_start; 1643 ifp->if_watchdog = bge_watchdog; 1644 ifp->if_init = bge_init; 1645 ifp->if_mtu = ETHERMTU; 1646 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1647 ifq_set_ready(&ifp->if_snd); 1648 ifp->if_hwassist = BGE_CSUM_FEATURES; 1649 ifp->if_capabilities = IFCAP_HWCSUM; 1650 ifp->if_capenable = ifp->if_capabilities; 1651 1652 /* 1653 * Figure out what sort of media we have by checking the 1654 * hardware config word in the first 32k of NIC internal memory, 1655 * or fall back to examining the EEPROM if necessary. 1656 * Note: on some BCM5700 cards, this value appears to be unset. 1657 * If that's the case, we have to rely on identifying the NIC 1658 * by its PCI subsystem ID, as we do below for the SysKonnect 1659 * SK-9D41. 1660 */ 1661 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1662 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1663 else { 1664 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1665 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1666 hwcfg = ntohl(hwcfg); 1667 } 1668 1669 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1670 sc->bge_tbi = 1; 1671 1672 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1673 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41) 1674 sc->bge_tbi = 1; 1675 1676 if (sc->bge_tbi) { 1677 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1678 bge_ifmedia_upd, bge_ifmedia_sts); 1679 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1680 ifmedia_add(&sc->bge_ifmedia, 1681 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1682 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1683 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1684 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 1685 } else { 1686 /* 1687 * Do transceiver setup. 1688 */ 1689 if (mii_phy_probe(dev, &sc->bge_miibus, 1690 bge_ifmedia_upd, bge_ifmedia_sts)) { 1691 device_printf(dev, "MII without any PHY!\n"); 1692 error = ENXIO; 1693 goto fail; 1694 } 1695 } 1696 1697 /* 1698 * When using the BCM5701 in PCI-X mode, data corruption has 1699 * been observed in the first few bytes of some received packets. 1700 * Aligning the packet buffer in memory eliminates the corruption. 1701 * Unfortunately, this misaligns the packet payloads. On platforms 1702 * which do not support unaligned accesses, we will realign the 1703 * payloads by copying the received packets. 1704 */ 1705 switch (sc->bge_chipid) { 1706 case BGE_CHIPID_BCM5701_A0: 1707 case BGE_CHIPID_BCM5701_B0: 1708 case BGE_CHIPID_BCM5701_B2: 1709 case BGE_CHIPID_BCM5701_B5: 1710 /* If in PCI-X mode, work around the alignment bug. */ 1711 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1712 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1713 BGE_PCISTATE_PCI_BUSSPEED) 1714 sc->bge_rx_alignment_bug = 1; 1715 break; 1716 } 1717 1718 /* 1719 * Call MI attach routine. 1720 */ 1721 ether_ifattach(ifp, ether_addr); 1722 1723 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1724 bge_intr, sc, &sc->bge_intrhand, NULL); 1725 if (error) { 1726 ether_ifdetach(ifp); 1727 device_printf(dev, "couldn't set up irq\n"); 1728 goto fail; 1729 } 1730 1731 return(0); 1732 1733 fail: 1734 bge_detach(dev); 1735 1736 return(error); 1737 } 1738 1739 static int 1740 bge_detach(device_t dev) 1741 { 1742 struct bge_softc *sc = device_get_softc(dev); 1743 struct ifnet *ifp = &sc->arpcom.ac_if; 1744 1745 crit_enter(); 1746 1747 if (device_is_attached(dev)) { 1748 ether_ifdetach(ifp); 1749 bge_stop(sc); 1750 bge_reset(sc); 1751 } 1752 1753 if (sc->bge_tbi) 1754 ifmedia_removeall(&sc->bge_ifmedia); 1755 if (sc->bge_miibus); 1756 device_delete_child(dev, sc->bge_miibus); 1757 bus_generic_detach(dev); 1758 1759 bge_release_resources(sc); 1760 1761 crit_exit(); 1762 1763 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1764 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1765 bge_free_jumbo_mem(sc); 1766 1767 return(0); 1768 } 1769 1770 static void 1771 bge_release_resources(struct bge_softc *sc) 1772 { 1773 device_t dev; 1774 1775 dev = sc->bge_dev; 1776 1777 if (sc->bge_vpd_prodname != NULL) 1778 free(sc->bge_vpd_prodname, M_DEVBUF); 1779 1780 if (sc->bge_vpd_readonly != NULL) 1781 free(sc->bge_vpd_readonly, M_DEVBUF); 1782 1783 if (sc->bge_intrhand != NULL) 1784 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1785 1786 if (sc->bge_irq != NULL) 1787 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1788 1789 if (sc->bge_res != NULL) 1790 bus_release_resource(dev, SYS_RES_MEMORY, 1791 BGE_PCI_BAR0, sc->bge_res); 1792 1793 if (sc->bge_rdata != NULL) 1794 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data), 1795 M_DEVBUF); 1796 1797 return; 1798 } 1799 1800 static void 1801 bge_reset(struct bge_softc *sc) 1802 { 1803 device_t dev; 1804 uint32_t cachesize, command, pcistate, reset; 1805 int i, val = 0; 1806 1807 dev = sc->bge_dev; 1808 1809 /* Save some important PCI state. */ 1810 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1811 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1812 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1813 1814 pci_write_config(dev, BGE_PCI_MISC_CTL, 1815 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1816 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1817 1818 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 1819 1820 /* XXX: Broadcom Linux driver. */ 1821 if (sc->bge_pcie) { 1822 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */ 1823 CSR_WRITE_4(sc, 0x7e2c, 0x20); 1824 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 1825 /* Prevent PCIE link training during global reset */ 1826 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 1827 reset |= (1<<29); 1828 } 1829 } 1830 1831 /* Issue global reset */ 1832 bge_writereg_ind(sc, BGE_MISC_CFG, reset); 1833 1834 DELAY(1000); 1835 1836 /* XXX: Broadcom Linux driver. */ 1837 if (sc->bge_pcie) { 1838 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 1839 uint32_t v; 1840 1841 DELAY(500000); /* wait for link training to complete */ 1842 v = pci_read_config(dev, 0xc4, 4); 1843 pci_write_config(dev, 0xc4, v | (1<<15), 4); 1844 } 1845 /* Set PCIE max payload size and clear error status. */ 1846 pci_write_config(dev, 0xd8, 0xf5000, 4); 1847 } 1848 1849 /* Reset some of the PCI state that got zapped by reset */ 1850 pci_write_config(dev, BGE_PCI_MISC_CTL, 1851 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1852 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1853 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1854 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1855 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1856 1857 /* Enable memory arbiter. */ 1858 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1859 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1860 1861 /* 1862 * Prevent PXE restart: write a magic number to the 1863 * general communications memory at 0xB50. 1864 */ 1865 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1866 /* 1867 * Poll the value location we just wrote until 1868 * we see the 1's complement of the magic number. 1869 * This indicates that the firmware initialization 1870 * is complete. 1871 */ 1872 for (i = 0; i < BGE_TIMEOUT; i++) { 1873 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1874 if (val == ~BGE_MAGIC_NUMBER) 1875 break; 1876 DELAY(10); 1877 } 1878 1879 if (i == BGE_TIMEOUT) { 1880 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n"); 1881 return; 1882 } 1883 1884 /* 1885 * XXX Wait for the value of the PCISTATE register to 1886 * return to its original pre-reset state. This is a 1887 * fairly good indicator of reset completion. If we don't 1888 * wait for the reset to fully complete, trying to read 1889 * from the device's non-PCI registers may yield garbage 1890 * results. 1891 */ 1892 for (i = 0; i < BGE_TIMEOUT; i++) { 1893 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1894 break; 1895 DELAY(10); 1896 } 1897 1898 /* Fix up byte swapping */ 1899 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1900 BGE_MODECTL_BYTESWAP_DATA); 1901 1902 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1903 1904 /* 1905 * The 5704 in TBI mode apparently needs some special 1906 * adjustment to insure the SERDES drive level is set 1907 * to 1.2V. 1908 */ 1909 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) { 1910 uint32_t serdescfg; 1911 1912 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 1913 serdescfg = (serdescfg & ~0xFFF) | 0x880; 1914 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 1915 } 1916 1917 /* XXX: Broadcom Linux driver. */ 1918 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 1919 uint32_t v; 1920 1921 v = CSR_READ_4(sc, 0x7c00); 1922 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 1923 } 1924 1925 DELAY(10000); 1926 } 1927 1928 /* 1929 * Frame reception handling. This is called if there's a frame 1930 * on the receive return list. 1931 * 1932 * Note: we have to be able to handle two possibilities here: 1933 * 1) the frame is from the jumbo recieve ring 1934 * 2) the frame is from the standard receive ring 1935 */ 1936 1937 static void 1938 bge_rxeof(struct bge_softc *sc) 1939 { 1940 struct ifnet *ifp; 1941 int stdcnt = 0, jumbocnt = 0; 1942 1943 ifp = &sc->arpcom.ac_if; 1944 1945 while(sc->bge_rx_saved_considx != 1946 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1947 struct bge_rx_bd *cur_rx; 1948 uint32_t rxidx; 1949 struct mbuf *m = NULL; 1950 uint16_t vlan_tag = 0; 1951 int have_tag = 0; 1952 1953 cur_rx = 1954 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1955 1956 rxidx = cur_rx->bge_idx; 1957 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 1958 1959 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1960 have_tag = 1; 1961 vlan_tag = cur_rx->bge_vlan_tag; 1962 } 1963 1964 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1965 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1966 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1967 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1968 jumbocnt++; 1969 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1970 ifp->if_ierrors++; 1971 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1972 continue; 1973 } 1974 if (bge_newbuf_jumbo(sc, 1975 sc->bge_jumbo, NULL) == ENOBUFS) { 1976 ifp->if_ierrors++; 1977 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1978 continue; 1979 } 1980 } else { 1981 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1982 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1983 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1984 stdcnt++; 1985 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1986 ifp->if_ierrors++; 1987 bge_newbuf_std(sc, sc->bge_std, m); 1988 continue; 1989 } 1990 if (bge_newbuf_std(sc, sc->bge_std, 1991 NULL) == ENOBUFS) { 1992 ifp->if_ierrors++; 1993 bge_newbuf_std(sc, sc->bge_std, m); 1994 continue; 1995 } 1996 } 1997 1998 ifp->if_ipackets++; 1999 #ifndef __i386__ 2000 /* 2001 * The i386 allows unaligned accesses, but for other 2002 * platforms we must make sure the payload is aligned. 2003 */ 2004 if (sc->bge_rx_alignment_bug) { 2005 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2006 cur_rx->bge_len); 2007 m->m_data += ETHER_ALIGN; 2008 } 2009 #endif 2010 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2011 m->m_pkthdr.rcvif = ifp; 2012 2013 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2014 if (ifp->if_hwassist) { 2015 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2016 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2017 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2018 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2019 m->m_pkthdr.csum_data = 2020 cur_rx->bge_tcp_udp_csum; 2021 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2022 } 2023 } 2024 #endif 2025 2026 /* 2027 * If we received a packet with a vlan tag, pass it 2028 * to vlan_input() instead of ether_input(). 2029 */ 2030 if (have_tag) { 2031 VLAN_INPUT_TAG(m, vlan_tag); 2032 have_tag = vlan_tag = 0; 2033 continue; 2034 } 2035 2036 (*ifp->if_input)(ifp, m); 2037 } 2038 2039 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2040 if (stdcnt) 2041 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2042 if (jumbocnt) 2043 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2044 } 2045 2046 static void 2047 bge_txeof(struct bge_softc *sc) 2048 { 2049 struct bge_tx_bd *cur_tx = NULL; 2050 struct ifnet *ifp; 2051 2052 ifp = &sc->arpcom.ac_if; 2053 2054 /* 2055 * Go through our tx ring and free mbufs for those 2056 * frames that have been sent. 2057 */ 2058 while (sc->bge_tx_saved_considx != 2059 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2060 uint32_t idx = 0; 2061 2062 idx = sc->bge_tx_saved_considx; 2063 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2064 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2065 ifp->if_opackets++; 2066 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2067 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2068 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2069 } 2070 sc->bge_txcnt--; 2071 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2072 ifp->if_timer = 0; 2073 } 2074 2075 if (cur_tx != NULL) 2076 ifp->if_flags &= ~IFF_OACTIVE; 2077 } 2078 2079 static void 2080 bge_intr(void *xsc) 2081 { 2082 struct bge_softc *sc = xsc; 2083 struct ifnet *ifp = &sc->arpcom.ac_if; 2084 uint32_t status, statusword, mimode; 2085 2086 /* XXX */ 2087 statusword = loadandclear(&sc->bge_rdata->bge_status_block.bge_status); 2088 2089 #ifdef notdef 2090 /* Avoid this for now -- checking this register is expensive. */ 2091 /* Make sure this is really our interrupt. */ 2092 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2093 return; 2094 #endif 2095 /* Ack interrupt and stop others from occuring. */ 2096 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2097 2098 /* 2099 * Process link state changes. 2100 * Grrr. The link status word in the status block does 2101 * not work correctly on the BCM5700 rev AX and BX chips, 2102 * according to all available information. Hence, we have 2103 * to enable MII interrupts in order to properly obtain 2104 * async link changes. Unfortunately, this also means that 2105 * we have to read the MAC status register to detect link 2106 * changes, thereby adding an additional register access to 2107 * the interrupt handler. 2108 */ 2109 2110 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2111 status = CSR_READ_4(sc, BGE_MAC_STS); 2112 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2113 sc->bge_link = 0; 2114 callout_stop(&sc->bge_stat_timer); 2115 bge_tick(sc); 2116 /* Clear the interrupt */ 2117 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2118 BGE_EVTENB_MI_INTERRUPT); 2119 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2120 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2121 BRGPHY_INTRS); 2122 } 2123 } else { 2124 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2125 /* 2126 * Sometimes PCS encoding errors are detected in 2127 * TBI mode (on fiber NICs), and for some reason 2128 * the chip will signal them as link changes. 2129 * If we get a link change event, but the 'PCS 2130 * encoding error' bit in the MAC status register 2131 * is set, don't bother doing a link check. 2132 * This avoids spurious "gigabit link up" messages 2133 * that sometimes appear on fiber NICs during 2134 * periods of heavy traffic. (There should be no 2135 * effect on copper NICs.) 2136 * 2137 * If we do have a copper NIC (bge_tbi == 0) then 2138 * check that the AUTOPOLL bit is set before 2139 * processing the event as a real link change. 2140 * Turning AUTOPOLL on and off in the MII read/write 2141 * functions will often trigger a link status 2142 * interrupt for no reason. 2143 */ 2144 status = CSR_READ_4(sc, BGE_MAC_STS); 2145 mimode = CSR_READ_4(sc, BGE_MI_MODE); 2146 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR | 2147 BGE_MACSTAT_MI_COMPLETE)) && 2148 (!sc->bge_tbi && (mimode & BGE_MIMODE_AUTOPOLL))) { 2149 sc->bge_link = 0; 2150 callout_stop(&sc->bge_stat_timer); 2151 bge_tick(sc); 2152 } 2153 sc->bge_link = 0; 2154 callout_stop(&sc->bge_stat_timer); 2155 bge_tick(sc); 2156 /* Clear the interrupt */ 2157 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2158 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2159 BGE_MACSTAT_LINK_CHANGED); 2160 2161 /* Force flush the status block cached by PCI bridge */ 2162 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2163 } 2164 } 2165 2166 if (ifp->if_flags & IFF_RUNNING) { 2167 /* Check RX return ring producer/consumer */ 2168 bge_rxeof(sc); 2169 2170 /* Check TX ring producer/consumer */ 2171 bge_txeof(sc); 2172 } 2173 2174 bge_handle_events(sc); 2175 2176 /* Re-enable interrupts. */ 2177 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2178 2179 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 2180 (*ifp->if_start)(ifp); 2181 } 2182 2183 static void 2184 bge_tick(void *xsc) 2185 { 2186 struct bge_softc *sc = xsc; 2187 struct ifnet *ifp = &sc->arpcom.ac_if; 2188 struct mii_data *mii = NULL; 2189 struct ifmedia *ifm = NULL; 2190 2191 crit_enter(); 2192 2193 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 2194 sc->bge_asicrev == BGE_ASICREV_BCM5750) 2195 bge_stats_update_regs(sc); 2196 else 2197 bge_stats_update(sc); 2198 2199 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 2200 2201 if (sc->bge_link) { 2202 crit_exit(); 2203 return; 2204 } 2205 2206 if (sc->bge_tbi) { 2207 ifm = &sc->bge_ifmedia; 2208 if (CSR_READ_4(sc, BGE_MAC_STS) & 2209 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2210 sc->bge_link++; 2211 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 2212 BGE_CLRBIT(sc, BGE_MAC_MODE, 2213 BGE_MACMODE_TBI_SEND_CFGS); 2214 } 2215 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2216 if_printf(ifp, "gigabit link up\n"); 2217 if (!ifq_is_empty(&ifp->if_snd)) 2218 (*ifp->if_start)(ifp); 2219 } 2220 crit_exit(); 2221 return; 2222 } 2223 2224 mii = device_get_softc(sc->bge_miibus); 2225 mii_tick(mii); 2226 2227 if (!sc->bge_link) { 2228 mii_pollstat(mii); 2229 if (mii->mii_media_status & IFM_ACTIVE && 2230 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2231 sc->bge_link++; 2232 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2233 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2234 if_printf(ifp, "gigabit link up\n"); 2235 if (!ifq_is_empty(&ifp->if_snd)) 2236 (*ifp->if_start)(ifp); 2237 } 2238 } 2239 2240 crit_exit(); 2241 } 2242 2243 static void 2244 bge_stats_update_regs(struct bge_softc *sc) 2245 { 2246 struct ifnet *ifp = &sc->arpcom.ac_if; 2247 struct bge_mac_stats_regs stats; 2248 uint32_t *s; 2249 int i; 2250 2251 s = (uint32_t *)&stats; 2252 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2253 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2254 s++; 2255 } 2256 2257 ifp->if_collisions += 2258 (stats.dot3StatsSingleCollisionFrames + 2259 stats.dot3StatsMultipleCollisionFrames + 2260 stats.dot3StatsExcessiveCollisions + 2261 stats.dot3StatsLateCollisions) - 2262 ifp->if_collisions; 2263 } 2264 2265 static void 2266 bge_stats_update(struct bge_softc *sc) 2267 { 2268 struct ifnet *ifp = &sc->arpcom.ac_if; 2269 struct bge_stats *stats; 2270 2271 stats = (struct bge_stats *)(sc->bge_vhandle + 2272 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2273 2274 ifp->if_collisions += 2275 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 2276 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 2277 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 2278 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 2279 ifp->if_collisions; 2280 2281 #ifdef notdef 2282 ifp->if_collisions += 2283 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2284 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2285 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2286 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2287 ifp->if_collisions; 2288 #endif 2289 } 2290 2291 /* 2292 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2293 * pointers to descriptors. 2294 */ 2295 static int 2296 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2297 { 2298 struct bge_tx_bd *f = NULL; 2299 struct mbuf *m; 2300 uint32_t frag, cur, cnt = 0; 2301 uint16_t csum_flags = 0; 2302 struct ifvlan *ifv = NULL; 2303 2304 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2305 m_head->m_pkthdr.rcvif != NULL && 2306 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2307 ifv = m_head->m_pkthdr.rcvif->if_softc; 2308 2309 m = m_head; 2310 cur = frag = *txidx; 2311 2312 if (m_head->m_pkthdr.csum_flags) { 2313 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2314 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2315 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2316 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2317 if (m_head->m_flags & M_LASTFRAG) 2318 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2319 else if (m_head->m_flags & M_FRAG) 2320 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2321 } 2322 /* 2323 * Start packing the mbufs in this chain into 2324 * the fragment pointers. Stop when we run out 2325 * of fragments or hit the end of the mbuf chain. 2326 */ 2327 for (m = m_head; m != NULL; m = m->m_next) { 2328 if (m->m_len != 0) { 2329 f = &sc->bge_rdata->bge_tx_ring[frag]; 2330 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2331 break; 2332 BGE_HOSTADDR(f->bge_addr, 2333 vtophys(mtod(m, vm_offset_t))); 2334 f->bge_len = m->m_len; 2335 f->bge_flags = csum_flags; 2336 if (ifv != NULL) { 2337 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2338 f->bge_vlan_tag = ifv->ifv_tag; 2339 } else { 2340 f->bge_vlan_tag = 0; 2341 } 2342 /* 2343 * Sanity check: avoid coming within 16 descriptors 2344 * of the end of the ring. 2345 */ 2346 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2347 return(ENOBUFS); 2348 cur = frag; 2349 BGE_INC(frag, BGE_TX_RING_CNT); 2350 cnt++; 2351 } 2352 } 2353 2354 if (m != NULL) 2355 return(ENOBUFS); 2356 2357 if (frag == sc->bge_tx_saved_considx) 2358 return(ENOBUFS); 2359 2360 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2361 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2362 sc->bge_txcnt += cnt; 2363 2364 *txidx = frag; 2365 2366 return(0); 2367 } 2368 2369 /* 2370 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2371 * to the mbuf data regions directly in the transmit descriptors. 2372 */ 2373 static void 2374 bge_start(struct ifnet *ifp) 2375 { 2376 struct bge_softc *sc; 2377 struct mbuf *m_head = NULL; 2378 uint32_t prodidx = 0; 2379 2380 sc = ifp->if_softc; 2381 2382 if (!sc->bge_link) 2383 return; 2384 2385 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2386 2387 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2388 m_head = ifq_poll(&ifp->if_snd); 2389 if (m_head == NULL) 2390 break; 2391 2392 /* 2393 * XXX 2394 * safety overkill. If this is a fragmented packet chain 2395 * with delayed TCP/UDP checksums, then only encapsulate 2396 * it if we have enough descriptors to handle the entire 2397 * chain at once. 2398 * (paranoia -- may not actually be needed) 2399 */ 2400 if (m_head->m_flags & M_FIRSTFRAG && 2401 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2402 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2403 m_head->m_pkthdr.csum_data + 16) { 2404 ifp->if_flags |= IFF_OACTIVE; 2405 break; 2406 } 2407 } 2408 2409 /* 2410 * Pack the data into the transmit ring. If we 2411 * don't have room, set the OACTIVE flag and wait 2412 * for the NIC to drain the ring. 2413 */ 2414 if (bge_encap(sc, m_head, &prodidx)) { 2415 ifp->if_flags |= IFF_OACTIVE; 2416 break; 2417 } 2418 m_head = ifq_dequeue(&ifp->if_snd); 2419 2420 BPF_MTAP(ifp, m_head); 2421 } 2422 2423 /* Transmit */ 2424 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2425 /* 5700 b2 errata */ 2426 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2427 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2428 2429 /* 2430 * Set a timeout in case the chip goes out to lunch. 2431 */ 2432 ifp->if_timer = 5; 2433 } 2434 2435 static void 2436 bge_init(void *xsc) 2437 { 2438 struct bge_softc *sc = xsc; 2439 struct ifnet *ifp = &sc->arpcom.ac_if; 2440 uint16_t *m; 2441 2442 crit_enter(); 2443 2444 if (ifp->if_flags & IFF_RUNNING) { 2445 crit_exit(); 2446 return; 2447 } 2448 2449 /* Cancel pending I/O and flush buffers. */ 2450 bge_stop(sc); 2451 bge_reset(sc); 2452 bge_chipinit(sc); 2453 2454 /* 2455 * Init the various state machines, ring 2456 * control blocks and firmware. 2457 */ 2458 if (bge_blockinit(sc)) { 2459 if_printf(ifp, "initialization failure\n"); 2460 crit_exit(); 2461 return; 2462 } 2463 2464 /* Specify MTU. */ 2465 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2466 ETHER_HDR_LEN + ETHER_CRC_LEN); 2467 2468 /* Load our MAC address. */ 2469 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 2470 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2471 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2472 2473 /* Enable or disable promiscuous mode as needed. */ 2474 if (ifp->if_flags & IFF_PROMISC) { 2475 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2476 } else { 2477 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2478 } 2479 2480 /* Program multicast filter. */ 2481 bge_setmulti(sc); 2482 2483 /* Init RX ring. */ 2484 bge_init_rx_ring_std(sc); 2485 2486 /* 2487 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 2488 * memory to insure that the chip has in fact read the first 2489 * entry of the ring. 2490 */ 2491 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 2492 uint32_t v, i; 2493 for (i = 0; i < 10; i++) { 2494 DELAY(20); 2495 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 2496 if (v == (MCLBYTES - ETHER_ALIGN)) 2497 break; 2498 } 2499 if (i == 10) 2500 if_printf(ifp, "5705 A0 chip failed to load RX ring\n"); 2501 } 2502 2503 /* Init jumbo RX ring. */ 2504 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2505 bge_init_rx_ring_jumbo(sc); 2506 2507 /* Init our RX return ring index */ 2508 sc->bge_rx_saved_considx = 0; 2509 2510 /* Init TX ring. */ 2511 bge_init_tx_ring(sc); 2512 2513 /* Turn on transmitter */ 2514 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2515 2516 /* Turn on receiver */ 2517 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2518 2519 /* Tell firmware we're alive. */ 2520 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2521 2522 /* Enable host interrupts. */ 2523 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2524 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2525 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2526 2527 bge_ifmedia_upd(ifp); 2528 2529 ifp->if_flags |= IFF_RUNNING; 2530 ifp->if_flags &= ~IFF_OACTIVE; 2531 2532 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 2533 2534 crit_exit(); 2535 } 2536 2537 /* 2538 * Set media options. 2539 */ 2540 static int 2541 bge_ifmedia_upd(struct ifnet *ifp) 2542 { 2543 struct bge_softc *sc = ifp->if_softc; 2544 struct ifmedia *ifm = &sc->bge_ifmedia; 2545 struct mii_data *mii; 2546 2547 /* If this is a 1000baseX NIC, enable the TBI port. */ 2548 if (sc->bge_tbi) { 2549 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2550 return(EINVAL); 2551 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2552 case IFM_AUTO: 2553 #ifndef BGE_FAKE_AUTONEG 2554 /* 2555 * The BCM5704 ASIC appears to have a special 2556 * mechanism for programming the autoneg 2557 * advertisement registers in TBI mode. 2558 */ 2559 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 2560 uint32_t sgdig; 2561 2562 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 2563 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 2564 sgdig |= BGE_SGDIGCFG_AUTO | 2565 BGE_SGDIGCFG_PAUSE_CAP | 2566 BGE_SGDIGCFG_ASYM_PAUSE; 2567 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 2568 sgdig | BGE_SGDIGCFG_SEND); 2569 DELAY(5); 2570 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 2571 } 2572 #endif /* !BEG_FAKE_AUTONEG */ 2573 break; 2574 case IFM_1000_SX: 2575 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2576 BGE_CLRBIT(sc, BGE_MAC_MODE, 2577 BGE_MACMODE_HALF_DUPLEX); 2578 } else { 2579 BGE_SETBIT(sc, BGE_MAC_MODE, 2580 BGE_MACMODE_HALF_DUPLEX); 2581 } 2582 break; 2583 default: 2584 return(EINVAL); 2585 } 2586 return(0); 2587 } 2588 2589 mii = device_get_softc(sc->bge_miibus); 2590 sc->bge_link = 0; 2591 if (mii->mii_instance) { 2592 struct mii_softc *miisc; 2593 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2594 miisc = LIST_NEXT(miisc, mii_list)) 2595 mii_phy_reset(miisc); 2596 } 2597 mii_mediachg(mii); 2598 2599 return(0); 2600 } 2601 2602 /* 2603 * Report current media status. 2604 */ 2605 static void 2606 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2607 { 2608 struct bge_softc *sc = ifp->if_softc; 2609 struct mii_data *mii; 2610 2611 if (sc->bge_tbi) { 2612 ifmr->ifm_status = IFM_AVALID; 2613 ifmr->ifm_active = IFM_ETHER; 2614 if (CSR_READ_4(sc, BGE_MAC_STS) & 2615 BGE_MACSTAT_TBI_PCS_SYNCHED) 2616 ifmr->ifm_status |= IFM_ACTIVE; 2617 ifmr->ifm_active |= IFM_1000_SX; 2618 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2619 ifmr->ifm_active |= IFM_HDX; 2620 else 2621 ifmr->ifm_active |= IFM_FDX; 2622 return; 2623 } 2624 2625 mii = device_get_softc(sc->bge_miibus); 2626 mii_pollstat(mii); 2627 ifmr->ifm_active = mii->mii_media_active; 2628 ifmr->ifm_status = mii->mii_media_status; 2629 } 2630 2631 static int 2632 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2633 { 2634 struct bge_softc *sc = ifp->if_softc; 2635 struct ifreq *ifr = (struct ifreq *) data; 2636 int mask, error = 0; 2637 struct mii_data *mii; 2638 2639 crit_enter(); 2640 2641 switch(command) { 2642 case SIOCSIFMTU: 2643 /* Disallow jumbo frames on 5705/5750. */ 2644 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 || 2645 sc->bge_asicrev == BGE_ASICREV_BCM5750) && 2646 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 2647 error = EINVAL; 2648 else { 2649 ifp->if_mtu = ifr->ifr_mtu; 2650 ifp->if_flags &= ~IFF_RUNNING; 2651 bge_init(sc); 2652 } 2653 break; 2654 case SIOCSIFFLAGS: 2655 if (ifp->if_flags & IFF_UP) { 2656 /* 2657 * If only the state of the PROMISC flag changed, 2658 * then just use the 'set promisc mode' command 2659 * instead of reinitializing the entire NIC. Doing 2660 * a full re-init means reloading the firmware and 2661 * waiting for it to start up, which may take a 2662 * second or two. 2663 */ 2664 if (ifp->if_flags & IFF_RUNNING && 2665 ifp->if_flags & IFF_PROMISC && 2666 !(sc->bge_if_flags & IFF_PROMISC)) { 2667 BGE_SETBIT(sc, BGE_RX_MODE, 2668 BGE_RXMODE_RX_PROMISC); 2669 } else if (ifp->if_flags & IFF_RUNNING && 2670 !(ifp->if_flags & IFF_PROMISC) && 2671 sc->bge_if_flags & IFF_PROMISC) { 2672 BGE_CLRBIT(sc, BGE_RX_MODE, 2673 BGE_RXMODE_RX_PROMISC); 2674 } else 2675 bge_init(sc); 2676 } else { 2677 if (ifp->if_flags & IFF_RUNNING) { 2678 bge_stop(sc); 2679 } 2680 } 2681 sc->bge_if_flags = ifp->if_flags; 2682 error = 0; 2683 break; 2684 case SIOCADDMULTI: 2685 case SIOCDELMULTI: 2686 if (ifp->if_flags & IFF_RUNNING) { 2687 bge_setmulti(sc); 2688 error = 0; 2689 } 2690 break; 2691 case SIOCSIFMEDIA: 2692 case SIOCGIFMEDIA: 2693 if (sc->bge_tbi) { 2694 error = ifmedia_ioctl(ifp, ifr, 2695 &sc->bge_ifmedia, command); 2696 } else { 2697 mii = device_get_softc(sc->bge_miibus); 2698 error = ifmedia_ioctl(ifp, ifr, 2699 &mii->mii_media, command); 2700 } 2701 break; 2702 case SIOCSIFCAP: 2703 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2704 if (mask & IFCAP_HWCSUM) { 2705 if (IFCAP_HWCSUM & ifp->if_capenable) 2706 ifp->if_capenable &= ~IFCAP_HWCSUM; 2707 else 2708 ifp->if_capenable |= IFCAP_HWCSUM; 2709 } 2710 error = 0; 2711 break; 2712 default: 2713 error = ether_ioctl(ifp, command, data); 2714 break; 2715 } 2716 2717 crit_exit(); 2718 2719 return(error); 2720 } 2721 2722 static void 2723 bge_watchdog(struct ifnet *ifp) 2724 { 2725 struct bge_softc *sc = ifp->if_softc; 2726 2727 if_printf(ifp, "watchdog timeout -- resetting\n"); 2728 2729 ifp->if_flags &= ~IFF_RUNNING; 2730 bge_init(sc); 2731 2732 ifp->if_oerrors++; 2733 } 2734 2735 /* 2736 * Stop the adapter and free any mbufs allocated to the 2737 * RX and TX lists. 2738 */ 2739 static void 2740 bge_stop(struct bge_softc *sc) 2741 { 2742 struct ifnet *ifp = &sc->arpcom.ac_if; 2743 struct ifmedia_entry *ifm; 2744 struct mii_data *mii = NULL; 2745 int mtmp, itmp; 2746 2747 if (!sc->bge_tbi) 2748 mii = device_get_softc(sc->bge_miibus); 2749 2750 callout_stop(&sc->bge_stat_timer); 2751 2752 /* 2753 * Disable all of the receiver blocks 2754 */ 2755 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2756 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2757 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2758 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2759 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2760 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2761 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2762 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2763 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2764 2765 /* 2766 * Disable all of the transmit blocks 2767 */ 2768 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2769 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2770 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2771 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2772 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2773 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2774 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2775 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2776 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2777 2778 /* 2779 * Shut down all of the memory managers and related 2780 * state machines. 2781 */ 2782 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2783 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2784 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2785 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2786 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2787 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2788 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2789 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2790 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 2791 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2792 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2793 } 2794 2795 /* Disable host interrupts. */ 2796 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2797 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2798 2799 /* 2800 * Tell firmware we're shutting down. 2801 */ 2802 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2803 2804 /* Free the RX lists. */ 2805 bge_free_rx_ring_std(sc); 2806 2807 /* Free jumbo RX list. */ 2808 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2809 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2810 bge_free_rx_ring_jumbo(sc); 2811 2812 /* Free TX buffers. */ 2813 bge_free_tx_ring(sc); 2814 2815 /* 2816 * Isolate/power down the PHY, but leave the media selection 2817 * unchanged so that things will be put back to normal when 2818 * we bring the interface back up. 2819 */ 2820 if (!sc->bge_tbi) { 2821 itmp = ifp->if_flags; 2822 ifp->if_flags |= IFF_UP; 2823 ifm = mii->mii_media.ifm_cur; 2824 mtmp = ifm->ifm_media; 2825 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2826 mii_mediachg(mii); 2827 ifm->ifm_media = mtmp; 2828 ifp->if_flags = itmp; 2829 } 2830 2831 sc->bge_link = 0; 2832 2833 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2834 2835 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2836 } 2837 2838 /* 2839 * Stop all chip I/O so that the kernel's probe routines don't 2840 * get confused by errant DMAs when rebooting. 2841 */ 2842 static void 2843 bge_shutdown(device_t dev) 2844 { 2845 struct bge_softc *sc = device_get_softc(dev); 2846 2847 bge_stop(sc); 2848 bge_reset(sc); 2849 } 2850