1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.25 2005/01/23 20:21:30 joerg Exp $ 35 * 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/sockio.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/queue.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/vlan/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <vm/vm.h> /* for vtophys */ 100 #include <vm/pmap.h> /* for vtophys */ 101 #include <machine/clock.h> /* for DELAY */ 102 #include <machine/bus_memio.h> 103 #include <machine/bus.h> 104 #include <machine/resource.h> 105 #include <sys/bus.h> 106 #include <sys/rman.h> 107 108 #include <dev/netif/mii_layer/mii.h> 109 #include <dev/netif/mii_layer/miivar.h> 110 #include <dev/netif/mii_layer/miidevs.h> 111 #include <dev/netif/mii_layer/brgphyreg.h> 112 113 #include <bus/pci/pcidevs.h> 114 #include <bus/pci/pcireg.h> 115 #include <bus/pci/pcivar.h> 116 117 #include "if_bgereg.h" 118 119 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 /* 125 * Various supported device vendors/types and their names. Note: the 126 * spec seems to indicate that the hardware still has Alteon's vendor 127 * ID burned into it, though it will always be overriden by the vendor 128 * ID in the EEPROM. Just to be safe, we cover all possibilities. 129 */ 130 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 131 132 static struct bge_type bge_devs[] = { 133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 134 "Broadcom BCM5700 Gigabit Ethernet" }, 135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 136 "Broadcom BCM5701 Gigabit Ethernet" }, 137 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700, 138 "Broadcom BCM5700 Gigabit Ethernet" }, 139 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701, 140 "Broadcom BCM5701 Gigabit Ethernet" }, 141 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X, 142 "Broadcom BCM5702X Gigabit Ethernet" }, 143 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5702X, 144 "Broadcom BCM5702X Gigabit Ethernet" }, 145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X, 146 "Broadcom BCM5703X Gigabit Ethernet" }, 147 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5703X, 148 "Broadcom BCM5703X Gigabit Ethernet" }, 149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C, 150 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S, 152 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705, 154 "Broadcom BCM5705 Gigabit Ethernet" }, 155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M, 156 "Broadcom BCM5705M Gigabit Ethernet" }, 157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705_ALT, 158 "Broadcom BCM5705M Gigabit Ethernet" }, 159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782, 160 "Broadcom BCM5782 Gigabit Ethernet" }, 161 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5788, 162 "Broadcom BCM5788 Gigabit Ethernet" }, 163 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901, 164 "Broadcom BCM5901 Fast Ethernet" }, 165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2, 166 "Broadcom BCM5901A2 Fast Ethernet" }, 167 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 168 "SysKonnect Gigabit Ethernet" }, 169 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000, 170 "Altima AC1000 Gigabit Ethernet" }, 171 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001, 172 "Altima AC1002 Gigabit Ethernet" }, 173 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100, 174 "Altima AC9100 Gigabit Ethernet" }, 175 { 0, 0, NULL } 176 }; 177 178 static int bge_probe (device_t); 179 static int bge_attach (device_t); 180 static int bge_detach (device_t); 181 static void bge_release_resources 182 (struct bge_softc *); 183 static void bge_txeof (struct bge_softc *); 184 static void bge_rxeof (struct bge_softc *); 185 186 static void bge_tick (void *); 187 static void bge_stats_update (struct bge_softc *); 188 static void bge_stats_update_regs 189 (struct bge_softc *); 190 static int bge_encap (struct bge_softc *, struct mbuf *, 191 u_int32_t *); 192 193 static void bge_intr (void *); 194 static void bge_start (struct ifnet *); 195 static int bge_ioctl (struct ifnet *, u_long, caddr_t, 196 struct ucred *); 197 static void bge_init (void *); 198 static void bge_stop (struct bge_softc *); 199 static void bge_watchdog (struct ifnet *); 200 static void bge_shutdown (device_t); 201 static int bge_ifmedia_upd (struct ifnet *); 202 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 203 204 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, 205 int, u_int8_t *); 206 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 207 208 static u_int32_t bge_crc (caddr_t); 209 static void bge_setmulti (struct bge_softc *); 210 211 static void bge_handle_events (struct bge_softc *); 212 static int bge_alloc_jumbo_mem (struct bge_softc *); 213 static void bge_free_jumbo_mem (struct bge_softc *); 214 static void *bge_jalloc (struct bge_softc *); 215 static void bge_jfree (caddr_t, u_int); 216 static void bge_jref (caddr_t, u_int); 217 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 218 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 219 static int bge_init_rx_ring_std (struct bge_softc *); 220 static void bge_free_rx_ring_std (struct bge_softc *); 221 static int bge_init_rx_ring_jumbo (struct bge_softc *); 222 static void bge_free_rx_ring_jumbo (struct bge_softc *); 223 static void bge_free_tx_ring (struct bge_softc *); 224 static int bge_init_tx_ring (struct bge_softc *); 225 226 static int bge_chipinit (struct bge_softc *); 227 static int bge_blockinit (struct bge_softc *); 228 229 #ifdef notdef 230 static u_int8_t bge_vpd_readbyte (struct bge_softc *, int); 231 static void bge_vpd_read_res (struct bge_softc *, 232 struct vpd_res *, int); 233 static void bge_vpd_read (struct bge_softc *); 234 #endif 235 236 static u_int32_t bge_readmem_ind 237 (struct bge_softc *, int); 238 static void bge_writemem_ind (struct bge_softc *, int, int); 239 #ifdef notdef 240 static u_int32_t bge_readreg_ind 241 (struct bge_softc *, int); 242 #endif 243 static void bge_writereg_ind (struct bge_softc *, int, int); 244 245 static int bge_miibus_readreg (device_t, int, int); 246 static int bge_miibus_writereg (device_t, int, int, int); 247 static void bge_miibus_statchg (device_t); 248 249 static void bge_reset (struct bge_softc *); 250 251 static device_method_t bge_methods[] = { 252 /* Device interface */ 253 DEVMETHOD(device_probe, bge_probe), 254 DEVMETHOD(device_attach, bge_attach), 255 DEVMETHOD(device_detach, bge_detach), 256 DEVMETHOD(device_shutdown, bge_shutdown), 257 258 /* bus interface */ 259 DEVMETHOD(bus_print_child, bus_generic_print_child), 260 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 261 262 /* MII interface */ 263 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 264 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 265 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 266 267 { 0, 0 } 268 }; 269 270 static driver_t bge_driver = { 271 "bge", 272 bge_methods, 273 sizeof(struct bge_softc) 274 }; 275 276 static devclass_t bge_devclass; 277 278 DECLARE_DUMMY_MODULE(if_bge); 279 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 280 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 281 282 static u_int32_t 283 bge_readmem_ind(sc, off) 284 struct bge_softc *sc; 285 int off; 286 { 287 device_t dev; 288 289 dev = sc->bge_dev; 290 291 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 292 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 293 } 294 295 static void 296 bge_writemem_ind(sc, off, val) 297 struct bge_softc *sc; 298 int off, val; 299 { 300 device_t dev; 301 302 dev = sc->bge_dev; 303 304 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 305 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 306 307 return; 308 } 309 310 #ifdef notdef 311 static u_int32_t 312 bge_readreg_ind(sc, off) 313 struct bge_softc *sc; 314 int off; 315 { 316 device_t dev; 317 318 dev = sc->bge_dev; 319 320 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 321 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 322 } 323 #endif 324 325 static void 326 bge_writereg_ind(sc, off, val) 327 struct bge_softc *sc; 328 int off, val; 329 { 330 device_t dev; 331 332 dev = sc->bge_dev; 333 334 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 335 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 336 337 return; 338 } 339 340 #ifdef notdef 341 static u_int8_t 342 bge_vpd_readbyte(sc, addr) 343 struct bge_softc *sc; 344 int addr; 345 { 346 int i; 347 device_t dev; 348 u_int32_t val; 349 350 dev = sc->bge_dev; 351 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 352 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 353 DELAY(10); 354 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 355 break; 356 } 357 358 if (i == BGE_TIMEOUT) { 359 printf("bge%d: VPD read timed out\n", sc->bge_unit); 360 return(0); 361 } 362 363 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 364 365 return((val >> ((addr % 4) * 8)) & 0xFF); 366 } 367 368 static void 369 bge_vpd_read_res(sc, res, addr) 370 struct bge_softc *sc; 371 struct vpd_res *res; 372 int addr; 373 { 374 int i; 375 u_int8_t *ptr; 376 377 ptr = (u_int8_t *)res; 378 for (i = 0; i < sizeof(struct vpd_res); i++) 379 ptr[i] = bge_vpd_readbyte(sc, i + addr); 380 381 return; 382 } 383 384 static void 385 bge_vpd_read(sc) 386 struct bge_softc *sc; 387 { 388 int pos = 0, i; 389 struct vpd_res res; 390 391 if (sc->bge_vpd_prodname != NULL) 392 free(sc->bge_vpd_prodname, M_DEVBUF); 393 if (sc->bge_vpd_readonly != NULL) 394 free(sc->bge_vpd_readonly, M_DEVBUF); 395 sc->bge_vpd_prodname = NULL; 396 sc->bge_vpd_readonly = NULL; 397 398 bge_vpd_read_res(sc, &res, pos); 399 400 if (res.vr_id != VPD_RES_ID) { 401 printf("bge%d: bad VPD resource id: expected %x got %x\n", 402 sc->bge_unit, VPD_RES_ID, res.vr_id); 403 return; 404 } 405 406 pos += sizeof(res); 407 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 408 for (i = 0; i < res.vr_len; i++) 409 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 410 sc->bge_vpd_prodname[i] = '\0'; 411 pos += i; 412 413 bge_vpd_read_res(sc, &res, pos); 414 415 if (res.vr_id != VPD_RES_READ) { 416 printf("bge%d: bad VPD resource id: expected %x got %x\n", 417 sc->bge_unit, VPD_RES_READ, res.vr_id); 418 return; 419 } 420 421 pos += sizeof(res); 422 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 423 for (i = 0; i < res.vr_len + 1; i++) 424 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 425 426 return; 427 } 428 #endif 429 430 /* 431 * Read a byte of data stored in the EEPROM at address 'addr.' The 432 * BCM570x supports both the traditional bitbang interface and an 433 * auto access interface for reading the EEPROM. We use the auto 434 * access method. 435 */ 436 static u_int8_t 437 bge_eeprom_getbyte(sc, addr, dest) 438 struct bge_softc *sc; 439 int addr; 440 u_int8_t *dest; 441 { 442 int i; 443 u_int32_t byte = 0; 444 445 /* 446 * Enable use of auto EEPROM access so we can avoid 447 * having to use the bitbang method. 448 */ 449 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 450 451 /* Reset the EEPROM, load the clock period. */ 452 CSR_WRITE_4(sc, BGE_EE_ADDR, 453 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 454 DELAY(20); 455 456 /* Issue the read EEPROM command. */ 457 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 458 459 /* Wait for completion */ 460 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 461 DELAY(10); 462 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 463 break; 464 } 465 466 if (i == BGE_TIMEOUT) { 467 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 468 return(0); 469 } 470 471 /* Get result. */ 472 byte = CSR_READ_4(sc, BGE_EE_DATA); 473 474 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 475 476 return(0); 477 } 478 479 /* 480 * Read a sequence of bytes from the EEPROM. 481 */ 482 static int 483 bge_read_eeprom(sc, dest, off, cnt) 484 struct bge_softc *sc; 485 caddr_t dest; 486 int off; 487 int cnt; 488 { 489 int err = 0, i; 490 u_int8_t byte = 0; 491 492 for (i = 0; i < cnt; i++) { 493 err = bge_eeprom_getbyte(sc, off + i, &byte); 494 if (err) 495 break; 496 *(dest + i) = byte; 497 } 498 499 return(err ? 1 : 0); 500 } 501 502 static int 503 bge_miibus_readreg(dev, phy, reg) 504 device_t dev; 505 int phy, reg; 506 { 507 struct bge_softc *sc; 508 struct ifnet *ifp; 509 u_int32_t val, autopoll; 510 int i; 511 512 sc = device_get_softc(dev); 513 ifp = &sc->arpcom.ac_if; 514 515 /* 516 * Broadcom's own driver always assumes the internal 517 * PHY is at GMII address 1. On some chips, the PHY responds 518 * to accesses at all addresses, which could cause us to 519 * bogusly attach the PHY 32 times at probe type. Always 520 * restricting the lookup to address 1 is simpler than 521 * trying to figure out which chips revisions should be 522 * special-cased. 523 */ 524 if (phy != 1) 525 return(0); 526 527 /* Reading with autopolling on may trigger PCI errors */ 528 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 529 if (autopoll & BGE_MIMODE_AUTOPOLL) { 530 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 531 DELAY(40); 532 } 533 534 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 535 BGE_MIPHY(phy)|BGE_MIREG(reg)); 536 537 for (i = 0; i < BGE_TIMEOUT; i++) { 538 val = CSR_READ_4(sc, BGE_MI_COMM); 539 if (!(val & BGE_MICOMM_BUSY)) 540 break; 541 } 542 543 if (i == BGE_TIMEOUT) { 544 printf("bge%d: PHY read timed out\n", sc->bge_unit); 545 val = 0; 546 goto done; 547 } 548 549 val = CSR_READ_4(sc, BGE_MI_COMM); 550 551 done: 552 if (autopoll & BGE_MIMODE_AUTOPOLL) { 553 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 554 DELAY(40); 555 } 556 557 if (val & BGE_MICOMM_READFAIL) 558 return(0); 559 560 return(val & 0xFFFF); 561 } 562 563 static int 564 bge_miibus_writereg(dev, phy, reg, val) 565 device_t dev; 566 int phy, reg, val; 567 { 568 struct bge_softc *sc; 569 u_int32_t autopoll; 570 int i; 571 572 sc = device_get_softc(dev); 573 574 /* Reading with autopolling on may trigger PCI errors */ 575 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 576 if (autopoll & BGE_MIMODE_AUTOPOLL) { 577 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 578 DELAY(40); 579 } 580 581 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 582 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 583 584 for (i = 0; i < BGE_TIMEOUT; i++) { 585 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 586 break; 587 } 588 589 if (autopoll & BGE_MIMODE_AUTOPOLL) { 590 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 591 DELAY(40); 592 } 593 594 if (i == BGE_TIMEOUT) { 595 printf("bge%d: PHY read timed out\n", sc->bge_unit); 596 return(0); 597 } 598 599 return(0); 600 } 601 602 static void 603 bge_miibus_statchg(dev) 604 device_t dev; 605 { 606 struct bge_softc *sc; 607 struct mii_data *mii; 608 609 sc = device_get_softc(dev); 610 mii = device_get_softc(sc->bge_miibus); 611 612 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 613 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 614 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 615 } else { 616 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 617 } 618 619 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 620 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 621 } else { 622 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 623 } 624 625 return; 626 } 627 628 /* 629 * Handle events that have triggered interrupts. 630 */ 631 static void 632 bge_handle_events(sc) 633 struct bge_softc *sc; 634 { 635 636 return; 637 } 638 639 /* 640 * Memory management for jumbo frames. 641 */ 642 643 static int 644 bge_alloc_jumbo_mem(sc) 645 struct bge_softc *sc; 646 { 647 caddr_t ptr; 648 int i; 649 struct bge_jpool_entry *entry; 650 651 /* Grab a big chunk o' storage. */ 652 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 653 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 654 655 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 656 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 657 return(ENOBUFS); 658 } 659 660 SLIST_INIT(&sc->bge_jfree_listhead); 661 SLIST_INIT(&sc->bge_jinuse_listhead); 662 663 /* 664 * Now divide it up into 9K pieces and save the addresses 665 * in an array. Note that we play an evil trick here by using 666 * the first few bytes in the buffer to hold the the address 667 * of the softc structure for this interface. This is because 668 * bge_jfree() needs it, but it is called by the mbuf management 669 * code which will not pass it to us explicitly. 670 */ 671 ptr = sc->bge_cdata.bge_jumbo_buf; 672 for (i = 0; i < BGE_JSLOTS; i++) { 673 u_int64_t **aptr; 674 aptr = (u_int64_t **)ptr; 675 aptr[0] = (u_int64_t *)sc; 676 ptr += sizeof(u_int64_t); 677 sc->bge_cdata.bge_jslots[i].bge_buf = ptr; 678 sc->bge_cdata.bge_jslots[i].bge_inuse = 0; 679 ptr += (BGE_JLEN - sizeof(u_int64_t)); 680 entry = malloc(sizeof(struct bge_jpool_entry), 681 M_DEVBUF, M_INTWAIT); 682 entry->slot = i; 683 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 684 entry, jpool_entries); 685 } 686 687 return(0); 688 } 689 690 static void 691 bge_free_jumbo_mem(sc) 692 struct bge_softc *sc; 693 { 694 int i; 695 struct bge_jpool_entry *entry; 696 697 for (i = 0; i < BGE_JSLOTS; i++) { 698 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 699 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 700 free(entry, M_DEVBUF); 701 } 702 703 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 704 705 return; 706 } 707 708 /* 709 * Allocate a jumbo buffer. 710 */ 711 static void * 712 bge_jalloc(sc) 713 struct bge_softc *sc; 714 { 715 struct bge_jpool_entry *entry; 716 717 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 718 719 if (entry == NULL) { 720 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 721 return(NULL); 722 } 723 724 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 725 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 726 sc->bge_cdata.bge_jslots[entry->slot].bge_inuse = 1; 727 return(sc->bge_cdata.bge_jslots[entry->slot].bge_buf); 728 } 729 730 /* 731 * Adjust usage count on a jumbo buffer. 732 */ 733 static void 734 bge_jref(buf, size) 735 caddr_t buf; 736 u_int size; 737 { 738 struct bge_softc *sc; 739 u_int64_t **aptr; 740 int i; 741 742 /* Extract the softc struct pointer. */ 743 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 744 sc = (struct bge_softc *)(aptr[0]); 745 746 if (sc == NULL) 747 panic("bge_jref: can't find softc pointer!"); 748 749 if (size != BGE_JUMBO_FRAMELEN) 750 panic("bge_jref: adjusting refcount of buf of wrong size!"); 751 752 /* calculate the slot this buffer belongs to */ 753 754 i = ((vm_offset_t)aptr 755 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 756 757 if ((i < 0) || (i >= BGE_JSLOTS)) 758 panic("bge_jref: asked to reference buffer " 759 "that we don't manage!"); 760 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0) 761 panic("bge_jref: buffer already free!"); 762 else 763 sc->bge_cdata.bge_jslots[i].bge_inuse++; 764 765 return; 766 } 767 768 /* 769 * Release a jumbo buffer. 770 */ 771 static void 772 bge_jfree(buf, size) 773 caddr_t buf; 774 u_int size; 775 { 776 struct bge_softc *sc; 777 u_int64_t **aptr; 778 int i; 779 struct bge_jpool_entry *entry; 780 781 /* Extract the softc struct pointer. */ 782 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 783 sc = (struct bge_softc *)(aptr[0]); 784 785 if (sc == NULL) 786 panic("bge_jfree: can't find softc pointer!"); 787 788 if (size != BGE_JUMBO_FRAMELEN) 789 panic("bge_jfree: freeing buffer of wrong size!"); 790 791 /* calculate the slot this buffer belongs to */ 792 793 i = ((vm_offset_t)aptr 794 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 795 796 if ((i < 0) || (i >= BGE_JSLOTS)) 797 panic("bge_jfree: asked to free buffer that we don't manage!"); 798 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0) 799 panic("bge_jfree: buffer already free!"); 800 else { 801 sc->bge_cdata.bge_jslots[i].bge_inuse--; 802 if(sc->bge_cdata.bge_jslots[i].bge_inuse == 0) { 803 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 804 if (entry == NULL) 805 panic("bge_jfree: buffer not in use!"); 806 entry->slot = i; 807 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, 808 jpool_entries); 809 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 810 entry, jpool_entries); 811 } 812 } 813 814 return; 815 } 816 817 818 /* 819 * Intialize a standard receive ring descriptor. 820 */ 821 static int 822 bge_newbuf_std(sc, i, m) 823 struct bge_softc *sc; 824 int i; 825 struct mbuf *m; 826 { 827 struct mbuf *m_new = NULL; 828 struct bge_rx_bd *r; 829 830 if (m == NULL) { 831 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 832 if (m_new == NULL) { 833 return(ENOBUFS); 834 } 835 836 MCLGET(m_new, MB_DONTWAIT); 837 if (!(m_new->m_flags & M_EXT)) { 838 m_freem(m_new); 839 return(ENOBUFS); 840 } 841 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 842 } else { 843 m_new = m; 844 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 845 m_new->m_data = m_new->m_ext.ext_buf; 846 } 847 848 if (!sc->bge_rx_alignment_bug) 849 m_adj(m_new, ETHER_ALIGN); 850 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 851 r = &sc->bge_rdata->bge_rx_std_ring[i]; 852 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 853 r->bge_flags = BGE_RXBDFLAG_END; 854 r->bge_len = m_new->m_len; 855 r->bge_idx = i; 856 857 return(0); 858 } 859 860 /* 861 * Initialize a jumbo receive ring descriptor. This allocates 862 * a jumbo buffer from the pool managed internally by the driver. 863 */ 864 static int 865 bge_newbuf_jumbo(sc, i, m) 866 struct bge_softc *sc; 867 int i; 868 struct mbuf *m; 869 { 870 struct mbuf *m_new = NULL; 871 struct bge_rx_bd *r; 872 873 if (m == NULL) { 874 caddr_t *buf = NULL; 875 876 /* Allocate the mbuf. */ 877 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 878 if (m_new == NULL) { 879 return(ENOBUFS); 880 } 881 882 /* Allocate the jumbo buffer */ 883 buf = bge_jalloc(sc); 884 if (buf == NULL) { 885 m_freem(m_new); 886 printf("bge%d: jumbo allocation failed " 887 "-- packet dropped!\n", sc->bge_unit); 888 return(ENOBUFS); 889 } 890 891 /* Attach the buffer to the mbuf. */ 892 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 893 m_new->m_flags |= M_EXT | M_EXT_OLD; 894 m_new->m_len = m_new->m_pkthdr.len = 895 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 896 m_new->m_ext.ext_nfree.old = bge_jfree; 897 m_new->m_ext.ext_nref.old = bge_jref; 898 } else { 899 m_new = m; 900 m_new->m_data = m_new->m_ext.ext_buf; 901 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 902 } 903 904 if (!sc->bge_rx_alignment_bug) 905 m_adj(m_new, ETHER_ALIGN); 906 /* Set up the descriptor. */ 907 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 908 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 909 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 910 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 911 r->bge_len = m_new->m_len; 912 r->bge_idx = i; 913 914 return(0); 915 } 916 917 /* 918 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 919 * that's 1MB or memory, which is a lot. For now, we fill only the first 920 * 256 ring entries and hope that our CPU is fast enough to keep up with 921 * the NIC. 922 */ 923 static int 924 bge_init_rx_ring_std(sc) 925 struct bge_softc *sc; 926 { 927 int i; 928 929 for (i = 0; i < BGE_SSLOTS; i++) { 930 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 931 return(ENOBUFS); 932 }; 933 934 sc->bge_std = i - 1; 935 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 936 937 return(0); 938 } 939 940 static void 941 bge_free_rx_ring_std(sc) 942 struct bge_softc *sc; 943 { 944 int i; 945 946 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 947 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 948 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 949 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 950 } 951 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 952 sizeof(struct bge_rx_bd)); 953 } 954 955 return; 956 } 957 958 static int 959 bge_init_rx_ring_jumbo(sc) 960 struct bge_softc *sc; 961 { 962 int i; 963 struct bge_rcb *rcb; 964 965 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 966 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 967 return(ENOBUFS); 968 }; 969 970 sc->bge_jumbo = i - 1; 971 972 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 973 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 974 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 975 976 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 977 978 return(0); 979 } 980 981 static void 982 bge_free_rx_ring_jumbo(sc) 983 struct bge_softc *sc; 984 { 985 int i; 986 987 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 988 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 989 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 990 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 991 } 992 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 993 sizeof(struct bge_rx_bd)); 994 } 995 996 return; 997 } 998 999 static void 1000 bge_free_tx_ring(sc) 1001 struct bge_softc *sc; 1002 { 1003 int i; 1004 1005 if (sc->bge_rdata->bge_tx_ring == NULL) 1006 return; 1007 1008 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1009 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1010 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1011 sc->bge_cdata.bge_tx_chain[i] = NULL; 1012 } 1013 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 1014 sizeof(struct bge_tx_bd)); 1015 } 1016 1017 return; 1018 } 1019 1020 static int 1021 bge_init_tx_ring(sc) 1022 struct bge_softc *sc; 1023 { 1024 sc->bge_txcnt = 0; 1025 sc->bge_tx_saved_considx = 0; 1026 1027 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1028 /* 5700 b2 errata */ 1029 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1030 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1031 1032 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1033 /* 5700 b2 errata */ 1034 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1035 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1036 1037 return(0); 1038 } 1039 1040 #define BGE_POLY 0xEDB88320 1041 1042 static u_int32_t 1043 bge_crc(addr) 1044 caddr_t addr; 1045 { 1046 u_int32_t idx, bit, data, crc; 1047 1048 /* Compute CRC for the address value. */ 1049 crc = 0xFFFFFFFF; /* initial value */ 1050 1051 for (idx = 0; idx < 6; idx++) { 1052 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1053 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1054 } 1055 1056 return(crc & 0x7F); 1057 } 1058 1059 static void 1060 bge_setmulti(sc) 1061 struct bge_softc *sc; 1062 { 1063 struct ifnet *ifp; 1064 struct ifmultiaddr *ifma; 1065 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1066 int h, i; 1067 1068 ifp = &sc->arpcom.ac_if; 1069 1070 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1071 for (i = 0; i < 4; i++) 1072 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1073 return; 1074 } 1075 1076 /* First, zot all the existing filters. */ 1077 for (i = 0; i < 4; i++) 1078 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1079 1080 /* Now program new ones. */ 1081 for (ifma = ifp->if_multiaddrs.lh_first; 1082 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1083 if (ifma->ifma_addr->sa_family != AF_LINK) 1084 continue; 1085 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1086 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1087 } 1088 1089 for (i = 0; i < 4; i++) 1090 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1091 1092 return; 1093 } 1094 1095 /* 1096 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1097 * self-test results. 1098 */ 1099 static int 1100 bge_chipinit(sc) 1101 struct bge_softc *sc; 1102 { 1103 int i; 1104 u_int32_t dma_rw_ctl; 1105 1106 /* Set endianness before we access any non-PCI registers. */ 1107 #if BYTE_ORDER == BIG_ENDIAN 1108 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1109 BGE_BIGENDIAN_INIT, 4); 1110 #else 1111 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1112 BGE_LITTLEENDIAN_INIT, 4); 1113 #endif 1114 1115 /* 1116 * Check the 'ROM failed' bit on the RX CPU to see if 1117 * self-tests passed. 1118 */ 1119 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1120 printf("bge%d: RX CPU self-diagnostics failed!\n", 1121 sc->bge_unit); 1122 return(ENODEV); 1123 } 1124 1125 /* Clear the MAC control register */ 1126 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1127 1128 /* 1129 * Clear the MAC statistics block in the NIC's 1130 * internal memory. 1131 */ 1132 for (i = BGE_STATS_BLOCK; 1133 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1134 BGE_MEMWIN_WRITE(sc, i, 0); 1135 1136 for (i = BGE_STATUS_BLOCK; 1137 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1138 BGE_MEMWIN_WRITE(sc, i, 0); 1139 1140 /* Set up the PCI DMA control register. */ 1141 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1142 BGE_PCISTATE_PCI_BUSMODE) { 1143 /* Conventional PCI bus */ 1144 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1145 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1146 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1147 (0x0F); 1148 } else { 1149 /* PCI-X bus */ 1150 /* 1151 * The 5704 uses a different encoding of read/write 1152 * watermarks. 1153 */ 1154 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1155 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1156 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1157 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1158 else 1159 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1160 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1161 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1162 (0x0F); 1163 1164 /* 1165 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1166 * for hardware bugs. 1167 */ 1168 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1169 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1170 u_int32_t tmp; 1171 1172 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1173 if (tmp == 0x6 || tmp == 0x7) 1174 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1175 } 1176 } 1177 1178 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1179 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1180 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1181 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1182 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1183 1184 /* 1185 * Set up general mode register. 1186 */ 1187 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1188 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1189 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1190 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1191 1192 /* 1193 * Disable memory write invalidate. Apparently it is not supported 1194 * properly by these devices. 1195 */ 1196 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1197 1198 #ifdef __brokenalpha__ 1199 /* 1200 * Must insure that we do not cross an 8K (bytes) boundary 1201 * for DMA reads. Our highest limit is 1K bytes. This is a 1202 * restriction on some ALPHA platforms with early revision 1203 * 21174 PCI chipsets, such as the AlphaPC 164lx 1204 */ 1205 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1206 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1207 #endif 1208 1209 /* Set the timer prescaler (always 66Mhz) */ 1210 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1211 1212 return(0); 1213 } 1214 1215 static int 1216 bge_blockinit(sc) 1217 struct bge_softc *sc; 1218 { 1219 struct bge_rcb *rcb; 1220 volatile struct bge_rcb *vrcb; 1221 int i; 1222 1223 /* 1224 * Initialize the memory window pointer register so that 1225 * we can access the first 32K of internal NIC RAM. This will 1226 * allow us to set up the TX send ring RCBs and the RX return 1227 * ring RCBs, plus other things which live in NIC memory. 1228 */ 1229 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1230 1231 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1232 1233 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1234 /* Configure mbuf memory pool */ 1235 if (sc->bge_extram) { 1236 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1237 BGE_EXT_SSRAM); 1238 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1239 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1240 else 1241 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1242 } else { 1243 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1244 BGE_BUFFPOOL_1); 1245 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1246 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1247 else 1248 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1249 } 1250 1251 /* Configure DMA resource pool */ 1252 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1253 BGE_DMA_DESCRIPTORS); 1254 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1255 } 1256 1257 /* Configure mbuf pool watermarks */ 1258 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1259 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1260 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1261 } else { 1262 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1263 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1264 } 1265 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1266 1267 /* Configure DMA resource watermarks */ 1268 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1269 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1270 1271 /* Enable buffer manager */ 1272 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1273 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1274 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1275 1276 /* Poll for buffer manager start indication */ 1277 for (i = 0; i < BGE_TIMEOUT; i++) { 1278 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1279 break; 1280 DELAY(10); 1281 } 1282 1283 if (i == BGE_TIMEOUT) { 1284 printf("bge%d: buffer manager failed to start\n", 1285 sc->bge_unit); 1286 return(ENXIO); 1287 } 1288 } 1289 1290 /* Enable flow-through queues */ 1291 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1292 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1293 1294 /* Wait until queue initialization is complete */ 1295 for (i = 0; i < BGE_TIMEOUT; i++) { 1296 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1297 break; 1298 DELAY(10); 1299 } 1300 1301 if (i == BGE_TIMEOUT) { 1302 printf("bge%d: flow-through queue init failed\n", 1303 sc->bge_unit); 1304 return(ENXIO); 1305 } 1306 1307 /* Initialize the standard RX ring control block */ 1308 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1309 BGE_HOSTADDR(rcb->bge_hostaddr, 1310 vtophys(&sc->bge_rdata->bge_rx_std_ring)); 1311 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1312 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1313 else 1314 rcb->bge_maxlen_flags = 1315 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1316 if (sc->bge_extram) 1317 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1318 else 1319 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1320 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1321 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1322 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1323 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1324 1325 /* 1326 * Initialize the jumbo RX ring control block 1327 * We set the 'ring disabled' bit in the flags 1328 * field until we're actually ready to start 1329 * using this ring (i.e. once we set the MTU 1330 * high enough to require it). 1331 */ 1332 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1333 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1334 BGE_HOSTADDR(rcb->bge_hostaddr, 1335 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring)); 1336 rcb->bge_maxlen_flags = 1337 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1338 BGE_RCB_FLAG_RING_DISABLED); 1339 if (sc->bge_extram) 1340 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1341 else 1342 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1343 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1344 rcb->bge_hostaddr.bge_addr_hi); 1345 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1346 rcb->bge_hostaddr.bge_addr_lo); 1347 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1348 rcb->bge_maxlen_flags); 1349 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1350 1351 /* Set up dummy disabled mini ring RCB */ 1352 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1353 rcb->bge_maxlen_flags = 1354 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1355 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1356 rcb->bge_maxlen_flags); 1357 } 1358 1359 /* 1360 * Set the BD ring replentish thresholds. The recommended 1361 * values are 1/8th the number of descriptors allocated to 1362 * each ring. 1363 */ 1364 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1365 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1366 1367 /* 1368 * Disable all unused send rings by setting the 'ring disabled' 1369 * bit in the flags field of all the TX send ring control blocks. 1370 * These are located in NIC memory. 1371 */ 1372 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1373 BGE_SEND_RING_RCB); 1374 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1375 vrcb->bge_maxlen_flags = 1376 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1377 vrcb->bge_nicaddr = 0; 1378 vrcb++; 1379 } 1380 1381 /* Configure TX RCB 0 (we use only the first ring) */ 1382 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1383 BGE_SEND_RING_RCB); 1384 vrcb->bge_hostaddr.bge_addr_hi = 0; 1385 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring)); 1386 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1387 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1388 vrcb->bge_maxlen_flags = 1389 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1390 1391 /* Disable all unused RX return rings */ 1392 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1393 BGE_RX_RETURN_RING_RCB); 1394 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1395 vrcb->bge_hostaddr.bge_addr_hi = 0; 1396 vrcb->bge_hostaddr.bge_addr_lo = 0; 1397 vrcb->bge_maxlen_flags = 1398 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1399 BGE_RCB_FLAG_RING_DISABLED); 1400 vrcb->bge_nicaddr = 0; 1401 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1402 (i * (sizeof(u_int64_t))), 0); 1403 vrcb++; 1404 } 1405 1406 /* Initialize RX ring indexes */ 1407 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1408 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1409 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1410 1411 /* 1412 * Set up RX return ring 0 1413 * Note that the NIC address for RX return rings is 0x00000000. 1414 * The return rings live entirely within the host, so the 1415 * nicaddr field in the RCB isn't used. 1416 */ 1417 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1418 BGE_RX_RETURN_RING_RCB); 1419 vrcb->bge_hostaddr.bge_addr_hi = 0; 1420 BGE_HOSTADDR(vrcb->bge_hostaddr, 1421 vtophys(&sc->bge_rdata->bge_rx_return_ring)); 1422 vrcb->bge_nicaddr = 0x00000000; 1423 vrcb->bge_maxlen_flags = 1424 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1425 1426 /* Set random backoff seed for TX */ 1427 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1428 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1429 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1430 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1431 BGE_TX_BACKOFF_SEED_MASK); 1432 1433 /* Set inter-packet gap */ 1434 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1435 1436 /* 1437 * Specify which ring to use for packets that don't match 1438 * any RX rules. 1439 */ 1440 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1441 1442 /* 1443 * Configure number of RX lists. One interrupt distribution 1444 * list, sixteen active lists, one bad frames class. 1445 */ 1446 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1447 1448 /* Inialize RX list placement stats mask. */ 1449 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1450 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1451 1452 /* Disable host coalescing until we get it set up */ 1453 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1454 1455 /* Poll to make sure it's shut down. */ 1456 for (i = 0; i < BGE_TIMEOUT; i++) { 1457 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1458 break; 1459 DELAY(10); 1460 } 1461 1462 if (i == BGE_TIMEOUT) { 1463 printf("bge%d: host coalescing engine failed to idle\n", 1464 sc->bge_unit); 1465 return(ENXIO); 1466 } 1467 1468 /* Set up host coalescing defaults */ 1469 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1470 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1471 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1472 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1473 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1474 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1475 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1476 } 1477 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1478 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1479 1480 /* Set up address of statistics block */ 1481 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1482 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1483 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1484 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1485 1486 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1487 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1488 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1489 } 1490 1491 /* Set up address of status block */ 1492 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1493 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1494 vtophys(&sc->bge_rdata->bge_status_block)); 1495 1496 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1497 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1498 1499 /* Turn on host coalescing state machine */ 1500 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1501 1502 /* Turn on RX BD completion state machine and enable attentions */ 1503 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1504 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1505 1506 /* Turn on RX list placement state machine */ 1507 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1508 1509 /* Turn on RX list selector state machine. */ 1510 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1511 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1512 1513 /* Turn on DMA, clear stats */ 1514 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1515 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1516 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1517 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1518 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1519 1520 /* Set misc. local control, enable interrupts on attentions */ 1521 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1522 1523 #ifdef notdef 1524 /* Assert GPIO pins for PHY reset */ 1525 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1526 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1527 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1528 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1529 #endif 1530 1531 /* Turn on DMA completion state machine */ 1532 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1533 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1534 1535 /* Turn on write DMA state machine */ 1536 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1537 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1538 1539 /* Turn on read DMA state machine */ 1540 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1541 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1542 1543 /* Turn on RX data completion state machine */ 1544 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1545 1546 /* Turn on RX BD initiator state machine */ 1547 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1548 1549 /* Turn on RX data and RX BD initiator state machine */ 1550 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1551 1552 /* Turn on Mbuf cluster free state machine */ 1553 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1554 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1555 1556 /* Turn on send BD completion state machine */ 1557 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1558 1559 /* Turn on send data completion state machine */ 1560 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1561 1562 /* Turn on send data initiator state machine */ 1563 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1564 1565 /* Turn on send BD initiator state machine */ 1566 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1567 1568 /* Turn on send BD selector state machine */ 1569 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1570 1571 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1572 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1573 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1574 1575 /* ack/clear link change events */ 1576 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1577 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1578 BGE_MACSTAT_LINK_CHANGED); 1579 1580 /* Enable PHY auto polling (for MII/GMII only) */ 1581 if (sc->bge_tbi) { 1582 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1583 } else { 1584 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1585 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1586 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1587 BGE_EVTENB_MI_INTERRUPT); 1588 } 1589 1590 /* Enable link state change attentions. */ 1591 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1592 1593 return(0); 1594 } 1595 1596 /* 1597 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1598 * against our list and return its name if we find a match. Note 1599 * that since the Broadcom controller contains VPD support, we 1600 * can get the device name string from the controller itself instead 1601 * of the compiled-in string. This is a little slow, but it guarantees 1602 * we'll always announce the right product name. 1603 */ 1604 static int 1605 bge_probe(dev) 1606 device_t dev; 1607 { 1608 struct bge_type *t; 1609 struct bge_softc *sc; 1610 char *descbuf; 1611 1612 t = bge_devs; 1613 1614 sc = device_get_softc(dev); 1615 bzero(sc, sizeof(struct bge_softc)); 1616 sc->bge_unit = device_get_unit(dev); 1617 sc->bge_dev = dev; 1618 1619 while(t->bge_name != NULL) { 1620 if ((pci_get_vendor(dev) == t->bge_vid) && 1621 (pci_get_device(dev) == t->bge_did)) { 1622 #ifdef notdef 1623 bge_vpd_read(sc); 1624 device_set_desc(dev, sc->bge_vpd_prodname); 1625 #endif 1626 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_INTWAIT); 1627 snprintf(descbuf, BGE_DEVDESC_MAX, 1628 "%s, ASIC rev. %#04x", t->bge_name, 1629 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1630 device_set_desc_copy(dev, descbuf); 1631 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) 1632 sc->bge_no_3_led = 1; 1633 free(descbuf, M_TEMP); 1634 return(0); 1635 } 1636 t++; 1637 } 1638 1639 return(ENXIO); 1640 } 1641 1642 static int 1643 bge_attach(dev) 1644 device_t dev; 1645 { 1646 int s; 1647 u_int32_t command; 1648 struct ifnet *ifp; 1649 struct bge_softc *sc; 1650 u_int32_t hwcfg = 0; 1651 u_int32_t mac_addr = 0; 1652 int unit, error = 0, rid; 1653 uint8_t ether_addr[ETHER_ADDR_LEN]; 1654 1655 s = splimp(); 1656 1657 sc = device_get_softc(dev); 1658 unit = device_get_unit(dev); 1659 sc->bge_dev = dev; 1660 sc->bge_unit = unit; 1661 callout_init(&sc->bge_stat_timer); 1662 1663 /* 1664 * Map control/status registers. 1665 */ 1666 command = pci_read_config(dev, PCIR_COMMAND, 4); 1667 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1668 pci_write_config(dev, PCIR_COMMAND, command, 4); 1669 command = pci_read_config(dev, PCIR_COMMAND, 4); 1670 1671 if (!(command & PCIM_CMD_MEMEN)) { 1672 printf("bge%d: failed to enable memory mapping!\n", unit); 1673 error = ENXIO; 1674 goto fail; 1675 } 1676 1677 rid = BGE_PCI_BAR0; 1678 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1679 0, ~0, 1, RF_ACTIVE); 1680 1681 if (sc->bge_res == NULL) { 1682 printf ("bge%d: couldn't map memory\n", unit); 1683 error = ENXIO; 1684 goto fail; 1685 } 1686 1687 sc->bge_btag = rman_get_bustag(sc->bge_res); 1688 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1689 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1690 1691 /* 1692 * XXX FIXME: rman_get_virtual() on the alpha is currently 1693 * broken and returns a physical address instead of a kernel 1694 * virtual address. Consequently, we need to do a little 1695 * extra mangling of the vhandle on the alpha. This should 1696 * eventually be fixed! The whole idea here is to get rid 1697 * of platform dependencies. 1698 */ 1699 #ifdef __alpha__ 1700 if (pci_cvt_to_bwx(sc->bge_vhandle)) 1701 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); 1702 else 1703 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); 1704 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); 1705 #endif 1706 1707 /* Allocate interrupt */ 1708 rid = 0; 1709 1710 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1711 RF_SHAREABLE | RF_ACTIVE); 1712 1713 if (sc->bge_irq == NULL) { 1714 printf("bge%d: couldn't map interrupt\n", unit); 1715 error = ENXIO; 1716 goto fail; 1717 } 1718 1719 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1720 bge_intr, sc, &sc->bge_intrhand); 1721 1722 if (error) { 1723 bge_release_resources(sc); 1724 printf("bge%d: couldn't set up irq\n", unit); 1725 goto fail; 1726 } 1727 1728 sc->bge_unit = unit; 1729 1730 /* Try to reset the chip. */ 1731 bge_reset(sc); 1732 1733 if (bge_chipinit(sc)) { 1734 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1735 bge_release_resources(sc); 1736 error = ENXIO; 1737 goto fail; 1738 } 1739 1740 /* 1741 * Get station address from the EEPROM. 1742 */ 1743 mac_addr = bge_readmem_ind(sc, 0x0c14); 1744 if ((mac_addr >> 16) == 0x484b) { 1745 ether_addr[0] = (uint8_t)(mac_addr >> 8); 1746 ether_addr[1] = (uint8_t)mac_addr; 1747 mac_addr = bge_readmem_ind(sc, 0x0c18); 1748 ether_addr[2] = (uint8_t)(mac_addr >> 24); 1749 ether_addr[3] = (uint8_t)(mac_addr >> 16); 1750 ether_addr[4] = (uint8_t)(mac_addr >> 8); 1751 ether_addr[5] = (uint8_t)mac_addr; 1752 } else if (bge_read_eeprom(sc, ether_addr, 1753 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1754 printf("bge%d: failed to read station address\n", unit); 1755 bge_release_resources(sc); 1756 error = ENXIO; 1757 goto fail; 1758 } 1759 1760 /* Allocate the general information block and ring buffers. */ 1761 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1762 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1763 1764 if (sc->bge_rdata == NULL) { 1765 bge_release_resources(sc); 1766 error = ENXIO; 1767 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1768 goto fail; 1769 } 1770 1771 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1772 1773 /* Save ASIC rev. */ 1774 1775 sc->bge_chipid = 1776 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1777 BGE_PCIMISCCTL_ASICREV; 1778 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1779 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1780 1781 /* 1782 * Try to allocate memory for jumbo buffers. 1783 * The 5705 does not appear to support jumbo frames. 1784 */ 1785 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1786 if (bge_alloc_jumbo_mem(sc)) { 1787 printf("bge%d: jumbo buffer allocation " 1788 "failed\n", sc->bge_unit); 1789 bge_release_resources(sc); 1790 error = ENXIO; 1791 goto fail; 1792 } 1793 } 1794 1795 /* Set default tuneable values. */ 1796 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1797 sc->bge_rx_coal_ticks = 150; 1798 sc->bge_tx_coal_ticks = 150; 1799 sc->bge_rx_max_coal_bds = 64; 1800 sc->bge_tx_max_coal_bds = 128; 1801 1802 /* 5705 limits RX return ring to 512 entries. */ 1803 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1804 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1805 else 1806 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1807 1808 /* Set up ifnet structure */ 1809 ifp = &sc->arpcom.ac_if; 1810 ifp->if_softc = sc; 1811 if_initname(ifp, "bge", sc->bge_unit); 1812 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1813 ifp->if_ioctl = bge_ioctl; 1814 ifp->if_start = bge_start; 1815 ifp->if_watchdog = bge_watchdog; 1816 ifp->if_init = bge_init; 1817 ifp->if_mtu = ETHERMTU; 1818 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1819 ifp->if_hwassist = BGE_CSUM_FEATURES; 1820 ifp->if_capabilities = IFCAP_HWCSUM; 1821 ifp->if_capenable = ifp->if_capabilities; 1822 1823 /* 1824 * Figure out what sort of media we have by checking the 1825 * hardware config word in the first 32k of NIC internal memory, 1826 * or fall back to examining the EEPROM if necessary. 1827 * Note: on some BCM5700 cards, this value appears to be unset. 1828 * If that's the case, we have to rely on identifying the NIC 1829 * by its PCI subsystem ID, as we do below for the SysKonnect 1830 * SK-9D41. 1831 */ 1832 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1833 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1834 else { 1835 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1836 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1837 hwcfg = ntohl(hwcfg); 1838 } 1839 1840 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1841 sc->bge_tbi = 1; 1842 1843 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1844 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 1845 PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41) 1846 sc->bge_tbi = 1; 1847 1848 if (sc->bge_tbi) { 1849 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1850 bge_ifmedia_upd, bge_ifmedia_sts); 1851 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1852 ifmedia_add(&sc->bge_ifmedia, 1853 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1854 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1855 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1856 } else { 1857 /* 1858 * Do transceiver setup. 1859 */ 1860 if (mii_phy_probe(dev, &sc->bge_miibus, 1861 bge_ifmedia_upd, bge_ifmedia_sts)) { 1862 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1863 bge_release_resources(sc); 1864 bge_free_jumbo_mem(sc); 1865 error = ENXIO; 1866 goto fail; 1867 } 1868 } 1869 1870 /* 1871 * When using the BCM5701 in PCI-X mode, data corruption has 1872 * been observed in the first few bytes of some received packets. 1873 * Aligning the packet buffer in memory eliminates the corruption. 1874 * Unfortunately, this misaligns the packet payloads. On platforms 1875 * which do not support unaligned accesses, we will realign the 1876 * payloads by copying the received packets. 1877 */ 1878 switch (sc->bge_chipid) { 1879 case BGE_CHIPID_BCM5701_A0: 1880 case BGE_CHIPID_BCM5701_B0: 1881 case BGE_CHIPID_BCM5701_B2: 1882 case BGE_CHIPID_BCM5701_B5: 1883 /* If in PCI-X mode, work around the alignment bug. */ 1884 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1885 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1886 BGE_PCISTATE_PCI_BUSSPEED) 1887 sc->bge_rx_alignment_bug = 1; 1888 break; 1889 } 1890 1891 /* 1892 * Call MI attach routine. 1893 */ 1894 ether_ifattach(ifp, ether_addr); 1895 1896 fail: 1897 splx(s); 1898 1899 return(error); 1900 } 1901 1902 static int 1903 bge_detach(dev) 1904 device_t dev; 1905 { 1906 struct bge_softc *sc; 1907 struct ifnet *ifp; 1908 int s; 1909 1910 s = splimp(); 1911 1912 sc = device_get_softc(dev); 1913 ifp = &sc->arpcom.ac_if; 1914 1915 ether_ifdetach(ifp); 1916 bge_stop(sc); 1917 bge_reset(sc); 1918 1919 if (sc->bge_tbi) { 1920 ifmedia_removeall(&sc->bge_ifmedia); 1921 } else { 1922 bus_generic_detach(dev); 1923 device_delete_child(dev, sc->bge_miibus); 1924 } 1925 1926 bge_release_resources(sc); 1927 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1928 bge_free_jumbo_mem(sc); 1929 1930 splx(s); 1931 1932 return(0); 1933 } 1934 1935 static void 1936 bge_release_resources(sc) 1937 struct bge_softc *sc; 1938 { 1939 device_t dev; 1940 1941 dev = sc->bge_dev; 1942 1943 if (sc->bge_vpd_prodname != NULL) 1944 free(sc->bge_vpd_prodname, M_DEVBUF); 1945 1946 if (sc->bge_vpd_readonly != NULL) 1947 free(sc->bge_vpd_readonly, M_DEVBUF); 1948 1949 if (sc->bge_intrhand != NULL) 1950 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1951 1952 if (sc->bge_irq != NULL) 1953 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1954 1955 if (sc->bge_res != NULL) 1956 bus_release_resource(dev, SYS_RES_MEMORY, 1957 BGE_PCI_BAR0, sc->bge_res); 1958 1959 if (sc->bge_rdata != NULL) 1960 contigfree(sc->bge_rdata, 1961 sizeof(struct bge_ring_data), M_DEVBUF); 1962 1963 return; 1964 } 1965 1966 static void 1967 bge_reset(sc) 1968 struct bge_softc *sc; 1969 { 1970 device_t dev; 1971 u_int32_t cachesize, command, pcistate; 1972 int i, val = 0; 1973 1974 dev = sc->bge_dev; 1975 1976 /* Save some important PCI state. */ 1977 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1978 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1979 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1980 1981 pci_write_config(dev, BGE_PCI_MISC_CTL, 1982 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1983 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1984 1985 /* Issue global reset */ 1986 bge_writereg_ind(sc, BGE_MISC_CFG, 1987 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1988 1989 DELAY(1000); 1990 1991 /* Reset some of the PCI state that got zapped by reset */ 1992 pci_write_config(dev, BGE_PCI_MISC_CTL, 1993 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1994 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1995 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1996 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1997 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1998 1999 /* 2000 * Prevent PXE restart: write a magic number to the 2001 * general communications memory at 0xB50. 2002 */ 2003 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2004 /* 2005 * Poll the value location we just wrote until 2006 * we see the 1's complement of the magic number. 2007 * This indicates that the firmware initialization 2008 * is complete. 2009 */ 2010 for (i = 0; i < BGE_TIMEOUT; i++) { 2011 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2012 if (val == ~BGE_MAGIC_NUMBER) 2013 break; 2014 DELAY(10); 2015 } 2016 2017 if (i == BGE_TIMEOUT) { 2018 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 2019 return; 2020 } 2021 2022 /* 2023 * XXX Wait for the value of the PCISTATE register to 2024 * return to its original pre-reset state. This is a 2025 * fairly good indicator of reset completion. If we don't 2026 * wait for the reset to fully complete, trying to read 2027 * from the device's non-PCI registers may yield garbage 2028 * results. 2029 */ 2030 for (i = 0; i < BGE_TIMEOUT; i++) { 2031 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2032 break; 2033 DELAY(10); 2034 } 2035 2036 /* Enable memory arbiter. */ 2037 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2038 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2039 2040 /* Fix up byte swapping */ 2041 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2042 BGE_MODECTL_BYTESWAP_DATA); 2043 2044 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2045 2046 DELAY(10000); 2047 2048 return; 2049 } 2050 2051 /* 2052 * Frame reception handling. This is called if there's a frame 2053 * on the receive return list. 2054 * 2055 * Note: we have to be able to handle two possibilities here: 2056 * 1) the frame is from the jumbo recieve ring 2057 * 2) the frame is from the standard receive ring 2058 */ 2059 2060 static void 2061 bge_rxeof(sc) 2062 struct bge_softc *sc; 2063 { 2064 struct ifnet *ifp; 2065 int stdcnt = 0, jumbocnt = 0; 2066 2067 ifp = &sc->arpcom.ac_if; 2068 2069 while(sc->bge_rx_saved_considx != 2070 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2071 struct bge_rx_bd *cur_rx; 2072 u_int32_t rxidx; 2073 struct mbuf *m = NULL; 2074 u_int16_t vlan_tag = 0; 2075 int have_tag = 0; 2076 2077 cur_rx = 2078 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 2079 2080 rxidx = cur_rx->bge_idx; 2081 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2082 2083 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2084 have_tag = 1; 2085 vlan_tag = cur_rx->bge_vlan_tag; 2086 } 2087 2088 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2089 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2090 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2091 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2092 jumbocnt++; 2093 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2094 ifp->if_ierrors++; 2095 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2096 continue; 2097 } 2098 if (bge_newbuf_jumbo(sc, 2099 sc->bge_jumbo, NULL) == ENOBUFS) { 2100 ifp->if_ierrors++; 2101 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2102 continue; 2103 } 2104 } else { 2105 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2106 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2107 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2108 stdcnt++; 2109 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2110 ifp->if_ierrors++; 2111 bge_newbuf_std(sc, sc->bge_std, m); 2112 continue; 2113 } 2114 if (bge_newbuf_std(sc, sc->bge_std, 2115 NULL) == ENOBUFS) { 2116 ifp->if_ierrors++; 2117 bge_newbuf_std(sc, sc->bge_std, m); 2118 continue; 2119 } 2120 } 2121 2122 ifp->if_ipackets++; 2123 #ifndef __i386__ 2124 /* 2125 * The i386 allows unaligned accesses, but for other 2126 * platforms we must make sure the payload is aligned. 2127 */ 2128 if (sc->bge_rx_alignment_bug) { 2129 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2130 cur_rx->bge_len); 2131 m->m_data += ETHER_ALIGN; 2132 } 2133 #endif 2134 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2135 m->m_pkthdr.rcvif = ifp; 2136 2137 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2138 if (ifp->if_hwassist) { 2139 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2140 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2141 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2142 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2143 m->m_pkthdr.csum_data = 2144 cur_rx->bge_tcp_udp_csum; 2145 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2146 } 2147 } 2148 #endif 2149 2150 /* 2151 * If we received a packet with a vlan tag, pass it 2152 * to vlan_input() instead of ether_input(). 2153 */ 2154 if (have_tag) { 2155 VLAN_INPUT_TAG(m, vlan_tag); 2156 have_tag = vlan_tag = 0; 2157 continue; 2158 } 2159 2160 (*ifp->if_input)(ifp, m); 2161 } 2162 2163 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2164 if (stdcnt) 2165 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2166 if (jumbocnt) 2167 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2168 2169 return; 2170 } 2171 2172 static void 2173 bge_txeof(sc) 2174 struct bge_softc *sc; 2175 { 2176 struct bge_tx_bd *cur_tx = NULL; 2177 struct ifnet *ifp; 2178 2179 ifp = &sc->arpcom.ac_if; 2180 2181 /* 2182 * Go through our tx ring and free mbufs for those 2183 * frames that have been sent. 2184 */ 2185 while (sc->bge_tx_saved_considx != 2186 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2187 u_int32_t idx = 0; 2188 2189 idx = sc->bge_tx_saved_considx; 2190 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2191 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2192 ifp->if_opackets++; 2193 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2194 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2195 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2196 } 2197 sc->bge_txcnt--; 2198 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2199 ifp->if_timer = 0; 2200 } 2201 2202 if (cur_tx != NULL) 2203 ifp->if_flags &= ~IFF_OACTIVE; 2204 2205 return; 2206 } 2207 2208 static void 2209 bge_intr(xsc) 2210 void *xsc; 2211 { 2212 struct bge_softc *sc; 2213 struct ifnet *ifp; 2214 u_int32_t status; 2215 2216 sc = xsc; 2217 ifp = &sc->arpcom.ac_if; 2218 2219 #ifdef notdef 2220 /* Avoid this for now -- checking this register is expensive. */ 2221 /* Make sure this is really our interrupt. */ 2222 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2223 return; 2224 #endif 2225 /* Ack interrupt and stop others from occuring. */ 2226 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2227 2228 /* 2229 * Process link state changes. 2230 * Grrr. The link status word in the status block does 2231 * not work correctly on the BCM5700 rev AX and BX chips, 2232 * according to all available information. Hence, we have 2233 * to enable MII interrupts in order to properly obtain 2234 * async link changes. Unfortunately, this also means that 2235 * we have to read the MAC status register to detect link 2236 * changes, thereby adding an additional register access to 2237 * the interrupt handler. 2238 */ 2239 2240 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2241 status = CSR_READ_4(sc, BGE_MAC_STS); 2242 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2243 sc->bge_link = 0; 2244 callout_stop(&sc->bge_stat_timer); 2245 bge_tick(sc); 2246 /* Clear the interrupt */ 2247 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2248 BGE_EVTENB_MI_INTERRUPT); 2249 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2250 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2251 BRGPHY_INTRS); 2252 } 2253 } else { 2254 if ((sc->bge_rdata->bge_status_block.bge_status & 2255 BGE_STATFLAG_UPDATED) && 2256 (sc->bge_rdata->bge_status_block.bge_status & 2257 BGE_STATFLAG_LINKSTATE_CHANGED)) { 2258 sc->bge_rdata->bge_status_block.bge_status &= 2259 ~(BGE_STATFLAG_UPDATED| 2260 BGE_STATFLAG_LINKSTATE_CHANGED); 2261 /* 2262 * Sometimes PCS encoding errors are detected in 2263 * TBI mode (on fiber NICs), and for some reason 2264 * the chip will signal them as link changes. 2265 * If we get a link change event, but the 'PCS 2266 * encoding error' bit in the MAC status register 2267 * is set, don't bother doing a link check. 2268 * This avoids spurious "gigabit link up" messages 2269 * that sometimes appear on fiber NICs during 2270 * periods of heavy traffic. (There should be no 2271 * effect on copper NICs.) 2272 */ 2273 status = CSR_READ_4(sc, BGE_MAC_STS); 2274 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2275 BGE_MACSTAT_MI_COMPLETE))) { 2276 sc->bge_link = 0; 2277 callout_stop(&sc->bge_stat_timer); 2278 bge_tick(sc); 2279 } 2280 sc->bge_link = 0; 2281 callout_stop(&sc->bge_stat_timer); 2282 bge_tick(sc); 2283 /* Clear the interrupt */ 2284 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2285 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2286 BGE_MACSTAT_LINK_CHANGED); 2287 2288 /* Force flush the status block cached by PCI bridge */ 2289 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2290 } 2291 } 2292 2293 if (ifp->if_flags & IFF_RUNNING) { 2294 /* Check RX return ring producer/consumer */ 2295 bge_rxeof(sc); 2296 2297 /* Check TX ring producer/consumer */ 2298 bge_txeof(sc); 2299 } 2300 2301 bge_handle_events(sc); 2302 2303 /* Re-enable interrupts. */ 2304 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2305 2306 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2307 bge_start(ifp); 2308 2309 return; 2310 } 2311 2312 static void 2313 bge_tick(xsc) 2314 void *xsc; 2315 { 2316 struct bge_softc *sc; 2317 struct mii_data *mii = NULL; 2318 struct ifmedia *ifm = NULL; 2319 struct ifnet *ifp; 2320 int s; 2321 2322 sc = xsc; 2323 ifp = &sc->arpcom.ac_if; 2324 2325 s = splimp(); 2326 2327 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2328 bge_stats_update_regs(sc); 2329 else 2330 bge_stats_update(sc); 2331 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 2332 if (sc->bge_link) { 2333 splx(s); 2334 return; 2335 } 2336 2337 if (sc->bge_tbi) { 2338 ifm = &sc->bge_ifmedia; 2339 if (CSR_READ_4(sc, BGE_MAC_STS) & 2340 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2341 sc->bge_link++; 2342 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2343 printf("bge%d: gigabit link up\n", sc->bge_unit); 2344 if (ifp->if_snd.ifq_head != NULL) 2345 bge_start(ifp); 2346 } 2347 splx(s); 2348 return; 2349 } 2350 2351 mii = device_get_softc(sc->bge_miibus); 2352 mii_tick(mii); 2353 2354 if (!sc->bge_link) { 2355 mii_pollstat(mii); 2356 if (mii->mii_media_status & IFM_ACTIVE && 2357 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2358 sc->bge_link++; 2359 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 2360 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2361 printf("bge%d: gigabit link up\n", 2362 sc->bge_unit); 2363 if (ifp->if_snd.ifq_head != NULL) 2364 bge_start(ifp); 2365 } 2366 } 2367 2368 splx(s); 2369 2370 return; 2371 } 2372 2373 static void 2374 bge_stats_update_regs(sc) 2375 struct bge_softc *sc; 2376 { 2377 struct ifnet *ifp; 2378 struct bge_mac_stats_regs stats; 2379 u_int32_t *s; 2380 int i; 2381 2382 ifp = &sc->arpcom.ac_if; 2383 2384 s = (u_int32_t *)&stats; 2385 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2386 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2387 s++; 2388 } 2389 2390 ifp->if_collisions += 2391 (stats.dot3StatsSingleCollisionFrames + 2392 stats.dot3StatsMultipleCollisionFrames + 2393 stats.dot3StatsExcessiveCollisions + 2394 stats.dot3StatsLateCollisions) - 2395 ifp->if_collisions; 2396 2397 return; 2398 } 2399 2400 static void 2401 bge_stats_update(sc) 2402 struct bge_softc *sc; 2403 { 2404 struct ifnet *ifp; 2405 struct bge_stats *stats; 2406 2407 ifp = &sc->arpcom.ac_if; 2408 2409 stats = (struct bge_stats *)(sc->bge_vhandle + 2410 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2411 2412 ifp->if_collisions += 2413 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 2414 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 2415 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 2416 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 2417 ifp->if_collisions; 2418 2419 #ifdef notdef 2420 ifp->if_collisions += 2421 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2422 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2423 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2424 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2425 ifp->if_collisions; 2426 #endif 2427 2428 return; 2429 } 2430 2431 /* 2432 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2433 * pointers to descriptors. 2434 */ 2435 static int 2436 bge_encap(sc, m_head, txidx) 2437 struct bge_softc *sc; 2438 struct mbuf *m_head; 2439 u_int32_t *txidx; 2440 { 2441 struct bge_tx_bd *f = NULL; 2442 struct mbuf *m; 2443 u_int32_t frag, cur, cnt = 0; 2444 u_int16_t csum_flags = 0; 2445 struct ifvlan *ifv = NULL; 2446 2447 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2448 m_head->m_pkthdr.rcvif != NULL && 2449 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2450 ifv = m_head->m_pkthdr.rcvif->if_softc; 2451 2452 m = m_head; 2453 cur = frag = *txidx; 2454 2455 if (m_head->m_pkthdr.csum_flags) { 2456 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2457 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2458 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2459 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2460 if (m_head->m_flags & M_LASTFRAG) 2461 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2462 else if (m_head->m_flags & M_FRAG) 2463 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2464 } 2465 /* 2466 * Start packing the mbufs in this chain into 2467 * the fragment pointers. Stop when we run out 2468 * of fragments or hit the end of the mbuf chain. 2469 */ 2470 for (m = m_head; m != NULL; m = m->m_next) { 2471 if (m->m_len != 0) { 2472 f = &sc->bge_rdata->bge_tx_ring[frag]; 2473 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2474 break; 2475 BGE_HOSTADDR(f->bge_addr, 2476 vtophys(mtod(m, vm_offset_t))); 2477 f->bge_len = m->m_len; 2478 f->bge_flags = csum_flags; 2479 if (ifv != NULL) { 2480 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2481 f->bge_vlan_tag = ifv->ifv_tag; 2482 } else { 2483 f->bge_vlan_tag = 0; 2484 } 2485 /* 2486 * Sanity check: avoid coming within 16 descriptors 2487 * of the end of the ring. 2488 */ 2489 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2490 return(ENOBUFS); 2491 cur = frag; 2492 BGE_INC(frag, BGE_TX_RING_CNT); 2493 cnt++; 2494 } 2495 } 2496 2497 if (m != NULL) 2498 return(ENOBUFS); 2499 2500 if (frag == sc->bge_tx_saved_considx) 2501 return(ENOBUFS); 2502 2503 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2504 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2505 sc->bge_txcnt += cnt; 2506 2507 *txidx = frag; 2508 2509 return(0); 2510 } 2511 2512 /* 2513 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2514 * to the mbuf data regions directly in the transmit descriptors. 2515 */ 2516 static void 2517 bge_start(ifp) 2518 struct ifnet *ifp; 2519 { 2520 struct bge_softc *sc; 2521 struct mbuf *m_head = NULL; 2522 u_int32_t prodidx = 0; 2523 2524 sc = ifp->if_softc; 2525 2526 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2527 return; 2528 2529 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2530 2531 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2532 IF_DEQUEUE(&ifp->if_snd, m_head); 2533 if (m_head == NULL) 2534 break; 2535 2536 /* 2537 * XXX 2538 * safety overkill. If this is a fragmented packet chain 2539 * with delayed TCP/UDP checksums, then only encapsulate 2540 * it if we have enough descriptors to handle the entire 2541 * chain at once. 2542 * (paranoia -- may not actually be needed) 2543 */ 2544 if (m_head->m_flags & M_FIRSTFRAG && 2545 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2546 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2547 m_head->m_pkthdr.csum_data + 16) { 2548 IF_PREPEND(&ifp->if_snd, m_head); 2549 ifp->if_flags |= IFF_OACTIVE; 2550 break; 2551 } 2552 } 2553 2554 /* 2555 * Pack the data into the transmit ring. If we 2556 * don't have room, set the OACTIVE flag and wait 2557 * for the NIC to drain the ring. 2558 */ 2559 if (bge_encap(sc, m_head, &prodidx)) { 2560 IF_PREPEND(&ifp->if_snd, m_head); 2561 ifp->if_flags |= IFF_OACTIVE; 2562 break; 2563 } 2564 2565 BPF_MTAP(ifp, m_head); 2566 } 2567 2568 /* Transmit */ 2569 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2570 /* 5700 b2 errata */ 2571 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2572 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2573 2574 /* 2575 * Set a timeout in case the chip goes out to lunch. 2576 */ 2577 ifp->if_timer = 5; 2578 2579 return; 2580 } 2581 2582 static void 2583 bge_init(xsc) 2584 void *xsc; 2585 { 2586 struct bge_softc *sc = xsc; 2587 struct ifnet *ifp; 2588 u_int16_t *m; 2589 int s; 2590 2591 s = splimp(); 2592 2593 ifp = &sc->arpcom.ac_if; 2594 2595 if (ifp->if_flags & IFF_RUNNING) { 2596 splx(s); 2597 return; 2598 } 2599 2600 /* Cancel pending I/O and flush buffers. */ 2601 bge_stop(sc); 2602 bge_reset(sc); 2603 bge_chipinit(sc); 2604 2605 /* 2606 * Init the various state machines, ring 2607 * control blocks and firmware. 2608 */ 2609 if (bge_blockinit(sc)) { 2610 printf("bge%d: initialization failure\n", sc->bge_unit); 2611 splx(s); 2612 return; 2613 } 2614 2615 ifp = &sc->arpcom.ac_if; 2616 2617 /* Specify MTU. */ 2618 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2619 ETHER_HDR_LEN + ETHER_CRC_LEN); 2620 2621 /* Load our MAC address. */ 2622 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2623 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2624 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2625 2626 /* Enable or disable promiscuous mode as needed. */ 2627 if (ifp->if_flags & IFF_PROMISC) { 2628 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2629 } else { 2630 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2631 } 2632 2633 /* Program multicast filter. */ 2634 bge_setmulti(sc); 2635 2636 /* Init RX ring. */ 2637 bge_init_rx_ring_std(sc); 2638 2639 /* 2640 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 2641 * memory to insure that the chip has in fact read the first 2642 * entry of the ring. 2643 */ 2644 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 2645 u_int32_t v, i; 2646 for (i = 0; i < 10; i++) { 2647 DELAY(20); 2648 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 2649 if (v == (MCLBYTES - ETHER_ALIGN)) 2650 break; 2651 } 2652 if (i == 10) 2653 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 2654 sc->bge_unit); 2655 } 2656 2657 /* Init jumbo RX ring. */ 2658 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2659 bge_init_rx_ring_jumbo(sc); 2660 2661 /* Init our RX return ring index */ 2662 sc->bge_rx_saved_considx = 0; 2663 2664 /* Init TX ring. */ 2665 bge_init_tx_ring(sc); 2666 2667 /* Turn on transmitter */ 2668 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2669 2670 /* Turn on receiver */ 2671 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2672 2673 /* Tell firmware we're alive. */ 2674 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2675 2676 /* Enable host interrupts. */ 2677 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2678 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2679 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2680 2681 bge_ifmedia_upd(ifp); 2682 2683 ifp->if_flags |= IFF_RUNNING; 2684 ifp->if_flags &= ~IFF_OACTIVE; 2685 2686 splx(s); 2687 2688 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 2689 } 2690 2691 /* 2692 * Set media options. 2693 */ 2694 static int 2695 bge_ifmedia_upd(ifp) 2696 struct ifnet *ifp; 2697 { 2698 struct bge_softc *sc; 2699 struct mii_data *mii; 2700 struct ifmedia *ifm; 2701 2702 sc = ifp->if_softc; 2703 ifm = &sc->bge_ifmedia; 2704 2705 /* If this is a 1000baseX NIC, enable the TBI port. */ 2706 if (sc->bge_tbi) { 2707 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2708 return(EINVAL); 2709 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2710 case IFM_AUTO: 2711 break; 2712 case IFM_1000_SX: 2713 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2714 BGE_CLRBIT(sc, BGE_MAC_MODE, 2715 BGE_MACMODE_HALF_DUPLEX); 2716 } else { 2717 BGE_SETBIT(sc, BGE_MAC_MODE, 2718 BGE_MACMODE_HALF_DUPLEX); 2719 } 2720 break; 2721 default: 2722 return(EINVAL); 2723 } 2724 return(0); 2725 } 2726 2727 mii = device_get_softc(sc->bge_miibus); 2728 sc->bge_link = 0; 2729 if (mii->mii_instance) { 2730 struct mii_softc *miisc; 2731 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2732 miisc = LIST_NEXT(miisc, mii_list)) 2733 mii_phy_reset(miisc); 2734 } 2735 mii_mediachg(mii); 2736 2737 return(0); 2738 } 2739 2740 /* 2741 * Report current media status. 2742 */ 2743 static void 2744 bge_ifmedia_sts(ifp, ifmr) 2745 struct ifnet *ifp; 2746 struct ifmediareq *ifmr; 2747 { 2748 struct bge_softc *sc; 2749 struct mii_data *mii; 2750 2751 sc = ifp->if_softc; 2752 2753 if (sc->bge_tbi) { 2754 ifmr->ifm_status = IFM_AVALID; 2755 ifmr->ifm_active = IFM_ETHER; 2756 if (CSR_READ_4(sc, BGE_MAC_STS) & 2757 BGE_MACSTAT_TBI_PCS_SYNCHED) 2758 ifmr->ifm_status |= IFM_ACTIVE; 2759 ifmr->ifm_active |= IFM_1000_SX; 2760 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2761 ifmr->ifm_active |= IFM_HDX; 2762 else 2763 ifmr->ifm_active |= IFM_FDX; 2764 return; 2765 } 2766 2767 mii = device_get_softc(sc->bge_miibus); 2768 mii_pollstat(mii); 2769 ifmr->ifm_active = mii->mii_media_active; 2770 ifmr->ifm_status = mii->mii_media_status; 2771 2772 return; 2773 } 2774 2775 static int 2776 bge_ioctl(ifp, command, data, cr) 2777 struct ifnet *ifp; 2778 u_long command; 2779 caddr_t data; 2780 struct ucred *cr; 2781 { 2782 struct bge_softc *sc = ifp->if_softc; 2783 struct ifreq *ifr = (struct ifreq *) data; 2784 int s, mask, error = 0; 2785 struct mii_data *mii; 2786 2787 s = splimp(); 2788 2789 switch(command) { 2790 case SIOCSIFADDR: 2791 case SIOCGIFADDR: 2792 error = ether_ioctl(ifp, command, data); 2793 break; 2794 case SIOCSIFMTU: 2795 /* Disallow jumbo frames on 5705. */ 2796 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2797 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 2798 error = EINVAL; 2799 else { 2800 ifp->if_mtu = ifr->ifr_mtu; 2801 ifp->if_flags &= ~IFF_RUNNING; 2802 bge_init(sc); 2803 } 2804 break; 2805 case SIOCSIFFLAGS: 2806 if (ifp->if_flags & IFF_UP) { 2807 /* 2808 * If only the state of the PROMISC flag changed, 2809 * then just use the 'set promisc mode' command 2810 * instead of reinitializing the entire NIC. Doing 2811 * a full re-init means reloading the firmware and 2812 * waiting for it to start up, which may take a 2813 * second or two. 2814 */ 2815 if (ifp->if_flags & IFF_RUNNING && 2816 ifp->if_flags & IFF_PROMISC && 2817 !(sc->bge_if_flags & IFF_PROMISC)) { 2818 BGE_SETBIT(sc, BGE_RX_MODE, 2819 BGE_RXMODE_RX_PROMISC); 2820 } else if (ifp->if_flags & IFF_RUNNING && 2821 !(ifp->if_flags & IFF_PROMISC) && 2822 sc->bge_if_flags & IFF_PROMISC) { 2823 BGE_CLRBIT(sc, BGE_RX_MODE, 2824 BGE_RXMODE_RX_PROMISC); 2825 } else 2826 bge_init(sc); 2827 } else { 2828 if (ifp->if_flags & IFF_RUNNING) { 2829 bge_stop(sc); 2830 } 2831 } 2832 sc->bge_if_flags = ifp->if_flags; 2833 error = 0; 2834 break; 2835 case SIOCADDMULTI: 2836 case SIOCDELMULTI: 2837 if (ifp->if_flags & IFF_RUNNING) { 2838 bge_setmulti(sc); 2839 error = 0; 2840 } 2841 break; 2842 case SIOCSIFMEDIA: 2843 case SIOCGIFMEDIA: 2844 if (sc->bge_tbi) { 2845 error = ifmedia_ioctl(ifp, ifr, 2846 &sc->bge_ifmedia, command); 2847 } else { 2848 mii = device_get_softc(sc->bge_miibus); 2849 error = ifmedia_ioctl(ifp, ifr, 2850 &mii->mii_media, command); 2851 } 2852 break; 2853 case SIOCSIFCAP: 2854 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2855 if (mask & IFCAP_HWCSUM) { 2856 if (IFCAP_HWCSUM & ifp->if_capenable) 2857 ifp->if_capenable &= ~IFCAP_HWCSUM; 2858 else 2859 ifp->if_capenable |= IFCAP_HWCSUM; 2860 } 2861 error = 0; 2862 break; 2863 default: 2864 error = EINVAL; 2865 break; 2866 } 2867 2868 (void)splx(s); 2869 2870 return(error); 2871 } 2872 2873 static void 2874 bge_watchdog(ifp) 2875 struct ifnet *ifp; 2876 { 2877 struct bge_softc *sc; 2878 2879 sc = ifp->if_softc; 2880 2881 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2882 2883 ifp->if_flags &= ~IFF_RUNNING; 2884 bge_init(sc); 2885 2886 ifp->if_oerrors++; 2887 2888 return; 2889 } 2890 2891 /* 2892 * Stop the adapter and free any mbufs allocated to the 2893 * RX and TX lists. 2894 */ 2895 static void 2896 bge_stop(sc) 2897 struct bge_softc *sc; 2898 { 2899 struct ifnet *ifp; 2900 struct ifmedia_entry *ifm; 2901 struct mii_data *mii = NULL; 2902 int mtmp, itmp; 2903 2904 ifp = &sc->arpcom.ac_if; 2905 2906 if (!sc->bge_tbi) 2907 mii = device_get_softc(sc->bge_miibus); 2908 2909 callout_stop(&sc->bge_stat_timer); 2910 2911 /* 2912 * Disable all of the receiver blocks 2913 */ 2914 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2915 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2916 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2917 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2918 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2919 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2920 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2921 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2922 2923 /* 2924 * Disable all of the transmit blocks 2925 */ 2926 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2927 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2928 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2929 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2930 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2931 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2932 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2933 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2934 2935 /* 2936 * Shut down all of the memory managers and related 2937 * state machines. 2938 */ 2939 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2940 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2941 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2942 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2943 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2944 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2945 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2946 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2947 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2948 } 2949 2950 /* Disable host interrupts. */ 2951 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2952 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2953 2954 /* 2955 * Tell firmware we're shutting down. 2956 */ 2957 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2958 2959 /* Free the RX lists. */ 2960 bge_free_rx_ring_std(sc); 2961 2962 /* Free jumbo RX list. */ 2963 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2964 bge_free_rx_ring_jumbo(sc); 2965 2966 /* Free TX buffers. */ 2967 bge_free_tx_ring(sc); 2968 2969 /* 2970 * Isolate/power down the PHY, but leave the media selection 2971 * unchanged so that things will be put back to normal when 2972 * we bring the interface back up. 2973 */ 2974 if (!sc->bge_tbi) { 2975 itmp = ifp->if_flags; 2976 ifp->if_flags |= IFF_UP; 2977 ifm = mii->mii_media.ifm_cur; 2978 mtmp = ifm->ifm_media; 2979 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2980 mii_mediachg(mii); 2981 ifm->ifm_media = mtmp; 2982 ifp->if_flags = itmp; 2983 } 2984 2985 sc->bge_link = 0; 2986 2987 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2988 2989 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2990 2991 return; 2992 } 2993 2994 /* 2995 * Stop all chip I/O so that the kernel's probe routines don't 2996 * get confused by errant DMAs when rebooting. 2997 */ 2998 static void 2999 bge_shutdown(dev) 3000 device_t dev; 3001 { 3002 struct bge_softc *sc; 3003 3004 sc = device_get_softc(dev); 3005 3006 bge_stop(sc); 3007 bge_reset(sc); 3008 3009 return; 3010 } 3011