1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.52 2005/12/31 14:07:59 sephe Exp $ 35 * 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include "opt_bge.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/sockio.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 #include <sys/queue.h> 85 #include <sys/serialize.h> 86 #include <sys/thread2.h> 87 88 #include <net/if.h> 89 #include <net/ifq_var.h> 90 #include <net/if_arp.h> 91 #include <net/ethernet.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 95 #include <net/bpf.h> 96 97 #include <net/if_types.h> 98 #include <net/vlan/if_vlan_var.h> 99 100 #include <netinet/in_systm.h> 101 #include <netinet/in.h> 102 #include <netinet/ip.h> 103 104 #include <vm/vm.h> /* for vtophys */ 105 #include <vm/pmap.h> /* for vtophys */ 106 #include <machine/resource.h> 107 #include <sys/bus.h> 108 #include <sys/rman.h> 109 110 #include <dev/netif/mii_layer/mii.h> 111 #include <dev/netif/mii_layer/miivar.h> 112 #include <dev/netif/mii_layer/miidevs.h> 113 #include <dev/netif/mii_layer/brgphyreg.h> 114 115 #include <bus/pci/pcidevs.h> 116 #include <bus/pci/pcireg.h> 117 #include <bus/pci/pcivar.h> 118 119 #include "if_bgereg.h" 120 121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 122 123 /* "controller miibus0" required. See GENERIC if you get errors here. */ 124 #include "miibus_if.h" 125 126 /* 127 * Various supported device vendors/types and their names. Note: the 128 * spec seems to indicate that the hardware still has Alteon's vendor 129 * ID burned into it, though it will always be overriden by the vendor 130 * ID in the EEPROM. Just to be safe, we cover all possibilities. 131 */ 132 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 133 134 static struct bge_type bge_devs[] = { 135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 136 "Alteon BCM5700 Gigabit Ethernet" }, 137 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701, 138 "Alteon BCM5701 Gigabit Ethernet" }, 139 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700, 140 "Broadcom BCM5700 Gigabit Ethernet" }, 141 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701, 142 "Broadcom BCM5701 Gigabit Ethernet" }, 143 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X, 144 "Broadcom BCM5702X Gigabit Ethernet" }, 145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT, 146 "Broadcom BCM5702 Gigabit Ethernet" }, 147 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X, 148 "Broadcom BCM5703X Gigabit Ethernet" }, 149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3, 150 "Broadcom BCM5703 Gigabit Ethernet" }, 151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C, 152 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S, 154 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705, 156 "Broadcom BCM5705 Gigabit Ethernet" }, 157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K, 158 "Broadcom BCM5705K Gigabit Ethernet" }, 159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M, 160 "Broadcom BCM5705M Gigabit Ethernet" }, 161 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 162 "Broadcom BCM5705M Gigabit Ethernet" }, 163 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5714C, 164 "Broadcom BCM5714C Gigabit Ethernet" }, 165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721, 166 "Broadcom BCM5721 Gigabit Ethernet" }, 167 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750, 168 "Broadcom BCM5750 Gigabit Ethernet" }, 169 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M, 170 "Broadcom BCM5750M Gigabit Ethernet" }, 171 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751, 172 "Broadcom BCM5751 Gigabit Ethernet" }, 173 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M, 174 "Broadcom BCM5751M Gigabit Ethernet" }, 175 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782, 176 "Broadcom BCM5782 Gigabit Ethernet" }, 177 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788, 178 "Broadcom BCM5788 Gigabit Ethernet" }, 179 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789, 180 "Broadcom BCM5789 Gigabit Ethernet" }, 181 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901, 182 "Broadcom BCM5901 Fast Ethernet" }, 183 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2, 184 "Broadcom BCM5901A2 Fast Ethernet" }, 185 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 186 "SysKonnect Gigabit Ethernet" }, 187 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000, 188 "Altima AC1000 Gigabit Ethernet" }, 189 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001, 190 "Altima AC1002 Gigabit Ethernet" }, 191 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100, 192 "Altima AC9100 Gigabit Ethernet" }, 193 { 0, 0, NULL } 194 }; 195 196 static int bge_probe(device_t); 197 static int bge_attach(device_t); 198 static int bge_detach(device_t); 199 static void bge_release_resources(struct bge_softc *); 200 static void bge_txeof(struct bge_softc *); 201 static void bge_rxeof(struct bge_softc *); 202 203 static void bge_tick(void *); 204 static void bge_tick_serialized(void *); 205 static void bge_stats_update(struct bge_softc *); 206 static void bge_stats_update_regs(struct bge_softc *); 207 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 208 209 static void bge_intr(void *); 210 static void bge_start(struct ifnet *); 211 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 212 static void bge_init(void *); 213 static void bge_stop(struct bge_softc *); 214 static void bge_watchdog(struct ifnet *); 215 static void bge_shutdown(device_t); 216 static int bge_ifmedia_upd(struct ifnet *); 217 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t); 221 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 static struct bge_jslot 228 *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(void *); 230 static void bge_jref(void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 243 #ifdef notdef 244 static uint8_t bge_vpd_readbyte(struct bge_softc *, uint32_t); 245 static void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t); 246 static void bge_vpd_read(struct bge_softc *); 247 #endif 248 249 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t); 250 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t); 251 #ifdef notdef 252 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t); 253 #endif 254 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t); 255 256 static int bge_miibus_readreg(device_t, int, int); 257 static int bge_miibus_writereg(device_t, int, int, int); 258 static void bge_miibus_statchg(device_t); 259 260 static void bge_reset(struct bge_softc *); 261 262 static device_method_t bge_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, bge_probe), 265 DEVMETHOD(device_attach, bge_attach), 266 DEVMETHOD(device_detach, bge_detach), 267 DEVMETHOD(device_shutdown, bge_shutdown), 268 269 /* bus interface */ 270 DEVMETHOD(bus_print_child, bus_generic_print_child), 271 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 272 273 /* MII interface */ 274 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 275 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 276 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 277 278 { 0, 0 } 279 }; 280 281 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc)); 282 static devclass_t bge_devclass; 283 284 DECLARE_DUMMY_MODULE(if_bge); 285 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 286 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 287 288 static uint32_t 289 bge_readmem_ind(struct bge_softc *sc, uint32_t off) 290 { 291 device_t dev = sc->bge_dev; 292 293 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 294 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 295 } 296 297 static void 298 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 299 { 300 device_t dev = sc->bge_dev; 301 302 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 303 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 304 } 305 306 #ifdef notdef 307 static uint32_t 308 bge_readreg_ind(struct bge_softc *sc, uin32_t off) 309 { 310 device_t dev = sc->bge_dev; 311 312 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 313 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 314 } 315 #endif 316 317 static void 318 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 319 { 320 device_t dev = sc->bge_dev; 321 322 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 323 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 324 } 325 326 #ifdef notdef 327 static uint8_t 328 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr) 329 { 330 device_t dev = sc->bge_dev; 331 uint32_t val; 332 int i; 333 334 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 335 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 336 DELAY(10); 337 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 338 break; 339 } 340 341 if (i == BGE_TIMEOUT) { 342 device_printf(sc->bge_dev, "VPD read timed out\n"); 343 return(0); 344 } 345 346 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 347 348 return((val >> ((addr % 4) * 8)) & 0xFF); 349 } 350 351 static void 352 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr) 353 { 354 size_t i; 355 uint8_t *ptr; 356 357 ptr = (uint8_t *)res; 358 for (i = 0; i < sizeof(struct vpd_res); i++) 359 ptr[i] = bge_vpd_readbyte(sc, i + addr); 360 361 return; 362 } 363 364 static void 365 bge_vpd_read(struct bge_softc *sc) 366 { 367 int pos = 0, i; 368 struct vpd_res res; 369 370 if (sc->bge_vpd_prodname != NULL) 371 free(sc->bge_vpd_prodname, M_DEVBUF); 372 if (sc->bge_vpd_readonly != NULL) 373 free(sc->bge_vpd_readonly, M_DEVBUF); 374 sc->bge_vpd_prodname = NULL; 375 sc->bge_vpd_readonly = NULL; 376 377 bge_vpd_read_res(sc, &res, pos); 378 379 if (res.vr_id != VPD_RES_ID) { 380 device_printf(sc->bge_dev, 381 "bad VPD resource id: expected %x got %x\n", 382 VPD_RES_ID, res.vr_id); 383 return; 384 } 385 386 pos += sizeof(res); 387 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 388 for (i = 0; i < res.vr_len; i++) 389 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 390 sc->bge_vpd_prodname[i] = '\0'; 391 pos += i; 392 393 bge_vpd_read_res(sc, &res, pos); 394 395 if (res.vr_id != VPD_RES_READ) { 396 device_printf(sc->bge_dev, 397 "bad VPD resource id: expected %x got %x\n", 398 VPD_RES_READ, res.vr_id); 399 return; 400 } 401 402 pos += sizeof(res); 403 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 404 for (i = 0; i < res.vr_len + 1; i++) 405 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 406 } 407 #endif 408 409 /* 410 * Read a byte of data stored in the EEPROM at address 'addr.' The 411 * BCM570x supports both the traditional bitbang interface and an 412 * auto access interface for reading the EEPROM. We use the auto 413 * access method. 414 */ 415 static uint8_t 416 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest) 417 { 418 int i; 419 uint32_t byte = 0; 420 421 /* 422 * Enable use of auto EEPROM access so we can avoid 423 * having to use the bitbang method. 424 */ 425 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 426 427 /* Reset the EEPROM, load the clock period. */ 428 CSR_WRITE_4(sc, BGE_EE_ADDR, 429 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 430 DELAY(20); 431 432 /* Issue the read EEPROM command. */ 433 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 434 435 /* Wait for completion */ 436 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 437 DELAY(10); 438 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 439 break; 440 } 441 442 if (i == BGE_TIMEOUT) { 443 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n"); 444 return(0); 445 } 446 447 /* Get result. */ 448 byte = CSR_READ_4(sc, BGE_EE_DATA); 449 450 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 451 452 return(0); 453 } 454 455 /* 456 * Read a sequence of bytes from the EEPROM. 457 */ 458 static int 459 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len) 460 { 461 size_t i; 462 int err; 463 uint8_t byte; 464 465 for (byte = 0, err = 0, i = 0; i < len; i++) { 466 err = bge_eeprom_getbyte(sc, off + i, &byte); 467 if (err) 468 break; 469 *(dest + i) = byte; 470 } 471 472 return(err ? 1 : 0); 473 } 474 475 static int 476 bge_miibus_readreg(device_t dev, int phy, int reg) 477 { 478 struct bge_softc *sc; 479 struct ifnet *ifp; 480 uint32_t val, autopoll; 481 int i; 482 483 sc = device_get_softc(dev); 484 ifp = &sc->arpcom.ac_if; 485 486 /* 487 * Broadcom's own driver always assumes the internal 488 * PHY is at GMII address 1. On some chips, the PHY responds 489 * to accesses at all addresses, which could cause us to 490 * bogusly attach the PHY 32 times at probe type. Always 491 * restricting the lookup to address 1 is simpler than 492 * trying to figure out which chips revisions should be 493 * special-cased. 494 */ 495 if (phy != 1) 496 return(0); 497 498 /* Reading with autopolling on may trigger PCI errors */ 499 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 500 if (autopoll & BGE_MIMODE_AUTOPOLL) { 501 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 502 DELAY(40); 503 } 504 505 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 506 BGE_MIPHY(phy)|BGE_MIREG(reg)); 507 508 for (i = 0; i < BGE_TIMEOUT; i++) { 509 val = CSR_READ_4(sc, BGE_MI_COMM); 510 if (!(val & BGE_MICOMM_BUSY)) 511 break; 512 } 513 514 if (i == BGE_TIMEOUT) { 515 if_printf(ifp, "PHY read timed out\n"); 516 val = 0; 517 goto done; 518 } 519 520 val = CSR_READ_4(sc, BGE_MI_COMM); 521 522 done: 523 if (autopoll & BGE_MIMODE_AUTOPOLL) { 524 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 525 DELAY(40); 526 } 527 528 if (val & BGE_MICOMM_READFAIL) 529 return(0); 530 531 return(val & 0xFFFF); 532 } 533 534 static int 535 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 536 { 537 struct bge_softc *sc; 538 uint32_t autopoll; 539 int i; 540 541 sc = device_get_softc(dev); 542 543 /* Reading with autopolling on may trigger PCI errors */ 544 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 545 if (autopoll & BGE_MIMODE_AUTOPOLL) { 546 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 547 DELAY(40); 548 } 549 550 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 551 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 552 553 for (i = 0; i < BGE_TIMEOUT; i++) { 554 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 555 break; 556 } 557 558 if (autopoll & BGE_MIMODE_AUTOPOLL) { 559 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 560 DELAY(40); 561 } 562 563 if (i == BGE_TIMEOUT) { 564 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n"); 565 return(0); 566 } 567 568 return(0); 569 } 570 571 static void 572 bge_miibus_statchg(device_t dev) 573 { 574 struct bge_softc *sc; 575 struct mii_data *mii; 576 577 sc = device_get_softc(dev); 578 mii = device_get_softc(sc->bge_miibus); 579 580 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 581 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 582 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 583 } else { 584 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 585 } 586 587 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 588 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 589 } else { 590 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 591 } 592 } 593 594 /* 595 * Handle events that have triggered interrupts. 596 */ 597 static void 598 bge_handle_events(struct bge_softc *sc) 599 { 600 } 601 602 /* 603 * Memory management for jumbo frames. 604 */ 605 static int 606 bge_alloc_jumbo_mem(struct bge_softc *sc) 607 { 608 struct bge_jslot *entry; 609 caddr_t ptr; 610 int i; 611 612 /* Grab a big chunk o' storage. */ 613 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 614 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 615 616 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 617 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n"); 618 return(ENOBUFS); 619 } 620 621 SLIST_INIT(&sc->bge_jfree_listhead); 622 623 /* 624 * Now divide it up into 9K pieces and save the addresses 625 * in an array. Note that we play an evil trick here by using 626 * the first few bytes in the buffer to hold the the address 627 * of the softc structure for this interface. This is because 628 * bge_jfree() needs it, but it is called by the mbuf management 629 * code which will not pass it to us explicitly. 630 */ 631 ptr = sc->bge_cdata.bge_jumbo_buf; 632 for (i = 0; i < BGE_JSLOTS; i++) { 633 entry = &sc->bge_cdata.bge_jslots[i]; 634 entry->bge_sc = sc; 635 entry->bge_buf = ptr; 636 entry->bge_inuse = 0; 637 entry->bge_slot = i; 638 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link); 639 ptr += BGE_JLEN; 640 } 641 642 return(0); 643 } 644 645 static void 646 bge_free_jumbo_mem(struct bge_softc *sc) 647 { 648 if (sc->bge_cdata.bge_jumbo_buf) 649 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 650 } 651 652 /* 653 * Allocate a jumbo buffer. 654 */ 655 static struct bge_jslot * 656 bge_jalloc(struct bge_softc *sc) 657 { 658 struct bge_jslot *entry; 659 660 lwkt_serialize_enter(&sc->bge_jslot_serializer); 661 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 662 if (entry) { 663 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link); 664 entry->bge_inuse = 1; 665 } else { 666 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 667 } 668 lwkt_serialize_exit(&sc->bge_jslot_serializer); 669 return(entry); 670 } 671 672 /* 673 * Adjust usage count on a jumbo buffer. 674 */ 675 static void 676 bge_jref(void *arg) 677 { 678 struct bge_jslot *entry = (struct bge_jslot *)arg; 679 struct bge_softc *sc = entry->bge_sc; 680 681 if (sc == NULL) 682 panic("bge_jref: can't find softc pointer!"); 683 684 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 685 panic("bge_jref: asked to reference buffer " 686 "that we don't manage!"); 687 } else if (entry->bge_inuse == 0) { 688 panic("bge_jref: buffer already free!"); 689 } else { 690 atomic_add_int(&entry->bge_inuse, 1); 691 } 692 } 693 694 /* 695 * Release a jumbo buffer. 696 */ 697 static void 698 bge_jfree(void *arg) 699 { 700 struct bge_jslot *entry = (struct bge_jslot *)arg; 701 struct bge_softc *sc = entry->bge_sc; 702 703 if (sc == NULL) 704 panic("bge_jfree: can't find softc pointer!"); 705 706 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 707 panic("bge_jfree: asked to free buffer that we don't manage!"); 708 } else if (entry->bge_inuse == 0) { 709 panic("bge_jfree: buffer already free!"); 710 } else { 711 /* 712 * Possible MP race to 0, use the serializer. The atomic insn 713 * is still needed for races against bge_jref(). 714 */ 715 lwkt_serialize_enter(&sc->bge_jslot_serializer); 716 atomic_subtract_int(&entry->bge_inuse, 1); 717 if (entry->bge_inuse == 0) { 718 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 719 entry, jslot_link); 720 } 721 lwkt_serialize_exit(&sc->bge_jslot_serializer); 722 } 723 } 724 725 726 /* 727 * Intialize a standard receive ring descriptor. 728 */ 729 static int 730 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 731 { 732 struct mbuf *m_new = NULL; 733 struct bge_rx_bd *r; 734 735 if (m == NULL) { 736 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 737 if (m_new == NULL) 738 return (ENOBUFS); 739 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 740 } else { 741 m_new = m; 742 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 743 m_new->m_data = m_new->m_ext.ext_buf; 744 } 745 746 if (!sc->bge_rx_alignment_bug) 747 m_adj(m_new, ETHER_ALIGN); 748 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 749 r = &sc->bge_rdata->bge_rx_std_ring[i]; 750 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 751 r->bge_flags = BGE_RXBDFLAG_END; 752 r->bge_len = m_new->m_len; 753 r->bge_idx = i; 754 755 return(0); 756 } 757 758 /* 759 * Initialize a jumbo receive ring descriptor. This allocates 760 * a jumbo buffer from the pool managed internally by the driver. 761 */ 762 static int 763 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 764 { 765 struct mbuf *m_new = NULL; 766 struct bge_rx_bd *r; 767 768 if (m == NULL) { 769 struct bge_jslot *buf; 770 771 /* Allocate the mbuf. */ 772 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 773 if (m_new == NULL) 774 return(ENOBUFS); 775 776 /* Allocate the jumbo buffer */ 777 buf = bge_jalloc(sc); 778 if (buf == NULL) { 779 m_freem(m_new); 780 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed " 781 "-- packet dropped!\n"); 782 return(ENOBUFS); 783 } 784 785 /* Attach the buffer to the mbuf. */ 786 m_new->m_ext.ext_arg = buf; 787 m_new->m_ext.ext_buf = buf->bge_buf; 788 m_new->m_ext.ext_free = bge_jfree; 789 m_new->m_ext.ext_ref = bge_jref; 790 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 791 792 m_new->m_data = m_new->m_ext.ext_buf; 793 m_new->m_flags |= M_EXT; 794 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 795 } else { 796 m_new = m; 797 m_new->m_data = m_new->m_ext.ext_buf; 798 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 799 } 800 801 if (!sc->bge_rx_alignment_bug) 802 m_adj(m_new, ETHER_ALIGN); 803 /* Set up the descriptor. */ 804 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 805 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 806 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 807 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 808 r->bge_len = m_new->m_len; 809 r->bge_idx = i; 810 811 return(0); 812 } 813 814 /* 815 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 816 * that's 1MB or memory, which is a lot. For now, we fill only the first 817 * 256 ring entries and hope that our CPU is fast enough to keep up with 818 * the NIC. 819 */ 820 static int 821 bge_init_rx_ring_std(struct bge_softc *sc) 822 { 823 int i; 824 825 for (i = 0; i < BGE_SSLOTS; i++) { 826 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 827 return(ENOBUFS); 828 }; 829 830 sc->bge_std = i - 1; 831 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 832 833 return(0); 834 } 835 836 static void 837 bge_free_rx_ring_std(struct bge_softc *sc) 838 { 839 int i; 840 841 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 842 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 843 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 844 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 845 } 846 bzero(&sc->bge_rdata->bge_rx_std_ring[i], 847 sizeof(struct bge_rx_bd)); 848 } 849 } 850 851 static int 852 bge_init_rx_ring_jumbo(struct bge_softc *sc) 853 { 854 int i; 855 struct bge_rcb *rcb; 856 857 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 858 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 859 return(ENOBUFS); 860 }; 861 862 sc->bge_jumbo = i - 1; 863 864 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 865 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 866 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 867 868 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 869 870 return(0); 871 } 872 873 static void 874 bge_free_rx_ring_jumbo(struct bge_softc *sc) 875 { 876 int i; 877 878 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 879 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 880 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 881 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 882 } 883 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i], 884 sizeof(struct bge_rx_bd)); 885 } 886 } 887 888 static void 889 bge_free_tx_ring(struct bge_softc *sc) 890 { 891 int i; 892 893 if (sc->bge_rdata->bge_tx_ring == NULL) 894 return; 895 896 for (i = 0; i < BGE_TX_RING_CNT; i++) { 897 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 898 m_freem(sc->bge_cdata.bge_tx_chain[i]); 899 sc->bge_cdata.bge_tx_chain[i] = NULL; 900 } 901 bzero(&sc->bge_rdata->bge_tx_ring[i], 902 sizeof(struct bge_tx_bd)); 903 } 904 } 905 906 static int 907 bge_init_tx_ring(struct bge_softc *sc) 908 { 909 sc->bge_txcnt = 0; 910 sc->bge_tx_saved_considx = 0; 911 912 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 913 /* 5700 b2 errata */ 914 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 915 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 916 917 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 918 /* 5700 b2 errata */ 919 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 920 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 921 922 return(0); 923 } 924 925 static void 926 bge_setmulti(struct bge_softc *sc) 927 { 928 struct ifnet *ifp; 929 struct ifmultiaddr *ifma; 930 uint32_t hashes[4] = { 0, 0, 0, 0 }; 931 int h, i; 932 933 ifp = &sc->arpcom.ac_if; 934 935 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 936 for (i = 0; i < 4; i++) 937 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 938 return; 939 } 940 941 /* First, zot all the existing filters. */ 942 for (i = 0; i < 4; i++) 943 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 944 945 /* Now program new ones. */ 946 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 947 if (ifma->ifma_addr->sa_family != AF_LINK) 948 continue; 949 h = ether_crc32_le( 950 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 951 ETHER_ADDR_LEN) & 0x7f; 952 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 953 } 954 955 for (i = 0; i < 4; i++) 956 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 957 } 958 959 /* 960 * Do endian, PCI and DMA initialization. Also check the on-board ROM 961 * self-test results. 962 */ 963 static int 964 bge_chipinit(struct bge_softc *sc) 965 { 966 int i; 967 uint32_t dma_rw_ctl; 968 969 /* Set endianness before we access any non-PCI registers. */ 970 #if BYTE_ORDER == BIG_ENDIAN 971 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 972 BGE_BIGENDIAN_INIT, 4); 973 #else 974 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 975 BGE_LITTLEENDIAN_INIT, 4); 976 #endif 977 978 /* 979 * Check the 'ROM failed' bit on the RX CPU to see if 980 * self-tests passed. 981 */ 982 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 983 if_printf(&sc->arpcom.ac_if, 984 "RX CPU self-diagnostics failed!\n"); 985 return(ENODEV); 986 } 987 988 /* Clear the MAC control register */ 989 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 990 991 /* 992 * Clear the MAC statistics block in the NIC's 993 * internal memory. 994 */ 995 for (i = BGE_STATS_BLOCK; 996 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 997 BGE_MEMWIN_WRITE(sc, i, 0); 998 999 for (i = BGE_STATUS_BLOCK; 1000 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1001 BGE_MEMWIN_WRITE(sc, i, 0); 1002 1003 /* Set up the PCI DMA control register. */ 1004 if (sc->bge_pcie) { 1005 /* PCI Express */ 1006 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1007 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1008 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1009 } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1010 BGE_PCISTATE_PCI_BUSMODE) { 1011 /* Conventional PCI bus */ 1012 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1013 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1014 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1015 (0x0F); 1016 } else { 1017 /* PCI-X bus */ 1018 /* 1019 * The 5704 uses a different encoding of read/write 1020 * watermarks. 1021 */ 1022 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1023 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1024 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1025 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1026 else 1027 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1028 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1029 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1030 (0x0F); 1031 1032 /* 1033 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1034 * for hardware bugs. 1035 */ 1036 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1037 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1038 uint32_t tmp; 1039 1040 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1041 if (tmp == 0x6 || tmp == 0x7) 1042 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1043 } 1044 } 1045 1046 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1047 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1048 sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1049 sc->bge_asicrev == BGE_ASICREV_BCM5750) 1050 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1051 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1052 1053 /* 1054 * Set up general mode register. 1055 */ 1056 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1057 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1058 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1059 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1060 1061 /* 1062 * Disable memory write invalidate. Apparently it is not supported 1063 * properly by these devices. 1064 */ 1065 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1066 1067 /* Set the timer prescaler (always 66Mhz) */ 1068 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1069 1070 return(0); 1071 } 1072 1073 static int 1074 bge_blockinit(struct bge_softc *sc) 1075 { 1076 struct bge_rcb *rcb; 1077 volatile struct bge_rcb *vrcb; 1078 int i; 1079 1080 /* 1081 * Initialize the memory window pointer register so that 1082 * we can access the first 32K of internal NIC RAM. This will 1083 * allow us to set up the TX send ring RCBs and the RX return 1084 * ring RCBs, plus other things which live in NIC memory. 1085 */ 1086 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1087 1088 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1089 1090 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1091 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1092 /* Configure mbuf memory pool */ 1093 if (sc->bge_extram) { 1094 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1095 BGE_EXT_SSRAM); 1096 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1097 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1098 else 1099 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1100 } else { 1101 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1102 BGE_BUFFPOOL_1); 1103 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1104 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1105 else 1106 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1107 } 1108 1109 /* Configure DMA resource pool */ 1110 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1111 BGE_DMA_DESCRIPTORS); 1112 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1113 } 1114 1115 /* Configure mbuf pool watermarks */ 1116 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1117 sc->bge_asicrev == BGE_ASICREV_BCM5750) { 1118 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1119 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1120 } else { 1121 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1122 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1123 } 1124 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1125 1126 /* Configure DMA resource watermarks */ 1127 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1128 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1129 1130 /* Enable buffer manager */ 1131 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1132 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1133 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1134 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1135 1136 /* Poll for buffer manager start indication */ 1137 for (i = 0; i < BGE_TIMEOUT; i++) { 1138 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1139 break; 1140 DELAY(10); 1141 } 1142 1143 if (i == BGE_TIMEOUT) { 1144 if_printf(&sc->arpcom.ac_if, 1145 "buffer manager failed to start\n"); 1146 return(ENXIO); 1147 } 1148 } 1149 1150 /* Enable flow-through queues */ 1151 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1152 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1153 1154 /* Wait until queue initialization is complete */ 1155 for (i = 0; i < BGE_TIMEOUT; i++) { 1156 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1157 break; 1158 DELAY(10); 1159 } 1160 1161 if (i == BGE_TIMEOUT) { 1162 if_printf(&sc->arpcom.ac_if, 1163 "flow-through queue init failed\n"); 1164 return(ENXIO); 1165 } 1166 1167 /* Initialize the standard RX ring control block */ 1168 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1169 BGE_HOSTADDR(rcb->bge_hostaddr, 1170 vtophys(&sc->bge_rdata->bge_rx_std_ring)); 1171 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1172 sc->bge_asicrev == BGE_ASICREV_BCM5750) 1173 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1174 else 1175 rcb->bge_maxlen_flags = 1176 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1177 if (sc->bge_extram) 1178 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1179 else 1180 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1181 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1182 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1183 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1184 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1185 1186 /* 1187 * Initialize the jumbo RX ring control block 1188 * We set the 'ring disabled' bit in the flags 1189 * field until we're actually ready to start 1190 * using this ring (i.e. once we set the MTU 1191 * high enough to require it). 1192 */ 1193 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1194 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1195 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1196 BGE_HOSTADDR(rcb->bge_hostaddr, 1197 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring)); 1198 rcb->bge_maxlen_flags = 1199 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1200 BGE_RCB_FLAG_RING_DISABLED); 1201 if (sc->bge_extram) 1202 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1203 else 1204 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1205 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1206 rcb->bge_hostaddr.bge_addr_hi); 1207 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1208 rcb->bge_hostaddr.bge_addr_lo); 1209 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1210 rcb->bge_maxlen_flags); 1211 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1212 1213 /* Set up dummy disabled mini ring RCB */ 1214 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1215 rcb->bge_maxlen_flags = 1216 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1217 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1218 rcb->bge_maxlen_flags); 1219 } 1220 1221 /* 1222 * Set the BD ring replentish thresholds. The recommended 1223 * values are 1/8th the number of descriptors allocated to 1224 * each ring. 1225 */ 1226 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1227 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1228 1229 /* 1230 * Disable all unused send rings by setting the 'ring disabled' 1231 * bit in the flags field of all the TX send ring control blocks. 1232 * These are located in NIC memory. 1233 */ 1234 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1235 BGE_SEND_RING_RCB); 1236 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1237 vrcb->bge_maxlen_flags = 1238 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1239 vrcb->bge_nicaddr = 0; 1240 vrcb++; 1241 } 1242 1243 /* Configure TX RCB 0 (we use only the first ring) */ 1244 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1245 BGE_SEND_RING_RCB); 1246 vrcb->bge_hostaddr.bge_addr_hi = 0; 1247 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring)); 1248 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1249 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1250 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1251 vrcb->bge_maxlen_flags = 1252 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1253 1254 /* Disable all unused RX return rings */ 1255 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1256 BGE_RX_RETURN_RING_RCB); 1257 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1258 vrcb->bge_hostaddr.bge_addr_hi = 0; 1259 vrcb->bge_hostaddr.bge_addr_lo = 0; 1260 vrcb->bge_maxlen_flags = 1261 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1262 BGE_RCB_FLAG_RING_DISABLED); 1263 vrcb->bge_nicaddr = 0; 1264 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1265 (i * (sizeof(uint64_t))), 0); 1266 vrcb++; 1267 } 1268 1269 /* Initialize RX ring indexes */ 1270 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1271 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1272 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1273 1274 /* 1275 * Set up RX return ring 0 1276 * Note that the NIC address for RX return rings is 0x00000000. 1277 * The return rings live entirely within the host, so the 1278 * nicaddr field in the RCB isn't used. 1279 */ 1280 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1281 BGE_RX_RETURN_RING_RCB); 1282 vrcb->bge_hostaddr.bge_addr_hi = 0; 1283 BGE_HOSTADDR(vrcb->bge_hostaddr, 1284 vtophys(&sc->bge_rdata->bge_rx_return_ring)); 1285 vrcb->bge_nicaddr = 0x00000000; 1286 vrcb->bge_maxlen_flags = 1287 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1288 1289 /* Set random backoff seed for TX */ 1290 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1291 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1292 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1293 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1294 BGE_TX_BACKOFF_SEED_MASK); 1295 1296 /* Set inter-packet gap */ 1297 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1298 1299 /* 1300 * Specify which ring to use for packets that don't match 1301 * any RX rules. 1302 */ 1303 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1304 1305 /* 1306 * Configure number of RX lists. One interrupt distribution 1307 * list, sixteen active lists, one bad frames class. 1308 */ 1309 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1310 1311 /* Inialize RX list placement stats mask. */ 1312 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1313 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1314 1315 /* Disable host coalescing until we get it set up */ 1316 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1317 1318 /* Poll to make sure it's shut down. */ 1319 for (i = 0; i < BGE_TIMEOUT; i++) { 1320 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1321 break; 1322 DELAY(10); 1323 } 1324 1325 if (i == BGE_TIMEOUT) { 1326 if_printf(&sc->arpcom.ac_if, 1327 "host coalescing engine failed to idle\n"); 1328 return(ENXIO); 1329 } 1330 1331 /* Set up host coalescing defaults */ 1332 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1333 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1334 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1335 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1336 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1337 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1338 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1339 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1340 } 1341 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1342 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1343 1344 /* Set up address of statistics block */ 1345 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1346 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1347 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1348 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1349 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1350 1351 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1352 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1353 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1354 } 1355 1356 /* Set up address of status block */ 1357 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1358 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1359 vtophys(&sc->bge_rdata->bge_status_block)); 1360 1361 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1362 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1363 1364 /* Turn on host coalescing state machine */ 1365 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1366 1367 /* Turn on RX BD completion state machine and enable attentions */ 1368 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1369 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1370 1371 /* Turn on RX list placement state machine */ 1372 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1373 1374 /* Turn on RX list selector state machine. */ 1375 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1376 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1377 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1378 1379 /* Turn on DMA, clear stats */ 1380 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1381 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1382 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1383 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1384 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1385 1386 /* Set misc. local control, enable interrupts on attentions */ 1387 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1388 1389 #ifdef notdef 1390 /* Assert GPIO pins for PHY reset */ 1391 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1392 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1393 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1394 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1395 #endif 1396 1397 /* Turn on DMA completion state machine */ 1398 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1399 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1400 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1401 1402 /* Turn on write DMA state machine */ 1403 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1404 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1405 1406 /* Turn on read DMA state machine */ 1407 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1408 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1409 1410 /* Turn on RX data completion state machine */ 1411 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1412 1413 /* Turn on RX BD initiator state machine */ 1414 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1415 1416 /* Turn on RX data and RX BD initiator state machine */ 1417 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1418 1419 /* Turn on Mbuf cluster free state machine */ 1420 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1421 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1422 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1423 1424 /* Turn on send BD completion state machine */ 1425 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1426 1427 /* Turn on send data completion state machine */ 1428 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1429 1430 /* Turn on send data initiator state machine */ 1431 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1432 1433 /* Turn on send BD initiator state machine */ 1434 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1435 1436 /* Turn on send BD selector state machine */ 1437 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1438 1439 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1440 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1441 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1442 1443 /* ack/clear link change events */ 1444 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1445 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1446 BGE_MACSTAT_LINK_CHANGED); 1447 1448 /* Enable PHY auto polling (for MII/GMII only) */ 1449 if (sc->bge_tbi) { 1450 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1451 } else { 1452 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1453 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1454 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1455 BGE_EVTENB_MI_INTERRUPT); 1456 } 1457 1458 /* Enable link state change attentions. */ 1459 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1460 1461 return(0); 1462 } 1463 1464 /* 1465 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1466 * against our list and return its name if we find a match. Note 1467 * that since the Broadcom controller contains VPD support, we 1468 * can get the device name string from the controller itself instead 1469 * of the compiled-in string. This is a little slow, but it guarantees 1470 * we'll always announce the right product name. 1471 */ 1472 static int 1473 bge_probe(device_t dev) 1474 { 1475 struct bge_softc *sc; 1476 struct bge_type *t; 1477 char *descbuf; 1478 uint16_t product, vendor; 1479 1480 product = pci_get_device(dev); 1481 vendor = pci_get_vendor(dev); 1482 1483 for (t = bge_devs; t->bge_name != NULL; t++) { 1484 if (vendor == t->bge_vid && product == t->bge_did) 1485 break; 1486 } 1487 1488 if (t->bge_name == NULL) 1489 return(ENXIO); 1490 1491 sc = device_get_softc(dev); 1492 #ifdef notdef 1493 sc->bge_dev = dev; 1494 1495 bge_vpd_read(sc); 1496 device_set_desc(dev, sc->bge_vpd_prodname); 1497 #endif 1498 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK); 1499 snprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name, 1500 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1501 device_set_desc_copy(dev, descbuf); 1502 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) 1503 sc->bge_no_3_led = 1; 1504 free(descbuf, M_TEMP); 1505 return(0); 1506 } 1507 1508 static int 1509 bge_attach(device_t dev) 1510 { 1511 struct ifnet *ifp; 1512 struct bge_softc *sc; 1513 uint32_t hwcfg = 0; 1514 uint32_t mac_addr = 0; 1515 int error = 0, rid; 1516 uint8_t ether_addr[ETHER_ADDR_LEN]; 1517 1518 sc = device_get_softc(dev); 1519 sc->bge_dev = dev; 1520 callout_init(&sc->bge_stat_timer); 1521 lwkt_serialize_init(&sc->bge_jslot_serializer); 1522 1523 /* 1524 * Map control/status registers. 1525 */ 1526 pci_enable_busmaster(dev); 1527 1528 rid = BGE_PCI_BAR0; 1529 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1530 RF_ACTIVE); 1531 1532 if (sc->bge_res == NULL) { 1533 device_printf(dev, "couldn't map memory\n"); 1534 error = ENXIO; 1535 return(error); 1536 } 1537 1538 sc->bge_btag = rman_get_bustag(sc->bge_res); 1539 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1540 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1541 1542 /* Allocate interrupt */ 1543 rid = 0; 1544 1545 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1546 RF_SHAREABLE | RF_ACTIVE); 1547 1548 if (sc->bge_irq == NULL) { 1549 device_printf(dev, "couldn't map interrupt\n"); 1550 error = ENXIO; 1551 goto fail; 1552 } 1553 1554 /* Save ASIC rev. */ 1555 sc->bge_chipid = 1556 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1557 BGE_PCIMISCCTL_ASICREV; 1558 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1559 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1560 1561 /* 1562 * Treat the 5714 like the 5750 until we have more info 1563 * on this chip. 1564 */ 1565 if (sc->bge_asicrev == BGE_ASICREV_BCM5714) 1566 sc->bge_asicrev = BGE_ASICREV_BCM5750; 1567 1568 /* 1569 * XXX: Broadcom Linux driver. Not in specs or eratta. 1570 * PCI-Express? 1571 */ 1572 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 1573 uint32_t v; 1574 1575 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4); 1576 if (((v >> 8) & 0xff) == BGE_PCIE_MSI_CAPID) { 1577 v = pci_read_config(dev, BGE_PCIE_MSI_CAPID, 4); 1578 if ((v & 0xff) == BGE_PCIE_MSI_CAPID_VAL) 1579 sc->bge_pcie = 1; 1580 } 1581 } 1582 1583 ifp = &sc->arpcom.ac_if; 1584 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1585 1586 /* Try to reset the chip. */ 1587 bge_reset(sc); 1588 1589 if (bge_chipinit(sc)) { 1590 device_printf(dev, "chip initialization failed\n"); 1591 error = ENXIO; 1592 goto fail; 1593 } 1594 1595 /* 1596 * Get station address from the EEPROM. 1597 */ 1598 mac_addr = bge_readmem_ind(sc, 0x0c14); 1599 if ((mac_addr >> 16) == 0x484b) { 1600 ether_addr[0] = (uint8_t)(mac_addr >> 8); 1601 ether_addr[1] = (uint8_t)mac_addr; 1602 mac_addr = bge_readmem_ind(sc, 0x0c18); 1603 ether_addr[2] = (uint8_t)(mac_addr >> 24); 1604 ether_addr[3] = (uint8_t)(mac_addr >> 16); 1605 ether_addr[4] = (uint8_t)(mac_addr >> 8); 1606 ether_addr[5] = (uint8_t)mac_addr; 1607 } else if (bge_read_eeprom(sc, ether_addr, 1608 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1609 device_printf(dev, "failed to read station address\n"); 1610 error = ENXIO; 1611 goto fail; 1612 } 1613 1614 /* Allocate the general information block and ring buffers. */ 1615 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1616 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1617 1618 if (sc->bge_rdata == NULL) { 1619 error = ENXIO; 1620 device_printf(dev, "no memory for list buffers!\n"); 1621 goto fail; 1622 } 1623 1624 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1625 1626 /* 1627 * Try to allocate memory for jumbo buffers. 1628 * The 5705/5750 does not appear to support jumbo frames. 1629 */ 1630 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1631 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1632 if (bge_alloc_jumbo_mem(sc)) { 1633 device_printf(dev, "jumbo buffer allocation failed\n"); 1634 error = ENXIO; 1635 goto fail; 1636 } 1637 } 1638 1639 /* Set default tuneable values. */ 1640 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1641 sc->bge_rx_coal_ticks = 150; 1642 sc->bge_tx_coal_ticks = 150; 1643 sc->bge_rx_max_coal_bds = 64; 1644 sc->bge_tx_max_coal_bds = 128; 1645 1646 /* 5705/5750 limits RX return ring to 512 entries. */ 1647 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1648 sc->bge_asicrev == BGE_ASICREV_BCM5750) 1649 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1650 else 1651 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1652 1653 /* Set up ifnet structure */ 1654 ifp->if_softc = sc; 1655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1656 ifp->if_ioctl = bge_ioctl; 1657 ifp->if_start = bge_start; 1658 ifp->if_watchdog = bge_watchdog; 1659 ifp->if_init = bge_init; 1660 ifp->if_mtu = ETHERMTU; 1661 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1662 ifq_set_ready(&ifp->if_snd); 1663 ifp->if_hwassist = BGE_CSUM_FEATURES; 1664 ifp->if_capabilities = IFCAP_HWCSUM; 1665 ifp->if_capenable = ifp->if_capabilities; 1666 1667 /* 1668 * Figure out what sort of media we have by checking the 1669 * hardware config word in the first 32k of NIC internal memory, 1670 * or fall back to examining the EEPROM if necessary. 1671 * Note: on some BCM5700 cards, this value appears to be unset. 1672 * If that's the case, we have to rely on identifying the NIC 1673 * by its PCI subsystem ID, as we do below for the SysKonnect 1674 * SK-9D41. 1675 */ 1676 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1677 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1678 else { 1679 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1680 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1681 hwcfg = ntohl(hwcfg); 1682 } 1683 1684 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1685 sc->bge_tbi = 1; 1686 1687 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1688 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41) 1689 sc->bge_tbi = 1; 1690 1691 if (sc->bge_tbi) { 1692 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1693 bge_ifmedia_upd, bge_ifmedia_sts); 1694 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1695 ifmedia_add(&sc->bge_ifmedia, 1696 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1697 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1698 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1699 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 1700 } else { 1701 /* 1702 * Do transceiver setup. 1703 */ 1704 if (mii_phy_probe(dev, &sc->bge_miibus, 1705 bge_ifmedia_upd, bge_ifmedia_sts)) { 1706 device_printf(dev, "MII without any PHY!\n"); 1707 error = ENXIO; 1708 goto fail; 1709 } 1710 } 1711 1712 /* 1713 * When using the BCM5701 in PCI-X mode, data corruption has 1714 * been observed in the first few bytes of some received packets. 1715 * Aligning the packet buffer in memory eliminates the corruption. 1716 * Unfortunately, this misaligns the packet payloads. On platforms 1717 * which do not support unaligned accesses, we will realign the 1718 * payloads by copying the received packets. 1719 */ 1720 switch (sc->bge_chipid) { 1721 case BGE_CHIPID_BCM5701_A0: 1722 case BGE_CHIPID_BCM5701_B0: 1723 case BGE_CHIPID_BCM5701_B2: 1724 case BGE_CHIPID_BCM5701_B5: 1725 /* If in PCI-X mode, work around the alignment bug. */ 1726 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1727 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1728 BGE_PCISTATE_PCI_BUSSPEED) 1729 sc->bge_rx_alignment_bug = 1; 1730 break; 1731 } 1732 1733 /* 1734 * Call MI attach routine. 1735 */ 1736 ether_ifattach(ifp, ether_addr, NULL); 1737 1738 error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE, 1739 bge_intr, sc, &sc->bge_intrhand, 1740 ifp->if_serializer); 1741 if (error) { 1742 ether_ifdetach(ifp); 1743 device_printf(dev, "couldn't set up irq\n"); 1744 goto fail; 1745 } 1746 1747 return(0); 1748 1749 fail: 1750 bge_detach(dev); 1751 1752 return(error); 1753 } 1754 1755 static int 1756 bge_detach(device_t dev) 1757 { 1758 struct bge_softc *sc = device_get_softc(dev); 1759 struct ifnet *ifp = &sc->arpcom.ac_if; 1760 1761 if (device_is_attached(dev)) { 1762 lwkt_serialize_enter(ifp->if_serializer); 1763 bge_stop(sc); 1764 bge_reset(sc); 1765 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1766 lwkt_serialize_exit(ifp->if_serializer); 1767 1768 ether_ifdetach(ifp); 1769 } 1770 if (sc->bge_tbi) 1771 ifmedia_removeall(&sc->bge_ifmedia); 1772 if (sc->bge_miibus); 1773 device_delete_child(dev, sc->bge_miibus); 1774 bus_generic_detach(dev); 1775 1776 bge_release_resources(sc); 1777 1778 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1779 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1780 bge_free_jumbo_mem(sc); 1781 1782 return(0); 1783 } 1784 1785 static void 1786 bge_release_resources(struct bge_softc *sc) 1787 { 1788 device_t dev; 1789 1790 dev = sc->bge_dev; 1791 1792 if (sc->bge_vpd_prodname != NULL) 1793 free(sc->bge_vpd_prodname, M_DEVBUF); 1794 1795 if (sc->bge_vpd_readonly != NULL) 1796 free(sc->bge_vpd_readonly, M_DEVBUF); 1797 1798 if (sc->bge_irq != NULL) 1799 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1800 1801 if (sc->bge_res != NULL) 1802 bus_release_resource(dev, SYS_RES_MEMORY, 1803 BGE_PCI_BAR0, sc->bge_res); 1804 1805 if (sc->bge_rdata != NULL) 1806 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data), 1807 M_DEVBUF); 1808 1809 return; 1810 } 1811 1812 static void 1813 bge_reset(struct bge_softc *sc) 1814 { 1815 device_t dev; 1816 uint32_t cachesize, command, pcistate, reset; 1817 int i, val = 0; 1818 1819 dev = sc->bge_dev; 1820 1821 /* Save some important PCI state. */ 1822 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1823 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1824 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1825 1826 pci_write_config(dev, BGE_PCI_MISC_CTL, 1827 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1828 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1829 1830 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 1831 1832 /* XXX: Broadcom Linux driver. */ 1833 if (sc->bge_pcie) { 1834 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */ 1835 CSR_WRITE_4(sc, 0x7e2c, 0x20); 1836 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 1837 /* Prevent PCIE link training during global reset */ 1838 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 1839 reset |= (1<<29); 1840 } 1841 } 1842 1843 /* Issue global reset */ 1844 bge_writereg_ind(sc, BGE_MISC_CFG, reset); 1845 1846 DELAY(1000); 1847 1848 /* XXX: Broadcom Linux driver. */ 1849 if (sc->bge_pcie) { 1850 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 1851 uint32_t v; 1852 1853 DELAY(500000); /* wait for link training to complete */ 1854 v = pci_read_config(dev, 0xc4, 4); 1855 pci_write_config(dev, 0xc4, v | (1<<15), 4); 1856 } 1857 /* Set PCIE max payload size and clear error status. */ 1858 pci_write_config(dev, 0xd8, 0xf5000, 4); 1859 } 1860 1861 /* Reset some of the PCI state that got zapped by reset */ 1862 pci_write_config(dev, BGE_PCI_MISC_CTL, 1863 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1864 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1865 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1866 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1867 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1868 1869 /* Enable memory arbiter. */ 1870 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1871 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1872 1873 /* 1874 * Prevent PXE restart: write a magic number to the 1875 * general communications memory at 0xB50. 1876 */ 1877 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1878 /* 1879 * Poll the value location we just wrote until 1880 * we see the 1's complement of the magic number. 1881 * This indicates that the firmware initialization 1882 * is complete. 1883 */ 1884 for (i = 0; i < BGE_TIMEOUT; i++) { 1885 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1886 if (val == ~BGE_MAGIC_NUMBER) 1887 break; 1888 DELAY(10); 1889 } 1890 1891 if (i == BGE_TIMEOUT) { 1892 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n"); 1893 return; 1894 } 1895 1896 /* 1897 * XXX Wait for the value of the PCISTATE register to 1898 * return to its original pre-reset state. This is a 1899 * fairly good indicator of reset completion. If we don't 1900 * wait for the reset to fully complete, trying to read 1901 * from the device's non-PCI registers may yield garbage 1902 * results. 1903 */ 1904 for (i = 0; i < BGE_TIMEOUT; i++) { 1905 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1906 break; 1907 DELAY(10); 1908 } 1909 1910 /* Fix up byte swapping */ 1911 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1912 BGE_MODECTL_BYTESWAP_DATA); 1913 1914 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1915 1916 /* 1917 * The 5704 in TBI mode apparently needs some special 1918 * adjustment to insure the SERDES drive level is set 1919 * to 1.2V. 1920 */ 1921 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) { 1922 uint32_t serdescfg; 1923 1924 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 1925 serdescfg = (serdescfg & ~0xFFF) | 0x880; 1926 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 1927 } 1928 1929 /* XXX: Broadcom Linux driver. */ 1930 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 1931 uint32_t v; 1932 1933 v = CSR_READ_4(sc, 0x7c00); 1934 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 1935 } 1936 1937 DELAY(10000); 1938 } 1939 1940 /* 1941 * Frame reception handling. This is called if there's a frame 1942 * on the receive return list. 1943 * 1944 * Note: we have to be able to handle two possibilities here: 1945 * 1) the frame is from the jumbo recieve ring 1946 * 2) the frame is from the standard receive ring 1947 */ 1948 1949 static void 1950 bge_rxeof(struct bge_softc *sc) 1951 { 1952 struct ifnet *ifp; 1953 int stdcnt = 0, jumbocnt = 0; 1954 1955 ifp = &sc->arpcom.ac_if; 1956 1957 while(sc->bge_rx_saved_considx != 1958 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1959 struct bge_rx_bd *cur_rx; 1960 uint32_t rxidx; 1961 struct mbuf *m = NULL; 1962 uint16_t vlan_tag = 0; 1963 int have_tag = 0; 1964 1965 cur_rx = 1966 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1967 1968 rxidx = cur_rx->bge_idx; 1969 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 1970 1971 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1972 have_tag = 1; 1973 vlan_tag = cur_rx->bge_vlan_tag; 1974 } 1975 1976 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1977 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1978 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1979 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1980 jumbocnt++; 1981 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1982 ifp->if_ierrors++; 1983 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1984 continue; 1985 } 1986 if (bge_newbuf_jumbo(sc, 1987 sc->bge_jumbo, NULL) == ENOBUFS) { 1988 ifp->if_ierrors++; 1989 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1990 continue; 1991 } 1992 } else { 1993 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1994 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1995 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1996 stdcnt++; 1997 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1998 ifp->if_ierrors++; 1999 bge_newbuf_std(sc, sc->bge_std, m); 2000 continue; 2001 } 2002 if (bge_newbuf_std(sc, sc->bge_std, 2003 NULL) == ENOBUFS) { 2004 ifp->if_ierrors++; 2005 bge_newbuf_std(sc, sc->bge_std, m); 2006 continue; 2007 } 2008 } 2009 2010 ifp->if_ipackets++; 2011 #ifndef __i386__ 2012 /* 2013 * The i386 allows unaligned accesses, but for other 2014 * platforms we must make sure the payload is aligned. 2015 */ 2016 if (sc->bge_rx_alignment_bug) { 2017 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2018 cur_rx->bge_len); 2019 m->m_data += ETHER_ALIGN; 2020 } 2021 #endif 2022 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2023 m->m_pkthdr.rcvif = ifp; 2024 2025 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2026 if (ifp->if_hwassist) { 2027 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2028 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2029 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2030 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2031 m->m_pkthdr.csum_data = 2032 cur_rx->bge_tcp_udp_csum; 2033 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2034 } 2035 } 2036 #endif 2037 2038 /* 2039 * If we received a packet with a vlan tag, pass it 2040 * to vlan_input() instead of ether_input(). 2041 */ 2042 if (have_tag) { 2043 VLAN_INPUT_TAG(m, vlan_tag); 2044 have_tag = vlan_tag = 0; 2045 } else { 2046 ifp->if_input(ifp, m); 2047 } 2048 } 2049 2050 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2051 if (stdcnt) 2052 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2053 if (jumbocnt) 2054 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2055 } 2056 2057 static void 2058 bge_txeof(struct bge_softc *sc) 2059 { 2060 struct bge_tx_bd *cur_tx = NULL; 2061 struct ifnet *ifp; 2062 2063 ifp = &sc->arpcom.ac_if; 2064 2065 /* 2066 * Go through our tx ring and free mbufs for those 2067 * frames that have been sent. 2068 */ 2069 while (sc->bge_tx_saved_considx != 2070 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2071 uint32_t idx = 0; 2072 2073 idx = sc->bge_tx_saved_considx; 2074 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2075 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2076 ifp->if_opackets++; 2077 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2078 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2079 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2080 } 2081 sc->bge_txcnt--; 2082 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2083 ifp->if_timer = 0; 2084 } 2085 2086 if (cur_tx != NULL) 2087 ifp->if_flags &= ~IFF_OACTIVE; 2088 } 2089 2090 static void 2091 bge_intr(void *xsc) 2092 { 2093 struct bge_softc *sc = xsc; 2094 struct ifnet *ifp = &sc->arpcom.ac_if; 2095 uint32_t status, statusword, mimode; 2096 2097 /* XXX */ 2098 statusword = loadandclear(&sc->bge_rdata->bge_status_block.bge_status); 2099 2100 #ifdef notdef 2101 /* Avoid this for now -- checking this register is expensive. */ 2102 /* Make sure this is really our interrupt. */ 2103 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2104 return; 2105 #endif 2106 /* Ack interrupt and stop others from occuring. */ 2107 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2108 2109 /* 2110 * Process link state changes. 2111 * Grrr. The link status word in the status block does 2112 * not work correctly on the BCM5700 rev AX and BX chips, 2113 * according to all available information. Hence, we have 2114 * to enable MII interrupts in order to properly obtain 2115 * async link changes. Unfortunately, this also means that 2116 * we have to read the MAC status register to detect link 2117 * changes, thereby adding an additional register access to 2118 * the interrupt handler. 2119 */ 2120 2121 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2122 status = CSR_READ_4(sc, BGE_MAC_STS); 2123 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2124 sc->bge_link = 0; 2125 callout_stop(&sc->bge_stat_timer); 2126 bge_tick_serialized(sc); 2127 /* Clear the interrupt */ 2128 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2129 BGE_EVTENB_MI_INTERRUPT); 2130 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2131 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2132 BRGPHY_INTRS); 2133 } 2134 } else { 2135 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2136 /* 2137 * Sometimes PCS encoding errors are detected in 2138 * TBI mode (on fiber NICs), and for some reason 2139 * the chip will signal them as link changes. 2140 * If we get a link change event, but the 'PCS 2141 * encoding error' bit in the MAC status register 2142 * is set, don't bother doing a link check. 2143 * This avoids spurious "gigabit link up" messages 2144 * that sometimes appear on fiber NICs during 2145 * periods of heavy traffic. (There should be no 2146 * effect on copper NICs.) 2147 * 2148 * If we do have a copper NIC (bge_tbi == 0) then 2149 * check that the AUTOPOLL bit is set before 2150 * processing the event as a real link change. 2151 * Turning AUTOPOLL on and off in the MII read/write 2152 * functions will often trigger a link status 2153 * interrupt for no reason. 2154 */ 2155 status = CSR_READ_4(sc, BGE_MAC_STS); 2156 mimode = CSR_READ_4(sc, BGE_MI_MODE); 2157 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR | 2158 BGE_MACSTAT_MI_COMPLETE)) && 2159 (!sc->bge_tbi && (mimode & BGE_MIMODE_AUTOPOLL))) { 2160 sc->bge_link = 0; 2161 callout_stop(&sc->bge_stat_timer); 2162 bge_tick_serialized(sc); 2163 } 2164 sc->bge_link = 0; 2165 callout_stop(&sc->bge_stat_timer); 2166 bge_tick_serialized(sc); 2167 /* Clear the interrupt */ 2168 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2169 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2170 BGE_MACSTAT_LINK_CHANGED); 2171 2172 /* Force flush the status block cached by PCI bridge */ 2173 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2174 } 2175 } 2176 2177 if (ifp->if_flags & IFF_RUNNING) { 2178 /* Check RX return ring producer/consumer */ 2179 bge_rxeof(sc); 2180 2181 /* Check TX ring producer/consumer */ 2182 bge_txeof(sc); 2183 } 2184 2185 bge_handle_events(sc); 2186 2187 /* Re-enable interrupts. */ 2188 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2189 2190 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 2191 (*ifp->if_start)(ifp); 2192 } 2193 2194 static void 2195 bge_tick(void *xsc) 2196 { 2197 struct bge_softc *sc = xsc; 2198 struct ifnet *ifp = &sc->arpcom.ac_if; 2199 2200 lwkt_serialize_enter(ifp->if_serializer); 2201 bge_tick_serialized(xsc); 2202 lwkt_serialize_exit(ifp->if_serializer); 2203 } 2204 2205 static void 2206 bge_tick_serialized(void *xsc) 2207 { 2208 struct bge_softc *sc = xsc; 2209 struct ifnet *ifp = &sc->arpcom.ac_if; 2210 struct mii_data *mii = NULL; 2211 struct ifmedia *ifm = NULL; 2212 2213 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 2214 sc->bge_asicrev == BGE_ASICREV_BCM5750) 2215 bge_stats_update_regs(sc); 2216 else 2217 bge_stats_update(sc); 2218 2219 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 2220 2221 if (sc->bge_link) { 2222 return; 2223 } 2224 2225 if (sc->bge_tbi) { 2226 ifm = &sc->bge_ifmedia; 2227 if (CSR_READ_4(sc, BGE_MAC_STS) & 2228 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2229 sc->bge_link++; 2230 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 2231 BGE_CLRBIT(sc, BGE_MAC_MODE, 2232 BGE_MACMODE_TBI_SEND_CFGS); 2233 } 2234 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2235 if_printf(ifp, "gigabit link up\n"); 2236 if (!ifq_is_empty(&ifp->if_snd)) 2237 (*ifp->if_start)(ifp); 2238 } 2239 return; 2240 } 2241 2242 mii = device_get_softc(sc->bge_miibus); 2243 mii_tick(mii); 2244 2245 if (!sc->bge_link) { 2246 mii_pollstat(mii); 2247 if (mii->mii_media_status & IFM_ACTIVE && 2248 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2249 sc->bge_link++; 2250 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2251 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2252 if_printf(ifp, "gigabit link up\n"); 2253 if (!ifq_is_empty(&ifp->if_snd)) 2254 (*ifp->if_start)(ifp); 2255 } 2256 } 2257 } 2258 2259 static void 2260 bge_stats_update_regs(struct bge_softc *sc) 2261 { 2262 struct ifnet *ifp = &sc->arpcom.ac_if; 2263 struct bge_mac_stats_regs stats; 2264 uint32_t *s; 2265 int i; 2266 2267 s = (uint32_t *)&stats; 2268 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2269 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2270 s++; 2271 } 2272 2273 ifp->if_collisions += 2274 (stats.dot3StatsSingleCollisionFrames + 2275 stats.dot3StatsMultipleCollisionFrames + 2276 stats.dot3StatsExcessiveCollisions + 2277 stats.dot3StatsLateCollisions) - 2278 ifp->if_collisions; 2279 } 2280 2281 static void 2282 bge_stats_update(struct bge_softc *sc) 2283 { 2284 struct ifnet *ifp = &sc->arpcom.ac_if; 2285 struct bge_stats *stats; 2286 2287 stats = (struct bge_stats *)(sc->bge_vhandle + 2288 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2289 2290 ifp->if_collisions += 2291 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 2292 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 2293 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 2294 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 2295 ifp->if_collisions; 2296 2297 #ifdef notdef 2298 ifp->if_collisions += 2299 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2300 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2301 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2302 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2303 ifp->if_collisions; 2304 #endif 2305 } 2306 2307 /* 2308 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2309 * pointers to descriptors. 2310 */ 2311 static int 2312 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2313 { 2314 struct bge_tx_bd *f = NULL; 2315 struct mbuf *m; 2316 uint32_t frag, cur, cnt = 0; 2317 uint16_t csum_flags = 0; 2318 struct ifvlan *ifv = NULL; 2319 2320 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2321 m_head->m_pkthdr.rcvif != NULL && 2322 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2323 ifv = m_head->m_pkthdr.rcvif->if_softc; 2324 2325 m = m_head; 2326 cur = frag = *txidx; 2327 2328 if (m_head->m_pkthdr.csum_flags) { 2329 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2330 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2331 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2332 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2333 if (m_head->m_flags & M_LASTFRAG) 2334 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2335 else if (m_head->m_flags & M_FRAG) 2336 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2337 } 2338 /* 2339 * Start packing the mbufs in this chain into 2340 * the fragment pointers. Stop when we run out 2341 * of fragments or hit the end of the mbuf chain. 2342 */ 2343 for (m = m_head; m != NULL; m = m->m_next) { 2344 if (m->m_len != 0) { 2345 f = &sc->bge_rdata->bge_tx_ring[frag]; 2346 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2347 break; 2348 BGE_HOSTADDR(f->bge_addr, 2349 vtophys(mtod(m, vm_offset_t))); 2350 f->bge_len = m->m_len; 2351 f->bge_flags = csum_flags; 2352 if (ifv != NULL) { 2353 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2354 f->bge_vlan_tag = ifv->ifv_tag; 2355 } else { 2356 f->bge_vlan_tag = 0; 2357 } 2358 /* 2359 * Sanity check: avoid coming within 16 descriptors 2360 * of the end of the ring. 2361 */ 2362 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2363 return(ENOBUFS); 2364 cur = frag; 2365 BGE_INC(frag, BGE_TX_RING_CNT); 2366 cnt++; 2367 } 2368 } 2369 2370 if (m != NULL) 2371 return(ENOBUFS); 2372 2373 if (frag == sc->bge_tx_saved_considx) 2374 return(ENOBUFS); 2375 2376 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2377 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2378 sc->bge_txcnt += cnt; 2379 2380 *txidx = frag; 2381 2382 return(0); 2383 } 2384 2385 /* 2386 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2387 * to the mbuf data regions directly in the transmit descriptors. 2388 */ 2389 static void 2390 bge_start(struct ifnet *ifp) 2391 { 2392 struct bge_softc *sc; 2393 struct mbuf *m_head = NULL; 2394 uint32_t prodidx = 0; 2395 int need_trans; 2396 2397 sc = ifp->if_softc; 2398 2399 if (!sc->bge_link) 2400 return; 2401 2402 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2403 2404 need_trans = 0; 2405 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2406 m_head = ifq_poll(&ifp->if_snd); 2407 if (m_head == NULL) 2408 break; 2409 2410 /* 2411 * XXX 2412 * safety overkill. If this is a fragmented packet chain 2413 * with delayed TCP/UDP checksums, then only encapsulate 2414 * it if we have enough descriptors to handle the entire 2415 * chain at once. 2416 * (paranoia -- may not actually be needed) 2417 */ 2418 if (m_head->m_flags & M_FIRSTFRAG && 2419 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2420 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2421 m_head->m_pkthdr.csum_data + 16) { 2422 ifp->if_flags |= IFF_OACTIVE; 2423 break; 2424 } 2425 } 2426 2427 /* 2428 * Pack the data into the transmit ring. If we 2429 * don't have room, set the OACTIVE flag and wait 2430 * for the NIC to drain the ring. 2431 */ 2432 if (bge_encap(sc, m_head, &prodidx)) { 2433 ifp->if_flags |= IFF_OACTIVE; 2434 break; 2435 } 2436 ifq_dequeue(&ifp->if_snd, m_head); 2437 need_trans = 1; 2438 2439 BPF_MTAP(ifp, m_head); 2440 } 2441 2442 if (!need_trans) 2443 return; 2444 2445 /* Transmit */ 2446 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2447 /* 5700 b2 errata */ 2448 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2449 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2450 2451 /* 2452 * Set a timeout in case the chip goes out to lunch. 2453 */ 2454 ifp->if_timer = 5; 2455 } 2456 2457 static void 2458 bge_init(void *xsc) 2459 { 2460 struct bge_softc *sc = xsc; 2461 struct ifnet *ifp = &sc->arpcom.ac_if; 2462 uint16_t *m; 2463 2464 if (ifp->if_flags & IFF_RUNNING) { 2465 return; 2466 } 2467 2468 /* Cancel pending I/O and flush buffers. */ 2469 bge_stop(sc); 2470 bge_reset(sc); 2471 bge_chipinit(sc); 2472 2473 /* 2474 * Init the various state machines, ring 2475 * control blocks and firmware. 2476 */ 2477 if (bge_blockinit(sc)) { 2478 if_printf(ifp, "initialization failure\n"); 2479 return; 2480 } 2481 2482 /* Specify MTU. */ 2483 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2484 ETHER_HDR_LEN + ETHER_CRC_LEN); 2485 2486 /* Load our MAC address. */ 2487 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 2488 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2489 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2490 2491 /* Enable or disable promiscuous mode as needed. */ 2492 if (ifp->if_flags & IFF_PROMISC) { 2493 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2494 } else { 2495 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2496 } 2497 2498 /* Program multicast filter. */ 2499 bge_setmulti(sc); 2500 2501 /* Init RX ring. */ 2502 bge_init_rx_ring_std(sc); 2503 2504 /* 2505 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 2506 * memory to insure that the chip has in fact read the first 2507 * entry of the ring. 2508 */ 2509 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 2510 uint32_t v, i; 2511 for (i = 0; i < 10; i++) { 2512 DELAY(20); 2513 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 2514 if (v == (MCLBYTES - ETHER_ALIGN)) 2515 break; 2516 } 2517 if (i == 10) 2518 if_printf(ifp, "5705 A0 chip failed to load RX ring\n"); 2519 } 2520 2521 /* Init jumbo RX ring. */ 2522 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2523 bge_init_rx_ring_jumbo(sc); 2524 2525 /* Init our RX return ring index */ 2526 sc->bge_rx_saved_considx = 0; 2527 2528 /* Init TX ring. */ 2529 bge_init_tx_ring(sc); 2530 2531 /* Turn on transmitter */ 2532 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2533 2534 /* Turn on receiver */ 2535 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2536 2537 /* Tell firmware we're alive. */ 2538 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2539 2540 /* Enable host interrupts. */ 2541 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2542 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2543 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2544 2545 bge_ifmedia_upd(ifp); 2546 2547 ifp->if_flags |= IFF_RUNNING; 2548 ifp->if_flags &= ~IFF_OACTIVE; 2549 2550 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 2551 } 2552 2553 /* 2554 * Set media options. 2555 */ 2556 static int 2557 bge_ifmedia_upd(struct ifnet *ifp) 2558 { 2559 struct bge_softc *sc = ifp->if_softc; 2560 struct ifmedia *ifm = &sc->bge_ifmedia; 2561 struct mii_data *mii; 2562 2563 /* If this is a 1000baseX NIC, enable the TBI port. */ 2564 if (sc->bge_tbi) { 2565 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2566 return(EINVAL); 2567 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2568 case IFM_AUTO: 2569 #ifndef BGE_FAKE_AUTONEG 2570 /* 2571 * The BCM5704 ASIC appears to have a special 2572 * mechanism for programming the autoneg 2573 * advertisement registers in TBI mode. 2574 */ 2575 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 2576 uint32_t sgdig; 2577 2578 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 2579 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 2580 sgdig |= BGE_SGDIGCFG_AUTO | 2581 BGE_SGDIGCFG_PAUSE_CAP | 2582 BGE_SGDIGCFG_ASYM_PAUSE; 2583 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 2584 sgdig | BGE_SGDIGCFG_SEND); 2585 DELAY(5); 2586 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 2587 } 2588 #endif /* !BEG_FAKE_AUTONEG */ 2589 break; 2590 case IFM_1000_SX: 2591 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2592 BGE_CLRBIT(sc, BGE_MAC_MODE, 2593 BGE_MACMODE_HALF_DUPLEX); 2594 } else { 2595 BGE_SETBIT(sc, BGE_MAC_MODE, 2596 BGE_MACMODE_HALF_DUPLEX); 2597 } 2598 break; 2599 default: 2600 return(EINVAL); 2601 } 2602 return(0); 2603 } 2604 2605 mii = device_get_softc(sc->bge_miibus); 2606 sc->bge_link = 0; 2607 if (mii->mii_instance) { 2608 struct mii_softc *miisc; 2609 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2610 miisc = LIST_NEXT(miisc, mii_list)) 2611 mii_phy_reset(miisc); 2612 } 2613 mii_mediachg(mii); 2614 2615 return(0); 2616 } 2617 2618 /* 2619 * Report current media status. 2620 */ 2621 static void 2622 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2623 { 2624 struct bge_softc *sc = ifp->if_softc; 2625 struct mii_data *mii; 2626 2627 if (sc->bge_tbi) { 2628 ifmr->ifm_status = IFM_AVALID; 2629 ifmr->ifm_active = IFM_ETHER; 2630 if (CSR_READ_4(sc, BGE_MAC_STS) & 2631 BGE_MACSTAT_TBI_PCS_SYNCHED) 2632 ifmr->ifm_status |= IFM_ACTIVE; 2633 ifmr->ifm_active |= IFM_1000_SX; 2634 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2635 ifmr->ifm_active |= IFM_HDX; 2636 else 2637 ifmr->ifm_active |= IFM_FDX; 2638 return; 2639 } 2640 2641 mii = device_get_softc(sc->bge_miibus); 2642 mii_pollstat(mii); 2643 ifmr->ifm_active = mii->mii_media_active; 2644 ifmr->ifm_status = mii->mii_media_status; 2645 } 2646 2647 static int 2648 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2649 { 2650 struct bge_softc *sc = ifp->if_softc; 2651 struct ifreq *ifr = (struct ifreq *) data; 2652 int mask, error = 0; 2653 struct mii_data *mii; 2654 2655 switch(command) { 2656 case SIOCSIFMTU: 2657 /* Disallow jumbo frames on 5705/5750. */ 2658 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 || 2659 sc->bge_asicrev == BGE_ASICREV_BCM5750) && 2660 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 2661 error = EINVAL; 2662 else { 2663 ifp->if_mtu = ifr->ifr_mtu; 2664 ifp->if_flags &= ~IFF_RUNNING; 2665 bge_init(sc); 2666 } 2667 break; 2668 case SIOCSIFFLAGS: 2669 if (ifp->if_flags & IFF_UP) { 2670 /* 2671 * If only the state of the PROMISC flag changed, 2672 * then just use the 'set promisc mode' command 2673 * instead of reinitializing the entire NIC. Doing 2674 * a full re-init means reloading the firmware and 2675 * waiting for it to start up, which may take a 2676 * second or two. 2677 */ 2678 if (ifp->if_flags & IFF_RUNNING && 2679 ifp->if_flags & IFF_PROMISC && 2680 !(sc->bge_if_flags & IFF_PROMISC)) { 2681 BGE_SETBIT(sc, BGE_RX_MODE, 2682 BGE_RXMODE_RX_PROMISC); 2683 } else if (ifp->if_flags & IFF_RUNNING && 2684 !(ifp->if_flags & IFF_PROMISC) && 2685 sc->bge_if_flags & IFF_PROMISC) { 2686 BGE_CLRBIT(sc, BGE_RX_MODE, 2687 BGE_RXMODE_RX_PROMISC); 2688 } else 2689 bge_init(sc); 2690 } else { 2691 if (ifp->if_flags & IFF_RUNNING) { 2692 bge_stop(sc); 2693 } 2694 } 2695 sc->bge_if_flags = ifp->if_flags; 2696 error = 0; 2697 break; 2698 case SIOCADDMULTI: 2699 case SIOCDELMULTI: 2700 if (ifp->if_flags & IFF_RUNNING) { 2701 bge_setmulti(sc); 2702 error = 0; 2703 } 2704 break; 2705 case SIOCSIFMEDIA: 2706 case SIOCGIFMEDIA: 2707 if (sc->bge_tbi) { 2708 error = ifmedia_ioctl(ifp, ifr, 2709 &sc->bge_ifmedia, command); 2710 } else { 2711 mii = device_get_softc(sc->bge_miibus); 2712 error = ifmedia_ioctl(ifp, ifr, 2713 &mii->mii_media, command); 2714 } 2715 break; 2716 case SIOCSIFCAP: 2717 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2718 if (mask & IFCAP_HWCSUM) { 2719 if (IFCAP_HWCSUM & ifp->if_capenable) 2720 ifp->if_capenable &= ~IFCAP_HWCSUM; 2721 else 2722 ifp->if_capenable |= IFCAP_HWCSUM; 2723 } 2724 error = 0; 2725 break; 2726 default: 2727 error = ether_ioctl(ifp, command, data); 2728 break; 2729 } 2730 return(error); 2731 } 2732 2733 static void 2734 bge_watchdog(struct ifnet *ifp) 2735 { 2736 struct bge_softc *sc = ifp->if_softc; 2737 2738 if_printf(ifp, "watchdog timeout -- resetting\n"); 2739 2740 ifp->if_flags &= ~IFF_RUNNING; 2741 bge_init(sc); 2742 2743 ifp->if_oerrors++; 2744 2745 if (!ifq_is_empty(&ifp->if_snd)) 2746 ifp->if_start(ifp); 2747 } 2748 2749 /* 2750 * Stop the adapter and free any mbufs allocated to the 2751 * RX and TX lists. 2752 */ 2753 static void 2754 bge_stop(struct bge_softc *sc) 2755 { 2756 struct ifnet *ifp = &sc->arpcom.ac_if; 2757 struct ifmedia_entry *ifm; 2758 struct mii_data *mii = NULL; 2759 int mtmp, itmp; 2760 2761 if (!sc->bge_tbi) 2762 mii = device_get_softc(sc->bge_miibus); 2763 2764 callout_stop(&sc->bge_stat_timer); 2765 2766 /* 2767 * Disable all of the receiver blocks 2768 */ 2769 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2770 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2771 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2772 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2773 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2774 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2775 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2776 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2777 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2778 2779 /* 2780 * Disable all of the transmit blocks 2781 */ 2782 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2783 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2784 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2785 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2786 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2787 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2788 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2789 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2790 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2791 2792 /* 2793 * Shut down all of the memory managers and related 2794 * state machines. 2795 */ 2796 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2797 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2798 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2799 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2800 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2801 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2802 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2803 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2804 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 2805 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2806 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2807 } 2808 2809 /* Disable host interrupts. */ 2810 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2811 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2812 2813 /* 2814 * Tell firmware we're shutting down. 2815 */ 2816 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2817 2818 /* Free the RX lists. */ 2819 bge_free_rx_ring_std(sc); 2820 2821 /* Free jumbo RX list. */ 2822 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2823 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2824 bge_free_rx_ring_jumbo(sc); 2825 2826 /* Free TX buffers. */ 2827 bge_free_tx_ring(sc); 2828 2829 /* 2830 * Isolate/power down the PHY, but leave the media selection 2831 * unchanged so that things will be put back to normal when 2832 * we bring the interface back up. 2833 */ 2834 if (!sc->bge_tbi) { 2835 itmp = ifp->if_flags; 2836 ifp->if_flags |= IFF_UP; 2837 ifm = mii->mii_media.ifm_cur; 2838 mtmp = ifm->ifm_media; 2839 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2840 mii_mediachg(mii); 2841 ifm->ifm_media = mtmp; 2842 ifp->if_flags = itmp; 2843 } 2844 2845 sc->bge_link = 0; 2846 2847 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2848 2849 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2850 } 2851 2852 /* 2853 * Stop all chip I/O so that the kernel's probe routines don't 2854 * get confused by errant DMAs when rebooting. 2855 */ 2856 static void 2857 bge_shutdown(device_t dev) 2858 { 2859 struct bge_softc *sc = device_get_softc(dev); 2860 2861 bge_stop(sc); 2862 bge_reset(sc); 2863 } 2864