1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $ 34 */ 35 36 /* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43 /* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73 #include "opt_ifpoll.h" 74 75 #include <sys/param.h> 76 #include <sys/bus.h> 77 #include <sys/endian.h> 78 #include <sys/kernel.h> 79 #include <sys/ktr.h> 80 #include <sys/interrupt.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/queue.h> 84 #include <sys/rman.h> 85 #include <sys/serialize.h> 86 #include <sys/socket.h> 87 #include <sys/sockio.h> 88 #include <sys/sysctl.h> 89 90 #include <netinet/ip.h> 91 #include <netinet/tcp.h> 92 93 #include <net/bpf.h> 94 #include <net/ethernet.h> 95 #include <net/if.h> 96 #include <net/if_arp.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_poll.h> 100 #include <net/if_types.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <dev/netif/mii_layer/mii.h> 106 #include <dev/netif/mii_layer/miivar.h> 107 #include <dev/netif/mii_layer/brgphyreg.h> 108 109 #include "pcidevs.h" 110 #include <bus/pci/pcireg.h> 111 #include <bus/pci/pcivar.h> 112 113 #include <dev/netif/bge/if_bgereg.h> 114 #include <dev/netif/bge/if_bgevar.h> 115 116 /* "device miibus" required. See GENERIC if you get errors here. */ 117 #include "miibus_if.h" 118 119 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 120 121 #define BGE_RESET_SHUTDOWN 0 122 #define BGE_RESET_START 1 123 #define BGE_RESET_SUSPEND 2 124 125 static const struct bge_type { 126 uint16_t bge_vid; 127 uint16_t bge_did; 128 char *bge_name; 129 } bge_devs[] = { 130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996, 131 "3COM 3C996 Gigabit Ethernet" }, 132 133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 134 "Alteon BCM5700 Gigabit Ethernet" }, 135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701, 136 "Alteon BCM5701 Gigabit Ethernet" }, 137 138 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000, 139 "Altima AC1000 Gigabit Ethernet" }, 140 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001, 141 "Altima AC1002 Gigabit Ethernet" }, 142 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100, 143 "Altima AC9100 Gigabit Ethernet" }, 144 145 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701, 146 "Apple BCM5701 Gigabit Ethernet" }, 147 148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700, 149 "Broadcom BCM5700 Gigabit Ethernet" }, 150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701, 151 "Broadcom BCM5701 Gigabit Ethernet" }, 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702, 153 "Broadcom BCM5702 Gigabit Ethernet" }, 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X, 155 "Broadcom BCM5702X Gigabit Ethernet" }, 156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT, 157 "Broadcom BCM5702 Gigabit Ethernet" }, 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703, 159 "Broadcom BCM5703 Gigabit Ethernet" }, 160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X, 161 "Broadcom BCM5703X Gigabit Ethernet" }, 162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3, 163 "Broadcom BCM5703 Gigabit Ethernet" }, 164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C, 165 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S, 167 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT, 169 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705, 171 "Broadcom BCM5705 Gigabit Ethernet" }, 172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F, 173 "Broadcom BCM5705F Gigabit Ethernet" }, 174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K, 175 "Broadcom BCM5705K Gigabit Ethernet" }, 176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M, 177 "Broadcom BCM5705M Gigabit Ethernet" }, 178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 179 "Broadcom BCM5705M Gigabit Ethernet" }, 180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714, 181 "Broadcom BCM5714C Gigabit Ethernet" }, 182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S, 183 "Broadcom BCM5714S Gigabit Ethernet" }, 184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715, 185 "Broadcom BCM5715 Gigabit Ethernet" }, 186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S, 187 "Broadcom BCM5715S Gigabit Ethernet" }, 188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720, 189 "Broadcom BCM5720 Gigabit Ethernet" }, 190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721, 191 "Broadcom BCM5721 Gigabit Ethernet" }, 192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722, 193 "Broadcom BCM5722 Gigabit Ethernet" }, 194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723, 195 "Broadcom BCM5723 Gigabit Ethernet" }, 196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750, 197 "Broadcom BCM5750 Gigabit Ethernet" }, 198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M, 199 "Broadcom BCM5750M Gigabit Ethernet" }, 200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751, 201 "Broadcom BCM5751 Gigabit Ethernet" }, 202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F, 203 "Broadcom BCM5751F Gigabit Ethernet" }, 204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M, 205 "Broadcom BCM5751M Gigabit Ethernet" }, 206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752, 207 "Broadcom BCM5752 Gigabit Ethernet" }, 208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M, 209 "Broadcom BCM5752M Gigabit Ethernet" }, 210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753, 211 "Broadcom BCM5753 Gigabit Ethernet" }, 212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F, 213 "Broadcom BCM5753F Gigabit Ethernet" }, 214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M, 215 "Broadcom BCM5753M Gigabit Ethernet" }, 216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754, 217 "Broadcom BCM5754 Gigabit Ethernet" }, 218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M, 219 "Broadcom BCM5754M Gigabit Ethernet" }, 220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755, 221 "Broadcom BCM5755 Gigabit Ethernet" }, 222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M, 223 "Broadcom BCM5755M Gigabit Ethernet" }, 224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756, 225 "Broadcom BCM5756 Gigabit Ethernet" }, 226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761, 227 "Broadcom BCM5761 Gigabit Ethernet" }, 228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E, 229 "Broadcom BCM5761E Gigabit Ethernet" }, 230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S, 231 "Broadcom BCM5761S Gigabit Ethernet" }, 232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE, 233 "Broadcom BCM5761SE Gigabit Ethernet" }, 234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764, 235 "Broadcom BCM5764 Gigabit Ethernet" }, 236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780, 237 "Broadcom BCM5780 Gigabit Ethernet" }, 238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S, 239 "Broadcom BCM5780S Gigabit Ethernet" }, 240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781, 241 "Broadcom BCM5781 Gigabit Ethernet" }, 242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782, 243 "Broadcom BCM5782 Gigabit Ethernet" }, 244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784, 245 "Broadcom BCM5784 Gigabit Ethernet" }, 246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F, 247 "Broadcom BCM5785F Gigabit Ethernet" }, 248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G, 249 "Broadcom BCM5785G Gigabit Ethernet" }, 250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786, 251 "Broadcom BCM5786 Gigabit Ethernet" }, 252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787, 253 "Broadcom BCM5787 Gigabit Ethernet" }, 254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F, 255 "Broadcom BCM5787F Gigabit Ethernet" }, 256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M, 257 "Broadcom BCM5787M Gigabit Ethernet" }, 258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788, 259 "Broadcom BCM5788 Gigabit Ethernet" }, 260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789, 261 "Broadcom BCM5789 Gigabit Ethernet" }, 262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901, 263 "Broadcom BCM5901 Fast Ethernet" }, 264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2, 265 "Broadcom BCM5901A2 Fast Ethernet" }, 266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M, 267 "Broadcom BCM5903M Fast Ethernet" }, 268 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906, 269 "Broadcom BCM5906 Fast Ethernet"}, 270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M, 271 "Broadcom BCM5906M Fast Ethernet"}, 272 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760, 273 "Broadcom BCM57760 Gigabit Ethernet"}, 274 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780, 275 "Broadcom BCM57780 Gigabit Ethernet"}, 276 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788, 277 "Broadcom BCM57788 Gigabit Ethernet"}, 278 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790, 279 "Broadcom BCM57790 Gigabit Ethernet"}, 280 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 281 "SysKonnect Gigabit Ethernet" }, 282 283 { 0, 0, NULL } 284 }; 285 286 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 287 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 288 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 289 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 290 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 291 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 292 #define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788) 293 294 #define BGE_IS_CRIPPLED(sc) \ 295 (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700) 296 297 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 298 299 static int bge_probe(device_t); 300 static int bge_attach(device_t); 301 static int bge_detach(device_t); 302 static void bge_txeof(struct bge_softc *, uint16_t); 303 static void bge_rxeof(struct bge_softc *, uint16_t, int); 304 305 static void bge_tick(void *); 306 static void bge_stats_update(struct bge_softc *); 307 static void bge_stats_update_regs(struct bge_softc *); 308 static struct mbuf * 309 bge_defrag_shortdma(struct mbuf *); 310 static int bge_encap(struct bge_softc *, struct mbuf **, 311 uint32_t *, int *); 312 static void bge_xmit(struct bge_softc *, uint32_t); 313 static int bge_setup_tso(struct bge_softc *, struct mbuf **, 314 uint16_t *, uint16_t *); 315 316 #ifdef IFPOLL_ENABLE 317 static void bge_npoll(struct ifnet *, struct ifpoll_info *); 318 static void bge_npoll_compat(struct ifnet *, void *, int ); 319 #endif 320 static void bge_intr_crippled(void *); 321 static void bge_intr_legacy(void *); 322 static void bge_msi(void *); 323 static void bge_msi_oneshot(void *); 324 static void bge_intr(struct bge_softc *); 325 static void bge_enable_intr(struct bge_softc *); 326 static void bge_disable_intr(struct bge_softc *); 327 static void bge_start(struct ifnet *, struct ifaltq_subque *); 328 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 329 static void bge_init(void *); 330 static void bge_stop(struct bge_softc *); 331 static void bge_watchdog(struct ifnet *); 332 static void bge_shutdown(device_t); 333 static int bge_suspend(device_t); 334 static int bge_resume(device_t); 335 static int bge_ifmedia_upd(struct ifnet *); 336 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 337 338 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 339 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 340 341 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *); 342 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t); 343 344 static void bge_setmulti(struct bge_softc *); 345 static void bge_setpromisc(struct bge_softc *); 346 static void bge_enable_msi(struct bge_softc *sc); 347 348 static int bge_alloc_jumbo_mem(struct bge_softc *); 349 static void bge_free_jumbo_mem(struct bge_softc *); 350 static struct bge_jslot 351 *bge_jalloc(struct bge_softc *); 352 static void bge_jfree(void *); 353 static void bge_jref(void *); 354 static int bge_newbuf_std(struct bge_softc *, int, int); 355 static int bge_newbuf_jumbo(struct bge_softc *, int, int); 356 static void bge_setup_rxdesc_std(struct bge_softc *, int); 357 static void bge_setup_rxdesc_jumbo(struct bge_softc *, int); 358 static int bge_init_rx_ring_std(struct bge_softc *); 359 static void bge_free_rx_ring_std(struct bge_softc *); 360 static int bge_init_rx_ring_jumbo(struct bge_softc *); 361 static void bge_free_rx_ring_jumbo(struct bge_softc *); 362 static void bge_free_tx_ring(struct bge_softc *); 363 static int bge_init_tx_ring(struct bge_softc *); 364 365 static int bge_chipinit(struct bge_softc *); 366 static int bge_blockinit(struct bge_softc *); 367 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 368 369 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t); 370 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t); 371 #ifdef notdef 372 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t); 373 #endif 374 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t); 375 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t); 376 static void bge_writembx(struct bge_softc *, int, int); 377 378 static int bge_miibus_readreg(device_t, int, int); 379 static int bge_miibus_writereg(device_t, int, int, int); 380 static void bge_miibus_statchg(device_t); 381 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t); 382 static void bge_tbi_link_upd(struct bge_softc *, uint32_t); 383 static void bge_copper_link_upd(struct bge_softc *, uint32_t); 384 static void bge_autopoll_link_upd(struct bge_softc *, uint32_t); 385 static void bge_link_poll(struct bge_softc *); 386 387 static void bge_reset(struct bge_softc *); 388 389 static int bge_dma_alloc(struct bge_softc *); 390 static void bge_dma_free(struct bge_softc *); 391 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t, 392 bus_dma_tag_t *, bus_dmamap_t *, 393 void **, bus_addr_t *); 394 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *); 395 396 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 397 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 398 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 399 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 400 401 static void bge_coal_change(struct bge_softc *); 402 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS); 403 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS); 404 static int bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS); 405 static int bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS); 406 static int bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS); 407 static int bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS); 408 static int bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS); 409 static int bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS); 410 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, 411 int, int, uint32_t); 412 413 static void bge_sig_post_reset(struct bge_softc *, int); 414 static void bge_sig_legacy(struct bge_softc *, int); 415 static void bge_sig_pre_reset(struct bge_softc *, int); 416 static void bge_stop_fw(struct bge_softc *); 417 static void bge_asf_driver_up(struct bge_softc *); 418 419 static void bge_ape_lock_init(struct bge_softc *); 420 static void bge_ape_read_fw_ver(struct bge_softc *); 421 static int bge_ape_lock(struct bge_softc *, int); 422 static void bge_ape_unlock(struct bge_softc *, int); 423 static void bge_ape_send_event(struct bge_softc *, uint32_t); 424 static void bge_ape_driver_state_change(struct bge_softc *, int); 425 426 /* 427 * Set following tunable to 1 for some IBM blade servers with the DNLK 428 * switch module. Auto negotiation is broken for those configurations. 429 */ 430 static int bge_fake_autoneg = 0; 431 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg); 432 433 static int bge_msi_enable = 1; 434 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable); 435 436 static int bge_allow_asf = 1; 437 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 438 439 #if !defined(KTR_IF_BGE) 440 #define KTR_IF_BGE KTR_ALL 441 #endif 442 KTR_INFO_MASTER(if_bge); 443 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr"); 444 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt"); 445 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt"); 446 #define logif(name) KTR_LOG(if_bge_ ## name) 447 448 static device_method_t bge_methods[] = { 449 /* Device interface */ 450 DEVMETHOD(device_probe, bge_probe), 451 DEVMETHOD(device_attach, bge_attach), 452 DEVMETHOD(device_detach, bge_detach), 453 DEVMETHOD(device_shutdown, bge_shutdown), 454 DEVMETHOD(device_suspend, bge_suspend), 455 DEVMETHOD(device_resume, bge_resume), 456 457 /* bus interface */ 458 DEVMETHOD(bus_print_child, bus_generic_print_child), 459 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 460 461 /* MII interface */ 462 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 463 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 464 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 465 466 DEVMETHOD_END 467 }; 468 469 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc)); 470 static devclass_t bge_devclass; 471 472 DECLARE_DUMMY_MODULE(if_bge); 473 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL); 474 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL); 475 476 static uint32_t 477 bge_readmem_ind(struct bge_softc *sc, uint32_t off) 478 { 479 device_t dev = sc->bge_dev; 480 uint32_t val; 481 482 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 483 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 484 return 0; 485 486 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 487 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 488 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 489 return (val); 490 } 491 492 static void 493 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 494 { 495 device_t dev = sc->bge_dev; 496 497 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 498 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 499 return; 500 501 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 502 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 503 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 504 } 505 506 #ifdef notdef 507 static uint32_t 508 bge_readreg_ind(struct bge_softc *sc, uin32_t off) 509 { 510 device_t dev = sc->bge_dev; 511 512 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 513 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 514 } 515 #endif 516 517 static void 518 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 519 { 520 device_t dev = sc->bge_dev; 521 522 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 523 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 524 } 525 526 static void 527 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val) 528 { 529 CSR_WRITE_4(sc, off, val); 530 } 531 532 static void 533 bge_writembx(struct bge_softc *sc, int off, int val) 534 { 535 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 536 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 537 538 CSR_WRITE_4(sc, off, val); 539 if (sc->bge_mbox_reorder) 540 CSR_READ_4(sc, off); 541 } 542 543 static uint8_t 544 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 545 { 546 uint32_t access, byte = 0; 547 int i; 548 549 /* Lock. */ 550 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 551 for (i = 0; i < 8000; i++) { 552 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 553 break; 554 DELAY(20); 555 } 556 if (i == 8000) 557 return (1); 558 559 /* Enable access. */ 560 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 561 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 562 563 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 564 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 565 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 566 DELAY(10); 567 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 568 DELAY(10); 569 break; 570 } 571 } 572 573 if (i == BGE_TIMEOUT * 10) { 574 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n"); 575 return (1); 576 } 577 578 /* Get result. */ 579 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 580 581 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 582 583 /* Disable access. */ 584 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 585 586 /* Unlock. */ 587 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 588 CSR_READ_4(sc, BGE_NVRAM_SWARB); 589 590 return (0); 591 } 592 593 /* 594 * Read a sequence of bytes from NVRAM. 595 */ 596 static int 597 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 598 { 599 int err = 0, i; 600 uint8_t byte = 0; 601 602 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 603 return (1); 604 605 for (i = 0; i < cnt; i++) { 606 err = bge_nvram_getbyte(sc, off + i, &byte); 607 if (err) 608 break; 609 *(dest + i) = byte; 610 } 611 612 return (err ? 1 : 0); 613 } 614 615 /* 616 * Read a byte of data stored in the EEPROM at address 'addr.' The 617 * BCM570x supports both the traditional bitbang interface and an 618 * auto access interface for reading the EEPROM. We use the auto 619 * access method. 620 */ 621 static uint8_t 622 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest) 623 { 624 int i; 625 uint32_t byte = 0; 626 627 /* 628 * Enable use of auto EEPROM access so we can avoid 629 * having to use the bitbang method. 630 */ 631 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 632 633 /* Reset the EEPROM, load the clock period. */ 634 CSR_WRITE_4(sc, BGE_EE_ADDR, 635 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 636 DELAY(20); 637 638 /* Issue the read EEPROM command. */ 639 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 640 641 /* Wait for completion */ 642 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 643 DELAY(10); 644 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 645 break; 646 } 647 648 if (i == BGE_TIMEOUT) { 649 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n"); 650 return(1); 651 } 652 653 /* Get result. */ 654 byte = CSR_READ_4(sc, BGE_EE_DATA); 655 656 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 657 658 return(0); 659 } 660 661 /* 662 * Read a sequence of bytes from the EEPROM. 663 */ 664 static int 665 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len) 666 { 667 size_t i; 668 int err; 669 uint8_t byte; 670 671 for (byte = 0, err = 0, i = 0; i < len; i++) { 672 err = bge_eeprom_getbyte(sc, off + i, &byte); 673 if (err) 674 break; 675 *(dest + i) = byte; 676 } 677 678 return(err ? 1 : 0); 679 } 680 681 static int 682 bge_miibus_readreg(device_t dev, int phy, int reg) 683 { 684 struct bge_softc *sc = device_get_softc(dev); 685 uint32_t val; 686 int i; 687 688 KASSERT(phy == sc->bge_phyno, 689 ("invalid phyno %d, should be %d", phy, sc->bge_phyno)); 690 691 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 692 return 0; 693 694 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 695 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 696 CSR_WRITE_4(sc, BGE_MI_MODE, 697 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 698 DELAY(80); 699 } 700 701 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 702 BGE_MIPHY(phy) | BGE_MIREG(reg)); 703 704 /* Poll for the PHY register access to complete. */ 705 for (i = 0; i < BGE_TIMEOUT; i++) { 706 DELAY(10); 707 val = CSR_READ_4(sc, BGE_MI_COMM); 708 if ((val & BGE_MICOMM_BUSY) == 0) { 709 DELAY(5); 710 val = CSR_READ_4(sc, BGE_MI_COMM); 711 break; 712 } 713 } 714 if (i == BGE_TIMEOUT) { 715 if_printf(&sc->arpcom.ac_if, "PHY read timed out " 716 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val); 717 val = 0; 718 } 719 720 /* Restore the autopoll bit if necessary. */ 721 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 722 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 723 DELAY(80); 724 } 725 726 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 727 728 if (val & BGE_MICOMM_READFAIL) 729 return 0; 730 731 return (val & 0xFFFF); 732 } 733 734 static int 735 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 736 { 737 struct bge_softc *sc = device_get_softc(dev); 738 int i; 739 740 KASSERT(phy == sc->bge_phyno, 741 ("invalid phyno %d, should be %d", phy, sc->bge_phyno)); 742 743 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 744 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 745 return 0; 746 747 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 748 return 0; 749 750 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 751 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 752 CSR_WRITE_4(sc, BGE_MI_MODE, 753 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 754 DELAY(80); 755 } 756 757 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 758 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 759 760 for (i = 0; i < BGE_TIMEOUT; i++) { 761 DELAY(10); 762 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 763 DELAY(5); 764 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 765 break; 766 } 767 } 768 if (i == BGE_TIMEOUT) { 769 if_printf(&sc->arpcom.ac_if, "PHY write timed out " 770 "(phy %d, reg %d, val %d)\n", phy, reg, val); 771 } 772 773 /* Restore the autopoll bit if necessary. */ 774 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 775 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 776 DELAY(80); 777 } 778 779 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 780 781 return 0; 782 } 783 784 static void 785 bge_miibus_statchg(device_t dev) 786 { 787 struct bge_softc *sc; 788 struct mii_data *mii; 789 uint32_t mac_mode; 790 791 sc = device_get_softc(dev); 792 if ((sc->arpcom.ac_if.if_flags & IFF_RUNNING) == 0) 793 return; 794 795 mii = device_get_softc(sc->bge_miibus); 796 797 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 798 (IFM_ACTIVE | IFM_AVALID)) { 799 switch (IFM_SUBTYPE(mii->mii_media_active)) { 800 case IFM_10_T: 801 case IFM_100_TX: 802 sc->bge_link = 1; 803 break; 804 case IFM_1000_T: 805 case IFM_1000_SX: 806 case IFM_2500_SX: 807 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 808 sc->bge_link = 1; 809 else 810 sc->bge_link = 0; 811 break; 812 default: 813 sc->bge_link = 0; 814 break; 815 } 816 } else { 817 sc->bge_link = 0; 818 } 819 if (sc->bge_link == 0) 820 return; 821 822 /* 823 * APE firmware touches these registers to keep the MAC 824 * connected to the outside world. Try to keep the 825 * accesses atomic. 826 */ 827 828 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 829 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 830 831 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 832 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 833 mac_mode |= BGE_PORTMODE_GMII; 834 else 835 mac_mode |= BGE_PORTMODE_MII; 836 837 if ((mii->mii_media_active & IFM_GMASK) != IFM_FDX) 838 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 839 840 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 841 DELAY(40); 842 } 843 844 /* 845 * Memory management for jumbo frames. 846 */ 847 static int 848 bge_alloc_jumbo_mem(struct bge_softc *sc) 849 { 850 struct ifnet *ifp = &sc->arpcom.ac_if; 851 struct bge_jslot *entry; 852 uint8_t *ptr; 853 bus_addr_t paddr; 854 int i, error; 855 856 /* 857 * Create tag for jumbo mbufs. 858 * This is really a bit of a kludge. We allocate a special 859 * jumbo buffer pool which (thanks to the way our DMA 860 * memory allocation works) will consist of contiguous 861 * pages. This means that even though a jumbo buffer might 862 * be larger than a page size, we don't really need to 863 * map it into more than one DMA segment. However, the 864 * default mbuf tag will result in multi-segment mappings, 865 * so we have to create a special jumbo mbuf tag that 866 * lets us get away with mapping the jumbo buffers as 867 * a single segment. I think eventually the driver should 868 * be changed so that it uses ordinary mbufs and cluster 869 * buffers, i.e. jumbo frames can span multiple DMA 870 * descriptors. But that's a project for another day. 871 */ 872 873 /* 874 * Create DMA stuffs for jumbo RX ring. 875 */ 876 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ, 877 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 878 &sc->bge_cdata.bge_rx_jumbo_ring_map, 879 (void *)&sc->bge_ldata.bge_rx_jumbo_ring, 880 &sc->bge_ldata.bge_rx_jumbo_ring_paddr); 881 if (error) { 882 if_printf(ifp, "could not create jumbo RX ring\n"); 883 return error; 884 } 885 886 /* 887 * Create DMA stuffs for jumbo buffer block. 888 */ 889 error = bge_dma_block_alloc(sc, BGE_JMEM, 890 &sc->bge_cdata.bge_jumbo_tag, 891 &sc->bge_cdata.bge_jumbo_map, 892 (void **)&sc->bge_ldata.bge_jumbo_buf, 893 &paddr); 894 if (error) { 895 if_printf(ifp, "could not create jumbo buffer\n"); 896 return error; 897 } 898 899 SLIST_INIT(&sc->bge_jfree_listhead); 900 901 /* 902 * Now divide it up into 9K pieces and save the addresses 903 * in an array. Note that we play an evil trick here by using 904 * the first few bytes in the buffer to hold the the address 905 * of the softc structure for this interface. This is because 906 * bge_jfree() needs it, but it is called by the mbuf management 907 * code which will not pass it to us explicitly. 908 */ 909 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) { 910 entry = &sc->bge_cdata.bge_jslots[i]; 911 entry->bge_sc = sc; 912 entry->bge_buf = ptr; 913 entry->bge_paddr = paddr; 914 entry->bge_inuse = 0; 915 entry->bge_slot = i; 916 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link); 917 918 ptr += BGE_JLEN; 919 paddr += BGE_JLEN; 920 } 921 return 0; 922 } 923 924 static void 925 bge_free_jumbo_mem(struct bge_softc *sc) 926 { 927 /* Destroy jumbo RX ring. */ 928 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 929 sc->bge_cdata.bge_rx_jumbo_ring_map, 930 sc->bge_ldata.bge_rx_jumbo_ring); 931 932 /* Destroy jumbo buffer block. */ 933 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag, 934 sc->bge_cdata.bge_jumbo_map, 935 sc->bge_ldata.bge_jumbo_buf); 936 } 937 938 /* 939 * Allocate a jumbo buffer. 940 */ 941 static struct bge_jslot * 942 bge_jalloc(struct bge_softc *sc) 943 { 944 struct bge_jslot *entry; 945 946 lwkt_serialize_enter(&sc->bge_jslot_serializer); 947 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 948 if (entry) { 949 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link); 950 entry->bge_inuse = 1; 951 } else { 952 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 953 } 954 lwkt_serialize_exit(&sc->bge_jslot_serializer); 955 return(entry); 956 } 957 958 /* 959 * Adjust usage count on a jumbo buffer. 960 */ 961 static void 962 bge_jref(void *arg) 963 { 964 struct bge_jslot *entry = (struct bge_jslot *)arg; 965 struct bge_softc *sc = entry->bge_sc; 966 967 if (sc == NULL) 968 panic("bge_jref: can't find softc pointer!"); 969 970 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 971 panic("bge_jref: asked to reference buffer " 972 "that we don't manage!"); 973 } else if (entry->bge_inuse == 0) { 974 panic("bge_jref: buffer already free!"); 975 } else { 976 atomic_add_int(&entry->bge_inuse, 1); 977 } 978 } 979 980 /* 981 * Release a jumbo buffer. 982 */ 983 static void 984 bge_jfree(void *arg) 985 { 986 struct bge_jslot *entry = (struct bge_jslot *)arg; 987 struct bge_softc *sc = entry->bge_sc; 988 989 if (sc == NULL) 990 panic("bge_jfree: can't find softc pointer!"); 991 992 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 993 panic("bge_jfree: asked to free buffer that we don't manage!"); 994 } else if (entry->bge_inuse == 0) { 995 panic("bge_jfree: buffer already free!"); 996 } else { 997 /* 998 * Possible MP race to 0, use the serializer. The atomic insn 999 * is still needed for races against bge_jref(). 1000 */ 1001 lwkt_serialize_enter(&sc->bge_jslot_serializer); 1002 atomic_subtract_int(&entry->bge_inuse, 1); 1003 if (entry->bge_inuse == 0) { 1004 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1005 entry, jslot_link); 1006 } 1007 lwkt_serialize_exit(&sc->bge_jslot_serializer); 1008 } 1009 } 1010 1011 1012 /* 1013 * Intialize a standard receive ring descriptor. 1014 */ 1015 static int 1016 bge_newbuf_std(struct bge_softc *sc, int i, int init) 1017 { 1018 struct mbuf *m_new = NULL; 1019 bus_dma_segment_t seg; 1020 bus_dmamap_t map; 1021 int error, nsegs; 1022 1023 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1024 if (m_new == NULL) 1025 return ENOBUFS; 1026 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1027 1028 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1029 m_adj(m_new, ETHER_ALIGN); 1030 1031 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag, 1032 sc->bge_cdata.bge_rx_tmpmap, m_new, 1033 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1034 if (error) { 1035 m_freem(m_new); 1036 return error; 1037 } 1038 1039 if (!init) { 1040 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1041 sc->bge_cdata.bge_rx_std_dmamap[i], 1042 BUS_DMASYNC_POSTREAD); 1043 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1044 sc->bge_cdata.bge_rx_std_dmamap[i]); 1045 } 1046 1047 map = sc->bge_cdata.bge_rx_tmpmap; 1048 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i]; 1049 sc->bge_cdata.bge_rx_std_dmamap[i] = map; 1050 1051 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new; 1052 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr; 1053 1054 bge_setup_rxdesc_std(sc, i); 1055 return 0; 1056 } 1057 1058 static void 1059 bge_setup_rxdesc_std(struct bge_softc *sc, int i) 1060 { 1061 struct bge_rxchain *rc; 1062 struct bge_rx_bd *r; 1063 1064 rc = &sc->bge_cdata.bge_rx_std_chain[i]; 1065 r = &sc->bge_ldata.bge_rx_std_ring[i]; 1066 1067 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr); 1068 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr); 1069 r->bge_len = rc->bge_mbuf->m_len; 1070 r->bge_idx = i; 1071 r->bge_flags = BGE_RXBDFLAG_END; 1072 } 1073 1074 /* 1075 * Initialize a jumbo receive ring descriptor. This allocates 1076 * a jumbo buffer from the pool managed internally by the driver. 1077 */ 1078 static int 1079 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init) 1080 { 1081 struct mbuf *m_new = NULL; 1082 struct bge_jslot *buf; 1083 bus_addr_t paddr; 1084 1085 /* Allocate the mbuf. */ 1086 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1087 if (m_new == NULL) 1088 return ENOBUFS; 1089 1090 /* Allocate the jumbo buffer */ 1091 buf = bge_jalloc(sc); 1092 if (buf == NULL) { 1093 m_freem(m_new); 1094 return ENOBUFS; 1095 } 1096 1097 /* Attach the buffer to the mbuf. */ 1098 m_new->m_ext.ext_arg = buf; 1099 m_new->m_ext.ext_buf = buf->bge_buf; 1100 m_new->m_ext.ext_free = bge_jfree; 1101 m_new->m_ext.ext_ref = bge_jref; 1102 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1103 1104 m_new->m_flags |= M_EXT; 1105 1106 m_new->m_data = m_new->m_ext.ext_buf; 1107 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1108 1109 paddr = buf->bge_paddr; 1110 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) { 1111 m_adj(m_new, ETHER_ALIGN); 1112 paddr += ETHER_ALIGN; 1113 } 1114 1115 /* Save necessary information */ 1116 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new; 1117 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr; 1118 1119 /* Set up the descriptor. */ 1120 bge_setup_rxdesc_jumbo(sc, i); 1121 return 0; 1122 } 1123 1124 static void 1125 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i) 1126 { 1127 struct bge_rx_bd *r; 1128 struct bge_rxchain *rc; 1129 1130 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 1131 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i]; 1132 1133 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr); 1134 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr); 1135 r->bge_len = rc->bge_mbuf->m_len; 1136 r->bge_idx = i; 1137 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1138 } 1139 1140 static int 1141 bge_init_rx_ring_std(struct bge_softc *sc) 1142 { 1143 int i, error; 1144 1145 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1146 error = bge_newbuf_std(sc, i, 1); 1147 if (error) 1148 return error; 1149 } 1150 1151 sc->bge_std = BGE_STD_RX_RING_CNT - 1; 1152 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1153 1154 return(0); 1155 } 1156 1157 static void 1158 bge_free_rx_ring_std(struct bge_softc *sc) 1159 { 1160 int i; 1161 1162 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1163 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i]; 1164 1165 if (rc->bge_mbuf != NULL) { 1166 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1167 sc->bge_cdata.bge_rx_std_dmamap[i]); 1168 m_freem(rc->bge_mbuf); 1169 rc->bge_mbuf = NULL; 1170 } 1171 bzero(&sc->bge_ldata.bge_rx_std_ring[i], 1172 sizeof(struct bge_rx_bd)); 1173 } 1174 } 1175 1176 static int 1177 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1178 { 1179 struct bge_rcb *rcb; 1180 int i, error; 1181 1182 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1183 error = bge_newbuf_jumbo(sc, i, 1); 1184 if (error) 1185 return error; 1186 } 1187 1188 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1; 1189 1190 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1191 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1192 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1193 1194 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1195 1196 return(0); 1197 } 1198 1199 static void 1200 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1201 { 1202 int i; 1203 1204 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1205 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i]; 1206 1207 if (rc->bge_mbuf != NULL) { 1208 m_freem(rc->bge_mbuf); 1209 rc->bge_mbuf = NULL; 1210 } 1211 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i], 1212 sizeof(struct bge_rx_bd)); 1213 } 1214 } 1215 1216 static void 1217 bge_free_tx_ring(struct bge_softc *sc) 1218 { 1219 int i; 1220 1221 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1222 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1223 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1224 sc->bge_cdata.bge_tx_dmamap[i]); 1225 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1226 sc->bge_cdata.bge_tx_chain[i] = NULL; 1227 } 1228 bzero(&sc->bge_ldata.bge_tx_ring[i], 1229 sizeof(struct bge_tx_bd)); 1230 } 1231 } 1232 1233 static int 1234 bge_init_tx_ring(struct bge_softc *sc) 1235 { 1236 sc->bge_txcnt = 0; 1237 sc->bge_tx_saved_considx = 0; 1238 sc->bge_tx_prodidx = 0; 1239 1240 /* Initialize transmit producer index for host-memory send ring. */ 1241 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1242 1243 /* 5700 b2 errata */ 1244 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1245 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1246 1247 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1248 /* 5700 b2 errata */ 1249 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1250 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1251 1252 return(0); 1253 } 1254 1255 static void 1256 bge_setmulti(struct bge_softc *sc) 1257 { 1258 struct ifnet *ifp; 1259 struct ifmultiaddr *ifma; 1260 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1261 int h, i; 1262 1263 ifp = &sc->arpcom.ac_if; 1264 1265 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1266 for (i = 0; i < 4; i++) 1267 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1268 return; 1269 } 1270 1271 /* First, zot all the existing filters. */ 1272 for (i = 0; i < 4; i++) 1273 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1274 1275 /* Now program new ones. */ 1276 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1277 if (ifma->ifma_addr->sa_family != AF_LINK) 1278 continue; 1279 h = ether_crc32_le( 1280 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1281 ETHER_ADDR_LEN) & 0x7f; 1282 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1283 } 1284 1285 for (i = 0; i < 4; i++) 1286 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1287 } 1288 1289 /* 1290 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1291 * self-test results. 1292 */ 1293 static int 1294 bge_chipinit(struct bge_softc *sc) 1295 { 1296 int i; 1297 uint32_t dma_rw_ctl, mode_ctl; 1298 uint16_t val; 1299 1300 /* Set endian type before we access any non-PCI registers. */ 1301 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1302 BGE_INIT | sc->bge_pci_miscctl, 4); 1303 1304 /* 1305 * Clear the MAC statistics block in the NIC's 1306 * internal memory. 1307 */ 1308 for (i = BGE_STATS_BLOCK; 1309 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1310 BGE_MEMWIN_WRITE(sc, i, 0); 1311 1312 for (i = BGE_STATUS_BLOCK; 1313 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1314 BGE_MEMWIN_WRITE(sc, i, 0); 1315 1316 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1317 /* 1318 * Fix data corruption caused by non-qword write with WB. 1319 * Fix master abort in PCI mode. 1320 * Fix PCI latency timer. 1321 */ 1322 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1323 val |= (1 << 10) | (1 << 12) | (1 << 13); 1324 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1325 } 1326 1327 /* Set up the PCI DMA control register. */ 1328 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1329 if (sc->bge_flags & BGE_FLAG_PCIE) { 1330 /* PCI-E bus */ 1331 /* DMA read watermark not used on PCI-E */ 1332 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1333 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1334 /* PCI-X bus */ 1335 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) { 1336 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1337 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1338 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1339 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) { 1340 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1341 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1342 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1343 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1344 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1345 uint32_t rd_wat = 0x7; 1346 uint32_t clkctl; 1347 1348 clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1349 if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) && 1350 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1351 dma_rw_ctl |= 1352 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1353 } else if (clkctl == 0x6 || clkctl == 0x7) { 1354 dma_rw_ctl |= 1355 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1356 } 1357 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) 1358 rd_wat = 0x4; 1359 1360 dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1361 (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1362 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1363 } else { 1364 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1365 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1366 dma_rw_ctl |= 0xf; 1367 } 1368 } else { 1369 /* Conventional PCI bus */ 1370 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1371 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1372 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1373 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1374 dma_rw_ctl |= 0xf; 1375 } 1376 1377 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1378 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1379 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1380 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1381 sc->bge_asicrev == BGE_ASICREV_BCM5701) { 1382 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1383 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1384 } 1385 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1386 1387 /* 1388 * Set up general mode register. 1389 */ 1390 mode_ctl = BGE_DMA_SWAP_OPTIONS| 1391 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1392 BGE_MODECTL_TX_NO_PHDR_CSUM; 1393 1394 /* 1395 * BCM5701 B5 have a bug causing data corruption when using 1396 * 64-bit DMA reads, which can be terminated early and then 1397 * completed later as 32-bit accesses, in combination with 1398 * certain bridges. 1399 */ 1400 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1401 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1402 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1403 1404 /* 1405 * Tell the firmware the driver is running 1406 */ 1407 if (sc->bge_asf_mode & ASF_STACKUP) 1408 mode_ctl |= BGE_MODECTL_STACKUP; 1409 1410 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1411 1412 /* 1413 * Disable memory write invalidate. Apparently it is not supported 1414 * properly by these devices. Also ensure that INTx isn't disabled, 1415 * as these chips need it even when using MSI. 1416 */ 1417 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1418 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4); 1419 1420 /* Set the timer prescaler (always 66Mhz) */ 1421 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1422 1423 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1424 DELAY(40); /* XXX */ 1425 1426 /* Put PHY into ready state */ 1427 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1428 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1429 DELAY(40); 1430 } 1431 1432 return(0); 1433 } 1434 1435 static int 1436 bge_blockinit(struct bge_softc *sc) 1437 { 1438 struct bge_rcb *rcb; 1439 bus_size_t vrcb; 1440 bge_hostaddr taddr; 1441 uint32_t val; 1442 int i, limit; 1443 1444 /* 1445 * Initialize the memory window pointer register so that 1446 * we can access the first 32K of internal NIC RAM. This will 1447 * allow us to set up the TX send ring RCBs and the RX return 1448 * ring RCBs, plus other things which live in NIC memory. 1449 */ 1450 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1451 1452 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1453 1454 if (!BGE_IS_5705_PLUS(sc)) { 1455 /* Configure mbuf memory pool */ 1456 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1457 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1458 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1459 else 1460 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1461 1462 /* Configure DMA resource pool */ 1463 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1464 BGE_DMA_DESCRIPTORS); 1465 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1466 } 1467 1468 /* Configure mbuf pool watermarks */ 1469 if (!BGE_IS_5705_PLUS(sc)) { 1470 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1471 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1472 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1473 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1474 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1475 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1476 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1477 } else { 1478 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1479 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1480 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1481 } 1482 1483 /* Configure DMA resource watermarks */ 1484 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1485 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1486 1487 /* Enable buffer manager */ 1488 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1489 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1490 1491 /* Poll for buffer manager start indication */ 1492 for (i = 0; i < BGE_TIMEOUT; i++) { 1493 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1494 break; 1495 DELAY(10); 1496 } 1497 1498 if (i == BGE_TIMEOUT) { 1499 if_printf(&sc->arpcom.ac_if, 1500 "buffer manager failed to start\n"); 1501 return(ENXIO); 1502 } 1503 1504 /* Enable flow-through queues */ 1505 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1506 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1507 1508 /* Wait until queue initialization is complete */ 1509 for (i = 0; i < BGE_TIMEOUT; i++) { 1510 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1511 break; 1512 DELAY(10); 1513 } 1514 1515 if (i == BGE_TIMEOUT) { 1516 if_printf(&sc->arpcom.ac_if, 1517 "flow-through queue init failed\n"); 1518 return(ENXIO); 1519 } 1520 1521 /* 1522 * Summary of rings supported by the controller: 1523 * 1524 * Standard Receive Producer Ring 1525 * - This ring is used to feed receive buffers for "standard" 1526 * sized frames (typically 1536 bytes) to the controller. 1527 * 1528 * Jumbo Receive Producer Ring 1529 * - This ring is used to feed receive buffers for jumbo sized 1530 * frames (i.e. anything bigger than the "standard" frames) 1531 * to the controller. 1532 * 1533 * Mini Receive Producer Ring 1534 * - This ring is used to feed receive buffers for "mini" 1535 * sized frames to the controller. 1536 * - This feature required external memory for the controller 1537 * but was never used in a production system. Should always 1538 * be disabled. 1539 * 1540 * Receive Return Ring 1541 * - After the controller has placed an incoming frame into a 1542 * receive buffer that buffer is moved into a receive return 1543 * ring. The driver is then responsible to passing the 1544 * buffer up to the stack. Many versions of the controller 1545 * support multiple RR rings. 1546 * 1547 * Send Ring 1548 * - This ring is used for outgoing frames. Many versions of 1549 * the controller support multiple send rings. 1550 */ 1551 1552 /* Initialize the standard receive producer ring control block. */ 1553 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1554 rcb->bge_hostaddr.bge_addr_lo = 1555 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1556 rcb->bge_hostaddr.bge_addr_hi = 1557 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1558 if (BGE_IS_5705_PLUS(sc)) { 1559 /* 1560 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1561 * Bits 15-2 : Reserved (should be 0) 1562 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1563 * Bit 0 : Reserved 1564 */ 1565 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1566 } else { 1567 /* 1568 * Ring size is always XXX entries 1569 * Bits 31-16: Maximum RX frame size 1570 * Bits 15-2 : Reserved (should be 0) 1571 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1572 * Bit 0 : Reserved 1573 */ 1574 rcb->bge_maxlen_flags = 1575 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1576 } 1577 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1578 /* Write the standard receive producer ring control block. */ 1579 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1580 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1581 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1582 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1583 /* Reset the standard receive producer ring producer index. */ 1584 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1585 1586 /* 1587 * Initialize the jumbo RX producer ring control 1588 * block. We set the 'ring disabled' bit in the 1589 * flags field until we're actually ready to start 1590 * using this ring (i.e. once we set the MTU 1591 * high enough to require it). 1592 */ 1593 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1594 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1595 /* Get the jumbo receive producer ring RCB parameters. */ 1596 rcb->bge_hostaddr.bge_addr_lo = 1597 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1598 rcb->bge_hostaddr.bge_addr_hi = 1599 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1600 rcb->bge_maxlen_flags = 1601 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1602 BGE_RCB_FLAG_RING_DISABLED); 1603 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1604 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1605 rcb->bge_hostaddr.bge_addr_hi); 1606 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1607 rcb->bge_hostaddr.bge_addr_lo); 1608 /* Program the jumbo receive producer ring RCB parameters. */ 1609 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1610 rcb->bge_maxlen_flags); 1611 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1612 /* Reset the jumbo receive producer ring producer index. */ 1613 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1614 } 1615 1616 /* Disable the mini receive producer ring RCB. */ 1617 if (BGE_IS_5700_FAMILY(sc)) { 1618 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1619 rcb->bge_maxlen_flags = 1620 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1621 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1622 rcb->bge_maxlen_flags); 1623 /* Reset the mini receive producer ring producer index. */ 1624 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1625 } 1626 1627 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1628 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1629 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1630 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1631 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) { 1632 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1633 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1634 } 1635 1636 /* 1637 * The BD ring replenish thresholds control how often the 1638 * hardware fetches new BD's from the producer rings in host 1639 * memory. Setting the value too low on a busy system can 1640 * starve the hardware and recue the throughpout. 1641 * 1642 * Set the BD ring replentish thresholds. The recommended 1643 * values are 1/8th the number of descriptors allocated to 1644 * each ring. 1645 */ 1646 if (BGE_IS_5705_PLUS(sc)) 1647 val = 8; 1648 else 1649 val = BGE_STD_RX_RING_CNT / 8; 1650 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1651 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1652 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1653 BGE_JUMBO_RX_RING_CNT/8); 1654 } 1655 1656 /* 1657 * Disable all send rings by setting the 'ring disabled' bit 1658 * in the flags field of all the TX send ring control blocks, 1659 * located in NIC memory. 1660 */ 1661 if (!BGE_IS_5705_PLUS(sc)) { 1662 /* 5700 to 5704 had 16 send rings. */ 1663 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1664 } else { 1665 limit = 1; 1666 } 1667 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1668 for (i = 0; i < limit; i++) { 1669 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1670 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1671 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1672 vrcb += sizeof(struct bge_rcb); 1673 } 1674 1675 /* Configure send ring RCB 0 (we use only the first ring) */ 1676 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1677 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1678 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1679 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1680 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1681 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1682 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1683 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1684 1685 /* 1686 * Disable all receive return rings by setting the 1687 * 'ring diabled' bit in the flags field of all the receive 1688 * return ring control blocks, located in NIC memory. 1689 */ 1690 if (!BGE_IS_5705_PLUS(sc)) 1691 limit = BGE_RX_RINGS_MAX; 1692 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755) 1693 limit = 4; 1694 else 1695 limit = 1; 1696 /* Disable all receive return rings. */ 1697 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1698 for (i = 0; i < limit; i++) { 1699 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1700 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1701 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1702 BGE_RCB_FLAG_RING_DISABLED); 1703 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1704 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1705 (i * (sizeof(uint64_t))), 0); 1706 vrcb += sizeof(struct bge_rcb); 1707 } 1708 1709 /* 1710 * Set up receive return ring 0. Note that the NIC address 1711 * for RX return rings is 0x0. The return rings live entirely 1712 * within the host, so the nicaddr field in the RCB isn't used. 1713 */ 1714 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1715 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1716 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1717 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1718 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1719 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1720 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1721 1722 /* Set random backoff seed for TX */ 1723 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1724 (sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1725 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1726 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 1727 BGE_TX_BACKOFF_SEED_MASK); 1728 1729 /* Set inter-packet gap */ 1730 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1731 1732 /* 1733 * Specify which ring to use for packets that don't match 1734 * any RX rules. 1735 */ 1736 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1737 1738 /* 1739 * Configure number of RX lists. One interrupt distribution 1740 * list, sixteen active lists, one bad frames class. 1741 */ 1742 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1743 1744 /* Inialize RX list placement stats mask. */ 1745 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1746 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1747 1748 /* Disable host coalescing until we get it set up */ 1749 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1750 1751 /* Poll to make sure it's shut down. */ 1752 for (i = 0; i < BGE_TIMEOUT; i++) { 1753 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1754 break; 1755 DELAY(10); 1756 } 1757 1758 if (i == BGE_TIMEOUT) { 1759 if_printf(&sc->arpcom.ac_if, 1760 "host coalescing engine failed to idle\n"); 1761 return(ENXIO); 1762 } 1763 1764 /* Set up host coalescing defaults */ 1765 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1766 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1767 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds); 1768 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds); 1769 if (!BGE_IS_5705_PLUS(sc)) { 1770 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 1771 sc->bge_rx_coal_ticks_int); 1772 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 1773 sc->bge_tx_coal_ticks_int); 1774 } 1775 /* 1776 * NOTE: 1777 * The datasheet (57XX-PG105-R) says BCM5705+ do not 1778 * have following two registers; obviously it is wrong. 1779 */ 1780 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int); 1781 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int); 1782 1783 /* Set up address of statistics block */ 1784 if (!BGE_IS_5705_PLUS(sc)) { 1785 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1786 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1787 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1788 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1789 1790 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1791 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1792 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1793 } 1794 1795 /* Set up address of status block */ 1796 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1797 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1798 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1799 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1800 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1801 1802 /* 1803 * Set up status block partail update size. 1804 * 1805 * Because only single TX ring, RX produce ring and Rx return ring 1806 * are used, ask device to update only minimum part of status block 1807 * except for BCM5700 AX/BX, whose status block partial update size 1808 * can't be configured. 1809 */ 1810 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1811 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1812 /* XXX Actually reserved on BCM5700 AX/BX */ 1813 val = BGE_STATBLKSZ_FULL; 1814 } else { 1815 val = BGE_STATBLKSZ_32BYTE; 1816 } 1817 #if 0 1818 /* 1819 * Does not seem to have visible effect in both 1820 * bulk data (1472B UDP datagram) and tiny data 1821 * (18B UDP datagram) TX tests. 1822 */ 1823 if (!BGE_IS_CRIPPLED(sc)) 1824 val |= BGE_HCCMODE_CLRTICK_TX; 1825 #endif 1826 1827 /* Turn on host coalescing state machine */ 1828 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1829 1830 /* Turn on RX BD completion state machine and enable attentions */ 1831 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1832 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1833 1834 /* Turn on RX list placement state machine */ 1835 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1836 1837 /* Turn on RX list selector state machine. */ 1838 if (!BGE_IS_5705_PLUS(sc)) 1839 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1840 1841 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1842 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1843 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1844 BGE_MACMODE_FRMHDR_DMA_ENB; 1845 1846 if (sc->bge_flags & BGE_FLAG_TBI) 1847 val |= BGE_PORTMODE_TBI; 1848 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1849 val |= BGE_PORTMODE_GMII; 1850 else 1851 val |= BGE_PORTMODE_MII; 1852 1853 /* Allow APE to send/receive frames. */ 1854 if (sc->bge_mfw_flags & BGE_MFW_ON_APE) 1855 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 1856 1857 /* Turn on DMA, clear stats */ 1858 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1859 DELAY(40); 1860 1861 /* Set misc. local control, enable interrupts on attentions */ 1862 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1863 1864 #ifdef notdef 1865 /* Assert GPIO pins for PHY reset */ 1866 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1867 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1868 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1869 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1870 #endif 1871 1872 /* Turn on DMA completion state machine */ 1873 if (!BGE_IS_5705_PLUS(sc)) 1874 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1875 1876 /* Turn on write DMA state machine */ 1877 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1878 if (BGE_IS_5755_PLUS(sc)) { 1879 /* Enable host coalescing bug fix. */ 1880 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1881 } 1882 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) { 1883 /* Request larger DMA burst size to get better performance. */ 1884 val |= BGE_WDMAMODE_BURST_ALL_DATA; 1885 } 1886 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1887 DELAY(40); 1888 1889 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 1890 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1891 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1892 sc->bge_asicrev == BGE_ASICREV_BCM57780) { 1893 /* 1894 * Enable fix for read DMA FIFO overruns. 1895 * The fix is to limit the number of RX BDs 1896 * the hardware would fetch at a fime. 1897 */ 1898 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 1899 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, 1900 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 1901 } 1902 1903 /* Turn on read DMA state machine */ 1904 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1905 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1906 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1907 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1908 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1909 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1910 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1911 if (sc->bge_flags & BGE_FLAG_PCIE) 1912 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1913 if (sc->bge_flags & BGE_FLAG_TSO) 1914 val |= BGE_RDMAMODE_TSO4_ENABLE; 1915 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1916 DELAY(40); 1917 1918 /* Turn on RX data completion state machine */ 1919 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1920 1921 /* Turn on RX BD initiator state machine */ 1922 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1923 1924 /* Turn on RX data and RX BD initiator state machine */ 1925 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1926 1927 /* Turn on Mbuf cluster free state machine */ 1928 if (!BGE_IS_5705_PLUS(sc)) 1929 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1930 1931 /* Turn on send BD completion state machine */ 1932 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1933 1934 /* Turn on send data completion state machine */ 1935 val = BGE_SDCMODE_ENABLE; 1936 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1937 val |= BGE_SDCMODE_CDELAY; 1938 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1939 1940 /* Turn on send data initiator state machine */ 1941 if (sc->bge_flags & BGE_FLAG_TSO) 1942 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 1943 BGE_SDIMODE_HW_LSO_PRE_DMA); 1944 else 1945 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1946 1947 /* Turn on send BD initiator state machine */ 1948 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1949 1950 /* Turn on send BD selector state machine */ 1951 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1952 1953 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1954 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1955 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1956 1957 /* ack/clear link change events */ 1958 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1959 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1960 BGE_MACSTAT_LINK_CHANGED); 1961 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1962 1963 /* 1964 * Enable attention when the link has changed state for 1965 * devices that use auto polling. 1966 */ 1967 if (sc->bge_flags & BGE_FLAG_TBI) { 1968 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1969 } else { 1970 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 1971 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1972 DELAY(80); 1973 } 1974 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1975 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 1976 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1977 BGE_EVTENB_MI_INTERRUPT); 1978 } 1979 } 1980 1981 /* 1982 * Clear any pending link state attention. 1983 * Otherwise some link state change events may be lost until attention 1984 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence. 1985 * It's not necessary on newer BCM chips - perhaps enabling link 1986 * state change attentions implies clearing pending attention. 1987 */ 1988 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1989 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1990 BGE_MACSTAT_LINK_CHANGED); 1991 1992 /* Enable link state change attentions. */ 1993 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1994 1995 return(0); 1996 } 1997 1998 /* 1999 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2000 * against our list and return its name if we find a match. Note 2001 * that since the Broadcom controller contains VPD support, we 2002 * can get the device name string from the controller itself instead 2003 * of the compiled-in string. This is a little slow, but it guarantees 2004 * we'll always announce the right product name. 2005 */ 2006 static int 2007 bge_probe(device_t dev) 2008 { 2009 const struct bge_type *t; 2010 uint16_t product, vendor; 2011 2012 product = pci_get_device(dev); 2013 vendor = pci_get_vendor(dev); 2014 2015 for (t = bge_devs; t->bge_name != NULL; t++) { 2016 if (vendor == t->bge_vid && product == t->bge_did) 2017 break; 2018 } 2019 if (t->bge_name == NULL) 2020 return(ENXIO); 2021 2022 device_set_desc(dev, t->bge_name); 2023 return(0); 2024 } 2025 2026 static int 2027 bge_attach(device_t dev) 2028 { 2029 struct ifnet *ifp; 2030 struct bge_softc *sc; 2031 struct sysctl_ctx_list *ctx; 2032 struct sysctl_oid *tree; 2033 uint32_t hwcfg = 0, misccfg; 2034 int error = 0, rid, capmask; 2035 uint8_t ether_addr[ETHER_ADDR_LEN]; 2036 uint16_t product, vendor; 2037 driver_intr_t *intr_func; 2038 uintptr_t mii_priv = 0; 2039 u_int intr_flags; 2040 int msi_enable; 2041 2042 sc = device_get_softc(dev); 2043 sc->bge_dev = dev; 2044 callout_init_mp(&sc->bge_stat_timer); 2045 lwkt_serialize_init(&sc->bge_jslot_serializer); 2046 2047 sc->bge_func_addr = pci_get_function(dev); 2048 product = pci_get_device(dev); 2049 vendor = pci_get_vendor(dev); 2050 2051 #ifndef BURN_BRIDGES 2052 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2053 uint32_t irq, mem; 2054 2055 irq = pci_read_config(dev, PCIR_INTLINE, 4); 2056 mem = pci_read_config(dev, BGE_PCI_BAR0, 4); 2057 2058 device_printf(dev, "chip is in D%d power mode " 2059 "-- setting to D0\n", pci_get_powerstate(dev)); 2060 2061 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2062 2063 pci_write_config(dev, PCIR_INTLINE, irq, 4); 2064 pci_write_config(dev, BGE_PCI_BAR0, mem, 4); 2065 } 2066 #endif /* !BURN_BRIDGE */ 2067 2068 /* 2069 * Map control/status registers. 2070 */ 2071 pci_enable_busmaster(dev); 2072 2073 rid = BGE_PCI_BAR0; 2074 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2075 RF_ACTIVE); 2076 2077 if (sc->bge_res == NULL) { 2078 device_printf(dev, "couldn't map memory\n"); 2079 return ENXIO; 2080 } 2081 2082 sc->bge_btag = rman_get_bustag(sc->bge_res); 2083 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2084 2085 /* Save various chip information */ 2086 sc->bge_chipid = 2087 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2088 BGE_PCIMISCCTL_ASICREV_SHIFT; 2089 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2090 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */ 2091 sc->bge_flags |= BGE_FLAG_CPMU; 2092 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2093 } 2094 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2095 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2096 2097 /* Save chipset family. */ 2098 switch (sc->bge_asicrev) { 2099 case BGE_ASICREV_BCM5755: 2100 case BGE_ASICREV_BCM5761: 2101 case BGE_ASICREV_BCM5784: 2102 case BGE_ASICREV_BCM5785: 2103 case BGE_ASICREV_BCM5787: 2104 case BGE_ASICREV_BCM57780: 2105 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2106 BGE_FLAG_5705_PLUS; 2107 break; 2108 2109 case BGE_ASICREV_BCM5700: 2110 case BGE_ASICREV_BCM5701: 2111 case BGE_ASICREV_BCM5703: 2112 case BGE_ASICREV_BCM5704: 2113 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2114 break; 2115 2116 case BGE_ASICREV_BCM5714_A0: 2117 case BGE_ASICREV_BCM5780: 2118 case BGE_ASICREV_BCM5714: 2119 sc->bge_flags |= BGE_FLAG_5714_FAMILY; 2120 /* Fall through */ 2121 2122 case BGE_ASICREV_BCM5750: 2123 case BGE_ASICREV_BCM5752: 2124 case BGE_ASICREV_BCM5906: 2125 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2126 /* Fall through */ 2127 2128 case BGE_ASICREV_BCM5705: 2129 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2130 break; 2131 } 2132 2133 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2134 sc->bge_flags |= BGE_FLAG_NO_EEPROM; 2135 2136 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2137 sc->bge_flags |= BGE_FLAG_APE; 2138 2139 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 2140 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2141 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2142 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2143 sc->bge_flags |= BGE_FLAG_5788; 2144 2145 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 2146 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 2147 sc->bge_flags |= BGE_FLAG_SHORTDMA; 2148 2149 /* 2150 * Increase STD RX ring prod index by at most 8 for BCM5750, 2151 * BCM5752 and BCM5755 to workaround hardware errata. 2152 */ 2153 if (sc->bge_asicrev == BGE_ASICREV_BCM5750 || 2154 sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2155 sc->bge_asicrev == BGE_ASICREV_BCM5755) 2156 sc->bge_rx_wreg = 8; 2157 2158 /* 2159 * Check if this is a PCI-X or PCI Express device. 2160 */ 2161 if (BGE_IS_5705_PLUS(sc)) { 2162 if (pci_is_pcie(dev)) { 2163 sc->bge_flags |= BGE_FLAG_PCIE; 2164 sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev); 2165 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096); 2166 } 2167 } else { 2168 /* 2169 * Check if the device is in PCI-X Mode. 2170 * (This bit is not valid on PCI Express controllers.) 2171 */ 2172 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2173 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2174 sc->bge_flags |= BGE_FLAG_PCIX; 2175 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev); 2176 sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev, 2177 "mbox_reorder", 0); 2178 } 2179 } 2180 device_printf(dev, "CHIP ID 0x%08x; " 2181 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2182 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2183 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" 2184 : ((sc->bge_flags & BGE_FLAG_PCIE) ? 2185 "PCI-E" : "PCI")); 2186 2187 /* 2188 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2189 * not actually a MAC controller bug but an issue with the embedded 2190 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2191 */ 2192 if ((sc->bge_flags & BGE_FLAG_PCIX) && 2193 (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0))) 2194 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT; 2195 2196 /* 2197 * When using the BCM5701 in PCI-X mode, data corruption has 2198 * been observed in the first few bytes of some received packets. 2199 * Aligning the packet buffer in memory eliminates the corruption. 2200 * Unfortunately, this misaligns the packet payloads. On platforms 2201 * which do not support unaligned accesses, we will realign the 2202 * payloads by copying the received packets. 2203 */ 2204 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2205 (sc->bge_flags & BGE_FLAG_PCIX)) 2206 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2207 2208 if (!BGE_IS_CRIPPLED(sc)) { 2209 if (device_getenv_int(dev, "status_tag", 1)) { 2210 sc->bge_flags |= BGE_FLAG_STATUS_TAG; 2211 sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS; 2212 if (bootverbose) 2213 device_printf(dev, "enable status tag\n"); 2214 } 2215 } 2216 2217 if (BGE_IS_5755_PLUS(sc)) { 2218 /* 2219 * BCM5754 and BCM5787 shares the same ASIC id so 2220 * explicit device id check is required. 2221 * Due to unknown reason TSO does not work on BCM5755M. 2222 */ 2223 if (product != PCI_PRODUCT_BROADCOM_BCM5754 && 2224 product != PCI_PRODUCT_BROADCOM_BCM5754M && 2225 product != PCI_PRODUCT_BROADCOM_BCM5755M) 2226 sc->bge_flags |= BGE_FLAG_TSO; 2227 } 2228 2229 /* 2230 * Set various PHY quirk flags. 2231 */ 2232 2233 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2234 sc->bge_asicrev == BGE_ASICREV_BCM5701) && 2235 pci_get_subvendor(dev) == PCI_VENDOR_DELL) 2236 mii_priv |= BRGPHY_FLAG_NO_3LED; 2237 2238 capmask = MII_CAPMASK_DEFAULT; 2239 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 2240 (misccfg == 0x4000 || misccfg == 0x8000)) || 2241 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2242 vendor == PCI_VENDOR_BROADCOM && 2243 (product == PCI_PRODUCT_BROADCOM_BCM5901 || 2244 product == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2245 product == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2246 (vendor == PCI_VENDOR_BROADCOM && 2247 (product == PCI_PRODUCT_BROADCOM_BCM5751F || 2248 product == PCI_PRODUCT_BROADCOM_BCM5753F || 2249 product == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2250 product == PCI_PRODUCT_BROADCOM_BCM57790 || 2251 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2252 /* 10/100 only */ 2253 capmask &= ~BMSR_EXTSTAT; 2254 } 2255 2256 mii_priv |= BRGPHY_FLAG_WIRESPEED; 2257 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2258 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2259 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2260 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2261 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2262 mii_priv &= ~BRGPHY_FLAG_WIRESPEED; 2263 2264 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2265 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2266 mii_priv |= BRGPHY_FLAG_CRC_BUG; 2267 2268 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2269 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2270 mii_priv |= BRGPHY_FLAG_ADC_BUG; 2271 2272 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2273 mii_priv |= BRGPHY_FLAG_5704_A0; 2274 2275 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2276 mii_priv |= BRGPHY_FLAG_5906; 2277 2278 if (BGE_IS_5705_PLUS(sc) && 2279 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2280 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */ 2281 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2282 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */ 2283 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 2284 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2285 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2286 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2287 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2288 if (product != PCI_PRODUCT_BROADCOM_BCM5722 && 2289 product != PCI_PRODUCT_BROADCOM_BCM5756) 2290 mii_priv |= BRGPHY_FLAG_JITTER_BUG; 2291 if (product == PCI_PRODUCT_BROADCOM_BCM5755M) 2292 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM; 2293 } else { 2294 mii_priv |= BRGPHY_FLAG_BER_BUG; 2295 } 2296 } 2297 2298 /* 2299 * Chips with APE need BAR2 access for APE registers/memory. 2300 */ 2301 if (sc->bge_flags & BGE_FLAG_APE) { 2302 uint32_t pcistate; 2303 2304 rid = PCIR_BAR(2); 2305 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2306 RF_ACTIVE); 2307 if (sc->bge_res2 == NULL) { 2308 device_printf(dev, "couldn't map BAR2 memory\n"); 2309 error = ENXIO; 2310 goto fail; 2311 } 2312 2313 /* Enable APE register/memory access by host driver. */ 2314 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2315 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 2316 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 2317 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 2318 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 2319 2320 bge_ape_lock_init(sc); 2321 bge_ape_read_fw_ver(sc); 2322 } 2323 2324 /* 2325 * Allocate interrupt 2326 */ 2327 msi_enable = bge_msi_enable; 2328 if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) { 2329 /* If "tagged status" is disabled, don't enable MSI */ 2330 msi_enable = 0; 2331 } else if (msi_enable) { 2332 msi_enable = 0; /* Disable by default */ 2333 if (BGE_IS_575X_PLUS(sc)) { 2334 msi_enable = 1; 2335 /* XXX we filter all 5714 chips */ 2336 if (sc->bge_asicrev == BGE_ASICREV_BCM5714 || 2337 (sc->bge_asicrev == BGE_ASICREV_BCM5750 && 2338 (sc->bge_chiprev == BGE_CHIPREV_5750_AX || 2339 sc->bge_chiprev == BGE_CHIPREV_5750_BX))) 2340 msi_enable = 0; 2341 else if (BGE_IS_5755_PLUS(sc) || 2342 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2343 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI; 2344 } 2345 } 2346 if (msi_enable) { 2347 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) { 2348 device_printf(dev, "no MSI capability\n"); 2349 msi_enable = 0; 2350 } 2351 } 2352 2353 sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid, 2354 &intr_flags); 2355 2356 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid, 2357 intr_flags); 2358 if (sc->bge_irq == NULL) { 2359 device_printf(dev, "couldn't map interrupt\n"); 2360 error = ENXIO; 2361 goto fail; 2362 } 2363 2364 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) 2365 bge_enable_msi(sc); 2366 else 2367 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI; 2368 2369 /* Initialize if_name earlier, so if_printf could be used */ 2370 ifp = &sc->arpcom.ac_if; 2371 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2372 2373 sc->bge_asf_mode = 0; 2374 /* No ASF if APE present. */ 2375 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 2376 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 2377 BGE_SRAM_DATA_SIG_MAGIC)) { 2378 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 2379 BGE_HWCFG_ASF) { 2380 sc->bge_asf_mode |= ASF_ENABLE; 2381 sc->bge_asf_mode |= ASF_STACKUP; 2382 if (BGE_IS_575X_PLUS(sc)) 2383 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2384 } 2385 } 2386 } 2387 2388 /* 2389 * Try to reset the chip. 2390 */ 2391 bge_stop_fw(sc); 2392 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 2393 bge_reset(sc); 2394 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 2395 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 2396 2397 if (bge_chipinit(sc)) { 2398 device_printf(dev, "chip initialization failed\n"); 2399 error = ENXIO; 2400 goto fail; 2401 } 2402 2403 /* 2404 * Get station address 2405 */ 2406 error = bge_get_eaddr(sc, ether_addr); 2407 if (error) { 2408 device_printf(dev, "failed to read station address\n"); 2409 goto fail; 2410 } 2411 2412 /* 5705/5750 limits RX return ring to 512 entries. */ 2413 if (BGE_IS_5705_PLUS(sc)) 2414 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2415 else 2416 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2417 2418 error = bge_dma_alloc(sc); 2419 if (error) 2420 goto fail; 2421 2422 /* Set default tuneable values. */ 2423 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2424 sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF; 2425 sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF; 2426 sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF; 2427 sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF; 2428 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2429 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF; 2430 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF; 2431 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF; 2432 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF; 2433 } else { 2434 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN; 2435 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN; 2436 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN; 2437 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN; 2438 } 2439 sc->bge_tx_wreg = BGE_TX_WREG_NSEGS; 2440 2441 /* Set up TX spare and reserved descriptor count */ 2442 if (sc->bge_flags & BGE_FLAG_TSO) { 2443 sc->bge_txspare = BGE_NSEG_SPARE_TSO; 2444 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO; 2445 } else { 2446 sc->bge_txspare = BGE_NSEG_SPARE; 2447 sc->bge_txrsvd = BGE_NSEG_RSVD; 2448 } 2449 2450 /* Set up ifnet structure */ 2451 ifp->if_softc = sc; 2452 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2453 ifp->if_ioctl = bge_ioctl; 2454 ifp->if_start = bge_start; 2455 #ifdef IFPOLL_ENABLE 2456 ifp->if_npoll = bge_npoll; 2457 #endif 2458 ifp->if_watchdog = bge_watchdog; 2459 ifp->if_init = bge_init; 2460 ifp->if_mtu = ETHERMTU; 2461 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2462 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 2463 ifq_set_ready(&ifp->if_snd); 2464 2465 /* 2466 * 5700 B0 chips do not support checksumming correctly due 2467 * to hardware bugs. 2468 */ 2469 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) { 2470 ifp->if_capabilities |= IFCAP_HWCSUM; 2471 ifp->if_hwassist |= BGE_CSUM_FEATURES; 2472 } 2473 if (sc->bge_flags & BGE_FLAG_TSO) { 2474 ifp->if_capabilities |= IFCAP_TSO; 2475 ifp->if_hwassist |= CSUM_TSO; 2476 } 2477 ifp->if_capenable = ifp->if_capabilities; 2478 2479 /* 2480 * Figure out what sort of media we have by checking the 2481 * hardware config word in the first 32k of NIC internal memory, 2482 * or fall back to examining the EEPROM if necessary. 2483 * Note: on some BCM5700 cards, this value appears to be unset. 2484 * If that's the case, we have to rely on identifying the NIC 2485 * by its PCI subsystem ID, as we do below for the SysKonnect 2486 * SK-9D41. 2487 */ 2488 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 2489 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 2490 } else { 2491 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2492 sizeof(hwcfg))) { 2493 device_printf(dev, "failed to read EEPROM\n"); 2494 error = ENXIO; 2495 goto fail; 2496 } 2497 hwcfg = ntohl(hwcfg); 2498 } 2499 2500 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2501 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 || 2502 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2503 if (BGE_IS_5714_FAMILY(sc)) 2504 sc->bge_flags |= BGE_FLAG_MII_SERDES; 2505 else 2506 sc->bge_flags |= BGE_FLAG_TBI; 2507 } 2508 2509 /* Setup MI MODE */ 2510 if (sc->bge_flags & BGE_FLAG_CPMU) 2511 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 2512 else 2513 sc->bge_mi_mode = BGE_MIMODE_BASE; 2514 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) { 2515 /* Enable auto polling for BCM570[0-5]. */ 2516 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 2517 } 2518 2519 /* Setup link status update stuffs */ 2520 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2521 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 2522 sc->bge_link_upd = bge_bcm5700_link_upd; 2523 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT; 2524 } else if (sc->bge_flags & BGE_FLAG_TBI) { 2525 sc->bge_link_upd = bge_tbi_link_upd; 2526 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2527 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2528 sc->bge_link_upd = bge_autopoll_link_upd; 2529 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2530 } else { 2531 sc->bge_link_upd = bge_copper_link_upd; 2532 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2533 } 2534 2535 /* 2536 * Broadcom's own driver always assumes the internal 2537 * PHY is at GMII address 1. On some chips, the PHY responds 2538 * to accesses at all addresses, which could cause us to 2539 * bogusly attach the PHY 32 times at probe type. Always 2540 * restricting the lookup to address 1 is simpler than 2541 * trying to figure out which chips revisions should be 2542 * special-cased. 2543 */ 2544 sc->bge_phyno = 1; 2545 2546 if (sc->bge_flags & BGE_FLAG_TBI) { 2547 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2548 bge_ifmedia_upd, bge_ifmedia_sts); 2549 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2550 ifmedia_add(&sc->bge_ifmedia, 2551 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2552 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2553 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2554 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2555 } else { 2556 struct mii_probe_args mii_args; 2557 int tries; 2558 2559 /* 2560 * Do transceiver setup and tell the firmware the 2561 * driver is down so we can try to get access the 2562 * probe if ASF is running. Retry a couple of times 2563 * if we get a conflict with the ASF firmware accessing 2564 * the PHY. 2565 */ 2566 tries = 0; 2567 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2568 again: 2569 bge_asf_driver_up(sc); 2570 2571 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts); 2572 mii_args.mii_probemask = 1 << sc->bge_phyno; 2573 mii_args.mii_capmask = capmask; 2574 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY; 2575 mii_args.mii_priv = mii_priv; 2576 2577 error = mii_probe(dev, &sc->bge_miibus, &mii_args); 2578 if (error) { 2579 if (tries++ < 4) { 2580 device_printf(sc->bge_dev, "Probe MII again\n"); 2581 bge_miibus_writereg(sc->bge_dev, 2582 sc->bge_phyno, MII_BMCR, BMCR_RESET); 2583 goto again; 2584 } 2585 device_printf(dev, "MII without any PHY!\n"); 2586 goto fail; 2587 } 2588 2589 /* 2590 * Now tell the firmware we are going up after probing the PHY 2591 */ 2592 if (sc->bge_asf_mode & ASF_STACKUP) 2593 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2594 } 2595 2596 ctx = device_get_sysctl_ctx(sc->bge_dev); 2597 tree = device_get_sysctl_tree(sc->bge_dev); 2598 2599 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "rx_coal_ticks", 2600 CTLTYPE_INT | CTLFLAG_RW, 2601 sc, 0, bge_sysctl_rx_coal_ticks, "I", 2602 "Receive coalescing ticks (usec)."); 2603 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_coal_ticks", 2604 CTLTYPE_INT | CTLFLAG_RW, 2605 sc, 0, bge_sysctl_tx_coal_ticks, "I", 2606 "Transmit coalescing ticks (usec)."); 2607 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "rx_coal_bds", 2608 CTLTYPE_INT | CTLFLAG_RW, 2609 sc, 0, bge_sysctl_rx_coal_bds, "I", 2610 "Receive max coalesced BD count."); 2611 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_coal_bds", 2612 CTLTYPE_INT | CTLFLAG_RW, 2613 sc, 0, bge_sysctl_tx_coal_bds, "I", 2614 "Transmit max coalesced BD count."); 2615 2616 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_wreg", CTLFLAG_RW, 2617 &sc->bge_tx_wreg, 0, 2618 "# of segments before writing to hardware register"); 2619 2620 if (sc->bge_flags & BGE_FLAG_PCIE) { 2621 /* 2622 * A common design characteristic for many Broadcom 2623 * client controllers is that they only support a 2624 * single outstanding DMA read operation on the PCIe 2625 * bus. This means that it will take twice as long to 2626 * fetch a TX frame that is split into header and 2627 * payload buffers as it does to fetch a single, 2628 * contiguous TX frame (2 reads vs. 1 read). For these 2629 * controllers, coalescing buffers to reduce the number 2630 * of memory reads is effective way to get maximum 2631 * performance(about 940Mbps). Without collapsing TX 2632 * buffers the maximum TCP bulk transfer performance 2633 * is about 850Mbps. However forcing coalescing mbufs 2634 * consumes a lot of CPU cycles, so leave it off by 2635 * default. 2636 */ 2637 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2638 "force_defrag", CTLFLAG_RW, 2639 &sc->bge_force_defrag, 0, 2640 "Force defragment on TX path"); 2641 } 2642 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2643 if (!BGE_IS_5705_PLUS(sc)) { 2644 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2645 "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW, 2646 sc, 0, bge_sysctl_rx_coal_ticks_int, "I", 2647 "Receive coalescing ticks " 2648 "during interrupt (usec)."); 2649 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2650 "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW, 2651 sc, 0, bge_sysctl_tx_coal_ticks_int, "I", 2652 "Transmit coalescing ticks " 2653 "during interrupt (usec)."); 2654 } 2655 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2656 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2657 sc, 0, bge_sysctl_rx_coal_bds_int, "I", 2658 "Receive max coalesced BD count during interrupt."); 2659 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2660 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2661 sc, 0, bge_sysctl_tx_coal_bds_int, "I", 2662 "Transmit max coalesced BD count during interrupt."); 2663 } 2664 2665 /* 2666 * Call MI attach routine. 2667 */ 2668 ether_ifattach(ifp, ether_addr, NULL); 2669 2670 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq)); 2671 2672 #ifdef IFPOLL_ENABLE 2673 /* Polling setup */ 2674 ifpoll_compat_setup(&sc->bge_npoll, ctx, tree, 2675 device_get_unit(dev), ifp->if_serializer); 2676 #endif 2677 2678 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 2679 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 2680 intr_func = bge_msi_oneshot; 2681 if (bootverbose) 2682 device_printf(dev, "oneshot MSI\n"); 2683 } else { 2684 intr_func = bge_msi; 2685 } 2686 } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2687 intr_func = bge_intr_legacy; 2688 } else { 2689 intr_func = bge_intr_crippled; 2690 } 2691 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc, 2692 &sc->bge_intrhand, ifp->if_serializer); 2693 if (error) { 2694 ether_ifdetach(ifp); 2695 device_printf(dev, "couldn't set up irq\n"); 2696 goto fail; 2697 } 2698 2699 return(0); 2700 fail: 2701 bge_detach(dev); 2702 return(error); 2703 } 2704 2705 static int 2706 bge_detach(device_t dev) 2707 { 2708 struct bge_softc *sc = device_get_softc(dev); 2709 2710 if (device_is_attached(dev)) { 2711 struct ifnet *ifp = &sc->arpcom.ac_if; 2712 2713 lwkt_serialize_enter(ifp->if_serializer); 2714 bge_stop(sc); 2715 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2716 lwkt_serialize_exit(ifp->if_serializer); 2717 2718 ether_ifdetach(ifp); 2719 } 2720 2721 if (sc->bge_flags & BGE_FLAG_TBI) 2722 ifmedia_removeall(&sc->bge_ifmedia); 2723 if (sc->bge_miibus) 2724 device_delete_child(dev, sc->bge_miibus); 2725 bus_generic_detach(dev); 2726 2727 if (sc->bge_irq != NULL) { 2728 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid, 2729 sc->bge_irq); 2730 } 2731 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) 2732 pci_release_msi(dev); 2733 2734 if (sc->bge_res != NULL) { 2735 bus_release_resource(dev, SYS_RES_MEMORY, 2736 BGE_PCI_BAR0, sc->bge_res); 2737 } 2738 if (sc->bge_res2 != NULL) { 2739 bus_release_resource(dev, SYS_RES_MEMORY, 2740 PCIR_BAR(2), sc->bge_res2); 2741 } 2742 2743 bge_dma_free(sc); 2744 2745 return 0; 2746 } 2747 2748 static void 2749 bge_reset(struct bge_softc *sc) 2750 { 2751 device_t dev = sc->bge_dev; 2752 uint32_t cachesize, command, reset, mac_mode, mac_mode_mask; 2753 void (*write_op)(struct bge_softc *, uint32_t, uint32_t); 2754 int i, val = 0; 2755 2756 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 2757 if (sc->bge_mfw_flags & BGE_MFW_ON_APE) 2758 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2759 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 2760 2761 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2762 sc->bge_asicrev != BGE_ASICREV_BCM5906) { 2763 if (sc->bge_flags & BGE_FLAG_PCIE) 2764 write_op = bge_writemem_direct; 2765 else 2766 write_op = bge_writemem_ind; 2767 } else { 2768 write_op = bge_writereg_ind; 2769 } 2770 2771 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2772 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 2773 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 2774 for (i = 0; i < 8000; i++) { 2775 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 2776 BGE_NVRAMSWARB_GNT1) 2777 break; 2778 DELAY(20); 2779 } 2780 if (i == 8000) { 2781 if (bootverbose) { 2782 if_printf(&sc->arpcom.ac_if, 2783 "NVRAM lock timedout!\n"); 2784 } 2785 } 2786 } 2787 /* Take APE lock when performing reset. */ 2788 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 2789 2790 /* Save some important PCI state. */ 2791 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2792 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2793 2794 pci_write_config(dev, BGE_PCI_MISC_CTL, 2795 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2796 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2797 sc->bge_pci_miscctl, 4); 2798 2799 /* Disable fastboot on controllers that support it. */ 2800 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2801 BGE_IS_5755_PLUS(sc)) { 2802 if (bootverbose) 2803 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n"); 2804 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2805 } 2806 2807 /* 2808 * Write the magic number to SRAM at offset 0xB50. 2809 * When firmware finishes its initialization it will 2810 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 2811 */ 2812 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2813 2814 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2815 2816 /* XXX: Broadcom Linux driver. */ 2817 if (sc->bge_flags & BGE_FLAG_PCIE) { 2818 /* Force PCI-E 1.0a mode */ 2819 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2820 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) == 2821 (BGE_PCIE_PHY_TSTCTL_PSCRAM | 2822 BGE_PCIE_PHY_TSTCTL_PCIE10)) { 2823 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL, 2824 BGE_PCIE_PHY_TSTCTL_PSCRAM); 2825 } 2826 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2827 /* Prevent PCIE link training during global reset */ 2828 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2829 reset |= (1<<29); 2830 } 2831 } 2832 2833 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2834 uint32_t status, ctrl; 2835 2836 status = CSR_READ_4(sc, BGE_VCPU_STATUS); 2837 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2838 status | BGE_VCPU_STATUS_DRV_RESET); 2839 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2840 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2841 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2842 } 2843 2844 /* 2845 * Set GPHY Power Down Override to leave GPHY 2846 * powered up in D0 uninitialized. 2847 */ 2848 if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0) 2849 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 2850 2851 /* Issue global reset */ 2852 write_op(sc, BGE_MISC_CFG, reset); 2853 2854 if (sc->bge_flags & BGE_FLAG_PCIE) 2855 DELAY(100 * 1000); 2856 else 2857 DELAY(1000); 2858 2859 /* XXX: Broadcom Linux driver. */ 2860 if (sc->bge_flags & BGE_FLAG_PCIE) { 2861 uint16_t devctl; 2862 2863 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2864 uint32_t v; 2865 2866 DELAY(500000); /* wait for link training to complete */ 2867 v = pci_read_config(dev, 0xc4, 4); 2868 pci_write_config(dev, 0xc4, v | (1<<15), 4); 2869 } 2870 2871 devctl = pci_read_config(dev, 2872 sc->bge_pciecap + PCIER_DEVCTRL, 2); 2873 2874 /* Disable no snoop and disable relaxed ordering. */ 2875 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP); 2876 2877 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */ 2878 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) { 2879 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK; 2880 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128; 2881 } 2882 2883 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL, 2884 devctl, 2); 2885 2886 /* Clear error status. */ 2887 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS, 2888 PCIEM_DEVSTS_CORR_ERR | 2889 PCIEM_DEVSTS_NFATAL_ERR | 2890 PCIEM_DEVSTS_FATAL_ERR | 2891 PCIEM_DEVSTS_UNSUPP_REQ, 2); 2892 } 2893 2894 /* Reset some of the PCI state that got zapped by reset */ 2895 pci_write_config(dev, BGE_PCI_MISC_CTL, 2896 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2897 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2898 sc->bge_pci_miscctl, 4); 2899 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 2900 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 2901 (sc->bge_flags & BGE_FLAG_PCIX)) 2902 val |= BGE_PCISTATE_RETRY_SAME_DMA; 2903 if (sc->bge_mfw_flags & BGE_MFW_ON_APE) { 2904 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 2905 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 2906 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 2907 } 2908 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 2909 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2910 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2911 2912 /* 2913 * Disable PCI-X relaxed ordering to ensure status block update 2914 * comes first then packet buffer DMA. Otherwise driver may 2915 * read stale status block. 2916 */ 2917 if (sc->bge_flags & BGE_FLAG_PCIX) { 2918 uint16_t devctl; 2919 2920 devctl = pci_read_config(dev, 2921 sc->bge_pcixcap + PCIXR_COMMAND, 2); 2922 devctl &= ~PCIXM_COMMAND_ERO; 2923 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 2924 devctl &= ~PCIXM_COMMAND_MAX_READ; 2925 devctl |= PCIXM_COMMAND_MAX_READ_2048; 2926 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 2927 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 2928 PCIXM_COMMAND_MAX_READ); 2929 devctl |= PCIXM_COMMAND_MAX_READ_2048; 2930 } 2931 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 2932 devctl, 2); 2933 } 2934 2935 /* 2936 * Enable memory arbiter and re-enable MSI if necessary. 2937 */ 2938 if (BGE_IS_5714_FAMILY(sc)) { 2939 uint32_t val; 2940 2941 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 2942 /* 2943 * Resetting BCM5714 family will clear MSI 2944 * enable bit; restore it after resetting. 2945 */ 2946 PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL, 2947 PCIM_MSICTRL_MSI_ENABLE, 2); 2948 BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE); 2949 } 2950 val = CSR_READ_4(sc, BGE_MARB_MODE); 2951 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2952 } else { 2953 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2954 } 2955 2956 /* Fix up byte swapping. */ 2957 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2958 BGE_MODECTL_BYTESWAP_DATA); 2959 2960 val = CSR_READ_4(sc, BGE_MAC_MODE); 2961 val = (val & ~mac_mode_mask) | mac_mode; 2962 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2963 DELAY(40); 2964 2965 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 2966 2967 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2968 for (i = 0; i < BGE_TIMEOUT; i++) { 2969 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2970 if (val & BGE_VCPU_STATUS_INIT_DONE) 2971 break; 2972 DELAY(100); 2973 } 2974 if (i == BGE_TIMEOUT) { 2975 if_printf(&sc->arpcom.ac_if, "reset timed out\n"); 2976 return; 2977 } 2978 } else { 2979 int delay_us = 10; 2980 2981 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2982 delay_us = 100; 2983 2984 /* 2985 * Poll until we see the 1's complement of the magic number. 2986 * This indicates that the firmware initialization 2987 * is complete. 2988 */ 2989 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) { 2990 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2991 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2992 break; 2993 DELAY(delay_us); 2994 } 2995 if (i == BGE_FIRMWARE_TIMEOUT) { 2996 if_printf(&sc->arpcom.ac_if, "firmware handshake " 2997 "timed out, found 0x%08x\n", val); 2998 } 2999 } 3000 3001 /* 3002 * The 5704 in TBI mode apparently needs some special 3003 * adjustment to insure the SERDES drive level is set 3004 * to 1.2V. 3005 */ 3006 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3007 (sc->bge_flags & BGE_FLAG_TBI)) { 3008 uint32_t serdescfg; 3009 3010 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3011 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3012 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3013 } 3014 3015 /* XXX: Broadcom Linux driver. */ 3016 if ((sc->bge_flags & BGE_FLAG_PCIE) && 3017 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3018 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 3019 uint32_t v; 3020 3021 /* Enable Data FIFO protection. */ 3022 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT); 3023 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25)); 3024 } 3025 3026 DELAY(10000); 3027 } 3028 3029 /* 3030 * Frame reception handling. This is called if there's a frame 3031 * on the receive return list. 3032 * 3033 * Note: we have to be able to handle two possibilities here: 3034 * 1) the frame is from the jumbo recieve ring 3035 * 2) the frame is from the standard receive ring 3036 */ 3037 3038 static void 3039 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int count) 3040 { 3041 struct ifnet *ifp; 3042 int stdcnt = 0, jumbocnt = 0; 3043 3044 ifp = &sc->arpcom.ac_if; 3045 3046 while (sc->bge_rx_saved_considx != rx_prod && count != 0) { 3047 struct bge_rx_bd *cur_rx; 3048 uint32_t rxidx; 3049 struct mbuf *m = NULL; 3050 uint16_t vlan_tag = 0; 3051 int have_tag = 0; 3052 3053 --count; 3054 3055 cur_rx = 3056 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 3057 3058 rxidx = cur_rx->bge_idx; 3059 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3060 logif(rx_pkt); 3061 3062 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3063 have_tag = 1; 3064 vlan_tag = cur_rx->bge_vlan_tag; 3065 } 3066 3067 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3068 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3069 jumbocnt++; 3070 3071 if (rxidx != sc->bge_jumbo) { 3072 IFNET_STAT_INC(ifp, ierrors, 1); 3073 if_printf(ifp, "sw jumbo index(%d) " 3074 "and hw jumbo index(%d) mismatch, drop!\n", 3075 sc->bge_jumbo, rxidx); 3076 bge_setup_rxdesc_jumbo(sc, rxidx); 3077 continue; 3078 } 3079 3080 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf; 3081 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3082 IFNET_STAT_INC(ifp, ierrors, 1); 3083 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo); 3084 continue; 3085 } 3086 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) { 3087 IFNET_STAT_INC(ifp, ierrors, 1); 3088 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo); 3089 continue; 3090 } 3091 } else { 3092 int discard = 0; 3093 3094 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3095 stdcnt++; 3096 3097 if (rxidx != sc->bge_std) { 3098 IFNET_STAT_INC(ifp, ierrors, 1); 3099 if_printf(ifp, "sw std index(%d) " 3100 "and hw std index(%d) mismatch, drop!\n", 3101 sc->bge_std, rxidx); 3102 bge_setup_rxdesc_std(sc, rxidx); 3103 discard = 1; 3104 goto refresh_rx; 3105 } 3106 3107 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf; 3108 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3109 IFNET_STAT_INC(ifp, ierrors, 1); 3110 bge_setup_rxdesc_std(sc, sc->bge_std); 3111 discard = 1; 3112 goto refresh_rx; 3113 } 3114 if (bge_newbuf_std(sc, sc->bge_std, 0)) { 3115 IFNET_STAT_INC(ifp, ierrors, 1); 3116 bge_setup_rxdesc_std(sc, sc->bge_std); 3117 discard = 1; 3118 } 3119 refresh_rx: 3120 if (sc->bge_rx_wreg > 0 && stdcnt >= sc->bge_rx_wreg) { 3121 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 3122 sc->bge_std); 3123 stdcnt = 0; 3124 } 3125 if (discard) 3126 continue; 3127 } 3128 3129 IFNET_STAT_INC(ifp, ipackets, 1); 3130 #if !defined(__i386__) && !defined(__x86_64__) 3131 /* 3132 * The x86 allows unaligned accesses, but for other 3133 * platforms we must make sure the payload is aligned. 3134 */ 3135 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3136 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3137 cur_rx->bge_len); 3138 m->m_data += ETHER_ALIGN; 3139 } 3140 #endif 3141 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3142 m->m_pkthdr.rcvif = ifp; 3143 3144 if (ifp->if_capenable & IFCAP_RXCSUM) { 3145 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3146 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3147 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 3148 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3149 } 3150 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) && 3151 m->m_pkthdr.len >= BGE_MIN_FRAMELEN) { 3152 m->m_pkthdr.csum_data = 3153 cur_rx->bge_tcp_udp_csum; 3154 m->m_pkthdr.csum_flags |= 3155 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3156 } 3157 } 3158 3159 /* 3160 * If we received a packet with a vlan tag, pass it 3161 * to vlan_input() instead of ether_input(). 3162 */ 3163 if (have_tag) { 3164 m->m_flags |= M_VLANTAG; 3165 m->m_pkthdr.ether_vlantag = vlan_tag; 3166 } 3167 ifp->if_input(ifp, m, NULL, -1); 3168 } 3169 3170 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3171 if (stdcnt) 3172 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3173 if (jumbocnt) 3174 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3175 } 3176 3177 static void 3178 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3179 { 3180 struct ifnet *ifp; 3181 3182 ifp = &sc->arpcom.ac_if; 3183 3184 /* 3185 * Go through our tx ring and free mbufs for those 3186 * frames that have been sent. 3187 */ 3188 while (sc->bge_tx_saved_considx != tx_cons) { 3189 uint32_t idx = 0; 3190 3191 idx = sc->bge_tx_saved_considx; 3192 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3193 IFNET_STAT_INC(ifp, opackets, 1); 3194 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3195 sc->bge_cdata.bge_tx_dmamap[idx]); 3196 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3197 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3198 } 3199 sc->bge_txcnt--; 3200 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3201 logif(tx_pkt); 3202 } 3203 3204 if ((BGE_TX_RING_CNT - sc->bge_txcnt) >= 3205 (sc->bge_txrsvd + sc->bge_txspare)) 3206 ifq_clr_oactive(&ifp->if_snd); 3207 3208 if (sc->bge_txcnt == 0) 3209 ifp->if_timer = 0; 3210 3211 if (!ifq_is_empty(&ifp->if_snd)) 3212 if_devstart(ifp); 3213 } 3214 3215 #ifdef IFPOLL_ENABLE 3216 3217 static void 3218 bge_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycles) 3219 { 3220 struct bge_softc *sc = ifp->if_softc; 3221 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3222 uint16_t rx_prod, tx_cons; 3223 3224 ASSERT_SERIALIZED(ifp->if_serializer); 3225 3226 if (sc->bge_npoll.ifpc_stcount-- == 0) { 3227 sc->bge_npoll.ifpc_stcount = sc->bge_npoll.ifpc_stfrac; 3228 /* 3229 * Process link state changes. 3230 */ 3231 bge_link_poll(sc); 3232 } 3233 3234 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 3235 sc->bge_status_tag = sblk->bge_status_tag; 3236 /* 3237 * Use a load fence to ensure that status_tag 3238 * is saved before rx_prod and tx_cons. 3239 */ 3240 cpu_lfence(); 3241 } 3242 3243 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3244 if (sc->bge_rx_saved_considx != rx_prod) 3245 bge_rxeof(sc, rx_prod, cycles); 3246 3247 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3248 if (sc->bge_tx_saved_considx != tx_cons) 3249 bge_txeof(sc, tx_cons); 3250 3251 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) 3252 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 3253 3254 if (sc->bge_coal_chg) 3255 bge_coal_change(sc); 3256 } 3257 3258 static void 3259 bge_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3260 { 3261 struct bge_softc *sc = ifp->if_softc; 3262 3263 ASSERT_SERIALIZED(ifp->if_serializer); 3264 3265 if (info != NULL) { 3266 int cpuid = sc->bge_npoll.ifpc_cpuid; 3267 3268 info->ifpi_rx[cpuid].poll_func = bge_npoll_compat; 3269 info->ifpi_rx[cpuid].arg = NULL; 3270 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 3271 3272 if (ifp->if_flags & IFF_RUNNING) 3273 bge_disable_intr(sc); 3274 ifq_set_cpuid(&ifp->if_snd, cpuid); 3275 } else { 3276 if (ifp->if_flags & IFF_RUNNING) 3277 bge_enable_intr(sc); 3278 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq)); 3279 } 3280 } 3281 3282 #endif /* IFPOLL_ENABLE */ 3283 3284 static void 3285 bge_intr_crippled(void *xsc) 3286 { 3287 struct bge_softc *sc = xsc; 3288 struct ifnet *ifp = &sc->arpcom.ac_if; 3289 3290 logif(intr); 3291 3292 /* 3293 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3294 * disable interrupts by writing nonzero like we used to, since with 3295 * our current organization this just gives complications and 3296 * pessimizations for re-enabling interrupts. We used to have races 3297 * instead of the necessary complications. Disabling interrupts 3298 * would just reduce the chance of a status update while we are 3299 * running (by switching to the interrupt-mode coalescence 3300 * parameters), but this chance is already very low so it is more 3301 * efficient to get another interrupt than prevent it. 3302 * 3303 * We do the ack first to ensure another interrupt if there is a 3304 * status update after the ack. We don't check for the status 3305 * changing later because it is more efficient to get another 3306 * interrupt than prevent it, not quite as above (not checking is 3307 * a smaller optimization than not toggling the interrupt enable, 3308 * since checking doesn't involve PCI accesses and toggling require 3309 * the status check). So toggling would probably be a pessimization 3310 * even with MSI. It would only be needed for using a task queue. 3311 */ 3312 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3313 3314 /* 3315 * Process link state changes. 3316 */ 3317 bge_link_poll(sc); 3318 3319 if (ifp->if_flags & IFF_RUNNING) { 3320 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3321 uint16_t rx_prod, tx_cons; 3322 3323 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3324 if (sc->bge_rx_saved_considx != rx_prod) 3325 bge_rxeof(sc, rx_prod, -1); 3326 3327 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3328 if (sc->bge_tx_saved_considx != tx_cons) 3329 bge_txeof(sc, tx_cons); 3330 } 3331 3332 if (sc->bge_coal_chg) 3333 bge_coal_change(sc); 3334 } 3335 3336 static void 3337 bge_intr_legacy(void *xsc) 3338 { 3339 struct bge_softc *sc = xsc; 3340 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3341 3342 if (sc->bge_status_tag == sblk->bge_status_tag) { 3343 uint32_t val; 3344 3345 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3346 if (val & BGE_PCISTAT_INTR_NOTACT) 3347 return; 3348 } 3349 3350 /* 3351 * NOTE: 3352 * Interrupt will have to be disabled if tagged status 3353 * is used, else interrupt will always be asserted on 3354 * certain chips (at least on BCM5750 AX/BX). 3355 */ 3356 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3357 3358 bge_intr(sc); 3359 } 3360 3361 static void 3362 bge_msi(void *xsc) 3363 { 3364 struct bge_softc *sc = xsc; 3365 3366 /* Disable interrupt first */ 3367 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3368 bge_intr(sc); 3369 } 3370 3371 static void 3372 bge_msi_oneshot(void *xsc) 3373 { 3374 bge_intr(xsc); 3375 } 3376 3377 static void 3378 bge_intr(struct bge_softc *sc) 3379 { 3380 struct ifnet *ifp = &sc->arpcom.ac_if; 3381 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3382 uint16_t rx_prod, tx_cons; 3383 uint32_t status; 3384 3385 sc->bge_status_tag = sblk->bge_status_tag; 3386 /* 3387 * Use a load fence to ensure that status_tag is saved 3388 * before rx_prod, tx_cons and status. 3389 */ 3390 cpu_lfence(); 3391 3392 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3393 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3394 status = sblk->bge_status; 3395 3396 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt) 3397 bge_link_poll(sc); 3398 3399 if (ifp->if_flags & IFF_RUNNING) { 3400 if (sc->bge_rx_saved_considx != rx_prod) 3401 bge_rxeof(sc, rx_prod, -1); 3402 3403 if (sc->bge_tx_saved_considx != tx_cons) 3404 bge_txeof(sc, tx_cons); 3405 } 3406 3407 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 3408 3409 if (sc->bge_coal_chg) 3410 bge_coal_change(sc); 3411 } 3412 3413 static void 3414 bge_tick(void *xsc) 3415 { 3416 struct bge_softc *sc = xsc; 3417 struct ifnet *ifp = &sc->arpcom.ac_if; 3418 3419 lwkt_serialize_enter(ifp->if_serializer); 3420 3421 if (BGE_IS_5705_PLUS(sc)) 3422 bge_stats_update_regs(sc); 3423 else 3424 bge_stats_update(sc); 3425 3426 if (sc->bge_flags & BGE_FLAG_TBI) { 3427 /* 3428 * Since in TBI mode auto-polling can't be used we should poll 3429 * link status manually. Here we register pending link event 3430 * and trigger interrupt. 3431 */ 3432 sc->bge_link_evt++; 3433 if (BGE_IS_CRIPPLED(sc)) 3434 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3435 else 3436 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3437 } else if (!sc->bge_link) { 3438 mii_tick(device_get_softc(sc->bge_miibus)); 3439 } 3440 3441 bge_asf_driver_up(sc); 3442 3443 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 3444 3445 lwkt_serialize_exit(ifp->if_serializer); 3446 } 3447 3448 static void 3449 bge_stats_update_regs(struct bge_softc *sc) 3450 { 3451 struct ifnet *ifp = &sc->arpcom.ac_if; 3452 struct bge_mac_stats_regs stats; 3453 uint32_t *s; 3454 int i; 3455 3456 s = (uint32_t *)&stats; 3457 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 3458 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 3459 s++; 3460 } 3461 3462 IFNET_STAT_SET(ifp, collisions, 3463 (stats.dot3StatsSingleCollisionFrames + 3464 stats.dot3StatsMultipleCollisionFrames + 3465 stats.dot3StatsExcessiveCollisions + 3466 stats.dot3StatsLateCollisions)); 3467 } 3468 3469 static void 3470 bge_stats_update(struct bge_softc *sc) 3471 { 3472 struct ifnet *ifp = &sc->arpcom.ac_if; 3473 bus_size_t stats; 3474 3475 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3476 3477 #define READ_STAT(sc, stats, stat) \ 3478 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3479 3480 IFNET_STAT_SET(ifp, collisions, 3481 (READ_STAT(sc, stats, 3482 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) + 3483 READ_STAT(sc, stats, 3484 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3485 READ_STAT(sc, stats, 3486 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) + 3487 READ_STAT(sc, stats, 3488 txstats.dot3StatsLateCollisions.bge_addr_lo))); 3489 3490 #undef READ_STAT 3491 3492 #ifdef notdef 3493 IFNET_STAT_SET(ifp, collisions, 3494 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3495 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3496 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3497 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions)); 3498 #endif 3499 } 3500 3501 /* 3502 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3503 * pointers to descriptors. 3504 */ 3505 static int 3506 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx, 3507 int *segs_used) 3508 { 3509 struct bge_tx_bd *d = NULL, *last_d; 3510 uint16_t csum_flags = 0, mss = 0; 3511 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3512 bus_dmamap_t map; 3513 int error, maxsegs, nsegs, idx, i; 3514 struct mbuf *m_head = *m_head0, *m_new; 3515 3516 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3517 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags); 3518 if (error) 3519 return ENOBUFS; 3520 m_head = *m_head0; 3521 } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) { 3522 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3523 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3524 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3525 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3526 if (m_head->m_flags & M_LASTFRAG) 3527 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3528 else if (m_head->m_flags & M_FRAG) 3529 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3530 } 3531 3532 idx = *txidx; 3533 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3534 3535 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd; 3536 KASSERT(maxsegs >= sc->bge_txspare, 3537 ("not enough segments %d", maxsegs)); 3538 3539 if (maxsegs > BGE_NSEG_NEW) 3540 maxsegs = BGE_NSEG_NEW; 3541 3542 /* 3543 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason. 3544 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN, 3545 * but when such padded frames employ the bge IP/TCP checksum 3546 * offload, the hardware checksum assist gives incorrect results 3547 * (possibly from incorporating its own padding into the UDP/TCP 3548 * checksum; who knows). If we pad such runts with zeros, the 3549 * onboard checksum comes out correct. 3550 */ 3551 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) && 3552 m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) { 3553 error = m_devpad(m_head, BGE_MIN_FRAMELEN); 3554 if (error) 3555 goto back; 3556 } 3557 3558 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) { 3559 m_new = bge_defrag_shortdma(m_head); 3560 if (m_new == NULL) { 3561 error = ENOBUFS; 3562 goto back; 3563 } 3564 *m_head0 = m_head = m_new; 3565 } 3566 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3567 sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) && 3568 m_head->m_next != NULL) { 3569 /* 3570 * Forcefully defragment mbuf chain to overcome hardware 3571 * limitation which only support a single outstanding 3572 * DMA read operation. If it fails, keep moving on using 3573 * the original mbuf chain. 3574 */ 3575 m_new = m_defrag(m_head, MB_DONTWAIT); 3576 if (m_new != NULL) 3577 *m_head0 = m_head = m_new; 3578 } 3579 3580 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map, 3581 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 3582 if (error) 3583 goto back; 3584 *segs_used += nsegs; 3585 3586 m_head = *m_head0; 3587 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3588 3589 for (i = 0; ; i++) { 3590 d = &sc->bge_ldata.bge_tx_ring[idx]; 3591 3592 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3593 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3594 d->bge_len = segs[i].ds_len; 3595 d->bge_flags = csum_flags; 3596 d->bge_mss = mss; 3597 3598 if (i == nsegs - 1) 3599 break; 3600 BGE_INC(idx, BGE_TX_RING_CNT); 3601 } 3602 last_d = d; 3603 3604 /* Set vlan tag to the first segment of the packet. */ 3605 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3606 if (m_head->m_flags & M_VLANTAG) { 3607 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3608 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag; 3609 } else { 3610 d->bge_vlan_tag = 0; 3611 } 3612 3613 /* Mark the last segment as end of packet... */ 3614 last_d->bge_flags |= BGE_TXBDFLAG_END; 3615 3616 /* 3617 * Insure that the map for this transmission is placed at 3618 * the array index of the last descriptor in this chain. 3619 */ 3620 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3621 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3622 sc->bge_cdata.bge_tx_chain[idx] = m_head; 3623 sc->bge_txcnt += nsegs; 3624 3625 BGE_INC(idx, BGE_TX_RING_CNT); 3626 *txidx = idx; 3627 back: 3628 if (error) { 3629 m_freem(*m_head0); 3630 *m_head0 = NULL; 3631 } 3632 return error; 3633 } 3634 3635 static void 3636 bge_xmit(struct bge_softc *sc, uint32_t prodidx) 3637 { 3638 /* Transmit */ 3639 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3640 /* 5700 b2 errata */ 3641 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3642 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3643 } 3644 3645 /* 3646 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3647 * to the mbuf data regions directly in the transmit descriptors. 3648 */ 3649 static void 3650 bge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 3651 { 3652 struct bge_softc *sc = ifp->if_softc; 3653 struct mbuf *m_head = NULL; 3654 uint32_t prodidx; 3655 int nsegs = 0; 3656 3657 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 3658 3659 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 3660 return; 3661 3662 prodidx = sc->bge_tx_prodidx; 3663 3664 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3665 m_head = ifq_dequeue(&ifp->if_snd); 3666 if (m_head == NULL) 3667 break; 3668 3669 /* 3670 * XXX 3671 * The code inside the if() block is never reached since we 3672 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3673 * requests to checksum TCP/UDP in a fragmented packet. 3674 * 3675 * XXX 3676 * safety overkill. If this is a fragmented packet chain 3677 * with delayed TCP/UDP checksums, then only encapsulate 3678 * it if we have enough descriptors to handle the entire 3679 * chain at once. 3680 * (paranoia -- may not actually be needed) 3681 */ 3682 if ((m_head->m_flags & M_FIRSTFRAG) && 3683 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) { 3684 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3685 m_head->m_pkthdr.csum_data + sc->bge_txrsvd) { 3686 ifq_set_oactive(&ifp->if_snd); 3687 ifq_prepend(&ifp->if_snd, m_head); 3688 break; 3689 } 3690 } 3691 3692 /* 3693 * Sanity check: avoid coming within bge_txrsvd 3694 * descriptors of the end of the ring. Also make 3695 * sure there are bge_txspare descriptors for 3696 * jumbo buffers' defragmentation. 3697 */ 3698 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3699 (sc->bge_txrsvd + sc->bge_txspare)) { 3700 ifq_set_oactive(&ifp->if_snd); 3701 ifq_prepend(&ifp->if_snd, m_head); 3702 break; 3703 } 3704 3705 /* 3706 * Pack the data into the transmit ring. If we 3707 * don't have room, set the OACTIVE flag and wait 3708 * for the NIC to drain the ring. 3709 */ 3710 if (bge_encap(sc, &m_head, &prodidx, &nsegs)) { 3711 ifq_set_oactive(&ifp->if_snd); 3712 IFNET_STAT_INC(ifp, oerrors, 1); 3713 break; 3714 } 3715 3716 if (nsegs >= sc->bge_tx_wreg) { 3717 bge_xmit(sc, prodidx); 3718 nsegs = 0; 3719 } 3720 3721 ETHER_BPF_MTAP(ifp, m_head); 3722 3723 /* 3724 * Set a timeout in case the chip goes out to lunch. 3725 */ 3726 ifp->if_timer = 5; 3727 } 3728 3729 if (nsegs > 0) 3730 bge_xmit(sc, prodidx); 3731 sc->bge_tx_prodidx = prodidx; 3732 } 3733 3734 static void 3735 bge_init(void *xsc) 3736 { 3737 struct bge_softc *sc = xsc; 3738 struct ifnet *ifp = &sc->arpcom.ac_if; 3739 uint16_t *m; 3740 uint32_t mode; 3741 3742 ASSERT_SERIALIZED(ifp->if_serializer); 3743 3744 /* Cancel pending I/O and flush buffers. */ 3745 bge_stop(sc); 3746 3747 bge_stop_fw(sc); 3748 bge_sig_pre_reset(sc, BGE_RESET_START); 3749 bge_reset(sc); 3750 bge_sig_legacy(sc, BGE_RESET_START); 3751 bge_sig_post_reset(sc, BGE_RESET_START); 3752 3753 bge_chipinit(sc); 3754 3755 /* 3756 * Init the various state machines, ring 3757 * control blocks and firmware. 3758 */ 3759 if (bge_blockinit(sc)) { 3760 if_printf(ifp, "initialization failure\n"); 3761 bge_stop(sc); 3762 return; 3763 } 3764 3765 /* Specify MTU. */ 3766 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3767 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN); 3768 3769 /* Load our MAC address. */ 3770 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 3771 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3772 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3773 3774 /* Enable or disable promiscuous mode as needed. */ 3775 bge_setpromisc(sc); 3776 3777 /* Program multicast filter. */ 3778 bge_setmulti(sc); 3779 3780 /* Init RX ring. */ 3781 if (bge_init_rx_ring_std(sc)) { 3782 if_printf(ifp, "RX ring initialization failed\n"); 3783 bge_stop(sc); 3784 return; 3785 } 3786 3787 /* 3788 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3789 * memory to insure that the chip has in fact read the first 3790 * entry of the ring. 3791 */ 3792 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3793 uint32_t v, i; 3794 for (i = 0; i < 10; i++) { 3795 DELAY(20); 3796 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3797 if (v == (MCLBYTES - ETHER_ALIGN)) 3798 break; 3799 } 3800 if (i == 10) 3801 if_printf(ifp, "5705 A0 chip failed to load RX ring\n"); 3802 } 3803 3804 /* Init jumbo RX ring. */ 3805 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) { 3806 if (bge_init_rx_ring_jumbo(sc)) { 3807 if_printf(ifp, "Jumbo RX ring initialization failed\n"); 3808 bge_stop(sc); 3809 return; 3810 } 3811 } 3812 3813 /* Init our RX return ring index */ 3814 sc->bge_rx_saved_considx = 0; 3815 3816 /* Init TX ring. */ 3817 bge_init_tx_ring(sc); 3818 3819 /* Enable TX MAC state machine lockup fix. */ 3820 mode = CSR_READ_4(sc, BGE_TX_MODE); 3821 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3822 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 3823 /* Turn on transmitter */ 3824 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 3825 DELAY(100); 3826 3827 /* Turn on receiver */ 3828 mode = CSR_READ_4(sc, BGE_RX_MODE); 3829 if (BGE_IS_5755_PLUS(sc)) 3830 mode |= BGE_RXMODE_IPV6_ENABLE; 3831 CSR_WRITE_4(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 3832 DELAY(10); 3833 3834 /* 3835 * Set the number of good frames to receive after RX MBUF 3836 * Low Watermark has been reached. After the RX MAC receives 3837 * this number of frames, it will drop subsequent incoming 3838 * frames until the MBUF High Watermark is reached. 3839 */ 3840 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3841 3842 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 3843 if (bootverbose) { 3844 if_printf(ifp, "MSI_MODE: %#x\n", 3845 CSR_READ_4(sc, BGE_MSI_MODE)); 3846 } 3847 3848 /* 3849 * XXX 3850 * Linux driver turns it on for all chips supporting MSI?! 3851 */ 3852 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 3853 /* 3854 * XXX 3855 * According to 5722-PG101-R, 3856 * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to 3857 * BCM5906. 3858 */ 3859 BGE_SETBIT(sc, BGE_PCIE_TRANSACT, 3860 BGE_PCIE_TRANSACT_ONESHOT_MSI); 3861 } 3862 } 3863 3864 /* Tell firmware we're alive. */ 3865 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3866 3867 /* Enable host interrupts if polling(4) is not enabled. */ 3868 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4); 3869 #ifdef IFPOLL_ENABLE 3870 if (ifp->if_flags & IFF_NPOLLING) 3871 bge_disable_intr(sc); 3872 else 3873 #endif 3874 bge_enable_intr(sc); 3875 3876 ifp->if_flags |= IFF_RUNNING; 3877 ifq_clr_oactive(&ifp->if_snd); 3878 3879 bge_ifmedia_upd(ifp); 3880 3881 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 3882 } 3883 3884 /* 3885 * Set media options. 3886 */ 3887 static int 3888 bge_ifmedia_upd(struct ifnet *ifp) 3889 { 3890 struct bge_softc *sc = ifp->if_softc; 3891 3892 /* If this is a 1000baseX NIC, enable the TBI port. */ 3893 if (sc->bge_flags & BGE_FLAG_TBI) { 3894 struct ifmedia *ifm = &sc->bge_ifmedia; 3895 3896 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3897 return(EINVAL); 3898 3899 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3900 case IFM_AUTO: 3901 /* 3902 * The BCM5704 ASIC appears to have a special 3903 * mechanism for programming the autoneg 3904 * advertisement registers in TBI mode. 3905 */ 3906 if (!bge_fake_autoneg && 3907 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3908 uint32_t sgdig; 3909 3910 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3911 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3912 sgdig |= BGE_SGDIGCFG_AUTO | 3913 BGE_SGDIGCFG_PAUSE_CAP | 3914 BGE_SGDIGCFG_ASYM_PAUSE; 3915 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3916 sgdig | BGE_SGDIGCFG_SEND); 3917 DELAY(5); 3918 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3919 } 3920 break; 3921 case IFM_1000_SX: 3922 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3923 BGE_CLRBIT(sc, BGE_MAC_MODE, 3924 BGE_MACMODE_HALF_DUPLEX); 3925 } else { 3926 BGE_SETBIT(sc, BGE_MAC_MODE, 3927 BGE_MACMODE_HALF_DUPLEX); 3928 } 3929 DELAY(40); 3930 break; 3931 default: 3932 return(EINVAL); 3933 } 3934 } else { 3935 struct mii_data *mii = device_get_softc(sc->bge_miibus); 3936 3937 sc->bge_link_evt++; 3938 sc->bge_link = 0; 3939 if (mii->mii_instance) { 3940 struct mii_softc *miisc; 3941 3942 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3943 mii_phy_reset(miisc); 3944 } 3945 mii_mediachg(mii); 3946 3947 /* 3948 * Force an interrupt so that we will call bge_link_upd 3949 * if needed and clear any pending link state attention. 3950 * Without this we are not getting any further interrupts 3951 * for link state changes and thus will not UP the link and 3952 * not be able to send in bge_start. The only way to get 3953 * things working was to receive a packet and get an RX 3954 * intr. 3955 * 3956 * bge_tick should help for fiber cards and we might not 3957 * need to do this here if BGE_FLAG_TBI is set but as 3958 * we poll for fiber anyway it should not harm. 3959 */ 3960 if (BGE_IS_CRIPPLED(sc)) 3961 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3962 else 3963 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3964 } 3965 return(0); 3966 } 3967 3968 /* 3969 * Report current media status. 3970 */ 3971 static void 3972 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3973 { 3974 struct bge_softc *sc = ifp->if_softc; 3975 3976 if ((ifp->if_flags & IFF_RUNNING) == 0) 3977 return; 3978 3979 if (sc->bge_flags & BGE_FLAG_TBI) { 3980 ifmr->ifm_status = IFM_AVALID; 3981 ifmr->ifm_active = IFM_ETHER; 3982 if (CSR_READ_4(sc, BGE_MAC_STS) & 3983 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3984 ifmr->ifm_status |= IFM_ACTIVE; 3985 } else { 3986 ifmr->ifm_active |= IFM_NONE; 3987 return; 3988 } 3989 3990 ifmr->ifm_active |= IFM_1000_SX; 3991 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3992 ifmr->ifm_active |= IFM_HDX; 3993 else 3994 ifmr->ifm_active |= IFM_FDX; 3995 } else { 3996 struct mii_data *mii = device_get_softc(sc->bge_miibus); 3997 3998 mii_pollstat(mii); 3999 ifmr->ifm_active = mii->mii_media_active; 4000 ifmr->ifm_status = mii->mii_media_status; 4001 } 4002 } 4003 4004 static int 4005 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 4006 { 4007 struct bge_softc *sc = ifp->if_softc; 4008 struct ifreq *ifr = (struct ifreq *)data; 4009 int mask, error = 0; 4010 4011 ASSERT_SERIALIZED(ifp->if_serializer); 4012 4013 switch (command) { 4014 case SIOCSIFMTU: 4015 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) || 4016 (BGE_IS_JUMBO_CAPABLE(sc) && 4017 ifr->ifr_mtu > BGE_JUMBO_MTU)) { 4018 error = EINVAL; 4019 } else if (ifp->if_mtu != ifr->ifr_mtu) { 4020 ifp->if_mtu = ifr->ifr_mtu; 4021 if (ifp->if_flags & IFF_RUNNING) 4022 bge_init(sc); 4023 } 4024 break; 4025 case SIOCSIFFLAGS: 4026 if (ifp->if_flags & IFF_UP) { 4027 if (ifp->if_flags & IFF_RUNNING) { 4028 mask = ifp->if_flags ^ sc->bge_if_flags; 4029 4030 /* 4031 * If only the state of the PROMISC flag 4032 * changed, then just use the 'set promisc 4033 * mode' command instead of reinitializing 4034 * the entire NIC. Doing a full re-init 4035 * means reloading the firmware and waiting 4036 * for it to start up, which may take a 4037 * second or two. Similarly for ALLMULTI. 4038 */ 4039 if (mask & IFF_PROMISC) 4040 bge_setpromisc(sc); 4041 if (mask & IFF_ALLMULTI) 4042 bge_setmulti(sc); 4043 } else { 4044 bge_init(sc); 4045 } 4046 } else if (ifp->if_flags & IFF_RUNNING) { 4047 bge_stop(sc); 4048 } 4049 sc->bge_if_flags = ifp->if_flags; 4050 break; 4051 case SIOCADDMULTI: 4052 case SIOCDELMULTI: 4053 if (ifp->if_flags & IFF_RUNNING) 4054 bge_setmulti(sc); 4055 break; 4056 case SIOCSIFMEDIA: 4057 case SIOCGIFMEDIA: 4058 if (sc->bge_flags & BGE_FLAG_TBI) { 4059 error = ifmedia_ioctl(ifp, ifr, 4060 &sc->bge_ifmedia, command); 4061 } else { 4062 struct mii_data *mii; 4063 4064 mii = device_get_softc(sc->bge_miibus); 4065 error = ifmedia_ioctl(ifp, ifr, 4066 &mii->mii_media, command); 4067 } 4068 break; 4069 case SIOCSIFCAP: 4070 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4071 if (mask & IFCAP_HWCSUM) { 4072 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 4073 if (ifp->if_capenable & IFCAP_TXCSUM) 4074 ifp->if_hwassist |= BGE_CSUM_FEATURES; 4075 else 4076 ifp->if_hwassist &= ~BGE_CSUM_FEATURES; 4077 } 4078 if (mask & IFCAP_TSO) { 4079 ifp->if_capenable ^= IFCAP_TSO; 4080 if (ifp->if_capenable & IFCAP_TSO) 4081 ifp->if_hwassist |= CSUM_TSO; 4082 else 4083 ifp->if_hwassist &= ~CSUM_TSO; 4084 } 4085 break; 4086 default: 4087 error = ether_ioctl(ifp, command, data); 4088 break; 4089 } 4090 return error; 4091 } 4092 4093 static void 4094 bge_watchdog(struct ifnet *ifp) 4095 { 4096 struct bge_softc *sc = ifp->if_softc; 4097 4098 if_printf(ifp, "watchdog timeout -- resetting\n"); 4099 4100 bge_init(sc); 4101 4102 IFNET_STAT_INC(ifp, oerrors, 1); 4103 4104 if (!ifq_is_empty(&ifp->if_snd)) 4105 if_devstart(ifp); 4106 } 4107 4108 /* 4109 * Stop the adapter and free any mbufs allocated to the 4110 * RX and TX lists. 4111 */ 4112 static void 4113 bge_stop(struct bge_softc *sc) 4114 { 4115 struct ifnet *ifp = &sc->arpcom.ac_if; 4116 4117 ASSERT_SERIALIZED(ifp->if_serializer); 4118 4119 callout_stop(&sc->bge_stat_timer); 4120 4121 /* Disable host interrupts. */ 4122 bge_disable_intr(sc); 4123 4124 /* 4125 * Tell firmware we're shutting down. 4126 */ 4127 bge_stop_fw(sc); 4128 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 4129 4130 /* 4131 * Disable all of the receiver blocks 4132 */ 4133 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4134 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4135 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4136 if (BGE_IS_5700_FAMILY(sc)) 4137 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4138 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4139 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4140 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4141 4142 /* 4143 * Disable all of the transmit blocks 4144 */ 4145 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4146 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4147 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4148 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4149 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4150 if (BGE_IS_5700_FAMILY(sc)) 4151 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4152 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4153 4154 /* 4155 * Shut down all of the memory managers and related 4156 * state machines. 4157 */ 4158 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4159 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4160 if (BGE_IS_5700_FAMILY(sc)) 4161 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4162 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4163 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4164 if (!BGE_IS_5705_PLUS(sc)) { 4165 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4166 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4167 } 4168 4169 bge_reset(sc); 4170 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 4171 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 4172 4173 /* 4174 * Keep the ASF firmware running if up. 4175 */ 4176 if (sc->bge_asf_mode & ASF_STACKUP) 4177 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4178 else 4179 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4180 4181 /* Free the RX lists. */ 4182 bge_free_rx_ring_std(sc); 4183 4184 /* Free jumbo RX list. */ 4185 if (BGE_IS_JUMBO_CAPABLE(sc)) 4186 bge_free_rx_ring_jumbo(sc); 4187 4188 /* Free TX buffers. */ 4189 bge_free_tx_ring(sc); 4190 4191 sc->bge_status_tag = 0; 4192 sc->bge_link = 0; 4193 sc->bge_coal_chg = 0; 4194 4195 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4196 4197 ifp->if_flags &= ~IFF_RUNNING; 4198 ifq_clr_oactive(&ifp->if_snd); 4199 ifp->if_timer = 0; 4200 } 4201 4202 /* 4203 * Stop all chip I/O so that the kernel's probe routines don't 4204 * get confused by errant DMAs when rebooting. 4205 */ 4206 static void 4207 bge_shutdown(device_t dev) 4208 { 4209 struct bge_softc *sc = device_get_softc(dev); 4210 struct ifnet *ifp = &sc->arpcom.ac_if; 4211 4212 lwkt_serialize_enter(ifp->if_serializer); 4213 bge_stop(sc); 4214 lwkt_serialize_exit(ifp->if_serializer); 4215 } 4216 4217 static int 4218 bge_suspend(device_t dev) 4219 { 4220 struct bge_softc *sc = device_get_softc(dev); 4221 struct ifnet *ifp = &sc->arpcom.ac_if; 4222 4223 lwkt_serialize_enter(ifp->if_serializer); 4224 bge_stop(sc); 4225 lwkt_serialize_exit(ifp->if_serializer); 4226 4227 return 0; 4228 } 4229 4230 static int 4231 bge_resume(device_t dev) 4232 { 4233 struct bge_softc *sc = device_get_softc(dev); 4234 struct ifnet *ifp = &sc->arpcom.ac_if; 4235 4236 lwkt_serialize_enter(ifp->if_serializer); 4237 4238 if (ifp->if_flags & IFF_UP) { 4239 bge_init(sc); 4240 4241 if (!ifq_is_empty(&ifp->if_snd)) 4242 if_devstart(ifp); 4243 } 4244 4245 lwkt_serialize_exit(ifp->if_serializer); 4246 4247 return 0; 4248 } 4249 4250 static void 4251 bge_setpromisc(struct bge_softc *sc) 4252 { 4253 struct ifnet *ifp = &sc->arpcom.ac_if; 4254 4255 if (ifp->if_flags & IFF_PROMISC) 4256 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4257 else 4258 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4259 } 4260 4261 static void 4262 bge_dma_free(struct bge_softc *sc) 4263 { 4264 int i; 4265 4266 /* Destroy RX mbuf DMA stuffs. */ 4267 if (sc->bge_cdata.bge_rx_mtag != NULL) { 4268 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4269 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4270 sc->bge_cdata.bge_rx_std_dmamap[i]); 4271 } 4272 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4273 sc->bge_cdata.bge_rx_tmpmap); 4274 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4275 } 4276 4277 /* Destroy TX mbuf DMA stuffs. */ 4278 if (sc->bge_cdata.bge_tx_mtag != NULL) { 4279 for (i = 0; i < BGE_TX_RING_CNT; i++) { 4280 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 4281 sc->bge_cdata.bge_tx_dmamap[i]); 4282 } 4283 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 4284 } 4285 4286 /* Destroy standard RX ring */ 4287 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag, 4288 sc->bge_cdata.bge_rx_std_ring_map, 4289 sc->bge_ldata.bge_rx_std_ring); 4290 4291 if (BGE_IS_JUMBO_CAPABLE(sc)) 4292 bge_free_jumbo_mem(sc); 4293 4294 /* Destroy RX return ring */ 4295 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag, 4296 sc->bge_cdata.bge_rx_return_ring_map, 4297 sc->bge_ldata.bge_rx_return_ring); 4298 4299 /* Destroy TX ring */ 4300 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag, 4301 sc->bge_cdata.bge_tx_ring_map, 4302 sc->bge_ldata.bge_tx_ring); 4303 4304 /* Destroy status block */ 4305 bge_dma_block_free(sc->bge_cdata.bge_status_tag, 4306 sc->bge_cdata.bge_status_map, 4307 sc->bge_ldata.bge_status_block); 4308 4309 /* Destroy statistics block */ 4310 bge_dma_block_free(sc->bge_cdata.bge_stats_tag, 4311 sc->bge_cdata.bge_stats_map, 4312 sc->bge_ldata.bge_stats); 4313 4314 /* Destroy the parent tag */ 4315 if (sc->bge_cdata.bge_parent_tag != NULL) 4316 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 4317 } 4318 4319 static int 4320 bge_dma_alloc(struct bge_softc *sc) 4321 { 4322 struct ifnet *ifp = &sc->arpcom.ac_if; 4323 int i, error; 4324 bus_addr_t lowaddr; 4325 bus_size_t txmaxsz; 4326 4327 lowaddr = BUS_SPACE_MAXADDR; 4328 if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) 4329 lowaddr = BGE_DMA_MAXADDR_40BIT; 4330 4331 /* 4332 * Allocate the parent bus DMA tag appropriate for PCI. 4333 * 4334 * All of the NetExtreme/NetLink controllers have 4GB boundary 4335 * DMA bug. 4336 * Whenever an address crosses a multiple of the 4GB boundary 4337 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 4338 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 4339 * state machine will lockup and cause the device to hang. 4340 */ 4341 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G, 4342 lowaddr, BUS_SPACE_MAXADDR, 4343 NULL, NULL, 4344 BUS_SPACE_MAXSIZE_32BIT, 0, 4345 BUS_SPACE_MAXSIZE_32BIT, 4346 0, &sc->bge_cdata.bge_parent_tag); 4347 if (error) { 4348 if_printf(ifp, "could not allocate parent dma tag\n"); 4349 return error; 4350 } 4351 4352 /* 4353 * Create DMA tag and maps for RX mbufs. 4354 */ 4355 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 4356 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4357 NULL, NULL, MCLBYTES, 1, MCLBYTES, 4358 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 4359 &sc->bge_cdata.bge_rx_mtag); 4360 if (error) { 4361 if_printf(ifp, "could not allocate RX mbuf dma tag\n"); 4362 return error; 4363 } 4364 4365 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 4366 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap); 4367 if (error) { 4368 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4369 sc->bge_cdata.bge_rx_mtag = NULL; 4370 return error; 4371 } 4372 4373 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4374 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 4375 BUS_DMA_WAITOK, 4376 &sc->bge_cdata.bge_rx_std_dmamap[i]); 4377 if (error) { 4378 int j; 4379 4380 for (j = 0; j < i; ++j) { 4381 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4382 sc->bge_cdata.bge_rx_std_dmamap[j]); 4383 } 4384 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4385 sc->bge_cdata.bge_rx_mtag = NULL; 4386 4387 if_printf(ifp, "could not create DMA map for RX\n"); 4388 return error; 4389 } 4390 } 4391 4392 /* 4393 * Create DMA tag and maps for TX mbufs. 4394 */ 4395 if (sc->bge_flags & BGE_FLAG_TSO) 4396 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header); 4397 else 4398 txmaxsz = BGE_JUMBO_FRAMELEN; 4399 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 4400 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4401 NULL, NULL, 4402 txmaxsz, BGE_NSEG_NEW, PAGE_SIZE, 4403 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 4404 BUS_DMA_ONEBPAGE, 4405 &sc->bge_cdata.bge_tx_mtag); 4406 if (error) { 4407 if_printf(ifp, "could not allocate TX mbuf dma tag\n"); 4408 return error; 4409 } 4410 4411 for (i = 0; i < BGE_TX_RING_CNT; i++) { 4412 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 4413 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 4414 &sc->bge_cdata.bge_tx_dmamap[i]); 4415 if (error) { 4416 int j; 4417 4418 for (j = 0; j < i; ++j) { 4419 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 4420 sc->bge_cdata.bge_tx_dmamap[j]); 4421 } 4422 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 4423 sc->bge_cdata.bge_tx_mtag = NULL; 4424 4425 if_printf(ifp, "could not create DMA map for TX\n"); 4426 return error; 4427 } 4428 } 4429 4430 /* 4431 * Create DMA stuffs for standard RX ring. 4432 */ 4433 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ, 4434 &sc->bge_cdata.bge_rx_std_ring_tag, 4435 &sc->bge_cdata.bge_rx_std_ring_map, 4436 (void *)&sc->bge_ldata.bge_rx_std_ring, 4437 &sc->bge_ldata.bge_rx_std_ring_paddr); 4438 if (error) { 4439 if_printf(ifp, "could not create std RX ring\n"); 4440 return error; 4441 } 4442 4443 /* 4444 * Create jumbo buffer pool. 4445 */ 4446 if (BGE_IS_JUMBO_CAPABLE(sc)) { 4447 error = bge_alloc_jumbo_mem(sc); 4448 if (error) { 4449 if_printf(ifp, "could not create jumbo buffer pool\n"); 4450 return error; 4451 } 4452 } 4453 4454 /* 4455 * Create DMA stuffs for RX return ring. 4456 */ 4457 error = bge_dma_block_alloc(sc, 4458 BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt), 4459 &sc->bge_cdata.bge_rx_return_ring_tag, 4460 &sc->bge_cdata.bge_rx_return_ring_map, 4461 (void *)&sc->bge_ldata.bge_rx_return_ring, 4462 &sc->bge_ldata.bge_rx_return_ring_paddr); 4463 if (error) { 4464 if_printf(ifp, "could not create RX ret ring\n"); 4465 return error; 4466 } 4467 4468 /* 4469 * Create DMA stuffs for TX ring. 4470 */ 4471 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ, 4472 &sc->bge_cdata.bge_tx_ring_tag, 4473 &sc->bge_cdata.bge_tx_ring_map, 4474 (void *)&sc->bge_ldata.bge_tx_ring, 4475 &sc->bge_ldata.bge_tx_ring_paddr); 4476 if (error) { 4477 if_printf(ifp, "could not create TX ring\n"); 4478 return error; 4479 } 4480 4481 /* 4482 * Create DMA stuffs for status block. 4483 */ 4484 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ, 4485 &sc->bge_cdata.bge_status_tag, 4486 &sc->bge_cdata.bge_status_map, 4487 (void *)&sc->bge_ldata.bge_status_block, 4488 &sc->bge_ldata.bge_status_block_paddr); 4489 if (error) { 4490 if_printf(ifp, "could not create status block\n"); 4491 return error; 4492 } 4493 4494 /* 4495 * Create DMA stuffs for statistics block. 4496 */ 4497 error = bge_dma_block_alloc(sc, BGE_STATS_SZ, 4498 &sc->bge_cdata.bge_stats_tag, 4499 &sc->bge_cdata.bge_stats_map, 4500 (void *)&sc->bge_ldata.bge_stats, 4501 &sc->bge_ldata.bge_stats_paddr); 4502 if (error) { 4503 if_printf(ifp, "could not create stats block\n"); 4504 return error; 4505 } 4506 return 0; 4507 } 4508 4509 static int 4510 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag, 4511 bus_dmamap_t *map, void **addr, bus_addr_t *paddr) 4512 { 4513 bus_dmamem_t dmem; 4514 int error; 4515 4516 error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0, 4517 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4518 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 4519 if (error) 4520 return error; 4521 4522 *tag = dmem.dmem_tag; 4523 *map = dmem.dmem_map; 4524 *addr = dmem.dmem_addr; 4525 *paddr = dmem.dmem_busaddr; 4526 4527 return 0; 4528 } 4529 4530 static void 4531 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr) 4532 { 4533 if (tag != NULL) { 4534 bus_dmamap_unload(tag, map); 4535 bus_dmamem_free(tag, addr, map); 4536 bus_dma_tag_destroy(tag); 4537 } 4538 } 4539 4540 /* 4541 * Grrr. The link status word in the status block does 4542 * not work correctly on the BCM5700 rev AX and BX chips, 4543 * according to all available information. Hence, we have 4544 * to enable MII interrupts in order to properly obtain 4545 * async link changes. Unfortunately, this also means that 4546 * we have to read the MAC status register to detect link 4547 * changes, thereby adding an additional register access to 4548 * the interrupt handler. 4549 * 4550 * XXX: perhaps link state detection procedure used for 4551 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4552 */ 4553 static void 4554 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused) 4555 { 4556 struct ifnet *ifp = &sc->arpcom.ac_if; 4557 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4558 4559 mii_pollstat(mii); 4560 4561 if (!sc->bge_link && 4562 (mii->mii_media_status & IFM_ACTIVE) && 4563 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4564 sc->bge_link++; 4565 if (bootverbose) 4566 if_printf(ifp, "link UP\n"); 4567 } else if (sc->bge_link && 4568 (!(mii->mii_media_status & IFM_ACTIVE) || 4569 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4570 sc->bge_link = 0; 4571 if (bootverbose) 4572 if_printf(ifp, "link DOWN\n"); 4573 } 4574 4575 /* Clear the interrupt. */ 4576 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT); 4577 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4578 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS); 4579 } 4580 4581 static void 4582 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status) 4583 { 4584 struct ifnet *ifp = &sc->arpcom.ac_if; 4585 4586 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE) 4587 4588 /* 4589 * Sometimes PCS encoding errors are detected in 4590 * TBI mode (on fiber NICs), and for some reason 4591 * the chip will signal them as link changes. 4592 * If we get a link change event, but the 'PCS 4593 * encoding error' bit in the MAC status register 4594 * is set, don't bother doing a link check. 4595 * This avoids spurious "gigabit link up" messages 4596 * that sometimes appear on fiber NICs during 4597 * periods of heavy traffic. 4598 */ 4599 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4600 if (!sc->bge_link) { 4601 sc->bge_link++; 4602 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4603 BGE_CLRBIT(sc, BGE_MAC_MODE, 4604 BGE_MACMODE_TBI_SEND_CFGS); 4605 DELAY(40); 4606 } 4607 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4608 4609 if (bootverbose) 4610 if_printf(ifp, "link UP\n"); 4611 4612 ifp->if_link_state = LINK_STATE_UP; 4613 if_link_state_change(ifp); 4614 } 4615 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) { 4616 if (sc->bge_link) { 4617 sc->bge_link = 0; 4618 4619 if (bootverbose) 4620 if_printf(ifp, "link DOWN\n"); 4621 4622 ifp->if_link_state = LINK_STATE_DOWN; 4623 if_link_state_change(ifp); 4624 } 4625 } 4626 4627 #undef PCS_ENCODE_ERR 4628 4629 /* Clear the attention. */ 4630 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4631 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4632 BGE_MACSTAT_LINK_CHANGED); 4633 } 4634 4635 static void 4636 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused) 4637 { 4638 struct ifnet *ifp = &sc->arpcom.ac_if; 4639 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4640 4641 mii_pollstat(mii); 4642 bge_miibus_statchg(sc->bge_dev); 4643 4644 if (bootverbose) { 4645 if (sc->bge_link) 4646 if_printf(ifp, "link UP\n"); 4647 else 4648 if_printf(ifp, "link DOWN\n"); 4649 } 4650 4651 /* Clear the attention. */ 4652 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4653 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4654 BGE_MACSTAT_LINK_CHANGED); 4655 } 4656 4657 static void 4658 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused) 4659 { 4660 struct ifnet *ifp = &sc->arpcom.ac_if; 4661 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4662 4663 mii_pollstat(mii); 4664 4665 if (!sc->bge_link && 4666 (mii->mii_media_status & IFM_ACTIVE) && 4667 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4668 sc->bge_link++; 4669 if (bootverbose) 4670 if_printf(ifp, "link UP\n"); 4671 } else if (sc->bge_link && 4672 (!(mii->mii_media_status & IFM_ACTIVE) || 4673 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4674 sc->bge_link = 0; 4675 if (bootverbose) 4676 if_printf(ifp, "link DOWN\n"); 4677 } 4678 4679 /* Clear the attention. */ 4680 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4681 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4682 BGE_MACSTAT_LINK_CHANGED); 4683 } 4684 4685 static int 4686 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS) 4687 { 4688 struct bge_softc *sc = arg1; 4689 4690 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4691 &sc->bge_rx_coal_ticks, 4692 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX, 4693 BGE_RX_COAL_TICKS_CHG); 4694 } 4695 4696 static int 4697 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS) 4698 { 4699 struct bge_softc *sc = arg1; 4700 4701 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4702 &sc->bge_tx_coal_ticks, 4703 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX, 4704 BGE_TX_COAL_TICKS_CHG); 4705 } 4706 4707 static int 4708 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS) 4709 { 4710 struct bge_softc *sc = arg1; 4711 4712 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4713 &sc->bge_rx_coal_bds, 4714 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX, 4715 BGE_RX_COAL_BDS_CHG); 4716 } 4717 4718 static int 4719 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS) 4720 { 4721 struct bge_softc *sc = arg1; 4722 4723 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4724 &sc->bge_tx_coal_bds, 4725 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX, 4726 BGE_TX_COAL_BDS_CHG); 4727 } 4728 4729 static int 4730 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS) 4731 { 4732 struct bge_softc *sc = arg1; 4733 4734 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4735 &sc->bge_rx_coal_ticks_int, 4736 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX, 4737 BGE_RX_COAL_TICKS_INT_CHG); 4738 } 4739 4740 static int 4741 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS) 4742 { 4743 struct bge_softc *sc = arg1; 4744 4745 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4746 &sc->bge_tx_coal_ticks_int, 4747 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX, 4748 BGE_TX_COAL_TICKS_INT_CHG); 4749 } 4750 4751 static int 4752 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4753 { 4754 struct bge_softc *sc = arg1; 4755 4756 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4757 &sc->bge_rx_coal_bds_int, 4758 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX, 4759 BGE_RX_COAL_BDS_INT_CHG); 4760 } 4761 4762 static int 4763 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4764 { 4765 struct bge_softc *sc = arg1; 4766 4767 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4768 &sc->bge_tx_coal_bds_int, 4769 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX, 4770 BGE_TX_COAL_BDS_INT_CHG); 4771 } 4772 4773 static int 4774 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal, 4775 int coal_min, int coal_max, uint32_t coal_chg_mask) 4776 { 4777 struct bge_softc *sc = arg1; 4778 struct ifnet *ifp = &sc->arpcom.ac_if; 4779 int error = 0, v; 4780 4781 lwkt_serialize_enter(ifp->if_serializer); 4782 4783 v = *coal; 4784 error = sysctl_handle_int(oidp, &v, 0, req); 4785 if (!error && req->newptr != NULL) { 4786 if (v < coal_min || v > coal_max) { 4787 error = EINVAL; 4788 } else { 4789 *coal = v; 4790 sc->bge_coal_chg |= coal_chg_mask; 4791 } 4792 } 4793 4794 lwkt_serialize_exit(ifp->if_serializer); 4795 return error; 4796 } 4797 4798 static void 4799 bge_coal_change(struct bge_softc *sc) 4800 { 4801 struct ifnet *ifp = &sc->arpcom.ac_if; 4802 4803 ASSERT_SERIALIZED(ifp->if_serializer); 4804 4805 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) { 4806 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 4807 sc->bge_rx_coal_ticks); 4808 DELAY(10); 4809 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4810 4811 if (bootverbose) { 4812 if_printf(ifp, "rx_coal_ticks -> %u\n", 4813 sc->bge_rx_coal_ticks); 4814 } 4815 } 4816 4817 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) { 4818 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 4819 sc->bge_tx_coal_ticks); 4820 DELAY(10); 4821 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS); 4822 4823 if (bootverbose) { 4824 if_printf(ifp, "tx_coal_ticks -> %u\n", 4825 sc->bge_tx_coal_ticks); 4826 } 4827 } 4828 4829 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) { 4830 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 4831 sc->bge_rx_coal_bds); 4832 DELAY(10); 4833 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4834 4835 if (bootverbose) { 4836 if_printf(ifp, "rx_coal_bds -> %u\n", 4837 sc->bge_rx_coal_bds); 4838 } 4839 } 4840 4841 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) { 4842 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 4843 sc->bge_tx_coal_bds); 4844 DELAY(10); 4845 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS); 4846 4847 if (bootverbose) { 4848 if_printf(ifp, "tx_max_coal_bds -> %u\n", 4849 sc->bge_tx_coal_bds); 4850 } 4851 } 4852 4853 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) { 4854 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 4855 sc->bge_rx_coal_ticks_int); 4856 DELAY(10); 4857 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT); 4858 4859 if (bootverbose) { 4860 if_printf(ifp, "rx_coal_ticks_int -> %u\n", 4861 sc->bge_rx_coal_ticks_int); 4862 } 4863 } 4864 4865 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) { 4866 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 4867 sc->bge_tx_coal_ticks_int); 4868 DELAY(10); 4869 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT); 4870 4871 if (bootverbose) { 4872 if_printf(ifp, "tx_coal_ticks_int -> %u\n", 4873 sc->bge_tx_coal_ticks_int); 4874 } 4875 } 4876 4877 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) { 4878 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 4879 sc->bge_rx_coal_bds_int); 4880 DELAY(10); 4881 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT); 4882 4883 if (bootverbose) { 4884 if_printf(ifp, "rx_coal_bds_int -> %u\n", 4885 sc->bge_rx_coal_bds_int); 4886 } 4887 } 4888 4889 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) { 4890 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 4891 sc->bge_tx_coal_bds_int); 4892 DELAY(10); 4893 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT); 4894 4895 if (bootverbose) { 4896 if_printf(ifp, "tx_coal_bds_int -> %u\n", 4897 sc->bge_tx_coal_bds_int); 4898 } 4899 } 4900 4901 sc->bge_coal_chg = 0; 4902 } 4903 4904 static void 4905 bge_enable_intr(struct bge_softc *sc) 4906 { 4907 struct ifnet *ifp = &sc->arpcom.ac_if; 4908 4909 lwkt_serialize_handler_enable(ifp->if_serializer); 4910 4911 /* 4912 * Enable interrupt. 4913 */ 4914 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 4915 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 4916 /* XXX Linux driver */ 4917 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 4918 } 4919 4920 /* 4921 * Unmask the interrupt when we stop polling. 4922 */ 4923 PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL, 4924 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4925 4926 /* 4927 * Trigger another interrupt, since above writing 4928 * to interrupt mailbox0 may acknowledge pending 4929 * interrupt. 4930 */ 4931 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4932 } 4933 4934 static void 4935 bge_disable_intr(struct bge_softc *sc) 4936 { 4937 struct ifnet *ifp = &sc->arpcom.ac_if; 4938 4939 /* 4940 * Mask the interrupt when we start polling. 4941 */ 4942 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, 4943 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4944 4945 /* 4946 * Acknowledge possible asserted interrupt. 4947 */ 4948 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4949 4950 sc->bge_npoll.ifpc_stcount = 0; 4951 4952 lwkt_serialize_handler_disable(ifp->if_serializer); 4953 } 4954 4955 static int 4956 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4957 { 4958 uint32_t mac_addr; 4959 int ret = 1; 4960 4961 mac_addr = bge_readmem_ind(sc, 0x0c14); 4962 if ((mac_addr >> 16) == 0x484b) { 4963 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4964 ether_addr[1] = (uint8_t)mac_addr; 4965 mac_addr = bge_readmem_ind(sc, 0x0c18); 4966 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4967 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4968 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4969 ether_addr[5] = (uint8_t)mac_addr; 4970 ret = 0; 4971 } 4972 return ret; 4973 } 4974 4975 static int 4976 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4977 { 4978 int mac_offset = BGE_EE_MAC_OFFSET; 4979 4980 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4981 mac_offset = BGE_EE_MAC_OFFSET_5906; 4982 4983 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN); 4984 } 4985 4986 static int 4987 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4988 { 4989 if (sc->bge_flags & BGE_FLAG_NO_EEPROM) 4990 return 1; 4991 4992 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4993 ETHER_ADDR_LEN); 4994 } 4995 4996 static int 4997 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4998 { 4999 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5000 /* NOTE: Order is critical */ 5001 bge_get_eaddr_mem, 5002 bge_get_eaddr_nvram, 5003 bge_get_eaddr_eeprom, 5004 NULL 5005 }; 5006 const bge_eaddr_fcn_t *func; 5007 5008 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5009 if ((*func)(sc, eaddr) == 0) 5010 break; 5011 } 5012 return (*func == NULL ? ENXIO : 0); 5013 } 5014 5015 /* 5016 * NOTE: 'm' is not freed upon failure 5017 */ 5018 struct mbuf * 5019 bge_defrag_shortdma(struct mbuf *m) 5020 { 5021 struct mbuf *n; 5022 int found; 5023 5024 /* 5025 * If device receive two back-to-back send BDs with less than 5026 * or equal to 8 total bytes then the device may hang. The two 5027 * back-to-back send BDs must in the same frame for this failure 5028 * to occur. Scan mbuf chains and see whether two back-to-back 5029 * send BDs are there. If this is the case, allocate new mbuf 5030 * and copy the frame to workaround the silicon bug. 5031 */ 5032 for (n = m, found = 0; n != NULL; n = n->m_next) { 5033 if (n->m_len < 8) { 5034 found++; 5035 if (found > 1) 5036 break; 5037 continue; 5038 } 5039 found = 0; 5040 } 5041 5042 if (found > 1) 5043 n = m_defrag(m, MB_DONTWAIT); 5044 else 5045 n = m; 5046 return n; 5047 } 5048 5049 static void 5050 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5051 { 5052 int i; 5053 5054 BGE_CLRBIT(sc, reg, bit); 5055 for (i = 0; i < BGE_TIMEOUT; i++) { 5056 if ((CSR_READ_4(sc, reg) & bit) == 0) 5057 return; 5058 DELAY(100); 5059 } 5060 } 5061 5062 static void 5063 bge_link_poll(struct bge_softc *sc) 5064 { 5065 uint32_t status; 5066 5067 status = CSR_READ_4(sc, BGE_MAC_STS); 5068 if ((status & sc->bge_link_chg) || sc->bge_link_evt) { 5069 sc->bge_link_evt = 0; 5070 sc->bge_link_upd(sc, status); 5071 } 5072 } 5073 5074 static void 5075 bge_enable_msi(struct bge_softc *sc) 5076 { 5077 uint32_t msi_mode; 5078 5079 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE); 5080 msi_mode |= BGE_MSIMODE_ENABLE; 5081 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 5082 /* 5083 * According to all of the datasheets that are publicly 5084 * available, bit 5 of the MSI_MODE is defined to be 5085 * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on 5086 * which "oneshot MSI" is enabled. However, it is always 5087 * safe to clear it here. 5088 */ 5089 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE; 5090 } 5091 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode); 5092 } 5093 5094 static int 5095 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp, 5096 uint16_t *mss0, uint16_t *flags0) 5097 { 5098 struct mbuf *m; 5099 struct ip *ip; 5100 struct tcphdr *th; 5101 int thoff, iphlen, hoff, hlen; 5102 uint16_t flags, mss; 5103 5104 m = *mp; 5105 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 5106 5107 hoff = m->m_pkthdr.csum_lhlen; 5108 iphlen = m->m_pkthdr.csum_iphlen; 5109 thoff = m->m_pkthdr.csum_thlen; 5110 5111 KASSERT(hoff > 0, ("invalid ether header len")); 5112 KASSERT(iphlen > 0, ("invalid ip header len")); 5113 KASSERT(thoff > 0, ("invalid tcp header len")); 5114 5115 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 5116 m = m_pullup(m, hoff + iphlen + thoff); 5117 if (m == NULL) { 5118 *mp = NULL; 5119 return ENOBUFS; 5120 } 5121 *mp = m; 5122 } 5123 ip = mtodoff(m, struct ip *, hoff); 5124 th = mtodoff(m, struct tcphdr *, hoff + iphlen); 5125 5126 mss = m->m_pkthdr.tso_segsz; 5127 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA; 5128 5129 ip->ip_len = htons(mss + iphlen + thoff); 5130 th->th_sum = 0; 5131 5132 hlen = (iphlen + thoff) >> 2; 5133 mss |= (hlen << 11); 5134 5135 *mss0 = mss; 5136 *flags0 = flags; 5137 5138 return 0; 5139 } 5140 5141 static void 5142 bge_stop_fw(struct bge_softc *sc) 5143 { 5144 int i; 5145 5146 if (sc->bge_asf_mode) { 5147 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 5148 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 5149 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 5150 5151 for (i = 0; i < 100; i++ ) { 5152 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 5153 BGE_RX_CPU_DRV_EVENT)) 5154 break; 5155 DELAY(10); 5156 } 5157 } 5158 } 5159 5160 static void 5161 bge_sig_pre_reset(struct bge_softc *sc, int type) 5162 { 5163 /* 5164 * Some chips don't like this so only do this if ASF is enabled 5165 */ 5166 if (sc->bge_asf_mode) 5167 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 5168 5169 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 5170 switch (type) { 5171 case BGE_RESET_START: 5172 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5173 BGE_FW_DRV_STATE_START); 5174 break; 5175 case BGE_RESET_SHUTDOWN: 5176 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5177 BGE_FW_DRV_STATE_UNLOAD); 5178 break; 5179 case BGE_RESET_SUSPEND: 5180 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5181 BGE_FW_DRV_STATE_SUSPEND); 5182 break; 5183 } 5184 } 5185 5186 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 5187 bge_ape_driver_state_change(sc, type); 5188 } 5189 5190 static void 5191 bge_sig_legacy(struct bge_softc *sc, int type) 5192 { 5193 if (sc->bge_asf_mode) { 5194 switch (type) { 5195 case BGE_RESET_START: 5196 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5197 BGE_FW_DRV_STATE_START); 5198 break; 5199 case BGE_RESET_SHUTDOWN: 5200 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5201 BGE_FW_DRV_STATE_UNLOAD); 5202 break; 5203 } 5204 } 5205 } 5206 5207 static void 5208 bge_sig_post_reset(struct bge_softc *sc, int type) 5209 { 5210 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 5211 switch (type) { 5212 case BGE_RESET_START: 5213 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5214 BGE_FW_DRV_STATE_START_DONE); 5215 /* START DONE */ 5216 break; 5217 case BGE_RESET_SHUTDOWN: 5218 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5219 BGE_FW_DRV_STATE_UNLOAD_DONE); 5220 break; 5221 } 5222 } 5223 if (type == BGE_RESET_SHUTDOWN) 5224 bge_ape_driver_state_change(sc, type); 5225 } 5226 5227 static void 5228 bge_asf_driver_up(struct bge_softc *sc) 5229 { 5230 if (sc->bge_asf_mode & ASF_STACKUP) { 5231 /* Send ASF heartbeat aprox. every 2s */ 5232 if (sc->bge_asf_count) 5233 sc->bge_asf_count --; 5234 else { 5235 sc->bge_asf_count = 2; 5236 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 5237 BGE_FW_CMD_DRV_ALIVE); 5238 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 5239 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 5240 BGE_FW_HB_TIMEOUT_SEC); 5241 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 5242 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 5243 BGE_RX_CPU_DRV_EVENT); 5244 } 5245 } 5246 } 5247 5248 /* 5249 * Clear all stale locks and select the lock for this driver instance. 5250 */ 5251 static void 5252 bge_ape_lock_init(struct bge_softc *sc) 5253 { 5254 uint32_t bit, regbase; 5255 int i; 5256 5257 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 5258 regbase = BGE_APE_LOCK_GRANT; 5259 else 5260 regbase = BGE_APE_PER_LOCK_GRANT; 5261 5262 /* Clear any stale locks. */ 5263 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 5264 switch (i) { 5265 case BGE_APE_LOCK_PHY0: 5266 case BGE_APE_LOCK_PHY1: 5267 case BGE_APE_LOCK_PHY2: 5268 case BGE_APE_LOCK_PHY3: 5269 bit = BGE_APE_LOCK_GRANT_DRIVER0; 5270 break; 5271 default: 5272 if (sc->bge_func_addr == 0) 5273 bit = BGE_APE_LOCK_GRANT_DRIVER0; 5274 else 5275 bit = (1 << sc->bge_func_addr); 5276 } 5277 APE_WRITE_4(sc, regbase + 4 * i, bit); 5278 } 5279 5280 /* Select the PHY lock based on the device's function number. */ 5281 switch (sc->bge_func_addr) { 5282 case 0: 5283 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 5284 break; 5285 case 1: 5286 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 5287 break; 5288 case 2: 5289 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 5290 break; 5291 case 3: 5292 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 5293 break; 5294 default: 5295 device_printf(sc->bge_dev, 5296 "PHY lock not supported on this function\n"); 5297 } 5298 } 5299 5300 /* 5301 * Check for APE firmware, set flags, and print version info. 5302 */ 5303 static void 5304 bge_ape_read_fw_ver(struct bge_softc *sc) 5305 { 5306 const char *fwtype; 5307 uint32_t apedata, features; 5308 5309 /* Check for a valid APE signature in shared memory. */ 5310 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 5311 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 5312 device_printf(sc->bge_dev, "no APE signature\n"); 5313 sc->bge_mfw_flags &= ~BGE_MFW_ON_APE; 5314 return; 5315 } 5316 5317 /* Check if APE firmware is running. */ 5318 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 5319 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 5320 device_printf(sc->bge_dev, "APE signature found " 5321 "but FW status not ready! 0x%08x\n", apedata); 5322 return; 5323 } 5324 5325 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 5326 5327 /* Fetch the APE firwmare type and version. */ 5328 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 5329 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 5330 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 5331 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 5332 fwtype = "NCSI"; 5333 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 5334 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 5335 fwtype = "DASH"; 5336 } else 5337 fwtype = "UNKN"; 5338 5339 /* Print the APE firmware version. */ 5340 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 5341 fwtype, 5342 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 5343 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 5344 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 5345 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 5346 } 5347 5348 static int 5349 bge_ape_lock(struct bge_softc *sc, int locknum) 5350 { 5351 uint32_t bit, gnt, req, status; 5352 int i, off; 5353 5354 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 5355 return (0); 5356 5357 /* Lock request/grant registers have different bases. */ 5358 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 5359 req = BGE_APE_LOCK_REQ; 5360 gnt = BGE_APE_LOCK_GRANT; 5361 } else { 5362 req = BGE_APE_PER_LOCK_REQ; 5363 gnt = BGE_APE_PER_LOCK_GRANT; 5364 } 5365 5366 off = 4 * locknum; 5367 5368 switch (locknum) { 5369 case BGE_APE_LOCK_GPIO: 5370 /* Lock required when using GPIO. */ 5371 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 5372 return (0); 5373 if (sc->bge_func_addr == 0) 5374 bit = BGE_APE_LOCK_REQ_DRIVER0; 5375 else 5376 bit = (1 << sc->bge_func_addr); 5377 break; 5378 case BGE_APE_LOCK_GRC: 5379 /* Lock required to reset the device. */ 5380 if (sc->bge_func_addr == 0) 5381 bit = BGE_APE_LOCK_REQ_DRIVER0; 5382 else 5383 bit = (1 << sc->bge_func_addr); 5384 break; 5385 case BGE_APE_LOCK_MEM: 5386 /* Lock required when accessing certain APE memory. */ 5387 if (sc->bge_func_addr == 0) 5388 bit = BGE_APE_LOCK_REQ_DRIVER0; 5389 else 5390 bit = (1 << sc->bge_func_addr); 5391 break; 5392 case BGE_APE_LOCK_PHY0: 5393 case BGE_APE_LOCK_PHY1: 5394 case BGE_APE_LOCK_PHY2: 5395 case BGE_APE_LOCK_PHY3: 5396 /* Lock required when accessing PHYs. */ 5397 bit = BGE_APE_LOCK_REQ_DRIVER0; 5398 break; 5399 default: 5400 return (EINVAL); 5401 } 5402 5403 /* Request a lock. */ 5404 APE_WRITE_4(sc, req + off, bit); 5405 5406 /* Wait up to 1 second to acquire lock. */ 5407 for (i = 0; i < 20000; i++) { 5408 status = APE_READ_4(sc, gnt + off); 5409 if (status == bit) 5410 break; 5411 DELAY(50); 5412 } 5413 5414 /* Handle any errors. */ 5415 if (status != bit) { 5416 device_printf(sc->bge_dev, "APE lock %d request failed! " 5417 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 5418 locknum, req + off, bit & 0xFFFF, gnt + off, 5419 status & 0xFFFF); 5420 /* Revoke the lock request. */ 5421 APE_WRITE_4(sc, gnt + off, bit); 5422 return (EBUSY); 5423 } 5424 5425 return (0); 5426 } 5427 5428 static void 5429 bge_ape_unlock(struct bge_softc *sc, int locknum) 5430 { 5431 uint32_t bit, gnt; 5432 int off; 5433 5434 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 5435 return; 5436 5437 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 5438 gnt = BGE_APE_LOCK_GRANT; 5439 else 5440 gnt = BGE_APE_PER_LOCK_GRANT; 5441 5442 off = 4 * locknum; 5443 5444 switch (locknum) { 5445 case BGE_APE_LOCK_GPIO: 5446 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 5447 return; 5448 if (sc->bge_func_addr == 0) 5449 bit = BGE_APE_LOCK_GRANT_DRIVER0; 5450 else 5451 bit = (1 << sc->bge_func_addr); 5452 break; 5453 case BGE_APE_LOCK_GRC: 5454 if (sc->bge_func_addr == 0) 5455 bit = BGE_APE_LOCK_GRANT_DRIVER0; 5456 else 5457 bit = (1 << sc->bge_func_addr); 5458 break; 5459 case BGE_APE_LOCK_MEM: 5460 if (sc->bge_func_addr == 0) 5461 bit = BGE_APE_LOCK_GRANT_DRIVER0; 5462 else 5463 bit = (1 << sc->bge_func_addr); 5464 break; 5465 case BGE_APE_LOCK_PHY0: 5466 case BGE_APE_LOCK_PHY1: 5467 case BGE_APE_LOCK_PHY2: 5468 case BGE_APE_LOCK_PHY3: 5469 bit = BGE_APE_LOCK_GRANT_DRIVER0; 5470 break; 5471 default: 5472 return; 5473 } 5474 5475 APE_WRITE_4(sc, gnt + off, bit); 5476 } 5477 5478 /* 5479 * Send an event to the APE firmware. 5480 */ 5481 static void 5482 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 5483 { 5484 uint32_t apedata; 5485 int i; 5486 5487 /* NCSI does not support APE events. */ 5488 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 5489 return; 5490 5491 /* Wait up to 1ms for APE to service previous event. */ 5492 for (i = 10; i > 0; i--) { 5493 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 5494 break; 5495 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 5496 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 5497 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 5498 BGE_APE_EVENT_STATUS_EVENT_PENDING); 5499 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 5500 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 5501 break; 5502 } 5503 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 5504 DELAY(100); 5505 } 5506 if (i == 0) 5507 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 5508 event); 5509 } 5510 5511 static void 5512 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 5513 { 5514 uint32_t apedata, event; 5515 5516 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 5517 return; 5518 5519 switch (kind) { 5520 case BGE_RESET_START: 5521 /* If this is the first load, clear the load counter. */ 5522 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 5523 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 5524 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 5525 else { 5526 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 5527 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 5528 } 5529 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 5530 BGE_APE_HOST_SEG_SIG_MAGIC); 5531 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 5532 BGE_APE_HOST_SEG_LEN_MAGIC); 5533 5534 /* Add some version info if bge(4) supports it. */ 5535 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 5536 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 5537 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 5538 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 5539 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 5540 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 5541 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 5542 BGE_APE_HOST_DRVR_STATE_START); 5543 event = BGE_APE_EVENT_STATUS_STATE_START; 5544 break; 5545 case BGE_RESET_SHUTDOWN: 5546 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 5547 BGE_APE_HOST_DRVR_STATE_UNLOAD); 5548 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 5549 break; 5550 case BGE_RESET_SUSPEND: 5551 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 5552 break; 5553 default: 5554 return; 5555 } 5556 5557 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 5558 BGE_APE_EVENT_STATUS_STATE_CHNGE); 5559 } 5560