1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.13 2003/12/01 21:06:59 ambrisko Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.14 2006/08/12 05:17:03 swildner Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79 #define BGE_UNMAPPED 0x00001000 80 #define BGE_UNMAPPED_END 0x00001FFF 81 #define BGE_DMA_DESCRIPTORS 0x00002000 82 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83 #define BGE_SEND_RING_1_TO_4 0x00004000 84 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86 /* Mappings for internal memory configuration */ 87 #define BGE_STD_RX_RINGS 0x00006000 88 #define BGE_STD_RX_RINGS_END 0x00006FFF 89 #define BGE_JUMBO_RX_RINGS 0x00007000 90 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91 #define BGE_BUFFPOOL_1 0x00008000 92 #define BGE_BUFFPOOL_1_END 0x0000FFFF 93 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94 #define BGE_BUFFPOOL_2_END 0x00017FFF 95 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96 #define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98 /* Mappings for external SSRAM configurations */ 99 #define BGE_SEND_RING_5_TO_6 0x00006000 100 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101 #define BGE_SEND_RING_7_TO_8 0x00007000 102 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103 #define BGE_SEND_RING_9_TO_16 0x00008000 104 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105 #define BGE_EXT_STD_RX_RINGS 0x0000C000 106 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109 #define BGE_MINI_RX_RINGS 0x0000E000 110 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 111 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112 #define BGE_AVAIL_REGION1_END 0x00017FFF 113 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114 #define BGE_AVAIL_REGION2_END 0x0001FFFF 115 #define BGE_EXT_SSRAM 0x00020000 116 #define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119 /* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129 /* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132 #define BGE_PCI_VID 0x00 133 #define BGE_PCI_DID 0x02 134 #define BGE_PCI_CMD 0x04 135 #define BGE_PCI_STS 0x06 136 #define BGE_PCI_REV 0x08 137 #define BGE_PCI_CLASS 0x09 138 #define BGE_PCI_CACHESZ 0x0C 139 #define BGE_PCI_LATTIMER 0x0D 140 #define BGE_PCI_HDRTYPE 0x0E 141 #define BGE_PCI_BIST 0x0F 142 #define BGE_PCI_BAR0 0x10 143 #define BGE_PCI_BAR1 0x14 144 #define BGE_PCI_SUBSYS 0x2C 145 #define BGE_PCI_SUBVID 0x2E 146 #define BGE_PCI_ROMBASE 0x30 147 #define BGE_PCI_CAPPTR 0x34 148 #define BGE_PCI_INTLINE 0x3C 149 #define BGE_PCI_INTPIN 0x3D 150 #define BGE_PCI_MINGNT 0x3E 151 #define BGE_PCI_MAXLAT 0x3F 152 #define BGE_PCI_PCIXCAP 0x40 153 #define BGE_PCI_NEXTPTR_PM 0x41 154 #define BGE_PCI_PCIX_CMD 0x42 155 #define BGE_PCI_PCIX_STS 0x44 156 #define BGE_PCI_PWRMGMT_CAPID 0x48 157 #define BGE_PCI_NEXTPTR_VPD 0x49 158 #define BGE_PCI_PWRMGMT_CAPS 0x4A 159 #define BGE_PCI_PWRMGMT_CMD 0x4C 160 #define BGE_PCI_PWRMGMT_STS 0x4D 161 #define BGE_PCI_PWRMGMT_DATA 0x4F 162 #define BGE_PCI_VPD_CAPID 0x50 163 #define BGE_PCI_NEXTPTR_MSI 0x51 164 #define BGE_PCI_VPD_ADDR 0x52 165 #define BGE_PCI_VPD_DATA 0x54 166 #define BGE_PCI_MSI_CAPID 0x58 167 #define BGE_PCI_NEXTPTR_NONE 0x59 168 #define BGE_PCI_MSI_CTL 0x5A 169 #define BGE_PCI_MSI_ADDR_HI 0x5C 170 #define BGE_PCI_MSI_ADDR_LO 0x60 171 #define BGE_PCI_MSI_DATA 0x64 172 173 #define BGE_PCIE_MSI_CAPID 0xD0 174 #define BGE_PCIE_MSI_CAPID_VAL 0x10 175 176 /* 177 * PCI registers specific to the BCM570x family. 178 */ 179 #define BGE_PCI_MISC_CTL 0x68 180 #define BGE_PCI_DMA_RW_CTL 0x6C 181 #define BGE_PCI_PCISTATE 0x70 182 #define BGE_PCI_CLKCTL 0x74 183 #define BGE_PCI_REG_BASEADDR 0x78 184 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 185 #define BGE_PCI_REG_DATA 0x80 186 #define BGE_PCI_MEMWIN_DATA 0x84 187 #define BGE_PCI_MODECTL 0x88 188 #define BGE_PCI_MISC_CFG 0x8C 189 #define BGE_PCI_MISC_LOCALCTL 0x90 190 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 191 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 192 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 193 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 194 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 195 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 196 #define BGE_PCI_ISR_MBX_HI 0xB0 197 #define BGE_PCI_ISR_MBX_LO 0xB4 198 199 /* PCI Misc. Host control register */ 200 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 201 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 202 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 203 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 204 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 205 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 206 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 207 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 208 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 209 210 #define BGE_BIGENDIAN_INIT \ 211 (BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 212 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 213 BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR) 214 215 #define BGE_LITTLEENDIAN_INIT \ 216 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 217 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 218 219 #define BGE_CHIPID_TIGON_I 0x40000000 220 #define BGE_CHIPID_TIGON_II 0x60000000 221 #define BGE_CHIPID_BCM5700_B0 0x71000000 222 #define BGE_CHIPID_BCM5700_B1 0x71020000 223 #define BGE_CHIPID_BCM5700_B2 0x71030000 224 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 225 #define BGE_CHIPID_BCM5700_C0 0x72000000 226 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 227 #define BGE_CHIPID_BCM5701_B0 0x01000000 228 #define BGE_CHIPID_BCM5701_B2 0x01020000 229 #define BGE_CHIPID_BCM5701_B5 0x01050000 230 #define BGE_CHIPID_BCM5703_A0 0x10000000 231 #define BGE_CHIPID_BCM5703_A1 0x10010000 232 #define BGE_CHIPID_BCM5703_A2 0x10020000 233 #define BGE_CHIPID_BCM5704_A0 0x20000000 234 #define BGE_CHIPID_BCM5704_A1 0x20010000 235 #define BGE_CHIPID_BCM5704_A2 0x20020000 236 #define BGE_CHIPID_BCM5705_A0 0x30000000 237 #define BGE_CHIPID_BCM5705_A1 0x30010000 238 #define BGE_CHIPID_BCM5705_A2 0x30020000 239 #define BGE_CHIPID_BCM5705_A3 0x30030000 240 #define BGE_CHIPID_BCM5750_A0 0x40000000 241 #define BGE_CHIPID_BCM5750_A1 0x40010000 242 #define BGE_CHIPID_BCM5714_A0 0x50000000 243 244 /* shorthand one */ 245 #define BGE_ASICREV(x) ((x) >> 28) 246 #define BGE_ASICREV_BCM5700 0x07 247 #define BGE_ASICREV_BCM5701 0x00 248 #define BGE_ASICREV_BCM5703 0x01 249 #define BGE_ASICREV_BCM5704 0x02 250 #define BGE_ASICREV_BCM5705 0x03 251 #define BGE_ASICREV_BCM5750 0x04 252 #define BGE_ASICREV_BCM5714 0x05 253 254 /* chip revisions */ 255 #define BGE_CHIPREV(x) ((x) >> 24) 256 #define BGE_CHIPREV_5700_AX 0x70 257 #define BGE_CHIPREV_5700_BX 0x71 258 #define BGE_CHIPREV_5700_CX 0x72 259 #define BGE_CHIPREV_5701_AX 0x00 260 261 /* PCI DMA Read/Write Control register */ 262 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 263 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 264 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 265 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 266 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 267 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 268 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 269 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 270 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 271 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 272 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 273 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 274 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 275 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 276 277 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 278 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 279 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 280 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 281 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 282 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 283 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 284 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 285 286 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 287 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 288 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 289 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 290 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 291 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 292 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 293 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 294 295 /* 296 * PCI state register -- note, this register is read only 297 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 298 * register is set. 299 */ 300 #define BGE_PCISTATE_FORCE_RESET 0x00000001 301 #define BGE_PCISTATE_INTR_STATE 0x00000002 302 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 303 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 304 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 305 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 306 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 307 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 308 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 309 310 /* 311 * PCI Clock Control register -- note, this register is read only 312 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 313 * register is set. 314 */ 315 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 316 #define BGE_PCICLOCKCTL_M66EN 0x00000080 317 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 318 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 319 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 320 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 321 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 322 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 323 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 324 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 325 326 327 #ifndef PCIM_CMD_MWIEN 328 #define PCIM_CMD_MWIEN 0x0010 329 #endif 330 331 /* 332 * High priority mailbox registers 333 * Each mailbox is 64-bits wide, though we only use the 334 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 335 * first. The NIC will load the mailbox after the lower 32 bit word 336 * has been updated. 337 */ 338 #define BGE_MBX_IRQ0_HI 0x0200 339 #define BGE_MBX_IRQ0_LO 0x0204 340 #define BGE_MBX_IRQ1_HI 0x0208 341 #define BGE_MBX_IRQ1_LO 0x020C 342 #define BGE_MBX_IRQ2_HI 0x0210 343 #define BGE_MBX_IRQ2_LO 0x0214 344 #define BGE_MBX_IRQ3_HI 0x0218 345 #define BGE_MBX_IRQ3_LO 0x021C 346 #define BGE_MBX_GEN0_HI 0x0220 347 #define BGE_MBX_GEN0_LO 0x0224 348 #define BGE_MBX_GEN1_HI 0x0228 349 #define BGE_MBX_GEN1_LO 0x022C 350 #define BGE_MBX_GEN2_HI 0x0230 351 #define BGE_MBX_GEN2_LO 0x0234 352 #define BGE_MBX_GEN3_HI 0x0228 353 #define BGE_MBX_GEN3_LO 0x022C 354 #define BGE_MBX_GEN4_HI 0x0240 355 #define BGE_MBX_GEN4_LO 0x0244 356 #define BGE_MBX_GEN5_HI 0x0248 357 #define BGE_MBX_GEN5_LO 0x024C 358 #define BGE_MBX_GEN6_HI 0x0250 359 #define BGE_MBX_GEN6_LO 0x0254 360 #define BGE_MBX_GEN7_HI 0x0258 361 #define BGE_MBX_GEN7_LO 0x025C 362 #define BGE_MBX_RELOAD_STATS_HI 0x0260 363 #define BGE_MBX_RELOAD_STATS_LO 0x0264 364 #define BGE_MBX_RX_STD_PROD_HI 0x0268 365 #define BGE_MBX_RX_STD_PROD_LO 0x026C 366 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 367 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 368 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 369 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 370 #define BGE_MBX_RX_CONS0_HI 0x0280 371 #define BGE_MBX_RX_CONS0_LO 0x0284 372 #define BGE_MBX_RX_CONS1_HI 0x0288 373 #define BGE_MBX_RX_CONS1_LO 0x028C 374 #define BGE_MBX_RX_CONS2_HI 0x0290 375 #define BGE_MBX_RX_CONS2_LO 0x0294 376 #define BGE_MBX_RX_CONS3_HI 0x0298 377 #define BGE_MBX_RX_CONS3_LO 0x029C 378 #define BGE_MBX_RX_CONS4_HI 0x02A0 379 #define BGE_MBX_RX_CONS4_LO 0x02A4 380 #define BGE_MBX_RX_CONS5_HI 0x02A8 381 #define BGE_MBX_RX_CONS5_LO 0x02AC 382 #define BGE_MBX_RX_CONS6_HI 0x02B0 383 #define BGE_MBX_RX_CONS6_LO 0x02B4 384 #define BGE_MBX_RX_CONS7_HI 0x02B8 385 #define BGE_MBX_RX_CONS7_LO 0x02BC 386 #define BGE_MBX_RX_CONS8_HI 0x02C0 387 #define BGE_MBX_RX_CONS8_LO 0x02C4 388 #define BGE_MBX_RX_CONS9_HI 0x02C8 389 #define BGE_MBX_RX_CONS9_LO 0x02CC 390 #define BGE_MBX_RX_CONS10_HI 0x02D0 391 #define BGE_MBX_RX_CONS10_LO 0x02D4 392 #define BGE_MBX_RX_CONS11_HI 0x02D8 393 #define BGE_MBX_RX_CONS11_LO 0x02DC 394 #define BGE_MBX_RX_CONS12_HI 0x02E0 395 #define BGE_MBX_RX_CONS12_LO 0x02E4 396 #define BGE_MBX_RX_CONS13_HI 0x02E8 397 #define BGE_MBX_RX_CONS13_LO 0x02EC 398 #define BGE_MBX_RX_CONS14_HI 0x02F0 399 #define BGE_MBX_RX_CONS14_LO 0x02F4 400 #define BGE_MBX_RX_CONS15_HI 0x02F8 401 #define BGE_MBX_RX_CONS15_LO 0x02FC 402 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 403 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 404 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 405 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 406 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 407 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 408 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 409 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 410 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 411 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 412 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 413 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 414 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 415 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 416 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 417 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 418 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 419 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 420 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 421 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 422 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 423 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 424 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 425 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 426 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 427 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 428 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 429 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 430 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 431 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 432 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 433 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 434 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 435 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 436 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 437 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 438 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 439 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 440 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 441 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 442 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 443 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 444 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 445 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 446 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 447 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 448 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 449 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 450 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 451 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 452 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 453 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 454 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 455 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 456 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 457 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 458 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 459 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 460 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 461 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 462 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 463 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 464 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 465 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 466 467 #define BGE_TX_RINGS_MAX 4 468 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 469 #define BGE_RX_RINGS_MAX 16 470 471 /* Ethernet MAC control registers */ 472 #define BGE_MAC_MODE 0x0400 473 #define BGE_MAC_STS 0x0404 474 #define BGE_MAC_EVT_ENB 0x0408 475 #define BGE_MAC_LED_CTL 0x040C 476 #define BGE_MAC_ADDR1_LO 0x0410 477 #define BGE_MAC_ADDR1_HI 0x0414 478 #define BGE_MAC_ADDR2_LO 0x0418 479 #define BGE_MAC_ADDR2_HI 0x041C 480 #define BGE_MAC_ADDR3_LO 0x0420 481 #define BGE_MAC_ADDR3_HI 0x0424 482 #define BGE_MAC_ADDR4_LO 0x0428 483 #define BGE_MAC_ADDR4_HI 0x042C 484 #define BGE_WOL_PATPTR 0x0430 485 #define BGE_WOL_PATCFG 0x0434 486 #define BGE_TX_RANDOM_BACKOFF 0x0438 487 #define BGE_RX_MTU 0x043C 488 #define BGE_GBIT_PCS_TEST 0x0440 489 #define BGE_TX_TBI_AUTONEG 0x0444 490 #define BGE_RX_TBI_AUTONEG 0x0448 491 #define BGE_MI_COMM 0x044C 492 #define BGE_MI_STS 0x0450 493 #define BGE_MI_MODE 0x0454 494 #define BGE_AUTOPOLL_STS 0x0458 495 #define BGE_TX_MODE 0x045C 496 #define BGE_TX_STS 0x0460 497 #define BGE_TX_LENGTHS 0x0464 498 #define BGE_RX_MODE 0x0468 499 #define BGE_RX_STS 0x046C 500 #define BGE_MAR0 0x0470 501 #define BGE_MAR1 0x0474 502 #define BGE_MAR2 0x0478 503 #define BGE_MAR3 0x047C 504 #define BGE_RX_BD_RULES_CTL0 0x0480 505 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 506 #define BGE_RX_BD_RULES_CTL1 0x0488 507 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 508 #define BGE_RX_BD_RULES_CTL2 0x0490 509 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 510 #define BGE_RX_BD_RULES_CTL3 0x0498 511 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 512 #define BGE_RX_BD_RULES_CTL4 0x04A0 513 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 514 #define BGE_RX_BD_RULES_CTL5 0x04A8 515 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 516 #define BGE_RX_BD_RULES_CTL6 0x04B0 517 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 518 #define BGE_RX_BD_RULES_CTL7 0x04B8 519 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 520 #define BGE_RX_BD_RULES_CTL8 0x04C0 521 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 522 #define BGE_RX_BD_RULES_CTL9 0x04C8 523 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 524 #define BGE_RX_BD_RULES_CTL10 0x04D0 525 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 526 #define BGE_RX_BD_RULES_CTL11 0x04D8 527 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 528 #define BGE_RX_BD_RULES_CTL12 0x04E0 529 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 530 #define BGE_RX_BD_RULES_CTL13 0x04E8 531 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 532 #define BGE_RX_BD_RULES_CTL14 0x04F0 533 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 534 #define BGE_RX_BD_RULES_CTL15 0x04F8 535 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 536 #define BGE_RX_RULES_CFG 0x0500 537 #define BGE_SERDES_CFG 0x0590 538 #define BGE_SERDES_STS 0x0594 539 #define BGE_SGDIG_CFG 0x05B0 540 #define BGE_SGDIG_STS 0x05B4 541 #define BGE_RX_STATS 0x0800 542 #define BGE_TX_STATS 0x0880 543 544 /* Ethernet MAC Mode register */ 545 #define BGE_MACMODE_RESET 0x00000001 546 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 547 #define BGE_MACMODE_PORTMODE 0x0000000C 548 #define BGE_MACMODE_LOOPBACK 0x00000010 549 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 550 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 551 #define BGE_MACMODE_MAX_DEFER 0x00000200 552 #define BGE_MACMODE_LINK_POLARITY 0x00000400 553 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 554 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 555 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 556 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 557 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 558 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 559 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 560 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 561 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 562 #define BGE_MACMODE_MIP_ENB 0x00100000 563 #define BGE_MACMODE_TXDMA_ENB 0x00200000 564 #define BGE_MACMODE_RXDMA_ENB 0x00400000 565 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 566 567 #define BGE_PORTMODE_NONE 0x00000000 568 #define BGE_PORTMODE_MII 0x00000004 569 #define BGE_PORTMODE_GMII 0x00000008 570 #define BGE_PORTMODE_TBI 0x0000000C 571 572 /* MAC Status register */ 573 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 574 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 575 #define BGE_MACSTAT_RX_CFG 0x00000004 576 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 577 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 578 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 579 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 580 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 581 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 582 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 583 #define BGE_MACSTAT_ODI_ERROR 0x02000000 584 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 585 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 586 587 /* MAC Event Enable Register */ 588 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 589 #define BGE_EVTENB_LINK_CHANGED 0x00001000 590 #define BGE_EVTENB_MI_COMPLETE 0x00400000 591 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 592 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 593 #define BGE_EVTENB_ODI_ERROR 0x02000000 594 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 595 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 596 597 /* LED Control Register */ 598 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 599 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 600 #define BGE_LEDCTL_100MBPS_LED 0x00000004 601 #define BGE_LEDCTL_10MBPS_LED 0x00000008 602 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 603 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 604 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 605 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 606 #define BGE_LEDCTL_100MBPS_STS 0x00000100 607 #define BGE_LEDCTL_10MBPS_STS 0x00000200 608 #define BGE_LEDCTL_TRADLED_STS 0x00000400 609 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 610 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 611 612 /* TX backoff seed register */ 613 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 614 615 /* Autopoll status register */ 616 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 617 618 /* Transmit MAC mode register */ 619 #define BGE_TXMODE_RESET 0x00000001 620 #define BGE_TXMODE_ENABLE 0x00000002 621 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 622 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 623 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 624 625 /* Transmit MAC status register */ 626 #define BGE_TXSTAT_RX_XOFFED 0x00000001 627 #define BGE_TXSTAT_SENT_XOFF 0x00000002 628 #define BGE_TXSTAT_SENT_XON 0x00000004 629 #define BGE_TXSTAT_LINK_UP 0x00000008 630 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 631 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 632 633 /* Transmit MAC lengths register */ 634 #define BGE_TXLEN_SLOTTIME 0x000000FF 635 #define BGE_TXLEN_IPG 0x00000F00 636 #define BGE_TXLEN_CRS 0x00003000 637 638 /* Receive MAC mode register */ 639 #define BGE_RXMODE_RESET 0x00000001 640 #define BGE_RXMODE_ENABLE 0x00000002 641 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 642 #define BGE_RXMODE_RX_GIANTS 0x00000020 643 #define BGE_RXMODE_RX_RUNTS 0x00000040 644 #define BGE_RXMODE_8022_LENCHECK 0x00000080 645 #define BGE_RXMODE_RX_PROMISC 0x00000100 646 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 647 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 648 649 /* Receive MAC status register */ 650 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 651 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 652 #define BGE_RXSTAT_RCVD_XON 0x00000004 653 654 /* Receive Rules Control register */ 655 #define BGE_RXRULECTL_OFFSET 0x000000FF 656 #define BGE_RXRULECTL_CLASS 0x00001F00 657 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 658 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 659 #define BGE_RXRULECTL_MAP 0x01000000 660 #define BGE_RXRULECTL_DISCARD 0x02000000 661 #define BGE_RXRULECTL_MASK 0x04000000 662 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 663 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 664 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 665 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 666 667 /* Receive Rules Mask register */ 668 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 669 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 670 671 /* SERDES configuration register */ 672 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 673 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 674 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 675 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 676 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 677 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 678 #define BGE_SERDESCFG_TXMODE 0x00001000 679 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 680 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 681 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 682 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 683 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 684 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 685 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 686 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 687 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 688 689 /* SERDES status register */ 690 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 691 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 692 693 /* SGDIG config (not documented) */ 694 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 695 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 696 #define BGE_SGDIGCFG_SEND 0x40000000 697 #define BGE_SGDIGCFG_AUTO 0x80000000 698 699 /* SGDIG status (not documented) */ 700 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 701 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 702 #define BGE_SGDIGSTS_DONE 0x00000002 703 704 /* MI communication register */ 705 #define BGE_MICOMM_DATA 0x0000FFFF 706 #define BGE_MICOMM_REG 0x001F0000 707 #define BGE_MICOMM_PHY 0x03E00000 708 #define BGE_MICOMM_CMD 0x0C000000 709 #define BGE_MICOMM_READFAIL 0x10000000 710 #define BGE_MICOMM_BUSY 0x20000000 711 712 #define BGE_MIREG(x) ((x & 0x1F) << 16) 713 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 714 #define BGE_MICMD_WRITE 0x04000000 715 #define BGE_MICMD_READ 0x08000000 716 717 /* MI status register */ 718 #define BGE_MISTS_LINK 0x00000001 719 #define BGE_MISTS_10MBPS 0x00000002 720 721 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 722 #define BGE_MIMODE_AUTOPOLL 0x00000010 723 #define BGE_MIMODE_CLKCNT 0x001F0000 724 725 726 /* 727 * Send data initiator control registers. 728 */ 729 #define BGE_SDI_MODE 0x0C00 730 #define BGE_SDI_STATUS 0x0C04 731 #define BGE_SDI_STATS_CTL 0x0C08 732 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 733 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 734 #define BGE_LOCSTATS_COS0 0x0C80 735 #define BGE_LOCSTATS_COS1 0x0C84 736 #define BGE_LOCSTATS_COS2 0x0C88 737 #define BGE_LOCSTATS_COS3 0x0C8C 738 #define BGE_LOCSTATS_COS4 0x0C90 739 #define BGE_LOCSTATS_COS5 0x0C84 740 #define BGE_LOCSTATS_COS6 0x0C98 741 #define BGE_LOCSTATS_COS7 0x0C9C 742 #define BGE_LOCSTATS_COS8 0x0CA0 743 #define BGE_LOCSTATS_COS9 0x0CA4 744 #define BGE_LOCSTATS_COS10 0x0CA8 745 #define BGE_LOCSTATS_COS11 0x0CAC 746 #define BGE_LOCSTATS_COS12 0x0CB0 747 #define BGE_LOCSTATS_COS13 0x0CB4 748 #define BGE_LOCSTATS_COS14 0x0CB8 749 #define BGE_LOCSTATS_COS15 0x0CBC 750 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 751 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 752 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 753 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 754 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 755 #define BGE_LOCSTATS_IRQS 0x0CD4 756 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 757 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 758 759 /* Send Data Initiator mode register */ 760 #define BGE_SDIMODE_RESET 0x00000001 761 #define BGE_SDIMODE_ENABLE 0x00000002 762 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 763 764 /* Send Data Initiator stats register */ 765 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 766 767 /* Send Data Initiator stats control register */ 768 #define BGE_SDISTATSCTL_ENABLE 0x00000001 769 #define BGE_SDISTATSCTL_FASTER 0x00000002 770 #define BGE_SDISTATSCTL_CLEAR 0x00000004 771 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 772 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 773 774 /* 775 * Send Data Completion Control registers 776 */ 777 #define BGE_SDC_MODE 0x1000 778 #define BGE_SDC_STATUS 0x1004 779 780 /* Send Data completion mode register */ 781 #define BGE_SDCMODE_RESET 0x00000001 782 #define BGE_SDCMODE_ENABLE 0x00000002 783 #define BGE_SDCMODE_ATTN 0x00000004 784 785 /* Send Data completion status register */ 786 #define BGE_SDCSTAT_ATTN 0x00000004 787 788 /* 789 * Send BD Ring Selector Control registers 790 */ 791 #define BGE_SRS_MODE 0x1400 792 #define BGE_SRS_STATUS 0x1404 793 #define BGE_SRS_HWDIAG 0x1408 794 #define BGE_SRS_LOC_NIC_CONS0 0x1440 795 #define BGE_SRS_LOC_NIC_CONS1 0x1444 796 #define BGE_SRS_LOC_NIC_CONS2 0x1448 797 #define BGE_SRS_LOC_NIC_CONS3 0x144C 798 #define BGE_SRS_LOC_NIC_CONS4 0x1450 799 #define BGE_SRS_LOC_NIC_CONS5 0x1454 800 #define BGE_SRS_LOC_NIC_CONS6 0x1458 801 #define BGE_SRS_LOC_NIC_CONS7 0x145C 802 #define BGE_SRS_LOC_NIC_CONS8 0x1460 803 #define BGE_SRS_LOC_NIC_CONS9 0x1464 804 #define BGE_SRS_LOC_NIC_CONS10 0x1468 805 #define BGE_SRS_LOC_NIC_CONS11 0x146C 806 #define BGE_SRS_LOC_NIC_CONS12 0x1470 807 #define BGE_SRS_LOC_NIC_CONS13 0x1474 808 #define BGE_SRS_LOC_NIC_CONS14 0x1478 809 #define BGE_SRS_LOC_NIC_CONS15 0x147C 810 811 /* Send BD Ring Selector Mode register */ 812 #define BGE_SRSMODE_RESET 0x00000001 813 #define BGE_SRSMODE_ENABLE 0x00000002 814 #define BGE_SRSMODE_ATTN 0x00000004 815 816 /* Send BD Ring Selector Status register */ 817 #define BGE_SRSSTAT_ERROR 0x00000004 818 819 /* Send BD Ring Selector HW Diagnostics register */ 820 #define BGE_SRSHWDIAG_STATE 0x0000000F 821 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 822 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 823 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 824 825 /* 826 * Send BD Initiator Selector Control registers 827 */ 828 #define BGE_SBDI_MODE 0x1800 829 #define BGE_SBDI_STATUS 0x1804 830 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 831 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 832 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 833 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 834 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 835 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 836 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 837 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 838 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 839 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 840 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 841 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 842 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 843 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 844 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 845 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 846 847 /* Send BD Initiator Mode register */ 848 #define BGE_SBDIMODE_RESET 0x00000001 849 #define BGE_SBDIMODE_ENABLE 0x00000002 850 #define BGE_SBDIMODE_ATTN 0x00000004 851 852 /* Send BD Initiator Status register */ 853 #define BGE_SBDISTAT_ERROR 0x00000004 854 855 /* 856 * Send BD Completion Control registers 857 */ 858 #define BGE_SBDC_MODE 0x1C00 859 #define BGE_SBDC_STATUS 0x1C04 860 861 /* Send BD Completion Control Mode register */ 862 #define BGE_SBDCMODE_RESET 0x00000001 863 #define BGE_SBDCMODE_ENABLE 0x00000002 864 #define BGE_SBDCMODE_ATTN 0x00000004 865 866 /* Send BD Completion Control Status register */ 867 #define BGE_SBDCSTAT_ATTN 0x00000004 868 869 /* 870 * Receive List Placement Control registers 871 */ 872 #define BGE_RXLP_MODE 0x2000 873 #define BGE_RXLP_STATUS 0x2004 874 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 875 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 876 #define BGE_RXLP_CFG 0x2010 877 #define BGE_RXLP_STATS_CTL 0x2014 878 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 879 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 880 #define BGE_RXLP_HEAD0 0x2100 881 #define BGE_RXLP_TAIL0 0x2104 882 #define BGE_RXLP_COUNT0 0x2108 883 #define BGE_RXLP_HEAD1 0x2110 884 #define BGE_RXLP_TAIL1 0x2114 885 #define BGE_RXLP_COUNT1 0x2118 886 #define BGE_RXLP_HEAD2 0x2120 887 #define BGE_RXLP_TAIL2 0x2124 888 #define BGE_RXLP_COUNT2 0x2128 889 #define BGE_RXLP_HEAD3 0x2130 890 #define BGE_RXLP_TAIL3 0x2134 891 #define BGE_RXLP_COUNT3 0x2138 892 #define BGE_RXLP_HEAD4 0x2140 893 #define BGE_RXLP_TAIL4 0x2144 894 #define BGE_RXLP_COUNT4 0x2148 895 #define BGE_RXLP_HEAD5 0x2150 896 #define BGE_RXLP_TAIL5 0x2154 897 #define BGE_RXLP_COUNT5 0x2158 898 #define BGE_RXLP_HEAD6 0x2160 899 #define BGE_RXLP_TAIL6 0x2164 900 #define BGE_RXLP_COUNT6 0x2168 901 #define BGE_RXLP_HEAD7 0x2170 902 #define BGE_RXLP_TAIL7 0x2174 903 #define BGE_RXLP_COUNT7 0x2178 904 #define BGE_RXLP_HEAD8 0x2180 905 #define BGE_RXLP_TAIL8 0x2184 906 #define BGE_RXLP_COUNT8 0x2188 907 #define BGE_RXLP_HEAD9 0x2190 908 #define BGE_RXLP_TAIL9 0x2194 909 #define BGE_RXLP_COUNT9 0x2198 910 #define BGE_RXLP_HEAD10 0x21A0 911 #define BGE_RXLP_TAIL10 0x21A4 912 #define BGE_RXLP_COUNT10 0x21A8 913 #define BGE_RXLP_HEAD11 0x21B0 914 #define BGE_RXLP_TAIL11 0x21B4 915 #define BGE_RXLP_COUNT11 0x21B8 916 #define BGE_RXLP_HEAD12 0x21C0 917 #define BGE_RXLP_TAIL12 0x21C4 918 #define BGE_RXLP_COUNT12 0x21C8 919 #define BGE_RXLP_HEAD13 0x21D0 920 #define BGE_RXLP_TAIL13 0x21D4 921 #define BGE_RXLP_COUNT13 0x21D8 922 #define BGE_RXLP_HEAD14 0x21E0 923 #define BGE_RXLP_TAIL14 0x21E4 924 #define BGE_RXLP_COUNT14 0x21E8 925 #define BGE_RXLP_HEAD15 0x21F0 926 #define BGE_RXLP_TAIL15 0x21F4 927 #define BGE_RXLP_COUNT15 0x21F8 928 #define BGE_RXLP_LOCSTAT_COS0 0x2200 929 #define BGE_RXLP_LOCSTAT_COS1 0x2204 930 #define BGE_RXLP_LOCSTAT_COS2 0x2208 931 #define BGE_RXLP_LOCSTAT_COS3 0x220C 932 #define BGE_RXLP_LOCSTAT_COS4 0x2210 933 #define BGE_RXLP_LOCSTAT_COS5 0x2214 934 #define BGE_RXLP_LOCSTAT_COS6 0x2218 935 #define BGE_RXLP_LOCSTAT_COS7 0x221C 936 #define BGE_RXLP_LOCSTAT_COS8 0x2220 937 #define BGE_RXLP_LOCSTAT_COS9 0x2224 938 #define BGE_RXLP_LOCSTAT_COS10 0x2228 939 #define BGE_RXLP_LOCSTAT_COS11 0x222C 940 #define BGE_RXLP_LOCSTAT_COS12 0x2230 941 #define BGE_RXLP_LOCSTAT_COS13 0x2234 942 #define BGE_RXLP_LOCSTAT_COS14 0x2238 943 #define BGE_RXLP_LOCSTAT_COS15 0x223C 944 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 945 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 946 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 947 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 948 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 949 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 950 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 951 952 953 /* Receive List Placement mode register */ 954 #define BGE_RXLPMODE_RESET 0x00000001 955 #define BGE_RXLPMODE_ENABLE 0x00000002 956 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 957 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 958 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 959 960 /* Receive List Placement Status register */ 961 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 962 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 963 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 964 965 /* 966 * Receive Data and Receive BD Initiator Control Registers 967 */ 968 #define BGE_RDBDI_MODE 0x2400 969 #define BGE_RDBDI_STATUS 0x2404 970 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 971 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 972 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 973 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 974 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 975 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 976 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 977 #define BGE_RX_STD_RCB_NICADDR 0x245C 978 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 979 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 980 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 981 #define BGE_RX_MINI_RCB_NICADDR 0x246C 982 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 983 #define BGE_RDBDI_STD_RX_CONS 0x2474 984 #define BGE_RDBDI_MINI_RX_CONS 0x2478 985 #define BGE_RDBDI_RETURN_PROD0 0x2480 986 #define BGE_RDBDI_RETURN_PROD1 0x2484 987 #define BGE_RDBDI_RETURN_PROD2 0x2488 988 #define BGE_RDBDI_RETURN_PROD3 0x248C 989 #define BGE_RDBDI_RETURN_PROD4 0x2490 990 #define BGE_RDBDI_RETURN_PROD5 0x2494 991 #define BGE_RDBDI_RETURN_PROD6 0x2498 992 #define BGE_RDBDI_RETURN_PROD7 0x249C 993 #define BGE_RDBDI_RETURN_PROD8 0x24A0 994 #define BGE_RDBDI_RETURN_PROD9 0x24A4 995 #define BGE_RDBDI_RETURN_PROD10 0x24A8 996 #define BGE_RDBDI_RETURN_PROD11 0x24AC 997 #define BGE_RDBDI_RETURN_PROD12 0x24B0 998 #define BGE_RDBDI_RETURN_PROD13 0x24B4 999 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1000 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1001 #define BGE_RDBDI_HWDIAG 0x24C0 1002 1003 1004 /* Receive Data and Receive BD Initiator Mode register */ 1005 #define BGE_RDBDIMODE_RESET 0x00000001 1006 #define BGE_RDBDIMODE_ENABLE 0x00000002 1007 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1008 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1009 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1010 1011 /* Receive Data and Receive BD Initiator Status register */ 1012 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1013 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1014 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1015 1016 1017 /* 1018 * Receive Data Completion Control registers 1019 */ 1020 #define BGE_RDC_MODE 0x2800 1021 1022 /* Receive Data Completion Mode register */ 1023 #define BGE_RDCMODE_RESET 0x00000001 1024 #define BGE_RDCMODE_ENABLE 0x00000002 1025 #define BGE_RDCMODE_ATTN 0x00000004 1026 1027 /* 1028 * Receive BD Initiator Control registers 1029 */ 1030 #define BGE_RBDI_MODE 0x2C00 1031 #define BGE_RBDI_STATUS 0x2C04 1032 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1033 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1034 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1035 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1036 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1037 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1038 1039 /* Receive BD Initiator Mode register */ 1040 #define BGE_RBDIMODE_RESET 0x00000001 1041 #define BGE_RBDIMODE_ENABLE 0x00000002 1042 #define BGE_RBDIMODE_ATTN 0x00000004 1043 1044 /* Receive BD Initiator Status register */ 1045 #define BGE_RBDISTAT_ATTN 0x00000004 1046 1047 /* 1048 * Receive BD Completion Control registers 1049 */ 1050 #define BGE_RBDC_MODE 0x3000 1051 #define BGE_RBDC_STATUS 0x3004 1052 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1053 #define BGE_RBDC_STD_BD_PROD 0x300C 1054 #define BGE_RBDC_MINI_BD_PROD 0x3010 1055 1056 /* Receive BD completion mode register */ 1057 #define BGE_RBDCMODE_RESET 0x00000001 1058 #define BGE_RBDCMODE_ENABLE 0x00000002 1059 #define BGE_RBDCMODE_ATTN 0x00000004 1060 1061 /* Receive BD completion status register */ 1062 #define BGE_RBDCSTAT_ERROR 0x00000004 1063 1064 /* 1065 * Receive List Selector Control registers 1066 */ 1067 #define BGE_RXLS_MODE 0x3400 1068 #define BGE_RXLS_STATUS 0x3404 1069 1070 /* Receive List Selector Mode register */ 1071 #define BGE_RXLSMODE_RESET 0x00000001 1072 #define BGE_RXLSMODE_ENABLE 0x00000002 1073 #define BGE_RXLSMODE_ATTN 0x00000004 1074 1075 /* Receive List Selector Status register */ 1076 #define BGE_RXLSSTAT_ERROR 0x00000004 1077 1078 /* 1079 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1080 */ 1081 #define BGE_MBCF_MODE 0x3800 1082 #define BGE_MBCF_STATUS 0x3804 1083 1084 /* Mbuf Cluster Free mode register */ 1085 #define BGE_MBCFMODE_RESET 0x00000001 1086 #define BGE_MBCFMODE_ENABLE 0x00000002 1087 #define BGE_MBCFMODE_ATTN 0x00000004 1088 1089 /* Mbuf Cluster Free status register */ 1090 #define BGE_MBCFSTAT_ERROR 0x00000004 1091 1092 /* 1093 * Host Coalescing Control registers 1094 */ 1095 #define BGE_HCC_MODE 0x3C00 1096 #define BGE_HCC_STATUS 0x3C04 1097 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1098 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1099 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1100 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1101 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1102 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1103 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1104 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1105 #define BGE_HCC_STATS_TICKS 0x3C28 1106 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1107 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1108 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1109 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1110 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1111 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1112 #define BGE_FLOW_ATTN 0x3C48 1113 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1114 #define BGE_HCC_STD_BD_CONS 0x3C54 1115 #define BGE_HCC_MINI_BD_CONS 0x3C58 1116 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1117 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1118 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1119 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1120 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1121 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1122 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1123 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1124 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1125 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1126 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1127 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1128 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1129 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1130 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1131 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1132 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1133 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1134 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1135 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1136 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1137 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1138 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1139 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1140 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1141 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1142 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1143 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1144 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1145 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1146 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1147 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1148 1149 1150 /* Host coalescing mode register */ 1151 #define BGE_HCCMODE_RESET 0x00000001 1152 #define BGE_HCCMODE_ENABLE 0x00000002 1153 #define BGE_HCCMODE_ATTN 0x00000004 1154 #define BGE_HCCMODE_COAL_NOW 0x00000008 1155 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1156 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1157 1158 #define BGE_STATBLKSZ_FULL 0x00000000 1159 #define BGE_STATBLKSZ_64BYTE 0x00000080 1160 #define BGE_STATBLKSZ_32BYTE 0x00000100 1161 1162 /* Host coalescing status register */ 1163 #define BGE_HCCSTAT_ERROR 0x00000004 1164 1165 /* Flow attention register */ 1166 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1167 #define BGE_FLOWATTN_MEMARB 0x00000080 1168 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1169 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1170 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1171 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1172 #define BGE_FLOWATTN_RDBDI 0x00080000 1173 #define BGE_FLOWATTN_RXLS 0x00100000 1174 #define BGE_FLOWATTN_RXLP 0x00200000 1175 #define BGE_FLOWATTN_RBDC 0x00400000 1176 #define BGE_FLOWATTN_RBDI 0x00800000 1177 #define BGE_FLOWATTN_SDC 0x08000000 1178 #define BGE_FLOWATTN_SDI 0x10000000 1179 #define BGE_FLOWATTN_SRS 0x20000000 1180 #define BGE_FLOWATTN_SBDC 0x40000000 1181 #define BGE_FLOWATTN_SBDI 0x80000000 1182 1183 /* 1184 * Memory arbiter registers 1185 */ 1186 #define BGE_MARB_MODE 0x4000 1187 #define BGE_MARB_STATUS 0x4004 1188 #define BGE_MARB_TRAPADDR_HI 0x4008 1189 #define BGE_MARB_TRAPADDR_LO 0x400C 1190 1191 /* Memory arbiter mode register */ 1192 #define BGE_MARBMODE_RESET 0x00000001 1193 #define BGE_MARBMODE_ENABLE 0x00000002 1194 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1195 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1196 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1197 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1198 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1199 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1200 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1201 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1202 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1203 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1204 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1205 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1206 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1207 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1208 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1209 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1210 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1211 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1212 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1213 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1214 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1215 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1216 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1217 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1218 1219 /* Memory arbiter status register */ 1220 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1221 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1222 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1223 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1224 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1225 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1226 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1227 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1228 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1229 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1230 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1231 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1232 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1233 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1234 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1235 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1236 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1237 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1238 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1239 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1240 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1241 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1242 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1243 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1244 1245 /* 1246 * Buffer manager control registers 1247 */ 1248 #define BGE_BMAN_MODE 0x4400 1249 #define BGE_BMAN_STATUS 0x4404 1250 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1251 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1252 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1253 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1254 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1255 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1256 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1257 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1258 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1259 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1260 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1261 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1262 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1263 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1264 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1265 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1266 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1267 #define BGE_BMAN_HWDIAG_1 0x444C 1268 #define BGE_BMAN_HWDIAG_2 0x4450 1269 #define BGE_BMAN_HWDIAG_3 0x4454 1270 1271 /* Buffer manager mode register */ 1272 #define BGE_BMANMODE_RESET 0x00000001 1273 #define BGE_BMANMODE_ENABLE 0x00000002 1274 #define BGE_BMANMODE_ATTN 0x00000004 1275 #define BGE_BMANMODE_TESTMODE 0x00000008 1276 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1277 1278 /* Buffer manager status register */ 1279 #define BGE_BMANSTAT_ERRO 0x00000004 1280 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1281 1282 1283 /* 1284 * Read DMA Control registers 1285 */ 1286 #define BGE_RDMA_MODE 0x4800 1287 #define BGE_RDMA_STATUS 0x4804 1288 1289 /* Read DMA mode register */ 1290 #define BGE_RDMAMODE_RESET 0x00000001 1291 #define BGE_RDMAMODE_ENABLE 0x00000002 1292 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1293 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1294 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1295 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1296 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1297 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1298 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1299 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1300 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1301 1302 /* Read DMA status register */ 1303 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1304 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1305 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1306 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1307 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1308 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1309 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1310 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1311 1312 /* 1313 * Write DMA control registers 1314 */ 1315 #define BGE_WDMA_MODE 0x4C00 1316 #define BGE_WDMA_STATUS 0x4C04 1317 1318 /* Write DMA mode register */ 1319 #define BGE_WDMAMODE_RESET 0x00000001 1320 #define BGE_WDMAMODE_ENABLE 0x00000002 1321 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1322 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1323 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1324 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1325 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1326 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1327 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1328 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1329 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1330 1331 /* Write DMA status register */ 1332 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1333 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1334 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1335 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1336 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1337 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1338 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1339 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1340 1341 1342 /* 1343 * RX CPU registers 1344 */ 1345 #define BGE_RXCPU_MODE 0x5000 1346 #define BGE_RXCPU_STATUS 0x5004 1347 #define BGE_RXCPU_PC 0x501C 1348 1349 /* RX CPU mode register */ 1350 #define BGE_RXCPUMODE_RESET 0x00000001 1351 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1352 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1353 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1354 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1355 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1356 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1357 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1358 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1359 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1360 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1361 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1362 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1363 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1364 1365 /* RX CPU status register */ 1366 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1367 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1368 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1369 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1370 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1371 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1372 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1373 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1374 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1375 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1376 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1377 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1378 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1379 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1380 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1381 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1382 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1383 1384 1385 /* 1386 * TX CPU registers 1387 */ 1388 #define BGE_TXCPU_MODE 0x5400 1389 #define BGE_TXCPU_STATUS 0x5404 1390 #define BGE_TXCPU_PC 0x541C 1391 1392 /* TX CPU mode register */ 1393 #define BGE_TXCPUMODE_RESET 0x00000001 1394 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1395 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1396 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1397 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1398 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1399 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1400 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1401 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1402 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1403 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1404 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1405 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1406 1407 /* TX CPU status register */ 1408 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1409 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1410 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1411 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1412 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1413 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1414 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1415 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1416 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1417 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1418 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1419 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1420 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1421 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1422 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1423 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1424 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1425 1426 1427 /* 1428 * Low priority mailbox registers 1429 */ 1430 #define BGE_LPMBX_IRQ0_HI 0x5800 1431 #define BGE_LPMBX_IRQ0_LO 0x5804 1432 #define BGE_LPMBX_IRQ1_HI 0x5808 1433 #define BGE_LPMBX_IRQ1_LO 0x580C 1434 #define BGE_LPMBX_IRQ2_HI 0x5810 1435 #define BGE_LPMBX_IRQ2_LO 0x5814 1436 #define BGE_LPMBX_IRQ3_HI 0x5818 1437 #define BGE_LPMBX_IRQ3_LO 0x581C 1438 #define BGE_LPMBX_GEN0_HI 0x5820 1439 #define BGE_LPMBX_GEN0_LO 0x5824 1440 #define BGE_LPMBX_GEN1_HI 0x5828 1441 #define BGE_LPMBX_GEN1_LO 0x582C 1442 #define BGE_LPMBX_GEN2_HI 0x5830 1443 #define BGE_LPMBX_GEN2_LO 0x5834 1444 #define BGE_LPMBX_GEN3_HI 0x5828 1445 #define BGE_LPMBX_GEN3_LO 0x582C 1446 #define BGE_LPMBX_GEN4_HI 0x5840 1447 #define BGE_LPMBX_GEN4_LO 0x5844 1448 #define BGE_LPMBX_GEN5_HI 0x5848 1449 #define BGE_LPMBX_GEN5_LO 0x584C 1450 #define BGE_LPMBX_GEN6_HI 0x5850 1451 #define BGE_LPMBX_GEN6_LO 0x5854 1452 #define BGE_LPMBX_GEN7_HI 0x5858 1453 #define BGE_LPMBX_GEN7_LO 0x585C 1454 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1455 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1456 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1457 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1458 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1459 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1460 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1461 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1462 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1463 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1464 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1465 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1466 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1467 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1468 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1469 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1470 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1471 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1472 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1473 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1474 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1475 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1476 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1477 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1478 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1479 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1480 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1481 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1482 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1483 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1484 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1485 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1486 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1487 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1488 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1489 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1490 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1491 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1492 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1493 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1494 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1495 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1496 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1497 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1498 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1499 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1500 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1501 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1502 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1503 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1504 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1505 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1506 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1507 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1508 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1509 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1510 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1511 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1512 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1513 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1514 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1515 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1516 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1517 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1518 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1519 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1520 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1521 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1522 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1523 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1524 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1525 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1526 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1527 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1528 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1529 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1530 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1531 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1532 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1533 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1534 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1535 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1536 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1537 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1538 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1539 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1540 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1541 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1542 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1543 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1544 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1545 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1546 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1547 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1548 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1549 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1550 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1551 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1552 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1553 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1554 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1555 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1556 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1557 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1558 1559 /* 1560 * Flow throw Queue reset register 1561 */ 1562 #define BGE_FTQ_RESET 0x5C00 1563 1564 #define BGE_FTQRESET_DMAREAD 0x00000002 1565 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1566 #define BGE_FTQRESET_DMADONE 0x00000010 1567 #define BGE_FTQRESET_SBDC 0x00000020 1568 #define BGE_FTQRESET_SDI 0x00000040 1569 #define BGE_FTQRESET_WDMA 0x00000080 1570 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1571 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1572 #define BGE_FTQRESET_SDC 0x00000400 1573 #define BGE_FTQRESET_HCC 0x00000800 1574 #define BGE_FTQRESET_TXFIFO 0x00001000 1575 #define BGE_FTQRESET_MBC 0x00002000 1576 #define BGE_FTQRESET_RBDC 0x00004000 1577 #define BGE_FTQRESET_RXLP 0x00008000 1578 #define BGE_FTQRESET_RDBDI 0x00010000 1579 #define BGE_FTQRESET_RDC 0x00020000 1580 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1581 1582 /* 1583 * Message Signaled Interrupt registers 1584 */ 1585 #define BGE_MSI_MODE 0x6000 1586 #define BGE_MSI_STATUS 0x6004 1587 #define BGE_MSI_FIFOACCESS 0x6008 1588 1589 /* MSI mode register */ 1590 #define BGE_MSIMODE_RESET 0x00000001 1591 #define BGE_MSIMODE_ENABLE 0x00000002 1592 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1593 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1594 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1595 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1596 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1597 1598 /* MSI status register */ 1599 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1600 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1601 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1602 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1603 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1604 1605 1606 /* 1607 * DMA Completion registers 1608 */ 1609 #define BGE_DMAC_MODE 0x6400 1610 1611 /* DMA Completion mode register */ 1612 #define BGE_DMACMODE_RESET 0x00000001 1613 #define BGE_DMACMODE_ENABLE 0x00000002 1614 1615 1616 /* 1617 * General control registers. 1618 */ 1619 #define BGE_MODE_CTL 0x6800 1620 #define BGE_MISC_CFG 0x6804 1621 #define BGE_MISC_LOCAL_CTL 0x6808 1622 #define BGE_EE_ADDR 0x6838 1623 #define BGE_EE_DATA 0x683C 1624 #define BGE_EE_CTL 0x6840 1625 #define BGE_MDI_CTL 0x6844 1626 #define BGE_EE_DELAY 0x6848 1627 1628 /* Mode control register */ 1629 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1630 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1631 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1632 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1633 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1634 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1635 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1636 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1637 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1638 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1639 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1640 #define BGE_MODECTL_STACKUP 0x00010000 1641 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1642 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1643 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1644 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1645 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1646 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1647 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1648 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1649 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1650 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1651 1652 /* Misc. config register */ 1653 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1654 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1655 1656 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1657 1658 /* Misc. Local Control */ 1659 #define BGE_MLC_INTR_STATE 0x00000001 1660 #define BGE_MLC_INTR_CLR 0x00000002 1661 #define BGE_MLC_INTR_SET 0x00000004 1662 #define BGE_MLC_INTR_ONATTN 0x00000008 1663 #define BGE_MLC_MISCIO_IN0 0x00000100 1664 #define BGE_MLC_MISCIO_IN1 0x00000200 1665 #define BGE_MLC_MISCIO_IN2 0x00000400 1666 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1667 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1668 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1669 #define BGE_MLC_MISCIO_OUT0 0x00004000 1670 #define BGE_MLC_MISCIO_OUT1 0x00008000 1671 #define BGE_MLC_MISCIO_OUT2 0x00010000 1672 #define BGE_MLC_EXTRAM_ENB 0x00020000 1673 #define BGE_MLC_SRAM_SIZE 0x001C0000 1674 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1675 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1676 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1677 #define BGE_MLC_AUTO_EEPROM 0x01000000 1678 1679 #define BGE_SSRAMSIZE_256KB 0x00000000 1680 #define BGE_SSRAMSIZE_512KB 0x00040000 1681 #define BGE_SSRAMSIZE_1MB 0x00080000 1682 #define BGE_SSRAMSIZE_2MB 0x000C0000 1683 #define BGE_SSRAMSIZE_4MB 0x00100000 1684 #define BGE_SSRAMSIZE_8MB 0x00140000 1685 #define BGE_SSRAMSIZE_16M 0x00180000 1686 1687 /* EEPROM address register */ 1688 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1689 #define BGE_EEADDR_HALFCLK 0x01FF0000 1690 #define BGE_EEADDR_START 0x02000000 1691 #define BGE_EEADDR_DEVID 0x1C000000 1692 #define BGE_EEADDR_RESET 0x20000000 1693 #define BGE_EEADDR_DONE 0x40000000 1694 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1695 1696 #define BGE_EEDEVID(x) ((x & 7) << 26) 1697 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1698 #define BGE_HALFCLK_384SCL 0x60 1699 #define BGE_EE_READCMD \ 1700 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1701 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1702 #define BGE_EE_WRCMD \ 1703 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1704 BGE_EEADDR_START|BGE_EEADDR_DONE) 1705 1706 /* EEPROM Control register */ 1707 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1708 #define BGE_EECTL_CLKOUT 0x00000002 1709 #define BGE_EECTL_CLKIN 0x00000004 1710 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1711 #define BGE_EECTL_DATAOUT 0x00000010 1712 #define BGE_EECTL_DATAIN 0x00000020 1713 1714 /* MDI (MII/GMII) access register */ 1715 #define BGE_MDI_DATA 0x00000001 1716 #define BGE_MDI_DIR 0x00000002 1717 #define BGE_MDI_SEL 0x00000004 1718 #define BGE_MDI_CLK 0x00000008 1719 1720 #define BGE_MEMWIN_START 0x00008000 1721 #define BGE_MEMWIN_END 0x0000FFFF 1722 1723 1724 #define BGE_MEMWIN_READ(sc, x, val) \ 1725 do { \ 1726 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1727 (0xFFFF0000 & x), 4); \ 1728 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1729 } while(0) 1730 1731 #define BGE_MEMWIN_WRITE(sc, x, val) \ 1732 do { \ 1733 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1734 (0xFFFF0000 & x), 4); \ 1735 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1736 } while(0) 1737 1738 /* 1739 * This magic number is used to prevent PXE restart when we 1740 * issue a software reset. We write this magic number to the 1741 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1742 * code from running. 1743 */ 1744 #define BGE_MAGIC_NUMBER 0x4B657654 1745 1746 typedef struct { 1747 uint32_t bge_addr_hi; 1748 uint32_t bge_addr_lo; 1749 } bge_hostaddr; 1750 #define BGE_HOSTADDR(x, y) \ 1751 do { \ 1752 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1753 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1754 } while(0) 1755 1756 /* Ring control block structure */ 1757 struct bge_rcb { 1758 bge_hostaddr bge_hostaddr; 1759 uint32_t bge_maxlen_flags; 1760 uint32_t bge_nicaddr; 1761 }; 1762 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1763 1764 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1765 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1766 1767 struct bge_tx_bd { 1768 bge_hostaddr bge_addr; 1769 uint16_t bge_flags; 1770 uint16_t bge_len; 1771 uint16_t bge_vlan_tag; 1772 uint16_t bge_rsvd; 1773 }; 1774 1775 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1776 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1777 #define BGE_TXBDFLAG_END 0x0004 1778 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1779 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1780 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1781 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1782 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1783 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1784 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1785 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1786 #define BGE_TXBDFLAG_NO_CRC 0x8000 1787 1788 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1789 BGE_SEND_RING_1_TO_4 + \ 1790 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1791 1792 struct bge_rx_bd { 1793 bge_hostaddr bge_addr; 1794 uint16_t bge_len; 1795 uint16_t bge_idx; 1796 uint16_t bge_flags; 1797 uint16_t bge_type; 1798 uint16_t bge_tcp_udp_csum; 1799 uint16_t bge_ip_csum; 1800 uint16_t bge_vlan_tag; 1801 uint16_t bge_error_flag; 1802 uint32_t bge_rsvd; 1803 uint32_t bge_opaque; 1804 }; 1805 1806 #define BGE_RXBDFLAG_END 0x0004 1807 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1808 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1809 #define BGE_RXBDFLAG_ERROR 0x0400 1810 #define BGE_RXBDFLAG_MINI_RING 0x0800 1811 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1812 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1813 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1814 1815 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1816 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1817 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1818 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1819 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1820 #define BGE_RXERRFLAG_RUNT 0x0020 1821 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1822 #define BGE_RXERRFLAG_GIANT 0x0080 1823 1824 struct bge_sts_idx { 1825 uint16_t bge_rx_prod_idx; 1826 uint16_t bge_tx_cons_idx; 1827 }; 1828 1829 struct bge_status_block { 1830 uint32_t bge_status; 1831 uint32_t bge_rsvd0; 1832 uint16_t bge_rx_jumbo_cons_idx; 1833 uint16_t bge_rx_std_cons_idx; 1834 uint16_t bge_rx_mini_cons_idx; 1835 uint16_t bge_rsvd1; 1836 struct bge_sts_idx bge_idx[16]; 1837 }; 1838 1839 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1840 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1841 1842 #define BGE_STATFLAG_UPDATED 0x00000001 1843 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1844 #define BGE_STATFLAG_ERROR 0x00000004 1845 1846 1847 /* 1848 * Offset of MAC address inside EEPROM. 1849 */ 1850 #define BGE_EE_MAC_OFFSET 0x7C 1851 #define BGE_EE_HWCFG_OFFSET 0xC8 1852 1853 #define BGE_HWCFG_VOLTAGE 0x00000003 1854 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 1855 #define BGE_HWCFG_MEDIA 0x00000030 1856 1857 #define BGE_VOLTAGE_1POINT3 0x00000000 1858 #define BGE_VOLTAGE_1POINT8 0x00000001 1859 1860 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 1861 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1862 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 1863 1864 #define BGE_MEDIA_UNSPEC 0x00000000 1865 #define BGE_MEDIA_COPPER 0x00000010 1866 #define BGE_MEDIA_FIBER 0x00000020 1867 1868 #define BGE_PCI_READ_CMD 0x06000000 1869 #define BGE_PCI_WRITE_CMD 0x70000000 1870 1871 #define BGE_TICKS_PER_SEC 1000000 1872 1873 /* 1874 * Ring size constants. 1875 */ 1876 #define BGE_EVENT_RING_CNT 256 1877 #define BGE_CMD_RING_CNT 64 1878 #define BGE_STD_RX_RING_CNT 512 1879 #define BGE_JUMBO_RX_RING_CNT 256 1880 #define BGE_MINI_RX_RING_CNT 1024 1881 #define BGE_RETURN_RING_CNT 1024 1882 1883 /* 5705 has smaller return ring size */ 1884 1885 #define BGE_RETURN_RING_CNT_5705 512 1886 1887 /* 1888 * Possible TX ring sizes. 1889 */ 1890 #define BGE_TX_RING_CNT_128 128 1891 #define BGE_TX_RING_BASE_128 0x3800 1892 1893 #define BGE_TX_RING_CNT_256 256 1894 #define BGE_TX_RING_BASE_256 0x3000 1895 1896 #define BGE_TX_RING_CNT_512 512 1897 #define BGE_TX_RING_BASE_512 0x2000 1898 1899 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1900 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1901 1902 /* 1903 * Tigon III statistics counters. 1904 */ 1905 /* Statistics maintained MAC Receive block. */ 1906 struct bge_rx_mac_stats { 1907 bge_hostaddr ifHCInOctets; 1908 bge_hostaddr Reserved1; 1909 bge_hostaddr etherStatsFragments; 1910 bge_hostaddr ifHCInUcastPkts; 1911 bge_hostaddr ifHCInMulticastPkts; 1912 bge_hostaddr ifHCInBroadcastPkts; 1913 bge_hostaddr dot3StatsFCSErrors; 1914 bge_hostaddr dot3StatsAlignmentErrors; 1915 bge_hostaddr xonPauseFramesReceived; 1916 bge_hostaddr xoffPauseFramesReceived; 1917 bge_hostaddr macControlFramesReceived; 1918 bge_hostaddr xoffStateEntered; 1919 bge_hostaddr dot3StatsFramesTooLong; 1920 bge_hostaddr etherStatsJabbers; 1921 bge_hostaddr etherStatsUndersizePkts; 1922 bge_hostaddr inRangeLengthError; 1923 bge_hostaddr outRangeLengthError; 1924 bge_hostaddr etherStatsPkts64Octets; 1925 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1926 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1927 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1928 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1929 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1930 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1931 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1932 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1933 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1934 }; 1935 1936 1937 /* Statistics maintained MAC Transmit block. */ 1938 struct bge_tx_mac_stats { 1939 bge_hostaddr ifHCOutOctets; 1940 bge_hostaddr Reserved2; 1941 bge_hostaddr etherStatsCollisions; 1942 bge_hostaddr outXonSent; 1943 bge_hostaddr outXoffSent; 1944 bge_hostaddr flowControlDone; 1945 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1946 bge_hostaddr dot3StatsSingleCollisionFrames; 1947 bge_hostaddr dot3StatsMultipleCollisionFrames; 1948 bge_hostaddr dot3StatsDeferredTransmissions; 1949 bge_hostaddr Reserved3; 1950 bge_hostaddr dot3StatsExcessiveCollisions; 1951 bge_hostaddr dot3StatsLateCollisions; 1952 bge_hostaddr dot3Collided2Times; 1953 bge_hostaddr dot3Collided3Times; 1954 bge_hostaddr dot3Collided4Times; 1955 bge_hostaddr dot3Collided5Times; 1956 bge_hostaddr dot3Collided6Times; 1957 bge_hostaddr dot3Collided7Times; 1958 bge_hostaddr dot3Collided8Times; 1959 bge_hostaddr dot3Collided9Times; 1960 bge_hostaddr dot3Collided10Times; 1961 bge_hostaddr dot3Collided11Times; 1962 bge_hostaddr dot3Collided12Times; 1963 bge_hostaddr dot3Collided13Times; 1964 bge_hostaddr dot3Collided14Times; 1965 bge_hostaddr dot3Collided15Times; 1966 bge_hostaddr ifHCOutUcastPkts; 1967 bge_hostaddr ifHCOutMulticastPkts; 1968 bge_hostaddr ifHCOutBroadcastPkts; 1969 bge_hostaddr dot3StatsCarrierSenseErrors; 1970 bge_hostaddr ifOutDiscards; 1971 bge_hostaddr ifOutErrors; 1972 }; 1973 1974 /* Stats counters access through registers */ 1975 struct bge_mac_stats_regs { 1976 uint32_t ifHCOutOctets; 1977 uint32_t Reserved0; 1978 uint32_t etherStatsCollisions; 1979 uint32_t outXonSent; 1980 uint32_t outXoffSent; 1981 uint32_t Reserved1; 1982 uint32_t dot3StatsInternalMacTransmitErrors; 1983 uint32_t dot3StatsSingleCollisionFrames; 1984 uint32_t dot3StatsMultipleCollisionFrames; 1985 uint32_t dot3StatsDeferredTransmissions; 1986 uint32_t Reserved2; 1987 uint32_t dot3StatsExcessiveCollisions; 1988 uint32_t dot3StatsLateCollisions; 1989 uint32_t Reserved3[14]; 1990 uint32_t ifHCOutUcastPkts; 1991 uint32_t ifHCOutMulticastPkts; 1992 uint32_t ifHCOutBroadcastPkts; 1993 uint32_t Reserved4[2]; 1994 uint32_t ifHCInOctets; 1995 uint32_t Reserved5; 1996 uint32_t etherStatsFragments; 1997 uint32_t ifHCInUcastPkts; 1998 uint32_t ifHCInMulticastPkts; 1999 uint32_t ifHCInBroadcastPkts; 2000 uint32_t dot3StatsFCSErrors; 2001 uint32_t dot3StatsAlignmentErrors; 2002 uint32_t xonPauseFramesReceived; 2003 uint32_t xoffPauseFramesReceived; 2004 uint32_t macControlFramesReceived; 2005 uint32_t xoffStateEntered; 2006 uint32_t dot3StatsFramesTooLong; 2007 uint32_t etherStatsJabbers; 2008 uint32_t etherStatsUndersizePkts; 2009 }; 2010 2011 struct bge_stats { 2012 uint8_t Reserved0[256]; 2013 2014 /* Statistics maintained by Receive MAC. */ 2015 struct bge_rx_mac_stats rxstats; 2016 2017 bge_hostaddr Unused1[37]; 2018 2019 /* Statistics maintained by Transmit MAC. */ 2020 struct bge_tx_mac_stats txstats; 2021 2022 bge_hostaddr Unused2[31]; 2023 2024 /* Statistics maintained by Receive List Placement. */ 2025 bge_hostaddr COSIfHCInPkts[16]; 2026 bge_hostaddr COSFramesDroppedDueToFilters; 2027 bge_hostaddr nicDmaWriteQueueFull; 2028 bge_hostaddr nicDmaWriteHighPriQueueFull; 2029 bge_hostaddr nicNoMoreRxBDs; 2030 bge_hostaddr ifInDiscards; 2031 bge_hostaddr ifInErrors; 2032 bge_hostaddr nicRecvThresholdHit; 2033 2034 bge_hostaddr Unused3[9]; 2035 2036 /* Statistics maintained by Send Data Initiator. */ 2037 bge_hostaddr COSIfHCOutPkts[16]; 2038 bge_hostaddr nicDmaReadQueueFull; 2039 bge_hostaddr nicDmaReadHighPriQueueFull; 2040 bge_hostaddr nicSendDataCompQueueFull; 2041 2042 /* Statistics maintained by Host Coalescing. */ 2043 bge_hostaddr nicRingSetSendProdIndex; 2044 bge_hostaddr nicRingStatusUpdate; 2045 bge_hostaddr nicInterrupts; 2046 bge_hostaddr nicAvoidedInterrupts; 2047 bge_hostaddr nicSendThresholdHit; 2048 2049 uint8_t Reserved4[320]; 2050 }; 2051 2052 /* 2053 * Tigon general information block. This resides in host memory 2054 * and contains the status counters, ring control blocks and 2055 * producer pointers. 2056 */ 2057 2058 struct bge_gib { 2059 struct bge_stats bge_stats; 2060 struct bge_rcb bge_tx_rcb[16]; 2061 struct bge_rcb bge_std_rx_rcb; 2062 struct bge_rcb bge_jumbo_rx_rcb; 2063 struct bge_rcb bge_mini_rx_rcb; 2064 struct bge_rcb bge_return_rcb; 2065 }; 2066 2067 /* 2068 * NOTE! On the Alpha, we have an alignment constraint. 2069 * The first thing in the packet is a 14-byte Ethernet header. 2070 * This means that the packet is misaligned. To compensate, 2071 * we actually offset the data 2 bytes into the cluster. This 2072 * alignes the packet after the Ethernet header at a 32-bit 2073 * boundary. 2074 */ 2075 2076 #define ETHER_ALIGN 2 2077 2078 #define BGE_FRAMELEN 1518 2079 #define BGE_MAX_FRAMELEN 1536 2080 #define BGE_JUMBO_FRAMELEN 9018 2081 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2082 #define BGE_PAGE_SIZE PAGE_SIZE 2083 #define BGE_MIN_FRAMELEN 60 2084 2085 /* 2086 * Other utility macros. 2087 */ 2088 #define BGE_INC(x, y) (x) = (x + 1) % y 2089 2090 /* 2091 * Vital product data and structures. 2092 */ 2093 #define BGE_VPD_FLAG 0x8000 2094 2095 /* VPD structures */ 2096 struct vpd_res { 2097 uint8_t vr_id; 2098 uint8_t vr_len; 2099 uint8_t vr_pad; 2100 }; 2101 2102 struct vpd_key { 2103 char vk_key[2]; 2104 uint8_t vk_len; 2105 }; 2106 2107 #define VPD_RES_ID 0x82 /* ID string */ 2108 #define VPD_RES_READ 0x90 /* start of read only area */ 2109 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2110 #define VPD_RES_END 0x78 /* end tag */ 2111 2112 2113 /* 2114 * Register access macros. The Tigon always uses memory mapped register 2115 * accesses and all registers must be accessed with 32 bit operations. 2116 */ 2117 2118 #define CSR_WRITE_4(sc, reg, val) \ 2119 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2120 2121 #define CSR_READ_4(sc, reg) \ 2122 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2123 2124 #define BGE_SETBIT(sc, reg, x) \ 2125 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2126 #define BGE_CLRBIT(sc, reg, x) \ 2127 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2128 2129 #define PCI_SETBIT(dev, reg, x, s) \ 2130 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s) 2131 #define PCI_CLRBIT(dev, reg, x, s) \ 2132 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s) 2133 2134 /* 2135 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2136 * values are tuneable. They control the actual amount of buffers 2137 * allocated for the standard, mini and jumbo receive rings. 2138 */ 2139 2140 #define BGE_SSLOTS 256 2141 #define BGE_MSLOTS 256 2142 #define BGE_JSLOTS 384 2143 2144 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2145 #define BGE_JLEN (BGE_JRAWLEN + \ 2146 (sizeof(uint64_t) - BGE_JRAWLEN % sizeof(uint64_t))) 2147 #define BGE_JPAGESZ PAGE_SIZE 2148 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2149 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2150 2151 struct bge_softc; 2152 2153 struct bge_jslot { 2154 struct bge_softc *bge_sc; 2155 void *bge_buf; 2156 int bge_inuse; 2157 int bge_slot; 2158 SLIST_ENTRY(bge_jslot) jslot_link; 2159 }; 2160 2161 /* 2162 * Ring structures. Most of these reside in host memory and we tell 2163 * the NIC where they are via the ring control blocks. The exceptions 2164 * are the tx and command rings, which live in NIC memory and which 2165 * we access via the shared memory window. 2166 */ 2167 struct bge_ring_data { 2168 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2169 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2170 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2171 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2172 struct bge_status_block bge_status_block; 2173 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2174 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2175 struct bge_gib bge_info; 2176 }; 2177 2178 /* 2179 * Mbuf pointers. We need these to keep track of the virtual addresses 2180 * of our mbuf chains since we can only convert from physical to virtual, 2181 * not the other way around. 2182 */ 2183 struct bge_chain_data { 2184 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2185 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2186 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2187 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2188 /* Stick the jumbo mem management stuff here too. */ 2189 struct bge_jslot bge_jslots[BGE_JSLOTS]; 2190 void *bge_jumbo_buf; 2191 }; 2192 2193 struct bge_type { 2194 uint16_t bge_vid; 2195 uint16_t bge_did; 2196 char *bge_name; 2197 }; 2198 2199 #define BGE_HWREV_TIGON 0x01 2200 #define BGE_HWREV_TIGON_II 0x02 2201 #define BGE_TIMEOUT 100000 2202 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2203 2204 struct bge_bcom_hack { 2205 int reg; 2206 int val; 2207 }; 2208 2209 struct bge_softc { 2210 struct arpcom arpcom; /* interface info */ 2211 device_t bge_dev; 2212 device_t bge_miibus; 2213 bus_space_handle_t bge_bhandle; 2214 vm_offset_t bge_vhandle; 2215 bus_space_tag_t bge_btag; 2216 void *bge_intrhand; 2217 struct resource *bge_irq; 2218 struct resource *bge_res; 2219 struct ifmedia bge_ifmedia; /* TBI media info */ 2220 uint8_t bge_extram; /* has external SSRAM */ 2221 uint8_t bge_tbi; 2222 uint8_t bge_rx_alignment_bug; 2223 uint32_t bge_chipid; 2224 uint8_t bge_asicrev; 2225 uint8_t bge_chiprev; 2226 uint8_t bge_no_3_led; 2227 uint8_t bge_pcie; 2228 struct bge_ring_data *bge_rdata; /* rings */ 2229 struct bge_chain_data bge_cdata; /* mbufs */ 2230 uint16_t bge_tx_saved_considx; 2231 uint16_t bge_rx_saved_considx; 2232 uint16_t bge_ev_saved_considx; 2233 uint16_t bge_return_ring_cnt; 2234 uint16_t bge_std; /* current std ring head */ 2235 uint16_t bge_jumbo; /* current jumo ring head */ 2236 SLIST_HEAD(__bge_jfreehead, bge_jslot) bge_jfree_listhead; 2237 struct lwkt_serialize bge_jslot_serializer; 2238 uint32_t bge_stat_ticks; 2239 uint32_t bge_rx_coal_ticks; 2240 uint32_t bge_tx_coal_ticks; 2241 uint32_t bge_rx_max_coal_bds; 2242 uint32_t bge_tx_max_coal_bds; 2243 uint32_t bge_tx_buf_ratio; 2244 int bge_if_flags; 2245 int bge_txcnt; 2246 int bge_link; 2247 struct callout bge_stat_timer; 2248 char *bge_vpd_prodname; 2249 char *bge_vpd_readonly; 2250 }; 2251