1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $ 35 */ 36 37 #ifndef _IF_BGEREG_H_ 38 #define _IF_BGEREG_H_ 39 40 /* 41 * BCM570x memory map. The internal memory layout varies somewhat 42 * depending on whether or not we have external SSRAM attached. 43 * The BCM5700 can have up to 16MB of external memory. The BCM5701 44 * is apparently not designed to use external SSRAM. The mappings 45 * up to the first 4 send rings are the same for both internal and 46 * external memory configurations. Note that mini RX ring space is 47 * only available with external SSRAM configurations, which means 48 * the mini RX ring is not supported on the BCM5701. 49 * 50 * The NIC's memory can be accessed by the host in one of 3 ways: 51 * 52 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 53 * registers in PCI config space can be used to read any 32-bit 54 * address within the NIC's memory. 55 * 56 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 57 * space can be used in conjunction with the memory window in the 58 * device register space at offset 0x8000 to read any 32K chunk 59 * of NIC memory. 60 * 61 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 62 * set, the device I/O mapping consumes 32MB of host address space, 63 * allowing all of the registers and internal NIC memory to be 64 * accessed directly. NIC memory addresses are offset by 0x01000000. 65 * Flat mode consumes so much host address space that it is not 66 * recommended. 67 */ 68 #define BGE_PAGE_ZERO 0x00000000 69 #define BGE_PAGE_ZERO_END 0x000000FF 70 #define BGE_SEND_RING_RCB 0x00000100 71 #define BGE_SEND_RING_RCB_END 0x000001FF 72 #define BGE_RX_RETURN_RING_RCB 0x00000200 73 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 74 #define BGE_STATS_BLOCK 0x00000300 75 #define BGE_STATS_BLOCK_END 0x00000AFF 76 #define BGE_STATUS_BLOCK 0x00000B00 77 #define BGE_STATUS_BLOCK_END 0x00000B4F 78 #define BGE_SRAM_FW_MB 0x00000B50 79 #define BGE_SRAM_DATA_SIG 0x00000B54 80 #define BGE_SRAM_DATA_CFG 0x00000B58 81 #define BGE_SRAM_FW_CMD_MB 0x00000B78 82 #define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 83 #define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 84 #define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 85 #define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 86 #define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 87 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 88 #define BGE_UNMAPPED 0x00001000 89 #define BGE_UNMAPPED_END 0x00001FFF 90 #define BGE_DMA_DESCRIPTORS 0x00002000 91 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 92 #define BGE_SEND_RING_5717 0x00004000 93 #define BGE_SEND_RING_1_TO_4 0x00004000 94 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 95 96 /* Firmware interface */ 97 #define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 98 99 #define BGE_FW_CMD_DRV_ALIVE 0x00000001 100 #define BGE_FW_CMD_PAUSE 0x00000002 101 #define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 102 #define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 103 #define BGE_FW_CMD_LINK_UPDATE 0x0000000C 104 #define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 105 #define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 106 107 #define BGE_FW_HB_TIMEOUT_SEC 3 108 109 #define BGE_FW_DRV_STATE_START 0x00000001 110 #define BGE_FW_DRV_STATE_START_DONE 0x80000001 111 #define BGE_FW_DRV_STATE_UNLOAD 0x00000002 112 #define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 113 #define BGE_FW_DRV_STATE_WOL 0x00000003 114 #define BGE_FW_DRV_STATE_SUSPEND 0x00000004 115 116 /* Mappings for internal memory configuration */ 117 #define BGE_STD_RX_RINGS 0x00006000 118 #define BGE_STD_RX_RINGS_END 0x00006FFF 119 #define BGE_JUMBO_RX_RINGS 0x00007000 120 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 121 #define BGE_BUFFPOOL_1 0x00008000 122 #define BGE_BUFFPOOL_1_END 0x0000FFFF 123 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 124 #define BGE_BUFFPOOL_2_END 0x00017FFF 125 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 126 #define BGE_BUFFPOOL_3_END 0x0001FFFF 127 #define BGE_STD_RX_RINGS_5717 0x00040000 128 #define BGE_JUMBO_RX_RINGS_5717 0x00044400 129 130 /* Mappings for external SSRAM configurations */ 131 #define BGE_SEND_RING_5_TO_6 0x00006000 132 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 133 #define BGE_SEND_RING_7_TO_8 0x00007000 134 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 135 #define BGE_SEND_RING_9_TO_16 0x00008000 136 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 137 #define BGE_EXT_STD_RX_RINGS 0x0000C000 138 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 139 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 140 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 141 #define BGE_MINI_RX_RINGS 0x0000E000 142 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 143 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 144 #define BGE_AVAIL_REGION1_END 0x00017FFF 145 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 146 #define BGE_AVAIL_REGION2_END 0x0001FFFF 147 #define BGE_EXT_SSRAM 0x00020000 148 #define BGE_EXT_SSRAM_END 0x000FFFFF 149 150 151 /* 152 * BCM570x register offsets. These are memory mapped registers 153 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 154 * Each register must be accessed using 32 bit operations. 155 * 156 * All registers are accessed through a 32K shared memory block. 157 * The first group of registers are actually copies of the PCI 158 * configuration space registers. 159 */ 160 161 /* 162 * PCI registers defined in the PCI 2.2 spec. 163 */ 164 #define BGE_PCI_VID 0x00 165 #define BGE_PCI_DID 0x02 166 #define BGE_PCI_CMD 0x04 167 #define BGE_PCI_STS 0x06 168 #define BGE_PCI_REV 0x08 169 #define BGE_PCI_CLASS 0x09 170 #define BGE_PCI_CACHESZ 0x0C 171 #define BGE_PCI_LATTIMER 0x0D 172 #define BGE_PCI_HDRTYPE 0x0E 173 #define BGE_PCI_BIST 0x0F 174 #define BGE_PCI_BAR0 0x10 175 #define BGE_PCI_BAR1 0x14 176 #define BGE_PCI_SUBSYS 0x2C 177 #define BGE_PCI_SUBVID 0x2E 178 #define BGE_PCI_ROMBASE 0x30 179 #define BGE_PCI_CAPPTR 0x34 180 #define BGE_PCI_INTLINE 0x3C 181 #define BGE_PCI_INTPIN 0x3D 182 #define BGE_PCI_MINGNT 0x3E 183 #define BGE_PCI_MAXLAT 0x3F 184 #define BGE_PCI_PCIXCAP 0x40 185 #define BGE_PCI_NEXTPTR_PM 0x41 186 #define BGE_PCI_PCIX_CMD 0x42 187 #define BGE_PCI_PCIX_STS 0x44 188 #define BGE_PCI_PWRMGMT_CAPID 0x48 189 #define BGE_PCI_NEXTPTR_VPD 0x49 190 #define BGE_PCI_PWRMGMT_CAPS 0x4A 191 #define BGE_PCI_PWRMGMT_CMD 0x4C 192 #define BGE_PCI_PWRMGMT_STS 0x4D 193 #define BGE_PCI_PWRMGMT_DATA 0x4F 194 #define BGE_PCI_VPD_CAPID 0x50 195 #define BGE_PCI_NEXTPTR_MSI 0x51 196 #define BGE_PCI_VPD_ADDR 0x52 197 #define BGE_PCI_VPD_DATA 0x54 198 #define BGE_PCI_MSI_CAPID 0x58 199 #define BGE_PCI_NEXTPTR_NONE 0x59 200 #define BGE_PCI_MSI_CTL 0x5A 201 #define BGE_PCI_MSI_ADDR_HI 0x5C 202 #define BGE_PCI_MSI_ADDR_LO 0x60 203 #define BGE_PCI_MSI_DATA 0x64 204 205 /* PCI MSI. ??? */ 206 #define BGE_PCIE_CAPID_REG 0xD0 207 #define BGE_PCIE_CAPID 0x10 208 209 /* 210 * PCI registers specific to the BCM570x family. 211 */ 212 #define BGE_PCI_MISC_CTL 0x68 213 #define BGE_PCI_DMA_RW_CTL 0x6C 214 #define BGE_PCI_PCISTATE 0x70 215 #define BGE_PCI_CLKCTL 0x74 216 #define BGE_PCI_REG_BASEADDR 0x78 217 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 218 #define BGE_PCI_REG_DATA 0x80 219 #define BGE_PCI_MEMWIN_DATA 0x84 220 #define BGE_PCI_MODECTL 0x88 221 #define BGE_PCI_MISC_CFG 0x8C 222 #define BGE_PCI_MISC_LOCALCTL 0x90 223 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 224 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 225 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 226 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 227 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 228 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 229 #define BGE_PCI_ISR_MBX_HI 0xB0 230 #define BGE_PCI_ISR_MBX_LO 0xB4 231 #define BGE_PCI_PRODID_ASICREV 0xBC 232 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 233 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 234 235 /* PCI Misc. Host control register */ 236 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 237 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 238 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 239 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 240 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 241 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 242 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 243 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 244 #define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 245 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 246 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16 247 248 #if BYTE_ORDER == LITTLE_ENDIAN 249 #define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\ 250 BGE_MODECTL_BYTESWAP_DATA | \ 251 BGE_MODECTL_WORDSWAP_DATA) 252 #else 253 #define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\ 254 BGE_MODECTL_BYTESWAP_NONFRAME |\ 255 BGE_MODECTL_BYTESWAP_DATA | 256 BGE_MODECTL_WORDSWAP_DATA) 257 #endif 258 259 #define BGE_HIF_SWAP_OPTIONS BGE_PCIMISCCTL_ENDIAN_WORDSWAP 260 #define BGE_INIT (BGE_HIF_SWAP_OPTIONS | \ 261 BGE_PCIMISCCTL_CLEAR_INTA | \ 262 BGE_PCIMISCCTL_MASK_PCI_INTR | \ 263 BGE_PCIMISCCTL_INDIRECT_ACCESS) 264 265 #define BGE_PCISTAT_INTR_NOTACT 0x2 266 267 #define BGE_CHIPID_TIGON_I 0x4000 268 #define BGE_CHIPID_TIGON_II 0x6000 269 #define BGE_CHIPID_BCM5700_A0 0x7000 270 #define BGE_CHIPID_BCM5700_A1 0x7001 271 #define BGE_CHIPID_BCM5700_B0 0x7100 272 #define BGE_CHIPID_BCM5700_B1 0x7101 273 #define BGE_CHIPID_BCM5700_B2 0x7102 274 #define BGE_CHIPID_BCM5700_B3 0x7103 275 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104 276 #define BGE_CHIPID_BCM5700_C0 0x7200 277 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 278 #define BGE_CHIPID_BCM5701_B0 0x0100 279 #define BGE_CHIPID_BCM5701_B2 0x0102 280 #define BGE_CHIPID_BCM5701_B5 0x0105 281 #define BGE_CHIPID_BCM5703_A0 0x1000 282 #define BGE_CHIPID_BCM5703_A1 0x1001 283 #define BGE_CHIPID_BCM5703_A2 0x1002 284 #define BGE_CHIPID_BCM5703_A3 0x1003 285 #define BGE_CHIPID_BCM5703_B0 0x1100 286 #define BGE_CHIPID_BCM5704_A0 0x2000 287 #define BGE_CHIPID_BCM5704_A1 0x2001 288 #define BGE_CHIPID_BCM5704_A2 0x2002 289 #define BGE_CHIPID_BCM5704_A3 0x2003 290 #define BGE_CHIPID_BCM5704_B0 0x2100 291 #define BGE_CHIPID_BCM5705_A0 0x3000 292 #define BGE_CHIPID_BCM5705_A1 0x3001 293 #define BGE_CHIPID_BCM5705_A2 0x3002 294 #define BGE_CHIPID_BCM5705_A3 0x3003 295 #define BGE_CHIPID_BCM5750_A0 0x4000 296 #define BGE_CHIPID_BCM5750_A1 0x4001 297 #define BGE_CHIPID_BCM5750_A3 0x4003 298 #define BGE_CHIPID_BCM5750_B0 0x4100 299 #define BGE_CHIPID_BCM5750_B1 0x4101 300 #define BGE_CHIPID_BCM5750_C0 0x4200 301 #define BGE_CHIPID_BCM5750_C1 0x4201 302 #define BGE_CHIPID_BCM5750_C2 0x4202 303 #define BGE_CHIPID_BCM5714_A0 0x5000 304 #define BGE_CHIPID_BCM5752_A0 0x6000 305 #define BGE_CHIPID_BCM5752_A1 0x6001 306 #define BGE_CHIPID_BCM5752_A2 0x6002 307 #define BGE_CHIPID_BCM5714_B0 0x8000 308 #define BGE_CHIPID_BCM5714_B3 0x8003 309 #define BGE_CHIPID_BCM5715_A0 0x9000 310 #define BGE_CHIPID_BCM5715_A1 0x9001 311 #define BGE_CHIPID_BCM5715_A3 0x9003 312 #define BGE_CHIPID_BCM5722_A0 0xa200 313 #define BGE_CHIPID_BCM5755_A0 0xa000 314 #define BGE_CHIPID_BCM5755_A1 0xa001 315 #define BGE_CHIPID_BCM5755_A2 0xa002 316 #define BGE_CHIPID_BCM5754_A0 0xb000 317 #define BGE_CHIPID_BCM5754_A1 0xb001 318 #define BGE_CHIPID_BCM5754_A2 0xb002 319 #define BGE_CHIPID_BCM5761_A0 0x5761000 320 #define BGE_CHIPID_BCM5761_A1 0x5761100 321 #define BGE_CHIPID_BCM5784_A0 0x5784000 322 #define BGE_CHIPID_BCM5784_A1 0x5784100 323 #define BGE_CHIPID_BCM5787_A0 0xb000 324 #define BGE_CHIPID_BCM5787_A1 0xb001 325 #define BGE_CHIPID_BCM5787_A2 0xb002 326 #define BGE_CHIPID_BCM5906_A0 0xc000 327 #define BGE_CHIPID_BCM5906_A1 0xc001 328 #define BGE_CHIPID_BCM5906_A2 0xc002 329 #define BGE_CHIPID_BCM57780_A0 0x57780000 330 #define BGE_CHIPID_BCM57780_A1 0x57780001 331 #define BGE_CHIPID_BCM5717_A0 0x05717000 332 #define BGE_CHIPID_BCM5717_B0 0x05717100 333 #define BGE_CHIPID_BCM5717_C0 0x05717200 334 #define BGE_CHIPID_BCM5719_A0 0x05719000 335 #define BGE_CHIPID_BCM5720_A0 0x05720000 336 #define BGE_CHIPID_BCM5762_A0 0x05762000 337 #define BGE_CHIPID_BCM57765_A0 0x57785000 338 #define BGE_CHIPID_BCM57765_B0 0x57785100 339 340 /* shorthand one */ 341 #define BGE_ASICREV(x) ((x) >> 12) 342 #define BGE_ASICREV_BCM5701 0x00 343 #define BGE_ASICREV_BCM5703 0x01 344 #define BGE_ASICREV_BCM5704 0x02 345 #define BGE_ASICREV_BCM5705 0x03 346 #define BGE_ASICREV_BCM5750 0x04 347 #define BGE_ASICREV_BCM5714_A0 0x05 348 #define BGE_ASICREV_BCM5752 0x06 349 #define BGE_ASICREV_BCM5700 0x07 350 #define BGE_ASICREV_BCM5780 0x08 351 #define BGE_ASICREV_BCM5714 0x09 352 #define BGE_ASICREV_BCM5755 0x0a 353 #define BGE_ASICREV_BCM5754 0x0b 354 #define BGE_ASICREV_BCM5787 0x0b 355 #define BGE_ASICREV_BCM5906 0x0c 356 357 /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 358 #define BGE_ASICREV_USE_PRODID_REG 0x0f 359 /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 360 #define BGE_ASICREV_BCM5717 0x5717 361 #define BGE_ASICREV_BCM5719 0x5719 362 #define BGE_ASICREV_BCM5720 0x5720 363 #define BGE_ASICREV_BCM5761 0x5761 364 #define BGE_ASICREV_BCM5762 0x5762 365 #define BGE_ASICREV_BCM5784 0x5784 366 #define BGE_ASICREV_BCM5785 0x5785 367 #define BGE_ASICREV_BCM57765 0x57785 368 #define BGE_ASICREV_BCM57766 0x57766 369 #define BGE_ASICREV_BCM57780 0x57780 370 371 /* chip revisions */ 372 #define BGE_CHIPREV(x) ((x) >> 8) 373 #define BGE_CHIPREV_5700_AX 0x70 374 #define BGE_CHIPREV_5700_BX 0x71 375 #define BGE_CHIPREV_5700_CX 0x72 376 #define BGE_CHIPREV_5701_AX 0x00 377 #define BGE_CHIPREV_5703_AX 0x10 378 #define BGE_CHIPREV_5704_AX 0x20 379 #define BGE_CHIPREV_5704_BX 0x21 380 #define BGE_CHIPREV_5750_AX 0x40 381 #define BGE_CHIPREV_5750_BX 0x41 382 /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 383 #define BGE_CHIPREV_5717_AX 0x57170 384 #define BGE_CHIPREV_5717_BX 0x57171 385 #define BGE_CHIPREV_5761_AX 0x57611 386 #define BGE_CHIPREV_5784_AX 0x57841 387 #define BGE_CHIPREV_57765_AX 0x577850 388 389 /* PCI DMA Read/Write Control register */ 390 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 391 #define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 392 #define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 393 #define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 394 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 395 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 396 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 397 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 398 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 399 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 400 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 401 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 402 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 403 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 404 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 405 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 406 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 407 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 408 409 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 410 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 411 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 412 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 413 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 414 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 415 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 416 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 417 418 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 419 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 420 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 421 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 422 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 423 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 424 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 425 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 426 427 /* 428 * PCI state register -- note, this register is read only 429 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 430 * register is set. 431 */ 432 #define BGE_PCISTATE_FORCE_RESET 0x00000001 433 #define BGE_PCISTATE_INTR_STATE 0x00000002 434 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 435 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 436 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 437 #define BGE_PCISTATE_ROM_ENABLE 0x00000020 438 #define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 439 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 440 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 441 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 442 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 443 #define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 444 #define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 445 #define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 446 #define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 447 448 /* 449 * PCI Clock Control register -- note, this register is read only 450 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 451 * register is set. 452 */ 453 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 454 #define BGE_PCICLOCKCTL_M66EN 0x00000080 455 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 456 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 457 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 458 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 459 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 460 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 461 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 462 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 463 464 /* BAR0 (MAC) Register Definitions */ 465 466 /* 467 * High priority mailbox registers 468 * Each mailbox is 64-bits wide, though we only use the 469 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 470 * first. The NIC will load the mailbox after the lower 32 bit word 471 * has been updated. 472 */ 473 #define BGE_MBX_IRQ0_HI 0x0200 474 #define BGE_MBX_IRQ0_LO 0x0204 475 #define BGE_MBX_IRQ1_HI 0x0208 476 #define BGE_MBX_IRQ1_LO 0x020C 477 #define BGE_MBX_IRQ2_HI 0x0210 478 #define BGE_MBX_IRQ2_LO 0x0214 479 #define BGE_MBX_IRQ3_HI 0x0218 480 #define BGE_MBX_IRQ3_LO 0x021C 481 #define BGE_MBX_GEN0_HI 0x0220 482 #define BGE_MBX_GEN0_LO 0x0224 483 #define BGE_MBX_GEN1_HI 0x0228 484 #define BGE_MBX_GEN1_LO 0x022C 485 #define BGE_MBX_GEN2_HI 0x0230 486 #define BGE_MBX_GEN2_LO 0x0234 487 #define BGE_MBX_GEN3_HI 0x0228 488 #define BGE_MBX_GEN3_LO 0x022C 489 #define BGE_MBX_GEN4_HI 0x0240 490 #define BGE_MBX_GEN4_LO 0x0244 491 #define BGE_MBX_GEN5_HI 0x0248 492 #define BGE_MBX_GEN5_LO 0x024C 493 #define BGE_MBX_GEN6_HI 0x0250 494 #define BGE_MBX_GEN6_LO 0x0254 495 #define BGE_MBX_GEN7_HI 0x0258 496 #define BGE_MBX_GEN7_LO 0x025C 497 #define BGE_MBX_RELOAD_STATS_HI 0x0260 498 #define BGE_MBX_RELOAD_STATS_LO 0x0264 499 #define BGE_MBX_RX_STD_PROD_HI 0x0268 500 #define BGE_MBX_RX_STD_PROD_LO 0x026C 501 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 502 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 503 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 504 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 505 #define BGE_MBX_RX_CONS0_HI 0x0280 506 #define BGE_MBX_RX_CONS0_LO 0x0284 507 #define BGE_MBX_RX_CONS1_HI 0x0288 508 #define BGE_MBX_RX_CONS1_LO 0x028C 509 #define BGE_MBX_RX_CONS2_HI 0x0290 510 #define BGE_MBX_RX_CONS2_LO 0x0294 511 #define BGE_MBX_RX_CONS3_HI 0x0298 512 #define BGE_MBX_RX_CONS3_LO 0x029C 513 #define BGE_MBX_RX_CONS4_HI 0x02A0 514 #define BGE_MBX_RX_CONS4_LO 0x02A4 515 #define BGE_MBX_RX_CONS5_HI 0x02A8 516 #define BGE_MBX_RX_CONS5_LO 0x02AC 517 #define BGE_MBX_RX_CONS6_HI 0x02B0 518 #define BGE_MBX_RX_CONS6_LO 0x02B4 519 #define BGE_MBX_RX_CONS7_HI 0x02B8 520 #define BGE_MBX_RX_CONS7_LO 0x02BC 521 #define BGE_MBX_RX_CONS8_HI 0x02C0 522 #define BGE_MBX_RX_CONS8_LO 0x02C4 523 #define BGE_MBX_RX_CONS9_HI 0x02C8 524 #define BGE_MBX_RX_CONS9_LO 0x02CC 525 #define BGE_MBX_RX_CONS10_HI 0x02D0 526 #define BGE_MBX_RX_CONS10_LO 0x02D4 527 #define BGE_MBX_RX_CONS11_HI 0x02D8 528 #define BGE_MBX_RX_CONS11_LO 0x02DC 529 #define BGE_MBX_RX_CONS12_HI 0x02E0 530 #define BGE_MBX_RX_CONS12_LO 0x02E4 531 #define BGE_MBX_RX_CONS13_HI 0x02E8 532 #define BGE_MBX_RX_CONS13_LO 0x02EC 533 #define BGE_MBX_RX_CONS14_HI 0x02F0 534 #define BGE_MBX_RX_CONS14_LO 0x02F4 535 #define BGE_MBX_RX_CONS15_HI 0x02F8 536 #define BGE_MBX_RX_CONS15_LO 0x02FC 537 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 538 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 539 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 540 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 541 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 542 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 543 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 544 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 545 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 546 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 547 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 548 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 549 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 550 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 551 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 552 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 553 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 554 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 555 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 556 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 557 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 558 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 559 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 560 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 561 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 562 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 563 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 564 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 565 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 566 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 567 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 568 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 569 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 570 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 571 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 572 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 573 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 574 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 575 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 576 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 577 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 578 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 579 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 580 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 581 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 582 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 583 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 584 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 585 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 586 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 587 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 588 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 589 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 590 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 591 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 592 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 593 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 594 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 595 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 596 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 597 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 598 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 599 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 600 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 601 602 #define BGE_TX_RINGS_MAX 4 603 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 604 #define BGE_RX_RINGS_MAX 16 605 #define BGE_RX_RINGS_MAX_5717 17 606 607 /* Ethernet MAC control registers */ 608 #define BGE_MAC_MODE 0x0400 609 #define BGE_MAC_STS 0x0404 610 #define BGE_MAC_EVT_ENB 0x0408 611 #define BGE_MAC_LED_CTL 0x040C 612 #define BGE_MAC_ADDR1_LO 0x0410 613 #define BGE_MAC_ADDR1_HI 0x0414 614 #define BGE_MAC_ADDR2_LO 0x0418 615 #define BGE_MAC_ADDR2_HI 0x041C 616 #define BGE_MAC_ADDR3_LO 0x0420 617 #define BGE_MAC_ADDR3_HI 0x0424 618 #define BGE_MAC_ADDR4_LO 0x0428 619 #define BGE_MAC_ADDR4_HI 0x042C 620 #define BGE_WOL_PATPTR 0x0430 621 #define BGE_WOL_PATCFG 0x0434 622 #define BGE_TX_RANDOM_BACKOFF 0x0438 623 #define BGE_RX_MTU 0x043C 624 #define BGE_GBIT_PCS_TEST 0x0440 625 #define BGE_TX_TBI_AUTONEG 0x0444 626 #define BGE_RX_TBI_AUTONEG 0x0448 627 #define BGE_MI_COMM 0x044C 628 #define BGE_MI_STS 0x0450 629 #define BGE_MI_MODE 0x0454 630 #define BGE_AUTOPOLL_STS 0x0458 631 #define BGE_TX_MODE 0x045C 632 #define BGE_TX_STS 0x0460 633 #define BGE_TX_LENGTHS 0x0464 634 #define BGE_RX_MODE 0x0468 635 #define BGE_RX_STS 0x046C 636 #define BGE_MAR0 0x0470 637 #define BGE_MAR1 0x0474 638 #define BGE_MAR2 0x0478 639 #define BGE_MAR3 0x047C 640 #define BGE_RX_BD_RULES_CTL0 0x0480 641 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 642 #define BGE_RX_BD_RULES_CTL1 0x0488 643 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 644 #define BGE_RX_BD_RULES_CTL2 0x0490 645 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 646 #define BGE_RX_BD_RULES_CTL3 0x0498 647 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 648 #define BGE_RX_BD_RULES_CTL4 0x04A0 649 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 650 #define BGE_RX_BD_RULES_CTL5 0x04A8 651 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 652 #define BGE_RX_BD_RULES_CTL6 0x04B0 653 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 654 #define BGE_RX_BD_RULES_CTL7 0x04B8 655 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 656 #define BGE_RX_BD_RULES_CTL8 0x04C0 657 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 658 #define BGE_RX_BD_RULES_CTL9 0x04C8 659 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 660 #define BGE_RX_BD_RULES_CTL10 0x04D0 661 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 662 #define BGE_RX_BD_RULES_CTL11 0x04D8 663 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 664 #define BGE_RX_BD_RULES_CTL12 0x04E0 665 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 666 #define BGE_RX_BD_RULES_CTL13 0x04E8 667 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 668 #define BGE_RX_BD_RULES_CTL14 0x04F0 669 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 670 #define BGE_RX_BD_RULES_CTL15 0x04F8 671 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 672 #define BGE_RX_RULES_CFG 0x0500 673 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 674 #define BGE_SERDES_CFG 0x0590 675 #define BGE_SERDES_STS 0x0594 676 #define BGE_SGDIG_CFG 0x05B0 677 #define BGE_SGDIG_STS 0x05B4 678 #define BGE_RSS_INDIR_TBL0 0x0630 679 #define BGE_RSS_KEYREG0 0x0670 680 #define BGE_RX_STATS 0x0800 681 #define BGE_TX_STATS 0x0880 682 683 /* Ethernet MAC Mode register */ 684 #define BGE_MACMODE_RESET 0x00000001 685 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 686 #define BGE_MACMODE_PORTMODE 0x0000000C 687 #define BGE_MACMODE_LOOPBACK 0x00000010 688 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 689 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 690 #define BGE_MACMODE_MAX_DEFER 0x00000200 691 #define BGE_MACMODE_LINK_POLARITY 0x00000400 692 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 693 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 694 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 695 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 696 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 697 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 698 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 699 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 700 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 701 #define BGE_MACMODE_MIP_ENB 0x00100000 702 #define BGE_MACMODE_TXDMA_ENB 0x00200000 703 #define BGE_MACMODE_RXDMA_ENB 0x00400000 704 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 705 #define BGE_MACMODE_APE_RX_EN 0x08000000 706 #define BGE_MACMODE_APE_TX_EN 0x10000000 707 708 #define BGE_PORTMODE_NONE 0x00000000 709 #define BGE_PORTMODE_MII 0x00000004 710 #define BGE_PORTMODE_GMII 0x00000008 711 #define BGE_PORTMODE_TBI 0x0000000C 712 713 /* MAC Status register */ 714 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 715 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 716 #define BGE_MACSTAT_RX_CFG 0x00000004 717 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 718 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 719 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 720 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 721 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 722 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 723 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 724 #define BGE_MACSTAT_ODI_ERROR 0x02000000 725 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 726 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 727 728 /* MAC Event Enable Register */ 729 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 730 #define BGE_EVTENB_LINK_CHANGED 0x00001000 731 #define BGE_EVTENB_MI_COMPLETE 0x00400000 732 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 733 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 734 #define BGE_EVTENB_ODI_ERROR 0x02000000 735 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 736 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 737 738 /* LED Control Register */ 739 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 740 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 741 #define BGE_LEDCTL_100MBPS_LED 0x00000004 742 #define BGE_LEDCTL_10MBPS_LED 0x00000008 743 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 744 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 745 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 746 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 747 #define BGE_LEDCTL_100MBPS_STS 0x00000100 748 #define BGE_LEDCTL_10MBPS_STS 0x00000200 749 #define BGE_LEDCTL_TRADLED_STS 0x00000400 750 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 751 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 752 753 /* TX backoff seed register */ 754 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 755 756 /* Autopoll status register */ 757 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 758 759 /* Transmit MAC mode register */ 760 #define BGE_TXMODE_RESET 0x00000001 761 #define BGE_TXMODE_ENABLE 0x00000002 762 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 763 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 764 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 765 #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 766 #define BGE_TXMODE_JMB_FRM_LEN 0x00400000 767 #define BGE_TXMODE_CNT_DN_MODE 0x00800000 768 769 /* Transmit MAC status register */ 770 #define BGE_TXSTAT_RX_XOFFED 0x00000001 771 #define BGE_TXSTAT_SENT_XOFF 0x00000002 772 #define BGE_TXSTAT_SENT_XON 0x00000004 773 #define BGE_TXSTAT_LINK_UP 0x00000008 774 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 775 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 776 777 /* Transmit MAC lengths register */ 778 #define BGE_TXLEN_SLOTTIME 0x000000FF 779 #define BGE_TXLEN_IPG 0x00000F00 780 #define BGE_TXLEN_CRS 0x00003000 781 #define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 782 #define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 783 784 /* Receive MAC mode register */ 785 #define BGE_RXMODE_RESET 0x00000001 786 #define BGE_RXMODE_ENABLE 0x00000002 787 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 788 #define BGE_RXMODE_RX_GIANTS 0x00000020 789 #define BGE_RXMODE_RX_RUNTS 0x00000040 790 #define BGE_RXMODE_8022_LENCHECK 0x00000080 791 #define BGE_RXMODE_RX_PROMISC 0x00000100 792 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 793 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 794 #define BGE_RXMODE_RSS_IPV4_HASH 0x00010000 795 #define BGE_RXMODE_RSS_TCP_IPV4_HASH 0x00020000 796 #define BGE_RXMODE_RSS_IPV6_HASH 0x00040000 797 #define BGE_RXMODE_RSS_TCP_IPV6_HASH 0x00080000 798 #define BGE_RXMODE_RSS_HASH_MASK_BITS 0x00700000 799 #define BGE_RXMODE_RSS_ENABLE 0x00800000 800 #define BGE_RXMODE_IPV6_ENABLE 0x01000000 801 #define BGE_RXMODE_IPV4_FRAG_FIX 0x02000000 802 803 /* Receive MAC status register */ 804 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 805 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 806 #define BGE_RXSTAT_RCVD_XON 0x00000004 807 808 /* Receive Rules Control register */ 809 #define BGE_RXRULECTL_OFFSET 0x000000FF 810 #define BGE_RXRULECTL_CLASS 0x00001F00 811 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 812 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 813 #define BGE_RXRULECTL_MAP 0x01000000 814 #define BGE_RXRULECTL_DISCARD 0x02000000 815 #define BGE_RXRULECTL_MASK 0x04000000 816 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 817 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 818 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 819 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 820 821 /* Receive Rules Mask register */ 822 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 823 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 824 825 /* SERDES configuration register */ 826 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 827 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 828 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 829 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 830 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 831 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 832 #define BGE_SERDESCFG_TXMODE 0x00001000 833 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 834 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 835 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 836 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 837 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 838 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 839 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 840 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 841 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 842 843 /* SERDES status register */ 844 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 845 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 846 847 /* SGDIG config (not documented) */ 848 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 849 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 850 #define BGE_SGDIGCFG_SEND 0x40000000 851 #define BGE_SGDIGCFG_AUTO 0x80000000 852 853 /* SGDIG status (not documented) */ 854 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 855 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 856 #define BGE_SGDIGSTS_DONE 0x00000002 857 #define BGE_SGDIGSTS_IS_SERDES 0x00000100 858 859 /* MI communication register */ 860 #define BGE_MICOMM_DATA 0x0000FFFF 861 #define BGE_MICOMM_REG 0x001F0000 862 #define BGE_MICOMM_PHY 0x03E00000 863 #define BGE_MICOMM_CMD 0x0C000000 864 #define BGE_MICOMM_READFAIL 0x10000000 865 #define BGE_MICOMM_BUSY 0x20000000 866 867 #define BGE_MIREG(x) ((x & 0x1F) << 16) 868 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 869 #define BGE_MICMD_WRITE 0x04000000 870 #define BGE_MICMD_READ 0x08000000 871 872 /* MI status register */ 873 #define BGE_MISTS_LINK 0x00000001 874 #define BGE_MISTS_10MBPS 0x00000002 875 876 #define BGE_MIMODE_CLK_10MHZ 0x00000001 877 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 878 #define BGE_MIMODE_AUTOPOLL 0x00000010 879 #define BGE_MIMODE_CLKCNT 0x001F0000 880 #define BGE_MIMODE_500KHZ_CONST 0x00008000 881 #define BGE_MIMODE_BASE 0x000C0000 882 883 /* RSS key registers */ 884 #define BGE_RSS_KEYREG_CNT 10 885 #define BGE_RSS_KEYREG_SIZE 4 886 #define BGE_RSS_KEYREG(i) (BGE_RSS_KEYREG0 + \ 887 ((i) * BGE_RSS_KEYREG_SIZE)) 888 #define BGE_RSS_KEYREG_VAL(k, x) \ 889 (k[(x) * BGE_RSS_KEYREG_SIZE] << 24 | \ 890 k[(x) * BGE_RSS_KEYREG_SIZE + 1] << 16 | \ 891 k[(x) * BGE_RSS_KEYREG_SIZE + 2] << 8 | \ 892 k[(x) * BGE_RSS_KEYREG_SIZE + 3]) 893 894 /* RSS indirect table registers */ 895 #define BGE_RSS_INDIR_TBLENT_CNT 8 896 #define BGE_RSS_INDIR_TBLENT_SHIFT 4 897 #define BGE_RSS_INDIR_TBL_CNT 16 898 #define BGE_RSS_INDIR_TBL_SIZE 4 899 #define BGE_RSS_INDIR_TBL(i) (BGE_RSS_INDIR_TBL0 + \ 900 ((i) * BGE_RSS_INDIR_TBL_SIZE)) 901 902 /* 903 * Send data initiator control registers. 904 */ 905 #define BGE_SDI_MODE 0x0C00 906 #define BGE_SDI_STATUS 0x0C04 907 #define BGE_SDI_STATS_CTL 0x0C08 908 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 909 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 910 #define BGE_ISO_PKT_TX 0x0C20 911 #define BGE_LOCSTATS_COS0 0x0C80 912 #define BGE_LOCSTATS_COS1 0x0C84 913 #define BGE_LOCSTATS_COS2 0x0C88 914 #define BGE_LOCSTATS_COS3 0x0C8C 915 #define BGE_LOCSTATS_COS4 0x0C90 916 #define BGE_LOCSTATS_COS5 0x0C84 917 #define BGE_LOCSTATS_COS6 0x0C98 918 #define BGE_LOCSTATS_COS7 0x0C9C 919 #define BGE_LOCSTATS_COS8 0x0CA0 920 #define BGE_LOCSTATS_COS9 0x0CA4 921 #define BGE_LOCSTATS_COS10 0x0CA8 922 #define BGE_LOCSTATS_COS11 0x0CAC 923 #define BGE_LOCSTATS_COS12 0x0CB0 924 #define BGE_LOCSTATS_COS13 0x0CB4 925 #define BGE_LOCSTATS_COS14 0x0CB8 926 #define BGE_LOCSTATS_COS15 0x0CBC 927 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 928 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 929 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 930 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 931 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 932 #define BGE_LOCSTATS_IRQS 0x0CD4 933 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 934 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 935 936 /* Send Data Initiator mode register */ 937 #define BGE_SDIMODE_RESET 0x00000001 938 #define BGE_SDIMODE_ENABLE 0x00000002 939 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 940 #define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 941 942 /* Send Data Initiator stats register */ 943 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 944 945 /* Send Data Initiator stats control register */ 946 #define BGE_SDISTATSCTL_ENABLE 0x00000001 947 #define BGE_SDISTATSCTL_FASTER 0x00000002 948 #define BGE_SDISTATSCTL_CLEAR 0x00000004 949 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 950 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 951 952 /* 953 * Send Data Completion Control registers 954 */ 955 #define BGE_SDC_MODE 0x1000 956 #define BGE_SDC_STATUS 0x1004 957 958 /* Send Data completion mode register */ 959 #define BGE_SDCMODE_RESET 0x00000001 960 #define BGE_SDCMODE_ENABLE 0x00000002 961 #define BGE_SDCMODE_ATTN 0x00000004 962 #define BGE_SDCMODE_CDELAY 0x00000010 963 964 /* Send Data completion status register */ 965 #define BGE_SDCSTAT_ATTN 0x00000004 966 967 /* 968 * Send BD Ring Selector Control registers 969 */ 970 #define BGE_SRS_MODE 0x1400 971 #define BGE_SRS_STATUS 0x1404 972 #define BGE_SRS_HWDIAG 0x1408 973 #define BGE_SRS_LOC_NIC_CONS0 0x1440 974 #define BGE_SRS_LOC_NIC_CONS1 0x1444 975 #define BGE_SRS_LOC_NIC_CONS2 0x1448 976 #define BGE_SRS_LOC_NIC_CONS3 0x144C 977 #define BGE_SRS_LOC_NIC_CONS4 0x1450 978 #define BGE_SRS_LOC_NIC_CONS5 0x1454 979 #define BGE_SRS_LOC_NIC_CONS6 0x1458 980 #define BGE_SRS_LOC_NIC_CONS7 0x145C 981 #define BGE_SRS_LOC_NIC_CONS8 0x1460 982 #define BGE_SRS_LOC_NIC_CONS9 0x1464 983 #define BGE_SRS_LOC_NIC_CONS10 0x1468 984 #define BGE_SRS_LOC_NIC_CONS11 0x146C 985 #define BGE_SRS_LOC_NIC_CONS12 0x1470 986 #define BGE_SRS_LOC_NIC_CONS13 0x1474 987 #define BGE_SRS_LOC_NIC_CONS14 0x1478 988 #define BGE_SRS_LOC_NIC_CONS15 0x147C 989 990 /* Send BD Ring Selector Mode register */ 991 #define BGE_SRSMODE_RESET 0x00000001 992 #define BGE_SRSMODE_ENABLE 0x00000002 993 #define BGE_SRSMODE_ATTN 0x00000004 994 995 /* Send BD Ring Selector Status register */ 996 #define BGE_SRSSTAT_ERROR 0x00000004 997 998 /* Send BD Ring Selector HW Diagnostics register */ 999 #define BGE_SRSHWDIAG_STATE 0x0000000F 1000 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1001 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1002 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1003 1004 /* 1005 * Send BD Initiator Selector Control registers 1006 */ 1007 #define BGE_SBDI_MODE 0x1800 1008 #define BGE_SBDI_STATUS 0x1804 1009 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 1010 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 1011 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 1012 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 1013 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 1014 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 1015 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 1016 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 1017 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 1018 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 1019 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 1020 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 1021 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 1022 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 1023 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 1024 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 1025 1026 /* Send BD Initiator Mode register */ 1027 #define BGE_SBDIMODE_RESET 0x00000001 1028 #define BGE_SBDIMODE_ENABLE 0x00000002 1029 #define BGE_SBDIMODE_ATTN 0x00000004 1030 #define BGE_SBDIMODE_MULTI_TXR 0x00000020 1031 1032 /* Send BD Initiator Status register */ 1033 #define BGE_SBDISTAT_ERROR 0x00000004 1034 1035 /* 1036 * Send BD Completion Control registers 1037 */ 1038 #define BGE_SBDC_MODE 0x1C00 1039 #define BGE_SBDC_STATUS 0x1C04 1040 1041 /* Send BD Completion Control Mode register */ 1042 #define BGE_SBDCMODE_RESET 0x00000001 1043 #define BGE_SBDCMODE_ENABLE 0x00000002 1044 #define BGE_SBDCMODE_ATTN 0x00000004 1045 1046 /* Send BD Completion Control Status register */ 1047 #define BGE_SBDCSTAT_ATTN 0x00000004 1048 1049 /* 1050 * Receive List Placement Control registers 1051 */ 1052 #define BGE_RXLP_MODE 0x2000 1053 #define BGE_RXLP_STATUS 0x2004 1054 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 1055 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1056 #define BGE_RXLP_CFG 0x2010 1057 #define BGE_RXLP_STATS_CTL 0x2014 1058 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1059 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1060 #define BGE_RXLP_HEAD0 0x2100 1061 #define BGE_RXLP_TAIL0 0x2104 1062 #define BGE_RXLP_COUNT0 0x2108 1063 #define BGE_RXLP_HEAD1 0x2110 1064 #define BGE_RXLP_TAIL1 0x2114 1065 #define BGE_RXLP_COUNT1 0x2118 1066 #define BGE_RXLP_HEAD2 0x2120 1067 #define BGE_RXLP_TAIL2 0x2124 1068 #define BGE_RXLP_COUNT2 0x2128 1069 #define BGE_RXLP_HEAD3 0x2130 1070 #define BGE_RXLP_TAIL3 0x2134 1071 #define BGE_RXLP_COUNT3 0x2138 1072 #define BGE_RXLP_HEAD4 0x2140 1073 #define BGE_RXLP_TAIL4 0x2144 1074 #define BGE_RXLP_COUNT4 0x2148 1075 #define BGE_RXLP_HEAD5 0x2150 1076 #define BGE_RXLP_TAIL5 0x2154 1077 #define BGE_RXLP_COUNT5 0x2158 1078 #define BGE_RXLP_HEAD6 0x2160 1079 #define BGE_RXLP_TAIL6 0x2164 1080 #define BGE_RXLP_COUNT6 0x2168 1081 #define BGE_RXLP_HEAD7 0x2170 1082 #define BGE_RXLP_TAIL7 0x2174 1083 #define BGE_RXLP_COUNT7 0x2178 1084 #define BGE_RXLP_HEAD8 0x2180 1085 #define BGE_RXLP_TAIL8 0x2184 1086 #define BGE_RXLP_COUNT8 0x2188 1087 #define BGE_RXLP_HEAD9 0x2190 1088 #define BGE_RXLP_TAIL9 0x2194 1089 #define BGE_RXLP_COUNT9 0x2198 1090 #define BGE_RXLP_HEAD10 0x21A0 1091 #define BGE_RXLP_TAIL10 0x21A4 1092 #define BGE_RXLP_COUNT10 0x21A8 1093 #define BGE_RXLP_HEAD11 0x21B0 1094 #define BGE_RXLP_TAIL11 0x21B4 1095 #define BGE_RXLP_COUNT11 0x21B8 1096 #define BGE_RXLP_HEAD12 0x21C0 1097 #define BGE_RXLP_TAIL12 0x21C4 1098 #define BGE_RXLP_COUNT12 0x21C8 1099 #define BGE_RXLP_HEAD13 0x21D0 1100 #define BGE_RXLP_TAIL13 0x21D4 1101 #define BGE_RXLP_COUNT13 0x21D8 1102 #define BGE_RXLP_HEAD14 0x21E0 1103 #define BGE_RXLP_TAIL14 0x21E4 1104 #define BGE_RXLP_COUNT14 0x21E8 1105 #define BGE_RXLP_HEAD15 0x21F0 1106 #define BGE_RXLP_TAIL15 0x21F4 1107 #define BGE_RXLP_COUNT15 0x21F8 1108 #define BGE_RXLP_LOCSTAT_COS0 0x2200 1109 #define BGE_RXLP_LOCSTAT_COS1 0x2204 1110 #define BGE_RXLP_LOCSTAT_COS2 0x2208 1111 #define BGE_RXLP_LOCSTAT_COS3 0x220C 1112 #define BGE_RXLP_LOCSTAT_COS4 0x2210 1113 #define BGE_RXLP_LOCSTAT_COS5 0x2214 1114 #define BGE_RXLP_LOCSTAT_COS6 0x2218 1115 #define BGE_RXLP_LOCSTAT_COS7 0x221C 1116 #define BGE_RXLP_LOCSTAT_COS8 0x2220 1117 #define BGE_RXLP_LOCSTAT_COS9 0x2224 1118 #define BGE_RXLP_LOCSTAT_COS10 0x2228 1119 #define BGE_RXLP_LOCSTAT_COS11 0x222C 1120 #define BGE_RXLP_LOCSTAT_COS12 0x2230 1121 #define BGE_RXLP_LOCSTAT_COS13 0x2234 1122 #define BGE_RXLP_LOCSTAT_COS14 0x2238 1123 #define BGE_RXLP_LOCSTAT_COS15 0x223C 1124 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1125 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1126 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1127 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1128 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1129 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1130 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1131 1132 1133 /* Receive List Placement mode register */ 1134 #define BGE_RXLPMODE_RESET 0x00000001 1135 #define BGE_RXLPMODE_ENABLE 0x00000002 1136 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1137 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1138 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1139 1140 /* Receive List Placement Status register */ 1141 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1142 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1143 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1144 1145 /* 1146 * Receive Data and Receive BD Initiator Control Registers 1147 */ 1148 #define BGE_RDBDI_MODE 0x2400 1149 #define BGE_RDBDI_STATUS 0x2404 1150 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1151 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1152 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1153 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1154 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1155 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1156 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1157 #define BGE_RX_STD_RCB_NICADDR 0x245C 1158 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1159 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1160 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1161 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1162 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1163 #define BGE_RDBDI_STD_RX_CONS 0x2474 1164 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1165 #define BGE_RDBDI_RETURN_PROD0 0x2480 1166 #define BGE_RDBDI_RETURN_PROD1 0x2484 1167 #define BGE_RDBDI_RETURN_PROD2 0x2488 1168 #define BGE_RDBDI_RETURN_PROD3 0x248C 1169 #define BGE_RDBDI_RETURN_PROD4 0x2490 1170 #define BGE_RDBDI_RETURN_PROD5 0x2494 1171 #define BGE_RDBDI_RETURN_PROD6 0x2498 1172 #define BGE_RDBDI_RETURN_PROD7 0x249C 1173 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1174 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1175 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1176 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1177 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1178 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1179 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1180 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1181 #define BGE_RDBDI_HWDIAG 0x24C0 1182 1183 1184 /* Receive Data and Receive BD Initiator Mode register */ 1185 #define BGE_RDBDIMODE_RESET 0x00000001 1186 #define BGE_RDBDIMODE_ENABLE 0x00000002 1187 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1188 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1189 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1190 1191 /* Receive Data and Receive BD Initiator Status register */ 1192 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1193 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1194 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1195 1196 1197 /* 1198 * Receive Data Completion Control registers 1199 */ 1200 #define BGE_RDC_MODE 0x2800 1201 1202 /* Receive Data Completion Mode register */ 1203 #define BGE_RDCMODE_RESET 0x00000001 1204 #define BGE_RDCMODE_ENABLE 0x00000002 1205 #define BGE_RDCMODE_ATTN 0x00000004 1206 1207 /* 1208 * Receive BD Initiator Control registers 1209 */ 1210 #define BGE_RBDI_MODE 0x2C00 1211 #define BGE_RBDI_STATUS 0x2C04 1212 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1213 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1214 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1215 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1216 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1217 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1218 1219 #define BGE_STD_REPLENISH_LWM 0x2D00 1220 #define BGE_JMB_REPLENISH_LWM 0x2D04 1221 1222 /* Receive BD Initiator Mode register */ 1223 #define BGE_RBDIMODE_RESET 0x00000001 1224 #define BGE_RBDIMODE_ENABLE 0x00000002 1225 #define BGE_RBDIMODE_ATTN 0x00000004 1226 1227 /* Receive BD Initiator Status register */ 1228 #define BGE_RBDISTAT_ATTN 0x00000004 1229 1230 /* 1231 * Receive BD Completion Control registers 1232 */ 1233 #define BGE_RBDC_MODE 0x3000 1234 #define BGE_RBDC_STATUS 0x3004 1235 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1236 #define BGE_RBDC_STD_BD_PROD 0x300C 1237 #define BGE_RBDC_MINI_BD_PROD 0x3010 1238 1239 /* Receive BD completion mode register */ 1240 #define BGE_RBDCMODE_RESET 0x00000001 1241 #define BGE_RBDCMODE_ENABLE 0x00000002 1242 #define BGE_RBDCMODE_ATTN 0x00000004 1243 1244 /* Receive BD completion status register */ 1245 #define BGE_RBDCSTAT_ERROR 0x00000004 1246 1247 /* 1248 * Receive List Selector Control registers 1249 */ 1250 #define BGE_RXLS_MODE 0x3400 1251 #define BGE_RXLS_STATUS 0x3404 1252 1253 /* Receive List Selector Mode register */ 1254 #define BGE_RXLSMODE_RESET 0x00000001 1255 #define BGE_RXLSMODE_ENABLE 0x00000002 1256 #define BGE_RXLSMODE_ATTN 0x00000004 1257 1258 /* Receive List Selector Status register */ 1259 #define BGE_RXLSSTAT_ERROR 0x00000004 1260 1261 #define BGE_CPMU_CTRL 0x3600 1262 #define BGE_CPMU_LSPD_10MB_CLK 0x3604 1263 #define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1264 #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1265 #define BGE_CPMU_HST_ACC 0x361C 1266 #define BGE_CPMU_CLCK_STAT 0x3630 1267 #define BGE_CPMU_CLCK_ORIDE 0x3624 1268 #define BGE_CPMU_MUTEX_REQ 0x365C 1269 #define BGE_CPMU_MUTEX_GNT 0x3660 1270 #define BGE_CPMU_PHY_STRAP 0x3664 1271 #define BGE_CPMU_PADRNG_CTL 0x3668 1272 1273 /* Central Power Management Unit (CPMU) register */ 1274 #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1275 #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1276 #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1277 #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1278 1279 /* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1280 #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1281 #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1282 1283 /* Link Speed 1000MB Power Mode Clock Policy register */ 1284 #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1285 #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1286 #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1287 1288 /* Link Aware Power Mode Clock Policy register */ 1289 #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1290 #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1291 1292 #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1293 #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1294 1295 /* Clock Speed Override Policy register */ 1296 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1297 1298 /* CPMU Clock Status register */ 1299 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1300 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1301 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1302 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1303 1304 /* CPMU Mutex Request register */ 1305 #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1306 #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1307 1308 /* CPMU GPHY Strap register */ 1309 #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1310 1311 /* CPMU Padring Control register */ 1312 #define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1313 1314 /* 1315 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1316 */ 1317 #define BGE_MBCF_MODE 0x3800 1318 #define BGE_MBCF_STATUS 0x3804 1319 1320 /* Mbuf Cluster Free mode register */ 1321 #define BGE_MBCFMODE_RESET 0x00000001 1322 #define BGE_MBCFMODE_ENABLE 0x00000002 1323 #define BGE_MBCFMODE_ATTN 0x00000004 1324 1325 /* Mbuf Cluster Free status register */ 1326 #define BGE_MBCFSTAT_ERROR 0x00000004 1327 1328 /* 1329 * Host Coalescing Control registers 1330 */ 1331 #define BGE_HCC_MODE 0x3C00 1332 #define BGE_HCC_STATUS 0x3C04 1333 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1334 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1335 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1336 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1337 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1338 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1339 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1340 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1341 #define BGE_HCC_STATS_TICKS 0x3C28 1342 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1343 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1344 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1345 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1346 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1347 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1348 #define BGE_FLOW_ATTN 0x3C48 1349 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1350 #define BGE_HCC_STD_BD_CONS 0x3C54 1351 #define BGE_HCC_MINI_BD_CONS 0x3C58 1352 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1353 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1354 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1355 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1356 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1357 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1358 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1359 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1360 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1361 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1362 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1363 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1364 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1365 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1366 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1367 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1368 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1369 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1370 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1371 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1372 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1373 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1374 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1375 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1376 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1377 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1378 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1379 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1380 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1381 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1382 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1383 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1384 1385 1386 /* Host coalescing mode register */ 1387 #define BGE_HCCMODE_RESET 0x00000001 1388 #define BGE_HCCMODE_ENABLE 0x00000002 1389 #define BGE_HCCMODE_ATTN 0x00000004 1390 #define BGE_HCCMODE_COAL_NOW 0x00000008 1391 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1392 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1393 #define BGE_HCCMODE_CLRTICK_RX 0x00000200 1394 #define BGE_HCCMODE_CLRTICK_TX 0x00000400 1395 1396 #define BGE_STATBLKSZ_FULL 0x00000000 1397 #define BGE_STATBLKSZ_64BYTE 0x00000080 1398 #define BGE_STATBLKSZ_32BYTE 0x00000100 1399 1400 /* Host coalescing status register */ 1401 #define BGE_HCCSTAT_ERROR 0x00000004 1402 1403 /* Flow attention register */ 1404 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1405 #define BGE_FLOWATTN_MEMARB 0x00000080 1406 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1407 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1408 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1409 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1410 #define BGE_FLOWATTN_RDBDI 0x00080000 1411 #define BGE_FLOWATTN_RXLS 0x00100000 1412 #define BGE_FLOWATTN_RXLP 0x00200000 1413 #define BGE_FLOWATTN_RBDC 0x00400000 1414 #define BGE_FLOWATTN_RBDI 0x00800000 1415 #define BGE_FLOWATTN_SDC 0x08000000 1416 #define BGE_FLOWATTN_SDI 0x10000000 1417 #define BGE_FLOWATTN_SRS 0x20000000 1418 #define BGE_FLOWATTN_SBDC 0x40000000 1419 #define BGE_FLOWATTN_SBDI 0x80000000 1420 1421 #define BGE_VEC1_STATUSBLK_ADDR_HI 0x3D00 1422 #define BGE_VEC1_STATUSBLK_ADDR_LO 0x3D04 1423 1424 #define BGE_VEC1_RX_COAL_TICKS 0x3D80 1425 #define BGE_VEC1_TX_COAL_TICKS 0x3D84 1426 #define BGE_VEC1_RX_MAX_COAL_BDS 0x3D88 1427 #define BGE_VEC1_TX_MAX_COAL_BDS 0x3D8C 1428 #define BGE_VEC1_RX_MAX_COAL_BDS_INT 0x3D90 /* BDs during interrupt */ 1429 #define BGE_VEC1_TX_MAX_COAL_BDS_INT 0x3D94 /* BDs during interrupt */ 1430 1431 #define BGE_VEC_COALSET_SIZE 24 1432 1433 /* 1434 * Memory arbiter registers 1435 */ 1436 #define BGE_MARB_MODE 0x4000 1437 #define BGE_MARB_STATUS 0x4004 1438 #define BGE_MARB_TRAPADDR_HI 0x4008 1439 #define BGE_MARB_TRAPADDR_LO 0x400C 1440 1441 /* Memory arbiter mode register */ 1442 #define BGE_MARBMODE_RESET 0x00000001 1443 #define BGE_MARBMODE_ENABLE 0x00000002 1444 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1445 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1446 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1447 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1448 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1449 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1450 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1451 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1452 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1453 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1454 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1455 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1456 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1457 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1458 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1459 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1460 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1461 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1462 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1463 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1464 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1465 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1466 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1467 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1468 1469 /* Memory arbiter status register */ 1470 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1471 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1472 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1473 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1474 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1475 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1476 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1477 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1478 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1479 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1480 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1481 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1482 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1483 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1484 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1485 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1486 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1487 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1488 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1489 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1490 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1491 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1492 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1493 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1494 1495 /* 1496 * Buffer manager control registers 1497 */ 1498 #define BGE_BMAN_MODE 0x4400 1499 #define BGE_BMAN_STATUS 0x4404 1500 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1501 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1502 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1503 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1504 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1505 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1506 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1507 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1508 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1509 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1510 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1511 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1512 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1513 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1514 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1515 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1516 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1517 #define BGE_BMAN_HWDIAG_1 0x444C 1518 #define BGE_BMAN_HWDIAG_2 0x4450 1519 #define BGE_BMAN_HWDIAG_3 0x4454 1520 1521 /* Buffer manager mode register */ 1522 #define BGE_BMANMODE_RESET 0x00000001 1523 #define BGE_BMANMODE_ENABLE 0x00000002 1524 #define BGE_BMANMODE_ATTN 0x00000004 1525 #define BGE_BMANMODE_TESTMODE 0x00000008 1526 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1527 #define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1528 1529 /* Buffer manager status register */ 1530 #define BGE_BMANSTAT_ERRO 0x00000004 1531 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1532 1533 1534 /* 1535 * Read DMA Control registers 1536 */ 1537 #define BGE_RDMA_MODE 0x4800 1538 #define BGE_RDMA_STATUS 0x4804 1539 #define BGE_RDMA_RSRVCTRL2 0x4890 1540 #define BGE_RDMA_LSO_CRPTEN_CTRL2 0x48a0 1541 #define BGE_RDMA_RSRVCTRL 0x4900 1542 #define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1543 1544 /* Read DMA mode register */ 1545 #define BGE_RDMAMODE_RESET 0x00000001 1546 #define BGE_RDMAMODE_ENABLE 0x00000002 1547 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1548 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1549 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1550 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1551 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1552 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1553 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1554 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1555 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1556 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1557 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1558 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1559 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1560 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1561 #define BGE_RDMAMODE_JMB_2K_MMRR 0x00800000 1562 #define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1563 #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1564 #define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1565 1566 /* Read DMA status register */ 1567 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1568 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1569 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1570 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1571 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1572 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1573 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1574 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1575 1576 /* Read DMA Reserved Control register */ 1577 #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1578 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1579 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1580 #define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1581 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1582 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1583 #define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1584 1585 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1586 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1587 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1588 #define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000 1589 #define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000 1590 1591 /* BD Read DMA Mode register */ 1592 #define BGE_RDMA_BD_MODE 0x4A00 1593 /* BD Read DMA Mode status register */ 1594 #define BGE_RDMA_BD_STATUS 0x4A04 1595 1596 #define BGE_RDMA_BD_MODE_RESET 0x00000001 1597 #define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1598 1599 /* Non-LSO Read DMA Mode register */ 1600 #define BGE_RDMA_NON_LSO_MODE 0x4B00 1601 /* Non-LSO Read DMA Mode status register */ 1602 #define BGE_RDMA_NON_LSO_STATUS 0x4B04 1603 1604 #define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1605 #define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1606 1607 #define BGE_RDMA_NCHAN 4 1608 #define BGE_RDMA_LENGTH 0x4BE0 1609 1610 /* 1611 * Write DMA control registers 1612 */ 1613 #define BGE_WDMA_MODE 0x4C00 1614 #define BGE_WDMA_STATUS 0x4C04 1615 1616 /* Write DMA mode register */ 1617 #define BGE_WDMAMODE_RESET 0x00000001 1618 #define BGE_WDMAMODE_ENABLE 0x00000002 1619 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1620 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1621 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1622 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1623 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1624 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1625 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1626 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1627 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1628 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1629 #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1630 1631 /* Write DMA status register */ 1632 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1633 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1634 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1635 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1636 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1637 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1638 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1639 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1640 1641 1642 /* 1643 * RX CPU registers 1644 */ 1645 #define BGE_RXCPU_MODE 0x5000 1646 #define BGE_RXCPU_STATUS 0x5004 1647 #define BGE_RXCPU_PC 0x501C 1648 1649 /* RX CPU mode register */ 1650 #define BGE_RXCPUMODE_RESET 0x00000001 1651 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1652 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1653 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1654 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1655 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1656 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1657 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1658 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1659 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1660 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1661 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1662 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1663 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1664 1665 /* RX CPU status register */ 1666 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1667 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1668 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1669 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1670 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1671 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1672 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1673 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1674 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1675 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1676 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1677 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1678 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1679 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1680 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1681 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1682 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1683 1684 /* 1685 * V? CPU registers 1686 */ 1687 #define BGE_VCPU_STATUS 0x5100 1688 #define BGE_VCPU_EXT_CTRL 0x6890 1689 1690 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1691 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1692 1693 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1694 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1695 1696 1697 /* 1698 * TX CPU registers 1699 */ 1700 #define BGE_TXCPU_MODE 0x5400 1701 #define BGE_TXCPU_STATUS 0x5404 1702 #define BGE_TXCPU_PC 0x541C 1703 1704 /* TX CPU mode register */ 1705 #define BGE_TXCPUMODE_RESET 0x00000001 1706 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1707 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1708 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1709 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1710 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1711 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1712 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1713 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1714 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1715 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1716 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1717 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1718 1719 /* TX CPU status register */ 1720 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1721 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1722 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1723 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1724 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1725 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1726 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1727 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1728 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1729 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1730 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1731 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1732 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1733 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1734 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1735 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1736 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1737 1738 1739 /* 1740 * Low priority mailbox registers 1741 */ 1742 #define BGE_LPMBX_IRQ0_HI 0x5800 1743 #define BGE_LPMBX_IRQ0_LO 0x5804 1744 #define BGE_LPMBX_IRQ1_HI 0x5808 1745 #define BGE_LPMBX_IRQ1_LO 0x580C 1746 #define BGE_LPMBX_IRQ2_HI 0x5810 1747 #define BGE_LPMBX_IRQ2_LO 0x5814 1748 #define BGE_LPMBX_IRQ3_HI 0x5818 1749 #define BGE_LPMBX_IRQ3_LO 0x581C 1750 #define BGE_LPMBX_GEN0_HI 0x5820 1751 #define BGE_LPMBX_GEN0_LO 0x5824 1752 #define BGE_LPMBX_GEN1_HI 0x5828 1753 #define BGE_LPMBX_GEN1_LO 0x582C 1754 #define BGE_LPMBX_GEN2_HI 0x5830 1755 #define BGE_LPMBX_GEN2_LO 0x5834 1756 #define BGE_LPMBX_GEN3_HI 0x5828 1757 #define BGE_LPMBX_GEN3_LO 0x582C 1758 #define BGE_LPMBX_GEN4_HI 0x5840 1759 #define BGE_LPMBX_GEN4_LO 0x5844 1760 #define BGE_LPMBX_GEN5_HI 0x5848 1761 #define BGE_LPMBX_GEN5_LO 0x584C 1762 #define BGE_LPMBX_GEN6_HI 0x5850 1763 #define BGE_LPMBX_GEN6_LO 0x5854 1764 #define BGE_LPMBX_GEN7_HI 0x5858 1765 #define BGE_LPMBX_GEN7_LO 0x585C 1766 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1767 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1768 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1769 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1770 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1771 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1772 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1773 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1774 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1775 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1776 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1777 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1778 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1779 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1780 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1781 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1782 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1783 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1784 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1785 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1786 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1787 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1788 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1789 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1790 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1791 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1792 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1793 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1794 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1795 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1796 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1797 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1798 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1799 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1800 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1801 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1802 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1803 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1804 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1805 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1806 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1807 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1808 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1809 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1810 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1811 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1812 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1813 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1814 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1815 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1816 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1817 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1818 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1819 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1820 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1821 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1822 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1823 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1824 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1825 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1826 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1827 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1828 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1829 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1830 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1831 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1832 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1833 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1834 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1835 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1836 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1837 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1838 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1839 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1840 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1841 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1842 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1843 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1844 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1845 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1846 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1847 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1848 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1849 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1850 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1851 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1852 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1853 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1854 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1855 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1856 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1857 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1858 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1859 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1860 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1861 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1862 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1863 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1864 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1865 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1866 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1867 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1868 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1869 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1870 1871 /* 1872 * Flow throw Queue reset register 1873 */ 1874 #define BGE_FTQ_RESET 0x5C00 1875 1876 #define BGE_FTQRESET_DMAREAD 0x00000002 1877 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1878 #define BGE_FTQRESET_DMADONE 0x00000010 1879 #define BGE_FTQRESET_SBDC 0x00000020 1880 #define BGE_FTQRESET_SDI 0x00000040 1881 #define BGE_FTQRESET_WDMA 0x00000080 1882 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1883 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1884 #define BGE_FTQRESET_SDC 0x00000400 1885 #define BGE_FTQRESET_HCC 0x00000800 1886 #define BGE_FTQRESET_TXFIFO 0x00001000 1887 #define BGE_FTQRESET_MBC 0x00002000 1888 #define BGE_FTQRESET_RBDC 0x00004000 1889 #define BGE_FTQRESET_RXLP 0x00008000 1890 #define BGE_FTQRESET_RDBDI 0x00010000 1891 #define BGE_FTQRESET_RDC 0x00020000 1892 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1893 1894 /* 1895 * Message Signaled Interrupt registers 1896 */ 1897 #define BGE_MSI_MODE 0x6000 1898 #define BGE_MSI_STATUS 0x6004 1899 #define BGE_MSI_FIFOACCESS 0x6008 1900 1901 /* MSI mode register */ 1902 #define BGE_MSIMODE_RESET 0x00000001 1903 #define BGE_MSIMODE_ENABLE 0x00000002 1904 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1905 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1906 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1907 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1908 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1909 #define BGE_MSIMODE_MSIX_MULTIMODE 0x00000080 1910 /* 1911 * Duplicate MSI_FIFOUFLOW_ATTN, only applies to BCM57785 and BCM5718 1912 * families. See 5718-PG105-R. 1913 */ 1914 #define BGE_MSIMODE_ONESHOT_DISABLE 0x00000020 1915 1916 /* MSI status register */ 1917 #define BGE_MSISTAT_MSI_PCI_REQ 0x00000001 1918 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1919 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1920 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1921 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1922 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1923 1924 1925 /* 1926 * DMA Completion registers 1927 */ 1928 #define BGE_DMAC_MODE 0x6400 1929 1930 /* DMA Completion mode register */ 1931 #define BGE_DMACMODE_RESET 0x00000001 1932 #define BGE_DMACMODE_ENABLE 0x00000002 1933 1934 1935 /* 1936 * General control registers. 1937 */ 1938 #define BGE_MODE_CTL 0x6800 1939 #define BGE_MISC_CFG 0x6804 1940 #define BGE_MISC_LOCAL_CTL 0x6808 1941 #define BGE_RX_CPU_EVENT 0x6810 1942 #define BGE_EE_ADDR 0x6838 1943 #define BGE_EE_DATA 0x683C 1944 #define BGE_EE_CTL 0x6840 1945 #define BGE_MDI_CTL 0x6844 1946 #define BGE_EE_DELAY 0x6848 1947 #define BGE_FASTBOOT_PC 0x6894 1948 1949 #define BGE_RX_CPU_DRV_EVENT 0x00004000 1950 1951 /* 1952 * NVRAM Control registers 1953 */ 1954 #define BGE_NVRAM_CMD 0x7000 1955 #define BGE_NVRAM_STAT 0x7004 1956 #define BGE_NVRAM_WRDATA 0x7008 1957 #define BGE_NVRAM_ADDR 0x700c 1958 #define BGE_NVRAM_RDDATA 0x7010 1959 #define BGE_NVRAM_CFG1 0x7014 1960 #define BGE_NVRAM_CFG2 0x7018 1961 #define BGE_NVRAM_CFG3 0x701c 1962 #define BGE_NVRAM_SWARB 0x7020 1963 #define BGE_NVRAM_ACCESS 0x7024 1964 #define BGE_NVRAM_WRITE1 0x7028 1965 1966 #define BGE_NVRAMCMD_RESET 0x00000001 1967 #define BGE_NVRAMCMD_DONE 0x00000008 1968 #define BGE_NVRAMCMD_START 0x00000010 1969 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1970 #define BGE_NVRAMCMD_ERASE 0x00000040 1971 #define BGE_NVRAMCMD_FIRST 0x00000080 1972 #define BGE_NVRAMCMD_LAST 0x00000100 1973 1974 #define BGE_NVRAM_READCMD \ 1975 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1976 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1977 #define BGE_NVRAM_WRITECMD \ 1978 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1979 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1980 1981 #define BGE_NVRAMSWARB_SET0 0x00000001 1982 #define BGE_NVRAMSWARB_SET1 0x00000002 1983 #define BGE_NVRAMSWARB_SET2 0x00000003 1984 #define BGE_NVRAMSWARB_SET3 0x00000004 1985 #define BGE_NVRAMSWARB_CLR0 0x00000010 1986 #define BGE_NVRAMSWARB_CLR1 0x00000020 1987 #define BGE_NVRAMSWARB_CLR2 0x00000040 1988 #define BGE_NVRAMSWARB_CLR3 0x00000080 1989 #define BGE_NVRAMSWARB_GNT0 0x00000100 1990 #define BGE_NVRAMSWARB_GNT1 0x00000200 1991 #define BGE_NVRAMSWARB_GNT2 0x00000400 1992 #define BGE_NVRAMSWARB_GNT3 0x00000800 1993 #define BGE_NVRAMSWARB_REQ0 0x00001000 1994 #define BGE_NVRAMSWARB_REQ1 0x00002000 1995 #define BGE_NVRAMSWARB_REQ2 0x00004000 1996 #define BGE_NVRAMSWARB_REQ3 0x00008000 1997 1998 #define BGE_NVRAMACC_ENABLE 0x00000001 1999 #define BGE_NVRAMACC_WRENABLE 0x00000002 2000 2001 /* Mode control register */ 2002 #define BGE_MODECTL_PCIE_TL_SEL 0x00000000 2003 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 2004 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 2005 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 2006 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 2007 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 2008 #define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 2009 #define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2010 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2011 #define BGE_MODECTL_NO_RX_CRC 0x00000400 2012 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 2013 #define BGE_MODECTL_NO_TX_INTR 0x00002000 2014 #define BGE_MODECTL_NO_RX_INTR 0x00004000 2015 #define BGE_MODECTL_FORCE_PCI32 0x00008000 2016 #define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2017 #define BGE_MODECTL_STACKUP 0x00010000 2018 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2019 #define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2020 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2021 #define BGE_MODECTL_PCIE_PL_SEL 0x00400000 2022 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2023 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2024 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2025 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2026 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2027 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2028 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2029 #define BGE_MODECTL_PCIE_DL_SEL 0x20000000 2030 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2031 #define BGE_MODECTL_PCIE_HI1K_EN 0x80000000 2032 #define BGE_MODECTL_PCIE_PORTS \ 2033 (BGE_MODECTL_PCIE_HI1K_EN | \ 2034 BGE_MODECTL_PCIE_TL_SEL | \ 2035 BGE_MODECTL_PCIE_PL_SEL | \ 2036 BGE_MODECTL_PCIE_DL_SEL) 2037 2038 /* Misc. config register */ 2039 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2040 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2041 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2042 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2043 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 2044 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2045 #define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 2046 2047 #define BGE_32BITTIME_66MHZ (0x41 << 1) 2048 2049 /* Misc. Local Control */ 2050 #define BGE_MLC_INTR_STATE 0x00000001 2051 #define BGE_MLC_INTR_CLR 0x00000002 2052 #define BGE_MLC_INTR_SET 0x00000004 2053 #define BGE_MLC_INTR_ONATTN 0x00000008 2054 #define BGE_MLC_MISCIO_IN0 0x00000100 2055 #define BGE_MLC_MISCIO_IN1 0x00000200 2056 #define BGE_MLC_MISCIO_IN2 0x00000400 2057 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 2058 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 2059 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 2060 #define BGE_MLC_MISCIO_OUT0 0x00004000 2061 #define BGE_MLC_MISCIO_OUT1 0x00008000 2062 #define BGE_MLC_MISCIO_OUT2 0x00010000 2063 #define BGE_MLC_EXTRAM_ENB 0x00020000 2064 #define BGE_MLC_SRAM_SIZE 0x001C0000 2065 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2066 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2067 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2068 #define BGE_MLC_AUTO_EEPROM 0x01000000 2069 2070 #define BGE_SSRAMSIZE_256KB 0x00000000 2071 #define BGE_SSRAMSIZE_512KB 0x00040000 2072 #define BGE_SSRAMSIZE_1MB 0x00080000 2073 #define BGE_SSRAMSIZE_2MB 0x000C0000 2074 #define BGE_SSRAMSIZE_4MB 0x00100000 2075 #define BGE_SSRAMSIZE_8MB 0x00140000 2076 #define BGE_SSRAMSIZE_16M 0x00180000 2077 2078 /* EEPROM address register */ 2079 #define BGE_EEADDR_ADDRESS 0x0000FFFC 2080 #define BGE_EEADDR_HALFCLK 0x01FF0000 2081 #define BGE_EEADDR_START 0x02000000 2082 #define BGE_EEADDR_DEVID 0x1C000000 2083 #define BGE_EEADDR_RESET 0x20000000 2084 #define BGE_EEADDR_DONE 0x40000000 2085 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2086 2087 #define BGE_EEDEVID(x) ((x & 7) << 26) 2088 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2089 #define BGE_HALFCLK_384SCL 0x60 2090 #define BGE_EE_READCMD \ 2091 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2092 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2093 #define BGE_EE_WRCMD \ 2094 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2095 BGE_EEADDR_START|BGE_EEADDR_DONE) 2096 2097 /* EEPROM Control register */ 2098 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2099 #define BGE_EECTL_CLKOUT 0x00000002 2100 #define BGE_EECTL_CLKIN 0x00000004 2101 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2102 #define BGE_EECTL_DATAOUT 0x00000010 2103 #define BGE_EECTL_DATAIN 0x00000020 2104 2105 /* MDI (MII/GMII) access register */ 2106 #define BGE_MDI_DATA 0x00000001 2107 #define BGE_MDI_DIR 0x00000002 2108 #define BGE_MDI_SEL 0x00000004 2109 #define BGE_MDI_CLK 0x00000008 2110 2111 #define BGE_MEMWIN_START 0x00008000 2112 #define BGE_MEMWIN_END 0x0000FFFF 2113 2114 /* BAR1 (APE) Register Definitions */ 2115 2116 #define BGE_APE_GPIO_MSG 0x0008 2117 #define BGE_APE_EVENT 0x000C 2118 #define BGE_APE_LOCK_REQ 0x002C 2119 #define BGE_APE_LOCK_GRANT 0x004C 2120 2121 #define BGE_APE_GPIO_MSG_SHIFT 4 2122 2123 #define BGE_APE_EVENT_1 0x00000001 2124 2125 #define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2126 2127 #define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2128 2129 /* APE Shared Memory block (writable by APE only) */ 2130 #define BGE_APE_SEG_SIG 0x4000 2131 #define BGE_APE_FW_STATUS 0x400C 2132 #define BGE_APE_FW_FEATURES 0x4010 2133 #define BGE_APE_FW_BEHAVIOR 0x4014 2134 #define BGE_APE_FW_VERSION 0x4018 2135 #define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2136 #define BGE_APE_FW_HEARTBEAT 0x4028 2137 #define BGE_APE_FW_ERROR_FLAGS 0x4074 2138 2139 #define BGE_APE_SEG_SIG_MAGIC 0x41504521 2140 2141 #define BGE_APE_FW_STATUS_READY 0x00000100 2142 2143 #define BGE_APE_FW_FEATURE_DASH 0x00000001 2144 #define BGE_APE_FW_FEATURE_NCSI 0x00000002 2145 2146 #define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2147 #define BGE_APE_FW_VERSION_MAJSFT 24 2148 #define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2149 #define BGE_APE_FW_VERSION_MINSFT 16 2150 #define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2151 #define BGE_APE_FW_VERSION_REVSFT 8 2152 #define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2153 2154 /* Host Shared Memory block (writable by host only) */ 2155 #define BGE_APE_HOST_SEG_SIG 0x4200 2156 #define BGE_APE_HOST_SEG_LEN 0x4204 2157 #define BGE_APE_HOST_INIT_COUNT 0x4208 2158 #define BGE_APE_HOST_DRIVER_ID 0x420C 2159 #define BGE_APE_HOST_BEHAVIOR 0x4210 2160 #define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2161 #define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2162 #define BGE_APE_HOST_DRVR_STATE 0x421C 2163 #define BGE_APE_HOST_WOL_SPEED 0x4224 2164 2165 #define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2166 2167 #define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2168 2169 #define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2170 #define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2171 (BGE_APE_HOST_DRIVER_ID_FBSD | \ 2172 ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) 2173 2174 #define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2175 2176 #define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2177 #define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2178 2179 #define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2180 #define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2181 #define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2182 #define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2183 2184 #define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2185 2186 #define BGE_APE_EVENT_STATUS 0x4300 2187 2188 #define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2189 #define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2190 #define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2191 #define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2192 #define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2193 #define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2194 #define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2195 2196 #define BGE_APE_DEBUG_LOG 0x4E00 2197 #define BGE_APE_DEBUG_LOG_LEN 0x0100 2198 2199 #define BGE_APE_PER_LOCK_REQ 0x8400 2200 #define BGE_APE_PER_LOCK_GRANT 0x8420 2201 2202 #define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2203 #define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2204 #define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2205 #define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2206 2207 #define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2208 #define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2209 #define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2210 #define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2211 2212 /* APE Mutex Resources */ 2213 #define BGE_APE_LOCK_PHY0 0 2214 #define BGE_APE_LOCK_GRC 1 2215 #define BGE_APE_LOCK_PHY1 2 2216 #define BGE_APE_LOCK_PHY2 3 2217 #define BGE_APE_LOCK_MEM 4 2218 #define BGE_APE_LOCK_PHY3 5 2219 #define BGE_APE_LOCK_GPIO 7 2220 2221 /* 2222 * PCI-E Core Private Register Access to TL, DL & PL 2223 */ 2224 #define BGE_PCIE_TLDLPL_PORT 0x7c00 2225 #define BGE_PCIE_PL_LO_PHYCTL5 0x7c14 2226 #define BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 2227 #define BGE_PCIE_DL_LO_FTSMAX 0x7c0c 2228 #define BGE_PCIE_DL_LO_FTSMAX_MASK 0x000000ff 2229 #define BGE_PCIE_DL_LO_FTSMAX_VAL 0x0000002c 2230 2231 /* 2232 * PCI-E transaction configure register. 2233 * Applies to BCM5906 and BCM5755+. See 5722-PG101-R. 2234 * 2235 * Earlier PCI-E chips, e.g. 5750, call it TLP workaround, 2236 * and there are no interesting bits in it. 2237 */ 2238 #define BGE_PCIE_TRANSACT 0x7c04 2239 #define BGE_PCIE_TRANSACT_ONESHOT_MSI 0x20000000 2240 2241 /* PCI-E PHY test control register */ 2242 #define BGE_PCIE_PHY_TSTCTL 0x7e2c 2243 #define BGE_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 2244 #define BGE_PCIE_PHY_TSTCTL_PCIE10 0x00000040 2245 2246 #define PCI_SETBIT(dev, reg, x, s) \ 2247 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s) 2248 #define PCI_CLRBIT(dev, reg, x, s) \ 2249 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s) 2250 2251 /* 2252 * This magic number is written to the firmware mailbox at 0xb50 2253 * before a software reset is issued. After the internal firmware 2254 * has completed its initialization it will write the opposite of 2255 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, allowing 2256 * the driver to synchronize with the firmware. 2257 */ 2258 #define BGE_SRAM_FW_MB_MAGIC 0x4B657654 2259 2260 typedef struct { 2261 uint32_t bge_addr_hi; 2262 uint32_t bge_addr_lo; 2263 } bge_hostaddr; 2264 2265 #define BGE_HOSTADDR(x, y) \ 2266 do { \ 2267 (x).bge_addr_lo = ((uint64_t)(y) & 0xffffffff); \ 2268 (x).bge_addr_hi = ((uint64_t)(y) >> 32); \ 2269 } while(0) 2270 2271 #define BGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 2272 #define BGE_ADDR_HI(y) ((uint64_t)(y) >> 32) 2273 2274 /* Ring control block structure */ 2275 struct bge_rcb { 2276 bge_hostaddr bge_hostaddr; 2277 uint32_t bge_maxlen_flags; 2278 uint32_t bge_nicaddr; 2279 }; 2280 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2281 2282 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2283 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 2284 2285 struct bge_tx_bd { 2286 bge_hostaddr bge_addr; 2287 #if BYTE_ORDER == LITTLE_ENDIAN 2288 uint16_t bge_flags; 2289 uint16_t bge_len; 2290 uint16_t bge_vlan_tag; 2291 uint16_t bge_mss; 2292 #else 2293 uint16_t bge_len; 2294 uint16_t bge_flags; 2295 uint16_t bge_mss; 2296 uint16_t bge_vlan_tag; 2297 #endif 2298 }; 2299 2300 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2301 #define BGE_TXBDFLAG_IP_CSUM 0x0002 2302 #define BGE_TXBDFLAG_END 0x0004 2303 #define BGE_TXBDFLAG_IP_FRAG 0x0008 2304 #define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2305 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2306 #define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2307 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 2308 #define BGE_TXBDFLAG_COAL_NOW 0x0080 2309 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2310 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2311 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2312 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2313 #define BGE_TXBDFLAG_NO_CRC 0x8000 2314 2315 #define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2316 /* Bits [1:0] of the MSS header length. */ 2317 #define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2318 2319 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 2320 BGE_SEND_RING_1_TO_4 + \ 2321 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2322 2323 struct bge_rx_bd { 2324 bge_hostaddr bge_addr; 2325 #if BYTE_ORDER == LITTLE_ENDIAN 2326 uint16_t bge_len; 2327 uint16_t bge_idx; 2328 uint16_t bge_flags; 2329 uint16_t bge_type; 2330 uint16_t bge_tcp_udp_csum; 2331 uint16_t bge_ip_csum; 2332 uint16_t bge_vlan_tag; 2333 uint16_t bge_error_flag; 2334 #else 2335 uint16_t bge_idx; 2336 uint16_t bge_len; 2337 uint16_t bge_type; 2338 uint16_t bge_flags; 2339 uint16_t bge_ip_csum; 2340 uint16_t bge_tcp_udp_csum; 2341 uint16_t bge_error_flag; 2342 uint16_t bge_vlan_tag; 2343 #endif 2344 uint32_t bge_hash; 2345 uint32_t bge_opaque; 2346 }; 2347 2348 #define BGE_RXBDFLAG_END 0x0004 2349 #define BGE_RXBDFLAG_RSS_HASH 0x0008 2350 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 2351 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 2352 #define BGE_RXBDFLAG_ERROR 0x0400 2353 #define BGE_RXBDFLAG_MINI_RING 0x0800 2354 #define BGE_RXBDFLAG_IP_CSUM 0x1000 2355 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2356 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2357 #define BGE_RXBDFLAG_IPV6 0x8000 2358 2359 #define BGE_RXERRFLAG_BAD_CRC 0x0001 2360 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 2361 #define BGE_RXERRFLAG_LINK_LOST 0x0004 2362 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2363 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 2364 #define BGE_RXERRFLAG_RUNT 0x0020 2365 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2366 #define BGE_RXERRFLAG_GIANT 0x0080 2367 #define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2368 2369 struct bge_sts_idx { 2370 #if BYTE_ORDER == LITTLE_ENDIAN 2371 uint16_t bge_rx_prod_idx; 2372 uint16_t bge_tx_cons_idx; 2373 #else 2374 uint16_t bge_tx_cons_idx; 2375 uint16_t bge_rx_prod_idx; 2376 #endif 2377 }; 2378 2379 struct bge_status_block { 2380 uint32_t bge_status; 2381 uint32_t bge_status_tag; 2382 #if BYTE_ORDER == LITTLE_ENDIAN 2383 uint16_t bge_rx_jumbo_cons_idx; 2384 uint16_t bge_rx_std_cons_idx; 2385 uint16_t bge_rx_mini_cons_idx; 2386 uint16_t bge_rsvd1; 2387 #else 2388 uint16_t bge_rx_std_cons_idx; 2389 uint16_t bge_rx_jumbo_cons_idx; 2390 uint16_t bge_rsvd1; 2391 uint16_t bge_rx_mini_cons_idx; 2392 #endif 2393 struct bge_sts_idx bge_idx[16]; 2394 }; 2395 #define BGE_STATUS_BLK_SZ sizeof(struct bge_status_block) 2396 2397 #define BGE_STATFLAG_UPDATED 0x00000001 2398 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2399 #define BGE_STATFLAG_ERROR 0x00000004 2400 2401 /* 2402 * Offset of MAC address inside EEPROM. 2403 */ 2404 #define BGE_EE_MAC_OFFSET 0x7C 2405 #define BGE_EE_MAC_OFFSET_5906 0x10 2406 #define BGE_EE_HWCFG_OFFSET 0xC8 2407 #define BGE_EE_MAC_OFFSET_5717 0xCC 2408 #define BGE_EE_MAC_OFFSET_5717_OFF 0x18C 2409 2410 #define BGE_HWCFG_VOLTAGE 0x00000003 2411 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2412 #define BGE_HWCFG_MEDIA 0x00000030 2413 #define BGE_HWCFG_ASF 0x00000080 2414 2415 #define BGE_VOLTAGE_1POINT3 0x00000000 2416 #define BGE_VOLTAGE_1POINT8 0x00000001 2417 2418 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2419 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2420 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2421 2422 #define BGE_MEDIA_UNSPEC 0x00000000 2423 #define BGE_MEDIA_COPPER 0x00000010 2424 #define BGE_MEDIA_FIBER 0x00000020 2425 2426 #define BGE_PCI_READ_CMD 0x06000000 2427 #define BGE_PCI_WRITE_CMD 0x70000000 2428 2429 #define BGE_TICKS_PER_SEC 1000000 2430 2431 /* 2432 * Ring size constants. 2433 */ 2434 #define BGE_EVENT_RING_CNT 256 2435 #define BGE_CMD_RING_CNT 64 2436 #define BGE_STD_RX_RING_CNT 512 2437 #define BGE_JUMBO_RX_RING_CNT 256 2438 #define BGE_MINI_RX_RING_CNT 1024 2439 #define BGE_RETURN_RING_CNT 1024 2440 2441 /* 5705 has smaller return ring size */ 2442 2443 #define BGE_RETURN_RING_CNT_5705 512 2444 2445 /* 2446 * Possible TX ring sizes. 2447 */ 2448 #define BGE_TX_RING_CNT_128 128 2449 #define BGE_TX_RING_BASE_128 0x3800 2450 2451 #define BGE_TX_RING_CNT_256 256 2452 #define BGE_TX_RING_BASE_256 0x3000 2453 2454 #define BGE_TX_RING_CNT_512 512 2455 #define BGE_TX_RING_BASE_512 0x2000 2456 2457 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2458 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2459 2460 /* 2461 * Tigon III statistics counters. 2462 */ 2463 /* Statistics maintained MAC Receive block. */ 2464 struct bge_rx_mac_stats { 2465 bge_hostaddr ifHCInOctets; 2466 bge_hostaddr Reserved1; 2467 bge_hostaddr etherStatsFragments; 2468 bge_hostaddr ifHCInUcastPkts; 2469 bge_hostaddr ifHCInMulticastPkts; 2470 bge_hostaddr ifHCInBroadcastPkts; 2471 bge_hostaddr dot3StatsFCSErrors; 2472 bge_hostaddr dot3StatsAlignmentErrors; 2473 bge_hostaddr xonPauseFramesReceived; 2474 bge_hostaddr xoffPauseFramesReceived; 2475 bge_hostaddr macControlFramesReceived; 2476 bge_hostaddr xoffStateEntered; 2477 bge_hostaddr dot3StatsFramesTooLong; 2478 bge_hostaddr etherStatsJabbers; 2479 bge_hostaddr etherStatsUndersizePkts; 2480 bge_hostaddr inRangeLengthError; 2481 bge_hostaddr outRangeLengthError; 2482 bge_hostaddr etherStatsPkts64Octets; 2483 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2484 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2485 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2486 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2487 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2488 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2489 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2490 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2491 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2492 }; 2493 2494 2495 /* Statistics maintained MAC Transmit block. */ 2496 struct bge_tx_mac_stats { 2497 bge_hostaddr ifHCOutOctets; 2498 bge_hostaddr Reserved2; 2499 bge_hostaddr etherStatsCollisions; 2500 bge_hostaddr outXonSent; 2501 bge_hostaddr outXoffSent; 2502 bge_hostaddr flowControlDone; 2503 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2504 bge_hostaddr dot3StatsSingleCollisionFrames; 2505 bge_hostaddr dot3StatsMultipleCollisionFrames; 2506 bge_hostaddr dot3StatsDeferredTransmissions; 2507 bge_hostaddr Reserved3; 2508 bge_hostaddr dot3StatsExcessiveCollisions; 2509 bge_hostaddr dot3StatsLateCollisions; 2510 bge_hostaddr dot3Collided2Times; 2511 bge_hostaddr dot3Collided3Times; 2512 bge_hostaddr dot3Collided4Times; 2513 bge_hostaddr dot3Collided5Times; 2514 bge_hostaddr dot3Collided6Times; 2515 bge_hostaddr dot3Collided7Times; 2516 bge_hostaddr dot3Collided8Times; 2517 bge_hostaddr dot3Collided9Times; 2518 bge_hostaddr dot3Collided10Times; 2519 bge_hostaddr dot3Collided11Times; 2520 bge_hostaddr dot3Collided12Times; 2521 bge_hostaddr dot3Collided13Times; 2522 bge_hostaddr dot3Collided14Times; 2523 bge_hostaddr dot3Collided15Times; 2524 bge_hostaddr ifHCOutUcastPkts; 2525 bge_hostaddr ifHCOutMulticastPkts; 2526 bge_hostaddr ifHCOutBroadcastPkts; 2527 bge_hostaddr dot3StatsCarrierSenseErrors; 2528 bge_hostaddr ifOutDiscards; 2529 bge_hostaddr ifOutErrors; 2530 }; 2531 2532 /* Stats counters access through registers */ 2533 struct bge_mac_stats_regs { 2534 uint32_t ifHCOutOctets; 2535 uint32_t Reserved0; 2536 uint32_t etherStatsCollisions; 2537 uint32_t outXonSent; 2538 uint32_t outXoffSent; 2539 uint32_t Reserved1; 2540 uint32_t dot3StatsInternalMacTransmitErrors; 2541 uint32_t dot3StatsSingleCollisionFrames; 2542 uint32_t dot3StatsMultipleCollisionFrames; 2543 uint32_t dot3StatsDeferredTransmissions; 2544 uint32_t Reserved2; 2545 uint32_t dot3StatsExcessiveCollisions; 2546 uint32_t dot3StatsLateCollisions; 2547 uint32_t Reserved3[14]; 2548 uint32_t ifHCOutUcastPkts; 2549 uint32_t ifHCOutMulticastPkts; 2550 uint32_t ifHCOutBroadcastPkts; 2551 uint32_t Reserved4[2]; 2552 uint32_t ifHCInOctets; 2553 uint32_t Reserved5; 2554 uint32_t etherStatsFragments; 2555 uint32_t ifHCInUcastPkts; 2556 uint32_t ifHCInMulticastPkts; 2557 uint32_t ifHCInBroadcastPkts; 2558 uint32_t dot3StatsFCSErrors; 2559 uint32_t dot3StatsAlignmentErrors; 2560 uint32_t xonPauseFramesReceived; 2561 uint32_t xoffPauseFramesReceived; 2562 uint32_t macControlFramesReceived; 2563 uint32_t xoffStateEntered; 2564 uint32_t dot3StatsFramesTooLong; 2565 uint32_t etherStatsJabbers; 2566 uint32_t etherStatsUndersizePkts; 2567 }; 2568 2569 struct bge_stats { 2570 uint8_t Reserved0[256]; 2571 2572 /* Statistics maintained by Receive MAC. */ 2573 struct bge_rx_mac_stats rxstats; 2574 2575 bge_hostaddr Unused1[37]; 2576 2577 /* Statistics maintained by Transmit MAC. */ 2578 struct bge_tx_mac_stats txstats; 2579 2580 bge_hostaddr Unused2[31]; 2581 2582 /* Statistics maintained by Receive List Placement. */ 2583 bge_hostaddr COSIfHCInPkts[16]; 2584 bge_hostaddr COSFramesDroppedDueToFilters; 2585 bge_hostaddr nicDmaWriteQueueFull; 2586 bge_hostaddr nicDmaWriteHighPriQueueFull; 2587 bge_hostaddr nicNoMoreRxBDs; 2588 bge_hostaddr ifInDiscards; 2589 bge_hostaddr ifInErrors; 2590 bge_hostaddr nicRecvThresholdHit; 2591 2592 bge_hostaddr Unused3[9]; 2593 2594 /* Statistics maintained by Send Data Initiator. */ 2595 bge_hostaddr COSIfHCOutPkts[16]; 2596 bge_hostaddr nicDmaReadQueueFull; 2597 bge_hostaddr nicDmaReadHighPriQueueFull; 2598 bge_hostaddr nicSendDataCompQueueFull; 2599 2600 /* Statistics maintained by Host Coalescing. */ 2601 bge_hostaddr nicRingSetSendProdIndex; 2602 bge_hostaddr nicRingStatusUpdate; 2603 bge_hostaddr nicInterrupts; 2604 bge_hostaddr nicAvoidedInterrupts; 2605 bge_hostaddr nicSendThresholdHit; 2606 2607 uint8_t Reserved4[320]; 2608 }; 2609 #define BGE_STATS_SZ sizeof(struct bge_stats) 2610 2611 #if (BUS_SPACE_MAXADDR != BUS_SPACE_MAXADDR_32BIT) 2612 #define BGE_DMA_MAXADDR_40BIT 0xFFFFFFFFFF 2613 #define BGE_DMA_BOUNDARY_4G 0x100000000ULL 2614 #else 2615 #define BGE_DMA_MAXADDR_40BIT BUS_SPACE_MAXADDR 2616 #define BGE_DMA_BOUNDARY_4G 0 2617 #endif 2618 2619 #define BGE_STD_RX_RING_SZ \ 2620 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2621 #define BGE_JUMBO_RX_RING_SZ \ 2622 (sizeof(struct bge_rx_bd) * BGE_JUMBO_RX_RING_CNT) 2623 #define BGE_TX_RING_SZ \ 2624 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2625 #define BGE_RX_RTN_RING_SZ(cnt) \ 2626 (sizeof(struct bge_rx_bd) * (cnt)) 2627 2628 #endif /* !_IF_BGEREG_H_ */ 2629