1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.13 2003/12/01 21:06:59 ambrisko Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.5 2004/09/14 22:31:01 joerg Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79 #define BGE_UNMAPPED 0x00001000 80 #define BGE_UNMAPPED_END 0x00001FFF 81 #define BGE_DMA_DESCRIPTORS 0x00002000 82 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83 #define BGE_SEND_RING_1_TO_4 0x00004000 84 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86 /* Mappings for internal memory configuration */ 87 #define BGE_STD_RX_RINGS 0x00006000 88 #define BGE_STD_RX_RINGS_END 0x00006FFF 89 #define BGE_JUMBO_RX_RINGS 0x00007000 90 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91 #define BGE_BUFFPOOL_1 0x00008000 92 #define BGE_BUFFPOOL_1_END 0x0000FFFF 93 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94 #define BGE_BUFFPOOL_2_END 0x00017FFF 95 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96 #define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98 /* Mappings for external SSRAM configurations */ 99 #define BGE_SEND_RING_5_TO_6 0x00006000 100 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101 #define BGE_SEND_RING_7_TO_8 0x00007000 102 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103 #define BGE_SEND_RING_9_TO_16 0x00008000 104 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105 #define BGE_EXT_STD_RX_RINGS 0x0000C000 106 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109 #define BGE_MINI_RX_RINGS 0x0000E000 110 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 111 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112 #define BGE_AVAIL_REGION1_END 0x00017FFF 113 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114 #define BGE_AVAIL_REGION2_END 0x0001FFFF 115 #define BGE_EXT_SSRAM 0x00020000 116 #define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119 /* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129 /* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132 #define BGE_PCI_VID 0x00 133 #define BGE_PCI_DID 0x02 134 #define BGE_PCI_CMD 0x04 135 #define BGE_PCI_STS 0x06 136 #define BGE_PCI_REV 0x08 137 #define BGE_PCI_CLASS 0x09 138 #define BGE_PCI_CACHESZ 0x0C 139 #define BGE_PCI_LATTIMER 0x0D 140 #define BGE_PCI_HDRTYPE 0x0E 141 #define BGE_PCI_BIST 0x0F 142 #define BGE_PCI_BAR0 0x10 143 #define BGE_PCI_BAR1 0x14 144 #define BGE_PCI_SUBSYS 0x2C 145 #define BGE_PCI_SUBVID 0x2E 146 #define BGE_PCI_ROMBASE 0x30 147 #define BGE_PCI_CAPPTR 0x34 148 #define BGE_PCI_INTLINE 0x3C 149 #define BGE_PCI_INTPIN 0x3D 150 #define BGE_PCI_MINGNT 0x3E 151 #define BGE_PCI_MAXLAT 0x3F 152 #define BGE_PCI_PCIXCAP 0x40 153 #define BGE_PCI_NEXTPTR_PM 0x41 154 #define BGE_PCI_PCIX_CMD 0x42 155 #define BGE_PCI_PCIX_STS 0x44 156 #define BGE_PCI_PWRMGMT_CAPID 0x48 157 #define BGE_PCI_NEXTPTR_VPD 0x49 158 #define BGE_PCI_PWRMGMT_CAPS 0x4A 159 #define BGE_PCI_PWRMGMT_CMD 0x4C 160 #define BGE_PCI_PWRMGMT_STS 0x4D 161 #define BGE_PCI_PWRMGMT_DATA 0x4F 162 #define BGE_PCI_VPD_CAPID 0x50 163 #define BGE_PCI_NEXTPTR_MSI 0x51 164 #define BGE_PCI_VPD_ADDR 0x52 165 #define BGE_PCI_VPD_DATA 0x54 166 #define BGE_PCI_MSI_CAPID 0x58 167 #define BGE_PCI_NEXTPTR_NONE 0x59 168 #define BGE_PCI_MSI_CTL 0x5A 169 #define BGE_PCI_MSI_ADDR_HI 0x5C 170 #define BGE_PCI_MSI_ADDR_LO 0x60 171 #define BGE_PCI_MSI_DATA 0x64 172 173 /* 174 * PCI registers specific to the BCM570x family. 175 */ 176 #define BGE_PCI_MISC_CTL 0x68 177 #define BGE_PCI_DMA_RW_CTL 0x6C 178 #define BGE_PCI_PCISTATE 0x70 179 #define BGE_PCI_CLKCTL 0x74 180 #define BGE_PCI_REG_BASEADDR 0x78 181 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 182 #define BGE_PCI_REG_DATA 0x80 183 #define BGE_PCI_MEMWIN_DATA 0x84 184 #define BGE_PCI_MODECTL 0x88 185 #define BGE_PCI_MISC_CFG 0x8C 186 #define BGE_PCI_MISC_LOCALCTL 0x90 187 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 188 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 189 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 190 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 191 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 192 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 193 #define BGE_PCI_ISR_MBX_HI 0xB0 194 #define BGE_PCI_ISR_MBX_LO 0xB4 195 196 /* PCI Misc. Host control register */ 197 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 198 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 199 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 200 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 201 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 202 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 203 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 204 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 205 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 206 207 #define BGE_BIGENDIAN_INIT \ 208 (BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 209 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 210 BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR) 211 212 #define BGE_LITTLEENDIAN_INIT \ 213 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 214 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 215 216 #define BGE_CHIPID_TIGON_I 0x40000000 217 #define BGE_CHIPID_TIGON_II 0x60000000 218 #define BGE_CHIPID_BCM5700_B0 0x71000000 219 #define BGE_CHIPID_BCM5700_B1 0x71020000 220 #define BGE_CHIPID_BCM5700_B2 0x71030000 221 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 222 #define BGE_CHIPID_BCM5700_C0 0x72000000 223 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 224 #define BGE_CHIPID_BCM5701_B0 0x01000000 225 #define BGE_CHIPID_BCM5701_B2 0x01020000 226 #define BGE_CHIPID_BCM5701_B5 0x01050000 227 #define BGE_CHIPID_BCM5703_A0 0x10000000 228 #define BGE_CHIPID_BCM5703_A1 0x10010000 229 #define BGE_CHIPID_BCM5703_A2 0x10020000 230 #define BGE_CHIPID_BCM5704_A0 0x20000000 231 #define BGE_CHIPID_BCM5704_A1 0x20010000 232 #define BGE_CHIPID_BCM5704_A2 0x20020000 233 #define BGE_CHIPID_BCM5705_A0 0x30000000 234 #define BGE_CHIPID_BCM5705_A1 0x30010000 235 #define BGE_CHIPID_BCM5705_A2 0x30020000 236 #define BGE_CHIPID_BCM5705_A3 0x30030000 237 238 /* shorthand one */ 239 #define BGE_ASICREV(x) ((x) >> 28) 240 #define BGE_ASICREV_BCM5700 0x07 241 #define BGE_ASICREV_BCM5701 0x00 242 #define BGE_ASICREV_BCM5703 0x01 243 #define BGE_ASICREV_BCM5704 0x02 244 #define BGE_ASICREV_BCM5705 0x03 245 246 /* chip revisions */ 247 #define BGE_CHIPREV(x) ((x) >> 24) 248 #define BGE_CHIPREV_5700_AX 0x70 249 #define BGE_CHIPREV_5700_BX 0x71 250 #define BGE_CHIPREV_5700_CX 0x72 251 #define BGE_CHIPREV_5701_AX 0x00 252 253 /* PCI DMA Read/Write Control register */ 254 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 255 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 256 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 257 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 258 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 259 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 260 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 261 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 262 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 263 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 264 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 265 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 266 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 267 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 268 269 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 270 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 271 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 272 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 273 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 274 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 275 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 276 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 277 278 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 279 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 280 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 281 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 282 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 283 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 284 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 285 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 286 287 /* 288 * PCI state register -- note, this register is read only 289 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 290 * register is set. 291 */ 292 #define BGE_PCISTATE_FORCE_RESET 0x00000001 293 #define BGE_PCISTATE_INTR_STATE 0x00000002 294 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 295 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 296 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 297 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 298 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 299 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 300 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 301 302 /* 303 * PCI Clock Control register -- note, this register is read only 304 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 305 * register is set. 306 */ 307 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 308 #define BGE_PCICLOCKCTL_M66EN 0x00000080 309 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 310 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 311 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 312 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 313 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 314 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 315 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 316 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 317 318 319 #ifndef PCIM_CMD_MWIEN 320 #define PCIM_CMD_MWIEN 0x0010 321 #endif 322 323 /* 324 * High priority mailbox registers 325 * Each mailbox is 64-bits wide, though we only use the 326 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 327 * first. The NIC will load the mailbox after the lower 32 bit word 328 * has been updated. 329 */ 330 #define BGE_MBX_IRQ0_HI 0x0200 331 #define BGE_MBX_IRQ0_LO 0x0204 332 #define BGE_MBX_IRQ1_HI 0x0208 333 #define BGE_MBX_IRQ1_LO 0x020C 334 #define BGE_MBX_IRQ2_HI 0x0210 335 #define BGE_MBX_IRQ2_LO 0x0214 336 #define BGE_MBX_IRQ3_HI 0x0218 337 #define BGE_MBX_IRQ3_LO 0x021C 338 #define BGE_MBX_GEN0_HI 0x0220 339 #define BGE_MBX_GEN0_LO 0x0224 340 #define BGE_MBX_GEN1_HI 0x0228 341 #define BGE_MBX_GEN1_LO 0x022C 342 #define BGE_MBX_GEN2_HI 0x0230 343 #define BGE_MBX_GEN2_LO 0x0234 344 #define BGE_MBX_GEN3_HI 0x0228 345 #define BGE_MBX_GEN3_LO 0x022C 346 #define BGE_MBX_GEN4_HI 0x0240 347 #define BGE_MBX_GEN4_LO 0x0244 348 #define BGE_MBX_GEN5_HI 0x0248 349 #define BGE_MBX_GEN5_LO 0x024C 350 #define BGE_MBX_GEN6_HI 0x0250 351 #define BGE_MBX_GEN6_LO 0x0254 352 #define BGE_MBX_GEN7_HI 0x0258 353 #define BGE_MBX_GEN7_LO 0x025C 354 #define BGE_MBX_RELOAD_STATS_HI 0x0260 355 #define BGE_MBX_RELOAD_STATS_LO 0x0264 356 #define BGE_MBX_RX_STD_PROD_HI 0x0268 357 #define BGE_MBX_RX_STD_PROD_LO 0x026C 358 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 359 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 360 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 361 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 362 #define BGE_MBX_RX_CONS0_HI 0x0280 363 #define BGE_MBX_RX_CONS0_LO 0x0284 364 #define BGE_MBX_RX_CONS1_HI 0x0288 365 #define BGE_MBX_RX_CONS1_LO 0x028C 366 #define BGE_MBX_RX_CONS2_HI 0x0290 367 #define BGE_MBX_RX_CONS2_LO 0x0294 368 #define BGE_MBX_RX_CONS3_HI 0x0298 369 #define BGE_MBX_RX_CONS3_LO 0x029C 370 #define BGE_MBX_RX_CONS4_HI 0x02A0 371 #define BGE_MBX_RX_CONS4_LO 0x02A4 372 #define BGE_MBX_RX_CONS5_HI 0x02A8 373 #define BGE_MBX_RX_CONS5_LO 0x02AC 374 #define BGE_MBX_RX_CONS6_HI 0x02B0 375 #define BGE_MBX_RX_CONS6_LO 0x02B4 376 #define BGE_MBX_RX_CONS7_HI 0x02B8 377 #define BGE_MBX_RX_CONS7_LO 0x02BC 378 #define BGE_MBX_RX_CONS8_HI 0x02C0 379 #define BGE_MBX_RX_CONS8_LO 0x02C4 380 #define BGE_MBX_RX_CONS9_HI 0x02C8 381 #define BGE_MBX_RX_CONS9_LO 0x02CC 382 #define BGE_MBX_RX_CONS10_HI 0x02D0 383 #define BGE_MBX_RX_CONS10_LO 0x02D4 384 #define BGE_MBX_RX_CONS11_HI 0x02D8 385 #define BGE_MBX_RX_CONS11_LO 0x02DC 386 #define BGE_MBX_RX_CONS12_HI 0x02E0 387 #define BGE_MBX_RX_CONS12_LO 0x02E4 388 #define BGE_MBX_RX_CONS13_HI 0x02E8 389 #define BGE_MBX_RX_CONS13_LO 0x02EC 390 #define BGE_MBX_RX_CONS14_HI 0x02F0 391 #define BGE_MBX_RX_CONS14_LO 0x02F4 392 #define BGE_MBX_RX_CONS15_HI 0x02F8 393 #define BGE_MBX_RX_CONS15_LO 0x02FC 394 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 395 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 396 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 397 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 398 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 399 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 400 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 401 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 402 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 403 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 404 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 405 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 406 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 407 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 408 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 409 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 410 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 411 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 412 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 413 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 414 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 415 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 416 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 417 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 418 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 419 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 420 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 421 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 422 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 423 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 424 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 425 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 426 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 427 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 428 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 429 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 430 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 431 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 432 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 433 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 434 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 435 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 436 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 437 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 438 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 439 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 440 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 441 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 442 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 443 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 444 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 445 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 446 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 447 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 448 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 449 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 450 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 451 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 452 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 453 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 454 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 455 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 456 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 457 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 458 459 #define BGE_TX_RINGS_MAX 4 460 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 461 #define BGE_RX_RINGS_MAX 16 462 463 /* Ethernet MAC control registers */ 464 #define BGE_MAC_MODE 0x0400 465 #define BGE_MAC_STS 0x0404 466 #define BGE_MAC_EVT_ENB 0x0408 467 #define BGE_MAC_LED_CTL 0x040C 468 #define BGE_MAC_ADDR1_LO 0x0410 469 #define BGE_MAC_ADDR1_HI 0x0414 470 #define BGE_MAC_ADDR2_LO 0x0418 471 #define BGE_MAC_ADDR2_HI 0x041C 472 #define BGE_MAC_ADDR3_LO 0x0420 473 #define BGE_MAC_ADDR3_HI 0x0424 474 #define BGE_MAC_ADDR4_LO 0x0428 475 #define BGE_MAC_ADDR4_HI 0x042C 476 #define BGE_WOL_PATPTR 0x0430 477 #define BGE_WOL_PATCFG 0x0434 478 #define BGE_TX_RANDOM_BACKOFF 0x0438 479 #define BGE_RX_MTU 0x043C 480 #define BGE_GBIT_PCS_TEST 0x0440 481 #define BGE_TX_TBI_AUTONEG 0x0444 482 #define BGE_RX_TBI_AUTONEG 0x0448 483 #define BGE_MI_COMM 0x044C 484 #define BGE_MI_STS 0x0450 485 #define BGE_MI_MODE 0x0454 486 #define BGE_AUTOPOLL_STS 0x0458 487 #define BGE_TX_MODE 0x045C 488 #define BGE_TX_STS 0x0460 489 #define BGE_TX_LENGTHS 0x0464 490 #define BGE_RX_MODE 0x0468 491 #define BGE_RX_STS 0x046C 492 #define BGE_MAR0 0x0470 493 #define BGE_MAR1 0x0474 494 #define BGE_MAR2 0x0478 495 #define BGE_MAR3 0x047C 496 #define BGE_RX_BD_RULES_CTL0 0x0480 497 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 498 #define BGE_RX_BD_RULES_CTL1 0x0488 499 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 500 #define BGE_RX_BD_RULES_CTL2 0x0490 501 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 502 #define BGE_RX_BD_RULES_CTL3 0x0498 503 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 504 #define BGE_RX_BD_RULES_CTL4 0x04A0 505 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 506 #define BGE_RX_BD_RULES_CTL5 0x04A8 507 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 508 #define BGE_RX_BD_RULES_CTL6 0x04B0 509 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 510 #define BGE_RX_BD_RULES_CTL7 0x04B8 511 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 512 #define BGE_RX_BD_RULES_CTL8 0x04C0 513 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 514 #define BGE_RX_BD_RULES_CTL9 0x04C8 515 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 516 #define BGE_RX_BD_RULES_CTL10 0x04D0 517 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 518 #define BGE_RX_BD_RULES_CTL11 0x04D8 519 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 520 #define BGE_RX_BD_RULES_CTL12 0x04E0 521 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 522 #define BGE_RX_BD_RULES_CTL13 0x04E8 523 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 524 #define BGE_RX_BD_RULES_CTL14 0x04F0 525 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 526 #define BGE_RX_BD_RULES_CTL15 0x04F8 527 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 528 #define BGE_RX_RULES_CFG 0x0500 529 #define BGE_RX_STATS 0x0800 530 #define BGE_TX_STATS 0x0880 531 532 /* Ethernet MAC Mode register */ 533 #define BGE_MACMODE_RESET 0x00000001 534 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 535 #define BGE_MACMODE_PORTMODE 0x0000000C 536 #define BGE_MACMODE_LOOPBACK 0x00000010 537 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 538 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 539 #define BGE_MACMODE_MAX_DEFER 0x00000200 540 #define BGE_MACMODE_LINK_POLARITY 0x00000400 541 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 542 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 543 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 544 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 545 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 546 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 547 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 548 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 549 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 550 #define BGE_MACMODE_MIP_ENB 0x00100000 551 #define BGE_MACMODE_TXDMA_ENB 0x00200000 552 #define BGE_MACMODE_RXDMA_ENB 0x00400000 553 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 554 555 #define BGE_PORTMODE_NONE 0x00000000 556 #define BGE_PORTMODE_MII 0x00000004 557 #define BGE_PORTMODE_GMII 0x00000008 558 #define BGE_PORTMODE_TBI 0x0000000C 559 560 /* MAC Status register */ 561 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 562 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 563 #define BGE_MACSTAT_RX_CFG 0x00000004 564 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 565 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 566 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 567 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 568 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 569 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 570 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 571 #define BGE_MACSTAT_ODI_ERROR 0x02000000 572 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 573 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 574 575 /* MAC Event Enable Register */ 576 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 577 #define BGE_EVTENB_LINK_CHANGED 0x00001000 578 #define BGE_EVTENB_MI_COMPLETE 0x00400000 579 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 580 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 581 #define BGE_EVTENB_ODI_ERROR 0x02000000 582 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 583 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 584 585 /* LED Control Register */ 586 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 587 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 588 #define BGE_LEDCTL_100MBPS_LED 0x00000004 589 #define BGE_LEDCTL_10MBPS_LED 0x00000008 590 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 591 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 592 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 593 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 594 #define BGE_LEDCTL_100MBPS_STS 0x00000100 595 #define BGE_LEDCTL_10MBPS_STS 0x00000200 596 #define BGE_LEDCTL_TRADLED_STS 0x00000400 597 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 598 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 599 600 /* TX backoff seed register */ 601 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 602 603 /* Autopoll status register */ 604 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 605 606 /* Transmit MAC mode register */ 607 #define BGE_TXMODE_RESET 0x00000001 608 #define BGE_TXMODE_ENABLE 0x00000002 609 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 610 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 611 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 612 613 /* Transmit MAC status register */ 614 #define BGE_TXSTAT_RX_XOFFED 0x00000001 615 #define BGE_TXSTAT_SENT_XOFF 0x00000002 616 #define BGE_TXSTAT_SENT_XON 0x00000004 617 #define BGE_TXSTAT_LINK_UP 0x00000008 618 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 619 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 620 621 /* Transmit MAC lengths register */ 622 #define BGE_TXLEN_SLOTTIME 0x000000FF 623 #define BGE_TXLEN_IPG 0x00000F00 624 #define BGE_TXLEN_CRS 0x00003000 625 626 /* Receive MAC mode register */ 627 #define BGE_RXMODE_RESET 0x00000001 628 #define BGE_RXMODE_ENABLE 0x00000002 629 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 630 #define BGE_RXMODE_RX_GIANTS 0x00000020 631 #define BGE_RXMODE_RX_RUNTS 0x00000040 632 #define BGE_RXMODE_8022_LENCHECK 0x00000080 633 #define BGE_RXMODE_RX_PROMISC 0x00000100 634 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 635 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 636 637 /* Receive MAC status register */ 638 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 639 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 640 #define BGE_RXSTAT_RCVD_XON 0x00000004 641 642 /* Receive Rules Control register */ 643 #define BGE_RXRULECTL_OFFSET 0x000000FF 644 #define BGE_RXRULECTL_CLASS 0x00001F00 645 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 646 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 647 #define BGE_RXRULECTL_MAP 0x01000000 648 #define BGE_RXRULECTL_DISCARD 0x02000000 649 #define BGE_RXRULECTL_MASK 0x04000000 650 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 651 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 652 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 653 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 654 655 /* Receive Rules Mask register */ 656 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 657 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 658 659 /* MI communication register */ 660 #define BGE_MICOMM_DATA 0x0000FFFF 661 #define BGE_MICOMM_REG 0x001F0000 662 #define BGE_MICOMM_PHY 0x03E00000 663 #define BGE_MICOMM_CMD 0x0C000000 664 #define BGE_MICOMM_READFAIL 0x10000000 665 #define BGE_MICOMM_BUSY 0x20000000 666 667 #define BGE_MIREG(x) ((x & 0x1F) << 16) 668 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 669 #define BGE_MICMD_WRITE 0x04000000 670 #define BGE_MICMD_READ 0x08000000 671 672 /* MI status register */ 673 #define BGE_MISTS_LINK 0x00000001 674 #define BGE_MISTS_10MBPS 0x00000002 675 676 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 677 #define BGE_MIMODE_AUTOPOLL 0x00000010 678 #define BGE_MIMODE_CLKCNT 0x001F0000 679 680 681 /* 682 * Send data initiator control registers. 683 */ 684 #define BGE_SDI_MODE 0x0C00 685 #define BGE_SDI_STATUS 0x0C04 686 #define BGE_SDI_STATS_CTL 0x0C08 687 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 688 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 689 #define BGE_LOCSTATS_COS0 0x0C80 690 #define BGE_LOCSTATS_COS1 0x0C84 691 #define BGE_LOCSTATS_COS2 0x0C88 692 #define BGE_LOCSTATS_COS3 0x0C8C 693 #define BGE_LOCSTATS_COS4 0x0C90 694 #define BGE_LOCSTATS_COS5 0x0C84 695 #define BGE_LOCSTATS_COS6 0x0C98 696 #define BGE_LOCSTATS_COS7 0x0C9C 697 #define BGE_LOCSTATS_COS8 0x0CA0 698 #define BGE_LOCSTATS_COS9 0x0CA4 699 #define BGE_LOCSTATS_COS10 0x0CA8 700 #define BGE_LOCSTATS_COS11 0x0CAC 701 #define BGE_LOCSTATS_COS12 0x0CB0 702 #define BGE_LOCSTATS_COS13 0x0CB4 703 #define BGE_LOCSTATS_COS14 0x0CB8 704 #define BGE_LOCSTATS_COS15 0x0CBC 705 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 706 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 707 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 708 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 709 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 710 #define BGE_LOCSTATS_IRQS 0x0CD4 711 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 712 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 713 714 /* Send Data Initiator mode register */ 715 #define BGE_SDIMODE_RESET 0x00000001 716 #define BGE_SDIMODE_ENABLE 0x00000002 717 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 718 719 /* Send Data Initiator stats register */ 720 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 721 722 /* Send Data Initiator stats control register */ 723 #define BGE_SDISTATSCTL_ENABLE 0x00000001 724 #define BGE_SDISTATSCTL_FASTER 0x00000002 725 #define BGE_SDISTATSCTL_CLEAR 0x00000004 726 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 727 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 728 729 /* 730 * Send Data Completion Control registers 731 */ 732 #define BGE_SDC_MODE 0x1000 733 #define BGE_SDC_STATUS 0x1004 734 735 /* Send Data completion mode register */ 736 #define BGE_SDCMODE_RESET 0x00000001 737 #define BGE_SDCMODE_ENABLE 0x00000002 738 #define BGE_SDCMODE_ATTN 0x00000004 739 740 /* Send Data completion status register */ 741 #define BGE_SDCSTAT_ATTN 0x00000004 742 743 /* 744 * Send BD Ring Selector Control registers 745 */ 746 #define BGE_SRS_MODE 0x1400 747 #define BGE_SRS_STATUS 0x1404 748 #define BGE_SRS_HWDIAG 0x1408 749 #define BGE_SRS_LOC_NIC_CONS0 0x1440 750 #define BGE_SRS_LOC_NIC_CONS1 0x1444 751 #define BGE_SRS_LOC_NIC_CONS2 0x1448 752 #define BGE_SRS_LOC_NIC_CONS3 0x144C 753 #define BGE_SRS_LOC_NIC_CONS4 0x1450 754 #define BGE_SRS_LOC_NIC_CONS5 0x1454 755 #define BGE_SRS_LOC_NIC_CONS6 0x1458 756 #define BGE_SRS_LOC_NIC_CONS7 0x145C 757 #define BGE_SRS_LOC_NIC_CONS8 0x1460 758 #define BGE_SRS_LOC_NIC_CONS9 0x1464 759 #define BGE_SRS_LOC_NIC_CONS10 0x1468 760 #define BGE_SRS_LOC_NIC_CONS11 0x146C 761 #define BGE_SRS_LOC_NIC_CONS12 0x1470 762 #define BGE_SRS_LOC_NIC_CONS13 0x1474 763 #define BGE_SRS_LOC_NIC_CONS14 0x1478 764 #define BGE_SRS_LOC_NIC_CONS15 0x147C 765 766 /* Send BD Ring Selector Mode register */ 767 #define BGE_SRSMODE_RESET 0x00000001 768 #define BGE_SRSMODE_ENABLE 0x00000002 769 #define BGE_SRSMODE_ATTN 0x00000004 770 771 /* Send BD Ring Selector Status register */ 772 #define BGE_SRSSTAT_ERROR 0x00000004 773 774 /* Send BD Ring Selector HW Diagnostics register */ 775 #define BGE_SRSHWDIAG_STATE 0x0000000F 776 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 777 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 778 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 779 780 /* 781 * Send BD Initiator Selector Control registers 782 */ 783 #define BGE_SBDI_MODE 0x1800 784 #define BGE_SBDI_STATUS 0x1804 785 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 786 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 787 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 788 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 789 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 790 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 791 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 792 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 793 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 794 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 795 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 796 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 797 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 798 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 799 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 800 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 801 802 /* Send BD Initiator Mode register */ 803 #define BGE_SBDIMODE_RESET 0x00000001 804 #define BGE_SBDIMODE_ENABLE 0x00000002 805 #define BGE_SBDIMODE_ATTN 0x00000004 806 807 /* Send BD Initiator Status register */ 808 #define BGE_SBDISTAT_ERROR 0x00000004 809 810 /* 811 * Send BD Completion Control registers 812 */ 813 #define BGE_SBDC_MODE 0x1C00 814 #define BGE_SBDC_STATUS 0x1C04 815 816 /* Send BD Completion Control Mode register */ 817 #define BGE_SBDCMODE_RESET 0x00000001 818 #define BGE_SBDCMODE_ENABLE 0x00000002 819 #define BGE_SBDCMODE_ATTN 0x00000004 820 821 /* Send BD Completion Control Status register */ 822 #define BGE_SBDCSTAT_ATTN 0x00000004 823 824 /* 825 * Receive List Placement Control registers 826 */ 827 #define BGE_RXLP_MODE 0x2000 828 #define BGE_RXLP_STATUS 0x2004 829 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 830 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 831 #define BGE_RXLP_CFG 0x2010 832 #define BGE_RXLP_STATS_CTL 0x2014 833 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 834 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 835 #define BGE_RXLP_HEAD0 0x2100 836 #define BGE_RXLP_TAIL0 0x2104 837 #define BGE_RXLP_COUNT0 0x2108 838 #define BGE_RXLP_HEAD1 0x2110 839 #define BGE_RXLP_TAIL1 0x2114 840 #define BGE_RXLP_COUNT1 0x2118 841 #define BGE_RXLP_HEAD2 0x2120 842 #define BGE_RXLP_TAIL2 0x2124 843 #define BGE_RXLP_COUNT2 0x2128 844 #define BGE_RXLP_HEAD3 0x2130 845 #define BGE_RXLP_TAIL3 0x2134 846 #define BGE_RXLP_COUNT3 0x2138 847 #define BGE_RXLP_HEAD4 0x2140 848 #define BGE_RXLP_TAIL4 0x2144 849 #define BGE_RXLP_COUNT4 0x2148 850 #define BGE_RXLP_HEAD5 0x2150 851 #define BGE_RXLP_TAIL5 0x2154 852 #define BGE_RXLP_COUNT5 0x2158 853 #define BGE_RXLP_HEAD6 0x2160 854 #define BGE_RXLP_TAIL6 0x2164 855 #define BGE_RXLP_COUNT6 0x2168 856 #define BGE_RXLP_HEAD7 0x2170 857 #define BGE_RXLP_TAIL7 0x2174 858 #define BGE_RXLP_COUNT7 0x2178 859 #define BGE_RXLP_HEAD8 0x2180 860 #define BGE_RXLP_TAIL8 0x2184 861 #define BGE_RXLP_COUNT8 0x2188 862 #define BGE_RXLP_HEAD9 0x2190 863 #define BGE_RXLP_TAIL9 0x2194 864 #define BGE_RXLP_COUNT9 0x2198 865 #define BGE_RXLP_HEAD10 0x21A0 866 #define BGE_RXLP_TAIL10 0x21A4 867 #define BGE_RXLP_COUNT10 0x21A8 868 #define BGE_RXLP_HEAD11 0x21B0 869 #define BGE_RXLP_TAIL11 0x21B4 870 #define BGE_RXLP_COUNT11 0x21B8 871 #define BGE_RXLP_HEAD12 0x21C0 872 #define BGE_RXLP_TAIL12 0x21C4 873 #define BGE_RXLP_COUNT12 0x21C8 874 #define BGE_RXLP_HEAD13 0x21D0 875 #define BGE_RXLP_TAIL13 0x21D4 876 #define BGE_RXLP_COUNT13 0x21D8 877 #define BGE_RXLP_HEAD14 0x21E0 878 #define BGE_RXLP_TAIL14 0x21E4 879 #define BGE_RXLP_COUNT14 0x21E8 880 #define BGE_RXLP_HEAD15 0x21F0 881 #define BGE_RXLP_TAIL15 0x21F4 882 #define BGE_RXLP_COUNT15 0x21F8 883 #define BGE_RXLP_LOCSTAT_COS0 0x2200 884 #define BGE_RXLP_LOCSTAT_COS1 0x2204 885 #define BGE_RXLP_LOCSTAT_COS2 0x2208 886 #define BGE_RXLP_LOCSTAT_COS3 0x220C 887 #define BGE_RXLP_LOCSTAT_COS4 0x2210 888 #define BGE_RXLP_LOCSTAT_COS5 0x2214 889 #define BGE_RXLP_LOCSTAT_COS6 0x2218 890 #define BGE_RXLP_LOCSTAT_COS7 0x221C 891 #define BGE_RXLP_LOCSTAT_COS8 0x2220 892 #define BGE_RXLP_LOCSTAT_COS9 0x2224 893 #define BGE_RXLP_LOCSTAT_COS10 0x2228 894 #define BGE_RXLP_LOCSTAT_COS11 0x222C 895 #define BGE_RXLP_LOCSTAT_COS12 0x2230 896 #define BGE_RXLP_LOCSTAT_COS13 0x2234 897 #define BGE_RXLP_LOCSTAT_COS14 0x2238 898 #define BGE_RXLP_LOCSTAT_COS15 0x223C 899 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 900 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 901 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 902 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 903 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 904 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 905 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 906 907 908 /* Receive List Placement mode register */ 909 #define BGE_RXLPMODE_RESET 0x00000001 910 #define BGE_RXLPMODE_ENABLE 0x00000002 911 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 912 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 913 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 914 915 /* Receive List Placement Status register */ 916 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 917 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 918 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 919 920 /* 921 * Receive Data and Receive BD Initiator Control Registers 922 */ 923 #define BGE_RDBDI_MODE 0x2400 924 #define BGE_RDBDI_STATUS 0x2404 925 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 926 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 927 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 928 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 929 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 930 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 931 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 932 #define BGE_RX_STD_RCB_NICADDR 0x245C 933 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 934 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 935 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 936 #define BGE_RX_MINI_RCB_NICADDR 0x246C 937 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 938 #define BGE_RDBDI_STD_RX_CONS 0x2474 939 #define BGE_RDBDI_MINI_RX_CONS 0x2478 940 #define BGE_RDBDI_RETURN_PROD0 0x2480 941 #define BGE_RDBDI_RETURN_PROD1 0x2484 942 #define BGE_RDBDI_RETURN_PROD2 0x2488 943 #define BGE_RDBDI_RETURN_PROD3 0x248C 944 #define BGE_RDBDI_RETURN_PROD4 0x2490 945 #define BGE_RDBDI_RETURN_PROD5 0x2494 946 #define BGE_RDBDI_RETURN_PROD6 0x2498 947 #define BGE_RDBDI_RETURN_PROD7 0x249C 948 #define BGE_RDBDI_RETURN_PROD8 0x24A0 949 #define BGE_RDBDI_RETURN_PROD9 0x24A4 950 #define BGE_RDBDI_RETURN_PROD10 0x24A8 951 #define BGE_RDBDI_RETURN_PROD11 0x24AC 952 #define BGE_RDBDI_RETURN_PROD12 0x24B0 953 #define BGE_RDBDI_RETURN_PROD13 0x24B4 954 #define BGE_RDBDI_RETURN_PROD14 0x24B8 955 #define BGE_RDBDI_RETURN_PROD15 0x24BC 956 #define BGE_RDBDI_HWDIAG 0x24C0 957 958 959 /* Receive Data and Receive BD Initiator Mode register */ 960 #define BGE_RDBDIMODE_RESET 0x00000001 961 #define BGE_RDBDIMODE_ENABLE 0x00000002 962 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 963 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 964 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 965 966 /* Receive Data and Receive BD Initiator Status register */ 967 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 968 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 969 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 970 971 972 /* 973 * Receive Data Completion Control registers 974 */ 975 #define BGE_RDC_MODE 0x2800 976 977 /* Receive Data Completion Mode register */ 978 #define BGE_RDCMODE_RESET 0x00000001 979 #define BGE_RDCMODE_ENABLE 0x00000002 980 #define BGE_RDCMODE_ATTN 0x00000004 981 982 /* 983 * Receive BD Initiator Control registers 984 */ 985 #define BGE_RBDI_MODE 0x2C00 986 #define BGE_RBDI_STATUS 0x2C04 987 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 988 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 989 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 990 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 991 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 992 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 993 994 /* Receive BD Initiator Mode register */ 995 #define BGE_RBDIMODE_RESET 0x00000001 996 #define BGE_RBDIMODE_ENABLE 0x00000002 997 #define BGE_RBDIMODE_ATTN 0x00000004 998 999 /* Receive BD Initiator Status register */ 1000 #define BGE_RBDISTAT_ATTN 0x00000004 1001 1002 /* 1003 * Receive BD Completion Control registers 1004 */ 1005 #define BGE_RBDC_MODE 0x3000 1006 #define BGE_RBDC_STATUS 0x3004 1007 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1008 #define BGE_RBDC_STD_BD_PROD 0x300C 1009 #define BGE_RBDC_MINI_BD_PROD 0x3010 1010 1011 /* Receive BD completion mode register */ 1012 #define BGE_RBDCMODE_RESET 0x00000001 1013 #define BGE_RBDCMODE_ENABLE 0x00000002 1014 #define BGE_RBDCMODE_ATTN 0x00000004 1015 1016 /* Receive BD completion status register */ 1017 #define BGE_RBDCSTAT_ERROR 0x00000004 1018 1019 /* 1020 * Receive List Selector Control registers 1021 */ 1022 #define BGE_RXLS_MODE 0x3400 1023 #define BGE_RXLS_STATUS 0x3404 1024 1025 /* Receive List Selector Mode register */ 1026 #define BGE_RXLSMODE_RESET 0x00000001 1027 #define BGE_RXLSMODE_ENABLE 0x00000002 1028 #define BGE_RXLSMODE_ATTN 0x00000004 1029 1030 /* Receive List Selector Status register */ 1031 #define BGE_RXLSSTAT_ERROR 0x00000004 1032 1033 /* 1034 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1035 */ 1036 #define BGE_MBCF_MODE 0x3800 1037 #define BGE_MBCF_STATUS 0x3804 1038 1039 /* Mbuf Cluster Free mode register */ 1040 #define BGE_MBCFMODE_RESET 0x00000001 1041 #define BGE_MBCFMODE_ENABLE 0x00000002 1042 #define BGE_MBCFMODE_ATTN 0x00000004 1043 1044 /* Mbuf Cluster Free status register */ 1045 #define BGE_MBCFSTAT_ERROR 0x00000004 1046 1047 /* 1048 * Host Coalescing Control registers 1049 */ 1050 #define BGE_HCC_MODE 0x3C00 1051 #define BGE_HCC_STATUS 0x3C04 1052 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1053 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1054 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1055 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1056 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1057 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1058 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1059 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1060 #define BGE_HCC_STATS_TICKS 0x3C28 1061 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1062 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1063 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1064 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1065 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1066 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1067 #define BGE_FLOW_ATTN 0x3C48 1068 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1069 #define BGE_HCC_STD_BD_CONS 0x3C54 1070 #define BGE_HCC_MINI_BD_CONS 0x3C58 1071 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1072 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1073 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1074 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1075 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1076 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1077 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1078 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1079 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1080 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1081 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1082 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1083 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1084 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1085 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1086 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1087 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1088 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1089 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1090 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1091 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1092 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1093 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1094 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1095 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1096 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1097 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1098 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1099 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1100 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1101 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1102 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1103 1104 1105 /* Host coalescing mode register */ 1106 #define BGE_HCCMODE_RESET 0x00000001 1107 #define BGE_HCCMODE_ENABLE 0x00000002 1108 #define BGE_HCCMODE_ATTN 0x00000004 1109 #define BGE_HCCMODE_COAL_NOW 0x00000008 1110 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1111 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1112 1113 #define BGE_STATBLKSZ_FULL 0x00000000 1114 #define BGE_STATBLKSZ_64BYTE 0x00000080 1115 #define BGE_STATBLKSZ_32BYTE 0x00000100 1116 1117 /* Host coalescing status register */ 1118 #define BGE_HCCSTAT_ERROR 0x00000004 1119 1120 /* Flow attention register */ 1121 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1122 #define BGE_FLOWATTN_MEMARB 0x00000080 1123 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1124 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1125 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1126 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1127 #define BGE_FLOWATTN_RDBDI 0x00080000 1128 #define BGE_FLOWATTN_RXLS 0x00100000 1129 #define BGE_FLOWATTN_RXLP 0x00200000 1130 #define BGE_FLOWATTN_RBDC 0x00400000 1131 #define BGE_FLOWATTN_RBDI 0x00800000 1132 #define BGE_FLOWATTN_SDC 0x08000000 1133 #define BGE_FLOWATTN_SDI 0x10000000 1134 #define BGE_FLOWATTN_SRS 0x20000000 1135 #define BGE_FLOWATTN_SBDC 0x40000000 1136 #define BGE_FLOWATTN_SBDI 0x80000000 1137 1138 /* 1139 * Memory arbiter registers 1140 */ 1141 #define BGE_MARB_MODE 0x4000 1142 #define BGE_MARB_STATUS 0x4004 1143 #define BGE_MARB_TRAPADDR_HI 0x4008 1144 #define BGE_MARB_TRAPADDR_LO 0x400C 1145 1146 /* Memory arbiter mode register */ 1147 #define BGE_MARBMODE_RESET 0x00000001 1148 #define BGE_MARBMODE_ENABLE 0x00000002 1149 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1150 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1151 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1152 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1153 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1154 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1155 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1156 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1157 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1158 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1159 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1160 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1161 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1162 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1163 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1164 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1165 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1166 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1167 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1168 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1169 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1170 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1171 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1172 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1173 1174 /* Memory arbiter status register */ 1175 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1176 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1177 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1178 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1179 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1180 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1181 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1182 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1183 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1184 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1185 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1186 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1187 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1188 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1189 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1190 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1191 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1192 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1193 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1194 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1195 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1196 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1197 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1198 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1199 1200 /* 1201 * Buffer manager control registers 1202 */ 1203 #define BGE_BMAN_MODE 0x4400 1204 #define BGE_BMAN_STATUS 0x4404 1205 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1206 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1207 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1208 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1209 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1210 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1211 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1212 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1213 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1214 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1215 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1216 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1217 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1218 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1219 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1220 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1221 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1222 #define BGE_BMAN_HWDIAG_1 0x444C 1223 #define BGE_BMAN_HWDIAG_2 0x4450 1224 #define BGE_BMAN_HWDIAG_3 0x4454 1225 1226 /* Buffer manager mode register */ 1227 #define BGE_BMANMODE_RESET 0x00000001 1228 #define BGE_BMANMODE_ENABLE 0x00000002 1229 #define BGE_BMANMODE_ATTN 0x00000004 1230 #define BGE_BMANMODE_TESTMODE 0x00000008 1231 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1232 1233 /* Buffer manager status register */ 1234 #define BGE_BMANSTAT_ERRO 0x00000004 1235 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1236 1237 1238 /* 1239 * Read DMA Control registers 1240 */ 1241 #define BGE_RDMA_MODE 0x4800 1242 #define BGE_RDMA_STATUS 0x4804 1243 1244 /* Read DMA mode register */ 1245 #define BGE_RDMAMODE_RESET 0x00000001 1246 #define BGE_RDMAMODE_ENABLE 0x00000002 1247 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1248 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1249 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1250 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1251 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1252 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1253 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1254 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1255 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1256 1257 /* Read DMA status register */ 1258 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1259 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1260 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1261 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1262 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1263 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1264 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1265 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1266 1267 /* 1268 * Write DMA control registers 1269 */ 1270 #define BGE_WDMA_MODE 0x4C00 1271 #define BGE_WDMA_STATUS 0x4C04 1272 1273 /* Write DMA mode register */ 1274 #define BGE_WDMAMODE_RESET 0x00000001 1275 #define BGE_WDMAMODE_ENABLE 0x00000002 1276 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1277 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1278 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1279 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1280 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1281 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1282 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1283 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1284 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1285 1286 /* Write DMA status register */ 1287 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1288 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1289 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1290 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1291 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1292 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1293 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1294 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1295 1296 1297 /* 1298 * RX CPU registers 1299 */ 1300 #define BGE_RXCPU_MODE 0x5000 1301 #define BGE_RXCPU_STATUS 0x5004 1302 #define BGE_RXCPU_PC 0x501C 1303 1304 /* RX CPU mode register */ 1305 #define BGE_RXCPUMODE_RESET 0x00000001 1306 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1307 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1308 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1309 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1310 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1311 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1312 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1313 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1314 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1315 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1316 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1317 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1318 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1319 1320 /* RX CPU status register */ 1321 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1322 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1323 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1324 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1325 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1326 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1327 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1328 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1329 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1330 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1331 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1332 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1333 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1334 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1335 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1336 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1337 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1338 1339 1340 /* 1341 * TX CPU registers 1342 */ 1343 #define BGE_TXCPU_MODE 0x5400 1344 #define BGE_TXCPU_STATUS 0x5404 1345 #define BGE_TXCPU_PC 0x541C 1346 1347 /* TX CPU mode register */ 1348 #define BGE_TXCPUMODE_RESET 0x00000001 1349 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1350 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1351 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1352 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1353 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1354 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1355 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1356 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1357 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1358 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1359 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1360 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1361 1362 /* TX CPU status register */ 1363 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1364 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1365 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1366 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1367 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1368 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1369 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1370 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1371 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1372 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1373 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1374 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1375 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1376 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1377 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1378 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1379 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1380 1381 1382 /* 1383 * Low priority mailbox registers 1384 */ 1385 #define BGE_LPMBX_IRQ0_HI 0x5800 1386 #define BGE_LPMBX_IRQ0_LO 0x5804 1387 #define BGE_LPMBX_IRQ1_HI 0x5808 1388 #define BGE_LPMBX_IRQ1_LO 0x580C 1389 #define BGE_LPMBX_IRQ2_HI 0x5810 1390 #define BGE_LPMBX_IRQ2_LO 0x5814 1391 #define BGE_LPMBX_IRQ3_HI 0x5818 1392 #define BGE_LPMBX_IRQ3_LO 0x581C 1393 #define BGE_LPMBX_GEN0_HI 0x5820 1394 #define BGE_LPMBX_GEN0_LO 0x5824 1395 #define BGE_LPMBX_GEN1_HI 0x5828 1396 #define BGE_LPMBX_GEN1_LO 0x582C 1397 #define BGE_LPMBX_GEN2_HI 0x5830 1398 #define BGE_LPMBX_GEN2_LO 0x5834 1399 #define BGE_LPMBX_GEN3_HI 0x5828 1400 #define BGE_LPMBX_GEN3_LO 0x582C 1401 #define BGE_LPMBX_GEN4_HI 0x5840 1402 #define BGE_LPMBX_GEN4_LO 0x5844 1403 #define BGE_LPMBX_GEN5_HI 0x5848 1404 #define BGE_LPMBX_GEN5_LO 0x584C 1405 #define BGE_LPMBX_GEN6_HI 0x5850 1406 #define BGE_LPMBX_GEN6_LO 0x5854 1407 #define BGE_LPMBX_GEN7_HI 0x5858 1408 #define BGE_LPMBX_GEN7_LO 0x585C 1409 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1410 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1411 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1412 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1413 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1414 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1415 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1416 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1417 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1418 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1419 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1420 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1421 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1422 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1423 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1424 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1425 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1426 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1427 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1428 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1429 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1430 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1431 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1432 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1433 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1434 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1435 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1436 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1437 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1438 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1439 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1440 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1441 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1442 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1443 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1444 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1445 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1446 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1447 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1448 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1449 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1450 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1451 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1452 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1453 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1454 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1455 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1456 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1457 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1458 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1459 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1460 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1461 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1462 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1463 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1464 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1465 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1466 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1467 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1468 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1469 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1470 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1471 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1472 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1473 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1474 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1475 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1476 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1477 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1478 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1479 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1480 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1481 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1482 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1483 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1484 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1485 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1486 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1487 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1488 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1489 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1490 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1491 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1492 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1493 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1494 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1495 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1496 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1497 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1498 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1499 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1500 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1501 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1502 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1503 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1504 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1505 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1506 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1507 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1508 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1509 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1510 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1511 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1512 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1513 1514 /* 1515 * Flow throw Queue reset register 1516 */ 1517 #define BGE_FTQ_RESET 0x5C00 1518 1519 #define BGE_FTQRESET_DMAREAD 0x00000002 1520 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1521 #define BGE_FTQRESET_DMADONE 0x00000010 1522 #define BGE_FTQRESET_SBDC 0x00000020 1523 #define BGE_FTQRESET_SDI 0x00000040 1524 #define BGE_FTQRESET_WDMA 0x00000080 1525 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1526 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1527 #define BGE_FTQRESET_SDC 0x00000400 1528 #define BGE_FTQRESET_HCC 0x00000800 1529 #define BGE_FTQRESET_TXFIFO 0x00001000 1530 #define BGE_FTQRESET_MBC 0x00002000 1531 #define BGE_FTQRESET_RBDC 0x00004000 1532 #define BGE_FTQRESET_RXLP 0x00008000 1533 #define BGE_FTQRESET_RDBDI 0x00010000 1534 #define BGE_FTQRESET_RDC 0x00020000 1535 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1536 1537 /* 1538 * Message Signaled Interrupt registers 1539 */ 1540 #define BGE_MSI_MODE 0x6000 1541 #define BGE_MSI_STATUS 0x6004 1542 #define BGE_MSI_FIFOACCESS 0x6008 1543 1544 /* MSI mode register */ 1545 #define BGE_MSIMODE_RESET 0x00000001 1546 #define BGE_MSIMODE_ENABLE 0x00000002 1547 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1548 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1549 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1550 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1551 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1552 1553 /* MSI status register */ 1554 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1555 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1556 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1557 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1558 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1559 1560 1561 /* 1562 * DMA Completion registers 1563 */ 1564 #define BGE_DMAC_MODE 0x6400 1565 1566 /* DMA Completion mode register */ 1567 #define BGE_DMACMODE_RESET 0x00000001 1568 #define BGE_DMACMODE_ENABLE 0x00000002 1569 1570 1571 /* 1572 * General control registers. 1573 */ 1574 #define BGE_MODE_CTL 0x6800 1575 #define BGE_MISC_CFG 0x6804 1576 #define BGE_MISC_LOCAL_CTL 0x6808 1577 #define BGE_EE_ADDR 0x6838 1578 #define BGE_EE_DATA 0x683C 1579 #define BGE_EE_CTL 0x6840 1580 #define BGE_MDI_CTL 0x6844 1581 #define BGE_EE_DELAY 0x6848 1582 1583 /* Mode control register */ 1584 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1585 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1586 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1587 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1588 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1589 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1590 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1591 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1592 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1593 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1594 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1595 #define BGE_MODECTL_STACKUP 0x00010000 1596 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1597 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1598 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1599 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1600 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1601 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1602 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1603 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1604 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1605 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1606 1607 /* Misc. config register */ 1608 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1609 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1610 1611 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1612 1613 /* Misc. Local Control */ 1614 #define BGE_MLC_INTR_STATE 0x00000001 1615 #define BGE_MLC_INTR_CLR 0x00000002 1616 #define BGE_MLC_INTR_SET 0x00000004 1617 #define BGE_MLC_INTR_ONATTN 0x00000008 1618 #define BGE_MLC_MISCIO_IN0 0x00000100 1619 #define BGE_MLC_MISCIO_IN1 0x00000200 1620 #define BGE_MLC_MISCIO_IN2 0x00000400 1621 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1622 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1623 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1624 #define BGE_MLC_MISCIO_OUT0 0x00004000 1625 #define BGE_MLC_MISCIO_OUT1 0x00008000 1626 #define BGE_MLC_MISCIO_OUT2 0x00010000 1627 #define BGE_MLC_EXTRAM_ENB 0x00020000 1628 #define BGE_MLC_SRAM_SIZE 0x001C0000 1629 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1630 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1631 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1632 #define BGE_MLC_AUTO_EEPROM 0x01000000 1633 1634 #define BGE_SSRAMSIZE_256KB 0x00000000 1635 #define BGE_SSRAMSIZE_512KB 0x00040000 1636 #define BGE_SSRAMSIZE_1MB 0x00080000 1637 #define BGE_SSRAMSIZE_2MB 0x000C0000 1638 #define BGE_SSRAMSIZE_4MB 0x00100000 1639 #define BGE_SSRAMSIZE_8MB 0x00140000 1640 #define BGE_SSRAMSIZE_16M 0x00180000 1641 1642 /* EEPROM address register */ 1643 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1644 #define BGE_EEADDR_HALFCLK 0x01FF0000 1645 #define BGE_EEADDR_START 0x02000000 1646 #define BGE_EEADDR_DEVID 0x1C000000 1647 #define BGE_EEADDR_RESET 0x20000000 1648 #define BGE_EEADDR_DONE 0x40000000 1649 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1650 1651 #define BGE_EEDEVID(x) ((x & 7) << 26) 1652 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1653 #define BGE_HALFCLK_384SCL 0x60 1654 #define BGE_EE_READCMD \ 1655 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1656 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1657 #define BGE_EE_WRCMD \ 1658 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1659 BGE_EEADDR_START|BGE_EEADDR_DONE) 1660 1661 /* EEPROM Control register */ 1662 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1663 #define BGE_EECTL_CLKOUT 0x00000002 1664 #define BGE_EECTL_CLKIN 0x00000004 1665 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1666 #define BGE_EECTL_DATAOUT 0x00000010 1667 #define BGE_EECTL_DATAIN 0x00000020 1668 1669 /* MDI (MII/GMII) access register */ 1670 #define BGE_MDI_DATA 0x00000001 1671 #define BGE_MDI_DIR 0x00000002 1672 #define BGE_MDI_SEL 0x00000004 1673 #define BGE_MDI_CLK 0x00000008 1674 1675 #define BGE_MEMWIN_START 0x00008000 1676 #define BGE_MEMWIN_END 0x0000FFFF 1677 1678 1679 #define BGE_MEMWIN_READ(sc, x, val) \ 1680 do { \ 1681 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1682 (0xFFFF0000 & x), 4); \ 1683 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1684 } while(0) 1685 1686 #define BGE_MEMWIN_WRITE(sc, x, val) \ 1687 do { \ 1688 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1689 (0xFFFF0000 & x), 4); \ 1690 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1691 } while(0) 1692 1693 /* 1694 * This magic number is used to prevent PXE restart when we 1695 * issue a software reset. We write this magic number to the 1696 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1697 * code from running. 1698 */ 1699 #define BGE_MAGIC_NUMBER 0x4B657654 1700 1701 typedef struct { 1702 u_int32_t bge_addr_hi; 1703 u_int32_t bge_addr_lo; 1704 } bge_hostaddr; 1705 #define BGE_HOSTADDR(x, y) \ 1706 do { \ 1707 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1708 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1709 } while(0) 1710 1711 /* Ring control block structure */ 1712 struct bge_rcb { 1713 bge_hostaddr bge_hostaddr; 1714 u_int32_t bge_maxlen_flags; 1715 u_int32_t bge_nicaddr; 1716 }; 1717 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1718 1719 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1720 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1721 1722 struct bge_tx_bd { 1723 bge_hostaddr bge_addr; 1724 u_int16_t bge_flags; 1725 u_int16_t bge_len; 1726 u_int16_t bge_vlan_tag; 1727 u_int16_t bge_rsvd; 1728 }; 1729 1730 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1731 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1732 #define BGE_TXBDFLAG_END 0x0004 1733 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1734 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1735 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1736 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1737 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1738 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1739 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1740 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1741 #define BGE_TXBDFLAG_NO_CRC 0x8000 1742 1743 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1744 BGE_SEND_RING_1_TO_4 + \ 1745 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1746 1747 struct bge_rx_bd { 1748 bge_hostaddr bge_addr; 1749 u_int16_t bge_len; 1750 u_int16_t bge_idx; 1751 u_int16_t bge_flags; 1752 u_int16_t bge_type; 1753 u_int16_t bge_tcp_udp_csum; 1754 u_int16_t bge_ip_csum; 1755 u_int16_t bge_vlan_tag; 1756 u_int16_t bge_error_flag; 1757 u_int32_t bge_rsvd; 1758 u_int32_t bge_opaque; 1759 }; 1760 1761 #define BGE_RXBDFLAG_END 0x0004 1762 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1763 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1764 #define BGE_RXBDFLAG_ERROR 0x0400 1765 #define BGE_RXBDFLAG_MINI_RING 0x0800 1766 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1767 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1768 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1769 1770 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1771 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1772 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1773 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1774 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1775 #define BGE_RXERRFLAG_RUNT 0x0020 1776 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1777 #define BGE_RXERRFLAG_GIANT 0x0080 1778 1779 struct bge_sts_idx { 1780 u_int16_t bge_rx_prod_idx; 1781 u_int16_t bge_tx_cons_idx; 1782 }; 1783 1784 struct bge_status_block { 1785 u_int32_t bge_status; 1786 u_int32_t bge_rsvd0; 1787 u_int16_t bge_rx_jumbo_cons_idx; 1788 u_int16_t bge_rx_std_cons_idx; 1789 u_int16_t bge_rx_mini_cons_idx; 1790 u_int16_t bge_rsvd1; 1791 struct bge_sts_idx bge_idx[16]; 1792 }; 1793 1794 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1795 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1796 1797 #define BGE_STATFLAG_UPDATED 0x00000001 1798 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1799 #define BGE_STATFLAG_ERROR 0x00000004 1800 1801 1802 /* 1803 * strange Broadcom PCI IDs 1804 */ 1805 #define BCOM_DEVICEID_BCM5702X 0x16C6 1806 #define BCOM_DEVICEID_BCM5703X 0x16C7 1807 #define BCOM_DEVICEID_BCM5788 0x169C 1808 1809 /* 1810 * Offset of MAC address inside EEPROM. 1811 */ 1812 #define BGE_EE_MAC_OFFSET 0x7C 1813 #define BGE_EE_HWCFG_OFFSET 0xC8 1814 1815 #define BGE_HWCFG_VOLTAGE 0x00000003 1816 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 1817 #define BGE_HWCFG_MEDIA 0x00000030 1818 1819 #define BGE_VOLTAGE_1POINT3 0x00000000 1820 #define BGE_VOLTAGE_1POINT8 0x00000001 1821 1822 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 1823 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1824 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 1825 1826 #define BGE_MEDIA_UNSPEC 0x00000000 1827 #define BGE_MEDIA_COPPER 0x00000010 1828 #define BGE_MEDIA_FIBER 0x00000020 1829 1830 #define BGE_PCI_READ_CMD 0x06000000 1831 #define BGE_PCI_WRITE_CMD 0x70000000 1832 1833 #define BGE_TICKS_PER_SEC 1000000 1834 1835 /* 1836 * Ring size constants. 1837 */ 1838 #define BGE_EVENT_RING_CNT 256 1839 #define BGE_CMD_RING_CNT 64 1840 #define BGE_STD_RX_RING_CNT 512 1841 #define BGE_JUMBO_RX_RING_CNT 256 1842 #define BGE_MINI_RX_RING_CNT 1024 1843 #define BGE_RETURN_RING_CNT 1024 1844 1845 /* 5705 has smaller return ring size */ 1846 1847 #define BGE_RETURN_RING_CNT_5705 512 1848 1849 /* 1850 * Possible TX ring sizes. 1851 */ 1852 #define BGE_TX_RING_CNT_128 128 1853 #define BGE_TX_RING_BASE_128 0x3800 1854 1855 #define BGE_TX_RING_CNT_256 256 1856 #define BGE_TX_RING_BASE_256 0x3000 1857 1858 #define BGE_TX_RING_CNT_512 512 1859 #define BGE_TX_RING_BASE_512 0x2000 1860 1861 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1862 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1863 1864 /* 1865 * Tigon III statistics counters. 1866 */ 1867 /* Statistics maintained MAC Receive block. */ 1868 struct bge_rx_mac_stats { 1869 bge_hostaddr ifHCInOctets; 1870 bge_hostaddr Reserved1; 1871 bge_hostaddr etherStatsFragments; 1872 bge_hostaddr ifHCInUcastPkts; 1873 bge_hostaddr ifHCInMulticastPkts; 1874 bge_hostaddr ifHCInBroadcastPkts; 1875 bge_hostaddr dot3StatsFCSErrors; 1876 bge_hostaddr dot3StatsAlignmentErrors; 1877 bge_hostaddr xonPauseFramesReceived; 1878 bge_hostaddr xoffPauseFramesReceived; 1879 bge_hostaddr macControlFramesReceived; 1880 bge_hostaddr xoffStateEntered; 1881 bge_hostaddr dot3StatsFramesTooLong; 1882 bge_hostaddr etherStatsJabbers; 1883 bge_hostaddr etherStatsUndersizePkts; 1884 bge_hostaddr inRangeLengthError; 1885 bge_hostaddr outRangeLengthError; 1886 bge_hostaddr etherStatsPkts64Octets; 1887 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1888 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1889 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1890 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1891 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1892 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1893 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1894 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1895 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1896 }; 1897 1898 1899 /* Statistics maintained MAC Transmit block. */ 1900 struct bge_tx_mac_stats { 1901 bge_hostaddr ifHCOutOctets; 1902 bge_hostaddr Reserved2; 1903 bge_hostaddr etherStatsCollisions; 1904 bge_hostaddr outXonSent; 1905 bge_hostaddr outXoffSent; 1906 bge_hostaddr flowControlDone; 1907 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1908 bge_hostaddr dot3StatsSingleCollisionFrames; 1909 bge_hostaddr dot3StatsMultipleCollisionFrames; 1910 bge_hostaddr dot3StatsDeferredTransmissions; 1911 bge_hostaddr Reserved3; 1912 bge_hostaddr dot3StatsExcessiveCollisions; 1913 bge_hostaddr dot3StatsLateCollisions; 1914 bge_hostaddr dot3Collided2Times; 1915 bge_hostaddr dot3Collided3Times; 1916 bge_hostaddr dot3Collided4Times; 1917 bge_hostaddr dot3Collided5Times; 1918 bge_hostaddr dot3Collided6Times; 1919 bge_hostaddr dot3Collided7Times; 1920 bge_hostaddr dot3Collided8Times; 1921 bge_hostaddr dot3Collided9Times; 1922 bge_hostaddr dot3Collided10Times; 1923 bge_hostaddr dot3Collided11Times; 1924 bge_hostaddr dot3Collided12Times; 1925 bge_hostaddr dot3Collided13Times; 1926 bge_hostaddr dot3Collided14Times; 1927 bge_hostaddr dot3Collided15Times; 1928 bge_hostaddr ifHCOutUcastPkts; 1929 bge_hostaddr ifHCOutMulticastPkts; 1930 bge_hostaddr ifHCOutBroadcastPkts; 1931 bge_hostaddr dot3StatsCarrierSenseErrors; 1932 bge_hostaddr ifOutDiscards; 1933 bge_hostaddr ifOutErrors; 1934 }; 1935 1936 /* Stats counters access through registers */ 1937 struct bge_mac_stats_regs { 1938 u_int32_t ifHCOutOctets; 1939 u_int32_t Reserved0; 1940 u_int32_t etherStatsCollisions; 1941 u_int32_t outXonSent; 1942 u_int32_t outXoffSent; 1943 u_int32_t Reserved1; 1944 u_int32_t dot3StatsInternalMacTransmitErrors; 1945 u_int32_t dot3StatsSingleCollisionFrames; 1946 u_int32_t dot3StatsMultipleCollisionFrames; 1947 u_int32_t dot3StatsDeferredTransmissions; 1948 u_int32_t Reserved2; 1949 u_int32_t dot3StatsExcessiveCollisions; 1950 u_int32_t dot3StatsLateCollisions; 1951 u_int32_t Reserved3[14]; 1952 u_int32_t ifHCOutUcastPkts; 1953 u_int32_t ifHCOutMulticastPkts; 1954 u_int32_t ifHCOutBroadcastPkts; 1955 u_int32_t Reserved4[2]; 1956 u_int32_t ifHCInOctets; 1957 u_int32_t Reserved5; 1958 u_int32_t etherStatsFragments; 1959 u_int32_t ifHCInUcastPkts; 1960 u_int32_t ifHCInMulticastPkts; 1961 u_int32_t ifHCInBroadcastPkts; 1962 u_int32_t dot3StatsFCSErrors; 1963 u_int32_t dot3StatsAlignmentErrors; 1964 u_int32_t xonPauseFramesReceived; 1965 u_int32_t xoffPauseFramesReceived; 1966 u_int32_t macControlFramesReceived; 1967 u_int32_t xoffStateEntered; 1968 u_int32_t dot3StatsFramesTooLong; 1969 u_int32_t etherStatsJabbers; 1970 u_int32_t etherStatsUndersizePkts; 1971 }; 1972 1973 struct bge_stats { 1974 u_int8_t Reserved0[256]; 1975 1976 /* Statistics maintained by Receive MAC. */ 1977 struct bge_rx_mac_stats rxstats; 1978 1979 bge_hostaddr Unused1[37]; 1980 1981 /* Statistics maintained by Transmit MAC. */ 1982 struct bge_tx_mac_stats txstats; 1983 1984 bge_hostaddr Unused2[31]; 1985 1986 /* Statistics maintained by Receive List Placement. */ 1987 bge_hostaddr COSIfHCInPkts[16]; 1988 bge_hostaddr COSFramesDroppedDueToFilters; 1989 bge_hostaddr nicDmaWriteQueueFull; 1990 bge_hostaddr nicDmaWriteHighPriQueueFull; 1991 bge_hostaddr nicNoMoreRxBDs; 1992 bge_hostaddr ifInDiscards; 1993 bge_hostaddr ifInErrors; 1994 bge_hostaddr nicRecvThresholdHit; 1995 1996 bge_hostaddr Unused3[9]; 1997 1998 /* Statistics maintained by Send Data Initiator. */ 1999 bge_hostaddr COSIfHCOutPkts[16]; 2000 bge_hostaddr nicDmaReadQueueFull; 2001 bge_hostaddr nicDmaReadHighPriQueueFull; 2002 bge_hostaddr nicSendDataCompQueueFull; 2003 2004 /* Statistics maintained by Host Coalescing. */ 2005 bge_hostaddr nicRingSetSendProdIndex; 2006 bge_hostaddr nicRingStatusUpdate; 2007 bge_hostaddr nicInterrupts; 2008 bge_hostaddr nicAvoidedInterrupts; 2009 bge_hostaddr nicSendThresholdHit; 2010 2011 u_int8_t Reserved4[320]; 2012 }; 2013 2014 /* 2015 * Tigon general information block. This resides in host memory 2016 * and contains the status counters, ring control blocks and 2017 * producer pointers. 2018 */ 2019 2020 struct bge_gib { 2021 struct bge_stats bge_stats; 2022 struct bge_rcb bge_tx_rcb[16]; 2023 struct bge_rcb bge_std_rx_rcb; 2024 struct bge_rcb bge_jumbo_rx_rcb; 2025 struct bge_rcb bge_mini_rx_rcb; 2026 struct bge_rcb bge_return_rcb; 2027 }; 2028 2029 /* 2030 * NOTE! On the Alpha, we have an alignment constraint. 2031 * The first thing in the packet is a 14-byte Ethernet header. 2032 * This means that the packet is misaligned. To compensate, 2033 * we actually offset the data 2 bytes into the cluster. This 2034 * alignes the packet after the Ethernet header at a 32-bit 2035 * boundary. 2036 */ 2037 2038 #define ETHER_ALIGN 2 2039 2040 #define BGE_FRAMELEN 1518 2041 #define BGE_MAX_FRAMELEN 1536 2042 #define BGE_JUMBO_FRAMELEN 9018 2043 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2044 #define BGE_PAGE_SIZE PAGE_SIZE 2045 #define BGE_MIN_FRAMELEN 60 2046 2047 /* 2048 * Other utility macros. 2049 */ 2050 #define BGE_INC(x, y) (x) = (x + 1) % y 2051 2052 /* 2053 * Vital product data and structures. 2054 */ 2055 #define BGE_VPD_FLAG 0x8000 2056 2057 /* VPD structures */ 2058 struct vpd_res { 2059 u_int8_t vr_id; 2060 u_int8_t vr_len; 2061 u_int8_t vr_pad; 2062 }; 2063 2064 struct vpd_key { 2065 char vk_key[2]; 2066 u_int8_t vk_len; 2067 }; 2068 2069 #define VPD_RES_ID 0x82 /* ID string */ 2070 #define VPD_RES_READ 0x90 /* start of read only area */ 2071 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2072 #define VPD_RES_END 0x78 /* end tag */ 2073 2074 2075 /* 2076 * Register access macros. The Tigon always uses memory mapped register 2077 * accesses and all registers must be accessed with 32 bit operations. 2078 */ 2079 2080 #define CSR_WRITE_4(sc, reg, val) \ 2081 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2082 2083 #define CSR_READ_4(sc, reg) \ 2084 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2085 2086 #define BGE_SETBIT(sc, reg, x) \ 2087 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2088 #define BGE_CLRBIT(sc, reg, x) \ 2089 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2090 2091 #define PCI_SETBIT(dev, reg, x, s) \ 2092 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s) 2093 #define PCI_CLRBIT(dev, reg, x, s) \ 2094 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s) 2095 2096 /* 2097 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2098 * values are tuneable. They control the actual amount of buffers 2099 * allocated for the standard, mini and jumbo receive rings. 2100 */ 2101 2102 #define BGE_SSLOTS 256 2103 #define BGE_MSLOTS 256 2104 #define BGE_JSLOTS 384 2105 2106 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 2107 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2108 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2109 #define BGE_JPAGESZ PAGE_SIZE 2110 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2111 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2112 2113 struct bge_jslot { 2114 caddr_t bge_buf; 2115 int bge_inuse; 2116 }; 2117 2118 /* 2119 * Ring structures. Most of these reside in host memory and we tell 2120 * the NIC where they are via the ring control blocks. The exceptions 2121 * are the tx and command rings, which live in NIC memory and which 2122 * we access via the shared memory window. 2123 */ 2124 struct bge_ring_data { 2125 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2126 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2127 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2128 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2129 struct bge_status_block bge_status_block; 2130 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2131 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2132 struct bge_gib bge_info; 2133 }; 2134 2135 /* 2136 * Mbuf pointers. We need these to keep track of the virtual addresses 2137 * of our mbuf chains since we can only convert from physical to virtual, 2138 * not the other way around. 2139 */ 2140 struct bge_chain_data { 2141 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2142 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2143 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2144 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2145 /* Stick the jumbo mem management stuff here too. */ 2146 struct bge_jslot bge_jslots[BGE_JSLOTS]; 2147 void *bge_jumbo_buf; 2148 }; 2149 2150 struct bge_type { 2151 u_int16_t bge_vid; 2152 u_int16_t bge_did; 2153 char *bge_name; 2154 }; 2155 2156 #define BGE_HWREV_TIGON 0x01 2157 #define BGE_HWREV_TIGON_II 0x02 2158 #define BGE_TIMEOUT 100000 2159 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2160 2161 struct bge_jpool_entry { 2162 int slot; 2163 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2164 }; 2165 2166 struct bge_bcom_hack { 2167 int reg; 2168 int val; 2169 }; 2170 2171 struct bge_softc { 2172 struct arpcom arpcom; /* interface info */ 2173 device_t bge_dev; 2174 device_t bge_miibus; 2175 bus_space_handle_t bge_bhandle; 2176 vm_offset_t bge_vhandle; 2177 bus_space_tag_t bge_btag; 2178 void *bge_intrhand; 2179 struct resource *bge_irq; 2180 struct resource *bge_res; 2181 struct ifmedia bge_ifmedia; /* TBI media info */ 2182 u_int8_t bge_unit; /* interface number */ 2183 u_int8_t bge_extram; /* has external SSRAM */ 2184 u_int8_t bge_tbi; 2185 u_int8_t bge_rx_alignment_bug; 2186 u_int32_t bge_chipid; 2187 u_int8_t bge_asicrev; 2188 u_int8_t bge_chiprev; 2189 u_int8_t bge_no_3_led; 2190 struct bge_ring_data *bge_rdata; /* rings */ 2191 struct bge_chain_data bge_cdata; /* mbufs */ 2192 u_int16_t bge_tx_saved_considx; 2193 u_int16_t bge_rx_saved_considx; 2194 u_int16_t bge_ev_saved_considx; 2195 u_int16_t bge_return_ring_cnt; 2196 u_int16_t bge_std; /* current std ring head */ 2197 u_int16_t bge_jumbo; /* current jumo ring head */ 2198 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2199 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2200 u_int32_t bge_stat_ticks; 2201 u_int32_t bge_rx_coal_ticks; 2202 u_int32_t bge_tx_coal_ticks; 2203 u_int32_t bge_rx_max_coal_bds; 2204 u_int32_t bge_tx_max_coal_bds; 2205 u_int32_t bge_tx_buf_ratio; 2206 int bge_if_flags; 2207 int bge_txcnt; 2208 int bge_link; 2209 struct callout bge_stat_timer; 2210 char *bge_vpd_prodname; 2211 char *bge_vpd_readonly; 2212 }; 2213 2214 #ifdef __alpha__ 2215 #undef vtophys 2216 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 2217 #endif 2218