1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $ 34 */ 35 36 #include "opt_bnx.h" 37 #include "opt_ifpoll.h" 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/kernel.h> 43 #include <sys/interrupt.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/rman.h> 48 #include <sys/serialize.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/sysctl.h> 52 53 #include <netinet/ip.h> 54 #include <netinet/tcp.h> 55 56 #include <net/bpf.h> 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_arp.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_poll.h> 63 #include <net/if_types.h> 64 #include <net/ifq_var.h> 65 #include <net/if_ringmap.h> 66 #include <net/toeplitz.h> 67 #include <net/toeplitz2.h> 68 #include <net/vlan/if_vlan_var.h> 69 #include <net/vlan/if_vlan_ether.h> 70 71 #include <dev/netif/mii_layer/mii.h> 72 #include <dev/netif/mii_layer/miivar.h> 73 #include <dev/netif/mii_layer/brgphyreg.h> 74 75 #include "pcidevs.h" 76 #include <bus/pci/pcireg.h> 77 #include <bus/pci/pcivar.h> 78 79 #include <dev/netif/bge/if_bgereg.h> 80 #include <dev/netif/bnx/if_bnxvar.h> 81 82 /* "device miibus" required. See GENERIC if you get errors here. */ 83 #include "miibus_if.h" 84 85 #define BNX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 87 #define BNX_RESET_SHUTDOWN 0 88 #define BNX_RESET_START 1 89 #define BNX_RESET_SUSPEND 2 90 91 #define BNX_INTR_CKINTVL ((10 * hz) / 1000) /* 10ms */ 92 93 #ifdef BNX_RSS_DEBUG 94 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 95 do { \ 96 if (sc->bnx_rss_debug >= lvl) \ 97 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 98 } while (0) 99 #else /* !BNX_RSS_DEBUG */ 100 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 101 #endif /* BNX_RSS_DEBUG */ 102 103 static const struct bnx_type { 104 uint16_t bnx_vid; 105 uint16_t bnx_did; 106 char *bnx_name; 107 } bnx_devs[] = { 108 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717, 109 "Broadcom BCM5717 Gigabit Ethernet" }, 110 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C, 111 "Broadcom BCM5717C Gigabit Ethernet" }, 112 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718, 113 "Broadcom BCM5718 Gigabit Ethernet" }, 114 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719, 115 "Broadcom BCM5719 Gigabit Ethernet" }, 116 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT, 117 "Broadcom BCM5720 Gigabit Ethernet" }, 118 119 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725, 120 "Broadcom BCM5725 Gigabit Ethernet" }, 121 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727, 122 "Broadcom BCM5727 Gigabit Ethernet" }, 123 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762, 124 "Broadcom BCM5762 Gigabit Ethernet" }, 125 126 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761, 127 "Broadcom BCM57761 Gigabit Ethernet" }, 128 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762, 129 "Broadcom BCM57762 Gigabit Ethernet" }, 130 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765, 131 "Broadcom BCM57765 Gigabit Ethernet" }, 132 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766, 133 "Broadcom BCM57766 Gigabit Ethernet" }, 134 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781, 135 "Broadcom BCM57781 Gigabit Ethernet" }, 136 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782, 137 "Broadcom BCM57782 Gigabit Ethernet" }, 138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785, 139 "Broadcom BCM57785 Gigabit Ethernet" }, 140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786, 141 "Broadcom BCM57786 Gigabit Ethernet" }, 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791, 143 "Broadcom BCM57791 Fast Ethernet" }, 144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795, 145 "Broadcom BCM57795 Fast Ethernet" }, 146 147 { 0, 0, NULL } 148 }; 149 150 static const int bnx_tx_mailbox[BNX_TX_RING_MAX] = { 151 BGE_MBX_TX_HOST_PROD0_LO, 152 BGE_MBX_TX_HOST_PROD0_HI, 153 BGE_MBX_TX_HOST_PROD1_LO, 154 BGE_MBX_TX_HOST_PROD1_HI 155 }; 156 157 #define BNX_IS_JUMBO_CAPABLE(sc) ((sc)->bnx_flags & BNX_FLAG_JUMBO) 158 #define BNX_IS_5717_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_5717_PLUS) 159 #define BNX_IS_57765_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_57765_PLUS) 160 #define BNX_IS_57765_FAMILY(sc) \ 161 ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY) 162 163 typedef int (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]); 164 165 static int bnx_probe(device_t); 166 static int bnx_attach(device_t); 167 static int bnx_detach(device_t); 168 static void bnx_shutdown(device_t); 169 static int bnx_suspend(device_t); 170 static int bnx_resume(device_t); 171 static int bnx_miibus_readreg(device_t, int, int); 172 static int bnx_miibus_writereg(device_t, int, int, int); 173 static void bnx_miibus_statchg(device_t); 174 175 static int bnx_handle_status(struct bnx_softc *); 176 #ifdef IFPOLL_ENABLE 177 static void bnx_npoll(struct ifnet *, struct ifpoll_info *); 178 static void bnx_npoll_rx(struct ifnet *, void *, int); 179 static void bnx_npoll_tx(struct ifnet *, void *, int); 180 static void bnx_npoll_tx_notag(struct ifnet *, void *, int); 181 static void bnx_npoll_status(struct ifnet *); 182 static void bnx_npoll_status_notag(struct ifnet *); 183 #endif 184 static void bnx_intr_legacy(void *); 185 static void bnx_msi(void *); 186 static void bnx_intr(struct bnx_softc *); 187 static void bnx_msix_status(void *); 188 static void bnx_msix_tx_status(void *); 189 static void bnx_msix_rx(void *); 190 static void bnx_msix_rxtx(void *); 191 static void bnx_enable_intr(struct bnx_softc *); 192 static void bnx_disable_intr(struct bnx_softc *); 193 static void bnx_txeof(struct bnx_tx_ring *, uint16_t); 194 static void bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int); 195 static int bnx_alloc_intr(struct bnx_softc *); 196 static int bnx_setup_intr(struct bnx_softc *); 197 static void bnx_free_intr(struct bnx_softc *); 198 static void bnx_teardown_intr(struct bnx_softc *, int); 199 static int bnx_alloc_msix(struct bnx_softc *); 200 static void bnx_free_msix(struct bnx_softc *, boolean_t); 201 static void bnx_check_intr_rxtx(void *); 202 static void bnx_check_intr_rx(void *); 203 static void bnx_check_intr_tx(void *); 204 static void bnx_rx_std_refill_ithread(void *); 205 static void bnx_rx_std_refill(void *, void *); 206 static void bnx_rx_std_refill_sched_ipi(void *); 207 static void bnx_rx_std_refill_stop(void *); 208 static void bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *, 209 struct bnx_rx_std_ring *); 210 211 static void bnx_start(struct ifnet *, struct ifaltq_subque *); 212 static int bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 213 static void bnx_init(void *); 214 static void bnx_stop(struct bnx_softc *); 215 static void bnx_watchdog(struct ifaltq_subque *); 216 static int bnx_ifmedia_upd(struct ifnet *); 217 static void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 static void bnx_tick(void *); 219 static void bnx_serialize(struct ifnet *, enum ifnet_serialize); 220 static void bnx_deserialize(struct ifnet *, enum ifnet_serialize); 221 static int bnx_tryserialize(struct ifnet *, enum ifnet_serialize); 222 #ifdef INVARIANTS 223 static void bnx_serialize_assert(struct ifnet *, enum ifnet_serialize, 224 boolean_t); 225 #endif 226 static void bnx_serialize_skipmain(struct bnx_softc *); 227 static void bnx_deserialize_skipmain(struct bnx_softc *sc); 228 229 static int bnx_alloc_jumbo_mem(struct bnx_softc *); 230 static void bnx_free_jumbo_mem(struct bnx_softc *); 231 static struct bnx_jslot 232 *bnx_jalloc(struct bnx_softc *); 233 static void bnx_jfree(void *); 234 static void bnx_jref(void *); 235 static int bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int); 236 static int bnx_newbuf_jumbo(struct bnx_softc *, int, int); 237 static void bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int); 238 static void bnx_setup_rxdesc_jumbo(struct bnx_softc *, int); 239 static int bnx_init_rx_ring_std(struct bnx_rx_std_ring *); 240 static void bnx_free_rx_ring_std(struct bnx_rx_std_ring *); 241 static int bnx_init_rx_ring_jumbo(struct bnx_softc *); 242 static void bnx_free_rx_ring_jumbo(struct bnx_softc *); 243 static void bnx_free_tx_ring(struct bnx_tx_ring *); 244 static int bnx_init_tx_ring(struct bnx_tx_ring *); 245 static int bnx_create_tx_ring(struct bnx_tx_ring *); 246 static void bnx_destroy_tx_ring(struct bnx_tx_ring *); 247 static int bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *); 248 static void bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *); 249 static int bnx_dma_alloc(device_t); 250 static void bnx_dma_free(struct bnx_softc *); 251 static int bnx_dma_block_alloc(struct bnx_softc *, bus_size_t, 252 bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *); 253 static void bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *); 254 static struct mbuf * 255 bnx_defrag_shortdma(struct mbuf *); 256 static int bnx_encap(struct bnx_tx_ring *, struct mbuf **, 257 uint32_t *, int *); 258 static int bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **, 259 uint16_t *, uint16_t *); 260 static void bnx_setup_serialize(struct bnx_softc *); 261 static void bnx_set_tick_cpuid(struct bnx_softc *, boolean_t); 262 static void bnx_setup_ring_cnt(struct bnx_softc *); 263 264 static struct pktinfo *bnx_rss_info(struct pktinfo *, 265 const struct bge_rx_bd *); 266 static void bnx_init_rss(struct bnx_softc *); 267 static void bnx_reset(struct bnx_softc *); 268 static int bnx_chipinit(struct bnx_softc *); 269 static int bnx_blockinit(struct bnx_softc *); 270 static void bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t); 271 static void bnx_enable_msi(struct bnx_softc *, boolean_t); 272 static void bnx_setmulti(struct bnx_softc *); 273 static void bnx_setpromisc(struct bnx_softc *); 274 static void bnx_stats_update_regs(struct bnx_softc *); 275 static uint32_t bnx_dma_swap_options(struct bnx_softc *); 276 277 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t); 278 static void bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t); 279 #ifdef notdef 280 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t); 281 #endif 282 static void bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t); 283 static void bnx_writembx(struct bnx_softc *, int, int); 284 static int bnx_read_nvram(struct bnx_softc *, caddr_t, int, int); 285 static uint8_t bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *); 286 static int bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t); 287 288 static void bnx_tbi_link_upd(struct bnx_softc *, uint32_t); 289 static void bnx_copper_link_upd(struct bnx_softc *, uint32_t); 290 static void bnx_autopoll_link_upd(struct bnx_softc *, uint32_t); 291 static void bnx_link_poll(struct bnx_softc *); 292 293 static int bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]); 294 static int bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]); 295 static int bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]); 296 static int bnx_get_eaddr(struct bnx_softc *, uint8_t[]); 297 298 static void bnx_coal_change(struct bnx_softc *); 299 static int bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS); 300 static int bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS); 301 static int bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS); 302 static int bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS); 303 static int bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS); 304 static int bnx_sysctl_rx_coal_bds_poll(SYSCTL_HANDLER_ARGS); 305 static int bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS); 306 static int bnx_sysctl_tx_coal_bds_poll(SYSCTL_HANDLER_ARGS); 307 static int bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS); 308 static int bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS); 309 static int bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, 310 int, int, uint32_t); 311 static int bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS); 312 313 static void bnx_sig_post_reset(struct bnx_softc *, int); 314 static void bnx_sig_pre_reset(struct bnx_softc *, int); 315 static void bnx_ape_lock_init(struct bnx_softc *); 316 static void bnx_ape_read_fw_ver(struct bnx_softc *); 317 static int bnx_ape_lock(struct bnx_softc *, int); 318 static void bnx_ape_unlock(struct bnx_softc *, int); 319 static void bnx_ape_send_event(struct bnx_softc *, uint32_t); 320 static void bnx_ape_driver_state_change(struct bnx_softc *, int); 321 322 static int bnx_msi_enable = 1; 323 static int bnx_msix_enable = 1; 324 325 static int bnx_rx_rings = 0; /* auto */ 326 static int bnx_tx_rings = 0; /* auto */ 327 328 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable); 329 TUNABLE_INT("hw.bnx.msix.enable", &bnx_msix_enable); 330 TUNABLE_INT("hw.bnx.rx_rings", &bnx_rx_rings); 331 TUNABLE_INT("hw.bnx.tx_rings", &bnx_tx_rings); 332 333 static device_method_t bnx_methods[] = { 334 /* Device interface */ 335 DEVMETHOD(device_probe, bnx_probe), 336 DEVMETHOD(device_attach, bnx_attach), 337 DEVMETHOD(device_detach, bnx_detach), 338 DEVMETHOD(device_shutdown, bnx_shutdown), 339 DEVMETHOD(device_suspend, bnx_suspend), 340 DEVMETHOD(device_resume, bnx_resume), 341 342 /* bus interface */ 343 DEVMETHOD(bus_print_child, bus_generic_print_child), 344 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 345 346 /* MII interface */ 347 DEVMETHOD(miibus_readreg, bnx_miibus_readreg), 348 DEVMETHOD(miibus_writereg, bnx_miibus_writereg), 349 DEVMETHOD(miibus_statchg, bnx_miibus_statchg), 350 351 DEVMETHOD_END 352 }; 353 354 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc)); 355 static devclass_t bnx_devclass; 356 357 DECLARE_DUMMY_MODULE(if_bnx); 358 MODULE_DEPEND(if_bnx, miibus, 1, 1, 1); 359 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL); 360 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL); 361 362 static uint32_t 363 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off) 364 { 365 device_t dev = sc->bnx_dev; 366 uint32_t val; 367 368 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 369 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 370 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 371 return (val); 372 } 373 374 static void 375 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val) 376 { 377 device_t dev = sc->bnx_dev; 378 379 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 380 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 381 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 382 } 383 384 static void 385 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val) 386 { 387 CSR_WRITE_4(sc, off, val); 388 } 389 390 static void 391 bnx_writembx(struct bnx_softc *sc, int off, int val) 392 { 393 CSR_WRITE_4(sc, off, val); 394 } 395 396 /* 397 * Read a sequence of bytes from NVRAM. 398 */ 399 static int 400 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt) 401 { 402 return (1); 403 } 404 405 /* 406 * Read a byte of data stored in the EEPROM at address 'addr.' The 407 * BCM570x supports both the traditional bitbang interface and an 408 * auto access interface for reading the EEPROM. We use the auto 409 * access method. 410 */ 411 static uint8_t 412 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest) 413 { 414 int i; 415 uint32_t byte = 0; 416 417 /* 418 * Enable use of auto EEPROM access so we can avoid 419 * having to use the bitbang method. 420 */ 421 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 422 423 /* Reset the EEPROM, load the clock period. */ 424 CSR_WRITE_4(sc, BGE_EE_ADDR, 425 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 426 DELAY(20); 427 428 /* Issue the read EEPROM command. */ 429 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 430 431 /* Wait for completion */ 432 for(i = 0; i < BNX_TIMEOUT * 10; i++) { 433 DELAY(10); 434 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 435 break; 436 } 437 438 if (i == BNX_TIMEOUT) { 439 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n"); 440 return(1); 441 } 442 443 /* Get result. */ 444 byte = CSR_READ_4(sc, BGE_EE_DATA); 445 446 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 447 448 return(0); 449 } 450 451 /* 452 * Read a sequence of bytes from the EEPROM. 453 */ 454 static int 455 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len) 456 { 457 size_t i; 458 int err; 459 uint8_t byte; 460 461 for (byte = 0, err = 0, i = 0; i < len; i++) { 462 err = bnx_eeprom_getbyte(sc, off + i, &byte); 463 if (err) 464 break; 465 *(dest + i) = byte; 466 } 467 468 return(err ? 1 : 0); 469 } 470 471 static int 472 bnx_miibus_readreg(device_t dev, int phy, int reg) 473 { 474 struct bnx_softc *sc = device_get_softc(dev); 475 uint32_t val; 476 int i; 477 478 KASSERT(phy == sc->bnx_phyno, 479 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno)); 480 481 if (bnx_ape_lock(sc, sc->bnx_phy_ape_lock) != 0) 482 return 0; 483 484 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 485 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 486 CSR_WRITE_4(sc, BGE_MI_MODE, 487 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL); 488 DELAY(80); 489 } 490 491 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 492 BGE_MIPHY(phy) | BGE_MIREG(reg)); 493 494 /* Poll for the PHY register access to complete. */ 495 for (i = 0; i < BNX_TIMEOUT; i++) { 496 DELAY(10); 497 val = CSR_READ_4(sc, BGE_MI_COMM); 498 if ((val & BGE_MICOMM_BUSY) == 0) { 499 DELAY(5); 500 val = CSR_READ_4(sc, BGE_MI_COMM); 501 break; 502 } 503 } 504 if (i == BNX_TIMEOUT) { 505 if_printf(&sc->arpcom.ac_if, "PHY read timed out " 506 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val); 507 val = 0; 508 } 509 510 /* Restore the autopoll bit if necessary. */ 511 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 512 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode); 513 DELAY(80); 514 } 515 516 bnx_ape_unlock(sc, sc->bnx_phy_ape_lock); 517 518 if (val & BGE_MICOMM_READFAIL) 519 return 0; 520 521 return (val & 0xFFFF); 522 } 523 524 static int 525 bnx_miibus_writereg(device_t dev, int phy, int reg, int val) 526 { 527 struct bnx_softc *sc = device_get_softc(dev); 528 int i; 529 530 KASSERT(phy == sc->bnx_phyno, 531 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno)); 532 533 if (bnx_ape_lock(sc, sc->bnx_phy_ape_lock) != 0) 534 return 0; 535 536 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 537 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 538 CSR_WRITE_4(sc, BGE_MI_MODE, 539 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL); 540 DELAY(80); 541 } 542 543 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 544 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 545 546 for (i = 0; i < BNX_TIMEOUT; i++) { 547 DELAY(10); 548 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 549 DELAY(5); 550 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 551 break; 552 } 553 } 554 if (i == BNX_TIMEOUT) { 555 if_printf(&sc->arpcom.ac_if, "PHY write timed out " 556 "(phy %d, reg %d, val %d)\n", phy, reg, val); 557 } 558 559 /* Restore the autopoll bit if necessary. */ 560 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 561 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode); 562 DELAY(80); 563 } 564 565 bnx_ape_unlock(sc, sc->bnx_phy_ape_lock); 566 567 return 0; 568 } 569 570 static void 571 bnx_miibus_statchg(device_t dev) 572 { 573 struct bnx_softc *sc; 574 struct mii_data *mii; 575 uint32_t mac_mode; 576 577 sc = device_get_softc(dev); 578 if ((sc->arpcom.ac_if.if_flags & IFF_RUNNING) == 0) 579 return; 580 581 mii = device_get_softc(sc->bnx_miibus); 582 583 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 584 (IFM_ACTIVE | IFM_AVALID)) { 585 switch (IFM_SUBTYPE(mii->mii_media_active)) { 586 case IFM_10_T: 587 case IFM_100_TX: 588 sc->bnx_link = 1; 589 break; 590 case IFM_1000_T: 591 case IFM_1000_SX: 592 case IFM_2500_SX: 593 sc->bnx_link = 1; 594 break; 595 default: 596 sc->bnx_link = 0; 597 break; 598 } 599 } else { 600 sc->bnx_link = 0; 601 } 602 if (sc->bnx_link == 0) 603 return; 604 605 /* 606 * APE firmware touches these registers to keep the MAC 607 * connected to the outside world. Try to keep the 608 * accesses atomic. 609 */ 610 611 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 612 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 613 614 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 615 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 616 mac_mode |= BGE_PORTMODE_GMII; 617 else 618 mac_mode |= BGE_PORTMODE_MII; 619 620 if ((mii->mii_media_active & IFM_GMASK) != IFM_FDX) 621 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 622 623 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 624 DELAY(40); 625 } 626 627 /* 628 * Memory management for jumbo frames. 629 */ 630 static int 631 bnx_alloc_jumbo_mem(struct bnx_softc *sc) 632 { 633 struct ifnet *ifp = &sc->arpcom.ac_if; 634 struct bnx_jslot *entry; 635 uint8_t *ptr; 636 bus_addr_t paddr; 637 int i, error; 638 639 /* 640 * Create tag for jumbo mbufs. 641 * This is really a bit of a kludge. We allocate a special 642 * jumbo buffer pool which (thanks to the way our DMA 643 * memory allocation works) will consist of contiguous 644 * pages. This means that even though a jumbo buffer might 645 * be larger than a page size, we don't really need to 646 * map it into more than one DMA segment. However, the 647 * default mbuf tag will result in multi-segment mappings, 648 * so we have to create a special jumbo mbuf tag that 649 * lets us get away with mapping the jumbo buffers as 650 * a single segment. I think eventually the driver should 651 * be changed so that it uses ordinary mbufs and cluster 652 * buffers, i.e. jumbo frames can span multiple DMA 653 * descriptors. But that's a project for another day. 654 */ 655 656 /* 657 * Create DMA stuffs for jumbo RX ring. 658 */ 659 error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ, 660 &sc->bnx_cdata.bnx_rx_jumbo_ring_tag, 661 &sc->bnx_cdata.bnx_rx_jumbo_ring_map, 662 (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring, 663 &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr); 664 if (error) { 665 if_printf(ifp, "could not create jumbo RX ring\n"); 666 return error; 667 } 668 669 /* 670 * Create DMA stuffs for jumbo buffer block. 671 */ 672 error = bnx_dma_block_alloc(sc, BNX_JMEM, 673 &sc->bnx_cdata.bnx_jumbo_tag, 674 &sc->bnx_cdata.bnx_jumbo_map, 675 (void **)&sc->bnx_ldata.bnx_jumbo_buf, 676 &paddr); 677 if (error) { 678 if_printf(ifp, "could not create jumbo buffer\n"); 679 return error; 680 } 681 682 SLIST_INIT(&sc->bnx_jfree_listhead); 683 684 /* 685 * Now divide it up into 9K pieces and save the addresses 686 * in an array. Note that we play an evil trick here by using 687 * the first few bytes in the buffer to hold the the address 688 * of the softc structure for this interface. This is because 689 * bnx_jfree() needs it, but it is called by the mbuf management 690 * code which will not pass it to us explicitly. 691 */ 692 for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) { 693 entry = &sc->bnx_cdata.bnx_jslots[i]; 694 entry->bnx_sc = sc; 695 entry->bnx_buf = ptr; 696 entry->bnx_paddr = paddr; 697 entry->bnx_inuse = 0; 698 entry->bnx_slot = i; 699 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link); 700 701 ptr += BNX_JLEN; 702 paddr += BNX_JLEN; 703 } 704 return 0; 705 } 706 707 static void 708 bnx_free_jumbo_mem(struct bnx_softc *sc) 709 { 710 /* Destroy jumbo RX ring. */ 711 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag, 712 sc->bnx_cdata.bnx_rx_jumbo_ring_map, 713 sc->bnx_ldata.bnx_rx_jumbo_ring); 714 715 /* Destroy jumbo buffer block. */ 716 bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag, 717 sc->bnx_cdata.bnx_jumbo_map, 718 sc->bnx_ldata.bnx_jumbo_buf); 719 } 720 721 /* 722 * Allocate a jumbo buffer. 723 */ 724 static struct bnx_jslot * 725 bnx_jalloc(struct bnx_softc *sc) 726 { 727 struct bnx_jslot *entry; 728 729 lwkt_serialize_enter(&sc->bnx_jslot_serializer); 730 entry = SLIST_FIRST(&sc->bnx_jfree_listhead); 731 if (entry) { 732 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link); 733 entry->bnx_inuse = 1; 734 } else { 735 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 736 } 737 lwkt_serialize_exit(&sc->bnx_jslot_serializer); 738 return(entry); 739 } 740 741 /* 742 * Adjust usage count on a jumbo buffer. 743 */ 744 static void 745 bnx_jref(void *arg) 746 { 747 struct bnx_jslot *entry = (struct bnx_jslot *)arg; 748 struct bnx_softc *sc = entry->bnx_sc; 749 750 if (sc == NULL) 751 panic("bnx_jref: can't find softc pointer!"); 752 753 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) { 754 panic("bnx_jref: asked to reference buffer " 755 "that we don't manage!"); 756 } else if (entry->bnx_inuse == 0) { 757 panic("bnx_jref: buffer already free!"); 758 } else { 759 atomic_add_int(&entry->bnx_inuse, 1); 760 } 761 } 762 763 /* 764 * Release a jumbo buffer. 765 */ 766 static void 767 bnx_jfree(void *arg) 768 { 769 struct bnx_jslot *entry = (struct bnx_jslot *)arg; 770 struct bnx_softc *sc = entry->bnx_sc; 771 772 if (sc == NULL) 773 panic("bnx_jfree: can't find softc pointer!"); 774 775 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) { 776 panic("bnx_jfree: asked to free buffer that we don't manage!"); 777 } else if (entry->bnx_inuse == 0) { 778 panic("bnx_jfree: buffer already free!"); 779 } else { 780 /* 781 * Possible MP race to 0, use the serializer. The atomic insn 782 * is still needed for races against bnx_jref(). 783 */ 784 lwkt_serialize_enter(&sc->bnx_jslot_serializer); 785 atomic_subtract_int(&entry->bnx_inuse, 1); 786 if (entry->bnx_inuse == 0) { 787 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, 788 entry, jslot_link); 789 } 790 lwkt_serialize_exit(&sc->bnx_jslot_serializer); 791 } 792 } 793 794 795 /* 796 * Intialize a standard receive ring descriptor. 797 */ 798 static int 799 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init) 800 { 801 struct mbuf *m_new = NULL; 802 bus_dma_segment_t seg; 803 bus_dmamap_t map; 804 int error, nsegs; 805 struct bnx_rx_buf *rb; 806 807 rb = &ret->bnx_std->bnx_rx_std_buf[i]; 808 KASSERT(!rb->bnx_rx_refilled, ("RX buf %dth has been refilled", i)); 809 810 m_new = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 811 if (m_new == NULL) { 812 error = ENOBUFS; 813 goto back; 814 } 815 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 816 m_adj(m_new, ETHER_ALIGN); 817 818 error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag, 819 ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT); 820 if (error) { 821 m_freem(m_new); 822 goto back; 823 } 824 825 if (!init) { 826 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap, 827 BUS_DMASYNC_POSTREAD); 828 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap); 829 } 830 831 map = ret->bnx_rx_tmpmap; 832 ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap; 833 834 rb->bnx_rx_dmamap = map; 835 rb->bnx_rx_mbuf = m_new; 836 rb->bnx_rx_paddr = seg.ds_addr; 837 rb->bnx_rx_len = m_new->m_len; 838 back: 839 cpu_sfence(); 840 rb->bnx_rx_refilled = 1; 841 return error; 842 } 843 844 static void 845 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i) 846 { 847 struct bnx_rx_buf *rb; 848 struct bge_rx_bd *r; 849 bus_addr_t paddr; 850 int len; 851 852 rb = &std->bnx_rx_std_buf[i]; 853 KASSERT(rb->bnx_rx_refilled, ("RX buf %dth is not refilled", i)); 854 855 paddr = rb->bnx_rx_paddr; 856 len = rb->bnx_rx_len; 857 858 cpu_mfence(); 859 860 rb->bnx_rx_refilled = 0; 861 862 r = &std->bnx_rx_std_ring[i]; 863 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr); 864 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr); 865 r->bge_len = len; 866 r->bge_idx = i; 867 r->bge_flags = BGE_RXBDFLAG_END; 868 } 869 870 /* 871 * Initialize a jumbo receive ring descriptor. This allocates 872 * a jumbo buffer from the pool managed internally by the driver. 873 */ 874 static int 875 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init) 876 { 877 struct mbuf *m_new = NULL; 878 struct bnx_jslot *buf; 879 bus_addr_t paddr; 880 881 /* Allocate the mbuf. */ 882 MGETHDR(m_new, init ? M_WAITOK : M_NOWAIT, MT_DATA); 883 if (m_new == NULL) 884 return ENOBUFS; 885 886 /* Allocate the jumbo buffer */ 887 buf = bnx_jalloc(sc); 888 if (buf == NULL) { 889 m_freem(m_new); 890 return ENOBUFS; 891 } 892 893 /* Attach the buffer to the mbuf. */ 894 m_new->m_ext.ext_arg = buf; 895 m_new->m_ext.ext_buf = buf->bnx_buf; 896 m_new->m_ext.ext_free = bnx_jfree; 897 m_new->m_ext.ext_ref = bnx_jref; 898 m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN; 899 900 m_new->m_flags |= M_EXT; 901 902 m_new->m_data = m_new->m_ext.ext_buf; 903 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 904 905 paddr = buf->bnx_paddr; 906 m_adj(m_new, ETHER_ALIGN); 907 paddr += ETHER_ALIGN; 908 909 /* Save necessary information */ 910 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new; 911 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr; 912 913 /* Set up the descriptor. */ 914 bnx_setup_rxdesc_jumbo(sc, i); 915 return 0; 916 } 917 918 static void 919 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i) 920 { 921 struct bge_rx_bd *r; 922 struct bnx_rx_buf *rc; 923 924 r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i]; 925 rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i]; 926 927 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr); 928 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr); 929 r->bge_len = rc->bnx_rx_mbuf->m_len; 930 r->bge_idx = i; 931 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 932 } 933 934 static int 935 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std) 936 { 937 int i, error; 938 939 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 940 /* Use the first RX return ring's tmp RX mbuf DMA map */ 941 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1); 942 if (error) 943 return error; 944 bnx_setup_rxdesc_std(std, i); 945 } 946 947 std->bnx_rx_std_used = 0; 948 std->bnx_rx_std_refill = 0; 949 std->bnx_rx_std_running = 0; 950 cpu_sfence(); 951 lwkt_serialize_handler_enable(&std->bnx_rx_std_serialize); 952 953 std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1; 954 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std); 955 956 return(0); 957 } 958 959 static void 960 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std) 961 { 962 int i; 963 964 lwkt_serialize_handler_disable(&std->bnx_rx_std_serialize); 965 966 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 967 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i]; 968 969 rb->bnx_rx_refilled = 0; 970 if (rb->bnx_rx_mbuf != NULL) { 971 bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap); 972 m_freem(rb->bnx_rx_mbuf); 973 rb->bnx_rx_mbuf = NULL; 974 } 975 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd)); 976 } 977 } 978 979 static int 980 bnx_init_rx_ring_jumbo(struct bnx_softc *sc) 981 { 982 struct bge_rcb *rcb; 983 int i, error; 984 985 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 986 error = bnx_newbuf_jumbo(sc, i, 1); 987 if (error) 988 return error; 989 } 990 991 sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1; 992 993 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb; 994 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 995 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 996 997 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo); 998 999 return(0); 1000 } 1001 1002 static void 1003 bnx_free_rx_ring_jumbo(struct bnx_softc *sc) 1004 { 1005 int i; 1006 1007 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1008 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i]; 1009 1010 if (rc->bnx_rx_mbuf != NULL) { 1011 m_freem(rc->bnx_rx_mbuf); 1012 rc->bnx_rx_mbuf = NULL; 1013 } 1014 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i], 1015 sizeof(struct bge_rx_bd)); 1016 } 1017 } 1018 1019 static void 1020 bnx_free_tx_ring(struct bnx_tx_ring *txr) 1021 { 1022 int i; 1023 1024 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1025 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i]; 1026 1027 if (buf->bnx_tx_mbuf != NULL) { 1028 bus_dmamap_unload(txr->bnx_tx_mtag, 1029 buf->bnx_tx_dmamap); 1030 m_freem(buf->bnx_tx_mbuf); 1031 buf->bnx_tx_mbuf = NULL; 1032 } 1033 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd)); 1034 } 1035 txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET; 1036 } 1037 1038 static int 1039 bnx_init_tx_ring(struct bnx_tx_ring *txr) 1040 { 1041 txr->bnx_tx_cnt = 0; 1042 txr->bnx_tx_saved_considx = 0; 1043 txr->bnx_tx_prodidx = 0; 1044 1045 /* Initialize transmit producer index for host-memory send ring. */ 1046 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx); 1047 1048 return(0); 1049 } 1050 1051 static void 1052 bnx_setmulti(struct bnx_softc *sc) 1053 { 1054 struct ifnet *ifp; 1055 struct ifmultiaddr *ifma; 1056 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1057 int h, i; 1058 1059 ifp = &sc->arpcom.ac_if; 1060 1061 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1062 for (i = 0; i < 4; i++) 1063 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1064 return; 1065 } 1066 1067 /* First, zot all the existing filters. */ 1068 for (i = 0; i < 4; i++) 1069 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1070 1071 /* Now program new ones. */ 1072 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1073 if (ifma->ifma_addr->sa_family != AF_LINK) 1074 continue; 1075 h = ether_crc32_le( 1076 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1077 ETHER_ADDR_LEN) & 0x7f; 1078 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1079 } 1080 1081 for (i = 0; i < 4; i++) 1082 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1083 } 1084 1085 /* 1086 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1087 * self-test results. 1088 */ 1089 static int 1090 bnx_chipinit(struct bnx_softc *sc) 1091 { 1092 uint32_t dma_rw_ctl, mode_ctl; 1093 int i; 1094 1095 /* Set endian type before we access any non-PCI registers. */ 1096 pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL, 1097 BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4); 1098 1099 /* 1100 * Clear the MAC statistics block in the NIC's 1101 * internal memory. 1102 */ 1103 for (i = BGE_STATS_BLOCK; 1104 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1105 BNX_MEMWIN_WRITE(sc, i, 0); 1106 1107 for (i = BGE_STATUS_BLOCK; 1108 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1109 BNX_MEMWIN_WRITE(sc, i, 0); 1110 1111 if (BNX_IS_57765_FAMILY(sc)) { 1112 uint32_t val; 1113 1114 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) { 1115 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 1116 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS; 1117 1118 /* Access the lower 1K of PL PCI-E block registers. */ 1119 CSR_WRITE_4(sc, BGE_MODE_CTL, 1120 val | BGE_MODECTL_PCIE_PL_SEL); 1121 1122 val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5); 1123 val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ; 1124 CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val); 1125 1126 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1127 } 1128 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) { 1129 /* Fix transmit hangs */ 1130 val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 1131 val |= BGE_CPMU_PADRNG_CTL_RDIV2; 1132 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val); 1133 1134 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 1135 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS; 1136 1137 /* Access the lower 1K of DL PCI-E block registers. */ 1138 CSR_WRITE_4(sc, BGE_MODE_CTL, 1139 val | BGE_MODECTL_PCIE_DL_SEL); 1140 1141 val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX); 1142 val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK; 1143 val |= BGE_PCIE_DL_LO_FTSMAX_VAL; 1144 CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val); 1145 1146 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1147 } 1148 1149 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 1150 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 1151 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 1152 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val); 1153 } 1154 1155 /* 1156 * Set up the PCI DMA control register. 1157 */ 1158 dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4); 1159 /* 1160 * Disable 32bytes cache alignment for DMA write to host memory 1161 * 1162 * NOTE: 1163 * 64bytes cache alignment for DMA write to host memory is still 1164 * enabled. 1165 */ 1166 dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1167 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) 1168 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1169 /* 1170 * Enable HW workaround for controllers that misinterpret 1171 * a status tag update and leave interrupts permanently 1172 * disabled. 1173 */ 1174 if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 && 1175 sc->bnx_asicrev != BGE_ASICREV_BCM5762 && 1176 !BNX_IS_57765_FAMILY(sc)) 1177 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1178 if (bootverbose) { 1179 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n", 1180 dma_rw_ctl); 1181 } 1182 pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1183 1184 /* 1185 * Set up general mode register. 1186 */ 1187 mode_ctl = bnx_dma_swap_options(sc); 1188 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1189 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1190 /* Retain Host-2-BMC settings written by APE firmware. */ 1191 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1192 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1193 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1194 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1195 } 1196 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | 1197 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM; 1198 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1199 1200 /* 1201 * Disable memory write invalidate. Apparently it is not supported 1202 * properly by these devices. Also ensure that INTx isn't disabled, 1203 * as these chips need it even when using MSI. 1204 */ 1205 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD, 1206 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4); 1207 1208 /* Set the timer prescaler (always 66Mhz) */ 1209 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1210 1211 return(0); 1212 } 1213 1214 static int 1215 bnx_blockinit(struct bnx_softc *sc) 1216 { 1217 struct bnx_intr_data *intr; 1218 struct bge_rcb *rcb; 1219 bus_size_t vrcb; 1220 bge_hostaddr taddr; 1221 uint32_t val; 1222 int i, limit; 1223 1224 /* 1225 * Initialize the memory window pointer register so that 1226 * we can access the first 32K of internal NIC RAM. This will 1227 * allow us to set up the TX send ring RCBs and the RX return 1228 * ring RCBs, plus other things which live in NIC memory. 1229 */ 1230 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1231 1232 /* Configure mbuf pool watermarks */ 1233 if (BNX_IS_57765_PLUS(sc)) { 1234 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1235 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) { 1236 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1237 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1238 } else { 1239 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1240 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1241 } 1242 } else { 1243 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1244 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1245 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1246 } 1247 1248 /* Configure DMA resource watermarks */ 1249 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1250 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1251 1252 /* Enable buffer manager */ 1253 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1254 /* 1255 * Change the arbitration algorithm of TXMBUF read request to 1256 * round-robin instead of priority based for BCM5719. When 1257 * TXFIFO is almost empty, RDMA will hold its request until 1258 * TXFIFO is not almost empty. 1259 */ 1260 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) 1261 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 1262 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 || 1263 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 || 1264 sc->bnx_chipid == BGE_CHIPID_BCM5720_A0) 1265 val |= BGE_BMANMODE_LOMBUF_ATTN; 1266 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 1267 1268 /* Poll for buffer manager start indication */ 1269 for (i = 0; i < BNX_TIMEOUT; i++) { 1270 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1271 break; 1272 DELAY(10); 1273 } 1274 1275 if (i == BNX_TIMEOUT) { 1276 if_printf(&sc->arpcom.ac_if, 1277 "buffer manager failed to start\n"); 1278 return(ENXIO); 1279 } 1280 1281 /* Enable flow-through queues */ 1282 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1283 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1284 1285 /* Wait until queue initialization is complete */ 1286 for (i = 0; i < BNX_TIMEOUT; i++) { 1287 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1288 break; 1289 DELAY(10); 1290 } 1291 1292 if (i == BNX_TIMEOUT) { 1293 if_printf(&sc->arpcom.ac_if, 1294 "flow-through queue init failed\n"); 1295 return(ENXIO); 1296 } 1297 1298 /* 1299 * Summary of rings supported by the controller: 1300 * 1301 * Standard Receive Producer Ring 1302 * - This ring is used to feed receive buffers for "standard" 1303 * sized frames (typically 1536 bytes) to the controller. 1304 * 1305 * Jumbo Receive Producer Ring 1306 * - This ring is used to feed receive buffers for jumbo sized 1307 * frames (i.e. anything bigger than the "standard" frames) 1308 * to the controller. 1309 * 1310 * Mini Receive Producer Ring 1311 * - This ring is used to feed receive buffers for "mini" 1312 * sized frames to the controller. 1313 * - This feature required external memory for the controller 1314 * but was never used in a production system. Should always 1315 * be disabled. 1316 * 1317 * Receive Return Ring 1318 * - After the controller has placed an incoming frame into a 1319 * receive buffer that buffer is moved into a receive return 1320 * ring. The driver is then responsible to passing the 1321 * buffer up to the stack. BCM5718/BCM57785 families support 1322 * multiple receive return rings. 1323 * 1324 * Send Ring 1325 * - This ring is used for outgoing frames. BCM5719/BCM5720 1326 * support multiple send rings. 1327 */ 1328 1329 /* Initialize the standard receive producer ring control block. */ 1330 rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb; 1331 rcb->bge_hostaddr.bge_addr_lo = 1332 BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr); 1333 rcb->bge_hostaddr.bge_addr_hi = 1334 BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr); 1335 if (BNX_IS_57765_PLUS(sc)) { 1336 /* 1337 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 1338 * Bits 15-2 : Maximum RX frame size 1339 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 1340 * Bit 0 : Reserved 1341 */ 1342 rcb->bge_maxlen_flags = 1343 BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2); 1344 } else { 1345 /* 1346 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1347 * Bits 15-2 : Reserved (should be 0) 1348 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1349 * Bit 0 : Reserved 1350 */ 1351 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1352 } 1353 if (BNX_IS_5717_PLUS(sc)) 1354 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 1355 else 1356 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1357 /* Write the standard receive producer ring control block. */ 1358 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1359 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1360 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1361 if (!BNX_IS_5717_PLUS(sc)) 1362 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1363 /* Reset the standard receive producer ring producer index. */ 1364 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1365 1366 /* 1367 * Initialize the jumbo RX producer ring control 1368 * block. We set the 'ring disabled' bit in the 1369 * flags field until we're actually ready to start 1370 * using this ring (i.e. once we set the MTU 1371 * high enough to require it). 1372 */ 1373 if (BNX_IS_JUMBO_CAPABLE(sc)) { 1374 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb; 1375 /* Get the jumbo receive producer ring RCB parameters. */ 1376 rcb->bge_hostaddr.bge_addr_lo = 1377 BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr); 1378 rcb->bge_hostaddr.bge_addr_hi = 1379 BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr); 1380 rcb->bge_maxlen_flags = 1381 BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN, 1382 BGE_RCB_FLAG_RING_DISABLED); 1383 if (BNX_IS_5717_PLUS(sc)) 1384 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 1385 else 1386 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1387 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1388 rcb->bge_hostaddr.bge_addr_hi); 1389 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1390 rcb->bge_hostaddr.bge_addr_lo); 1391 /* Program the jumbo receive producer ring RCB parameters. */ 1392 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1393 rcb->bge_maxlen_flags); 1394 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1395 /* Reset the jumbo receive producer ring producer index. */ 1396 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1397 } 1398 1399 /* 1400 * The BD ring replenish thresholds control how often the 1401 * hardware fetches new BD's from the producer rings in host 1402 * memory. Setting the value too low on a busy system can 1403 * starve the hardware and recue the throughpout. 1404 * 1405 * Set the BD ring replentish thresholds. The recommended 1406 * values are 1/8th the number of descriptors allocated to 1407 * each ring. 1408 */ 1409 val = 8; 1410 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1411 if (BNX_IS_JUMBO_CAPABLE(sc)) { 1412 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1413 BGE_JUMBO_RX_RING_CNT/8); 1414 } 1415 if (BNX_IS_57765_PLUS(sc)) { 1416 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 1417 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 1418 } 1419 1420 /* 1421 * Disable all send rings by setting the 'ring disabled' bit 1422 * in the flags field of all the TX send ring control blocks, 1423 * located in NIC memory. 1424 */ 1425 if (BNX_IS_5717_PLUS(sc)) 1426 limit = 4; 1427 else if (BNX_IS_57765_FAMILY(sc) || 1428 sc->bnx_asicrev == BGE_ASICREV_BCM5762) 1429 limit = 2; 1430 else 1431 limit = 1; 1432 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1433 for (i = 0; i < limit; i++) { 1434 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1435 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1436 vrcb += sizeof(struct bge_rcb); 1437 } 1438 1439 /* 1440 * Configure send ring RCBs 1441 */ 1442 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1443 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 1444 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 1445 1446 BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr); 1447 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 1448 taddr.bge_addr_hi); 1449 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 1450 taddr.bge_addr_lo); 1451 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1452 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1453 vrcb += sizeof(struct bge_rcb); 1454 } 1455 1456 /* 1457 * Disable all receive return rings by setting the 1458 * 'ring disabled' bit in the flags field of all the receive 1459 * return ring control blocks, located in NIC memory. 1460 */ 1461 if (BNX_IS_5717_PLUS(sc)) { 1462 /* Should be 17, use 16 until we get an SRAM map. */ 1463 limit = 16; 1464 } else if (BNX_IS_57765_FAMILY(sc) || 1465 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1466 limit = 4; 1467 } else { 1468 limit = 1; 1469 } 1470 /* Disable all receive return rings. */ 1471 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1472 for (i = 0; i < limit; i++) { 1473 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1474 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1475 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1476 BGE_RCB_FLAG_RING_DISABLED); 1477 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO + 1478 (i * (sizeof(uint64_t))), 0); 1479 vrcb += sizeof(struct bge_rcb); 1480 } 1481 1482 /* 1483 * Set up receive return rings. 1484 */ 1485 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1486 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 1487 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i]; 1488 1489 BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr); 1490 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 1491 taddr.bge_addr_hi); 1492 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 1493 taddr.bge_addr_lo); 1494 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1495 BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0)); 1496 vrcb += sizeof(struct bge_rcb); 1497 } 1498 1499 /* Set random backoff seed for TX */ 1500 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1501 (sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1502 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1503 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 1504 BGE_TX_BACKOFF_SEED_MASK); 1505 1506 /* Set inter-packet gap */ 1507 val = 0x2620; 1508 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1509 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1510 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 1511 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 1512 } 1513 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 1514 1515 /* 1516 * Specify which ring to use for packets that don't match 1517 * any RX rules. 1518 */ 1519 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1520 1521 /* 1522 * Configure number of RX lists. One interrupt distribution 1523 * list, sixteen active lists, one bad frames class. 1524 */ 1525 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1526 1527 /* Inialize RX list placement stats mask. */ 1528 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1529 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1530 1531 /* Disable host coalescing until we get it set up */ 1532 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1533 1534 /* Poll to make sure it's shut down. */ 1535 for (i = 0; i < BNX_TIMEOUT; i++) { 1536 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1537 break; 1538 DELAY(10); 1539 } 1540 1541 if (i == BNX_TIMEOUT) { 1542 if_printf(&sc->arpcom.ac_if, 1543 "host coalescing engine failed to idle\n"); 1544 return(ENXIO); 1545 } 1546 1547 /* Set up host coalescing defaults */ 1548 sc->bnx_coal_chg = BNX_RX_COAL_TICKS_CHG | 1549 BNX_TX_COAL_TICKS_CHG | 1550 BNX_RX_COAL_BDS_CHG | 1551 BNX_TX_COAL_BDS_CHG | 1552 BNX_RX_COAL_BDS_INT_CHG | 1553 BNX_TX_COAL_BDS_INT_CHG; 1554 bnx_coal_change(sc); 1555 1556 /* 1557 * Set up addresses of status blocks 1558 */ 1559 intr = &sc->bnx_intr_data[0]; 1560 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ); 1561 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1562 BGE_ADDR_HI(intr->bnx_status_block_paddr)); 1563 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1564 BGE_ADDR_LO(intr->bnx_status_block_paddr)); 1565 for (i = 1; i < sc->bnx_intr_cnt; ++i) { 1566 intr = &sc->bnx_intr_data[i]; 1567 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ); 1568 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_HI + ((i - 1) * 8), 1569 BGE_ADDR_HI(intr->bnx_status_block_paddr)); 1570 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_LO + ((i - 1) * 8), 1571 BGE_ADDR_LO(intr->bnx_status_block_paddr)); 1572 } 1573 1574 /* Set up status block partail update size. */ 1575 val = BGE_STATBLKSZ_32BYTE; 1576 #if 0 1577 /* 1578 * Does not seem to have visible effect in both 1579 * bulk data (1472B UDP datagram) and tiny data 1580 * (18B UDP datagram) TX tests. 1581 */ 1582 val |= BGE_HCCMODE_CLRTICK_TX; 1583 #endif 1584 /* Turn on host coalescing state machine */ 1585 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1586 1587 /* Turn on RX BD completion state machine and enable attentions */ 1588 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1589 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1590 1591 /* Turn on RX list placement state machine */ 1592 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1593 1594 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1595 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1596 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1597 BGE_MACMODE_FRMHDR_DMA_ENB; 1598 1599 if (sc->bnx_flags & BNX_FLAG_TBI) 1600 val |= BGE_PORTMODE_TBI; 1601 else if (sc->bnx_flags & BNX_FLAG_MII_SERDES) 1602 val |= BGE_PORTMODE_GMII; 1603 else 1604 val |= BGE_PORTMODE_MII; 1605 1606 /* Allow APE to send/receive frames. */ 1607 if (sc->bnx_mfw_flags & BNX_MFW_ON_APE) 1608 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 1609 1610 /* Turn on DMA, clear stats */ 1611 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1612 DELAY(40); 1613 1614 /* Set misc. local control, enable interrupts on attentions */ 1615 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1616 1617 #ifdef notdef 1618 /* Assert GPIO pins for PHY reset */ 1619 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1620 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1621 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1622 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1623 #endif 1624 1625 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) 1626 bnx_enable_msi(sc, TRUE); 1627 1628 /* Turn on write DMA state machine */ 1629 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1630 /* Enable host coalescing bug fix. */ 1631 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1632 if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) { 1633 /* Request larger DMA burst size to get better performance. */ 1634 val |= BGE_WDMAMODE_BURST_ALL_DATA; 1635 } 1636 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1637 DELAY(40); 1638 1639 if (BNX_IS_57765_PLUS(sc)) { 1640 uint32_t dmactl, dmactl_reg; 1641 1642 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762) 1643 dmactl_reg = BGE_RDMA_RSRVCTRL2; 1644 else 1645 dmactl_reg = BGE_RDMA_RSRVCTRL; 1646 1647 dmactl = CSR_READ_4(sc, dmactl_reg); 1648 /* 1649 * Adjust tx margin to prevent TX data corruption and 1650 * fix internal FIFO overflow. 1651 */ 1652 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 || 1653 sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1654 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1655 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 1656 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 1657 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 1658 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 1659 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 1660 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 1661 } 1662 /* 1663 * Enable fix for read DMA FIFO overruns. 1664 * The fix is to limit the number of RX BDs 1665 * the hardware would fetch at a fime. 1666 */ 1667 CSR_WRITE_4(sc, dmactl_reg, 1668 dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 1669 } 1670 1671 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) { 1672 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 1673 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 1674 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 1675 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 1676 } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1677 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1678 uint32_t ctrl_reg; 1679 1680 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762) 1681 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2; 1682 else 1683 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL; 1684 1685 /* 1686 * Allow 4KB burst length reads for non-LSO frames. 1687 * Enable 512B burst length reads for buffer descriptors. 1688 */ 1689 CSR_WRITE_4(sc, ctrl_reg, 1690 CSR_READ_4(sc, ctrl_reg) | 1691 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 1692 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 1693 } 1694 1695 /* Turn on read DMA state machine */ 1696 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1697 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717) 1698 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 1699 if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 || 1700 sc->bnx_asicrev == BGE_ASICREV_BCM5785 || 1701 sc->bnx_asicrev == BGE_ASICREV_BCM57780) { 1702 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1703 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1704 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1705 } 1706 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1707 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1708 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 1709 BGE_RDMAMODE_H2BNC_VLAN_DET; 1710 /* 1711 * Allow multiple outstanding read requests from 1712 * non-LSO read DMA engine. 1713 */ 1714 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 1715 } 1716 if (sc->bnx_asicrev == BGE_ASICREV_BCM57766) 1717 val |= BGE_RDMAMODE_JMB_2K_MMRR; 1718 if (sc->bnx_flags & BNX_FLAG_TSO) 1719 val |= BGE_RDMAMODE_TSO4_ENABLE; 1720 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1721 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1722 DELAY(40); 1723 1724 /* Turn on RX data completion state machine */ 1725 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1726 1727 /* Turn on RX BD initiator state machine */ 1728 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1729 1730 /* Turn on RX data and RX BD initiator state machine */ 1731 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1732 1733 /* Turn on send BD completion state machine */ 1734 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1735 1736 /* Turn on send data completion state machine */ 1737 val = BGE_SDCMODE_ENABLE; 1738 if (sc->bnx_asicrev == BGE_ASICREV_BCM5761) 1739 val |= BGE_SDCMODE_CDELAY; 1740 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1741 1742 /* Turn on send data initiator state machine */ 1743 if (sc->bnx_flags & BNX_FLAG_TSO) { 1744 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 1745 BGE_SDIMODE_HW_LSO_PRE_DMA); 1746 } else { 1747 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1748 } 1749 1750 /* Turn on send BD initiator state machine */ 1751 val = BGE_SBDIMODE_ENABLE; 1752 if (sc->bnx_tx_ringcnt > 1) 1753 val |= BGE_SBDIMODE_MULTI_TXR; 1754 CSR_WRITE_4(sc, BGE_SBDI_MODE, val); 1755 1756 /* Turn on send BD selector state machine */ 1757 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1758 1759 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1760 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1761 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1762 1763 /* ack/clear link change events */ 1764 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1765 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1766 BGE_MACSTAT_LINK_CHANGED); 1767 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1768 1769 /* 1770 * Enable attention when the link has changed state for 1771 * devices that use auto polling. 1772 */ 1773 if (sc->bnx_flags & BNX_FLAG_TBI) { 1774 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1775 } else { 1776 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 1777 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode); 1778 DELAY(80); 1779 } 1780 } 1781 1782 /* 1783 * Clear any pending link state attention. 1784 * Otherwise some link state change events may be lost until attention 1785 * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence. 1786 * It's not necessary on newer BCM chips - perhaps enabling link 1787 * state change attentions implies clearing pending attention. 1788 */ 1789 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1790 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1791 BGE_MACSTAT_LINK_CHANGED); 1792 1793 /* Enable link state change attentions. */ 1794 BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1795 1796 return(0); 1797 } 1798 1799 /* 1800 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1801 * against our list and return its name if we find a match. Note 1802 * that since the Broadcom controller contains VPD support, we 1803 * can get the device name string from the controller itself instead 1804 * of the compiled-in string. This is a little slow, but it guarantees 1805 * we'll always announce the right product name. 1806 */ 1807 static int 1808 bnx_probe(device_t dev) 1809 { 1810 const struct bnx_type *t; 1811 uint16_t product, vendor; 1812 1813 if (!pci_is_pcie(dev)) 1814 return ENXIO; 1815 1816 product = pci_get_device(dev); 1817 vendor = pci_get_vendor(dev); 1818 1819 for (t = bnx_devs; t->bnx_name != NULL; t++) { 1820 if (vendor == t->bnx_vid && product == t->bnx_did) 1821 break; 1822 } 1823 if (t->bnx_name == NULL) 1824 return ENXIO; 1825 1826 device_set_desc(dev, t->bnx_name); 1827 return 0; 1828 } 1829 1830 static int 1831 bnx_attach(device_t dev) 1832 { 1833 struct ifnet *ifp; 1834 struct bnx_softc *sc; 1835 struct bnx_rx_std_ring *std; 1836 struct sysctl_ctx_list *ctx; 1837 struct sysctl_oid_list *tree; 1838 uint32_t hwcfg = 0; 1839 int error = 0, rid, capmask, i, std_cpuid, std_cpuid_def; 1840 uint8_t ether_addr[ETHER_ADDR_LEN]; 1841 uint16_t product; 1842 uintptr_t mii_priv = 0; 1843 #if defined(BNX_TSO_DEBUG) || defined(BNX_RSS_DEBUG) || defined(BNX_TSS_DEBUG) 1844 char desc[32]; 1845 #endif 1846 1847 sc = device_get_softc(dev); 1848 sc->bnx_dev = dev; 1849 callout_init_mp(&sc->bnx_tick_timer); 1850 lwkt_serialize_init(&sc->bnx_jslot_serializer); 1851 lwkt_serialize_init(&sc->bnx_main_serialize); 1852 1853 /* Always setup interrupt mailboxes */ 1854 for (i = 0; i < BNX_INTR_MAX; ++i) { 1855 callout_init_mp(&sc->bnx_intr_data[i].bnx_intr_timer); 1856 sc->bnx_intr_data[i].bnx_sc = sc; 1857 sc->bnx_intr_data[i].bnx_intr_mbx = BGE_MBX_IRQ0_LO + (i * 8); 1858 sc->bnx_intr_data[i].bnx_intr_rid = -1; 1859 sc->bnx_intr_data[i].bnx_intr_cpuid = -1; 1860 } 1861 1862 sc->bnx_func_addr = pci_get_function(dev); 1863 product = pci_get_device(dev); 1864 1865 #ifndef BURN_BRIDGES 1866 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1867 uint32_t irq, mem; 1868 1869 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1870 mem = pci_read_config(dev, BGE_PCI_BAR0, 4); 1871 1872 device_printf(dev, "chip is in D%d power mode " 1873 "-- setting to D0\n", pci_get_powerstate(dev)); 1874 1875 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1876 1877 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1878 pci_write_config(dev, BGE_PCI_BAR0, mem, 4); 1879 } 1880 #endif /* !BURN_BRIDGE */ 1881 1882 /* 1883 * Map control/status registers. 1884 */ 1885 pci_enable_busmaster(dev); 1886 1887 rid = BGE_PCI_BAR0; 1888 sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1889 RF_ACTIVE); 1890 1891 if (sc->bnx_res == NULL) { 1892 device_printf(dev, "couldn't map memory\n"); 1893 return ENXIO; 1894 } 1895 1896 sc->bnx_btag = rman_get_bustag(sc->bnx_res); 1897 sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res); 1898 1899 /* Save various chip information */ 1900 sc->bnx_chipid = 1901 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 1902 BGE_PCIMISCCTL_ASICREV_SHIFT; 1903 if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) { 1904 /* All chips having dedicated ASICREV register have CPMU */ 1905 sc->bnx_flags |= BNX_FLAG_CPMU; 1906 1907 switch (product) { 1908 case PCI_PRODUCT_BROADCOM_BCM5717: 1909 case PCI_PRODUCT_BROADCOM_BCM5717C: 1910 case PCI_PRODUCT_BROADCOM_BCM5718: 1911 case PCI_PRODUCT_BROADCOM_BCM5719: 1912 case PCI_PRODUCT_BROADCOM_BCM5720_ALT: 1913 case PCI_PRODUCT_BROADCOM_BCM5725: 1914 case PCI_PRODUCT_BROADCOM_BCM5727: 1915 case PCI_PRODUCT_BROADCOM_BCM5762: 1916 sc->bnx_chipid = pci_read_config(dev, 1917 BGE_PCI_GEN2_PRODID_ASICREV, 4); 1918 break; 1919 1920 case PCI_PRODUCT_BROADCOM_BCM57761: 1921 case PCI_PRODUCT_BROADCOM_BCM57762: 1922 case PCI_PRODUCT_BROADCOM_BCM57765: 1923 case PCI_PRODUCT_BROADCOM_BCM57766: 1924 case PCI_PRODUCT_BROADCOM_BCM57781: 1925 case PCI_PRODUCT_BROADCOM_BCM57782: 1926 case PCI_PRODUCT_BROADCOM_BCM57785: 1927 case PCI_PRODUCT_BROADCOM_BCM57786: 1928 case PCI_PRODUCT_BROADCOM_BCM57791: 1929 case PCI_PRODUCT_BROADCOM_BCM57795: 1930 sc->bnx_chipid = pci_read_config(dev, 1931 BGE_PCI_GEN15_PRODID_ASICREV, 4); 1932 break; 1933 1934 default: 1935 sc->bnx_chipid = pci_read_config(dev, 1936 BGE_PCI_PRODID_ASICREV, 4); 1937 break; 1938 } 1939 } 1940 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0) 1941 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0; 1942 1943 sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid); 1944 sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid); 1945 1946 switch (sc->bnx_asicrev) { 1947 case BGE_ASICREV_BCM5717: 1948 case BGE_ASICREV_BCM5719: 1949 case BGE_ASICREV_BCM5720: 1950 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS; 1951 break; 1952 1953 case BGE_ASICREV_BCM5762: 1954 sc->bnx_flags |= BNX_FLAG_57765_PLUS; 1955 break; 1956 1957 case BGE_ASICREV_BCM57765: 1958 case BGE_ASICREV_BCM57766: 1959 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS; 1960 break; 1961 } 1962 1963 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 || 1964 sc->bnx_asicrev == BGE_ASICREV_BCM5719 || 1965 sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1966 sc->bnx_asicrev == BGE_ASICREV_BCM5762) 1967 sc->bnx_flags |= BNX_FLAG_APE; 1968 1969 sc->bnx_flags |= BNX_FLAG_TSO; 1970 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 && 1971 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0) 1972 sc->bnx_flags &= ~BNX_FLAG_TSO; 1973 1974 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 || 1975 BNX_IS_57765_FAMILY(sc)) { 1976 /* 1977 * All BCM57785 and BCM5718 families chips have a bug that 1978 * under certain situation interrupt will not be enabled 1979 * even if status tag is written to interrupt mailbox. 1980 * 1981 * While BCM5719 and BCM5720 have a hardware workaround 1982 * which could fix the above bug. 1983 * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in 1984 * bnx_chipinit(). 1985 * 1986 * For the rest of the chips in these two families, we will 1987 * have to poll the status block at high rate (10ms currently) 1988 * to check whether the interrupt is hosed or not. 1989 * See bnx_check_intr_*() for details. 1990 */ 1991 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG; 1992 } 1993 1994 sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev); 1995 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 || 1996 sc->bnx_asicrev == BGE_ASICREV_BCM5720) 1997 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048); 1998 else 1999 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096); 2000 device_printf(dev, "CHIP ID 0x%08x; " 2001 "ASIC REV 0x%02x; CHIP REV 0x%02x\n", 2002 sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev); 2003 2004 /* 2005 * Set various PHY quirk flags. 2006 */ 2007 2008 capmask = MII_CAPMASK_DEFAULT; 2009 if (product == PCI_PRODUCT_BROADCOM_BCM57791 || 2010 product == PCI_PRODUCT_BROADCOM_BCM57795) { 2011 /* 10/100 only */ 2012 capmask &= ~BMSR_EXTSTAT; 2013 } 2014 2015 mii_priv |= BRGPHY_FLAG_WIRESPEED; 2016 if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0) 2017 mii_priv |= BRGPHY_FLAG_5762_A0; 2018 2019 /* 2020 * Chips with APE need BAR2 access for APE registers/memory. 2021 */ 2022 if (sc->bnx_flags & BNX_FLAG_APE) { 2023 uint32_t pcistate; 2024 2025 rid = PCIR_BAR(2); 2026 sc->bnx_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2027 RF_ACTIVE); 2028 if (sc->bnx_res2 == NULL) { 2029 device_printf(dev, "couldn't map BAR2 memory\n"); 2030 error = ENXIO; 2031 goto fail; 2032 } 2033 2034 /* Enable APE register/memory access by host driver. */ 2035 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2036 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 2037 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 2038 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 2039 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 2040 2041 bnx_ape_lock_init(sc); 2042 bnx_ape_read_fw_ver(sc); 2043 } 2044 2045 /* Initialize if_name earlier, so if_printf could be used */ 2046 ifp = &sc->arpcom.ac_if; 2047 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2048 2049 /* 2050 * Try to reset the chip. 2051 */ 2052 bnx_sig_pre_reset(sc, BNX_RESET_SHUTDOWN); 2053 bnx_reset(sc); 2054 bnx_sig_post_reset(sc, BNX_RESET_SHUTDOWN); 2055 2056 if (bnx_chipinit(sc)) { 2057 device_printf(dev, "chip initialization failed\n"); 2058 error = ENXIO; 2059 goto fail; 2060 } 2061 2062 /* 2063 * Get station address 2064 */ 2065 error = bnx_get_eaddr(sc, ether_addr); 2066 if (error) { 2067 device_printf(dev, "failed to read station address\n"); 2068 goto fail; 2069 } 2070 2071 /* Setup RX/TX and interrupt count */ 2072 bnx_setup_ring_cnt(sc); 2073 2074 if ((sc->bnx_rx_retcnt == 1 && sc->bnx_tx_ringcnt == 1) || 2075 (sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt > 1)) { 2076 /* 2077 * The RX ring and the corresponding TX ring processing 2078 * should be on the same CPU, since they share the same 2079 * status block. 2080 */ 2081 sc->bnx_flags |= BNX_FLAG_RXTX_BUNDLE; 2082 if (bootverbose) 2083 device_printf(dev, "RX/TX bundle\n"); 2084 if (sc->bnx_tx_ringcnt > 1) { 2085 /* 2086 * Multiple TX rings do not share status block 2087 * with link status, so link status will have 2088 * to save its own status_tag. 2089 */ 2090 sc->bnx_flags |= BNX_FLAG_STATUS_HASTAG; 2091 if (bootverbose) 2092 device_printf(dev, "status needs tag\n"); 2093 } 2094 } else { 2095 KKASSERT(sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt == 1); 2096 if (bootverbose) 2097 device_printf(dev, "RX/TX not bundled\n"); 2098 } 2099 2100 error = bnx_dma_alloc(dev); 2101 if (error) 2102 goto fail; 2103 2104 /* 2105 * Allocate interrupt 2106 */ 2107 error = bnx_alloc_intr(sc); 2108 if (error) 2109 goto fail; 2110 2111 /* Setup serializers */ 2112 bnx_setup_serialize(sc); 2113 2114 /* Set default tuneable values. */ 2115 sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF; 2116 sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF; 2117 sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF; 2118 sc->bnx_rx_coal_bds_poll = sc->bnx_rx_ret_ring[0].bnx_rx_cntmax; 2119 sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF; 2120 sc->bnx_tx_coal_bds_poll = BNX_TX_COAL_BDS_POLL_DEF; 2121 sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF; 2122 sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF; 2123 2124 /* Set up ifnet structure */ 2125 ifp->if_softc = sc; 2126 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2127 ifp->if_ioctl = bnx_ioctl; 2128 ifp->if_start = bnx_start; 2129 #ifdef IFPOLL_ENABLE 2130 ifp->if_npoll = bnx_npoll; 2131 #endif 2132 ifp->if_init = bnx_init; 2133 ifp->if_serialize = bnx_serialize; 2134 ifp->if_deserialize = bnx_deserialize; 2135 ifp->if_tryserialize = bnx_tryserialize; 2136 #ifdef INVARIANTS 2137 ifp->if_serialize_assert = bnx_serialize_assert; 2138 #endif 2139 ifp->if_mtu = ETHERMTU; 2140 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2141 2142 ifp->if_capabilities |= IFCAP_HWCSUM; 2143 ifp->if_hwassist = BNX_CSUM_FEATURES; 2144 if (sc->bnx_flags & BNX_FLAG_TSO) { 2145 ifp->if_capabilities |= IFCAP_TSO; 2146 ifp->if_hwassist |= CSUM_TSO; 2147 } 2148 if (BNX_RSS_ENABLED(sc)) 2149 ifp->if_capabilities |= IFCAP_RSS; 2150 ifp->if_capenable = ifp->if_capabilities; 2151 2152 ifp->if_nmbclusters = BGE_STD_RX_RING_CNT; 2153 2154 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 2155 ifq_set_ready(&ifp->if_snd); 2156 ifq_set_subq_cnt(&ifp->if_snd, sc->bnx_tx_ringcnt); 2157 2158 if (sc->bnx_tx_ringcnt > 1) { 2159 ifp->if_mapsubq = ifq_mapsubq_modulo; 2160 ifq_set_subq_divisor(&ifp->if_snd, sc->bnx_tx_ringcnt); 2161 } 2162 2163 /* 2164 * Figure out what sort of media we have by checking the 2165 * hardware config word in the first 32k of NIC internal memory, 2166 * or fall back to examining the EEPROM if necessary. 2167 * Note: on some BCM5700 cards, this value appears to be unset. 2168 * If that's the case, we have to rely on identifying the NIC 2169 * by its PCI subsystem ID, as we do below for the SysKonnect 2170 * SK-9D41. 2171 */ 2172 if (bnx_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 2173 hwcfg = bnx_readmem_ind(sc, BGE_SRAM_DATA_CFG); 2174 } else { 2175 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2176 sizeof(hwcfg))) { 2177 device_printf(dev, "failed to read EEPROM\n"); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 hwcfg = ntohl(hwcfg); 2182 } 2183 2184 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2185 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 || 2186 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2187 sc->bnx_flags |= BNX_FLAG_TBI; 2188 2189 /* Setup MI MODE */ 2190 if (sc->bnx_flags & BNX_FLAG_CPMU) 2191 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST; 2192 else 2193 sc->bnx_mi_mode = BGE_MIMODE_BASE; 2194 2195 /* Setup link status update stuffs */ 2196 if (sc->bnx_flags & BNX_FLAG_TBI) { 2197 sc->bnx_link_upd = bnx_tbi_link_upd; 2198 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED; 2199 } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 2200 sc->bnx_link_upd = bnx_autopoll_link_upd; 2201 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED; 2202 } else { 2203 sc->bnx_link_upd = bnx_copper_link_upd; 2204 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED; 2205 } 2206 2207 /* Set default PHY address */ 2208 sc->bnx_phyno = 1; 2209 2210 /* 2211 * PHY address mapping for various devices. 2212 * 2213 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2214 * ---------+-------+-------+-------+-------+ 2215 * BCM57XX | 1 | X | X | X | 2216 * BCM5717 | 1 | 8 | 2 | 9 | 2217 * BCM5719 | 1 | 8 | 2 | 9 | 2218 * BCM5720 | 1 | 8 | 2 | 9 | 2219 * 2220 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2221 * ---------+-------+-------+-------+-------+ 2222 * BCM57XX | X | X | X | X | 2223 * BCM5717 | X | X | X | X | 2224 * BCM5719 | 3 | 10 | 4 | 11 | 2225 * BCM5720 | X | X | X | X | 2226 * 2227 * Other addresses may respond but they are not 2228 * IEEE compliant PHYs and should be ignored. 2229 */ 2230 if (BNX_IS_5717_PLUS(sc)) { 2231 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) { 2232 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 2233 BGE_SGDIGSTS_IS_SERDES) 2234 sc->bnx_phyno = sc->bnx_func_addr + 8; 2235 else 2236 sc->bnx_phyno = sc->bnx_func_addr + 1; 2237 } else { 2238 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2239 BGE_CPMU_PHY_STRAP_IS_SERDES) 2240 sc->bnx_phyno = sc->bnx_func_addr + 8; 2241 else 2242 sc->bnx_phyno = sc->bnx_func_addr + 1; 2243 } 2244 } 2245 2246 if (sc->bnx_flags & BNX_FLAG_TBI) { 2247 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK, 2248 bnx_ifmedia_upd, bnx_ifmedia_sts); 2249 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2250 ifmedia_add(&sc->bnx_ifmedia, 2251 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2252 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2253 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO); 2254 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media; 2255 } else { 2256 struct mii_probe_args mii_args; 2257 2258 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts); 2259 mii_args.mii_probemask = 1 << sc->bnx_phyno; 2260 mii_args.mii_capmask = capmask; 2261 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY; 2262 mii_args.mii_priv = mii_priv; 2263 2264 error = mii_probe(dev, &sc->bnx_miibus, &mii_args); 2265 if (error) { 2266 device_printf(dev, "MII without any PHY!\n"); 2267 goto fail; 2268 } 2269 } 2270 2271 ctx = device_get_sysctl_ctx(sc->bnx_dev); 2272 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bnx_dev)); 2273 2274 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2275 "rx_rings", CTLFLAG_RD, &sc->bnx_rx_retcnt, 0, "# of RX rings"); 2276 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2277 "tx_rings", CTLFLAG_RD, &sc->bnx_tx_ringcnt, 0, "# of TX rings"); 2278 2279 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_coal_ticks", 2280 CTLTYPE_INT | CTLFLAG_RW, 2281 sc, 0, bnx_sysctl_rx_coal_ticks, "I", 2282 "Receive coalescing ticks (usec)."); 2283 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_coal_ticks", 2284 CTLTYPE_INT | CTLFLAG_RW, 2285 sc, 0, bnx_sysctl_tx_coal_ticks, "I", 2286 "Transmit coalescing ticks (usec)."); 2287 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_coal_bds", 2288 CTLTYPE_INT | CTLFLAG_RW, 2289 sc, 0, bnx_sysctl_rx_coal_bds, "I", 2290 "Receive max coalesced BD count."); 2291 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_coal_bds_poll", 2292 CTLTYPE_INT | CTLFLAG_RW, 2293 sc, 0, bnx_sysctl_rx_coal_bds_poll, "I", 2294 "Receive max coalesced BD count in polling."); 2295 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_coal_bds", 2296 CTLTYPE_INT | CTLFLAG_RW, 2297 sc, 0, bnx_sysctl_tx_coal_bds, "I", 2298 "Transmit max coalesced BD count."); 2299 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_coal_bds_poll", 2300 CTLTYPE_INT | CTLFLAG_RW, 2301 sc, 0, bnx_sysctl_tx_coal_bds_poll, "I", 2302 "Transmit max coalesced BD count in polling."); 2303 /* 2304 * A common design characteristic for many Broadcom 2305 * client controllers is that they only support a 2306 * single outstanding DMA read operation on the PCIe 2307 * bus. This means that it will take twice as long to 2308 * fetch a TX frame that is split into header and 2309 * payload buffers as it does to fetch a single, 2310 * contiguous TX frame (2 reads vs. 1 read). For these 2311 * controllers, coalescing buffers to reduce the number 2312 * of memory reads is effective way to get maximum 2313 * performance(about 940Mbps). Without collapsing TX 2314 * buffers the maximum TCP bulk transfer performance 2315 * is about 850Mbps. However forcing coalescing mbufs 2316 * consumes a lot of CPU cycles, so leave it off by 2317 * default. 2318 */ 2319 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2320 "force_defrag", CTLTYPE_INT | CTLFLAG_RW, 2321 sc, 0, bnx_sysctl_force_defrag, "I", 2322 "Force defragment on TX path"); 2323 2324 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2325 "tx_wreg", CTLTYPE_INT | CTLFLAG_RW, 2326 sc, 0, bnx_sysctl_tx_wreg, "I", 2327 "# of segments before writing to hardware register"); 2328 2329 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2330 "std_refill", CTLTYPE_INT | CTLFLAG_RW, 2331 sc, 0, bnx_sysctl_std_refill, "I", 2332 "# of packets received before scheduling standard refilling"); 2333 2334 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2335 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2336 sc, 0, bnx_sysctl_rx_coal_bds_int, "I", 2337 "Receive max coalesced BD count during interrupt."); 2338 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2339 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2340 sc, 0, bnx_sysctl_tx_coal_bds_int, "I", 2341 "Transmit max coalesced BD count during interrupt."); 2342 2343 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) { 2344 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_cpumap", 2345 CTLTYPE_OPAQUE | CTLFLAG_RD, 2346 sc->bnx_tx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 2347 "TX ring CPU map"); 2348 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_cpumap", 2349 CTLTYPE_OPAQUE | CTLFLAG_RD, 2350 sc->bnx_rx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 2351 "RX ring CPU map"); 2352 } else { 2353 #ifdef IFPOLL_ENABLE 2354 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_poll_cpumap", 2355 CTLTYPE_OPAQUE | CTLFLAG_RD, 2356 sc->bnx_tx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 2357 "TX poll CPU map"); 2358 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_poll_cpumap", 2359 CTLTYPE_OPAQUE | CTLFLAG_RD, 2360 sc->bnx_rx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 2361 "RX poll CPU map"); 2362 #endif 2363 } 2364 2365 #ifdef BNX_RSS_DEBUG 2366 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2367 "std_refill_mask", CTLFLAG_RD, 2368 &sc->bnx_rx_std_ring.bnx_rx_std_refill, 0, ""); 2369 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2370 "std_used", CTLFLAG_RD, 2371 &sc->bnx_rx_std_ring.bnx_rx_std_used, 0, ""); 2372 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2373 "rss_debug", CTLFLAG_RW, &sc->bnx_rss_debug, 0, ""); 2374 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 2375 ksnprintf(desc, sizeof(desc), "rx_pkt%d", i); 2376 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2377 desc, CTLFLAG_RW, &sc->bnx_rx_ret_ring[i].bnx_rx_pkt, ""); 2378 2379 ksnprintf(desc, sizeof(desc), "rx_force_sched%d", i); 2380 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2381 desc, CTLFLAG_RW, 2382 &sc->bnx_rx_ret_ring[i].bnx_rx_force_sched, ""); 2383 } 2384 #endif 2385 #ifdef BNX_TSS_DEBUG 2386 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 2387 ksnprintf(desc, sizeof(desc), "tx_pkt%d", i); 2388 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2389 desc, CTLFLAG_RW, &sc->bnx_tx_ring[i].bnx_tx_pkt, ""); 2390 } 2391 #endif 2392 2393 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2394 "norxbds", CTLFLAG_RW, &sc->bnx_norxbds, ""); 2395 2396 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2397 "errors", CTLFLAG_RW, &sc->bnx_errors, ""); 2398 2399 #ifdef BNX_TSO_DEBUG 2400 for (i = 0; i < BNX_TSO_NSTATS; ++i) { 2401 ksnprintf(desc, sizeof(desc), "tso%d", i + 1); 2402 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2403 desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], ""); 2404 } 2405 #endif 2406 2407 /* 2408 * Call MI attach routine. 2409 */ 2410 ether_ifattach(ifp, ether_addr, NULL); 2411 2412 /* Setup TX rings and subqueues */ 2413 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 2414 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i); 2415 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 2416 2417 ifsq_set_cpuid(ifsq, txr->bnx_tx_cpuid); 2418 ifsq_set_hw_serialize(ifsq, &txr->bnx_tx_serialize); 2419 ifsq_set_priv(ifsq, txr); 2420 txr->bnx_ifsq = ifsq; 2421 2422 ifsq_watchdog_init(&txr->bnx_tx_watchdog, ifsq, 2423 bnx_watchdog, 0); 2424 2425 if (bootverbose) { 2426 device_printf(dev, "txr %d -> cpu%d\n", i, 2427 txr->bnx_tx_cpuid); 2428 } 2429 } 2430 2431 error = bnx_setup_intr(sc); 2432 if (error) { 2433 ether_ifdetach(ifp); 2434 goto fail; 2435 } 2436 bnx_set_tick_cpuid(sc, FALSE); 2437 2438 /* 2439 * Create RX standard ring refilling thread 2440 */ 2441 std_cpuid_def = if_ringmap_cpumap(sc->bnx_rx_rmap, 0); 2442 std_cpuid = device_getenv_int(dev, "std.cpuid", std_cpuid_def); 2443 if (std_cpuid < 0 || std_cpuid >= ncpus) { 2444 device_printf(dev, "invalid std.cpuid %d, use %d\n", 2445 std_cpuid, std_cpuid_def); 2446 std_cpuid = std_cpuid_def; 2447 } 2448 2449 std = &sc->bnx_rx_std_ring; 2450 lwkt_create(bnx_rx_std_refill_ithread, std, &std->bnx_rx_std_ithread, 2451 NULL, TDF_NOSTART | TDF_INTTHREAD, std_cpuid, 2452 "%s std", device_get_nameunit(dev)); 2453 lwkt_setpri(std->bnx_rx_std_ithread, TDPRI_INT_MED); 2454 std->bnx_rx_std_ithread->td_preemptable = lwkt_preempt; 2455 2456 return(0); 2457 fail: 2458 bnx_detach(dev); 2459 return(error); 2460 } 2461 2462 static int 2463 bnx_detach(device_t dev) 2464 { 2465 struct bnx_softc *sc = device_get_softc(dev); 2466 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring; 2467 2468 if (device_is_attached(dev)) { 2469 struct ifnet *ifp = &sc->arpcom.ac_if; 2470 2471 ifnet_serialize_all(ifp); 2472 bnx_stop(sc); 2473 bnx_teardown_intr(sc, sc->bnx_intr_cnt); 2474 ifnet_deserialize_all(ifp); 2475 2476 ether_ifdetach(ifp); 2477 } 2478 2479 if (std->bnx_rx_std_ithread != NULL) { 2480 tsleep_interlock(std, 0); 2481 2482 if (std->bnx_rx_std_ithread->td_gd == mycpu) { 2483 bnx_rx_std_refill_stop(std); 2484 } else { 2485 lwkt_send_ipiq(std->bnx_rx_std_ithread->td_gd, 2486 bnx_rx_std_refill_stop, std); 2487 } 2488 2489 tsleep(std, PINTERLOCKED, "bnx_detach", 0); 2490 if (bootverbose) 2491 device_printf(dev, "RX std ithread exited\n"); 2492 2493 lwkt_synchronize_ipiqs("bnx_detach_ipiq"); 2494 } 2495 2496 if (sc->bnx_flags & BNX_FLAG_TBI) 2497 ifmedia_removeall(&sc->bnx_ifmedia); 2498 if (sc->bnx_miibus) 2499 device_delete_child(dev, sc->bnx_miibus); 2500 bus_generic_detach(dev); 2501 2502 bnx_free_intr(sc); 2503 2504 if (sc->bnx_msix_mem_res != NULL) { 2505 bus_release_resource(dev, SYS_RES_MEMORY, sc->bnx_msix_mem_rid, 2506 sc->bnx_msix_mem_res); 2507 } 2508 if (sc->bnx_res != NULL) { 2509 bus_release_resource(dev, SYS_RES_MEMORY, 2510 BGE_PCI_BAR0, sc->bnx_res); 2511 } 2512 if (sc->bnx_res2 != NULL) { 2513 bus_release_resource(dev, SYS_RES_MEMORY, 2514 PCIR_BAR(2), sc->bnx_res2); 2515 } 2516 2517 bnx_dma_free(sc); 2518 2519 if (sc->bnx_serialize != NULL) 2520 kfree(sc->bnx_serialize, M_DEVBUF); 2521 2522 if (sc->bnx_rx_rmap != NULL) 2523 if_ringmap_free(sc->bnx_rx_rmap); 2524 if (sc->bnx_tx_rmap != NULL) 2525 if_ringmap_free(sc->bnx_tx_rmap); 2526 2527 return 0; 2528 } 2529 2530 static void 2531 bnx_reset(struct bnx_softc *sc) 2532 { 2533 device_t dev = sc->bnx_dev; 2534 uint32_t cachesize, command, reset, mac_mode, mac_mode_mask; 2535 void (*write_op)(struct bnx_softc *, uint32_t, uint32_t); 2536 int i, val = 0; 2537 uint16_t devctl; 2538 2539 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 2540 if (sc->bnx_mfw_flags & BNX_MFW_ON_APE) 2541 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2542 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 2543 2544 write_op = bnx_writemem_direct; 2545 2546 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 2547 for (i = 0; i < 8000; i++) { 2548 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 2549 break; 2550 DELAY(20); 2551 } 2552 if (i == 8000) 2553 if_printf(&sc->arpcom.ac_if, "NVRAM lock timedout!\n"); 2554 2555 /* Take APE lock when performing reset. */ 2556 bnx_ape_lock(sc, BGE_APE_LOCK_GRC); 2557 2558 /* Save some important PCI state. */ 2559 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2560 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2561 2562 pci_write_config(dev, BGE_PCI_MISC_CTL, 2563 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2564 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2565 BGE_PCIMISCCTL_TAGGED_STATUS, 4); 2566 2567 /* Disable fastboot on controllers that support it. */ 2568 if (bootverbose) 2569 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n"); 2570 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2571 2572 /* 2573 * Write the magic number to SRAM at offset 0xB50. 2574 * When firmware finishes its initialization it will 2575 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 2576 */ 2577 bnx_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2578 2579 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2580 2581 /* XXX: Broadcom Linux driver. */ 2582 /* Force PCI-E 1.0a mode */ 2583 if (!BNX_IS_57765_PLUS(sc) && 2584 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) == 2585 (BGE_PCIE_PHY_TSTCTL_PSCRAM | 2586 BGE_PCIE_PHY_TSTCTL_PCIE10)) { 2587 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL, 2588 BGE_PCIE_PHY_TSTCTL_PSCRAM); 2589 } 2590 if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) { 2591 /* Prevent PCIE link training during global reset */ 2592 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2593 reset |= (1<<29); 2594 } 2595 2596 /* 2597 * Set GPHY Power Down Override to leave GPHY 2598 * powered up in D0 uninitialized. 2599 */ 2600 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) 2601 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 2602 2603 /* Issue global reset */ 2604 write_op(sc, BGE_MISC_CFG, reset); 2605 2606 DELAY(100 * 1000); 2607 2608 /* XXX: Broadcom Linux driver. */ 2609 if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) { 2610 uint32_t v; 2611 2612 DELAY(500000); /* wait for link training to complete */ 2613 v = pci_read_config(dev, 0xc4, 4); 2614 pci_write_config(dev, 0xc4, v | (1<<15), 4); 2615 } 2616 2617 devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2); 2618 2619 /* Disable no snoop and disable relaxed ordering. */ 2620 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP); 2621 2622 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */ 2623 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) { 2624 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK; 2625 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128; 2626 } 2627 2628 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2629 devctl, 2); 2630 2631 /* Clear error status. */ 2632 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS, 2633 PCIEM_DEVSTS_CORR_ERR | 2634 PCIEM_DEVSTS_NFATAL_ERR | 2635 PCIEM_DEVSTS_FATAL_ERR | 2636 PCIEM_DEVSTS_UNSUPP_REQ, 2); 2637 2638 /* Reset some of the PCI state that got zapped by reset */ 2639 pci_write_config(dev, BGE_PCI_MISC_CTL, 2640 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2641 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2642 BGE_PCIMISCCTL_TAGGED_STATUS, 4); 2643 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 2644 if (sc->bnx_mfw_flags & BNX_MFW_ON_APE) { 2645 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 2646 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 2647 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 2648 } 2649 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 2650 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2651 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2652 2653 /* Enable memory arbiter */ 2654 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2655 2656 /* Fix up byte swapping */ 2657 CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc)); 2658 2659 val = CSR_READ_4(sc, BGE_MAC_MODE); 2660 val = (val & ~mac_mode_mask) | mac_mode; 2661 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2662 DELAY(40); 2663 2664 bnx_ape_unlock(sc, BGE_APE_LOCK_GRC); 2665 2666 /* 2667 * Poll until we see the 1's complement of the magic number. 2668 * This indicates that the firmware initialization is complete. 2669 */ 2670 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) { 2671 val = bnx_readmem_ind(sc, BGE_SRAM_FW_MB); 2672 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2673 break; 2674 DELAY(10); 2675 } 2676 if (i == BNX_FIRMWARE_TIMEOUT) { 2677 if_printf(&sc->arpcom.ac_if, "firmware handshake " 2678 "timed out, found 0x%08x\n", val); 2679 } 2680 2681 /* BCM57765 A0 needs additional time before accessing. */ 2682 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) 2683 DELAY(10 * 1000); 2684 2685 /* 2686 * The 5704 in TBI mode apparently needs some special 2687 * adjustment to insure the SERDES drive level is set 2688 * to 1.2V. 2689 */ 2690 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 && 2691 (sc->bnx_flags & BNX_FLAG_TBI)) { 2692 uint32_t serdescfg; 2693 2694 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2695 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2696 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2697 } 2698 2699 CSR_WRITE_4(sc, BGE_MI_MODE, 2700 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL); 2701 DELAY(80); 2702 2703 /* XXX: Broadcom Linux driver. */ 2704 if (!BNX_IS_57765_PLUS(sc)) { 2705 uint32_t v; 2706 2707 /* Enable Data FIFO protection. */ 2708 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT); 2709 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25)); 2710 } 2711 2712 DELAY(10000); 2713 2714 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) { 2715 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 2716 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 2717 } 2718 } 2719 2720 /* 2721 * Frame reception handling. This is called if there's a frame 2722 * on the receive return list. 2723 * 2724 * Note: we have to be able to handle two possibilities here: 2725 * 1) the frame is from the jumbo recieve ring 2726 * 2) the frame is from the standard receive ring 2727 */ 2728 2729 static void 2730 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count) 2731 { 2732 struct bnx_softc *sc = ret->bnx_sc; 2733 struct bnx_rx_std_ring *std = ret->bnx_std; 2734 struct ifnet *ifp = &sc->arpcom.ac_if; 2735 int std_used = 0, cpuid = mycpuid; 2736 2737 while (ret->bnx_rx_saved_considx != rx_prod && count != 0) { 2738 struct pktinfo pi0, *pi = NULL; 2739 struct bge_rx_bd *cur_rx; 2740 struct bnx_rx_buf *rb; 2741 uint32_t rxidx; 2742 struct mbuf *m = NULL; 2743 uint16_t vlan_tag = 0; 2744 int have_tag = 0; 2745 2746 --count; 2747 2748 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx]; 2749 2750 rxidx = cur_rx->bge_idx; 2751 KKASSERT(rxidx < BGE_STD_RX_RING_CNT); 2752 2753 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT); 2754 #ifdef BNX_RSS_DEBUG 2755 ret->bnx_rx_pkt++; 2756 #endif 2757 2758 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2759 have_tag = 1; 2760 vlan_tag = cur_rx->bge_vlan_tag; 2761 } 2762 2763 if (ret->bnx_rx_cnt >= ret->bnx_rx_cntmax) { 2764 atomic_add_int(&std->bnx_rx_std_used, std_used); 2765 std_used = 0; 2766 2767 bnx_rx_std_refill_sched(ret, std); 2768 } 2769 ret->bnx_rx_cnt++; 2770 ++std_used; 2771 2772 rb = &std->bnx_rx_std_buf[rxidx]; 2773 m = rb->bnx_rx_mbuf; 2774 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2775 IFNET_STAT_INC(ifp, ierrors, 1); 2776 cpu_sfence(); 2777 rb->bnx_rx_refilled = 1; 2778 continue; 2779 } 2780 if (bnx_newbuf_std(ret, rxidx, 0)) { 2781 IFNET_STAT_INC(ifp, ierrors, 1); 2782 continue; 2783 } 2784 2785 IFNET_STAT_INC(ifp, ipackets, 1); 2786 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2787 m->m_pkthdr.rcvif = ifp; 2788 2789 if ((ifp->if_capenable & IFCAP_RXCSUM) && 2790 (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 2791 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 2792 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2793 if ((cur_rx->bge_error_flag & 2794 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 2795 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2796 } 2797 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2798 m->m_pkthdr.csum_data = 2799 cur_rx->bge_tcp_udp_csum; 2800 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2801 CSUM_PSEUDO_HDR; 2802 } 2803 } 2804 if (ifp->if_capenable & IFCAP_RSS) { 2805 pi = bnx_rss_info(&pi0, cur_rx); 2806 if (pi != NULL && 2807 (cur_rx->bge_flags & BGE_RXBDFLAG_RSS_HASH)) 2808 m_sethash(m, toeplitz_hash(cur_rx->bge_hash)); 2809 } 2810 2811 /* 2812 * If we received a packet with a vlan tag, pass it 2813 * to vlan_input() instead of ether_input(). 2814 */ 2815 if (have_tag) { 2816 m->m_flags |= M_VLANTAG; 2817 m->m_pkthdr.ether_vlantag = vlan_tag; 2818 } 2819 ifp->if_input(ifp, m, pi, cpuid); 2820 } 2821 bnx_writembx(sc, ret->bnx_rx_mbx, ret->bnx_rx_saved_considx); 2822 2823 if (std_used > 0) { 2824 int cur_std_used; 2825 2826 cur_std_used = atomic_fetchadd_int(&std->bnx_rx_std_used, 2827 std_used); 2828 if (cur_std_used + std_used >= (BGE_STD_RX_RING_CNT / 2)) { 2829 #ifdef BNX_RSS_DEBUG 2830 ret->bnx_rx_force_sched++; 2831 #endif 2832 bnx_rx_std_refill_sched(ret, std); 2833 } 2834 } 2835 } 2836 2837 static void 2838 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons) 2839 { 2840 struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if; 2841 2842 /* 2843 * Go through our tx ring and free mbufs for those 2844 * frames that have been sent. 2845 */ 2846 while (txr->bnx_tx_saved_considx != tx_cons) { 2847 struct bnx_tx_buf *buf; 2848 uint32_t idx = 0; 2849 2850 idx = txr->bnx_tx_saved_considx; 2851 buf = &txr->bnx_tx_buf[idx]; 2852 if (buf->bnx_tx_mbuf != NULL) { 2853 IFNET_STAT_INC(ifp, opackets, 1); 2854 #ifdef BNX_TSS_DEBUG 2855 txr->bnx_tx_pkt++; 2856 #endif 2857 bus_dmamap_unload(txr->bnx_tx_mtag, 2858 buf->bnx_tx_dmamap); 2859 m_freem(buf->bnx_tx_mbuf); 2860 buf->bnx_tx_mbuf = NULL; 2861 } 2862 txr->bnx_tx_cnt--; 2863 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT); 2864 } 2865 2866 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >= 2867 (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) 2868 ifsq_clr_oactive(txr->bnx_ifsq); 2869 2870 if (txr->bnx_tx_cnt == 0) 2871 ifsq_watchdog_set_count(&txr->bnx_tx_watchdog, 0); 2872 2873 if (!ifsq_is_empty(txr->bnx_ifsq)) 2874 ifsq_devstart(txr->bnx_ifsq); 2875 } 2876 2877 static int 2878 bnx_handle_status(struct bnx_softc *sc) 2879 { 2880 uint32_t status; 2881 int handle = 0; 2882 2883 status = *sc->bnx_hw_status; 2884 2885 if (status & BGE_STATFLAG_ERROR) { 2886 uint32_t val; 2887 int reset = 0; 2888 2889 sc->bnx_errors++; 2890 2891 val = CSR_READ_4(sc, BGE_FLOW_ATTN); 2892 if (val & ~BGE_FLOWATTN_MB_LOWAT) { 2893 if_printf(&sc->arpcom.ac_if, 2894 "flow attn 0x%08x\n", val); 2895 reset = 1; 2896 } 2897 2898 val = CSR_READ_4(sc, BGE_MSI_STATUS); 2899 if (val & ~BGE_MSISTAT_MSI_PCI_REQ) { 2900 if_printf(&sc->arpcom.ac_if, 2901 "msi status 0x%08x\n", val); 2902 reset = 1; 2903 } 2904 2905 val = CSR_READ_4(sc, BGE_RDMA_STATUS); 2906 if (val) { 2907 if_printf(&sc->arpcom.ac_if, 2908 "rmda status 0x%08x\n", val); 2909 reset = 1; 2910 } 2911 2912 val = CSR_READ_4(sc, BGE_WDMA_STATUS); 2913 if (val) { 2914 if_printf(&sc->arpcom.ac_if, 2915 "wdma status 0x%08x\n", val); 2916 reset = 1; 2917 } 2918 2919 if (reset) { 2920 bnx_serialize_skipmain(sc); 2921 bnx_init(sc); 2922 bnx_deserialize_skipmain(sc); 2923 } 2924 handle = 1; 2925 } 2926 2927 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt) { 2928 if (bootverbose) { 2929 if_printf(&sc->arpcom.ac_if, "link change, " 2930 "link_evt %d\n", sc->bnx_link_evt); 2931 } 2932 bnx_link_poll(sc); 2933 handle = 1; 2934 } 2935 2936 return handle; 2937 } 2938 2939 #ifdef IFPOLL_ENABLE 2940 2941 static void 2942 bnx_npoll_rx(struct ifnet *ifp __unused, void *xret, int cycle) 2943 { 2944 struct bnx_rx_ret_ring *ret = xret; 2945 uint16_t rx_prod; 2946 2947 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize); 2948 2949 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag; 2950 cpu_lfence(); 2951 2952 rx_prod = *ret->bnx_rx_considx; 2953 if (ret->bnx_rx_saved_considx != rx_prod) 2954 bnx_rxeof(ret, rx_prod, cycle); 2955 } 2956 2957 static void 2958 bnx_npoll_tx_notag(struct ifnet *ifp __unused, void *xtxr, int cycle __unused) 2959 { 2960 struct bnx_tx_ring *txr = xtxr; 2961 uint16_t tx_cons; 2962 2963 ASSERT_SERIALIZED(&txr->bnx_tx_serialize); 2964 2965 tx_cons = *txr->bnx_tx_considx; 2966 if (txr->bnx_tx_saved_considx != tx_cons) 2967 bnx_txeof(txr, tx_cons); 2968 } 2969 2970 static void 2971 bnx_npoll_tx(struct ifnet *ifp, void *xtxr, int cycle) 2972 { 2973 struct bnx_tx_ring *txr = xtxr; 2974 2975 ASSERT_SERIALIZED(&txr->bnx_tx_serialize); 2976 2977 txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag; 2978 cpu_lfence(); 2979 bnx_npoll_tx_notag(ifp, txr, cycle); 2980 } 2981 2982 static void 2983 bnx_npoll_status_notag(struct ifnet *ifp) 2984 { 2985 struct bnx_softc *sc = ifp->if_softc; 2986 2987 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 2988 2989 if (bnx_handle_status(sc)) { 2990 /* 2991 * Status changes are handled; force the chip to 2992 * update the status block to reflect whether there 2993 * are more status changes or not, else staled status 2994 * changes are always seen. 2995 */ 2996 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 2997 } 2998 } 2999 3000 static void 3001 bnx_npoll_status(struct ifnet *ifp) 3002 { 3003 struct bnx_softc *sc = ifp->if_softc; 3004 3005 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 3006 3007 sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag; 3008 cpu_lfence(); 3009 bnx_npoll_status_notag(ifp); 3010 } 3011 3012 static void 3013 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3014 { 3015 struct bnx_softc *sc = ifp->if_softc; 3016 int i; 3017 3018 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3019 3020 if (info != NULL) { 3021 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) 3022 info->ifpi_status.status_func = bnx_npoll_status; 3023 else 3024 info->ifpi_status.status_func = bnx_npoll_status_notag; 3025 info->ifpi_status.serializer = &sc->bnx_main_serialize; 3026 3027 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3028 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 3029 int cpu = if_ringmap_cpumap(sc->bnx_tx_rmap, i); 3030 3031 KKASSERT(cpu < netisr_ncpus); 3032 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) { 3033 info->ifpi_tx[cpu].poll_func = 3034 bnx_npoll_tx_notag; 3035 } else { 3036 info->ifpi_tx[cpu].poll_func = bnx_npoll_tx; 3037 } 3038 info->ifpi_tx[cpu].arg = txr; 3039 info->ifpi_tx[cpu].serializer = &txr->bnx_tx_serialize; 3040 ifsq_set_cpuid(txr->bnx_ifsq, cpu); 3041 } 3042 3043 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 3044 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i]; 3045 int cpu = if_ringmap_cpumap(sc->bnx_rx_rmap, i); 3046 3047 KKASSERT(cpu < netisr_ncpus); 3048 info->ifpi_rx[cpu].poll_func = bnx_npoll_rx; 3049 info->ifpi_rx[cpu].arg = ret; 3050 info->ifpi_rx[cpu].serializer = 3051 &ret->bnx_rx_ret_serialize; 3052 } 3053 3054 if (ifp->if_flags & IFF_RUNNING) { 3055 bnx_disable_intr(sc); 3056 bnx_set_tick_cpuid(sc, TRUE); 3057 3058 sc->bnx_coal_chg = BNX_TX_COAL_BDS_CHG | 3059 BNX_RX_COAL_BDS_CHG; 3060 bnx_coal_change(sc); 3061 } 3062 } else { 3063 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3064 ifsq_set_cpuid(sc->bnx_tx_ring[i].bnx_ifsq, 3065 sc->bnx_tx_ring[i].bnx_tx_cpuid); 3066 } 3067 if (ifp->if_flags & IFF_RUNNING) { 3068 sc->bnx_coal_chg = BNX_TX_COAL_BDS_CHG | 3069 BNX_RX_COAL_BDS_CHG; 3070 bnx_coal_change(sc); 3071 3072 bnx_enable_intr(sc); 3073 bnx_set_tick_cpuid(sc, FALSE); 3074 } 3075 } 3076 } 3077 3078 #endif /* IFPOLL_ENABLE */ 3079 3080 static void 3081 bnx_intr_legacy(void *xsc) 3082 { 3083 struct bnx_softc *sc = xsc; 3084 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; 3085 3086 if (ret->bnx_saved_status_tag == *ret->bnx_hw_status_tag) { 3087 uint32_t val; 3088 3089 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4); 3090 if (val & BGE_PCISTAT_INTR_NOTACT) 3091 return; 3092 } 3093 3094 /* 3095 * NOTE: 3096 * Interrupt will have to be disabled if tagged status 3097 * is used, else interrupt will always be asserted on 3098 * certain chips (at least on BCM5750 AX/BX). 3099 */ 3100 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3101 3102 bnx_intr(sc); 3103 } 3104 3105 static void 3106 bnx_msi(void *xsc) 3107 { 3108 bnx_intr(xsc); 3109 } 3110 3111 static void 3112 bnx_intr(struct bnx_softc *sc) 3113 { 3114 struct ifnet *ifp = &sc->arpcom.ac_if; 3115 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; 3116 3117 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 3118 3119 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag; 3120 /* 3121 * Use a load fence to ensure that status_tag is saved 3122 * before rx_prod, tx_cons and status. 3123 */ 3124 cpu_lfence(); 3125 3126 bnx_handle_status(sc); 3127 3128 if (ifp->if_flags & IFF_RUNNING) { 3129 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; 3130 uint16_t rx_prod, tx_cons; 3131 3132 lwkt_serialize_enter(&ret->bnx_rx_ret_serialize); 3133 rx_prod = *ret->bnx_rx_considx; 3134 if (ret->bnx_rx_saved_considx != rx_prod) 3135 bnx_rxeof(ret, rx_prod, -1); 3136 lwkt_serialize_exit(&ret->bnx_rx_ret_serialize); 3137 3138 lwkt_serialize_enter(&txr->bnx_tx_serialize); 3139 tx_cons = *txr->bnx_tx_considx; 3140 if (txr->bnx_tx_saved_considx != tx_cons) 3141 bnx_txeof(txr, tx_cons); 3142 lwkt_serialize_exit(&txr->bnx_tx_serialize); 3143 } 3144 3145 bnx_writembx(sc, BGE_MBX_IRQ0_LO, ret->bnx_saved_status_tag << 24); 3146 } 3147 3148 static void 3149 bnx_msix_tx_status(void *xtxr) 3150 { 3151 struct bnx_tx_ring *txr = xtxr; 3152 struct bnx_softc *sc = txr->bnx_sc; 3153 struct ifnet *ifp = &sc->arpcom.ac_if; 3154 3155 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 3156 3157 txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag; 3158 /* 3159 * Use a load fence to ensure that status_tag is saved 3160 * before tx_cons and status. 3161 */ 3162 cpu_lfence(); 3163 3164 bnx_handle_status(sc); 3165 3166 if (ifp->if_flags & IFF_RUNNING) { 3167 uint16_t tx_cons; 3168 3169 lwkt_serialize_enter(&txr->bnx_tx_serialize); 3170 tx_cons = *txr->bnx_tx_considx; 3171 if (txr->bnx_tx_saved_considx != tx_cons) 3172 bnx_txeof(txr, tx_cons); 3173 lwkt_serialize_exit(&txr->bnx_tx_serialize); 3174 } 3175 3176 bnx_writembx(sc, BGE_MBX_IRQ0_LO, txr->bnx_saved_status_tag << 24); 3177 } 3178 3179 static void 3180 bnx_msix_rx(void *xret) 3181 { 3182 struct bnx_rx_ret_ring *ret = xret; 3183 uint16_t rx_prod; 3184 3185 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize); 3186 3187 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag; 3188 /* 3189 * Use a load fence to ensure that status_tag is saved 3190 * before rx_prod. 3191 */ 3192 cpu_lfence(); 3193 3194 rx_prod = *ret->bnx_rx_considx; 3195 if (ret->bnx_rx_saved_considx != rx_prod) 3196 bnx_rxeof(ret, rx_prod, -1); 3197 3198 bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx, 3199 ret->bnx_saved_status_tag << 24); 3200 } 3201 3202 static void 3203 bnx_msix_rxtx(void *xret) 3204 { 3205 struct bnx_rx_ret_ring *ret = xret; 3206 struct bnx_tx_ring *txr = ret->bnx_txr; 3207 uint16_t rx_prod, tx_cons; 3208 3209 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize); 3210 3211 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag; 3212 /* 3213 * Use a load fence to ensure that status_tag is saved 3214 * before rx_prod and tx_cons. 3215 */ 3216 cpu_lfence(); 3217 3218 rx_prod = *ret->bnx_rx_considx; 3219 if (ret->bnx_rx_saved_considx != rx_prod) 3220 bnx_rxeof(ret, rx_prod, -1); 3221 3222 lwkt_serialize_enter(&txr->bnx_tx_serialize); 3223 tx_cons = *txr->bnx_tx_considx; 3224 if (txr->bnx_tx_saved_considx != tx_cons) 3225 bnx_txeof(txr, tx_cons); 3226 lwkt_serialize_exit(&txr->bnx_tx_serialize); 3227 3228 bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx, 3229 ret->bnx_saved_status_tag << 24); 3230 } 3231 3232 static void 3233 bnx_msix_status(void *xsc) 3234 { 3235 struct bnx_softc *sc = xsc; 3236 3237 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 3238 3239 sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag; 3240 /* 3241 * Use a load fence to ensure that status_tag is saved 3242 * before status. 3243 */ 3244 cpu_lfence(); 3245 3246 bnx_handle_status(sc); 3247 3248 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_saved_status_tag << 24); 3249 } 3250 3251 static void 3252 bnx_tick(void *xsc) 3253 { 3254 struct bnx_softc *sc = xsc; 3255 3256 lwkt_serialize_enter(&sc->bnx_main_serialize); 3257 3258 bnx_stats_update_regs(sc); 3259 3260 if (sc->bnx_flags & BNX_FLAG_TBI) { 3261 /* 3262 * Since in TBI mode auto-polling can't be used we should poll 3263 * link status manually. Here we register pending link event 3264 * and trigger interrupt. 3265 */ 3266 sc->bnx_link_evt++; 3267 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3268 } else if (!sc->bnx_link) { 3269 mii_tick(device_get_softc(sc->bnx_miibus)); 3270 } 3271 3272 callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc, 3273 sc->bnx_tick_cpuid); 3274 3275 lwkt_serialize_exit(&sc->bnx_main_serialize); 3276 } 3277 3278 static void 3279 bnx_stats_update_regs(struct bnx_softc *sc) 3280 { 3281 struct ifnet *ifp = &sc->arpcom.ac_if; 3282 struct bge_mac_stats_regs stats; 3283 uint32_t *s, val; 3284 int i; 3285 3286 s = (uint32_t *)&stats; 3287 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 3288 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 3289 s++; 3290 } 3291 3292 IFNET_STAT_SET(ifp, collisions, 3293 (stats.dot3StatsSingleCollisionFrames + 3294 stats.dot3StatsMultipleCollisionFrames + 3295 stats.dot3StatsExcessiveCollisions + 3296 stats.dot3StatsLateCollisions)); 3297 3298 val = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3299 sc->bnx_norxbds += val; 3300 } 3301 3302 /* 3303 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3304 * pointers to descriptors. 3305 */ 3306 static int 3307 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx, 3308 int *segs_used) 3309 { 3310 struct bge_tx_bd *d = NULL; 3311 uint16_t csum_flags = 0, vlan_tag = 0, mss = 0; 3312 bus_dma_segment_t segs[BNX_NSEG_NEW]; 3313 bus_dmamap_t map; 3314 int error, maxsegs, nsegs, idx, i; 3315 struct mbuf *m_head = *m_head0, *m_new; 3316 3317 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3318 #ifdef BNX_TSO_DEBUG 3319 int tso_nsegs; 3320 #endif 3321 3322 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags); 3323 if (error) 3324 return error; 3325 m_head = *m_head0; 3326 3327 #ifdef BNX_TSO_DEBUG 3328 tso_nsegs = (m_head->m_pkthdr.len / 3329 m_head->m_pkthdr.tso_segsz) - 1; 3330 if (tso_nsegs > (BNX_TSO_NSTATS - 1)) 3331 tso_nsegs = BNX_TSO_NSTATS - 1; 3332 else if (tso_nsegs < 0) 3333 tso_nsegs = 0; 3334 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++; 3335 #endif 3336 } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) { 3337 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3338 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3339 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3340 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3341 if (m_head->m_flags & M_LASTFRAG) 3342 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3343 else if (m_head->m_flags & M_FRAG) 3344 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3345 } 3346 if (m_head->m_flags & M_VLANTAG) { 3347 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 3348 vlan_tag = m_head->m_pkthdr.ether_vlantag; 3349 } 3350 3351 idx = *txidx; 3352 map = txr->bnx_tx_buf[idx].bnx_tx_dmamap; 3353 3354 maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD; 3355 KASSERT(maxsegs >= BNX_NSEG_SPARE, 3356 ("not enough segments %d", maxsegs)); 3357 3358 if (maxsegs > BNX_NSEG_NEW) 3359 maxsegs = BNX_NSEG_NEW; 3360 3361 /* 3362 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason. 3363 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN, 3364 * but when such padded frames employ the bge IP/TCP checksum 3365 * offload, the hardware checksum assist gives incorrect results 3366 * (possibly from incorporating its own padding into the UDP/TCP 3367 * checksum; who knows). If we pad such runts with zeros, the 3368 * onboard checksum comes out correct. 3369 */ 3370 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) && 3371 m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) { 3372 error = m_devpad(m_head, BNX_MIN_FRAMELEN); 3373 if (error) 3374 goto back; 3375 } 3376 3377 if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) && 3378 m_head->m_next != NULL) { 3379 m_new = bnx_defrag_shortdma(m_head); 3380 if (m_new == NULL) { 3381 error = ENOBUFS; 3382 goto back; 3383 } 3384 *m_head0 = m_head = m_new; 3385 } 3386 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3387 (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) && 3388 m_head->m_next != NULL) { 3389 /* 3390 * Forcefully defragment mbuf chain to overcome hardware 3391 * limitation which only support a single outstanding 3392 * DMA read operation. If it fails, keep moving on using 3393 * the original mbuf chain. 3394 */ 3395 m_new = m_defrag(m_head, M_NOWAIT); 3396 if (m_new != NULL) 3397 *m_head0 = m_head = m_new; 3398 } 3399 3400 error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map, 3401 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 3402 if (error) 3403 goto back; 3404 *segs_used += nsegs; 3405 3406 m_head = *m_head0; 3407 bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3408 3409 for (i = 0; ; i++) { 3410 d = &txr->bnx_tx_ring[idx]; 3411 3412 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3413 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3414 d->bge_len = segs[i].ds_len; 3415 d->bge_flags = csum_flags; 3416 d->bge_vlan_tag = vlan_tag; 3417 d->bge_mss = mss; 3418 3419 if (i == nsegs - 1) 3420 break; 3421 BNX_INC(idx, BGE_TX_RING_CNT); 3422 } 3423 /* Mark the last segment as end of packet... */ 3424 d->bge_flags |= BGE_TXBDFLAG_END; 3425 3426 /* 3427 * Insure that the map for this transmission is placed at 3428 * the array index of the last descriptor in this chain. 3429 */ 3430 txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap; 3431 txr->bnx_tx_buf[idx].bnx_tx_dmamap = map; 3432 txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head; 3433 txr->bnx_tx_cnt += nsegs; 3434 3435 BNX_INC(idx, BGE_TX_RING_CNT); 3436 *txidx = idx; 3437 back: 3438 if (error) { 3439 m_freem(*m_head0); 3440 *m_head0 = NULL; 3441 } 3442 return error; 3443 } 3444 3445 /* 3446 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3447 * to the mbuf data regions directly in the transmit descriptors. 3448 */ 3449 static void 3450 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 3451 { 3452 struct bnx_tx_ring *txr = ifsq_get_priv(ifsq); 3453 struct mbuf *m_head = NULL; 3454 uint32_t prodidx; 3455 int nsegs = 0; 3456 3457 KKASSERT(txr->bnx_ifsq == ifsq); 3458 ASSERT_SERIALIZED(&txr->bnx_tx_serialize); 3459 3460 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq)) 3461 return; 3462 3463 prodidx = txr->bnx_tx_prodidx; 3464 3465 while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) { 3466 /* 3467 * Sanity check: avoid coming within BGE_NSEG_RSVD 3468 * descriptors of the end of the ring. Also make 3469 * sure there are BGE_NSEG_SPARE descriptors for 3470 * jumbo buffers' or TSO segments' defragmentation. 3471 */ 3472 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) < 3473 (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) { 3474 ifsq_set_oactive(ifsq); 3475 break; 3476 } 3477 3478 m_head = ifsq_dequeue(ifsq); 3479 if (m_head == NULL) 3480 break; 3481 3482 /* 3483 * Pack the data into the transmit ring. If we 3484 * don't have room, set the OACTIVE flag and wait 3485 * for the NIC to drain the ring. 3486 */ 3487 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) { 3488 ifsq_set_oactive(ifsq); 3489 IFNET_STAT_INC(ifp, oerrors, 1); 3490 break; 3491 } 3492 3493 if (nsegs >= txr->bnx_tx_wreg) { 3494 /* Transmit */ 3495 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx); 3496 nsegs = 0; 3497 } 3498 3499 ETHER_BPF_MTAP(ifp, m_head); 3500 3501 /* 3502 * Set a timeout in case the chip goes out to lunch. 3503 */ 3504 ifsq_watchdog_set_count(&txr->bnx_tx_watchdog, 5); 3505 } 3506 3507 if (nsegs > 0) { 3508 /* Transmit */ 3509 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx); 3510 } 3511 txr->bnx_tx_prodidx = prodidx; 3512 } 3513 3514 static void 3515 bnx_init(void *xsc) 3516 { 3517 struct bnx_softc *sc = xsc; 3518 struct ifnet *ifp = &sc->arpcom.ac_if; 3519 uint16_t *m; 3520 uint32_t mode; 3521 int i; 3522 boolean_t polling; 3523 3524 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3525 3526 /* Cancel pending I/O and flush buffers. */ 3527 bnx_stop(sc); 3528 3529 bnx_sig_pre_reset(sc, BNX_RESET_START); 3530 bnx_reset(sc); 3531 bnx_sig_post_reset(sc, BNX_RESET_START); 3532 3533 bnx_chipinit(sc); 3534 3535 /* 3536 * Init the various state machines, ring 3537 * control blocks and firmware. 3538 */ 3539 if (bnx_blockinit(sc)) { 3540 if_printf(ifp, "initialization failure\n"); 3541 bnx_stop(sc); 3542 return; 3543 } 3544 3545 /* Specify MTU. */ 3546 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3547 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN); 3548 3549 /* Load our MAC address. */ 3550 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 3551 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3552 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3553 3554 /* Enable or disable promiscuous mode as needed. */ 3555 bnx_setpromisc(sc); 3556 3557 /* Program multicast filter. */ 3558 bnx_setmulti(sc); 3559 3560 /* Init RX ring. */ 3561 if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) { 3562 if_printf(ifp, "RX ring initialization failed\n"); 3563 bnx_stop(sc); 3564 return; 3565 } 3566 3567 /* Init jumbo RX ring. */ 3568 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) { 3569 if (bnx_init_rx_ring_jumbo(sc)) { 3570 if_printf(ifp, "Jumbo RX ring initialization failed\n"); 3571 bnx_stop(sc); 3572 return; 3573 } 3574 } 3575 3576 /* Init our RX return ring index */ 3577 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 3578 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i]; 3579 3580 ret->bnx_rx_saved_considx = 0; 3581 ret->bnx_rx_cnt = 0; 3582 } 3583 3584 /* Init TX ring. */ 3585 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 3586 bnx_init_tx_ring(&sc->bnx_tx_ring[i]); 3587 3588 /* Enable TX MAC state machine lockup fix. */ 3589 mode = CSR_READ_4(sc, BGE_TX_MODE); 3590 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 3591 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 3592 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 3593 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 3594 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 3595 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 3596 } 3597 /* Turn on transmitter */ 3598 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 3599 DELAY(100); 3600 3601 /* Initialize RSS */ 3602 mode = BGE_RXMODE_ENABLE | BGE_RXMODE_IPV6_ENABLE; 3603 if (BNX_RSS_ENABLED(sc)) { 3604 bnx_init_rss(sc); 3605 mode |= BGE_RXMODE_RSS_ENABLE | 3606 BGE_RXMODE_RSS_HASH_MASK_BITS | 3607 BGE_RXMODE_RSS_IPV4_HASH | 3608 BGE_RXMODE_RSS_TCP_IPV4_HASH; 3609 } 3610 /* Turn on receiver */ 3611 BNX_SETBIT(sc, BGE_RX_MODE, mode); 3612 DELAY(10); 3613 3614 /* 3615 * Set the number of good frames to receive after RX MBUF 3616 * Low Watermark has been reached. After the RX MAC receives 3617 * this number of frames, it will drop subsequent incoming 3618 * frames until the MBUF High Watermark is reached. 3619 */ 3620 if (BNX_IS_57765_FAMILY(sc)) 3621 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 3622 else 3623 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3624 3625 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI || 3626 sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) { 3627 if (bootverbose) { 3628 if_printf(ifp, "MSI_MODE: %#x\n", 3629 CSR_READ_4(sc, BGE_MSI_MODE)); 3630 } 3631 } 3632 3633 /* Tell firmware we're alive. */ 3634 BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3635 3636 /* Enable host interrupts if polling(4) is not enabled. */ 3637 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4); 3638 3639 polling = FALSE; 3640 #ifdef IFPOLL_ENABLE 3641 if (ifp->if_flags & IFF_NPOLLING) 3642 polling = TRUE; 3643 #endif 3644 if (polling) 3645 bnx_disable_intr(sc); 3646 else 3647 bnx_enable_intr(sc); 3648 bnx_set_tick_cpuid(sc, polling); 3649 3650 ifp->if_flags |= IFF_RUNNING; 3651 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3652 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 3653 3654 ifsq_clr_oactive(txr->bnx_ifsq); 3655 ifsq_watchdog_start(&txr->bnx_tx_watchdog); 3656 } 3657 3658 bnx_ifmedia_upd(ifp); 3659 3660 callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc, 3661 sc->bnx_tick_cpuid); 3662 } 3663 3664 /* 3665 * Set media options. 3666 */ 3667 static int 3668 bnx_ifmedia_upd(struct ifnet *ifp) 3669 { 3670 struct bnx_softc *sc = ifp->if_softc; 3671 3672 /* If this is a 1000baseX NIC, enable the TBI port. */ 3673 if (sc->bnx_flags & BNX_FLAG_TBI) { 3674 struct ifmedia *ifm = &sc->bnx_ifmedia; 3675 3676 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3677 return(EINVAL); 3678 3679 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3680 case IFM_AUTO: 3681 break; 3682 3683 case IFM_1000_SX: 3684 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3685 BNX_CLRBIT(sc, BGE_MAC_MODE, 3686 BGE_MACMODE_HALF_DUPLEX); 3687 } else { 3688 BNX_SETBIT(sc, BGE_MAC_MODE, 3689 BGE_MACMODE_HALF_DUPLEX); 3690 } 3691 DELAY(40); 3692 break; 3693 default: 3694 return(EINVAL); 3695 } 3696 } else { 3697 struct mii_data *mii = device_get_softc(sc->bnx_miibus); 3698 3699 sc->bnx_link_evt++; 3700 sc->bnx_link = 0; 3701 if (mii->mii_instance) { 3702 struct mii_softc *miisc; 3703 3704 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3705 mii_phy_reset(miisc); 3706 } 3707 mii_mediachg(mii); 3708 3709 /* 3710 * Force an interrupt so that we will call bnx_link_upd 3711 * if needed and clear any pending link state attention. 3712 * Without this we are not getting any further interrupts 3713 * for link state changes and thus will not UP the link and 3714 * not be able to send in bnx_start. The only way to get 3715 * things working was to receive a packet and get an RX 3716 * intr. 3717 * 3718 * bnx_tick should help for fiber cards and we might not 3719 * need to do this here if BNX_FLAG_TBI is set but as 3720 * we poll for fiber anyway it should not harm. 3721 */ 3722 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3723 } 3724 return(0); 3725 } 3726 3727 /* 3728 * Report current media status. 3729 */ 3730 static void 3731 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3732 { 3733 struct bnx_softc *sc = ifp->if_softc; 3734 3735 if ((ifp->if_flags & IFF_RUNNING) == 0) 3736 return; 3737 3738 if (sc->bnx_flags & BNX_FLAG_TBI) { 3739 ifmr->ifm_status = IFM_AVALID; 3740 ifmr->ifm_active = IFM_ETHER; 3741 if (CSR_READ_4(sc, BGE_MAC_STS) & 3742 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3743 ifmr->ifm_status |= IFM_ACTIVE; 3744 } else { 3745 ifmr->ifm_active |= IFM_NONE; 3746 return; 3747 } 3748 3749 ifmr->ifm_active |= IFM_1000_SX; 3750 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3751 ifmr->ifm_active |= IFM_HDX; 3752 else 3753 ifmr->ifm_active |= IFM_FDX; 3754 } else { 3755 struct mii_data *mii = device_get_softc(sc->bnx_miibus); 3756 3757 mii_pollstat(mii); 3758 ifmr->ifm_active = mii->mii_media_active; 3759 ifmr->ifm_status = mii->mii_media_status; 3760 } 3761 } 3762 3763 static int 3764 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3765 { 3766 struct bnx_softc *sc = ifp->if_softc; 3767 struct ifreq *ifr = (struct ifreq *)data; 3768 int mask, error = 0; 3769 3770 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3771 3772 switch (command) { 3773 case SIOCSIFMTU: 3774 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) || 3775 (BNX_IS_JUMBO_CAPABLE(sc) && 3776 ifr->ifr_mtu > BNX_JUMBO_MTU)) { 3777 error = EINVAL; 3778 } else if (ifp->if_mtu != ifr->ifr_mtu) { 3779 ifp->if_mtu = ifr->ifr_mtu; 3780 if (ifp->if_flags & IFF_RUNNING) 3781 bnx_init(sc); 3782 } 3783 break; 3784 case SIOCSIFFLAGS: 3785 if (ifp->if_flags & IFF_UP) { 3786 if (ifp->if_flags & IFF_RUNNING) { 3787 mask = ifp->if_flags ^ sc->bnx_if_flags; 3788 3789 /* 3790 * If only the state of the PROMISC flag 3791 * changed, then just use the 'set promisc 3792 * mode' command instead of reinitializing 3793 * the entire NIC. Doing a full re-init 3794 * means reloading the firmware and waiting 3795 * for it to start up, which may take a 3796 * second or two. Similarly for ALLMULTI. 3797 */ 3798 if (mask & IFF_PROMISC) 3799 bnx_setpromisc(sc); 3800 if (mask & IFF_ALLMULTI) 3801 bnx_setmulti(sc); 3802 } else { 3803 bnx_init(sc); 3804 } 3805 } else if (ifp->if_flags & IFF_RUNNING) { 3806 bnx_stop(sc); 3807 } 3808 sc->bnx_if_flags = ifp->if_flags; 3809 break; 3810 case SIOCADDMULTI: 3811 case SIOCDELMULTI: 3812 if (ifp->if_flags & IFF_RUNNING) 3813 bnx_setmulti(sc); 3814 break; 3815 case SIOCSIFMEDIA: 3816 case SIOCGIFMEDIA: 3817 if (sc->bnx_flags & BNX_FLAG_TBI) { 3818 error = ifmedia_ioctl(ifp, ifr, 3819 &sc->bnx_ifmedia, command); 3820 } else { 3821 struct mii_data *mii; 3822 3823 mii = device_get_softc(sc->bnx_miibus); 3824 error = ifmedia_ioctl(ifp, ifr, 3825 &mii->mii_media, command); 3826 } 3827 break; 3828 case SIOCSIFCAP: 3829 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3830 if (mask & IFCAP_HWCSUM) { 3831 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 3832 if (ifp->if_capenable & IFCAP_TXCSUM) 3833 ifp->if_hwassist |= BNX_CSUM_FEATURES; 3834 else 3835 ifp->if_hwassist &= ~BNX_CSUM_FEATURES; 3836 } 3837 if (mask & IFCAP_TSO) { 3838 ifp->if_capenable ^= (mask & IFCAP_TSO); 3839 if (ifp->if_capenable & IFCAP_TSO) 3840 ifp->if_hwassist |= CSUM_TSO; 3841 else 3842 ifp->if_hwassist &= ~CSUM_TSO; 3843 } 3844 if (mask & IFCAP_RSS) 3845 ifp->if_capenable ^= IFCAP_RSS; 3846 break; 3847 default: 3848 error = ether_ioctl(ifp, command, data); 3849 break; 3850 } 3851 return error; 3852 } 3853 3854 static void 3855 bnx_watchdog(struct ifaltq_subque *ifsq) 3856 { 3857 struct ifnet *ifp = ifsq_get_ifp(ifsq); 3858 struct bnx_softc *sc = ifp->if_softc; 3859 int i; 3860 3861 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3862 3863 if_printf(ifp, "watchdog timeout -- resetting\n"); 3864 3865 bnx_init(sc); 3866 3867 IFNET_STAT_INC(ifp, oerrors, 1); 3868 3869 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 3870 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq); 3871 } 3872 3873 /* 3874 * Stop the adapter and free any mbufs allocated to the 3875 * RX and TX lists. 3876 */ 3877 static void 3878 bnx_stop(struct bnx_softc *sc) 3879 { 3880 struct ifnet *ifp = &sc->arpcom.ac_if; 3881 int i; 3882 3883 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3884 3885 callout_stop(&sc->bnx_tick_timer); 3886 3887 /* Disable host interrupts. */ 3888 bnx_disable_intr(sc); 3889 3890 /* 3891 * Tell firmware we're shutting down. 3892 */ 3893 bnx_sig_pre_reset(sc, BNX_RESET_SHUTDOWN); 3894 3895 /* 3896 * Disable all of the receiver blocks 3897 */ 3898 bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3899 bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3900 bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3901 bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3902 bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3903 bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3904 3905 /* 3906 * Disable all of the transmit blocks 3907 */ 3908 bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3909 bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3910 bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3911 bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3912 bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3913 bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3914 3915 /* 3916 * Shut down all of the memory managers and related 3917 * state machines. 3918 */ 3919 bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3920 bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3921 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3922 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3923 3924 bnx_reset(sc); 3925 bnx_sig_post_reset(sc, BNX_RESET_SHUTDOWN); 3926 3927 /* 3928 * Tell firmware we're shutting down. 3929 */ 3930 BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3931 3932 /* Free the RX lists. */ 3933 bnx_free_rx_ring_std(&sc->bnx_rx_std_ring); 3934 3935 /* Free jumbo RX list. */ 3936 if (BNX_IS_JUMBO_CAPABLE(sc)) 3937 bnx_free_rx_ring_jumbo(sc); 3938 3939 /* Free TX buffers. */ 3940 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3941 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 3942 3943 txr->bnx_saved_status_tag = 0; 3944 bnx_free_tx_ring(txr); 3945 } 3946 3947 /* Clear saved status tag */ 3948 for (i = 0; i < sc->bnx_rx_retcnt; ++i) 3949 sc->bnx_rx_ret_ring[i].bnx_saved_status_tag = 0; 3950 3951 sc->bnx_link = 0; 3952 sc->bnx_coal_chg = 0; 3953 3954 ifp->if_flags &= ~IFF_RUNNING; 3955 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3956 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 3957 3958 ifsq_clr_oactive(txr->bnx_ifsq); 3959 ifsq_watchdog_stop(&txr->bnx_tx_watchdog); 3960 } 3961 } 3962 3963 /* 3964 * Stop all chip I/O so that the kernel's probe routines don't 3965 * get confused by errant DMAs when rebooting. 3966 */ 3967 static void 3968 bnx_shutdown(device_t dev) 3969 { 3970 struct bnx_softc *sc = device_get_softc(dev); 3971 struct ifnet *ifp = &sc->arpcom.ac_if; 3972 3973 ifnet_serialize_all(ifp); 3974 bnx_stop(sc); 3975 ifnet_deserialize_all(ifp); 3976 } 3977 3978 static int 3979 bnx_suspend(device_t dev) 3980 { 3981 struct bnx_softc *sc = device_get_softc(dev); 3982 struct ifnet *ifp = &sc->arpcom.ac_if; 3983 3984 ifnet_serialize_all(ifp); 3985 bnx_stop(sc); 3986 ifnet_deserialize_all(ifp); 3987 3988 return 0; 3989 } 3990 3991 static int 3992 bnx_resume(device_t dev) 3993 { 3994 struct bnx_softc *sc = device_get_softc(dev); 3995 struct ifnet *ifp = &sc->arpcom.ac_if; 3996 3997 ifnet_serialize_all(ifp); 3998 3999 if (ifp->if_flags & IFF_UP) { 4000 int i; 4001 4002 bnx_init(sc); 4003 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 4004 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq); 4005 } 4006 4007 ifnet_deserialize_all(ifp); 4008 4009 return 0; 4010 } 4011 4012 static void 4013 bnx_setpromisc(struct bnx_softc *sc) 4014 { 4015 struct ifnet *ifp = &sc->arpcom.ac_if; 4016 4017 if (ifp->if_flags & IFF_PROMISC) 4018 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4019 else 4020 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4021 } 4022 4023 static void 4024 bnx_dma_free(struct bnx_softc *sc) 4025 { 4026 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring; 4027 int i; 4028 4029 /* Destroy RX return rings */ 4030 if (sc->bnx_rx_ret_ring != NULL) { 4031 for (i = 0; i < sc->bnx_rx_retcnt; ++i) 4032 bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]); 4033 kfree(sc->bnx_rx_ret_ring, M_DEVBUF); 4034 } 4035 4036 /* Destroy RX mbuf DMA stuffs. */ 4037 if (std->bnx_rx_mtag != NULL) { 4038 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4039 KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL); 4040 bus_dmamap_destroy(std->bnx_rx_mtag, 4041 std->bnx_rx_std_buf[i].bnx_rx_dmamap); 4042 } 4043 bus_dma_tag_destroy(std->bnx_rx_mtag); 4044 } 4045 4046 /* Destroy standard RX ring */ 4047 bnx_dma_block_free(std->bnx_rx_std_ring_tag, 4048 std->bnx_rx_std_ring_map, std->bnx_rx_std_ring); 4049 4050 /* Destroy TX rings */ 4051 if (sc->bnx_tx_ring != NULL) { 4052 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 4053 bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]); 4054 kfree(sc->bnx_tx_ring, M_DEVBUF); 4055 } 4056 4057 if (BNX_IS_JUMBO_CAPABLE(sc)) 4058 bnx_free_jumbo_mem(sc); 4059 4060 /* Destroy status blocks */ 4061 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4062 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4063 4064 bnx_dma_block_free(intr->bnx_status_tag, 4065 intr->bnx_status_map, intr->bnx_status_block); 4066 } 4067 4068 /* Destroy the parent tag */ 4069 if (sc->bnx_cdata.bnx_parent_tag != NULL) 4070 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag); 4071 } 4072 4073 static int 4074 bnx_dma_alloc(device_t dev) 4075 { 4076 struct bnx_softc *sc = device_get_softc(dev); 4077 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring; 4078 int i, error, mbx; 4079 4080 /* 4081 * Allocate the parent bus DMA tag appropriate for PCI. 4082 * 4083 * All of the NetExtreme/NetLink controllers have 4GB boundary 4084 * DMA bug. 4085 * Whenever an address crosses a multiple of the 4GB boundary 4086 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 4087 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 4088 * state machine will lockup and cause the device to hang. 4089 */ 4090 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G, 4091 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 4092 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 4093 0, &sc->bnx_cdata.bnx_parent_tag); 4094 if (error) { 4095 device_printf(dev, "could not create parent DMA tag\n"); 4096 return error; 4097 } 4098 4099 /* 4100 * Create DMA stuffs for status blocks. 4101 */ 4102 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4103 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4104 4105 error = bnx_dma_block_alloc(sc, 4106 __VM_CACHELINE_ALIGN(BGE_STATUS_BLK_SZ), 4107 &intr->bnx_status_tag, &intr->bnx_status_map, 4108 (void *)&intr->bnx_status_block, 4109 &intr->bnx_status_block_paddr); 4110 if (error) { 4111 device_printf(dev, 4112 "could not create %dth status block\n", i); 4113 return error; 4114 } 4115 } 4116 sc->bnx_hw_status = &sc->bnx_intr_data[0].bnx_status_block->bge_status; 4117 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) { 4118 sc->bnx_hw_status_tag = 4119 &sc->bnx_intr_data[0].bnx_status_block->bge_status_tag; 4120 } 4121 4122 /* 4123 * Create DMA tag and maps for RX mbufs. 4124 */ 4125 std->bnx_sc = sc; 4126 lwkt_serialize_init(&std->bnx_rx_std_serialize); 4127 error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0, 4128 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4129 NULL, NULL, MCLBYTES, 1, MCLBYTES, 4130 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag); 4131 if (error) { 4132 device_printf(dev, "could not create RX mbuf DMA tag\n"); 4133 return error; 4134 } 4135 4136 for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) { 4137 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK, 4138 &std->bnx_rx_std_buf[i].bnx_rx_dmamap); 4139 if (error) { 4140 int j; 4141 4142 for (j = 0; j < i; ++j) { 4143 bus_dmamap_destroy(std->bnx_rx_mtag, 4144 std->bnx_rx_std_buf[j].bnx_rx_dmamap); 4145 } 4146 bus_dma_tag_destroy(std->bnx_rx_mtag); 4147 std->bnx_rx_mtag = NULL; 4148 4149 device_printf(dev, 4150 "could not create %dth RX mbuf DMA map\n", i); 4151 return error; 4152 } 4153 } 4154 4155 /* 4156 * Create DMA stuffs for standard RX ring. 4157 */ 4158 error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ, 4159 &std->bnx_rx_std_ring_tag, 4160 &std->bnx_rx_std_ring_map, 4161 (void *)&std->bnx_rx_std_ring, 4162 &std->bnx_rx_std_ring_paddr); 4163 if (error) { 4164 device_printf(dev, "could not create std RX ring\n"); 4165 return error; 4166 } 4167 4168 /* 4169 * Create RX return rings 4170 */ 4171 mbx = BGE_MBX_RX_CONS0_LO; 4172 sc->bnx_rx_ret_ring = 4173 kmalloc(sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, 4174 M_DEVBUF, 4175 M_WAITOK | M_ZERO | M_CACHEALIGN); 4176 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 4177 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i]; 4178 struct bnx_intr_data *intr; 4179 4180 ret->bnx_sc = sc; 4181 ret->bnx_std = std; 4182 ret->bnx_rx_mbx = mbx; 4183 ret->bnx_rx_cntmax = (BGE_STD_RX_RING_CNT / 4) / 4184 sc->bnx_rx_retcnt; 4185 ret->bnx_rx_mask = 1 << i; 4186 4187 if (!BNX_RSS_ENABLED(sc)) { 4188 intr = &sc->bnx_intr_data[0]; 4189 } else { 4190 KKASSERT(i + 1 < sc->bnx_intr_cnt); 4191 intr = &sc->bnx_intr_data[i + 1]; 4192 } 4193 4194 if (i == 0) { 4195 ret->bnx_rx_considx = 4196 &intr->bnx_status_block->bge_idx[0].bge_rx_prod_idx; 4197 } else if (i == 1) { 4198 ret->bnx_rx_considx = 4199 &intr->bnx_status_block->bge_rx_jumbo_cons_idx; 4200 } else if (i == 2) { 4201 ret->bnx_rx_considx = 4202 &intr->bnx_status_block->bge_rsvd1; 4203 } else if (i == 3) { 4204 ret->bnx_rx_considx = 4205 &intr->bnx_status_block->bge_rx_mini_cons_idx; 4206 } else { 4207 panic("unknown RX return ring %d\n", i); 4208 } 4209 ret->bnx_hw_status_tag = 4210 &intr->bnx_status_block->bge_status_tag; 4211 4212 error = bnx_create_rx_ret_ring(ret); 4213 if (error) { 4214 device_printf(dev, 4215 "could not create %dth RX ret ring\n", i); 4216 return error; 4217 } 4218 mbx += 8; 4219 } 4220 4221 /* 4222 * Create TX rings 4223 */ 4224 sc->bnx_tx_ring = 4225 kmalloc(sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, 4226 M_DEVBUF, 4227 M_WAITOK | M_ZERO | M_CACHEALIGN); 4228 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 4229 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 4230 struct bnx_intr_data *intr; 4231 4232 txr->bnx_sc = sc; 4233 txr->bnx_tx_mbx = bnx_tx_mailbox[i]; 4234 4235 if (sc->bnx_tx_ringcnt == 1) { 4236 intr = &sc->bnx_intr_data[0]; 4237 } else { 4238 KKASSERT(i + 1 < sc->bnx_intr_cnt); 4239 intr = &sc->bnx_intr_data[i + 1]; 4240 } 4241 4242 if ((sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) == 0) { 4243 txr->bnx_hw_status_tag = 4244 &intr->bnx_status_block->bge_status_tag; 4245 } 4246 txr->bnx_tx_considx = 4247 &intr->bnx_status_block->bge_idx[0].bge_tx_cons_idx; 4248 4249 error = bnx_create_tx_ring(txr); 4250 if (error) { 4251 device_printf(dev, 4252 "could not create %dth TX ring\n", i); 4253 return error; 4254 } 4255 } 4256 4257 /* 4258 * Create jumbo buffer pool. 4259 */ 4260 if (BNX_IS_JUMBO_CAPABLE(sc)) { 4261 error = bnx_alloc_jumbo_mem(sc); 4262 if (error) { 4263 device_printf(dev, 4264 "could not create jumbo buffer pool\n"); 4265 return error; 4266 } 4267 } 4268 4269 return 0; 4270 } 4271 4272 static int 4273 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag, 4274 bus_dmamap_t *map, void **addr, bus_addr_t *paddr) 4275 { 4276 bus_dmamem_t dmem; 4277 int error; 4278 4279 error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0, 4280 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4281 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 4282 if (error) 4283 return error; 4284 4285 *tag = dmem.dmem_tag; 4286 *map = dmem.dmem_map; 4287 *addr = dmem.dmem_addr; 4288 *paddr = dmem.dmem_busaddr; 4289 4290 return 0; 4291 } 4292 4293 static void 4294 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr) 4295 { 4296 if (tag != NULL) { 4297 bus_dmamap_unload(tag, map); 4298 bus_dmamem_free(tag, addr, map); 4299 bus_dma_tag_destroy(tag); 4300 } 4301 } 4302 4303 static void 4304 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status) 4305 { 4306 struct ifnet *ifp = &sc->arpcom.ac_if; 4307 4308 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE) 4309 4310 /* 4311 * Sometimes PCS encoding errors are detected in 4312 * TBI mode (on fiber NICs), and for some reason 4313 * the chip will signal them as link changes. 4314 * If we get a link change event, but the 'PCS 4315 * encoding error' bit in the MAC status register 4316 * is set, don't bother doing a link check. 4317 * This avoids spurious "gigabit link up" messages 4318 * that sometimes appear on fiber NICs during 4319 * periods of heavy traffic. 4320 */ 4321 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4322 if (!sc->bnx_link) { 4323 sc->bnx_link++; 4324 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) { 4325 BNX_CLRBIT(sc, BGE_MAC_MODE, 4326 BGE_MACMODE_TBI_SEND_CFGS); 4327 DELAY(40); 4328 } 4329 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4330 4331 if (bootverbose) 4332 if_printf(ifp, "link UP\n"); 4333 4334 ifp->if_link_state = LINK_STATE_UP; 4335 if_link_state_change(ifp); 4336 } 4337 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) { 4338 if (sc->bnx_link) { 4339 sc->bnx_link = 0; 4340 4341 if (bootverbose) 4342 if_printf(ifp, "link DOWN\n"); 4343 4344 ifp->if_link_state = LINK_STATE_DOWN; 4345 if_link_state_change(ifp); 4346 } 4347 } 4348 4349 #undef PCS_ENCODE_ERR 4350 4351 /* Clear the attention. */ 4352 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4353 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4354 BGE_MACSTAT_LINK_CHANGED); 4355 } 4356 4357 static void 4358 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused) 4359 { 4360 struct ifnet *ifp = &sc->arpcom.ac_if; 4361 struct mii_data *mii = device_get_softc(sc->bnx_miibus); 4362 4363 mii_pollstat(mii); 4364 bnx_miibus_statchg(sc->bnx_dev); 4365 4366 if (bootverbose) { 4367 if (sc->bnx_link) 4368 if_printf(ifp, "link UP\n"); 4369 else 4370 if_printf(ifp, "link DOWN\n"); 4371 } 4372 4373 /* Clear the attention. */ 4374 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4375 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4376 BGE_MACSTAT_LINK_CHANGED); 4377 } 4378 4379 static void 4380 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused) 4381 { 4382 struct ifnet *ifp = &sc->arpcom.ac_if; 4383 struct mii_data *mii = device_get_softc(sc->bnx_miibus); 4384 4385 mii_pollstat(mii); 4386 4387 if (!sc->bnx_link && 4388 (mii->mii_media_status & IFM_ACTIVE) && 4389 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4390 sc->bnx_link++; 4391 if (bootverbose) 4392 if_printf(ifp, "link UP\n"); 4393 } else if (sc->bnx_link && 4394 (!(mii->mii_media_status & IFM_ACTIVE) || 4395 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4396 sc->bnx_link = 0; 4397 if (bootverbose) 4398 if_printf(ifp, "link DOWN\n"); 4399 } 4400 4401 /* Clear the attention. */ 4402 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4403 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4404 BGE_MACSTAT_LINK_CHANGED); 4405 } 4406 4407 static int 4408 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS) 4409 { 4410 struct bnx_softc *sc = arg1; 4411 4412 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4413 &sc->bnx_rx_coal_ticks, 4414 BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX, 4415 BNX_RX_COAL_TICKS_CHG); 4416 } 4417 4418 static int 4419 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS) 4420 { 4421 struct bnx_softc *sc = arg1; 4422 4423 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4424 &sc->bnx_tx_coal_ticks, 4425 BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX, 4426 BNX_TX_COAL_TICKS_CHG); 4427 } 4428 4429 static int 4430 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS) 4431 { 4432 struct bnx_softc *sc = arg1; 4433 4434 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4435 &sc->bnx_rx_coal_bds, 4436 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX, 4437 BNX_RX_COAL_BDS_CHG); 4438 } 4439 4440 static int 4441 bnx_sysctl_rx_coal_bds_poll(SYSCTL_HANDLER_ARGS) 4442 { 4443 struct bnx_softc *sc = arg1; 4444 4445 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4446 &sc->bnx_rx_coal_bds_poll, 4447 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX, 4448 BNX_RX_COAL_BDS_CHG); 4449 } 4450 4451 static int 4452 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS) 4453 { 4454 struct bnx_softc *sc = arg1; 4455 4456 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4457 &sc->bnx_tx_coal_bds, 4458 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX, 4459 BNX_TX_COAL_BDS_CHG); 4460 } 4461 4462 static int 4463 bnx_sysctl_tx_coal_bds_poll(SYSCTL_HANDLER_ARGS) 4464 { 4465 struct bnx_softc *sc = arg1; 4466 4467 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4468 &sc->bnx_tx_coal_bds_poll, 4469 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX, 4470 BNX_TX_COAL_BDS_CHG); 4471 } 4472 4473 static int 4474 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4475 { 4476 struct bnx_softc *sc = arg1; 4477 4478 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4479 &sc->bnx_rx_coal_bds_int, 4480 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX, 4481 BNX_RX_COAL_BDS_INT_CHG); 4482 } 4483 4484 static int 4485 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4486 { 4487 struct bnx_softc *sc = arg1; 4488 4489 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4490 &sc->bnx_tx_coal_bds_int, 4491 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX, 4492 BNX_TX_COAL_BDS_INT_CHG); 4493 } 4494 4495 static int 4496 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal, 4497 int coal_min, int coal_max, uint32_t coal_chg_mask) 4498 { 4499 struct bnx_softc *sc = arg1; 4500 struct ifnet *ifp = &sc->arpcom.ac_if; 4501 int error = 0, v; 4502 4503 ifnet_serialize_all(ifp); 4504 4505 v = *coal; 4506 error = sysctl_handle_int(oidp, &v, 0, req); 4507 if (!error && req->newptr != NULL) { 4508 if (v < coal_min || v > coal_max) { 4509 error = EINVAL; 4510 } else { 4511 *coal = v; 4512 sc->bnx_coal_chg |= coal_chg_mask; 4513 4514 /* Commit changes */ 4515 bnx_coal_change(sc); 4516 } 4517 } 4518 4519 ifnet_deserialize_all(ifp); 4520 return error; 4521 } 4522 4523 static void 4524 bnx_coal_change(struct bnx_softc *sc) 4525 { 4526 struct ifnet *ifp = &sc->arpcom.ac_if; 4527 int i; 4528 4529 ASSERT_IFNET_SERIALIZED_ALL(ifp); 4530 4531 if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) { 4532 if (sc->bnx_rx_retcnt == 1) { 4533 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 4534 sc->bnx_rx_coal_ticks); 4535 i = 0; 4536 } else { 4537 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 0); 4538 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 4539 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS + 4540 (i * BGE_VEC_COALSET_SIZE), 4541 sc->bnx_rx_coal_ticks); 4542 } 4543 } 4544 for (; i < BNX_INTR_MAX - 1; ++i) { 4545 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS + 4546 (i * BGE_VEC_COALSET_SIZE), 0); 4547 } 4548 if (bootverbose) { 4549 if_printf(ifp, "rx_coal_ticks -> %u\n", 4550 sc->bnx_rx_coal_ticks); 4551 } 4552 } 4553 4554 if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) { 4555 if (sc->bnx_tx_ringcnt == 1) { 4556 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 4557 sc->bnx_tx_coal_ticks); 4558 i = 0; 4559 } else { 4560 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 0); 4561 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 4562 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS + 4563 (i * BGE_VEC_COALSET_SIZE), 4564 sc->bnx_tx_coal_ticks); 4565 } 4566 } 4567 for (; i < BNX_INTR_MAX - 1; ++i) { 4568 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS + 4569 (i * BGE_VEC_COALSET_SIZE), 0); 4570 } 4571 if (bootverbose) { 4572 if_printf(ifp, "tx_coal_ticks -> %u\n", 4573 sc->bnx_tx_coal_ticks); 4574 } 4575 } 4576 4577 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) { 4578 uint32_t rx_coal_bds; 4579 4580 if (ifp->if_flags & IFF_NPOLLING) 4581 rx_coal_bds = sc->bnx_rx_coal_bds_poll; 4582 else 4583 rx_coal_bds = sc->bnx_rx_coal_bds; 4584 4585 if (sc->bnx_rx_retcnt == 1) { 4586 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_coal_bds); 4587 i = 0; 4588 } else { 4589 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 0); 4590 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 4591 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS + 4592 (i * BGE_VEC_COALSET_SIZE), rx_coal_bds); 4593 } 4594 } 4595 for (; i < BNX_INTR_MAX - 1; ++i) { 4596 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS + 4597 (i * BGE_VEC_COALSET_SIZE), 0); 4598 } 4599 if (bootverbose) { 4600 if_printf(ifp, "%srx_coal_bds -> %u\n", 4601 (ifp->if_flags & IFF_NPOLLING) ? "polling " : "", 4602 rx_coal_bds); 4603 } 4604 } 4605 4606 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) { 4607 uint32_t tx_coal_bds; 4608 4609 if (ifp->if_flags & IFF_NPOLLING) 4610 tx_coal_bds = sc->bnx_tx_coal_bds_poll; 4611 else 4612 tx_coal_bds = sc->bnx_tx_coal_bds; 4613 4614 if (sc->bnx_tx_ringcnt == 1) { 4615 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, tx_coal_bds); 4616 i = 0; 4617 } else { 4618 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 0); 4619 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 4620 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS + 4621 (i * BGE_VEC_COALSET_SIZE), tx_coal_bds); 4622 } 4623 } 4624 for (; i < BNX_INTR_MAX - 1; ++i) { 4625 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS + 4626 (i * BGE_VEC_COALSET_SIZE), 0); 4627 } 4628 if (bootverbose) { 4629 if_printf(ifp, "%stx_coal_bds -> %u\n", 4630 (ifp->if_flags & IFF_NPOLLING) ? "polling " : "", 4631 tx_coal_bds); 4632 } 4633 } 4634 4635 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) { 4636 if (sc->bnx_rx_retcnt == 1) { 4637 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 4638 sc->bnx_rx_coal_bds_int); 4639 i = 0; 4640 } else { 4641 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 4642 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 4643 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT + 4644 (i * BGE_VEC_COALSET_SIZE), 4645 sc->bnx_rx_coal_bds_int); 4646 } 4647 } 4648 for (; i < BNX_INTR_MAX - 1; ++i) { 4649 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT + 4650 (i * BGE_VEC_COALSET_SIZE), 0); 4651 } 4652 if (bootverbose) { 4653 if_printf(ifp, "rx_coal_bds_int -> %u\n", 4654 sc->bnx_rx_coal_bds_int); 4655 } 4656 } 4657 4658 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) { 4659 if (sc->bnx_tx_ringcnt == 1) { 4660 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 4661 sc->bnx_tx_coal_bds_int); 4662 i = 0; 4663 } else { 4664 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 4665 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 4666 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT + 4667 (i * BGE_VEC_COALSET_SIZE), 4668 sc->bnx_tx_coal_bds_int); 4669 } 4670 } 4671 for (; i < BNX_INTR_MAX - 1; ++i) { 4672 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT + 4673 (i * BGE_VEC_COALSET_SIZE), 0); 4674 } 4675 if (bootverbose) { 4676 if_printf(ifp, "tx_coal_bds_int -> %u\n", 4677 sc->bnx_tx_coal_bds_int); 4678 } 4679 } 4680 4681 sc->bnx_coal_chg = 0; 4682 } 4683 4684 static void 4685 bnx_check_intr_rxtx(void *xintr) 4686 { 4687 struct bnx_intr_data *intr = xintr; 4688 struct bnx_rx_ret_ring *ret; 4689 struct bnx_tx_ring *txr; 4690 struct ifnet *ifp; 4691 4692 lwkt_serialize_enter(intr->bnx_intr_serialize); 4693 4694 KKASSERT(mycpuid == intr->bnx_intr_cpuid); 4695 4696 ifp = &intr->bnx_sc->arpcom.ac_if; 4697 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) { 4698 lwkt_serialize_exit(intr->bnx_intr_serialize); 4699 return; 4700 } 4701 4702 txr = intr->bnx_txr; 4703 ret = intr->bnx_ret; 4704 4705 if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx || 4706 *txr->bnx_tx_considx != txr->bnx_tx_saved_considx) { 4707 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx && 4708 intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) { 4709 if (!intr->bnx_intr_maylose) { 4710 intr->bnx_intr_maylose = TRUE; 4711 goto done; 4712 } 4713 if (bootverbose) 4714 if_printf(ifp, "lost interrupt\n"); 4715 intr->bnx_intr_func(intr->bnx_intr_arg); 4716 } 4717 } 4718 intr->bnx_intr_maylose = FALSE; 4719 intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx; 4720 intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx; 4721 4722 done: 4723 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL, 4724 intr->bnx_intr_check, intr); 4725 lwkt_serialize_exit(intr->bnx_intr_serialize); 4726 } 4727 4728 static void 4729 bnx_check_intr_tx(void *xintr) 4730 { 4731 struct bnx_intr_data *intr = xintr; 4732 struct bnx_tx_ring *txr; 4733 struct ifnet *ifp; 4734 4735 lwkt_serialize_enter(intr->bnx_intr_serialize); 4736 4737 KKASSERT(mycpuid == intr->bnx_intr_cpuid); 4738 4739 ifp = &intr->bnx_sc->arpcom.ac_if; 4740 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) { 4741 lwkt_serialize_exit(intr->bnx_intr_serialize); 4742 return; 4743 } 4744 4745 txr = intr->bnx_txr; 4746 4747 if (*txr->bnx_tx_considx != txr->bnx_tx_saved_considx) { 4748 if (intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) { 4749 if (!intr->bnx_intr_maylose) { 4750 intr->bnx_intr_maylose = TRUE; 4751 goto done; 4752 } 4753 if (bootverbose) 4754 if_printf(ifp, "lost interrupt\n"); 4755 intr->bnx_intr_func(intr->bnx_intr_arg); 4756 } 4757 } 4758 intr->bnx_intr_maylose = FALSE; 4759 intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx; 4760 4761 done: 4762 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL, 4763 intr->bnx_intr_check, intr); 4764 lwkt_serialize_exit(intr->bnx_intr_serialize); 4765 } 4766 4767 static void 4768 bnx_check_intr_rx(void *xintr) 4769 { 4770 struct bnx_intr_data *intr = xintr; 4771 struct bnx_rx_ret_ring *ret; 4772 struct ifnet *ifp; 4773 4774 lwkt_serialize_enter(intr->bnx_intr_serialize); 4775 4776 KKASSERT(mycpuid == intr->bnx_intr_cpuid); 4777 4778 ifp = &intr->bnx_sc->arpcom.ac_if; 4779 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) { 4780 lwkt_serialize_exit(intr->bnx_intr_serialize); 4781 return; 4782 } 4783 4784 ret = intr->bnx_ret; 4785 4786 if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx) { 4787 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx) { 4788 if (!intr->bnx_intr_maylose) { 4789 intr->bnx_intr_maylose = TRUE; 4790 goto done; 4791 } 4792 if (bootverbose) 4793 if_printf(ifp, "lost interrupt\n"); 4794 intr->bnx_intr_func(intr->bnx_intr_arg); 4795 } 4796 } 4797 intr->bnx_intr_maylose = FALSE; 4798 intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx; 4799 4800 done: 4801 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL, 4802 intr->bnx_intr_check, intr); 4803 lwkt_serialize_exit(intr->bnx_intr_serialize); 4804 } 4805 4806 static void 4807 bnx_enable_intr(struct bnx_softc *sc) 4808 { 4809 struct ifnet *ifp = &sc->arpcom.ac_if; 4810 int i; 4811 4812 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4813 lwkt_serialize_handler_enable( 4814 sc->bnx_intr_data[i].bnx_intr_serialize); 4815 } 4816 4817 /* 4818 * Enable interrupt. 4819 */ 4820 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4821 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4822 4823 bnx_writembx(sc, intr->bnx_intr_mbx, 4824 (*intr->bnx_saved_status_tag) << 24); 4825 /* XXX Linux driver */ 4826 bnx_writembx(sc, intr->bnx_intr_mbx, 4827 (*intr->bnx_saved_status_tag) << 24); 4828 } 4829 4830 /* 4831 * Unmask the interrupt when we stop polling. 4832 */ 4833 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, 4834 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4835 4836 /* 4837 * Trigger another interrupt, since above writing 4838 * to interrupt mailbox0 may acknowledge pending 4839 * interrupt. 4840 */ 4841 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4842 4843 if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) { 4844 if (bootverbose) 4845 if_printf(ifp, "status tag bug workaround\n"); 4846 4847 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4848 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4849 4850 if (intr->bnx_intr_check == NULL) 4851 continue; 4852 intr->bnx_intr_maylose = FALSE; 4853 intr->bnx_rx_check_considx = 0; 4854 intr->bnx_tx_check_considx = 0; 4855 callout_reset_bycpu(&intr->bnx_intr_timer, 4856 BNX_INTR_CKINTVL, intr->bnx_intr_check, intr, 4857 intr->bnx_intr_cpuid); 4858 } 4859 } 4860 } 4861 4862 static void 4863 bnx_disable_intr(struct bnx_softc *sc) 4864 { 4865 int i; 4866 4867 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4868 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4869 4870 callout_stop(&intr->bnx_intr_timer); 4871 intr->bnx_intr_maylose = FALSE; 4872 intr->bnx_rx_check_considx = 0; 4873 intr->bnx_tx_check_considx = 0; 4874 } 4875 4876 /* 4877 * Mask the interrupt when we start polling. 4878 */ 4879 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, 4880 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4881 4882 /* 4883 * Acknowledge possible asserted interrupt. 4884 */ 4885 for (i = 0; i < BNX_INTR_MAX; ++i) 4886 bnx_writembx(sc, sc->bnx_intr_data[i].bnx_intr_mbx, 1); 4887 4888 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4889 lwkt_serialize_handler_disable( 4890 sc->bnx_intr_data[i].bnx_intr_serialize); 4891 } 4892 } 4893 4894 static int 4895 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[]) 4896 { 4897 uint32_t mac_addr; 4898 int ret = 1; 4899 4900 mac_addr = bnx_readmem_ind(sc, 0x0c14); 4901 if ((mac_addr >> 16) == 0x484b) { 4902 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4903 ether_addr[1] = (uint8_t)mac_addr; 4904 mac_addr = bnx_readmem_ind(sc, 0x0c18); 4905 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4906 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4907 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4908 ether_addr[5] = (uint8_t)mac_addr; 4909 ret = 0; 4910 } 4911 return ret; 4912 } 4913 4914 static int 4915 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[]) 4916 { 4917 int mac_offset = BGE_EE_MAC_OFFSET; 4918 4919 if (BNX_IS_5717_PLUS(sc)) { 4920 int f; 4921 4922 f = pci_get_function(sc->bnx_dev); 4923 if (f & 1) 4924 mac_offset = BGE_EE_MAC_OFFSET_5717; 4925 if (f > 1) 4926 mac_offset += BGE_EE_MAC_OFFSET_5717_OFF; 4927 } 4928 4929 return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN); 4930 } 4931 4932 static int 4933 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[]) 4934 { 4935 if (sc->bnx_flags & BNX_FLAG_NO_EEPROM) 4936 return 1; 4937 4938 return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4939 ETHER_ADDR_LEN); 4940 } 4941 4942 static int 4943 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[]) 4944 { 4945 static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = { 4946 /* NOTE: Order is critical */ 4947 bnx_get_eaddr_mem, 4948 bnx_get_eaddr_nvram, 4949 bnx_get_eaddr_eeprom, 4950 NULL 4951 }; 4952 const bnx_eaddr_fcn_t *func; 4953 4954 for (func = bnx_eaddr_funcs; *func != NULL; ++func) { 4955 if ((*func)(sc, eaddr) == 0) 4956 break; 4957 } 4958 return (*func == NULL ? ENXIO : 0); 4959 } 4960 4961 /* 4962 * NOTE: 'm' is not freed upon failure 4963 */ 4964 static struct mbuf * 4965 bnx_defrag_shortdma(struct mbuf *m) 4966 { 4967 struct mbuf *n; 4968 int found; 4969 4970 /* 4971 * If device receive two back-to-back send BDs with less than 4972 * or equal to 8 total bytes then the device may hang. The two 4973 * back-to-back send BDs must in the same frame for this failure 4974 * to occur. Scan mbuf chains and see whether two back-to-back 4975 * send BDs are there. If this is the case, allocate new mbuf 4976 * and copy the frame to workaround the silicon bug. 4977 */ 4978 for (n = m, found = 0; n != NULL; n = n->m_next) { 4979 if (n->m_len < 8) { 4980 found++; 4981 if (found > 1) 4982 break; 4983 continue; 4984 } 4985 found = 0; 4986 } 4987 4988 if (found > 1) 4989 n = m_defrag(m, M_NOWAIT); 4990 else 4991 n = m; 4992 return n; 4993 } 4994 4995 static void 4996 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit) 4997 { 4998 int i; 4999 5000 BNX_CLRBIT(sc, reg, bit); 5001 for (i = 0; i < BNX_TIMEOUT; i++) { 5002 if ((CSR_READ_4(sc, reg) & bit) == 0) 5003 return; 5004 DELAY(100); 5005 } 5006 } 5007 5008 static void 5009 bnx_link_poll(struct bnx_softc *sc) 5010 { 5011 uint32_t status; 5012 5013 status = CSR_READ_4(sc, BGE_MAC_STS); 5014 if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) { 5015 sc->bnx_link_evt = 0; 5016 sc->bnx_link_upd(sc, status); 5017 } 5018 } 5019 5020 static void 5021 bnx_enable_msi(struct bnx_softc *sc, boolean_t is_msix) 5022 { 5023 uint32_t msi_mode; 5024 5025 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE); 5026 msi_mode |= BGE_MSIMODE_ENABLE; 5027 /* 5028 * NOTE: 5029 * 5718-PG105-R says that "one shot" mode does not work 5030 * if MSI is used, however, it obviously works. 5031 */ 5032 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE; 5033 if (is_msix) 5034 msi_mode |= BGE_MSIMODE_MSIX_MULTIMODE; 5035 else 5036 msi_mode &= ~BGE_MSIMODE_MSIX_MULTIMODE; 5037 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode); 5038 } 5039 5040 static uint32_t 5041 bnx_dma_swap_options(struct bnx_softc *sc) 5042 { 5043 uint32_t dma_options; 5044 5045 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 5046 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 5047 #if BYTE_ORDER == BIG_ENDIAN 5048 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 5049 #endif 5050 return dma_options; 5051 } 5052 5053 static int 5054 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp, 5055 uint16_t *mss0, uint16_t *flags0) 5056 { 5057 struct mbuf *m; 5058 struct ip *ip; 5059 struct tcphdr *th; 5060 int thoff, iphlen, hoff, hlen; 5061 uint16_t flags, mss; 5062 5063 m = *mp; 5064 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 5065 5066 hoff = m->m_pkthdr.csum_lhlen; 5067 iphlen = m->m_pkthdr.csum_iphlen; 5068 thoff = m->m_pkthdr.csum_thlen; 5069 5070 KASSERT(hoff > 0, ("invalid ether header len")); 5071 KASSERT(iphlen > 0, ("invalid ip header len")); 5072 KASSERT(thoff > 0, ("invalid tcp header len")); 5073 5074 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 5075 m = m_pullup(m, hoff + iphlen + thoff); 5076 if (m == NULL) { 5077 *mp = NULL; 5078 return ENOBUFS; 5079 } 5080 *mp = m; 5081 } 5082 ip = mtodoff(m, struct ip *, hoff); 5083 th = mtodoff(m, struct tcphdr *, hoff + iphlen); 5084 5085 mss = m->m_pkthdr.tso_segsz; 5086 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA; 5087 5088 ip->ip_len = htons(mss + iphlen + thoff); 5089 th->th_sum = 0; 5090 5091 hlen = (iphlen + thoff) >> 2; 5092 mss |= ((hlen & 0x3) << 14); 5093 flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2); 5094 5095 *mss0 = mss; 5096 *flags0 = flags; 5097 5098 return 0; 5099 } 5100 5101 static int 5102 bnx_create_tx_ring(struct bnx_tx_ring *txr) 5103 { 5104 bus_size_t txmaxsz, txmaxsegsz; 5105 int i, error; 5106 5107 lwkt_serialize_init(&txr->bnx_tx_serialize); 5108 5109 /* 5110 * Create DMA tag and maps for TX mbufs. 5111 */ 5112 if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO) 5113 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header); 5114 else 5115 txmaxsz = BNX_JUMBO_FRAMELEN; 5116 if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766) 5117 txmaxsegsz = MCLBYTES; 5118 else 5119 txmaxsegsz = PAGE_SIZE; 5120 error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag, 5121 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 5122 txmaxsz, BNX_NSEG_NEW, txmaxsegsz, 5123 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 5124 &txr->bnx_tx_mtag); 5125 if (error) { 5126 device_printf(txr->bnx_sc->bnx_dev, 5127 "could not create TX mbuf DMA tag\n"); 5128 return error; 5129 } 5130 5131 for (i = 0; i < BGE_TX_RING_CNT; i++) { 5132 error = bus_dmamap_create(txr->bnx_tx_mtag, 5133 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 5134 &txr->bnx_tx_buf[i].bnx_tx_dmamap); 5135 if (error) { 5136 int j; 5137 5138 for (j = 0; j < i; ++j) { 5139 bus_dmamap_destroy(txr->bnx_tx_mtag, 5140 txr->bnx_tx_buf[j].bnx_tx_dmamap); 5141 } 5142 bus_dma_tag_destroy(txr->bnx_tx_mtag); 5143 txr->bnx_tx_mtag = NULL; 5144 5145 device_printf(txr->bnx_sc->bnx_dev, 5146 "could not create TX mbuf DMA map\n"); 5147 return error; 5148 } 5149 } 5150 5151 /* 5152 * Create DMA stuffs for TX ring. 5153 */ 5154 error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ, 5155 &txr->bnx_tx_ring_tag, 5156 &txr->bnx_tx_ring_map, 5157 (void *)&txr->bnx_tx_ring, 5158 &txr->bnx_tx_ring_paddr); 5159 if (error) { 5160 device_printf(txr->bnx_sc->bnx_dev, 5161 "could not create TX ring\n"); 5162 return error; 5163 } 5164 5165 txr->bnx_tx_flags |= BNX_TX_FLAG_SHORTDMA; 5166 txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS; 5167 5168 return 0; 5169 } 5170 5171 static void 5172 bnx_destroy_tx_ring(struct bnx_tx_ring *txr) 5173 { 5174 /* Destroy TX mbuf DMA stuffs. */ 5175 if (txr->bnx_tx_mtag != NULL) { 5176 int i; 5177 5178 for (i = 0; i < BGE_TX_RING_CNT; i++) { 5179 KKASSERT(txr->bnx_tx_buf[i].bnx_tx_mbuf == NULL); 5180 bus_dmamap_destroy(txr->bnx_tx_mtag, 5181 txr->bnx_tx_buf[i].bnx_tx_dmamap); 5182 } 5183 bus_dma_tag_destroy(txr->bnx_tx_mtag); 5184 } 5185 5186 /* Destroy TX ring */ 5187 bnx_dma_block_free(txr->bnx_tx_ring_tag, 5188 txr->bnx_tx_ring_map, txr->bnx_tx_ring); 5189 } 5190 5191 static int 5192 bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS) 5193 { 5194 struct bnx_softc *sc = (void *)arg1; 5195 struct ifnet *ifp = &sc->arpcom.ac_if; 5196 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; 5197 int error, defrag, i; 5198 5199 if (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) 5200 defrag = 1; 5201 else 5202 defrag = 0; 5203 5204 error = sysctl_handle_int(oidp, &defrag, 0, req); 5205 if (error || req->newptr == NULL) 5206 return error; 5207 5208 ifnet_serialize_all(ifp); 5209 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 5210 txr = &sc->bnx_tx_ring[i]; 5211 if (defrag) 5212 txr->bnx_tx_flags |= BNX_TX_FLAG_FORCE_DEFRAG; 5213 else 5214 txr->bnx_tx_flags &= ~BNX_TX_FLAG_FORCE_DEFRAG; 5215 } 5216 ifnet_deserialize_all(ifp); 5217 5218 return 0; 5219 } 5220 5221 static int 5222 bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS) 5223 { 5224 struct bnx_softc *sc = (void *)arg1; 5225 struct ifnet *ifp = &sc->arpcom.ac_if; 5226 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; 5227 int error, tx_wreg, i; 5228 5229 tx_wreg = txr->bnx_tx_wreg; 5230 error = sysctl_handle_int(oidp, &tx_wreg, 0, req); 5231 if (error || req->newptr == NULL) 5232 return error; 5233 5234 ifnet_serialize_all(ifp); 5235 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 5236 sc->bnx_tx_ring[i].bnx_tx_wreg = tx_wreg; 5237 ifnet_deserialize_all(ifp); 5238 5239 return 0; 5240 } 5241 5242 static int 5243 bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *ret) 5244 { 5245 int error; 5246 5247 lwkt_serialize_init(&ret->bnx_rx_ret_serialize); 5248 5249 /* 5250 * Create DMA stuffs for RX return ring. 5251 */ 5252 error = bnx_dma_block_alloc(ret->bnx_sc, 5253 BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT), 5254 &ret->bnx_rx_ret_ring_tag, 5255 &ret->bnx_rx_ret_ring_map, 5256 (void *)&ret->bnx_rx_ret_ring, 5257 &ret->bnx_rx_ret_ring_paddr); 5258 if (error) { 5259 device_printf(ret->bnx_sc->bnx_dev, 5260 "could not create RX ret ring\n"); 5261 return error; 5262 } 5263 5264 /* Shadow standard ring's RX mbuf DMA tag */ 5265 ret->bnx_rx_mtag = ret->bnx_std->bnx_rx_mtag; 5266 5267 /* 5268 * Create tmp DMA map for RX mbufs. 5269 */ 5270 error = bus_dmamap_create(ret->bnx_rx_mtag, BUS_DMA_WAITOK, 5271 &ret->bnx_rx_tmpmap); 5272 if (error) { 5273 device_printf(ret->bnx_sc->bnx_dev, 5274 "could not create tmp RX mbuf DMA map\n"); 5275 ret->bnx_rx_mtag = NULL; 5276 return error; 5277 } 5278 return 0; 5279 } 5280 5281 static void 5282 bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *ret) 5283 { 5284 /* Destroy tmp RX mbuf DMA map */ 5285 if (ret->bnx_rx_mtag != NULL) 5286 bus_dmamap_destroy(ret->bnx_rx_mtag, ret->bnx_rx_tmpmap); 5287 5288 /* Destroy RX return ring */ 5289 bnx_dma_block_free(ret->bnx_rx_ret_ring_tag, 5290 ret->bnx_rx_ret_ring_map, ret->bnx_rx_ret_ring); 5291 } 5292 5293 static int 5294 bnx_alloc_intr(struct bnx_softc *sc) 5295 { 5296 struct bnx_intr_data *intr; 5297 u_int intr_flags; 5298 int error; 5299 5300 if (sc->bnx_intr_cnt > 1) { 5301 error = bnx_alloc_msix(sc); 5302 if (error) 5303 return error; 5304 KKASSERT(sc->bnx_intr_type == PCI_INTR_TYPE_MSIX); 5305 return 0; 5306 } 5307 5308 KKASSERT(sc->bnx_intr_cnt == 1); 5309 5310 intr = &sc->bnx_intr_data[0]; 5311 intr->bnx_ret = &sc->bnx_rx_ret_ring[0]; 5312 intr->bnx_txr = &sc->bnx_tx_ring[0]; 5313 intr->bnx_intr_serialize = &sc->bnx_main_serialize; 5314 intr->bnx_intr_check = bnx_check_intr_rxtx; 5315 intr->bnx_saved_status_tag = &intr->bnx_ret->bnx_saved_status_tag; 5316 5317 sc->bnx_intr_type = pci_alloc_1intr(sc->bnx_dev, bnx_msi_enable, 5318 &intr->bnx_intr_rid, &intr_flags); 5319 5320 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, SYS_RES_IRQ, 5321 &intr->bnx_intr_rid, intr_flags); 5322 if (intr->bnx_intr_res == NULL) { 5323 device_printf(sc->bnx_dev, "could not alloc interrupt\n"); 5324 return ENXIO; 5325 } 5326 5327 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) { 5328 bnx_enable_msi(sc, FALSE); 5329 intr->bnx_intr_func = bnx_msi; 5330 if (bootverbose) 5331 device_printf(sc->bnx_dev, "oneshot MSI\n"); 5332 } else { 5333 intr->bnx_intr_func = bnx_intr_legacy; 5334 } 5335 intr->bnx_intr_arg = sc; 5336 intr->bnx_intr_cpuid = rman_get_cpuid(intr->bnx_intr_res); 5337 5338 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid; 5339 5340 return 0; 5341 } 5342 5343 static int 5344 bnx_setup_intr(struct bnx_softc *sc) 5345 { 5346 int error, i; 5347 5348 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 5349 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 5350 5351 error = bus_setup_intr_descr(sc->bnx_dev, intr->bnx_intr_res, 5352 INTR_MPSAFE, intr->bnx_intr_func, intr->bnx_intr_arg, 5353 &intr->bnx_intr_hand, intr->bnx_intr_serialize, 5354 intr->bnx_intr_desc); 5355 if (error) { 5356 device_printf(sc->bnx_dev, 5357 "could not set up %dth intr\n", i); 5358 bnx_teardown_intr(sc, i); 5359 return error; 5360 } 5361 } 5362 return 0; 5363 } 5364 5365 static void 5366 bnx_teardown_intr(struct bnx_softc *sc, int cnt) 5367 { 5368 int i; 5369 5370 for (i = 0; i < cnt; ++i) { 5371 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 5372 5373 bus_teardown_intr(sc->bnx_dev, intr->bnx_intr_res, 5374 intr->bnx_intr_hand); 5375 } 5376 } 5377 5378 static void 5379 bnx_free_intr(struct bnx_softc *sc) 5380 { 5381 if (sc->bnx_intr_type != PCI_INTR_TYPE_MSIX) { 5382 struct bnx_intr_data *intr; 5383 5384 KKASSERT(sc->bnx_intr_cnt <= 1); 5385 intr = &sc->bnx_intr_data[0]; 5386 5387 if (intr->bnx_intr_res != NULL) { 5388 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ, 5389 intr->bnx_intr_rid, intr->bnx_intr_res); 5390 } 5391 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) 5392 pci_release_msi(sc->bnx_dev); 5393 } else { 5394 bnx_free_msix(sc, TRUE); 5395 } 5396 } 5397 5398 static void 5399 bnx_setup_serialize(struct bnx_softc *sc) 5400 { 5401 int i, j; 5402 5403 /* 5404 * Allocate serializer array 5405 */ 5406 5407 /* Main + RX STD + TX + RX RET */ 5408 sc->bnx_serialize_cnt = 1 + 1 + sc->bnx_tx_ringcnt + sc->bnx_rx_retcnt; 5409 5410 sc->bnx_serialize = 5411 kmalloc(sc->bnx_serialize_cnt * sizeof(struct lwkt_serialize *), 5412 M_DEVBUF, M_WAITOK | M_ZERO); 5413 5414 /* 5415 * Setup serializers 5416 * 5417 * NOTE: Order is critical 5418 */ 5419 5420 i = 0; 5421 5422 KKASSERT(i < sc->bnx_serialize_cnt); 5423 sc->bnx_serialize[i++] = &sc->bnx_main_serialize; 5424 5425 KKASSERT(i < sc->bnx_serialize_cnt); 5426 sc->bnx_serialize[i++] = &sc->bnx_rx_std_ring.bnx_rx_std_serialize; 5427 5428 for (j = 0; j < sc->bnx_rx_retcnt; ++j) { 5429 KKASSERT(i < sc->bnx_serialize_cnt); 5430 sc->bnx_serialize[i++] = 5431 &sc->bnx_rx_ret_ring[j].bnx_rx_ret_serialize; 5432 } 5433 5434 for (j = 0; j < sc->bnx_tx_ringcnt; ++j) { 5435 KKASSERT(i < sc->bnx_serialize_cnt); 5436 sc->bnx_serialize[i++] = 5437 &sc->bnx_tx_ring[j].bnx_tx_serialize; 5438 } 5439 5440 KKASSERT(i == sc->bnx_serialize_cnt); 5441 } 5442 5443 static void 5444 bnx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 5445 { 5446 struct bnx_softc *sc = ifp->if_softc; 5447 5448 ifnet_serialize_array_enter(sc->bnx_serialize, 5449 sc->bnx_serialize_cnt, slz); 5450 } 5451 5452 static void 5453 bnx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 5454 { 5455 struct bnx_softc *sc = ifp->if_softc; 5456 5457 ifnet_serialize_array_exit(sc->bnx_serialize, 5458 sc->bnx_serialize_cnt, slz); 5459 } 5460 5461 static int 5462 bnx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 5463 { 5464 struct bnx_softc *sc = ifp->if_softc; 5465 5466 return ifnet_serialize_array_try(sc->bnx_serialize, 5467 sc->bnx_serialize_cnt, slz); 5468 } 5469 5470 #ifdef INVARIANTS 5471 5472 static void 5473 bnx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 5474 boolean_t serialized) 5475 { 5476 struct bnx_softc *sc = ifp->if_softc; 5477 5478 ifnet_serialize_array_assert(sc->bnx_serialize, sc->bnx_serialize_cnt, 5479 slz, serialized); 5480 } 5481 5482 #endif /* INVARIANTS */ 5483 5484 static void 5485 bnx_set_tick_cpuid(struct bnx_softc *sc, boolean_t polling) 5486 { 5487 if (polling) 5488 sc->bnx_tick_cpuid = 0; /* XXX */ 5489 else 5490 sc->bnx_tick_cpuid = sc->bnx_intr_data[0].bnx_intr_cpuid; 5491 } 5492 5493 static void 5494 bnx_rx_std_refill_ithread(void *xstd) 5495 { 5496 struct bnx_rx_std_ring *std = xstd; 5497 struct globaldata *gd = mycpu; 5498 5499 crit_enter_gd(gd); 5500 5501 while (!std->bnx_rx_std_stop) { 5502 if (std->bnx_rx_std_refill) { 5503 lwkt_serialize_handler_call( 5504 &std->bnx_rx_std_serialize, 5505 bnx_rx_std_refill, std, NULL); 5506 } 5507 5508 crit_exit_gd(gd); 5509 crit_enter_gd(gd); 5510 5511 atomic_poll_release_int(&std->bnx_rx_std_running); 5512 cpu_mfence(); 5513 5514 if (!std->bnx_rx_std_refill && !std->bnx_rx_std_stop) { 5515 lwkt_deschedule_self(gd->gd_curthread); 5516 lwkt_switch(); 5517 } 5518 } 5519 5520 crit_exit_gd(gd); 5521 5522 wakeup(std); 5523 5524 lwkt_exit(); 5525 } 5526 5527 static void 5528 bnx_rx_std_refill(void *xstd, void *frame __unused) 5529 { 5530 struct bnx_rx_std_ring *std = xstd; 5531 int cnt, refill_mask; 5532 5533 again: 5534 cnt = 0; 5535 5536 cpu_lfence(); 5537 refill_mask = std->bnx_rx_std_refill; 5538 atomic_clear_int(&std->bnx_rx_std_refill, refill_mask); 5539 5540 while (refill_mask) { 5541 uint16_t check_idx = std->bnx_rx_std; 5542 int ret_idx; 5543 5544 ret_idx = bsfl(refill_mask); 5545 for (;;) { 5546 struct bnx_rx_buf *rb; 5547 int refilled; 5548 5549 BNX_INC(check_idx, BGE_STD_RX_RING_CNT); 5550 rb = &std->bnx_rx_std_buf[check_idx]; 5551 refilled = rb->bnx_rx_refilled; 5552 cpu_lfence(); 5553 if (refilled) { 5554 bnx_setup_rxdesc_std(std, check_idx); 5555 std->bnx_rx_std = check_idx; 5556 ++cnt; 5557 if (cnt >= 8) { 5558 atomic_subtract_int( 5559 &std->bnx_rx_std_used, cnt); 5560 bnx_writembx(std->bnx_sc, 5561 BGE_MBX_RX_STD_PROD_LO, 5562 std->bnx_rx_std); 5563 cnt = 0; 5564 } 5565 } else { 5566 break; 5567 } 5568 } 5569 refill_mask &= ~(1 << ret_idx); 5570 } 5571 5572 if (cnt) { 5573 atomic_subtract_int(&std->bnx_rx_std_used, cnt); 5574 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, 5575 std->bnx_rx_std); 5576 } 5577 5578 if (std->bnx_rx_std_refill) 5579 goto again; 5580 5581 atomic_poll_release_int(&std->bnx_rx_std_running); 5582 cpu_mfence(); 5583 5584 if (std->bnx_rx_std_refill) 5585 goto again; 5586 } 5587 5588 static int 5589 bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS) 5590 { 5591 struct bnx_softc *sc = (void *)arg1; 5592 struct ifnet *ifp = &sc->arpcom.ac_if; 5593 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; 5594 int error, cntmax, i; 5595 5596 cntmax = ret->bnx_rx_cntmax; 5597 error = sysctl_handle_int(oidp, &cntmax, 0, req); 5598 if (error || req->newptr == NULL) 5599 return error; 5600 5601 ifnet_serialize_all(ifp); 5602 5603 if ((cntmax * sc->bnx_rx_retcnt) >= BGE_STD_RX_RING_CNT / 2) { 5604 error = EINVAL; 5605 goto back; 5606 } 5607 5608 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 5609 sc->bnx_rx_ret_ring[i].bnx_rx_cntmax = cntmax; 5610 error = 0; 5611 5612 back: 5613 ifnet_deserialize_all(ifp); 5614 5615 return error; 5616 } 5617 5618 static void 5619 bnx_init_rss(struct bnx_softc *sc) 5620 { 5621 uint8_t key[BGE_RSS_KEYREG_CNT * BGE_RSS_KEYREG_SIZE]; 5622 int i, j, r; 5623 5624 KKASSERT(BNX_RSS_ENABLED(sc)); 5625 5626 /* 5627 * Configure RSS redirect table. 5628 */ 5629 if_ringmap_rdrtable(sc->bnx_rx_rmap, sc->bnx_rdr_table, 5630 BNX_RDRTABLE_SIZE); 5631 r = 0; 5632 for (j = 0; j < BGE_RSS_INDIR_TBL_CNT; ++j) { 5633 uint32_t tbl = 0; 5634 5635 for (i = 0; i < BGE_RSS_INDIR_TBLENT_CNT; ++i) { 5636 uint32_t q; 5637 5638 q = sc->bnx_rdr_table[r]; 5639 tbl |= q << (BGE_RSS_INDIR_TBLENT_SHIFT * 5640 (BGE_RSS_INDIR_TBLENT_CNT - i - 1)); 5641 ++r; 5642 } 5643 5644 BNX_RSS_DPRINTF(sc, 1, "tbl%d %08x\n", j, tbl); 5645 CSR_WRITE_4(sc, BGE_RSS_INDIR_TBL(j), tbl); 5646 } 5647 5648 toeplitz_get_key(key, sizeof(key)); 5649 for (i = 0; i < BGE_RSS_KEYREG_CNT; ++i) { 5650 uint32_t keyreg; 5651 5652 keyreg = BGE_RSS_KEYREG_VAL(key, i); 5653 5654 BNX_RSS_DPRINTF(sc, 1, "key%d %08x\n", i, keyreg); 5655 CSR_WRITE_4(sc, BGE_RSS_KEYREG(i), keyreg); 5656 } 5657 } 5658 5659 static void 5660 bnx_setup_ring_cnt(struct bnx_softc *sc) 5661 { 5662 int msix_enable, msix_cnt, msix_ring, ring_max, ring_cnt; 5663 5664 /* One RX ring. */ 5665 sc->bnx_rx_rmap = if_ringmap_alloc(sc->bnx_dev, 1, 1); 5666 5667 if (netisr_ncpus == 1) 5668 goto skip_rx; 5669 5670 msix_enable = device_getenv_int(sc->bnx_dev, "msix.enable", 5671 bnx_msix_enable); 5672 if (!msix_enable) 5673 goto skip_rx; 5674 5675 /* 5676 * One MSI-X vector is dedicated to status or single TX queue, 5677 * so make sure that there are enough MSI-X vectors. 5678 */ 5679 msix_cnt = pci_msix_count(sc->bnx_dev); 5680 if (msix_cnt <= 1) 5681 goto skip_rx; 5682 if (bootverbose) 5683 device_printf(sc->bnx_dev, "MSI-X count %d\n", msix_cnt); 5684 msix_ring = msix_cnt - 1; 5685 5686 /* 5687 * Setup RX ring count 5688 */ 5689 ring_max = BNX_RX_RING_MAX; 5690 if (ring_max > msix_ring) 5691 ring_max = msix_ring; 5692 ring_cnt = device_getenv_int(sc->bnx_dev, "rx_rings", bnx_rx_rings); 5693 5694 if_ringmap_free(sc->bnx_rx_rmap); 5695 sc->bnx_rx_rmap = if_ringmap_alloc(sc->bnx_dev, ring_cnt, ring_max); 5696 5697 skip_rx: 5698 sc->bnx_rx_retcnt = if_ringmap_count(sc->bnx_rx_rmap); 5699 5700 /* 5701 * Setup TX ring count 5702 * 5703 * Currently only BCM5719 and BCM5720 support multiple TX rings 5704 * and the TX ring count must be less than the RX ring count. 5705 */ 5706 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 || 5707 sc->bnx_asicrev == BGE_ASICREV_BCM5720) { 5708 ring_max = BNX_TX_RING_MAX; 5709 if (ring_max > sc->bnx_rx_retcnt) 5710 ring_max = sc->bnx_rx_retcnt; 5711 ring_cnt = device_getenv_int(sc->bnx_dev, "tx_rings", 5712 bnx_tx_rings); 5713 } else { 5714 ring_max = 1; 5715 ring_cnt = 1; 5716 } 5717 sc->bnx_tx_rmap = if_ringmap_alloc(sc->bnx_dev, ring_cnt, ring_max); 5718 if_ringmap_align(sc->bnx_dev, sc->bnx_rx_rmap, sc->bnx_tx_rmap); 5719 5720 sc->bnx_tx_ringcnt = if_ringmap_count(sc->bnx_tx_rmap); 5721 KASSERT(sc->bnx_tx_ringcnt <= sc->bnx_rx_retcnt, 5722 ("invalid TX ring count %d and RX ring count %d", 5723 sc->bnx_tx_ringcnt, sc->bnx_rx_retcnt)); 5724 5725 /* 5726 * Setup interrupt count. 5727 */ 5728 if (sc->bnx_rx_retcnt == 1) { 5729 sc->bnx_intr_cnt = 1; 5730 } else { 5731 /* 5732 * We need one extra MSI-X vector for link status or 5733 * TX ring (if only one TX ring is enabled). 5734 */ 5735 sc->bnx_intr_cnt = sc->bnx_rx_retcnt + 1; 5736 } 5737 KKASSERT(sc->bnx_intr_cnt <= BNX_INTR_MAX); 5738 5739 if (bootverbose) { 5740 device_printf(sc->bnx_dev, "intr count %d, " 5741 "RX ring %d, TX ring %d\n", sc->bnx_intr_cnt, 5742 sc->bnx_rx_retcnt, sc->bnx_tx_ringcnt); 5743 } 5744 } 5745 5746 static int 5747 bnx_alloc_msix(struct bnx_softc *sc) 5748 { 5749 struct bnx_intr_data *intr; 5750 boolean_t setup = FALSE; 5751 int error, i; 5752 5753 KKASSERT(sc->bnx_intr_cnt > 1); 5754 KKASSERT(sc->bnx_intr_cnt == sc->bnx_rx_retcnt + 1); 5755 5756 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) { 5757 /* 5758 * Link status 5759 */ 5760 intr = &sc->bnx_intr_data[0]; 5761 5762 intr->bnx_intr_serialize = &sc->bnx_main_serialize; 5763 intr->bnx_saved_status_tag = &sc->bnx_saved_status_tag; 5764 5765 intr->bnx_intr_func = bnx_msix_status; 5766 intr->bnx_intr_arg = sc; 5767 intr->bnx_intr_cpuid = 0; /* XXX */ 5768 5769 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0), 5770 "%s sts", device_get_nameunit(sc->bnx_dev)); 5771 intr->bnx_intr_desc = intr->bnx_intr_desc0; 5772 5773 /* 5774 * RX/TX rings 5775 */ 5776 for (i = 1; i < sc->bnx_intr_cnt; ++i) { 5777 int idx = i - 1; 5778 5779 intr = &sc->bnx_intr_data[i]; 5780 5781 KKASSERT(idx < sc->bnx_rx_retcnt); 5782 intr->bnx_ret = &sc->bnx_rx_ret_ring[idx]; 5783 if (idx < sc->bnx_tx_ringcnt) { 5784 intr->bnx_txr = &sc->bnx_tx_ring[idx]; 5785 intr->bnx_ret->bnx_txr = intr->bnx_txr; 5786 } 5787 5788 intr->bnx_intr_serialize = 5789 &intr->bnx_ret->bnx_rx_ret_serialize; 5790 intr->bnx_saved_status_tag = 5791 &intr->bnx_ret->bnx_saved_status_tag; 5792 5793 intr->bnx_intr_arg = intr->bnx_ret; 5794 intr->bnx_intr_cpuid = 5795 if_ringmap_cpumap(sc->bnx_rx_rmap, idx); 5796 KKASSERT(intr->bnx_intr_cpuid < netisr_ncpus); 5797 5798 if (intr->bnx_txr == NULL) { 5799 intr->bnx_intr_check = bnx_check_intr_rx; 5800 intr->bnx_intr_func = bnx_msix_rx; 5801 ksnprintf(intr->bnx_intr_desc0, 5802 sizeof(intr->bnx_intr_desc0), "%s rx%d", 5803 device_get_nameunit(sc->bnx_dev), idx); 5804 } else { 5805 #ifdef INVARIANTS 5806 int tx_cpuid; 5807 #endif 5808 5809 intr->bnx_intr_check = bnx_check_intr_rxtx; 5810 intr->bnx_intr_func = bnx_msix_rxtx; 5811 ksnprintf(intr->bnx_intr_desc0, 5812 sizeof(intr->bnx_intr_desc0), "%s rxtx%d", 5813 device_get_nameunit(sc->bnx_dev), idx); 5814 5815 #ifdef INVARIANTS 5816 tx_cpuid = if_ringmap_cpumap(sc->bnx_tx_rmap, 5817 idx); 5818 KASSERT(intr->bnx_intr_cpuid == tx_cpuid, 5819 ("RX intr cpu%d, TX intr cpu%d, mismatch", 5820 intr->bnx_intr_cpuid, tx_cpuid)); 5821 #endif 5822 intr->bnx_txr->bnx_tx_cpuid = 5823 intr->bnx_intr_cpuid; 5824 } 5825 intr->bnx_intr_desc = intr->bnx_intr_desc0; 5826 5827 intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx; 5828 } 5829 } else { 5830 /* 5831 * TX ring0 and link status 5832 */ 5833 intr = &sc->bnx_intr_data[0]; 5834 5835 intr->bnx_txr = &sc->bnx_tx_ring[0]; 5836 intr->bnx_intr_serialize = &sc->bnx_main_serialize; 5837 intr->bnx_intr_check = bnx_check_intr_tx; 5838 intr->bnx_saved_status_tag = 5839 &intr->bnx_txr->bnx_saved_status_tag; 5840 5841 intr->bnx_intr_func = bnx_msix_tx_status; 5842 intr->bnx_intr_arg = intr->bnx_txr; 5843 intr->bnx_intr_cpuid = if_ringmap_cpumap(sc->bnx_tx_rmap, 0); 5844 KKASSERT(intr->bnx_intr_cpuid < netisr_ncpus); 5845 5846 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0), 5847 "%s ststx", device_get_nameunit(sc->bnx_dev)); 5848 intr->bnx_intr_desc = intr->bnx_intr_desc0; 5849 5850 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid; 5851 5852 /* 5853 * RX rings 5854 */ 5855 for (i = 1; i < sc->bnx_intr_cnt; ++i) { 5856 int idx = i - 1; 5857 5858 intr = &sc->bnx_intr_data[i]; 5859 5860 KKASSERT(idx < sc->bnx_rx_retcnt); 5861 intr->bnx_ret = &sc->bnx_rx_ret_ring[idx]; 5862 intr->bnx_intr_serialize = 5863 &intr->bnx_ret->bnx_rx_ret_serialize; 5864 intr->bnx_intr_check = bnx_check_intr_rx; 5865 intr->bnx_saved_status_tag = 5866 &intr->bnx_ret->bnx_saved_status_tag; 5867 5868 intr->bnx_intr_func = bnx_msix_rx; 5869 intr->bnx_intr_arg = intr->bnx_ret; 5870 intr->bnx_intr_cpuid = 5871 if_ringmap_cpumap(sc->bnx_rx_rmap, idx); 5872 KKASSERT(intr->bnx_intr_cpuid < netisr_ncpus); 5873 5874 ksnprintf(intr->bnx_intr_desc0, 5875 sizeof(intr->bnx_intr_desc0), "%s rx%d", 5876 device_get_nameunit(sc->bnx_dev), idx); 5877 intr->bnx_intr_desc = intr->bnx_intr_desc0; 5878 5879 intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx; 5880 } 5881 } 5882 5883 if (BNX_IS_5717_PLUS(sc)) { 5884 sc->bnx_msix_mem_rid = PCIR_BAR(4); 5885 } else { 5886 if (sc->bnx_res2 == NULL) 5887 sc->bnx_msix_mem_rid = PCIR_BAR(2); 5888 } 5889 if (sc->bnx_msix_mem_rid != 0) { 5890 sc->bnx_msix_mem_res = bus_alloc_resource_any(sc->bnx_dev, 5891 SYS_RES_MEMORY, &sc->bnx_msix_mem_rid, RF_ACTIVE); 5892 if (sc->bnx_msix_mem_res == NULL) { 5893 device_printf(sc->bnx_dev, 5894 "could not alloc MSI-X table\n"); 5895 return ENXIO; 5896 } 5897 } 5898 5899 bnx_enable_msi(sc, TRUE); 5900 5901 error = pci_setup_msix(sc->bnx_dev); 5902 if (error) { 5903 device_printf(sc->bnx_dev, "could not setup MSI-X\n"); 5904 goto back; 5905 } 5906 setup = TRUE; 5907 5908 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 5909 intr = &sc->bnx_intr_data[i]; 5910 5911 error = pci_alloc_msix_vector(sc->bnx_dev, i, 5912 &intr->bnx_intr_rid, intr->bnx_intr_cpuid); 5913 if (error) { 5914 device_printf(sc->bnx_dev, 5915 "could not alloc MSI-X %d on cpu%d\n", 5916 i, intr->bnx_intr_cpuid); 5917 goto back; 5918 } 5919 5920 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, 5921 SYS_RES_IRQ, &intr->bnx_intr_rid, RF_ACTIVE); 5922 if (intr->bnx_intr_res == NULL) { 5923 device_printf(sc->bnx_dev, 5924 "could not alloc MSI-X %d resource\n", i); 5925 error = ENXIO; 5926 goto back; 5927 } 5928 } 5929 5930 pci_enable_msix(sc->bnx_dev); 5931 sc->bnx_intr_type = PCI_INTR_TYPE_MSIX; 5932 back: 5933 if (error) 5934 bnx_free_msix(sc, setup); 5935 return error; 5936 } 5937 5938 static void 5939 bnx_free_msix(struct bnx_softc *sc, boolean_t setup) 5940 { 5941 int i; 5942 5943 KKASSERT(sc->bnx_intr_cnt > 1); 5944 5945 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 5946 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 5947 5948 if (intr->bnx_intr_res != NULL) { 5949 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ, 5950 intr->bnx_intr_rid, intr->bnx_intr_res); 5951 } 5952 if (intr->bnx_intr_rid >= 0) { 5953 pci_release_msix_vector(sc->bnx_dev, 5954 intr->bnx_intr_rid); 5955 } 5956 } 5957 if (setup) 5958 pci_teardown_msix(sc->bnx_dev); 5959 } 5960 5961 static void 5962 bnx_rx_std_refill_sched_ipi(void *xret) 5963 { 5964 struct bnx_rx_ret_ring *ret = xret; 5965 struct bnx_rx_std_ring *std = ret->bnx_std; 5966 struct globaldata *gd = mycpu; 5967 5968 crit_enter_gd(gd); 5969 5970 atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask); 5971 cpu_sfence(); 5972 5973 KKASSERT(std->bnx_rx_std_ithread->td_gd == gd); 5974 lwkt_schedule(std->bnx_rx_std_ithread); 5975 5976 crit_exit_gd(gd); 5977 } 5978 5979 static void 5980 bnx_rx_std_refill_stop(void *xstd) 5981 { 5982 struct bnx_rx_std_ring *std = xstd; 5983 struct globaldata *gd = mycpu; 5984 5985 crit_enter_gd(gd); 5986 5987 std->bnx_rx_std_stop = 1; 5988 cpu_sfence(); 5989 5990 KKASSERT(std->bnx_rx_std_ithread->td_gd == gd); 5991 lwkt_schedule(std->bnx_rx_std_ithread); 5992 5993 crit_exit_gd(gd); 5994 } 5995 5996 static void 5997 bnx_serialize_skipmain(struct bnx_softc *sc) 5998 { 5999 lwkt_serialize_array_enter(sc->bnx_serialize, 6000 sc->bnx_serialize_cnt, 1); 6001 } 6002 6003 static void 6004 bnx_deserialize_skipmain(struct bnx_softc *sc) 6005 { 6006 lwkt_serialize_array_exit(sc->bnx_serialize, 6007 sc->bnx_serialize_cnt, 1); 6008 } 6009 6010 static void 6011 bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *ret, 6012 struct bnx_rx_std_ring *std) 6013 { 6014 struct globaldata *gd = mycpu; 6015 6016 ret->bnx_rx_cnt = 0; 6017 cpu_sfence(); 6018 6019 crit_enter_gd(gd); 6020 6021 atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask); 6022 cpu_sfence(); 6023 if (atomic_poll_acquire_int(&std->bnx_rx_std_running)) { 6024 if (std->bnx_rx_std_ithread->td_gd == gd) { 6025 lwkt_schedule(std->bnx_rx_std_ithread); 6026 } else { 6027 lwkt_send_ipiq(std->bnx_rx_std_ithread->td_gd, 6028 bnx_rx_std_refill_sched_ipi, ret); 6029 } 6030 } 6031 6032 crit_exit_gd(gd); 6033 } 6034 6035 static struct pktinfo * 6036 bnx_rss_info(struct pktinfo *pi, const struct bge_rx_bd *cur_rx) 6037 { 6038 /* Don't pick up IPv6 packet */ 6039 if (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) 6040 return NULL; 6041 6042 /* Don't pick up IP packet w/o IP checksum */ 6043 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) == 0 || 6044 (cur_rx->bge_error_flag & BGE_RXERRFLAG_IP_CSUM_NOK)) 6045 return NULL; 6046 6047 /* Don't pick up IP packet w/o TCP/UDP checksum */ 6048 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) == 0) 6049 return NULL; 6050 6051 /* May be IP fragment */ 6052 if (cur_rx->bge_tcp_udp_csum != 0xffff) 6053 return NULL; 6054 6055 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_IS_TCP) 6056 pi->pi_l3proto = IPPROTO_TCP; 6057 else 6058 pi->pi_l3proto = IPPROTO_UDP; 6059 pi->pi_netisr = NETISR_IP; 6060 pi->pi_flags = 0; 6061 6062 return pi; 6063 } 6064 6065 static void 6066 bnx_sig_pre_reset(struct bnx_softc *sc, int type) 6067 { 6068 if (type == BNX_RESET_START || type == BNX_RESET_SUSPEND) 6069 bnx_ape_driver_state_change(sc, type); 6070 } 6071 6072 static void 6073 bnx_sig_post_reset(struct bnx_softc *sc, int type) 6074 { 6075 if (type == BNX_RESET_SHUTDOWN) 6076 bnx_ape_driver_state_change(sc, type); 6077 } 6078 6079 /* 6080 * Clear all stale locks and select the lock for this driver instance. 6081 */ 6082 static void 6083 bnx_ape_lock_init(struct bnx_softc *sc) 6084 { 6085 uint32_t bit, regbase; 6086 int i; 6087 6088 regbase = BGE_APE_PER_LOCK_GRANT; 6089 6090 /* Clear any stale locks. */ 6091 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 6092 switch (i) { 6093 case BGE_APE_LOCK_PHY0: 6094 case BGE_APE_LOCK_PHY1: 6095 case BGE_APE_LOCK_PHY2: 6096 case BGE_APE_LOCK_PHY3: 6097 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6098 break; 6099 6100 default: 6101 if (sc->bnx_func_addr == 0) 6102 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6103 else 6104 bit = 1 << sc->bnx_func_addr; 6105 break; 6106 } 6107 APE_WRITE_4(sc, regbase + 4 * i, bit); 6108 } 6109 6110 /* Select the PHY lock based on the device's function number. */ 6111 switch (sc->bnx_func_addr) { 6112 case 0: 6113 sc->bnx_phy_ape_lock = BGE_APE_LOCK_PHY0; 6114 break; 6115 6116 case 1: 6117 sc->bnx_phy_ape_lock = BGE_APE_LOCK_PHY1; 6118 break; 6119 6120 case 2: 6121 sc->bnx_phy_ape_lock = BGE_APE_LOCK_PHY2; 6122 break; 6123 6124 case 3: 6125 sc->bnx_phy_ape_lock = BGE_APE_LOCK_PHY3; 6126 break; 6127 6128 default: 6129 device_printf(sc->bnx_dev, 6130 "PHY lock not supported on this function\n"); 6131 break; 6132 } 6133 } 6134 6135 /* 6136 * Check for APE firmware, set flags, and print version info. 6137 */ 6138 static void 6139 bnx_ape_read_fw_ver(struct bnx_softc *sc) 6140 { 6141 const char *fwtype; 6142 uint32_t apedata, features; 6143 6144 /* Check for a valid APE signature in shared memory. */ 6145 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 6146 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 6147 device_printf(sc->bnx_dev, "no APE signature\n"); 6148 sc->bnx_mfw_flags &= ~BNX_MFW_ON_APE; 6149 return; 6150 } 6151 6152 /* Check if APE firmware is running. */ 6153 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 6154 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 6155 device_printf(sc->bnx_dev, "APE signature found " 6156 "but FW status not ready! 0x%08x\n", apedata); 6157 return; 6158 } 6159 6160 sc->bnx_mfw_flags |= BNX_MFW_ON_APE; 6161 6162 /* Fetch the APE firwmare type and version. */ 6163 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 6164 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 6165 if (features & BGE_APE_FW_FEATURE_NCSI) { 6166 sc->bnx_mfw_flags |= BNX_MFW_TYPE_NCSI; 6167 fwtype = "NCSI"; 6168 } else if (features & BGE_APE_FW_FEATURE_DASH) { 6169 sc->bnx_mfw_flags |= BNX_MFW_TYPE_DASH; 6170 fwtype = "DASH"; 6171 } else { 6172 fwtype = "UNKN"; 6173 } 6174 6175 /* Print the APE firmware version. */ 6176 device_printf(sc->bnx_dev, "APE FW version: %s v%d.%d.%d.%d\n", 6177 fwtype, 6178 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 6179 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 6180 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 6181 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 6182 } 6183 6184 static int 6185 bnx_ape_lock(struct bnx_softc *sc, int locknum) 6186 { 6187 uint32_t bit, gnt, req, status; 6188 int i, off; 6189 6190 if ((sc->bnx_mfw_flags & BNX_MFW_ON_APE) == 0) 6191 return 0; 6192 6193 /* Lock request/grant registers have different bases. */ 6194 req = BGE_APE_PER_LOCK_REQ; 6195 gnt = BGE_APE_PER_LOCK_GRANT; 6196 6197 off = 4 * locknum; 6198 6199 switch (locknum) { 6200 case BGE_APE_LOCK_GPIO: 6201 /* Lock required when using GPIO. */ 6202 if (sc->bnx_func_addr == 0) 6203 bit = BGE_APE_LOCK_REQ_DRIVER0; 6204 else 6205 bit = 1 << sc->bnx_func_addr; 6206 break; 6207 6208 case BGE_APE_LOCK_GRC: 6209 /* Lock required to reset the device. */ 6210 if (sc->bnx_func_addr == 0) 6211 bit = BGE_APE_LOCK_REQ_DRIVER0; 6212 else 6213 bit = 1 << sc->bnx_func_addr; 6214 break; 6215 6216 case BGE_APE_LOCK_MEM: 6217 /* Lock required when accessing certain APE memory. */ 6218 if (sc->bnx_func_addr == 0) 6219 bit = BGE_APE_LOCK_REQ_DRIVER0; 6220 else 6221 bit = 1 << sc->bnx_func_addr; 6222 break; 6223 6224 case BGE_APE_LOCK_PHY0: 6225 case BGE_APE_LOCK_PHY1: 6226 case BGE_APE_LOCK_PHY2: 6227 case BGE_APE_LOCK_PHY3: 6228 /* Lock required when accessing PHYs. */ 6229 bit = BGE_APE_LOCK_REQ_DRIVER0; 6230 break; 6231 6232 default: 6233 return EINVAL; 6234 } 6235 6236 /* Request a lock. */ 6237 APE_WRITE_4(sc, req + off, bit); 6238 6239 /* Wait up to 1 second to acquire lock. */ 6240 for (i = 0; i < 20000; i++) { 6241 status = APE_READ_4(sc, gnt + off); 6242 if (status == bit) 6243 break; 6244 DELAY(50); 6245 } 6246 6247 /* Handle any errors. */ 6248 if (status != bit) { 6249 if_printf(&sc->arpcom.ac_if, "APE lock %d request failed! " 6250 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 6251 locknum, req + off, bit & 0xFFFF, gnt + off, 6252 status & 0xFFFF); 6253 /* Revoke the lock request. */ 6254 APE_WRITE_4(sc, gnt + off, bit); 6255 return EBUSY; 6256 } 6257 6258 return 0; 6259 } 6260 6261 static void 6262 bnx_ape_unlock(struct bnx_softc *sc, int locknum) 6263 { 6264 uint32_t bit, gnt; 6265 int off; 6266 6267 if ((sc->bnx_mfw_flags & BNX_MFW_ON_APE) == 0) 6268 return; 6269 6270 gnt = BGE_APE_PER_LOCK_GRANT; 6271 6272 off = 4 * locknum; 6273 6274 switch (locknum) { 6275 case BGE_APE_LOCK_GPIO: 6276 if (sc->bnx_func_addr == 0) 6277 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6278 else 6279 bit = 1 << sc->bnx_func_addr; 6280 break; 6281 6282 case BGE_APE_LOCK_GRC: 6283 if (sc->bnx_func_addr == 0) 6284 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6285 else 6286 bit = 1 << sc->bnx_func_addr; 6287 break; 6288 6289 case BGE_APE_LOCK_MEM: 6290 if (sc->bnx_func_addr == 0) 6291 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6292 else 6293 bit = 1 << sc->bnx_func_addr; 6294 break; 6295 6296 case BGE_APE_LOCK_PHY0: 6297 case BGE_APE_LOCK_PHY1: 6298 case BGE_APE_LOCK_PHY2: 6299 case BGE_APE_LOCK_PHY3: 6300 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6301 break; 6302 6303 default: 6304 return; 6305 } 6306 6307 APE_WRITE_4(sc, gnt + off, bit); 6308 } 6309 6310 /* 6311 * Send an event to the APE firmware. 6312 */ 6313 static void 6314 bnx_ape_send_event(struct bnx_softc *sc, uint32_t event) 6315 { 6316 uint32_t apedata; 6317 int i; 6318 6319 /* NCSI does not support APE events. */ 6320 if ((sc->bnx_mfw_flags & BNX_MFW_ON_APE) == 0) 6321 return; 6322 6323 /* Wait up to 1ms for APE to service previous event. */ 6324 for (i = 10; i > 0; i--) { 6325 if (bnx_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 6326 break; 6327 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 6328 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 6329 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 6330 BGE_APE_EVENT_STATUS_EVENT_PENDING); 6331 bnx_ape_unlock(sc, BGE_APE_LOCK_MEM); 6332 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 6333 break; 6334 } 6335 bnx_ape_unlock(sc, BGE_APE_LOCK_MEM); 6336 DELAY(100); 6337 } 6338 if (i == 0) { 6339 if_printf(&sc->arpcom.ac_if, 6340 "APE event 0x%08x send timed out\n", event); 6341 } 6342 } 6343 6344 static void 6345 bnx_ape_driver_state_change(struct bnx_softc *sc, int kind) 6346 { 6347 uint32_t apedata, event; 6348 6349 if ((sc->bnx_mfw_flags & BNX_MFW_ON_APE) == 0) 6350 return; 6351 6352 switch (kind) { 6353 case BNX_RESET_START: 6354 /* If this is the first load, clear the load counter. */ 6355 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 6356 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) { 6357 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 6358 } else { 6359 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 6360 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 6361 } 6362 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 6363 BGE_APE_HOST_SEG_SIG_MAGIC); 6364 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 6365 BGE_APE_HOST_SEG_LEN_MAGIC); 6366 6367 /* Add some version info if bnx(4) supports it. */ 6368 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 6369 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 6370 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 6371 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 6372 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 6373 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 6374 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 6375 BGE_APE_HOST_DRVR_STATE_START); 6376 event = BGE_APE_EVENT_STATUS_STATE_START; 6377 break; 6378 6379 case BNX_RESET_SHUTDOWN: 6380 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 6381 BGE_APE_HOST_DRVR_STATE_UNLOAD); 6382 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 6383 break; 6384 6385 case BNX_RESET_SUSPEND: 6386 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 6387 break; 6388 6389 default: 6390 return; 6391 } 6392 6393 bnx_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 6394 BGE_APE_EVENT_STATUS_STATE_CHNGE); 6395 } 6396