1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $ 34 */ 35 36 #include "opt_bnx.h" 37 #include "opt_ifpoll.h" 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/kernel.h> 43 #include <sys/interrupt.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/rman.h> 48 #include <sys/serialize.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/sysctl.h> 52 53 #include <netinet/ip.h> 54 #include <netinet/tcp.h> 55 56 #include <net/bpf.h> 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_arp.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_poll.h> 63 #include <net/if_types.h> 64 #include <net/ifq_var.h> 65 #include <net/if_ringmap.h> 66 #include <net/toeplitz.h> 67 #include <net/toeplitz2.h> 68 #include <net/vlan/if_vlan_var.h> 69 #include <net/vlan/if_vlan_ether.h> 70 71 #include <dev/netif/mii_layer/mii.h> 72 #include <dev/netif/mii_layer/miivar.h> 73 #include <dev/netif/mii_layer/brgphyreg.h> 74 75 #include "pcidevs.h" 76 #include <bus/pci/pcireg.h> 77 #include <bus/pci/pcivar.h> 78 79 #include <dev/netif/bge/if_bgereg.h> 80 #include <dev/netif/bnx/if_bnxvar.h> 81 82 /* "device miibus" required. See GENERIC if you get errors here. */ 83 #include "miibus_if.h" 84 85 #define BNX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 87 #define BNX_RESET_SHUTDOWN 0 88 #define BNX_RESET_START 1 89 #define BNX_RESET_SUSPEND 2 90 91 #define BNX_INTR_CKINTVL ((10 * hz) / 1000) /* 10ms */ 92 93 #ifdef BNX_RSS_DEBUG 94 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 95 do { \ 96 if (sc->bnx_rss_debug >= lvl) \ 97 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 98 } while (0) 99 #else /* !BNX_RSS_DEBUG */ 100 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 101 #endif /* BNX_RSS_DEBUG */ 102 103 static const struct bnx_type { 104 uint16_t bnx_vid; 105 uint16_t bnx_did; 106 char *bnx_name; 107 } bnx_devs[] = { 108 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717, 109 "Broadcom BCM5717 Gigabit Ethernet" }, 110 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C, 111 "Broadcom BCM5717C Gigabit Ethernet" }, 112 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718, 113 "Broadcom BCM5718 Gigabit Ethernet" }, 114 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719, 115 "Broadcom BCM5719 Gigabit Ethernet" }, 116 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT, 117 "Broadcom BCM5720 Gigabit Ethernet" }, 118 119 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725, 120 "Broadcom BCM5725 Gigabit Ethernet" }, 121 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727, 122 "Broadcom BCM5727 Gigabit Ethernet" }, 123 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762, 124 "Broadcom BCM5762 Gigabit Ethernet" }, 125 126 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761, 127 "Broadcom BCM57761 Gigabit Ethernet" }, 128 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762, 129 "Broadcom BCM57762 Gigabit Ethernet" }, 130 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765, 131 "Broadcom BCM57765 Gigabit Ethernet" }, 132 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766, 133 "Broadcom BCM57766 Gigabit Ethernet" }, 134 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781, 135 "Broadcom BCM57781 Gigabit Ethernet" }, 136 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782, 137 "Broadcom BCM57782 Gigabit Ethernet" }, 138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785, 139 "Broadcom BCM57785 Gigabit Ethernet" }, 140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786, 141 "Broadcom BCM57786 Gigabit Ethernet" }, 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791, 143 "Broadcom BCM57791 Fast Ethernet" }, 144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795, 145 "Broadcom BCM57795 Fast Ethernet" }, 146 147 { 0, 0, NULL } 148 }; 149 150 static const int bnx_tx_mailbox[BNX_TX_RING_MAX] = { 151 BGE_MBX_TX_HOST_PROD0_LO, 152 BGE_MBX_TX_HOST_PROD0_HI, 153 BGE_MBX_TX_HOST_PROD1_LO, 154 BGE_MBX_TX_HOST_PROD1_HI 155 }; 156 157 #define BNX_IS_JUMBO_CAPABLE(sc) ((sc)->bnx_flags & BNX_FLAG_JUMBO) 158 #define BNX_IS_5717_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_5717_PLUS) 159 #define BNX_IS_57765_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_57765_PLUS) 160 #define BNX_IS_57765_FAMILY(sc) \ 161 ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY) 162 163 typedef int (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]); 164 165 static int bnx_probe(device_t); 166 static int bnx_attach(device_t); 167 static int bnx_detach(device_t); 168 static void bnx_shutdown(device_t); 169 static int bnx_suspend(device_t); 170 static int bnx_resume(device_t); 171 static int bnx_miibus_readreg(device_t, int, int); 172 static int bnx_miibus_writereg(device_t, int, int, int); 173 static void bnx_miibus_statchg(device_t); 174 175 static int bnx_handle_status(struct bnx_softc *); 176 #ifdef IFPOLL_ENABLE 177 static void bnx_npoll(struct ifnet *, struct ifpoll_info *); 178 static void bnx_npoll_rx(struct ifnet *, void *, int); 179 static void bnx_npoll_tx(struct ifnet *, void *, int); 180 static void bnx_npoll_tx_notag(struct ifnet *, void *, int); 181 static void bnx_npoll_status(struct ifnet *); 182 static void bnx_npoll_status_notag(struct ifnet *); 183 #endif 184 static void bnx_intr_legacy(void *); 185 static void bnx_msi(void *); 186 static void bnx_intr(struct bnx_softc *); 187 static void bnx_msix_status(void *); 188 static void bnx_msix_tx_status(void *); 189 static void bnx_msix_rx(void *); 190 static void bnx_msix_rxtx(void *); 191 static void bnx_enable_intr(struct bnx_softc *); 192 static void bnx_disable_intr(struct bnx_softc *); 193 static void bnx_txeof(struct bnx_tx_ring *, uint16_t); 194 static void bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int); 195 static int bnx_alloc_intr(struct bnx_softc *); 196 static int bnx_setup_intr(struct bnx_softc *); 197 static void bnx_free_intr(struct bnx_softc *); 198 static void bnx_teardown_intr(struct bnx_softc *, int); 199 static int bnx_alloc_msix(struct bnx_softc *); 200 static void bnx_free_msix(struct bnx_softc *, boolean_t); 201 static void bnx_check_intr_rxtx(void *); 202 static void bnx_check_intr_rx(void *); 203 static void bnx_check_intr_tx(void *); 204 static void bnx_rx_std_refill_ithread(void *); 205 static void bnx_rx_std_refill(void *, void *); 206 static void bnx_rx_std_refill_sched_ipi(void *); 207 static void bnx_rx_std_refill_stop(void *); 208 static void bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *, 209 struct bnx_rx_std_ring *); 210 211 static void bnx_start(struct ifnet *, struct ifaltq_subque *); 212 static int bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 213 static void bnx_init(void *); 214 static void bnx_stop(struct bnx_softc *); 215 static void bnx_watchdog(struct ifaltq_subque *); 216 static int bnx_ifmedia_upd(struct ifnet *); 217 static void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 static void bnx_tick(void *); 219 static void bnx_serialize(struct ifnet *, enum ifnet_serialize); 220 static void bnx_deserialize(struct ifnet *, enum ifnet_serialize); 221 static int bnx_tryserialize(struct ifnet *, enum ifnet_serialize); 222 #ifdef INVARIANTS 223 static void bnx_serialize_assert(struct ifnet *, enum ifnet_serialize, 224 boolean_t); 225 #endif 226 static void bnx_serialize_skipmain(struct bnx_softc *); 227 static void bnx_deserialize_skipmain(struct bnx_softc *sc); 228 229 static int bnx_alloc_jumbo_mem(struct bnx_softc *); 230 static void bnx_free_jumbo_mem(struct bnx_softc *); 231 static struct bnx_jslot 232 *bnx_jalloc(struct bnx_softc *); 233 static void bnx_jfree(void *); 234 static void bnx_jref(void *); 235 static int bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int); 236 static int bnx_newbuf_jumbo(struct bnx_softc *, int, int); 237 static void bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int); 238 static void bnx_setup_rxdesc_jumbo(struct bnx_softc *, int); 239 static int bnx_init_rx_ring_std(struct bnx_rx_std_ring *); 240 static void bnx_free_rx_ring_std(struct bnx_rx_std_ring *); 241 static int bnx_init_rx_ring_jumbo(struct bnx_softc *); 242 static void bnx_free_rx_ring_jumbo(struct bnx_softc *); 243 static void bnx_free_tx_ring(struct bnx_tx_ring *); 244 static int bnx_init_tx_ring(struct bnx_tx_ring *); 245 static int bnx_create_tx_ring(struct bnx_tx_ring *); 246 static void bnx_destroy_tx_ring(struct bnx_tx_ring *); 247 static int bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *); 248 static void bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *); 249 static int bnx_dma_alloc(device_t); 250 static void bnx_dma_free(struct bnx_softc *); 251 static int bnx_dma_block_alloc(struct bnx_softc *, bus_size_t, 252 bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *); 253 static void bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *); 254 static struct mbuf * 255 bnx_defrag_shortdma(struct mbuf *); 256 static int bnx_encap(struct bnx_tx_ring *, struct mbuf **, 257 uint32_t *, int *); 258 static int bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **, 259 uint16_t *, uint16_t *); 260 static void bnx_setup_serialize(struct bnx_softc *); 261 static void bnx_set_tick_cpuid(struct bnx_softc *, boolean_t); 262 static void bnx_setup_ring_cnt(struct bnx_softc *); 263 264 static struct pktinfo *bnx_rss_info(struct pktinfo *, 265 const struct bge_rx_bd *); 266 static void bnx_init_rss(struct bnx_softc *); 267 static void bnx_reset(struct bnx_softc *); 268 static int bnx_chipinit(struct bnx_softc *); 269 static int bnx_blockinit(struct bnx_softc *); 270 static void bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t); 271 static void bnx_enable_msi(struct bnx_softc *, boolean_t); 272 static void bnx_setmulti(struct bnx_softc *); 273 static void bnx_setpromisc(struct bnx_softc *); 274 static void bnx_stats_update_regs(struct bnx_softc *); 275 static uint32_t bnx_dma_swap_options(struct bnx_softc *); 276 277 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t); 278 static void bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t); 279 #ifdef notdef 280 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t); 281 #endif 282 static void bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t); 283 static void bnx_writembx(struct bnx_softc *, int, int); 284 static int bnx_read_nvram(struct bnx_softc *, caddr_t, int, int); 285 static uint8_t bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *); 286 static int bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t); 287 288 static void bnx_tbi_link_upd(struct bnx_softc *, uint32_t); 289 static void bnx_copper_link_upd(struct bnx_softc *, uint32_t); 290 static void bnx_autopoll_link_upd(struct bnx_softc *, uint32_t); 291 static void bnx_link_poll(struct bnx_softc *); 292 293 static int bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]); 294 static int bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]); 295 static int bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]); 296 static int bnx_get_eaddr(struct bnx_softc *, uint8_t[]); 297 298 static void bnx_coal_change(struct bnx_softc *); 299 static int bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS); 300 static int bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS); 301 static int bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS); 302 static int bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS); 303 static int bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS); 304 static int bnx_sysctl_rx_coal_bds_poll(SYSCTL_HANDLER_ARGS); 305 static int bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS); 306 static int bnx_sysctl_tx_coal_bds_poll(SYSCTL_HANDLER_ARGS); 307 static int bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS); 308 static int bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS); 309 static int bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, 310 int, int, uint32_t); 311 static int bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS); 312 313 static void bnx_sig_post_reset(struct bnx_softc *, int); 314 static void bnx_sig_pre_reset(struct bnx_softc *, int); 315 static void bnx_ape_lock_init(struct bnx_softc *); 316 static void bnx_ape_read_fw_ver(struct bnx_softc *); 317 static int bnx_ape_lock(struct bnx_softc *, int); 318 static void bnx_ape_unlock(struct bnx_softc *, int); 319 static void bnx_ape_send_event(struct bnx_softc *, uint32_t); 320 static void bnx_ape_driver_state_change(struct bnx_softc *, int); 321 322 static int bnx_msi_enable = 1; 323 static int bnx_msix_enable = 1; 324 325 static int bnx_rx_rings = 0; /* auto */ 326 static int bnx_tx_rings = 0; /* auto */ 327 328 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable); 329 TUNABLE_INT("hw.bnx.msix.enable", &bnx_msix_enable); 330 TUNABLE_INT("hw.bnx.rx_rings", &bnx_rx_rings); 331 TUNABLE_INT("hw.bnx.tx_rings", &bnx_tx_rings); 332 333 static device_method_t bnx_methods[] = { 334 /* Device interface */ 335 DEVMETHOD(device_probe, bnx_probe), 336 DEVMETHOD(device_attach, bnx_attach), 337 DEVMETHOD(device_detach, bnx_detach), 338 DEVMETHOD(device_shutdown, bnx_shutdown), 339 DEVMETHOD(device_suspend, bnx_suspend), 340 DEVMETHOD(device_resume, bnx_resume), 341 342 /* bus interface */ 343 DEVMETHOD(bus_print_child, bus_generic_print_child), 344 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 345 346 /* MII interface */ 347 DEVMETHOD(miibus_readreg, bnx_miibus_readreg), 348 DEVMETHOD(miibus_writereg, bnx_miibus_writereg), 349 DEVMETHOD(miibus_statchg, bnx_miibus_statchg), 350 351 DEVMETHOD_END 352 }; 353 354 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc)); 355 static devclass_t bnx_devclass; 356 357 DECLARE_DUMMY_MODULE(if_bnx); 358 MODULE_DEPEND(if_bnx, miibus, 1, 1, 1); 359 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL); 360 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL); 361 362 static uint32_t 363 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off) 364 { 365 device_t dev = sc->bnx_dev; 366 uint32_t val; 367 368 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 369 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 370 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 371 return (val); 372 } 373 374 static void 375 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val) 376 { 377 device_t dev = sc->bnx_dev; 378 379 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 380 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 381 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 382 } 383 384 static void 385 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val) 386 { 387 CSR_WRITE_4(sc, off, val); 388 } 389 390 static void 391 bnx_writembx(struct bnx_softc *sc, int off, int val) 392 { 393 CSR_WRITE_4(sc, off, val); 394 } 395 396 /* 397 * Read a sequence of bytes from NVRAM. 398 */ 399 static int 400 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt) 401 { 402 return (1); 403 } 404 405 /* 406 * Read a byte of data stored in the EEPROM at address 'addr.' The 407 * BCM570x supports both the traditional bitbang interface and an 408 * auto access interface for reading the EEPROM. We use the auto 409 * access method. 410 */ 411 static uint8_t 412 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest) 413 { 414 int i; 415 uint32_t byte = 0; 416 417 /* 418 * Enable use of auto EEPROM access so we can avoid 419 * having to use the bitbang method. 420 */ 421 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 422 423 /* Reset the EEPROM, load the clock period. */ 424 CSR_WRITE_4(sc, BGE_EE_ADDR, 425 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 426 DELAY(20); 427 428 /* Issue the read EEPROM command. */ 429 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 430 431 /* Wait for completion */ 432 for(i = 0; i < BNX_TIMEOUT * 10; i++) { 433 DELAY(10); 434 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 435 break; 436 } 437 438 if (i == BNX_TIMEOUT) { 439 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n"); 440 return(1); 441 } 442 443 /* Get result. */ 444 byte = CSR_READ_4(sc, BGE_EE_DATA); 445 446 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 447 448 return(0); 449 } 450 451 /* 452 * Read a sequence of bytes from the EEPROM. 453 */ 454 static int 455 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len) 456 { 457 size_t i; 458 int err; 459 uint8_t byte; 460 461 for (byte = 0, err = 0, i = 0; i < len; i++) { 462 err = bnx_eeprom_getbyte(sc, off + i, &byte); 463 if (err) 464 break; 465 *(dest + i) = byte; 466 } 467 468 return(err ? 1 : 0); 469 } 470 471 static int 472 bnx_miibus_readreg(device_t dev, int phy, int reg) 473 { 474 struct bnx_softc *sc = device_get_softc(dev); 475 uint32_t val; 476 int i; 477 478 KASSERT(phy == sc->bnx_phyno, 479 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno)); 480 481 if (bnx_ape_lock(sc, sc->bnx_phy_ape_lock) != 0) 482 return 0; 483 484 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 485 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 486 CSR_WRITE_4(sc, BGE_MI_MODE, 487 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL); 488 DELAY(80); 489 } 490 491 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 492 BGE_MIPHY(phy) | BGE_MIREG(reg)); 493 494 /* Poll for the PHY register access to complete. */ 495 for (i = 0; i < BNX_TIMEOUT; i++) { 496 DELAY(10); 497 val = CSR_READ_4(sc, BGE_MI_COMM); 498 if ((val & BGE_MICOMM_BUSY) == 0) { 499 DELAY(5); 500 val = CSR_READ_4(sc, BGE_MI_COMM); 501 break; 502 } 503 } 504 if (i == BNX_TIMEOUT) { 505 if_printf(&sc->arpcom.ac_if, "PHY read timed out " 506 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val); 507 val = 0; 508 } 509 510 /* Restore the autopoll bit if necessary. */ 511 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 512 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode); 513 DELAY(80); 514 } 515 516 bnx_ape_unlock(sc, sc->bnx_phy_ape_lock); 517 518 if (val & BGE_MICOMM_READFAIL) 519 return 0; 520 521 return (val & 0xFFFF); 522 } 523 524 static int 525 bnx_miibus_writereg(device_t dev, int phy, int reg, int val) 526 { 527 struct bnx_softc *sc = device_get_softc(dev); 528 int i; 529 530 KASSERT(phy == sc->bnx_phyno, 531 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno)); 532 533 if (bnx_ape_lock(sc, sc->bnx_phy_ape_lock) != 0) 534 return 0; 535 536 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 537 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 538 CSR_WRITE_4(sc, BGE_MI_MODE, 539 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL); 540 DELAY(80); 541 } 542 543 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 544 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 545 546 for (i = 0; i < BNX_TIMEOUT; i++) { 547 DELAY(10); 548 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 549 DELAY(5); 550 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 551 break; 552 } 553 } 554 if (i == BNX_TIMEOUT) { 555 if_printf(&sc->arpcom.ac_if, "PHY write timed out " 556 "(phy %d, reg %d, val %d)\n", phy, reg, val); 557 } 558 559 /* Restore the autopoll bit if necessary. */ 560 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 561 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode); 562 DELAY(80); 563 } 564 565 bnx_ape_unlock(sc, sc->bnx_phy_ape_lock); 566 567 return 0; 568 } 569 570 static void 571 bnx_miibus_statchg(device_t dev) 572 { 573 struct bnx_softc *sc; 574 struct mii_data *mii; 575 uint32_t mac_mode; 576 577 sc = device_get_softc(dev); 578 if ((sc->arpcom.ac_if.if_flags & IFF_RUNNING) == 0) 579 return; 580 581 mii = device_get_softc(sc->bnx_miibus); 582 583 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 584 (IFM_ACTIVE | IFM_AVALID)) { 585 switch (IFM_SUBTYPE(mii->mii_media_active)) { 586 case IFM_10_T: 587 case IFM_100_TX: 588 sc->bnx_link = 1; 589 break; 590 case IFM_1000_T: 591 case IFM_1000_SX: 592 case IFM_2500_SX: 593 sc->bnx_link = 1; 594 break; 595 default: 596 sc->bnx_link = 0; 597 break; 598 } 599 } else { 600 sc->bnx_link = 0; 601 } 602 if (sc->bnx_link == 0) 603 return; 604 605 /* 606 * APE firmware touches these registers to keep the MAC 607 * connected to the outside world. Try to keep the 608 * accesses atomic. 609 */ 610 611 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 612 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 613 614 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 615 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 616 mac_mode |= BGE_PORTMODE_GMII; 617 else 618 mac_mode |= BGE_PORTMODE_MII; 619 620 if ((mii->mii_media_active & IFM_GMASK) != IFM_FDX) 621 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 622 623 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 624 DELAY(40); 625 } 626 627 /* 628 * Memory management for jumbo frames. 629 */ 630 static int 631 bnx_alloc_jumbo_mem(struct bnx_softc *sc) 632 { 633 struct ifnet *ifp = &sc->arpcom.ac_if; 634 struct bnx_jslot *entry; 635 uint8_t *ptr; 636 bus_addr_t paddr; 637 int i, error; 638 639 /* 640 * Create tag for jumbo mbufs. 641 * This is really a bit of a kludge. We allocate a special 642 * jumbo buffer pool which (thanks to the way our DMA 643 * memory allocation works) will consist of contiguous 644 * pages. This means that even though a jumbo buffer might 645 * be larger than a page size, we don't really need to 646 * map it into more than one DMA segment. However, the 647 * default mbuf tag will result in multi-segment mappings, 648 * so we have to create a special jumbo mbuf tag that 649 * lets us get away with mapping the jumbo buffers as 650 * a single segment. I think eventually the driver should 651 * be changed so that it uses ordinary mbufs and cluster 652 * buffers, i.e. jumbo frames can span multiple DMA 653 * descriptors. But that's a project for another day. 654 */ 655 656 /* 657 * Create DMA stuffs for jumbo RX ring. 658 */ 659 error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ, 660 &sc->bnx_cdata.bnx_rx_jumbo_ring_tag, 661 &sc->bnx_cdata.bnx_rx_jumbo_ring_map, 662 (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring, 663 &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr); 664 if (error) { 665 if_printf(ifp, "could not create jumbo RX ring\n"); 666 return error; 667 } 668 669 /* 670 * Create DMA stuffs for jumbo buffer block. 671 */ 672 error = bnx_dma_block_alloc(sc, BNX_JMEM, 673 &sc->bnx_cdata.bnx_jumbo_tag, 674 &sc->bnx_cdata.bnx_jumbo_map, 675 (void **)&sc->bnx_ldata.bnx_jumbo_buf, 676 &paddr); 677 if (error) { 678 if_printf(ifp, "could not create jumbo buffer\n"); 679 return error; 680 } 681 682 SLIST_INIT(&sc->bnx_jfree_listhead); 683 684 /* 685 * Now divide it up into 9K pieces and save the addresses 686 * in an array. Note that we play an evil trick here by using 687 * the first few bytes in the buffer to hold the the address 688 * of the softc structure for this interface. This is because 689 * bnx_jfree() needs it, but it is called by the mbuf management 690 * code which will not pass it to us explicitly. 691 */ 692 for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) { 693 entry = &sc->bnx_cdata.bnx_jslots[i]; 694 entry->bnx_sc = sc; 695 entry->bnx_buf = ptr; 696 entry->bnx_paddr = paddr; 697 entry->bnx_inuse = 0; 698 entry->bnx_slot = i; 699 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link); 700 701 ptr += BNX_JLEN; 702 paddr += BNX_JLEN; 703 } 704 return 0; 705 } 706 707 static void 708 bnx_free_jumbo_mem(struct bnx_softc *sc) 709 { 710 /* Destroy jumbo RX ring. */ 711 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag, 712 sc->bnx_cdata.bnx_rx_jumbo_ring_map, 713 sc->bnx_ldata.bnx_rx_jumbo_ring); 714 715 /* Destroy jumbo buffer block. */ 716 bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag, 717 sc->bnx_cdata.bnx_jumbo_map, 718 sc->bnx_ldata.bnx_jumbo_buf); 719 } 720 721 /* 722 * Allocate a jumbo buffer. 723 */ 724 static struct bnx_jslot * 725 bnx_jalloc(struct bnx_softc *sc) 726 { 727 struct bnx_jslot *entry; 728 729 lwkt_serialize_enter(&sc->bnx_jslot_serializer); 730 entry = SLIST_FIRST(&sc->bnx_jfree_listhead); 731 if (entry) { 732 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link); 733 entry->bnx_inuse = 1; 734 } else { 735 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 736 } 737 lwkt_serialize_exit(&sc->bnx_jslot_serializer); 738 return(entry); 739 } 740 741 /* 742 * Adjust usage count on a jumbo buffer. 743 */ 744 static void 745 bnx_jref(void *arg) 746 { 747 struct bnx_jslot *entry = (struct bnx_jslot *)arg; 748 struct bnx_softc *sc = entry->bnx_sc; 749 750 if (sc == NULL) 751 panic("bnx_jref: can't find softc pointer!"); 752 753 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) { 754 panic("bnx_jref: asked to reference buffer " 755 "that we don't manage!"); 756 } else if (entry->bnx_inuse == 0) { 757 panic("bnx_jref: buffer already free!"); 758 } else { 759 atomic_add_int(&entry->bnx_inuse, 1); 760 } 761 } 762 763 /* 764 * Release a jumbo buffer. 765 */ 766 static void 767 bnx_jfree(void *arg) 768 { 769 struct bnx_jslot *entry = (struct bnx_jslot *)arg; 770 struct bnx_softc *sc = entry->bnx_sc; 771 772 if (sc == NULL) 773 panic("bnx_jfree: can't find softc pointer!"); 774 775 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) { 776 panic("bnx_jfree: asked to free buffer that we don't manage!"); 777 } else if (entry->bnx_inuse == 0) { 778 panic("bnx_jfree: buffer already free!"); 779 } else { 780 /* 781 * Possible MP race to 0, use the serializer. The atomic insn 782 * is still needed for races against bnx_jref(). 783 */ 784 lwkt_serialize_enter(&sc->bnx_jslot_serializer); 785 atomic_subtract_int(&entry->bnx_inuse, 1); 786 if (entry->bnx_inuse == 0) { 787 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, 788 entry, jslot_link); 789 } 790 lwkt_serialize_exit(&sc->bnx_jslot_serializer); 791 } 792 } 793 794 795 /* 796 * Intialize a standard receive ring descriptor. 797 */ 798 static int 799 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init) 800 { 801 struct mbuf *m_new = NULL; 802 bus_dma_segment_t seg; 803 bus_dmamap_t map; 804 int error, nsegs; 805 struct bnx_rx_buf *rb; 806 807 rb = &ret->bnx_std->bnx_rx_std_buf[i]; 808 KASSERT(!rb->bnx_rx_refilled, ("RX buf %dth has been refilled", i)); 809 810 m_new = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 811 if (m_new == NULL) { 812 error = ENOBUFS; 813 goto back; 814 } 815 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 816 m_adj(m_new, ETHER_ALIGN); 817 818 error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag, 819 ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT); 820 if (error) { 821 m_freem(m_new); 822 goto back; 823 } 824 825 if (!init) { 826 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap, 827 BUS_DMASYNC_POSTREAD); 828 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap); 829 } 830 831 map = ret->bnx_rx_tmpmap; 832 ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap; 833 834 rb->bnx_rx_dmamap = map; 835 rb->bnx_rx_mbuf = m_new; 836 rb->bnx_rx_paddr = seg.ds_addr; 837 rb->bnx_rx_len = m_new->m_len; 838 back: 839 cpu_sfence(); 840 rb->bnx_rx_refilled = 1; 841 return error; 842 } 843 844 static void 845 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i) 846 { 847 struct bnx_rx_buf *rb; 848 struct bge_rx_bd *r; 849 bus_addr_t paddr; 850 int len; 851 852 rb = &std->bnx_rx_std_buf[i]; 853 KASSERT(rb->bnx_rx_refilled, ("RX buf %dth is not refilled", i)); 854 855 paddr = rb->bnx_rx_paddr; 856 len = rb->bnx_rx_len; 857 858 cpu_mfence(); 859 860 rb->bnx_rx_refilled = 0; 861 862 r = &std->bnx_rx_std_ring[i]; 863 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr); 864 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr); 865 r->bge_len = len; 866 r->bge_idx = i; 867 r->bge_flags = BGE_RXBDFLAG_END; 868 } 869 870 /* 871 * Initialize a jumbo receive ring descriptor. This allocates 872 * a jumbo buffer from the pool managed internally by the driver. 873 */ 874 static int 875 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init) 876 { 877 struct mbuf *m_new = NULL; 878 struct bnx_jslot *buf; 879 bus_addr_t paddr; 880 881 /* Allocate the mbuf. */ 882 MGETHDR(m_new, init ? M_WAITOK : M_NOWAIT, MT_DATA); 883 if (m_new == NULL) 884 return ENOBUFS; 885 886 /* Allocate the jumbo buffer */ 887 buf = bnx_jalloc(sc); 888 if (buf == NULL) { 889 m_freem(m_new); 890 return ENOBUFS; 891 } 892 893 /* Attach the buffer to the mbuf. */ 894 m_new->m_ext.ext_arg = buf; 895 m_new->m_ext.ext_buf = buf->bnx_buf; 896 m_new->m_ext.ext_free = bnx_jfree; 897 m_new->m_ext.ext_ref = bnx_jref; 898 m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN; 899 900 m_new->m_flags |= M_EXT; 901 902 m_new->m_data = m_new->m_ext.ext_buf; 903 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 904 905 paddr = buf->bnx_paddr; 906 m_adj(m_new, ETHER_ALIGN); 907 paddr += ETHER_ALIGN; 908 909 /* Save necessary information */ 910 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new; 911 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr; 912 913 /* Set up the descriptor. */ 914 bnx_setup_rxdesc_jumbo(sc, i); 915 return 0; 916 } 917 918 static void 919 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i) 920 { 921 struct bge_rx_bd *r; 922 struct bnx_rx_buf *rc; 923 924 r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i]; 925 rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i]; 926 927 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr); 928 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr); 929 r->bge_len = rc->bnx_rx_mbuf->m_len; 930 r->bge_idx = i; 931 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 932 } 933 934 static int 935 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std) 936 { 937 int i, error; 938 939 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 940 /* Use the first RX return ring's tmp RX mbuf DMA map */ 941 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1); 942 if (error) 943 return error; 944 bnx_setup_rxdesc_std(std, i); 945 } 946 947 std->bnx_rx_std_used = 0; 948 std->bnx_rx_std_refill = 0; 949 std->bnx_rx_std_running = 0; 950 cpu_sfence(); 951 lwkt_serialize_handler_enable(&std->bnx_rx_std_serialize); 952 953 std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1; 954 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std); 955 956 return(0); 957 } 958 959 static void 960 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std) 961 { 962 int i; 963 964 lwkt_serialize_handler_disable(&std->bnx_rx_std_serialize); 965 966 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 967 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i]; 968 969 rb->bnx_rx_refilled = 0; 970 if (rb->bnx_rx_mbuf != NULL) { 971 bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap); 972 m_freem(rb->bnx_rx_mbuf); 973 rb->bnx_rx_mbuf = NULL; 974 } 975 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd)); 976 } 977 } 978 979 static int 980 bnx_init_rx_ring_jumbo(struct bnx_softc *sc) 981 { 982 struct bge_rcb *rcb; 983 int i, error; 984 985 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 986 error = bnx_newbuf_jumbo(sc, i, 1); 987 if (error) 988 return error; 989 } 990 991 sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1; 992 993 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb; 994 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 995 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 996 997 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo); 998 999 return(0); 1000 } 1001 1002 static void 1003 bnx_free_rx_ring_jumbo(struct bnx_softc *sc) 1004 { 1005 int i; 1006 1007 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1008 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i]; 1009 1010 if (rc->bnx_rx_mbuf != NULL) { 1011 m_freem(rc->bnx_rx_mbuf); 1012 rc->bnx_rx_mbuf = NULL; 1013 } 1014 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i], 1015 sizeof(struct bge_rx_bd)); 1016 } 1017 } 1018 1019 static void 1020 bnx_free_tx_ring(struct bnx_tx_ring *txr) 1021 { 1022 int i; 1023 1024 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1025 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i]; 1026 1027 if (buf->bnx_tx_mbuf != NULL) { 1028 bus_dmamap_unload(txr->bnx_tx_mtag, 1029 buf->bnx_tx_dmamap); 1030 m_freem(buf->bnx_tx_mbuf); 1031 buf->bnx_tx_mbuf = NULL; 1032 } 1033 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd)); 1034 } 1035 txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET; 1036 } 1037 1038 static int 1039 bnx_init_tx_ring(struct bnx_tx_ring *txr) 1040 { 1041 txr->bnx_tx_cnt = 0; 1042 txr->bnx_tx_saved_considx = 0; 1043 txr->bnx_tx_prodidx = 0; 1044 1045 /* Initialize transmit producer index for host-memory send ring. */ 1046 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx); 1047 1048 return(0); 1049 } 1050 1051 static void 1052 bnx_setmulti(struct bnx_softc *sc) 1053 { 1054 struct ifnet *ifp; 1055 struct ifmultiaddr *ifma; 1056 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1057 int h, i; 1058 1059 ifp = &sc->arpcom.ac_if; 1060 1061 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1062 for (i = 0; i < 4; i++) 1063 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1064 return; 1065 } 1066 1067 /* First, zot all the existing filters. */ 1068 for (i = 0; i < 4; i++) 1069 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1070 1071 /* Now program new ones. */ 1072 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1073 if (ifma->ifma_addr->sa_family != AF_LINK) 1074 continue; 1075 h = ether_crc32_le( 1076 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1077 ETHER_ADDR_LEN) & 0x7f; 1078 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1079 } 1080 1081 for (i = 0; i < 4; i++) 1082 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1083 } 1084 1085 /* 1086 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1087 * self-test results. 1088 */ 1089 static int 1090 bnx_chipinit(struct bnx_softc *sc) 1091 { 1092 uint32_t dma_rw_ctl, mode_ctl; 1093 int i; 1094 1095 /* Set endian type before we access any non-PCI registers. */ 1096 pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL, 1097 BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4); 1098 1099 /* 1100 * Clear the MAC statistics block in the NIC's 1101 * internal memory. 1102 */ 1103 for (i = BGE_STATS_BLOCK; 1104 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1105 BNX_MEMWIN_WRITE(sc, i, 0); 1106 1107 for (i = BGE_STATUS_BLOCK; 1108 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1109 BNX_MEMWIN_WRITE(sc, i, 0); 1110 1111 if (BNX_IS_57765_FAMILY(sc)) { 1112 uint32_t val; 1113 1114 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) { 1115 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 1116 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS; 1117 1118 /* Access the lower 1K of PL PCI-E block registers. */ 1119 CSR_WRITE_4(sc, BGE_MODE_CTL, 1120 val | BGE_MODECTL_PCIE_PL_SEL); 1121 1122 val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5); 1123 val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ; 1124 CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val); 1125 1126 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1127 } 1128 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) { 1129 /* Fix transmit hangs */ 1130 val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 1131 val |= BGE_CPMU_PADRNG_CTL_RDIV2; 1132 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val); 1133 1134 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 1135 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS; 1136 1137 /* Access the lower 1K of DL PCI-E block registers. */ 1138 CSR_WRITE_4(sc, BGE_MODE_CTL, 1139 val | BGE_MODECTL_PCIE_DL_SEL); 1140 1141 val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX); 1142 val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK; 1143 val |= BGE_PCIE_DL_LO_FTSMAX_VAL; 1144 CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val); 1145 1146 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1147 } 1148 1149 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 1150 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 1151 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 1152 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val); 1153 } 1154 1155 /* 1156 * Set up the PCI DMA control register. 1157 */ 1158 dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4); 1159 /* 1160 * Disable 32bytes cache alignment for DMA write to host memory 1161 * 1162 * NOTE: 1163 * 64bytes cache alignment for DMA write to host memory is still 1164 * enabled. 1165 */ 1166 dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1167 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) 1168 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1169 /* 1170 * Enable HW workaround for controllers that misinterpret 1171 * a status tag update and leave interrupts permanently 1172 * disabled. 1173 */ 1174 if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 && 1175 sc->bnx_asicrev != BGE_ASICREV_BCM5762 && 1176 !BNX_IS_57765_FAMILY(sc)) 1177 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1178 if (bootverbose) { 1179 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n", 1180 dma_rw_ctl); 1181 } 1182 pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1183 1184 /* 1185 * Set up general mode register. 1186 */ 1187 mode_ctl = bnx_dma_swap_options(sc); 1188 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1189 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1190 /* Retain Host-2-BMC settings written by APE firmware. */ 1191 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1192 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1193 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1194 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1195 } 1196 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | 1197 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM; 1198 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1199 1200 /* 1201 * Disable memory write invalidate. Apparently it is not supported 1202 * properly by these devices. Also ensure that INTx isn't disabled, 1203 * as these chips need it even when using MSI. 1204 */ 1205 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD, 1206 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4); 1207 1208 /* Set the timer prescaler (always 66Mhz) */ 1209 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1210 1211 return(0); 1212 } 1213 1214 static int 1215 bnx_blockinit(struct bnx_softc *sc) 1216 { 1217 struct bnx_intr_data *intr; 1218 struct bge_rcb *rcb; 1219 bus_size_t vrcb; 1220 bge_hostaddr taddr; 1221 uint32_t val; 1222 int i, limit; 1223 1224 /* 1225 * Initialize the memory window pointer register so that 1226 * we can access the first 32K of internal NIC RAM. This will 1227 * allow us to set up the TX send ring RCBs and the RX return 1228 * ring RCBs, plus other things which live in NIC memory. 1229 */ 1230 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1231 1232 /* Configure mbuf pool watermarks */ 1233 if (BNX_IS_57765_PLUS(sc)) { 1234 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1235 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) { 1236 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1237 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1238 } else { 1239 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1240 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1241 } 1242 } else { 1243 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1244 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1245 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1246 } 1247 1248 /* Configure DMA resource watermarks */ 1249 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1250 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1251 1252 /* Enable buffer manager */ 1253 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1254 /* 1255 * Change the arbitration algorithm of TXMBUF read request to 1256 * round-robin instead of priority based for BCM5719. When 1257 * TXFIFO is almost empty, RDMA will hold its request until 1258 * TXFIFO is not almost empty. 1259 */ 1260 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) 1261 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 1262 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 || 1263 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 || 1264 sc->bnx_chipid == BGE_CHIPID_BCM5720_A0) 1265 val |= BGE_BMANMODE_LOMBUF_ATTN; 1266 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 1267 1268 /* Poll for buffer manager start indication */ 1269 for (i = 0; i < BNX_TIMEOUT; i++) { 1270 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1271 break; 1272 DELAY(10); 1273 } 1274 1275 if (i == BNX_TIMEOUT) { 1276 if_printf(&sc->arpcom.ac_if, 1277 "buffer manager failed to start\n"); 1278 return(ENXIO); 1279 } 1280 1281 /* Enable flow-through queues */ 1282 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1283 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1284 1285 /* Wait until queue initialization is complete */ 1286 for (i = 0; i < BNX_TIMEOUT; i++) { 1287 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1288 break; 1289 DELAY(10); 1290 } 1291 1292 if (i == BNX_TIMEOUT) { 1293 if_printf(&sc->arpcom.ac_if, 1294 "flow-through queue init failed\n"); 1295 return(ENXIO); 1296 } 1297 1298 /* 1299 * Summary of rings supported by the controller: 1300 * 1301 * Standard Receive Producer Ring 1302 * - This ring is used to feed receive buffers for "standard" 1303 * sized frames (typically 1536 bytes) to the controller. 1304 * 1305 * Jumbo Receive Producer Ring 1306 * - This ring is used to feed receive buffers for jumbo sized 1307 * frames (i.e. anything bigger than the "standard" frames) 1308 * to the controller. 1309 * 1310 * Mini Receive Producer Ring 1311 * - This ring is used to feed receive buffers for "mini" 1312 * sized frames to the controller. 1313 * - This feature required external memory for the controller 1314 * but was never used in a production system. Should always 1315 * be disabled. 1316 * 1317 * Receive Return Ring 1318 * - After the controller has placed an incoming frame into a 1319 * receive buffer that buffer is moved into a receive return 1320 * ring. The driver is then responsible to passing the 1321 * buffer up to the stack. BCM5718/BCM57785 families support 1322 * multiple receive return rings. 1323 * 1324 * Send Ring 1325 * - This ring is used for outgoing frames. BCM5719/BCM5720 1326 * support multiple send rings. 1327 */ 1328 1329 /* Initialize the standard receive producer ring control block. */ 1330 rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb; 1331 rcb->bge_hostaddr.bge_addr_lo = 1332 BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr); 1333 rcb->bge_hostaddr.bge_addr_hi = 1334 BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr); 1335 if (BNX_IS_57765_PLUS(sc)) { 1336 /* 1337 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 1338 * Bits 15-2 : Maximum RX frame size 1339 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 1340 * Bit 0 : Reserved 1341 */ 1342 rcb->bge_maxlen_flags = 1343 BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2); 1344 } else { 1345 /* 1346 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1347 * Bits 15-2 : Reserved (should be 0) 1348 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1349 * Bit 0 : Reserved 1350 */ 1351 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1352 } 1353 if (BNX_IS_5717_PLUS(sc)) 1354 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 1355 else 1356 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1357 /* Write the standard receive producer ring control block. */ 1358 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1359 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1360 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1361 if (!BNX_IS_5717_PLUS(sc)) 1362 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1363 /* Reset the standard receive producer ring producer index. */ 1364 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1365 1366 /* 1367 * Initialize the jumbo RX producer ring control 1368 * block. We set the 'ring disabled' bit in the 1369 * flags field until we're actually ready to start 1370 * using this ring (i.e. once we set the MTU 1371 * high enough to require it). 1372 */ 1373 if (BNX_IS_JUMBO_CAPABLE(sc)) { 1374 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb; 1375 /* Get the jumbo receive producer ring RCB parameters. */ 1376 rcb->bge_hostaddr.bge_addr_lo = 1377 BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr); 1378 rcb->bge_hostaddr.bge_addr_hi = 1379 BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr); 1380 rcb->bge_maxlen_flags = 1381 BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN, 1382 BGE_RCB_FLAG_RING_DISABLED); 1383 if (BNX_IS_5717_PLUS(sc)) 1384 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 1385 else 1386 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1387 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1388 rcb->bge_hostaddr.bge_addr_hi); 1389 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1390 rcb->bge_hostaddr.bge_addr_lo); 1391 /* Program the jumbo receive producer ring RCB parameters. */ 1392 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1393 rcb->bge_maxlen_flags); 1394 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1395 /* Reset the jumbo receive producer ring producer index. */ 1396 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1397 } 1398 1399 /* 1400 * The BD ring replenish thresholds control how often the 1401 * hardware fetches new BD's from the producer rings in host 1402 * memory. Setting the value too low on a busy system can 1403 * starve the hardware and recue the throughpout. 1404 * 1405 * Set the BD ring replentish thresholds. The recommended 1406 * values are 1/8th the number of descriptors allocated to 1407 * each ring. 1408 */ 1409 val = 8; 1410 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1411 if (BNX_IS_JUMBO_CAPABLE(sc)) { 1412 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1413 BGE_JUMBO_RX_RING_CNT/8); 1414 } 1415 if (BNX_IS_57765_PLUS(sc)) { 1416 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 1417 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 1418 } 1419 1420 /* 1421 * Disable all send rings by setting the 'ring disabled' bit 1422 * in the flags field of all the TX send ring control blocks, 1423 * located in NIC memory. 1424 */ 1425 if (BNX_IS_5717_PLUS(sc)) 1426 limit = 4; 1427 else if (BNX_IS_57765_FAMILY(sc) || 1428 sc->bnx_asicrev == BGE_ASICREV_BCM5762) 1429 limit = 2; 1430 else 1431 limit = 1; 1432 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1433 for (i = 0; i < limit; i++) { 1434 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1435 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1436 vrcb += sizeof(struct bge_rcb); 1437 } 1438 1439 /* 1440 * Configure send ring RCBs 1441 */ 1442 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1443 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 1444 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 1445 1446 BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr); 1447 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 1448 taddr.bge_addr_hi); 1449 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 1450 taddr.bge_addr_lo); 1451 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1452 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1453 vrcb += sizeof(struct bge_rcb); 1454 } 1455 1456 /* 1457 * Disable all receive return rings by setting the 1458 * 'ring disabled' bit in the flags field of all the receive 1459 * return ring control blocks, located in NIC memory. 1460 */ 1461 if (BNX_IS_5717_PLUS(sc)) { 1462 /* Should be 17, use 16 until we get an SRAM map. */ 1463 limit = 16; 1464 } else if (BNX_IS_57765_FAMILY(sc) || 1465 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1466 limit = 4; 1467 } else { 1468 limit = 1; 1469 } 1470 /* Disable all receive return rings. */ 1471 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1472 for (i = 0; i < limit; i++) { 1473 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1474 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1475 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1476 BGE_RCB_FLAG_RING_DISABLED); 1477 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO + 1478 (i * (sizeof(uint64_t))), 0); 1479 vrcb += sizeof(struct bge_rcb); 1480 } 1481 1482 /* 1483 * Set up receive return rings. 1484 */ 1485 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1486 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 1487 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i]; 1488 1489 BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr); 1490 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 1491 taddr.bge_addr_hi); 1492 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 1493 taddr.bge_addr_lo); 1494 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1495 BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0)); 1496 vrcb += sizeof(struct bge_rcb); 1497 } 1498 1499 /* Set random backoff seed for TX */ 1500 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1501 (sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1502 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1503 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 1504 BGE_TX_BACKOFF_SEED_MASK); 1505 1506 /* Set inter-packet gap */ 1507 val = 0x2620; 1508 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1509 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1510 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 1511 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 1512 } 1513 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 1514 1515 /* 1516 * Specify which ring to use for packets that don't match 1517 * any RX rules. 1518 */ 1519 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1520 1521 /* 1522 * Configure number of RX lists. One interrupt distribution 1523 * list, sixteen active lists, one bad frames class. 1524 */ 1525 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1526 1527 /* Inialize RX list placement stats mask. */ 1528 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1529 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1530 1531 /* Disable host coalescing until we get it set up */ 1532 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1533 1534 /* Poll to make sure it's shut down. */ 1535 for (i = 0; i < BNX_TIMEOUT; i++) { 1536 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1537 break; 1538 DELAY(10); 1539 } 1540 1541 if (i == BNX_TIMEOUT) { 1542 if_printf(&sc->arpcom.ac_if, 1543 "host coalescing engine failed to idle\n"); 1544 return(ENXIO); 1545 } 1546 1547 /* Set up host coalescing defaults */ 1548 sc->bnx_coal_chg = BNX_RX_COAL_TICKS_CHG | 1549 BNX_TX_COAL_TICKS_CHG | 1550 BNX_RX_COAL_BDS_CHG | 1551 BNX_TX_COAL_BDS_CHG | 1552 BNX_RX_COAL_BDS_INT_CHG | 1553 BNX_TX_COAL_BDS_INT_CHG; 1554 bnx_coal_change(sc); 1555 1556 /* 1557 * Set up addresses of status blocks 1558 */ 1559 intr = &sc->bnx_intr_data[0]; 1560 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ); 1561 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1562 BGE_ADDR_HI(intr->bnx_status_block_paddr)); 1563 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1564 BGE_ADDR_LO(intr->bnx_status_block_paddr)); 1565 for (i = 1; i < sc->bnx_intr_cnt; ++i) { 1566 intr = &sc->bnx_intr_data[i]; 1567 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ); 1568 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_HI + ((i - 1) * 8), 1569 BGE_ADDR_HI(intr->bnx_status_block_paddr)); 1570 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_LO + ((i - 1) * 8), 1571 BGE_ADDR_LO(intr->bnx_status_block_paddr)); 1572 } 1573 1574 /* Set up status block partail update size. */ 1575 val = BGE_STATBLKSZ_32BYTE; 1576 #if 0 1577 /* 1578 * Does not seem to have visible effect in both 1579 * bulk data (1472B UDP datagram) and tiny data 1580 * (18B UDP datagram) TX tests. 1581 */ 1582 val |= BGE_HCCMODE_CLRTICK_TX; 1583 #endif 1584 /* Turn on host coalescing state machine */ 1585 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1586 1587 /* Turn on RX BD completion state machine and enable attentions */ 1588 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1589 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1590 1591 /* Turn on RX list placement state machine */ 1592 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1593 1594 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1595 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1596 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1597 BGE_MACMODE_FRMHDR_DMA_ENB; 1598 1599 if (sc->bnx_flags & BNX_FLAG_TBI) 1600 val |= BGE_PORTMODE_TBI; 1601 else if (sc->bnx_flags & BNX_FLAG_MII_SERDES) 1602 val |= BGE_PORTMODE_GMII; 1603 else 1604 val |= BGE_PORTMODE_MII; 1605 1606 /* Allow APE to send/receive frames. */ 1607 if (sc->bnx_mfw_flags & BNX_MFW_ON_APE) 1608 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 1609 1610 /* Turn on DMA, clear stats */ 1611 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1612 DELAY(40); 1613 1614 /* Set misc. local control, enable interrupts on attentions */ 1615 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1616 1617 #ifdef notdef 1618 /* Assert GPIO pins for PHY reset */ 1619 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1620 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1621 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1622 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1623 #endif 1624 1625 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) 1626 bnx_enable_msi(sc, TRUE); 1627 1628 /* Turn on write DMA state machine */ 1629 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1630 /* Enable host coalescing bug fix. */ 1631 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1632 if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) { 1633 /* Request larger DMA burst size to get better performance. */ 1634 val |= BGE_WDMAMODE_BURST_ALL_DATA; 1635 } 1636 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1637 DELAY(40); 1638 1639 if (BNX_IS_57765_PLUS(sc)) { 1640 uint32_t dmactl, dmactl_reg; 1641 1642 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762) 1643 dmactl_reg = BGE_RDMA_RSRVCTRL2; 1644 else 1645 dmactl_reg = BGE_RDMA_RSRVCTRL; 1646 1647 dmactl = CSR_READ_4(sc, dmactl_reg); 1648 /* 1649 * Adjust tx margin to prevent TX data corruption and 1650 * fix internal FIFO overflow. 1651 */ 1652 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 || 1653 sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1654 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1655 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 1656 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 1657 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 1658 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 1659 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 1660 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 1661 } 1662 /* 1663 * Enable fix for read DMA FIFO overruns. 1664 * The fix is to limit the number of RX BDs 1665 * the hardware would fetch at a fime. 1666 */ 1667 CSR_WRITE_4(sc, dmactl_reg, 1668 dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 1669 } 1670 1671 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) { 1672 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 1673 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 1674 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 1675 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 1676 } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1677 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1678 uint32_t ctrl_reg; 1679 1680 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762) 1681 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2; 1682 else 1683 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL; 1684 1685 /* 1686 * Allow 4KB burst length reads for non-LSO frames. 1687 * Enable 512B burst length reads for buffer descriptors. 1688 */ 1689 CSR_WRITE_4(sc, ctrl_reg, 1690 CSR_READ_4(sc, ctrl_reg) | 1691 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 1692 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 1693 } 1694 1695 /* Turn on read DMA state machine */ 1696 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1697 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717) 1698 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 1699 if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 || 1700 sc->bnx_asicrev == BGE_ASICREV_BCM5785 || 1701 sc->bnx_asicrev == BGE_ASICREV_BCM57780) { 1702 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1703 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1704 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1705 } 1706 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1707 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 1708 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 1709 BGE_RDMAMODE_H2BNC_VLAN_DET; 1710 /* 1711 * Allow multiple outstanding read requests from 1712 * non-LSO read DMA engine. 1713 */ 1714 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 1715 } 1716 if (sc->bnx_asicrev == BGE_ASICREV_BCM57766) 1717 val |= BGE_RDMAMODE_JMB_2K_MMRR; 1718 if (sc->bnx_flags & BNX_FLAG_TSO) 1719 val |= BGE_RDMAMODE_TSO4_ENABLE; 1720 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1721 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1722 DELAY(40); 1723 1724 /* Turn on RX data completion state machine */ 1725 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1726 1727 /* Turn on RX BD initiator state machine */ 1728 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1729 1730 /* Turn on RX data and RX BD initiator state machine */ 1731 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1732 1733 /* Turn on send BD completion state machine */ 1734 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1735 1736 /* Turn on send data completion state machine */ 1737 val = BGE_SDCMODE_ENABLE; 1738 if (sc->bnx_asicrev == BGE_ASICREV_BCM5761) 1739 val |= BGE_SDCMODE_CDELAY; 1740 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1741 1742 /* Turn on send data initiator state machine */ 1743 if (sc->bnx_flags & BNX_FLAG_TSO) { 1744 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 1745 BGE_SDIMODE_HW_LSO_PRE_DMA); 1746 } else { 1747 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1748 } 1749 1750 /* Turn on send BD initiator state machine */ 1751 val = BGE_SBDIMODE_ENABLE; 1752 if (sc->bnx_tx_ringcnt > 1) 1753 val |= BGE_SBDIMODE_MULTI_TXR; 1754 CSR_WRITE_4(sc, BGE_SBDI_MODE, val); 1755 1756 /* Turn on send BD selector state machine */ 1757 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1758 1759 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1760 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1761 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1762 1763 /* ack/clear link change events */ 1764 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1765 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1766 BGE_MACSTAT_LINK_CHANGED); 1767 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1768 1769 /* 1770 * Enable attention when the link has changed state for 1771 * devices that use auto polling. 1772 */ 1773 if (sc->bnx_flags & BNX_FLAG_TBI) { 1774 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1775 } else { 1776 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 1777 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode); 1778 DELAY(80); 1779 } 1780 } 1781 1782 /* 1783 * Clear any pending link state attention. 1784 * Otherwise some link state change events may be lost until attention 1785 * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence. 1786 * It's not necessary on newer BCM chips - perhaps enabling link 1787 * state change attentions implies clearing pending attention. 1788 */ 1789 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1790 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1791 BGE_MACSTAT_LINK_CHANGED); 1792 1793 /* Enable link state change attentions. */ 1794 BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1795 1796 return(0); 1797 } 1798 1799 /* 1800 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1801 * against our list and return its name if we find a match. Note 1802 * that since the Broadcom controller contains VPD support, we 1803 * can get the device name string from the controller itself instead 1804 * of the compiled-in string. This is a little slow, but it guarantees 1805 * we'll always announce the right product name. 1806 */ 1807 static int 1808 bnx_probe(device_t dev) 1809 { 1810 const struct bnx_type *t; 1811 uint16_t product, vendor; 1812 1813 if (!pci_is_pcie(dev)) 1814 return ENXIO; 1815 1816 product = pci_get_device(dev); 1817 vendor = pci_get_vendor(dev); 1818 1819 for (t = bnx_devs; t->bnx_name != NULL; t++) { 1820 if (vendor == t->bnx_vid && product == t->bnx_did) 1821 break; 1822 } 1823 if (t->bnx_name == NULL) 1824 return ENXIO; 1825 1826 device_set_desc(dev, t->bnx_name); 1827 return 0; 1828 } 1829 1830 static int 1831 bnx_attach(device_t dev) 1832 { 1833 struct ifnet *ifp; 1834 struct bnx_softc *sc; 1835 struct bnx_rx_std_ring *std; 1836 struct sysctl_ctx_list *ctx; 1837 struct sysctl_oid_list *tree; 1838 uint32_t hwcfg = 0; 1839 int error = 0, rid, capmask, i, std_cpuid, std_cpuid_def; 1840 uint8_t ether_addr[ETHER_ADDR_LEN]; 1841 uint16_t product; 1842 uintptr_t mii_priv = 0; 1843 #if defined(BNX_TSO_DEBUG) || defined(BNX_RSS_DEBUG) || defined(BNX_TSS_DEBUG) 1844 char desc[32]; 1845 #endif 1846 1847 sc = device_get_softc(dev); 1848 sc->bnx_dev = dev; 1849 callout_init_mp(&sc->bnx_tick_timer); 1850 lwkt_serialize_init(&sc->bnx_jslot_serializer); 1851 lwkt_serialize_init(&sc->bnx_main_serialize); 1852 1853 /* Always setup interrupt mailboxes */ 1854 for (i = 0; i < BNX_INTR_MAX; ++i) { 1855 callout_init_mp(&sc->bnx_intr_data[i].bnx_intr_timer); 1856 sc->bnx_intr_data[i].bnx_sc = sc; 1857 sc->bnx_intr_data[i].bnx_intr_mbx = BGE_MBX_IRQ0_LO + (i * 8); 1858 sc->bnx_intr_data[i].bnx_intr_rid = -1; 1859 sc->bnx_intr_data[i].bnx_intr_cpuid = -1; 1860 } 1861 1862 sc->bnx_func_addr = pci_get_function(dev); 1863 product = pci_get_device(dev); 1864 1865 #ifndef BURN_BRIDGES 1866 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1867 uint32_t irq, mem; 1868 1869 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1870 mem = pci_read_config(dev, BGE_PCI_BAR0, 4); 1871 1872 device_printf(dev, "chip is in D%d power mode " 1873 "-- setting to D0\n", pci_get_powerstate(dev)); 1874 1875 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1876 1877 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1878 pci_write_config(dev, BGE_PCI_BAR0, mem, 4); 1879 } 1880 #endif /* !BURN_BRIDGE */ 1881 1882 /* 1883 * Map control/status registers. 1884 */ 1885 pci_enable_busmaster(dev); 1886 1887 rid = BGE_PCI_BAR0; 1888 sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1889 RF_ACTIVE); 1890 1891 if (sc->bnx_res == NULL) { 1892 device_printf(dev, "couldn't map memory\n"); 1893 return ENXIO; 1894 } 1895 1896 sc->bnx_btag = rman_get_bustag(sc->bnx_res); 1897 sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res); 1898 1899 /* Save various chip information */ 1900 sc->bnx_chipid = 1901 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 1902 BGE_PCIMISCCTL_ASICREV_SHIFT; 1903 if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) { 1904 /* All chips having dedicated ASICREV register have CPMU */ 1905 sc->bnx_flags |= BNX_FLAG_CPMU; 1906 1907 switch (product) { 1908 case PCI_PRODUCT_BROADCOM_BCM5717: 1909 case PCI_PRODUCT_BROADCOM_BCM5717C: 1910 case PCI_PRODUCT_BROADCOM_BCM5718: 1911 case PCI_PRODUCT_BROADCOM_BCM5719: 1912 case PCI_PRODUCT_BROADCOM_BCM5720_ALT: 1913 case PCI_PRODUCT_BROADCOM_BCM5725: 1914 case PCI_PRODUCT_BROADCOM_BCM5727: 1915 case PCI_PRODUCT_BROADCOM_BCM5762: 1916 sc->bnx_chipid = pci_read_config(dev, 1917 BGE_PCI_GEN2_PRODID_ASICREV, 4); 1918 break; 1919 1920 case PCI_PRODUCT_BROADCOM_BCM57761: 1921 case PCI_PRODUCT_BROADCOM_BCM57762: 1922 case PCI_PRODUCT_BROADCOM_BCM57765: 1923 case PCI_PRODUCT_BROADCOM_BCM57766: 1924 case PCI_PRODUCT_BROADCOM_BCM57781: 1925 case PCI_PRODUCT_BROADCOM_BCM57782: 1926 case PCI_PRODUCT_BROADCOM_BCM57785: 1927 case PCI_PRODUCT_BROADCOM_BCM57786: 1928 case PCI_PRODUCT_BROADCOM_BCM57791: 1929 case PCI_PRODUCT_BROADCOM_BCM57795: 1930 sc->bnx_chipid = pci_read_config(dev, 1931 BGE_PCI_GEN15_PRODID_ASICREV, 4); 1932 break; 1933 1934 default: 1935 sc->bnx_chipid = pci_read_config(dev, 1936 BGE_PCI_PRODID_ASICREV, 4); 1937 break; 1938 } 1939 } 1940 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0) 1941 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0; 1942 1943 sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid); 1944 sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid); 1945 1946 switch (sc->bnx_asicrev) { 1947 case BGE_ASICREV_BCM5717: 1948 case BGE_ASICREV_BCM5719: 1949 case BGE_ASICREV_BCM5720: 1950 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS; 1951 break; 1952 1953 case BGE_ASICREV_BCM5762: 1954 sc->bnx_flags |= BNX_FLAG_57765_PLUS; 1955 break; 1956 1957 case BGE_ASICREV_BCM57765: 1958 case BGE_ASICREV_BCM57766: 1959 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS; 1960 break; 1961 } 1962 1963 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 || 1964 sc->bnx_asicrev == BGE_ASICREV_BCM5719 || 1965 sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 1966 sc->bnx_asicrev == BGE_ASICREV_BCM5762) 1967 sc->bnx_flags |= BNX_FLAG_APE; 1968 1969 sc->bnx_flags |= BNX_FLAG_TSO; 1970 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 && 1971 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0) 1972 sc->bnx_flags &= ~BNX_FLAG_TSO; 1973 1974 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 || 1975 BNX_IS_57765_FAMILY(sc)) { 1976 /* 1977 * All BCM57785 and BCM5718 families chips have a bug that 1978 * under certain situation interrupt will not be enabled 1979 * even if status tag is written to interrupt mailbox. 1980 * 1981 * While BCM5719 and BCM5720 have a hardware workaround 1982 * which could fix the above bug. 1983 * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in 1984 * bnx_chipinit(). 1985 * 1986 * For the rest of the chips in these two families, we will 1987 * have to poll the status block at high rate (10ms currently) 1988 * to check whether the interrupt is hosed or not. 1989 * See bnx_check_intr_*() for details. 1990 */ 1991 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG; 1992 } 1993 1994 sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev); 1995 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 || 1996 sc->bnx_asicrev == BGE_ASICREV_BCM5720) 1997 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048); 1998 else 1999 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096); 2000 device_printf(dev, "CHIP ID 0x%08x; " 2001 "ASIC REV 0x%02x; CHIP REV 0x%02x\n", 2002 sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev); 2003 2004 /* 2005 * Set various PHY quirk flags. 2006 */ 2007 2008 capmask = MII_CAPMASK_DEFAULT; 2009 if (product == PCI_PRODUCT_BROADCOM_BCM57791 || 2010 product == PCI_PRODUCT_BROADCOM_BCM57795) { 2011 /* 10/100 only */ 2012 capmask &= ~BMSR_EXTSTAT; 2013 } 2014 2015 mii_priv |= BRGPHY_FLAG_WIRESPEED; 2016 if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0) 2017 mii_priv |= BRGPHY_FLAG_5762_A0; 2018 2019 /* 2020 * Chips with APE need BAR2 access for APE registers/memory. 2021 */ 2022 if (sc->bnx_flags & BNX_FLAG_APE) { 2023 uint32_t pcistate; 2024 2025 rid = PCIR_BAR(2); 2026 sc->bnx_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2027 RF_ACTIVE); 2028 if (sc->bnx_res2 == NULL) { 2029 device_printf(dev, "couldn't map BAR2 memory\n"); 2030 error = ENXIO; 2031 goto fail; 2032 } 2033 2034 /* Enable APE register/memory access by host driver. */ 2035 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2036 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 2037 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 2038 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 2039 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 2040 2041 bnx_ape_lock_init(sc); 2042 bnx_ape_read_fw_ver(sc); 2043 } 2044 2045 /* Initialize if_name earlier, so if_printf could be used */ 2046 ifp = &sc->arpcom.ac_if; 2047 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2048 2049 /* 2050 * Try to reset the chip. 2051 */ 2052 bnx_sig_pre_reset(sc, BNX_RESET_SHUTDOWN); 2053 bnx_reset(sc); 2054 bnx_sig_post_reset(sc, BNX_RESET_SHUTDOWN); 2055 2056 if (bnx_chipinit(sc)) { 2057 device_printf(dev, "chip initialization failed\n"); 2058 error = ENXIO; 2059 goto fail; 2060 } 2061 2062 /* 2063 * Get station address 2064 */ 2065 error = bnx_get_eaddr(sc, ether_addr); 2066 if (error) { 2067 device_printf(dev, "failed to read station address\n"); 2068 goto fail; 2069 } 2070 2071 /* Setup RX/TX and interrupt count */ 2072 bnx_setup_ring_cnt(sc); 2073 2074 if ((sc->bnx_rx_retcnt == 1 && sc->bnx_tx_ringcnt == 1) || 2075 (sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt > 1)) { 2076 /* 2077 * The RX ring and the corresponding TX ring processing 2078 * should be on the same CPU, since they share the same 2079 * status block. 2080 */ 2081 sc->bnx_flags |= BNX_FLAG_RXTX_BUNDLE; 2082 if (bootverbose) 2083 device_printf(dev, "RX/TX bundle\n"); 2084 if (sc->bnx_tx_ringcnt > 1) { 2085 /* 2086 * Multiple TX rings do not share status block 2087 * with link status, so link status will have 2088 * to save its own status_tag. 2089 */ 2090 sc->bnx_flags |= BNX_FLAG_STATUS_HASTAG; 2091 if (bootverbose) 2092 device_printf(dev, "status needs tag\n"); 2093 } 2094 } else { 2095 KKASSERT(sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt == 1); 2096 if (bootverbose) 2097 device_printf(dev, "RX/TX not bundled\n"); 2098 } 2099 2100 error = bnx_dma_alloc(dev); 2101 if (error) 2102 goto fail; 2103 2104 /* 2105 * Allocate interrupt 2106 */ 2107 error = bnx_alloc_intr(sc); 2108 if (error) 2109 goto fail; 2110 2111 /* Setup serializers */ 2112 bnx_setup_serialize(sc); 2113 2114 /* Set default tuneable values. */ 2115 sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF; 2116 sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF; 2117 sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF; 2118 sc->bnx_rx_coal_bds_poll = sc->bnx_rx_ret_ring[0].bnx_rx_cntmax; 2119 sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF; 2120 sc->bnx_tx_coal_bds_poll = BNX_TX_COAL_BDS_POLL_DEF; 2121 sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF; 2122 sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF; 2123 2124 /* Set up ifnet structure */ 2125 ifp->if_softc = sc; 2126 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2127 ifp->if_ioctl = bnx_ioctl; 2128 ifp->if_start = bnx_start; 2129 #ifdef IFPOLL_ENABLE 2130 ifp->if_npoll = bnx_npoll; 2131 #endif 2132 ifp->if_init = bnx_init; 2133 ifp->if_serialize = bnx_serialize; 2134 ifp->if_deserialize = bnx_deserialize; 2135 ifp->if_tryserialize = bnx_tryserialize; 2136 #ifdef INVARIANTS 2137 ifp->if_serialize_assert = bnx_serialize_assert; 2138 #endif 2139 ifp->if_mtu = ETHERMTU; 2140 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2141 2142 ifp->if_capabilities |= IFCAP_HWCSUM; 2143 ifp->if_hwassist = BNX_CSUM_FEATURES; 2144 if (sc->bnx_flags & BNX_FLAG_TSO) { 2145 ifp->if_capabilities |= IFCAP_TSO; 2146 ifp->if_hwassist |= CSUM_TSO; 2147 } 2148 if (BNX_RSS_ENABLED(sc)) 2149 ifp->if_capabilities |= IFCAP_RSS; 2150 ifp->if_capenable = ifp->if_capabilities; 2151 2152 ifp->if_nmbclusters = BGE_STD_RX_RING_CNT; 2153 2154 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 2155 ifq_set_ready(&ifp->if_snd); 2156 ifq_set_subq_cnt(&ifp->if_snd, sc->bnx_tx_ringcnt); 2157 2158 if (sc->bnx_tx_ringcnt > 1) { 2159 ifp->if_mapsubq = ifq_mapsubq_modulo; 2160 ifq_set_subq_divisor(&ifp->if_snd, sc->bnx_tx_ringcnt); 2161 } 2162 2163 /* 2164 * Figure out what sort of media we have by checking the 2165 * hardware config word in the first 32k of NIC internal memory, 2166 * or fall back to examining the EEPROM if necessary. 2167 * Note: on some BCM5700 cards, this value appears to be unset. 2168 * If that's the case, we have to rely on identifying the NIC 2169 * by its PCI subsystem ID, as we do below for the SysKonnect 2170 * SK-9D41. 2171 */ 2172 if (bnx_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 2173 hwcfg = bnx_readmem_ind(sc, BGE_SRAM_DATA_CFG); 2174 } else { 2175 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2176 sizeof(hwcfg))) { 2177 device_printf(dev, "failed to read EEPROM\n"); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 hwcfg = ntohl(hwcfg); 2182 } 2183 2184 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2185 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 || 2186 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2187 sc->bnx_flags |= BNX_FLAG_TBI; 2188 2189 /* Setup MI MODE */ 2190 if (sc->bnx_flags & BNX_FLAG_CPMU) 2191 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST; 2192 else 2193 sc->bnx_mi_mode = BGE_MIMODE_BASE; 2194 2195 /* Setup link status update stuffs */ 2196 if (sc->bnx_flags & BNX_FLAG_TBI) { 2197 sc->bnx_link_upd = bnx_tbi_link_upd; 2198 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED; 2199 } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) { 2200 sc->bnx_link_upd = bnx_autopoll_link_upd; 2201 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED; 2202 } else { 2203 sc->bnx_link_upd = bnx_copper_link_upd; 2204 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED; 2205 } 2206 2207 /* Set default PHY address */ 2208 sc->bnx_phyno = 1; 2209 2210 /* 2211 * PHY address mapping for various devices. 2212 * 2213 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2214 * ---------+-------+-------+-------+-------+ 2215 * BCM57XX | 1 | X | X | X | 2216 * BCM5717 | 1 | 8 | 2 | 9 | 2217 * BCM5719 | 1 | 8 | 2 | 9 | 2218 * BCM5720 | 1 | 8 | 2 | 9 | 2219 * 2220 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2221 * ---------+-------+-------+-------+-------+ 2222 * BCM57XX | X | X | X | X | 2223 * BCM5717 | X | X | X | X | 2224 * BCM5719 | 3 | 10 | 4 | 11 | 2225 * BCM5720 | X | X | X | X | 2226 * 2227 * Other addresses may respond but they are not 2228 * IEEE compliant PHYs and should be ignored. 2229 */ 2230 if (BNX_IS_5717_PLUS(sc)) { 2231 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) { 2232 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 2233 BGE_SGDIGSTS_IS_SERDES) 2234 sc->bnx_phyno = sc->bnx_func_addr + 8; 2235 else 2236 sc->bnx_phyno = sc->bnx_func_addr + 1; 2237 } else { 2238 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2239 BGE_CPMU_PHY_STRAP_IS_SERDES) 2240 sc->bnx_phyno = sc->bnx_func_addr + 8; 2241 else 2242 sc->bnx_phyno = sc->bnx_func_addr + 1; 2243 } 2244 } 2245 2246 if (sc->bnx_flags & BNX_FLAG_TBI) { 2247 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK, 2248 bnx_ifmedia_upd, bnx_ifmedia_sts); 2249 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2250 ifmedia_add(&sc->bnx_ifmedia, 2251 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2252 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2253 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO); 2254 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media; 2255 } else { 2256 struct mii_probe_args mii_args; 2257 2258 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts); 2259 mii_args.mii_probemask = 1 << sc->bnx_phyno; 2260 mii_args.mii_capmask = capmask; 2261 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY; 2262 mii_args.mii_priv = mii_priv; 2263 2264 error = mii_probe(dev, &sc->bnx_miibus, &mii_args); 2265 if (error) { 2266 device_printf(dev, "MII without any PHY!\n"); 2267 goto fail; 2268 } 2269 } 2270 2271 ctx = device_get_sysctl_ctx(sc->bnx_dev); 2272 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bnx_dev)); 2273 2274 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2275 "rx_rings", CTLFLAG_RD, &sc->bnx_rx_retcnt, 0, "# of RX rings"); 2276 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2277 "tx_rings", CTLFLAG_RD, &sc->bnx_tx_ringcnt, 0, "# of TX rings"); 2278 2279 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_coal_ticks", 2280 CTLTYPE_INT | CTLFLAG_RW, 2281 sc, 0, bnx_sysctl_rx_coal_ticks, "I", 2282 "Receive coalescing ticks (usec)."); 2283 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_coal_ticks", 2284 CTLTYPE_INT | CTLFLAG_RW, 2285 sc, 0, bnx_sysctl_tx_coal_ticks, "I", 2286 "Transmit coalescing ticks (usec)."); 2287 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_coal_bds", 2288 CTLTYPE_INT | CTLFLAG_RW, 2289 sc, 0, bnx_sysctl_rx_coal_bds, "I", 2290 "Receive max coalesced BD count."); 2291 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_coal_bds_poll", 2292 CTLTYPE_INT | CTLFLAG_RW, 2293 sc, 0, bnx_sysctl_rx_coal_bds_poll, "I", 2294 "Receive max coalesced BD count in polling."); 2295 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_coal_bds", 2296 CTLTYPE_INT | CTLFLAG_RW, 2297 sc, 0, bnx_sysctl_tx_coal_bds, "I", 2298 "Transmit max coalesced BD count."); 2299 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_coal_bds_poll", 2300 CTLTYPE_INT | CTLFLAG_RW, 2301 sc, 0, bnx_sysctl_tx_coal_bds_poll, "I", 2302 "Transmit max coalesced BD count in polling."); 2303 /* 2304 * A common design characteristic for many Broadcom 2305 * client controllers is that they only support a 2306 * single outstanding DMA read operation on the PCIe 2307 * bus. This means that it will take twice as long to 2308 * fetch a TX frame that is split into header and 2309 * payload buffers as it does to fetch a single, 2310 * contiguous TX frame (2 reads vs. 1 read). For these 2311 * controllers, coalescing buffers to reduce the number 2312 * of memory reads is effective way to get maximum 2313 * performance(about 940Mbps). Without collapsing TX 2314 * buffers the maximum TCP bulk transfer performance 2315 * is about 850Mbps. However forcing coalescing mbufs 2316 * consumes a lot of CPU cycles, so leave it off by 2317 * default. 2318 */ 2319 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2320 "force_defrag", CTLTYPE_INT | CTLFLAG_RW, 2321 sc, 0, bnx_sysctl_force_defrag, "I", 2322 "Force defragment on TX path"); 2323 2324 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2325 "tx_wreg", CTLTYPE_INT | CTLFLAG_RW, 2326 sc, 0, bnx_sysctl_tx_wreg, "I", 2327 "# of segments before writing to hardware register"); 2328 2329 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2330 "std_refill", CTLTYPE_INT | CTLFLAG_RW, 2331 sc, 0, bnx_sysctl_std_refill, "I", 2332 "# of packets received before scheduling standard refilling"); 2333 2334 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2335 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2336 sc, 0, bnx_sysctl_rx_coal_bds_int, "I", 2337 "Receive max coalesced BD count during interrupt."); 2338 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, 2339 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2340 sc, 0, bnx_sysctl_tx_coal_bds_int, "I", 2341 "Transmit max coalesced BD count during interrupt."); 2342 2343 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) { 2344 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_cpumap", 2345 CTLTYPE_OPAQUE | CTLFLAG_RD, 2346 sc->bnx_tx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 2347 "TX ring CPU map"); 2348 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_cpumap", 2349 CTLTYPE_OPAQUE | CTLFLAG_RD, 2350 sc->bnx_rx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 2351 "RX ring CPU map"); 2352 } else { 2353 #ifdef IFPOLL_ENABLE 2354 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "tx_poll_cpumap", 2355 CTLTYPE_OPAQUE | CTLFLAG_RD, 2356 sc->bnx_tx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 2357 "TX poll CPU map"); 2358 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rx_poll_cpumap", 2359 CTLTYPE_OPAQUE | CTLFLAG_RD, 2360 sc->bnx_rx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 2361 "RX poll CPU map"); 2362 #endif 2363 } 2364 2365 #ifdef BNX_RSS_DEBUG 2366 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2367 "std_refill_mask", CTLFLAG_RD, 2368 &sc->bnx_rx_std_ring.bnx_rx_std_refill, 0, ""); 2369 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2370 "std_used", CTLFLAG_RD, 2371 &sc->bnx_rx_std_ring.bnx_rx_std_used, 0, ""); 2372 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, 2373 "rss_debug", CTLFLAG_RW, &sc->bnx_rss_debug, 0, ""); 2374 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 2375 ksnprintf(desc, sizeof(desc), "rx_pkt%d", i); 2376 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2377 desc, CTLFLAG_RW, &sc->bnx_rx_ret_ring[i].bnx_rx_pkt, ""); 2378 2379 ksnprintf(desc, sizeof(desc), "rx_force_sched%d", i); 2380 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2381 desc, CTLFLAG_RW, 2382 &sc->bnx_rx_ret_ring[i].bnx_rx_force_sched, ""); 2383 } 2384 #endif 2385 #ifdef BNX_TSS_DEBUG 2386 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 2387 ksnprintf(desc, sizeof(desc), "tx_pkt%d", i); 2388 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2389 desc, CTLFLAG_RW, &sc->bnx_tx_ring[i].bnx_tx_pkt, ""); 2390 } 2391 #endif 2392 2393 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2394 "norxbds", CTLFLAG_RW, &sc->bnx_norxbds, ""); 2395 2396 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2397 "errors", CTLFLAG_RW, &sc->bnx_errors, ""); 2398 2399 #ifdef BNX_TSO_DEBUG 2400 for (i = 0; i < BNX_TSO_NSTATS; ++i) { 2401 ksnprintf(desc, sizeof(desc), "tso%d", i + 1); 2402 SYSCTL_ADD_ULONG(ctx, tree, OID_AUTO, 2403 desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], ""); 2404 } 2405 #endif 2406 2407 /* 2408 * Call MI attach routine. 2409 */ 2410 ether_ifattach(ifp, ether_addr, NULL); 2411 2412 /* Setup TX rings and subqueues */ 2413 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 2414 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i); 2415 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 2416 2417 ifsq_set_cpuid(ifsq, txr->bnx_tx_cpuid); 2418 ifsq_set_hw_serialize(ifsq, &txr->bnx_tx_serialize); 2419 ifsq_set_priv(ifsq, txr); 2420 txr->bnx_ifsq = ifsq; 2421 2422 ifsq_watchdog_init(&txr->bnx_tx_watchdog, ifsq, bnx_watchdog); 2423 2424 if (bootverbose) { 2425 device_printf(dev, "txr %d -> cpu%d\n", i, 2426 txr->bnx_tx_cpuid); 2427 } 2428 } 2429 2430 error = bnx_setup_intr(sc); 2431 if (error) { 2432 ether_ifdetach(ifp); 2433 goto fail; 2434 } 2435 bnx_set_tick_cpuid(sc, FALSE); 2436 2437 /* 2438 * Create RX standard ring refilling thread 2439 */ 2440 std_cpuid_def = if_ringmap_cpumap(sc->bnx_rx_rmap, 0); 2441 std_cpuid = device_getenv_int(dev, "std.cpuid", std_cpuid_def); 2442 if (std_cpuid < 0 || std_cpuid >= ncpus) { 2443 device_printf(dev, "invalid std.cpuid %d, use %d\n", 2444 std_cpuid, std_cpuid_def); 2445 std_cpuid = std_cpuid_def; 2446 } 2447 2448 std = &sc->bnx_rx_std_ring; 2449 lwkt_create(bnx_rx_std_refill_ithread, std, &std->bnx_rx_std_ithread, 2450 NULL, TDF_NOSTART | TDF_INTTHREAD, std_cpuid, 2451 "%s std", device_get_nameunit(dev)); 2452 lwkt_setpri(std->bnx_rx_std_ithread, TDPRI_INT_MED); 2453 std->bnx_rx_std_ithread->td_preemptable = lwkt_preempt; 2454 2455 return(0); 2456 fail: 2457 bnx_detach(dev); 2458 return(error); 2459 } 2460 2461 static int 2462 bnx_detach(device_t dev) 2463 { 2464 struct bnx_softc *sc = device_get_softc(dev); 2465 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring; 2466 2467 if (device_is_attached(dev)) { 2468 struct ifnet *ifp = &sc->arpcom.ac_if; 2469 2470 ifnet_serialize_all(ifp); 2471 bnx_stop(sc); 2472 bnx_teardown_intr(sc, sc->bnx_intr_cnt); 2473 ifnet_deserialize_all(ifp); 2474 2475 ether_ifdetach(ifp); 2476 } 2477 2478 if (std->bnx_rx_std_ithread != NULL) { 2479 tsleep_interlock(std, 0); 2480 2481 if (std->bnx_rx_std_ithread->td_gd == mycpu) { 2482 bnx_rx_std_refill_stop(std); 2483 } else { 2484 lwkt_send_ipiq(std->bnx_rx_std_ithread->td_gd, 2485 bnx_rx_std_refill_stop, std); 2486 } 2487 2488 tsleep(std, PINTERLOCKED, "bnx_detach", 0); 2489 if (bootverbose) 2490 device_printf(dev, "RX std ithread exited\n"); 2491 2492 lwkt_synchronize_ipiqs("bnx_detach_ipiq"); 2493 } 2494 2495 if (sc->bnx_flags & BNX_FLAG_TBI) 2496 ifmedia_removeall(&sc->bnx_ifmedia); 2497 if (sc->bnx_miibus) 2498 device_delete_child(dev, sc->bnx_miibus); 2499 bus_generic_detach(dev); 2500 2501 bnx_free_intr(sc); 2502 2503 if (sc->bnx_msix_mem_res != NULL) { 2504 bus_release_resource(dev, SYS_RES_MEMORY, sc->bnx_msix_mem_rid, 2505 sc->bnx_msix_mem_res); 2506 } 2507 if (sc->bnx_res != NULL) { 2508 bus_release_resource(dev, SYS_RES_MEMORY, 2509 BGE_PCI_BAR0, sc->bnx_res); 2510 } 2511 if (sc->bnx_res2 != NULL) { 2512 bus_release_resource(dev, SYS_RES_MEMORY, 2513 PCIR_BAR(2), sc->bnx_res2); 2514 } 2515 2516 bnx_dma_free(sc); 2517 2518 if (sc->bnx_serialize != NULL) 2519 kfree(sc->bnx_serialize, M_DEVBUF); 2520 2521 if (sc->bnx_rx_rmap != NULL) 2522 if_ringmap_free(sc->bnx_rx_rmap); 2523 if (sc->bnx_tx_rmap != NULL) 2524 if_ringmap_free(sc->bnx_tx_rmap); 2525 2526 return 0; 2527 } 2528 2529 static void 2530 bnx_reset(struct bnx_softc *sc) 2531 { 2532 device_t dev = sc->bnx_dev; 2533 uint32_t cachesize, command, reset, mac_mode, mac_mode_mask; 2534 void (*write_op)(struct bnx_softc *, uint32_t, uint32_t); 2535 int i, val = 0; 2536 uint16_t devctl; 2537 2538 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 2539 if (sc->bnx_mfw_flags & BNX_MFW_ON_APE) 2540 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2541 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 2542 2543 write_op = bnx_writemem_direct; 2544 2545 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 2546 for (i = 0; i < 8000; i++) { 2547 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 2548 break; 2549 DELAY(20); 2550 } 2551 if (i == 8000) 2552 if_printf(&sc->arpcom.ac_if, "NVRAM lock timedout!\n"); 2553 2554 /* Take APE lock when performing reset. */ 2555 bnx_ape_lock(sc, BGE_APE_LOCK_GRC); 2556 2557 /* Save some important PCI state. */ 2558 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2559 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2560 2561 pci_write_config(dev, BGE_PCI_MISC_CTL, 2562 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2563 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2564 BGE_PCIMISCCTL_TAGGED_STATUS, 4); 2565 2566 /* Disable fastboot on controllers that support it. */ 2567 if (bootverbose) 2568 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n"); 2569 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2570 2571 /* 2572 * Write the magic number to SRAM at offset 0xB50. 2573 * When firmware finishes its initialization it will 2574 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 2575 */ 2576 bnx_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2577 2578 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2579 2580 /* XXX: Broadcom Linux driver. */ 2581 /* Force PCI-E 1.0a mode */ 2582 if (!BNX_IS_57765_PLUS(sc) && 2583 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) == 2584 (BGE_PCIE_PHY_TSTCTL_PSCRAM | 2585 BGE_PCIE_PHY_TSTCTL_PCIE10)) { 2586 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL, 2587 BGE_PCIE_PHY_TSTCTL_PSCRAM); 2588 } 2589 if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) { 2590 /* Prevent PCIE link training during global reset */ 2591 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2592 reset |= (1<<29); 2593 } 2594 2595 /* 2596 * Set GPHY Power Down Override to leave GPHY 2597 * powered up in D0 uninitialized. 2598 */ 2599 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) 2600 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 2601 2602 /* Issue global reset */ 2603 write_op(sc, BGE_MISC_CFG, reset); 2604 2605 DELAY(100 * 1000); 2606 2607 /* XXX: Broadcom Linux driver. */ 2608 if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) { 2609 uint32_t v; 2610 2611 DELAY(500000); /* wait for link training to complete */ 2612 v = pci_read_config(dev, 0xc4, 4); 2613 pci_write_config(dev, 0xc4, v | (1<<15), 4); 2614 } 2615 2616 devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2); 2617 2618 /* Disable no snoop and disable relaxed ordering. */ 2619 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP); 2620 2621 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */ 2622 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) { 2623 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK; 2624 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128; 2625 } 2626 2627 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2628 devctl, 2); 2629 2630 /* Clear error status. */ 2631 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS, 2632 PCIEM_DEVSTS_CORR_ERR | 2633 PCIEM_DEVSTS_NFATAL_ERR | 2634 PCIEM_DEVSTS_FATAL_ERR | 2635 PCIEM_DEVSTS_UNSUPP_REQ, 2); 2636 2637 /* Reset some of the PCI state that got zapped by reset */ 2638 pci_write_config(dev, BGE_PCI_MISC_CTL, 2639 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2640 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2641 BGE_PCIMISCCTL_TAGGED_STATUS, 4); 2642 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 2643 if (sc->bnx_mfw_flags & BNX_MFW_ON_APE) { 2644 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 2645 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 2646 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 2647 } 2648 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 2649 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2650 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2651 2652 /* Enable memory arbiter */ 2653 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2654 2655 /* Fix up byte swapping */ 2656 CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc)); 2657 2658 val = CSR_READ_4(sc, BGE_MAC_MODE); 2659 val = (val & ~mac_mode_mask) | mac_mode; 2660 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2661 DELAY(40); 2662 2663 bnx_ape_unlock(sc, BGE_APE_LOCK_GRC); 2664 2665 /* 2666 * Poll until we see the 1's complement of the magic number. 2667 * This indicates that the firmware initialization is complete. 2668 */ 2669 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) { 2670 val = bnx_readmem_ind(sc, BGE_SRAM_FW_MB); 2671 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2672 break; 2673 DELAY(10); 2674 } 2675 if (i == BNX_FIRMWARE_TIMEOUT) { 2676 if_printf(&sc->arpcom.ac_if, "firmware handshake " 2677 "timed out, found 0x%08x\n", val); 2678 } 2679 2680 /* BCM57765 A0 needs additional time before accessing. */ 2681 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) 2682 DELAY(10 * 1000); 2683 2684 /* 2685 * The 5704 in TBI mode apparently needs some special 2686 * adjustment to insure the SERDES drive level is set 2687 * to 1.2V. 2688 */ 2689 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 && 2690 (sc->bnx_flags & BNX_FLAG_TBI)) { 2691 uint32_t serdescfg; 2692 2693 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2694 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2695 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2696 } 2697 2698 CSR_WRITE_4(sc, BGE_MI_MODE, 2699 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL); 2700 DELAY(80); 2701 2702 /* XXX: Broadcom Linux driver. */ 2703 if (!BNX_IS_57765_PLUS(sc)) { 2704 uint32_t v; 2705 2706 /* Enable Data FIFO protection. */ 2707 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT); 2708 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25)); 2709 } 2710 2711 DELAY(10000); 2712 2713 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) { 2714 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 2715 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 2716 } 2717 } 2718 2719 /* 2720 * Frame reception handling. This is called if there's a frame 2721 * on the receive return list. 2722 * 2723 * Note: we have to be able to handle two possibilities here: 2724 * 1) the frame is from the jumbo recieve ring 2725 * 2) the frame is from the standard receive ring 2726 */ 2727 2728 static void 2729 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count) 2730 { 2731 struct bnx_softc *sc = ret->bnx_sc; 2732 struct bnx_rx_std_ring *std = ret->bnx_std; 2733 struct ifnet *ifp = &sc->arpcom.ac_if; 2734 int std_used = 0, cpuid = mycpuid; 2735 2736 while (ret->bnx_rx_saved_considx != rx_prod && count != 0) { 2737 struct pktinfo pi0, *pi = NULL; 2738 struct bge_rx_bd *cur_rx; 2739 struct bnx_rx_buf *rb; 2740 uint32_t rxidx; 2741 struct mbuf *m = NULL; 2742 uint16_t vlan_tag = 0; 2743 int have_tag = 0; 2744 2745 --count; 2746 2747 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx]; 2748 2749 rxidx = cur_rx->bge_idx; 2750 KKASSERT(rxidx < BGE_STD_RX_RING_CNT); 2751 2752 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT); 2753 #ifdef BNX_RSS_DEBUG 2754 ret->bnx_rx_pkt++; 2755 #endif 2756 2757 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2758 have_tag = 1; 2759 vlan_tag = cur_rx->bge_vlan_tag; 2760 } 2761 2762 if (ret->bnx_rx_cnt >= ret->bnx_rx_cntmax) { 2763 atomic_add_int(&std->bnx_rx_std_used, std_used); 2764 std_used = 0; 2765 2766 bnx_rx_std_refill_sched(ret, std); 2767 } 2768 ret->bnx_rx_cnt++; 2769 ++std_used; 2770 2771 rb = &std->bnx_rx_std_buf[rxidx]; 2772 m = rb->bnx_rx_mbuf; 2773 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2774 IFNET_STAT_INC(ifp, ierrors, 1); 2775 cpu_sfence(); 2776 rb->bnx_rx_refilled = 1; 2777 continue; 2778 } 2779 if (bnx_newbuf_std(ret, rxidx, 0)) { 2780 IFNET_STAT_INC(ifp, ierrors, 1); 2781 continue; 2782 } 2783 2784 IFNET_STAT_INC(ifp, ipackets, 1); 2785 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2786 m->m_pkthdr.rcvif = ifp; 2787 2788 if ((ifp->if_capenable & IFCAP_RXCSUM) && 2789 (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 2790 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 2791 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2792 if ((cur_rx->bge_error_flag & 2793 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 2794 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2795 } 2796 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2797 m->m_pkthdr.csum_data = 2798 cur_rx->bge_tcp_udp_csum; 2799 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2800 CSUM_PSEUDO_HDR; 2801 } 2802 } 2803 if (ifp->if_capenable & IFCAP_RSS) { 2804 pi = bnx_rss_info(&pi0, cur_rx); 2805 if (pi != NULL && 2806 (cur_rx->bge_flags & BGE_RXBDFLAG_RSS_HASH)) 2807 m_sethash(m, toeplitz_hash(cur_rx->bge_hash)); 2808 } 2809 2810 /* 2811 * If we received a packet with a vlan tag, pass it 2812 * to vlan_input() instead of ether_input(). 2813 */ 2814 if (have_tag) { 2815 m->m_flags |= M_VLANTAG; 2816 m->m_pkthdr.ether_vlantag = vlan_tag; 2817 } 2818 ifp->if_input(ifp, m, pi, cpuid); 2819 } 2820 bnx_writembx(sc, ret->bnx_rx_mbx, ret->bnx_rx_saved_considx); 2821 2822 if (std_used > 0) { 2823 int cur_std_used; 2824 2825 cur_std_used = atomic_fetchadd_int(&std->bnx_rx_std_used, 2826 std_used); 2827 if (cur_std_used + std_used >= (BGE_STD_RX_RING_CNT / 2)) { 2828 #ifdef BNX_RSS_DEBUG 2829 ret->bnx_rx_force_sched++; 2830 #endif 2831 bnx_rx_std_refill_sched(ret, std); 2832 } 2833 } 2834 } 2835 2836 static void 2837 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons) 2838 { 2839 struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if; 2840 2841 /* 2842 * Go through our tx ring and free mbufs for those 2843 * frames that have been sent. 2844 */ 2845 while (txr->bnx_tx_saved_considx != tx_cons) { 2846 struct bnx_tx_buf *buf; 2847 uint32_t idx = 0; 2848 2849 idx = txr->bnx_tx_saved_considx; 2850 buf = &txr->bnx_tx_buf[idx]; 2851 if (buf->bnx_tx_mbuf != NULL) { 2852 IFNET_STAT_INC(ifp, opackets, 1); 2853 #ifdef BNX_TSS_DEBUG 2854 txr->bnx_tx_pkt++; 2855 #endif 2856 bus_dmamap_unload(txr->bnx_tx_mtag, 2857 buf->bnx_tx_dmamap); 2858 m_freem(buf->bnx_tx_mbuf); 2859 buf->bnx_tx_mbuf = NULL; 2860 } 2861 txr->bnx_tx_cnt--; 2862 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT); 2863 } 2864 2865 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >= 2866 (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) 2867 ifsq_clr_oactive(txr->bnx_ifsq); 2868 2869 if (txr->bnx_tx_cnt == 0) 2870 txr->bnx_tx_watchdog.wd_timer = 0; 2871 2872 if (!ifsq_is_empty(txr->bnx_ifsq)) 2873 ifsq_devstart(txr->bnx_ifsq); 2874 } 2875 2876 static int 2877 bnx_handle_status(struct bnx_softc *sc) 2878 { 2879 uint32_t status; 2880 int handle = 0; 2881 2882 status = *sc->bnx_hw_status; 2883 2884 if (status & BGE_STATFLAG_ERROR) { 2885 uint32_t val; 2886 int reset = 0; 2887 2888 sc->bnx_errors++; 2889 2890 val = CSR_READ_4(sc, BGE_FLOW_ATTN); 2891 if (val & ~BGE_FLOWATTN_MB_LOWAT) { 2892 if_printf(&sc->arpcom.ac_if, 2893 "flow attn 0x%08x\n", val); 2894 reset = 1; 2895 } 2896 2897 val = CSR_READ_4(sc, BGE_MSI_STATUS); 2898 if (val & ~BGE_MSISTAT_MSI_PCI_REQ) { 2899 if_printf(&sc->arpcom.ac_if, 2900 "msi status 0x%08x\n", val); 2901 reset = 1; 2902 } 2903 2904 val = CSR_READ_4(sc, BGE_RDMA_STATUS); 2905 if (val) { 2906 if_printf(&sc->arpcom.ac_if, 2907 "rmda status 0x%08x\n", val); 2908 reset = 1; 2909 } 2910 2911 val = CSR_READ_4(sc, BGE_WDMA_STATUS); 2912 if (val) { 2913 if_printf(&sc->arpcom.ac_if, 2914 "wdma status 0x%08x\n", val); 2915 reset = 1; 2916 } 2917 2918 if (reset) { 2919 bnx_serialize_skipmain(sc); 2920 bnx_init(sc); 2921 bnx_deserialize_skipmain(sc); 2922 } 2923 handle = 1; 2924 } 2925 2926 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt) { 2927 if (bootverbose) { 2928 if_printf(&sc->arpcom.ac_if, "link change, " 2929 "link_evt %d\n", sc->bnx_link_evt); 2930 } 2931 bnx_link_poll(sc); 2932 handle = 1; 2933 } 2934 2935 return handle; 2936 } 2937 2938 #ifdef IFPOLL_ENABLE 2939 2940 static void 2941 bnx_npoll_rx(struct ifnet *ifp __unused, void *xret, int cycle) 2942 { 2943 struct bnx_rx_ret_ring *ret = xret; 2944 uint16_t rx_prod; 2945 2946 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize); 2947 2948 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag; 2949 cpu_lfence(); 2950 2951 rx_prod = *ret->bnx_rx_considx; 2952 if (ret->bnx_rx_saved_considx != rx_prod) 2953 bnx_rxeof(ret, rx_prod, cycle); 2954 } 2955 2956 static void 2957 bnx_npoll_tx_notag(struct ifnet *ifp __unused, void *xtxr, int cycle __unused) 2958 { 2959 struct bnx_tx_ring *txr = xtxr; 2960 uint16_t tx_cons; 2961 2962 ASSERT_SERIALIZED(&txr->bnx_tx_serialize); 2963 2964 tx_cons = *txr->bnx_tx_considx; 2965 if (txr->bnx_tx_saved_considx != tx_cons) 2966 bnx_txeof(txr, tx_cons); 2967 } 2968 2969 static void 2970 bnx_npoll_tx(struct ifnet *ifp, void *xtxr, int cycle) 2971 { 2972 struct bnx_tx_ring *txr = xtxr; 2973 2974 ASSERT_SERIALIZED(&txr->bnx_tx_serialize); 2975 2976 txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag; 2977 cpu_lfence(); 2978 bnx_npoll_tx_notag(ifp, txr, cycle); 2979 } 2980 2981 static void 2982 bnx_npoll_status_notag(struct ifnet *ifp) 2983 { 2984 struct bnx_softc *sc = ifp->if_softc; 2985 2986 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 2987 2988 if (bnx_handle_status(sc)) { 2989 /* 2990 * Status changes are handled; force the chip to 2991 * update the status block to reflect whether there 2992 * are more status changes or not, else staled status 2993 * changes are always seen. 2994 */ 2995 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 2996 } 2997 } 2998 2999 static void 3000 bnx_npoll_status(struct ifnet *ifp) 3001 { 3002 struct bnx_softc *sc = ifp->if_softc; 3003 3004 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 3005 3006 sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag; 3007 cpu_lfence(); 3008 bnx_npoll_status_notag(ifp); 3009 } 3010 3011 static void 3012 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3013 { 3014 struct bnx_softc *sc = ifp->if_softc; 3015 int i; 3016 3017 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3018 3019 if (info != NULL) { 3020 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) 3021 info->ifpi_status.status_func = bnx_npoll_status; 3022 else 3023 info->ifpi_status.status_func = bnx_npoll_status_notag; 3024 info->ifpi_status.serializer = &sc->bnx_main_serialize; 3025 3026 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3027 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 3028 int cpu = if_ringmap_cpumap(sc->bnx_tx_rmap, i); 3029 3030 KKASSERT(cpu < netisr_ncpus); 3031 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) { 3032 info->ifpi_tx[cpu].poll_func = 3033 bnx_npoll_tx_notag; 3034 } else { 3035 info->ifpi_tx[cpu].poll_func = bnx_npoll_tx; 3036 } 3037 info->ifpi_tx[cpu].arg = txr; 3038 info->ifpi_tx[cpu].serializer = &txr->bnx_tx_serialize; 3039 ifsq_set_cpuid(txr->bnx_ifsq, cpu); 3040 } 3041 3042 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 3043 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i]; 3044 int cpu = if_ringmap_cpumap(sc->bnx_rx_rmap, i); 3045 3046 KKASSERT(cpu < netisr_ncpus); 3047 info->ifpi_rx[cpu].poll_func = bnx_npoll_rx; 3048 info->ifpi_rx[cpu].arg = ret; 3049 info->ifpi_rx[cpu].serializer = 3050 &ret->bnx_rx_ret_serialize; 3051 } 3052 3053 if (ifp->if_flags & IFF_RUNNING) { 3054 bnx_disable_intr(sc); 3055 bnx_set_tick_cpuid(sc, TRUE); 3056 3057 sc->bnx_coal_chg = BNX_TX_COAL_BDS_CHG | 3058 BNX_RX_COAL_BDS_CHG; 3059 bnx_coal_change(sc); 3060 } 3061 } else { 3062 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3063 ifsq_set_cpuid(sc->bnx_tx_ring[i].bnx_ifsq, 3064 sc->bnx_tx_ring[i].bnx_tx_cpuid); 3065 } 3066 if (ifp->if_flags & IFF_RUNNING) { 3067 sc->bnx_coal_chg = BNX_TX_COAL_BDS_CHG | 3068 BNX_RX_COAL_BDS_CHG; 3069 bnx_coal_change(sc); 3070 3071 bnx_enable_intr(sc); 3072 bnx_set_tick_cpuid(sc, FALSE); 3073 } 3074 } 3075 } 3076 3077 #endif /* IFPOLL_ENABLE */ 3078 3079 static void 3080 bnx_intr_legacy(void *xsc) 3081 { 3082 struct bnx_softc *sc = xsc; 3083 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; 3084 3085 if (ret->bnx_saved_status_tag == *ret->bnx_hw_status_tag) { 3086 uint32_t val; 3087 3088 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4); 3089 if (val & BGE_PCISTAT_INTR_NOTACT) 3090 return; 3091 } 3092 3093 /* 3094 * NOTE: 3095 * Interrupt will have to be disabled if tagged status 3096 * is used, else interrupt will always be asserted on 3097 * certain chips (at least on BCM5750 AX/BX). 3098 */ 3099 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3100 3101 bnx_intr(sc); 3102 } 3103 3104 static void 3105 bnx_msi(void *xsc) 3106 { 3107 bnx_intr(xsc); 3108 } 3109 3110 static void 3111 bnx_intr(struct bnx_softc *sc) 3112 { 3113 struct ifnet *ifp = &sc->arpcom.ac_if; 3114 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; 3115 3116 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 3117 3118 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag; 3119 /* 3120 * Use a load fence to ensure that status_tag is saved 3121 * before rx_prod, tx_cons and status. 3122 */ 3123 cpu_lfence(); 3124 3125 bnx_handle_status(sc); 3126 3127 if (ifp->if_flags & IFF_RUNNING) { 3128 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; 3129 uint16_t rx_prod, tx_cons; 3130 3131 lwkt_serialize_enter(&ret->bnx_rx_ret_serialize); 3132 rx_prod = *ret->bnx_rx_considx; 3133 if (ret->bnx_rx_saved_considx != rx_prod) 3134 bnx_rxeof(ret, rx_prod, -1); 3135 lwkt_serialize_exit(&ret->bnx_rx_ret_serialize); 3136 3137 lwkt_serialize_enter(&txr->bnx_tx_serialize); 3138 tx_cons = *txr->bnx_tx_considx; 3139 if (txr->bnx_tx_saved_considx != tx_cons) 3140 bnx_txeof(txr, tx_cons); 3141 lwkt_serialize_exit(&txr->bnx_tx_serialize); 3142 } 3143 3144 bnx_writembx(sc, BGE_MBX_IRQ0_LO, ret->bnx_saved_status_tag << 24); 3145 } 3146 3147 static void 3148 bnx_msix_tx_status(void *xtxr) 3149 { 3150 struct bnx_tx_ring *txr = xtxr; 3151 struct bnx_softc *sc = txr->bnx_sc; 3152 struct ifnet *ifp = &sc->arpcom.ac_if; 3153 3154 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 3155 3156 txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag; 3157 /* 3158 * Use a load fence to ensure that status_tag is saved 3159 * before tx_cons and status. 3160 */ 3161 cpu_lfence(); 3162 3163 bnx_handle_status(sc); 3164 3165 if (ifp->if_flags & IFF_RUNNING) { 3166 uint16_t tx_cons; 3167 3168 lwkt_serialize_enter(&txr->bnx_tx_serialize); 3169 tx_cons = *txr->bnx_tx_considx; 3170 if (txr->bnx_tx_saved_considx != tx_cons) 3171 bnx_txeof(txr, tx_cons); 3172 lwkt_serialize_exit(&txr->bnx_tx_serialize); 3173 } 3174 3175 bnx_writembx(sc, BGE_MBX_IRQ0_LO, txr->bnx_saved_status_tag << 24); 3176 } 3177 3178 static void 3179 bnx_msix_rx(void *xret) 3180 { 3181 struct bnx_rx_ret_ring *ret = xret; 3182 uint16_t rx_prod; 3183 3184 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize); 3185 3186 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag; 3187 /* 3188 * Use a load fence to ensure that status_tag is saved 3189 * before rx_prod. 3190 */ 3191 cpu_lfence(); 3192 3193 rx_prod = *ret->bnx_rx_considx; 3194 if (ret->bnx_rx_saved_considx != rx_prod) 3195 bnx_rxeof(ret, rx_prod, -1); 3196 3197 bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx, 3198 ret->bnx_saved_status_tag << 24); 3199 } 3200 3201 static void 3202 bnx_msix_rxtx(void *xret) 3203 { 3204 struct bnx_rx_ret_ring *ret = xret; 3205 struct bnx_tx_ring *txr = ret->bnx_txr; 3206 uint16_t rx_prod, tx_cons; 3207 3208 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize); 3209 3210 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag; 3211 /* 3212 * Use a load fence to ensure that status_tag is saved 3213 * before rx_prod and tx_cons. 3214 */ 3215 cpu_lfence(); 3216 3217 rx_prod = *ret->bnx_rx_considx; 3218 if (ret->bnx_rx_saved_considx != rx_prod) 3219 bnx_rxeof(ret, rx_prod, -1); 3220 3221 lwkt_serialize_enter(&txr->bnx_tx_serialize); 3222 tx_cons = *txr->bnx_tx_considx; 3223 if (txr->bnx_tx_saved_considx != tx_cons) 3224 bnx_txeof(txr, tx_cons); 3225 lwkt_serialize_exit(&txr->bnx_tx_serialize); 3226 3227 bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx, 3228 ret->bnx_saved_status_tag << 24); 3229 } 3230 3231 static void 3232 bnx_msix_status(void *xsc) 3233 { 3234 struct bnx_softc *sc = xsc; 3235 3236 ASSERT_SERIALIZED(&sc->bnx_main_serialize); 3237 3238 sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag; 3239 /* 3240 * Use a load fence to ensure that status_tag is saved 3241 * before status. 3242 */ 3243 cpu_lfence(); 3244 3245 bnx_handle_status(sc); 3246 3247 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_saved_status_tag << 24); 3248 } 3249 3250 static void 3251 bnx_tick(void *xsc) 3252 { 3253 struct bnx_softc *sc = xsc; 3254 3255 lwkt_serialize_enter(&sc->bnx_main_serialize); 3256 3257 bnx_stats_update_regs(sc); 3258 3259 if (sc->bnx_flags & BNX_FLAG_TBI) { 3260 /* 3261 * Since in TBI mode auto-polling can't be used we should poll 3262 * link status manually. Here we register pending link event 3263 * and trigger interrupt. 3264 */ 3265 sc->bnx_link_evt++; 3266 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3267 } else if (!sc->bnx_link) { 3268 mii_tick(device_get_softc(sc->bnx_miibus)); 3269 } 3270 3271 callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc, 3272 sc->bnx_tick_cpuid); 3273 3274 lwkt_serialize_exit(&sc->bnx_main_serialize); 3275 } 3276 3277 static void 3278 bnx_stats_update_regs(struct bnx_softc *sc) 3279 { 3280 struct ifnet *ifp = &sc->arpcom.ac_if; 3281 struct bge_mac_stats_regs stats; 3282 uint32_t *s, val; 3283 int i; 3284 3285 s = (uint32_t *)&stats; 3286 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 3287 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 3288 s++; 3289 } 3290 3291 IFNET_STAT_SET(ifp, collisions, 3292 (stats.dot3StatsSingleCollisionFrames + 3293 stats.dot3StatsMultipleCollisionFrames + 3294 stats.dot3StatsExcessiveCollisions + 3295 stats.dot3StatsLateCollisions)); 3296 3297 val = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3298 sc->bnx_norxbds += val; 3299 } 3300 3301 /* 3302 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3303 * pointers to descriptors. 3304 */ 3305 static int 3306 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx, 3307 int *segs_used) 3308 { 3309 struct bge_tx_bd *d = NULL; 3310 uint16_t csum_flags = 0, vlan_tag = 0, mss = 0; 3311 bus_dma_segment_t segs[BNX_NSEG_NEW]; 3312 bus_dmamap_t map; 3313 int error, maxsegs, nsegs, idx, i; 3314 struct mbuf *m_head = *m_head0, *m_new; 3315 3316 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3317 #ifdef BNX_TSO_DEBUG 3318 int tso_nsegs; 3319 #endif 3320 3321 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags); 3322 if (error) 3323 return error; 3324 m_head = *m_head0; 3325 3326 #ifdef BNX_TSO_DEBUG 3327 tso_nsegs = (m_head->m_pkthdr.len / 3328 m_head->m_pkthdr.tso_segsz) - 1; 3329 if (tso_nsegs > (BNX_TSO_NSTATS - 1)) 3330 tso_nsegs = BNX_TSO_NSTATS - 1; 3331 else if (tso_nsegs < 0) 3332 tso_nsegs = 0; 3333 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++; 3334 #endif 3335 } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) { 3336 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3337 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3338 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3339 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3340 if (m_head->m_flags & M_LASTFRAG) 3341 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3342 else if (m_head->m_flags & M_FRAG) 3343 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3344 } 3345 if (m_head->m_flags & M_VLANTAG) { 3346 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 3347 vlan_tag = m_head->m_pkthdr.ether_vlantag; 3348 } 3349 3350 idx = *txidx; 3351 map = txr->bnx_tx_buf[idx].bnx_tx_dmamap; 3352 3353 maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD; 3354 KASSERT(maxsegs >= BNX_NSEG_SPARE, 3355 ("not enough segments %d", maxsegs)); 3356 3357 if (maxsegs > BNX_NSEG_NEW) 3358 maxsegs = BNX_NSEG_NEW; 3359 3360 /* 3361 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason. 3362 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN, 3363 * but when such padded frames employ the bge IP/TCP checksum 3364 * offload, the hardware checksum assist gives incorrect results 3365 * (possibly from incorporating its own padding into the UDP/TCP 3366 * checksum; who knows). If we pad such runts with zeros, the 3367 * onboard checksum comes out correct. 3368 */ 3369 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) && 3370 m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) { 3371 error = m_devpad(m_head, BNX_MIN_FRAMELEN); 3372 if (error) 3373 goto back; 3374 } 3375 3376 if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) && 3377 m_head->m_next != NULL) { 3378 m_new = bnx_defrag_shortdma(m_head); 3379 if (m_new == NULL) { 3380 error = ENOBUFS; 3381 goto back; 3382 } 3383 *m_head0 = m_head = m_new; 3384 } 3385 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3386 (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) && 3387 m_head->m_next != NULL) { 3388 /* 3389 * Forcefully defragment mbuf chain to overcome hardware 3390 * limitation which only support a single outstanding 3391 * DMA read operation. If it fails, keep moving on using 3392 * the original mbuf chain. 3393 */ 3394 m_new = m_defrag(m_head, M_NOWAIT); 3395 if (m_new != NULL) 3396 *m_head0 = m_head = m_new; 3397 } 3398 3399 error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map, 3400 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 3401 if (error) 3402 goto back; 3403 *segs_used += nsegs; 3404 3405 m_head = *m_head0; 3406 bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3407 3408 for (i = 0; ; i++) { 3409 d = &txr->bnx_tx_ring[idx]; 3410 3411 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3412 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3413 d->bge_len = segs[i].ds_len; 3414 d->bge_flags = csum_flags; 3415 d->bge_vlan_tag = vlan_tag; 3416 d->bge_mss = mss; 3417 3418 if (i == nsegs - 1) 3419 break; 3420 BNX_INC(idx, BGE_TX_RING_CNT); 3421 } 3422 /* Mark the last segment as end of packet... */ 3423 d->bge_flags |= BGE_TXBDFLAG_END; 3424 3425 /* 3426 * Insure that the map for this transmission is placed at 3427 * the array index of the last descriptor in this chain. 3428 */ 3429 txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap; 3430 txr->bnx_tx_buf[idx].bnx_tx_dmamap = map; 3431 txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head; 3432 txr->bnx_tx_cnt += nsegs; 3433 3434 BNX_INC(idx, BGE_TX_RING_CNT); 3435 *txidx = idx; 3436 back: 3437 if (error) { 3438 m_freem(*m_head0); 3439 *m_head0 = NULL; 3440 } 3441 return error; 3442 } 3443 3444 /* 3445 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3446 * to the mbuf data regions directly in the transmit descriptors. 3447 */ 3448 static void 3449 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 3450 { 3451 struct bnx_tx_ring *txr = ifsq_get_priv(ifsq); 3452 struct mbuf *m_head = NULL; 3453 uint32_t prodidx; 3454 int nsegs = 0; 3455 3456 KKASSERT(txr->bnx_ifsq == ifsq); 3457 ASSERT_SERIALIZED(&txr->bnx_tx_serialize); 3458 3459 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq)) 3460 return; 3461 3462 prodidx = txr->bnx_tx_prodidx; 3463 3464 while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) { 3465 /* 3466 * Sanity check: avoid coming within BGE_NSEG_RSVD 3467 * descriptors of the end of the ring. Also make 3468 * sure there are BGE_NSEG_SPARE descriptors for 3469 * jumbo buffers' or TSO segments' defragmentation. 3470 */ 3471 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) < 3472 (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) { 3473 ifsq_set_oactive(ifsq); 3474 break; 3475 } 3476 3477 m_head = ifsq_dequeue(ifsq); 3478 if (m_head == NULL) 3479 break; 3480 3481 /* 3482 * Pack the data into the transmit ring. If we 3483 * don't have room, set the OACTIVE flag and wait 3484 * for the NIC to drain the ring. 3485 */ 3486 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) { 3487 ifsq_set_oactive(ifsq); 3488 IFNET_STAT_INC(ifp, oerrors, 1); 3489 break; 3490 } 3491 3492 if (nsegs >= txr->bnx_tx_wreg) { 3493 /* Transmit */ 3494 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx); 3495 nsegs = 0; 3496 } 3497 3498 ETHER_BPF_MTAP(ifp, m_head); 3499 3500 /* 3501 * Set a timeout in case the chip goes out to lunch. 3502 */ 3503 txr->bnx_tx_watchdog.wd_timer = 5; 3504 } 3505 3506 if (nsegs > 0) { 3507 /* Transmit */ 3508 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx); 3509 } 3510 txr->bnx_tx_prodidx = prodidx; 3511 } 3512 3513 static void 3514 bnx_init(void *xsc) 3515 { 3516 struct bnx_softc *sc = xsc; 3517 struct ifnet *ifp = &sc->arpcom.ac_if; 3518 uint16_t *m; 3519 uint32_t mode; 3520 int i; 3521 boolean_t polling; 3522 3523 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3524 3525 /* Cancel pending I/O and flush buffers. */ 3526 bnx_stop(sc); 3527 3528 bnx_sig_pre_reset(sc, BNX_RESET_START); 3529 bnx_reset(sc); 3530 bnx_sig_post_reset(sc, BNX_RESET_START); 3531 3532 bnx_chipinit(sc); 3533 3534 /* 3535 * Init the various state machines, ring 3536 * control blocks and firmware. 3537 */ 3538 if (bnx_blockinit(sc)) { 3539 if_printf(ifp, "initialization failure\n"); 3540 bnx_stop(sc); 3541 return; 3542 } 3543 3544 /* Specify MTU. */ 3545 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3546 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN); 3547 3548 /* Load our MAC address. */ 3549 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 3550 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3551 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3552 3553 /* Enable or disable promiscuous mode as needed. */ 3554 bnx_setpromisc(sc); 3555 3556 /* Program multicast filter. */ 3557 bnx_setmulti(sc); 3558 3559 /* Init RX ring. */ 3560 if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) { 3561 if_printf(ifp, "RX ring initialization failed\n"); 3562 bnx_stop(sc); 3563 return; 3564 } 3565 3566 /* Init jumbo RX ring. */ 3567 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) { 3568 if (bnx_init_rx_ring_jumbo(sc)) { 3569 if_printf(ifp, "Jumbo RX ring initialization failed\n"); 3570 bnx_stop(sc); 3571 return; 3572 } 3573 } 3574 3575 /* Init our RX return ring index */ 3576 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 3577 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i]; 3578 3579 ret->bnx_rx_saved_considx = 0; 3580 ret->bnx_rx_cnt = 0; 3581 } 3582 3583 /* Init TX ring. */ 3584 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 3585 bnx_init_tx_ring(&sc->bnx_tx_ring[i]); 3586 3587 /* Enable TX MAC state machine lockup fix. */ 3588 mode = CSR_READ_4(sc, BGE_TX_MODE); 3589 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 3590 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 || 3591 sc->bnx_asicrev == BGE_ASICREV_BCM5762) { 3592 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 3593 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 3594 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 3595 } 3596 /* Turn on transmitter */ 3597 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 3598 DELAY(100); 3599 3600 /* Initialize RSS */ 3601 mode = BGE_RXMODE_ENABLE | BGE_RXMODE_IPV6_ENABLE; 3602 if (BNX_RSS_ENABLED(sc)) { 3603 bnx_init_rss(sc); 3604 mode |= BGE_RXMODE_RSS_ENABLE | 3605 BGE_RXMODE_RSS_HASH_MASK_BITS | 3606 BGE_RXMODE_RSS_IPV4_HASH | 3607 BGE_RXMODE_RSS_TCP_IPV4_HASH; 3608 } 3609 /* Turn on receiver */ 3610 BNX_SETBIT(sc, BGE_RX_MODE, mode); 3611 DELAY(10); 3612 3613 /* 3614 * Set the number of good frames to receive after RX MBUF 3615 * Low Watermark has been reached. After the RX MAC receives 3616 * this number of frames, it will drop subsequent incoming 3617 * frames until the MBUF High Watermark is reached. 3618 */ 3619 if (BNX_IS_57765_FAMILY(sc)) 3620 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 3621 else 3622 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3623 3624 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI || 3625 sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) { 3626 if (bootverbose) { 3627 if_printf(ifp, "MSI_MODE: %#x\n", 3628 CSR_READ_4(sc, BGE_MSI_MODE)); 3629 } 3630 } 3631 3632 /* Tell firmware we're alive. */ 3633 BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3634 3635 /* Enable host interrupts if polling(4) is not enabled. */ 3636 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4); 3637 3638 polling = FALSE; 3639 #ifdef IFPOLL_ENABLE 3640 if (ifp->if_flags & IFF_NPOLLING) 3641 polling = TRUE; 3642 #endif 3643 if (polling) 3644 bnx_disable_intr(sc); 3645 else 3646 bnx_enable_intr(sc); 3647 bnx_set_tick_cpuid(sc, polling); 3648 3649 ifp->if_flags |= IFF_RUNNING; 3650 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3651 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 3652 3653 ifsq_clr_oactive(txr->bnx_ifsq); 3654 ifsq_watchdog_start(&txr->bnx_tx_watchdog); 3655 } 3656 3657 bnx_ifmedia_upd(ifp); 3658 3659 callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc, 3660 sc->bnx_tick_cpuid); 3661 } 3662 3663 /* 3664 * Set media options. 3665 */ 3666 static int 3667 bnx_ifmedia_upd(struct ifnet *ifp) 3668 { 3669 struct bnx_softc *sc = ifp->if_softc; 3670 3671 /* If this is a 1000baseX NIC, enable the TBI port. */ 3672 if (sc->bnx_flags & BNX_FLAG_TBI) { 3673 struct ifmedia *ifm = &sc->bnx_ifmedia; 3674 3675 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3676 return(EINVAL); 3677 3678 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3679 case IFM_AUTO: 3680 break; 3681 3682 case IFM_1000_SX: 3683 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3684 BNX_CLRBIT(sc, BGE_MAC_MODE, 3685 BGE_MACMODE_HALF_DUPLEX); 3686 } else { 3687 BNX_SETBIT(sc, BGE_MAC_MODE, 3688 BGE_MACMODE_HALF_DUPLEX); 3689 } 3690 DELAY(40); 3691 break; 3692 default: 3693 return(EINVAL); 3694 } 3695 } else { 3696 struct mii_data *mii = device_get_softc(sc->bnx_miibus); 3697 3698 sc->bnx_link_evt++; 3699 sc->bnx_link = 0; 3700 if (mii->mii_instance) { 3701 struct mii_softc *miisc; 3702 3703 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3704 mii_phy_reset(miisc); 3705 } 3706 mii_mediachg(mii); 3707 3708 /* 3709 * Force an interrupt so that we will call bnx_link_upd 3710 * if needed and clear any pending link state attention. 3711 * Without this we are not getting any further interrupts 3712 * for link state changes and thus will not UP the link and 3713 * not be able to send in bnx_start. The only way to get 3714 * things working was to receive a packet and get an RX 3715 * intr. 3716 * 3717 * bnx_tick should help for fiber cards and we might not 3718 * need to do this here if BNX_FLAG_TBI is set but as 3719 * we poll for fiber anyway it should not harm. 3720 */ 3721 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3722 } 3723 return(0); 3724 } 3725 3726 /* 3727 * Report current media status. 3728 */ 3729 static void 3730 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3731 { 3732 struct bnx_softc *sc = ifp->if_softc; 3733 3734 if ((ifp->if_flags & IFF_RUNNING) == 0) 3735 return; 3736 3737 if (sc->bnx_flags & BNX_FLAG_TBI) { 3738 ifmr->ifm_status = IFM_AVALID; 3739 ifmr->ifm_active = IFM_ETHER; 3740 if (CSR_READ_4(sc, BGE_MAC_STS) & 3741 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3742 ifmr->ifm_status |= IFM_ACTIVE; 3743 } else { 3744 ifmr->ifm_active |= IFM_NONE; 3745 return; 3746 } 3747 3748 ifmr->ifm_active |= IFM_1000_SX; 3749 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3750 ifmr->ifm_active |= IFM_HDX; 3751 else 3752 ifmr->ifm_active |= IFM_FDX; 3753 } else { 3754 struct mii_data *mii = device_get_softc(sc->bnx_miibus); 3755 3756 mii_pollstat(mii); 3757 ifmr->ifm_active = mii->mii_media_active; 3758 ifmr->ifm_status = mii->mii_media_status; 3759 } 3760 } 3761 3762 static int 3763 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3764 { 3765 struct bnx_softc *sc = ifp->if_softc; 3766 struct ifreq *ifr = (struct ifreq *)data; 3767 int mask, error = 0; 3768 3769 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3770 3771 switch (command) { 3772 case SIOCSIFMTU: 3773 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) || 3774 (BNX_IS_JUMBO_CAPABLE(sc) && 3775 ifr->ifr_mtu > BNX_JUMBO_MTU)) { 3776 error = EINVAL; 3777 } else if (ifp->if_mtu != ifr->ifr_mtu) { 3778 ifp->if_mtu = ifr->ifr_mtu; 3779 if (ifp->if_flags & IFF_RUNNING) 3780 bnx_init(sc); 3781 } 3782 break; 3783 case SIOCSIFFLAGS: 3784 if (ifp->if_flags & IFF_UP) { 3785 if (ifp->if_flags & IFF_RUNNING) { 3786 mask = ifp->if_flags ^ sc->bnx_if_flags; 3787 3788 /* 3789 * If only the state of the PROMISC flag 3790 * changed, then just use the 'set promisc 3791 * mode' command instead of reinitializing 3792 * the entire NIC. Doing a full re-init 3793 * means reloading the firmware and waiting 3794 * for it to start up, which may take a 3795 * second or two. Similarly for ALLMULTI. 3796 */ 3797 if (mask & IFF_PROMISC) 3798 bnx_setpromisc(sc); 3799 if (mask & IFF_ALLMULTI) 3800 bnx_setmulti(sc); 3801 } else { 3802 bnx_init(sc); 3803 } 3804 } else if (ifp->if_flags & IFF_RUNNING) { 3805 bnx_stop(sc); 3806 } 3807 sc->bnx_if_flags = ifp->if_flags; 3808 break; 3809 case SIOCADDMULTI: 3810 case SIOCDELMULTI: 3811 if (ifp->if_flags & IFF_RUNNING) 3812 bnx_setmulti(sc); 3813 break; 3814 case SIOCSIFMEDIA: 3815 case SIOCGIFMEDIA: 3816 if (sc->bnx_flags & BNX_FLAG_TBI) { 3817 error = ifmedia_ioctl(ifp, ifr, 3818 &sc->bnx_ifmedia, command); 3819 } else { 3820 struct mii_data *mii; 3821 3822 mii = device_get_softc(sc->bnx_miibus); 3823 error = ifmedia_ioctl(ifp, ifr, 3824 &mii->mii_media, command); 3825 } 3826 break; 3827 case SIOCSIFCAP: 3828 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3829 if (mask & IFCAP_HWCSUM) { 3830 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 3831 if (ifp->if_capenable & IFCAP_TXCSUM) 3832 ifp->if_hwassist |= BNX_CSUM_FEATURES; 3833 else 3834 ifp->if_hwassist &= ~BNX_CSUM_FEATURES; 3835 } 3836 if (mask & IFCAP_TSO) { 3837 ifp->if_capenable ^= (mask & IFCAP_TSO); 3838 if (ifp->if_capenable & IFCAP_TSO) 3839 ifp->if_hwassist |= CSUM_TSO; 3840 else 3841 ifp->if_hwassist &= ~CSUM_TSO; 3842 } 3843 if (mask & IFCAP_RSS) 3844 ifp->if_capenable ^= IFCAP_RSS; 3845 break; 3846 default: 3847 error = ether_ioctl(ifp, command, data); 3848 break; 3849 } 3850 return error; 3851 } 3852 3853 static void 3854 bnx_watchdog(struct ifaltq_subque *ifsq) 3855 { 3856 struct ifnet *ifp = ifsq_get_ifp(ifsq); 3857 struct bnx_softc *sc = ifp->if_softc; 3858 int i; 3859 3860 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3861 3862 if_printf(ifp, "watchdog timeout -- resetting\n"); 3863 3864 bnx_init(sc); 3865 3866 IFNET_STAT_INC(ifp, oerrors, 1); 3867 3868 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 3869 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq); 3870 } 3871 3872 /* 3873 * Stop the adapter and free any mbufs allocated to the 3874 * RX and TX lists. 3875 */ 3876 static void 3877 bnx_stop(struct bnx_softc *sc) 3878 { 3879 struct ifnet *ifp = &sc->arpcom.ac_if; 3880 int i; 3881 3882 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3883 3884 callout_stop(&sc->bnx_tick_timer); 3885 3886 /* Disable host interrupts. */ 3887 bnx_disable_intr(sc); 3888 3889 /* 3890 * Tell firmware we're shutting down. 3891 */ 3892 bnx_sig_pre_reset(sc, BNX_RESET_SHUTDOWN); 3893 3894 /* 3895 * Disable all of the receiver blocks 3896 */ 3897 bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3898 bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3899 bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3900 bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3901 bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3902 bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3903 3904 /* 3905 * Disable all of the transmit blocks 3906 */ 3907 bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3908 bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3909 bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3910 bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3911 bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3912 bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3913 3914 /* 3915 * Shut down all of the memory managers and related 3916 * state machines. 3917 */ 3918 bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3919 bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3920 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3921 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3922 3923 bnx_reset(sc); 3924 bnx_sig_post_reset(sc, BNX_RESET_SHUTDOWN); 3925 3926 /* 3927 * Tell firmware we're shutting down. 3928 */ 3929 BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3930 3931 /* Free the RX lists. */ 3932 bnx_free_rx_ring_std(&sc->bnx_rx_std_ring); 3933 3934 /* Free jumbo RX list. */ 3935 if (BNX_IS_JUMBO_CAPABLE(sc)) 3936 bnx_free_rx_ring_jumbo(sc); 3937 3938 /* Free TX buffers. */ 3939 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3940 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 3941 3942 txr->bnx_saved_status_tag = 0; 3943 bnx_free_tx_ring(txr); 3944 } 3945 3946 /* Clear saved status tag */ 3947 for (i = 0; i < sc->bnx_rx_retcnt; ++i) 3948 sc->bnx_rx_ret_ring[i].bnx_saved_status_tag = 0; 3949 3950 sc->bnx_link = 0; 3951 sc->bnx_coal_chg = 0; 3952 3953 ifp->if_flags &= ~IFF_RUNNING; 3954 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 3955 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 3956 3957 ifsq_clr_oactive(txr->bnx_ifsq); 3958 ifsq_watchdog_stop(&txr->bnx_tx_watchdog); 3959 } 3960 } 3961 3962 /* 3963 * Stop all chip I/O so that the kernel's probe routines don't 3964 * get confused by errant DMAs when rebooting. 3965 */ 3966 static void 3967 bnx_shutdown(device_t dev) 3968 { 3969 struct bnx_softc *sc = device_get_softc(dev); 3970 struct ifnet *ifp = &sc->arpcom.ac_if; 3971 3972 ifnet_serialize_all(ifp); 3973 bnx_stop(sc); 3974 ifnet_deserialize_all(ifp); 3975 } 3976 3977 static int 3978 bnx_suspend(device_t dev) 3979 { 3980 struct bnx_softc *sc = device_get_softc(dev); 3981 struct ifnet *ifp = &sc->arpcom.ac_if; 3982 3983 ifnet_serialize_all(ifp); 3984 bnx_stop(sc); 3985 ifnet_deserialize_all(ifp); 3986 3987 return 0; 3988 } 3989 3990 static int 3991 bnx_resume(device_t dev) 3992 { 3993 struct bnx_softc *sc = device_get_softc(dev); 3994 struct ifnet *ifp = &sc->arpcom.ac_if; 3995 3996 ifnet_serialize_all(ifp); 3997 3998 if (ifp->if_flags & IFF_UP) { 3999 int i; 4000 4001 bnx_init(sc); 4002 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 4003 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq); 4004 } 4005 4006 ifnet_deserialize_all(ifp); 4007 4008 return 0; 4009 } 4010 4011 static void 4012 bnx_setpromisc(struct bnx_softc *sc) 4013 { 4014 struct ifnet *ifp = &sc->arpcom.ac_if; 4015 4016 if (ifp->if_flags & IFF_PROMISC) 4017 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4018 else 4019 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4020 } 4021 4022 static void 4023 bnx_dma_free(struct bnx_softc *sc) 4024 { 4025 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring; 4026 int i; 4027 4028 /* Destroy RX return rings */ 4029 if (sc->bnx_rx_ret_ring != NULL) { 4030 for (i = 0; i < sc->bnx_rx_retcnt; ++i) 4031 bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]); 4032 kfree(sc->bnx_rx_ret_ring, M_DEVBUF); 4033 } 4034 4035 /* Destroy RX mbuf DMA stuffs. */ 4036 if (std->bnx_rx_mtag != NULL) { 4037 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4038 KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL); 4039 bus_dmamap_destroy(std->bnx_rx_mtag, 4040 std->bnx_rx_std_buf[i].bnx_rx_dmamap); 4041 } 4042 bus_dma_tag_destroy(std->bnx_rx_mtag); 4043 } 4044 4045 /* Destroy standard RX ring */ 4046 bnx_dma_block_free(std->bnx_rx_std_ring_tag, 4047 std->bnx_rx_std_ring_map, std->bnx_rx_std_ring); 4048 4049 /* Destroy TX rings */ 4050 if (sc->bnx_tx_ring != NULL) { 4051 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 4052 bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]); 4053 kfree(sc->bnx_tx_ring, M_DEVBUF); 4054 } 4055 4056 if (BNX_IS_JUMBO_CAPABLE(sc)) 4057 bnx_free_jumbo_mem(sc); 4058 4059 /* Destroy status blocks */ 4060 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4061 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4062 4063 bnx_dma_block_free(intr->bnx_status_tag, 4064 intr->bnx_status_map, intr->bnx_status_block); 4065 } 4066 4067 /* Destroy the parent tag */ 4068 if (sc->bnx_cdata.bnx_parent_tag != NULL) 4069 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag); 4070 } 4071 4072 static int 4073 bnx_dma_alloc(device_t dev) 4074 { 4075 struct bnx_softc *sc = device_get_softc(dev); 4076 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring; 4077 int i, error, mbx; 4078 4079 /* 4080 * Allocate the parent bus DMA tag appropriate for PCI. 4081 * 4082 * All of the NetExtreme/NetLink controllers have 4GB boundary 4083 * DMA bug. 4084 * Whenever an address crosses a multiple of the 4GB boundary 4085 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 4086 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 4087 * state machine will lockup and cause the device to hang. 4088 */ 4089 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G, 4090 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 4091 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 4092 0, &sc->bnx_cdata.bnx_parent_tag); 4093 if (error) { 4094 device_printf(dev, "could not create parent DMA tag\n"); 4095 return error; 4096 } 4097 4098 /* 4099 * Create DMA stuffs for status blocks. 4100 */ 4101 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4102 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4103 4104 error = bnx_dma_block_alloc(sc, 4105 __VM_CACHELINE_ALIGN(BGE_STATUS_BLK_SZ), 4106 &intr->bnx_status_tag, &intr->bnx_status_map, 4107 (void *)&intr->bnx_status_block, 4108 &intr->bnx_status_block_paddr); 4109 if (error) { 4110 device_printf(dev, 4111 "could not create %dth status block\n", i); 4112 return error; 4113 } 4114 } 4115 sc->bnx_hw_status = &sc->bnx_intr_data[0].bnx_status_block->bge_status; 4116 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) { 4117 sc->bnx_hw_status_tag = 4118 &sc->bnx_intr_data[0].bnx_status_block->bge_status_tag; 4119 } 4120 4121 /* 4122 * Create DMA tag and maps for RX mbufs. 4123 */ 4124 std->bnx_sc = sc; 4125 lwkt_serialize_init(&std->bnx_rx_std_serialize); 4126 error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0, 4127 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4128 NULL, NULL, MCLBYTES, 1, MCLBYTES, 4129 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag); 4130 if (error) { 4131 device_printf(dev, "could not create RX mbuf DMA tag\n"); 4132 return error; 4133 } 4134 4135 for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) { 4136 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK, 4137 &std->bnx_rx_std_buf[i].bnx_rx_dmamap); 4138 if (error) { 4139 int j; 4140 4141 for (j = 0; j < i; ++j) { 4142 bus_dmamap_destroy(std->bnx_rx_mtag, 4143 std->bnx_rx_std_buf[j].bnx_rx_dmamap); 4144 } 4145 bus_dma_tag_destroy(std->bnx_rx_mtag); 4146 std->bnx_rx_mtag = NULL; 4147 4148 device_printf(dev, 4149 "could not create %dth RX mbuf DMA map\n", i); 4150 return error; 4151 } 4152 } 4153 4154 /* 4155 * Create DMA stuffs for standard RX ring. 4156 */ 4157 error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ, 4158 &std->bnx_rx_std_ring_tag, 4159 &std->bnx_rx_std_ring_map, 4160 (void *)&std->bnx_rx_std_ring, 4161 &std->bnx_rx_std_ring_paddr); 4162 if (error) { 4163 device_printf(dev, "could not create std RX ring\n"); 4164 return error; 4165 } 4166 4167 /* 4168 * Create RX return rings 4169 */ 4170 mbx = BGE_MBX_RX_CONS0_LO; 4171 sc->bnx_rx_ret_ring = kmalloc_cachealign( 4172 sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, M_DEVBUF, 4173 M_WAITOK | M_ZERO); 4174 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 4175 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i]; 4176 struct bnx_intr_data *intr; 4177 4178 ret->bnx_sc = sc; 4179 ret->bnx_std = std; 4180 ret->bnx_rx_mbx = mbx; 4181 ret->bnx_rx_cntmax = (BGE_STD_RX_RING_CNT / 4) / 4182 sc->bnx_rx_retcnt; 4183 ret->bnx_rx_mask = 1 << i; 4184 4185 if (!BNX_RSS_ENABLED(sc)) { 4186 intr = &sc->bnx_intr_data[0]; 4187 } else { 4188 KKASSERT(i + 1 < sc->bnx_intr_cnt); 4189 intr = &sc->bnx_intr_data[i + 1]; 4190 } 4191 4192 if (i == 0) { 4193 ret->bnx_rx_considx = 4194 &intr->bnx_status_block->bge_idx[0].bge_rx_prod_idx; 4195 } else if (i == 1) { 4196 ret->bnx_rx_considx = 4197 &intr->bnx_status_block->bge_rx_jumbo_cons_idx; 4198 } else if (i == 2) { 4199 ret->bnx_rx_considx = 4200 &intr->bnx_status_block->bge_rsvd1; 4201 } else if (i == 3) { 4202 ret->bnx_rx_considx = 4203 &intr->bnx_status_block->bge_rx_mini_cons_idx; 4204 } else { 4205 panic("unknown RX return ring %d\n", i); 4206 } 4207 ret->bnx_hw_status_tag = 4208 &intr->bnx_status_block->bge_status_tag; 4209 4210 error = bnx_create_rx_ret_ring(ret); 4211 if (error) { 4212 device_printf(dev, 4213 "could not create %dth RX ret ring\n", i); 4214 return error; 4215 } 4216 mbx += 8; 4217 } 4218 4219 /* 4220 * Create TX rings 4221 */ 4222 sc->bnx_tx_ring = kmalloc_cachealign( 4223 sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF, 4224 M_WAITOK | M_ZERO); 4225 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 4226 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i]; 4227 struct bnx_intr_data *intr; 4228 4229 txr->bnx_sc = sc; 4230 txr->bnx_tx_mbx = bnx_tx_mailbox[i]; 4231 4232 if (sc->bnx_tx_ringcnt == 1) { 4233 intr = &sc->bnx_intr_data[0]; 4234 } else { 4235 KKASSERT(i + 1 < sc->bnx_intr_cnt); 4236 intr = &sc->bnx_intr_data[i + 1]; 4237 } 4238 4239 if ((sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) == 0) { 4240 txr->bnx_hw_status_tag = 4241 &intr->bnx_status_block->bge_status_tag; 4242 } 4243 txr->bnx_tx_considx = 4244 &intr->bnx_status_block->bge_idx[0].bge_tx_cons_idx; 4245 4246 error = bnx_create_tx_ring(txr); 4247 if (error) { 4248 device_printf(dev, 4249 "could not create %dth TX ring\n", i); 4250 return error; 4251 } 4252 } 4253 4254 /* 4255 * Create jumbo buffer pool. 4256 */ 4257 if (BNX_IS_JUMBO_CAPABLE(sc)) { 4258 error = bnx_alloc_jumbo_mem(sc); 4259 if (error) { 4260 device_printf(dev, 4261 "could not create jumbo buffer pool\n"); 4262 return error; 4263 } 4264 } 4265 4266 return 0; 4267 } 4268 4269 static int 4270 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag, 4271 bus_dmamap_t *map, void **addr, bus_addr_t *paddr) 4272 { 4273 bus_dmamem_t dmem; 4274 int error; 4275 4276 error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0, 4277 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4278 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 4279 if (error) 4280 return error; 4281 4282 *tag = dmem.dmem_tag; 4283 *map = dmem.dmem_map; 4284 *addr = dmem.dmem_addr; 4285 *paddr = dmem.dmem_busaddr; 4286 4287 return 0; 4288 } 4289 4290 static void 4291 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr) 4292 { 4293 if (tag != NULL) { 4294 bus_dmamap_unload(tag, map); 4295 bus_dmamem_free(tag, addr, map); 4296 bus_dma_tag_destroy(tag); 4297 } 4298 } 4299 4300 static void 4301 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status) 4302 { 4303 struct ifnet *ifp = &sc->arpcom.ac_if; 4304 4305 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE) 4306 4307 /* 4308 * Sometimes PCS encoding errors are detected in 4309 * TBI mode (on fiber NICs), and for some reason 4310 * the chip will signal them as link changes. 4311 * If we get a link change event, but the 'PCS 4312 * encoding error' bit in the MAC status register 4313 * is set, don't bother doing a link check. 4314 * This avoids spurious "gigabit link up" messages 4315 * that sometimes appear on fiber NICs during 4316 * periods of heavy traffic. 4317 */ 4318 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4319 if (!sc->bnx_link) { 4320 sc->bnx_link++; 4321 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) { 4322 BNX_CLRBIT(sc, BGE_MAC_MODE, 4323 BGE_MACMODE_TBI_SEND_CFGS); 4324 DELAY(40); 4325 } 4326 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4327 4328 if (bootverbose) 4329 if_printf(ifp, "link UP\n"); 4330 4331 ifp->if_link_state = LINK_STATE_UP; 4332 if_link_state_change(ifp); 4333 } 4334 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) { 4335 if (sc->bnx_link) { 4336 sc->bnx_link = 0; 4337 4338 if (bootverbose) 4339 if_printf(ifp, "link DOWN\n"); 4340 4341 ifp->if_link_state = LINK_STATE_DOWN; 4342 if_link_state_change(ifp); 4343 } 4344 } 4345 4346 #undef PCS_ENCODE_ERR 4347 4348 /* Clear the attention. */ 4349 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4350 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4351 BGE_MACSTAT_LINK_CHANGED); 4352 } 4353 4354 static void 4355 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused) 4356 { 4357 struct ifnet *ifp = &sc->arpcom.ac_if; 4358 struct mii_data *mii = device_get_softc(sc->bnx_miibus); 4359 4360 mii_pollstat(mii); 4361 bnx_miibus_statchg(sc->bnx_dev); 4362 4363 if (bootverbose) { 4364 if (sc->bnx_link) 4365 if_printf(ifp, "link UP\n"); 4366 else 4367 if_printf(ifp, "link DOWN\n"); 4368 } 4369 4370 /* Clear the attention. */ 4371 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4372 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4373 BGE_MACSTAT_LINK_CHANGED); 4374 } 4375 4376 static void 4377 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused) 4378 { 4379 struct ifnet *ifp = &sc->arpcom.ac_if; 4380 struct mii_data *mii = device_get_softc(sc->bnx_miibus); 4381 4382 mii_pollstat(mii); 4383 4384 if (!sc->bnx_link && 4385 (mii->mii_media_status & IFM_ACTIVE) && 4386 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4387 sc->bnx_link++; 4388 if (bootverbose) 4389 if_printf(ifp, "link UP\n"); 4390 } else if (sc->bnx_link && 4391 (!(mii->mii_media_status & IFM_ACTIVE) || 4392 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4393 sc->bnx_link = 0; 4394 if (bootverbose) 4395 if_printf(ifp, "link DOWN\n"); 4396 } 4397 4398 /* Clear the attention. */ 4399 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4400 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4401 BGE_MACSTAT_LINK_CHANGED); 4402 } 4403 4404 static int 4405 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS) 4406 { 4407 struct bnx_softc *sc = arg1; 4408 4409 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4410 &sc->bnx_rx_coal_ticks, 4411 BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX, 4412 BNX_RX_COAL_TICKS_CHG); 4413 } 4414 4415 static int 4416 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS) 4417 { 4418 struct bnx_softc *sc = arg1; 4419 4420 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4421 &sc->bnx_tx_coal_ticks, 4422 BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX, 4423 BNX_TX_COAL_TICKS_CHG); 4424 } 4425 4426 static int 4427 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS) 4428 { 4429 struct bnx_softc *sc = arg1; 4430 4431 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4432 &sc->bnx_rx_coal_bds, 4433 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX, 4434 BNX_RX_COAL_BDS_CHG); 4435 } 4436 4437 static int 4438 bnx_sysctl_rx_coal_bds_poll(SYSCTL_HANDLER_ARGS) 4439 { 4440 struct bnx_softc *sc = arg1; 4441 4442 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4443 &sc->bnx_rx_coal_bds_poll, 4444 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX, 4445 BNX_RX_COAL_BDS_CHG); 4446 } 4447 4448 static int 4449 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS) 4450 { 4451 struct bnx_softc *sc = arg1; 4452 4453 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4454 &sc->bnx_tx_coal_bds, 4455 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX, 4456 BNX_TX_COAL_BDS_CHG); 4457 } 4458 4459 static int 4460 bnx_sysctl_tx_coal_bds_poll(SYSCTL_HANDLER_ARGS) 4461 { 4462 struct bnx_softc *sc = arg1; 4463 4464 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4465 &sc->bnx_tx_coal_bds_poll, 4466 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX, 4467 BNX_TX_COAL_BDS_CHG); 4468 } 4469 4470 static int 4471 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4472 { 4473 struct bnx_softc *sc = arg1; 4474 4475 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4476 &sc->bnx_rx_coal_bds_int, 4477 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX, 4478 BNX_RX_COAL_BDS_INT_CHG); 4479 } 4480 4481 static int 4482 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4483 { 4484 struct bnx_softc *sc = arg1; 4485 4486 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req, 4487 &sc->bnx_tx_coal_bds_int, 4488 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX, 4489 BNX_TX_COAL_BDS_INT_CHG); 4490 } 4491 4492 static int 4493 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal, 4494 int coal_min, int coal_max, uint32_t coal_chg_mask) 4495 { 4496 struct bnx_softc *sc = arg1; 4497 struct ifnet *ifp = &sc->arpcom.ac_if; 4498 int error = 0, v; 4499 4500 ifnet_serialize_all(ifp); 4501 4502 v = *coal; 4503 error = sysctl_handle_int(oidp, &v, 0, req); 4504 if (!error && req->newptr != NULL) { 4505 if (v < coal_min || v > coal_max) { 4506 error = EINVAL; 4507 } else { 4508 *coal = v; 4509 sc->bnx_coal_chg |= coal_chg_mask; 4510 4511 /* Commit changes */ 4512 bnx_coal_change(sc); 4513 } 4514 } 4515 4516 ifnet_deserialize_all(ifp); 4517 return error; 4518 } 4519 4520 static void 4521 bnx_coal_change(struct bnx_softc *sc) 4522 { 4523 struct ifnet *ifp = &sc->arpcom.ac_if; 4524 int i; 4525 4526 ASSERT_IFNET_SERIALIZED_ALL(ifp); 4527 4528 if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) { 4529 if (sc->bnx_rx_retcnt == 1) { 4530 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 4531 sc->bnx_rx_coal_ticks); 4532 i = 0; 4533 } else { 4534 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 0); 4535 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 4536 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS + 4537 (i * BGE_VEC_COALSET_SIZE), 4538 sc->bnx_rx_coal_ticks); 4539 } 4540 } 4541 for (; i < BNX_INTR_MAX - 1; ++i) { 4542 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS + 4543 (i * BGE_VEC_COALSET_SIZE), 0); 4544 } 4545 if (bootverbose) { 4546 if_printf(ifp, "rx_coal_ticks -> %u\n", 4547 sc->bnx_rx_coal_ticks); 4548 } 4549 } 4550 4551 if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) { 4552 if (sc->bnx_tx_ringcnt == 1) { 4553 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 4554 sc->bnx_tx_coal_ticks); 4555 i = 0; 4556 } else { 4557 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 0); 4558 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 4559 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS + 4560 (i * BGE_VEC_COALSET_SIZE), 4561 sc->bnx_tx_coal_ticks); 4562 } 4563 } 4564 for (; i < BNX_INTR_MAX - 1; ++i) { 4565 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS + 4566 (i * BGE_VEC_COALSET_SIZE), 0); 4567 } 4568 if (bootverbose) { 4569 if_printf(ifp, "tx_coal_ticks -> %u\n", 4570 sc->bnx_tx_coal_ticks); 4571 } 4572 } 4573 4574 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) { 4575 uint32_t rx_coal_bds; 4576 4577 if (ifp->if_flags & IFF_NPOLLING) 4578 rx_coal_bds = sc->bnx_rx_coal_bds_poll; 4579 else 4580 rx_coal_bds = sc->bnx_rx_coal_bds; 4581 4582 if (sc->bnx_rx_retcnt == 1) { 4583 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_coal_bds); 4584 i = 0; 4585 } else { 4586 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 0); 4587 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 4588 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS + 4589 (i * BGE_VEC_COALSET_SIZE), rx_coal_bds); 4590 } 4591 } 4592 for (; i < BNX_INTR_MAX - 1; ++i) { 4593 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS + 4594 (i * BGE_VEC_COALSET_SIZE), 0); 4595 } 4596 if (bootverbose) { 4597 if_printf(ifp, "%srx_coal_bds -> %u\n", 4598 (ifp->if_flags & IFF_NPOLLING) ? "polling " : "", 4599 rx_coal_bds); 4600 } 4601 } 4602 4603 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) { 4604 uint32_t tx_coal_bds; 4605 4606 if (ifp->if_flags & IFF_NPOLLING) 4607 tx_coal_bds = sc->bnx_tx_coal_bds_poll; 4608 else 4609 tx_coal_bds = sc->bnx_tx_coal_bds; 4610 4611 if (sc->bnx_tx_ringcnt == 1) { 4612 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, tx_coal_bds); 4613 i = 0; 4614 } else { 4615 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 0); 4616 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 4617 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS + 4618 (i * BGE_VEC_COALSET_SIZE), tx_coal_bds); 4619 } 4620 } 4621 for (; i < BNX_INTR_MAX - 1; ++i) { 4622 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS + 4623 (i * BGE_VEC_COALSET_SIZE), 0); 4624 } 4625 if (bootverbose) { 4626 if_printf(ifp, "%stx_coal_bds -> %u\n", 4627 (ifp->if_flags & IFF_NPOLLING) ? "polling " : "", 4628 tx_coal_bds); 4629 } 4630 } 4631 4632 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) { 4633 if (sc->bnx_rx_retcnt == 1) { 4634 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 4635 sc->bnx_rx_coal_bds_int); 4636 i = 0; 4637 } else { 4638 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 4639 for (i = 0; i < sc->bnx_rx_retcnt; ++i) { 4640 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT + 4641 (i * BGE_VEC_COALSET_SIZE), 4642 sc->bnx_rx_coal_bds_int); 4643 } 4644 } 4645 for (; i < BNX_INTR_MAX - 1; ++i) { 4646 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT + 4647 (i * BGE_VEC_COALSET_SIZE), 0); 4648 } 4649 if (bootverbose) { 4650 if_printf(ifp, "rx_coal_bds_int -> %u\n", 4651 sc->bnx_rx_coal_bds_int); 4652 } 4653 } 4654 4655 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) { 4656 if (sc->bnx_tx_ringcnt == 1) { 4657 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 4658 sc->bnx_tx_coal_bds_int); 4659 i = 0; 4660 } else { 4661 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 4662 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 4663 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT + 4664 (i * BGE_VEC_COALSET_SIZE), 4665 sc->bnx_tx_coal_bds_int); 4666 } 4667 } 4668 for (; i < BNX_INTR_MAX - 1; ++i) { 4669 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT + 4670 (i * BGE_VEC_COALSET_SIZE), 0); 4671 } 4672 if (bootverbose) { 4673 if_printf(ifp, "tx_coal_bds_int -> %u\n", 4674 sc->bnx_tx_coal_bds_int); 4675 } 4676 } 4677 4678 sc->bnx_coal_chg = 0; 4679 } 4680 4681 static void 4682 bnx_check_intr_rxtx(void *xintr) 4683 { 4684 struct bnx_intr_data *intr = xintr; 4685 struct bnx_rx_ret_ring *ret; 4686 struct bnx_tx_ring *txr; 4687 struct ifnet *ifp; 4688 4689 lwkt_serialize_enter(intr->bnx_intr_serialize); 4690 4691 KKASSERT(mycpuid == intr->bnx_intr_cpuid); 4692 4693 ifp = &intr->bnx_sc->arpcom.ac_if; 4694 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) { 4695 lwkt_serialize_exit(intr->bnx_intr_serialize); 4696 return; 4697 } 4698 4699 txr = intr->bnx_txr; 4700 ret = intr->bnx_ret; 4701 4702 if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx || 4703 *txr->bnx_tx_considx != txr->bnx_tx_saved_considx) { 4704 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx && 4705 intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) { 4706 if (!intr->bnx_intr_maylose) { 4707 intr->bnx_intr_maylose = TRUE; 4708 goto done; 4709 } 4710 if (bootverbose) 4711 if_printf(ifp, "lost interrupt\n"); 4712 intr->bnx_intr_func(intr->bnx_intr_arg); 4713 } 4714 } 4715 intr->bnx_intr_maylose = FALSE; 4716 intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx; 4717 intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx; 4718 4719 done: 4720 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL, 4721 intr->bnx_intr_check, intr); 4722 lwkt_serialize_exit(intr->bnx_intr_serialize); 4723 } 4724 4725 static void 4726 bnx_check_intr_tx(void *xintr) 4727 { 4728 struct bnx_intr_data *intr = xintr; 4729 struct bnx_tx_ring *txr; 4730 struct ifnet *ifp; 4731 4732 lwkt_serialize_enter(intr->bnx_intr_serialize); 4733 4734 KKASSERT(mycpuid == intr->bnx_intr_cpuid); 4735 4736 ifp = &intr->bnx_sc->arpcom.ac_if; 4737 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) { 4738 lwkt_serialize_exit(intr->bnx_intr_serialize); 4739 return; 4740 } 4741 4742 txr = intr->bnx_txr; 4743 4744 if (*txr->bnx_tx_considx != txr->bnx_tx_saved_considx) { 4745 if (intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) { 4746 if (!intr->bnx_intr_maylose) { 4747 intr->bnx_intr_maylose = TRUE; 4748 goto done; 4749 } 4750 if (bootverbose) 4751 if_printf(ifp, "lost interrupt\n"); 4752 intr->bnx_intr_func(intr->bnx_intr_arg); 4753 } 4754 } 4755 intr->bnx_intr_maylose = FALSE; 4756 intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx; 4757 4758 done: 4759 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL, 4760 intr->bnx_intr_check, intr); 4761 lwkt_serialize_exit(intr->bnx_intr_serialize); 4762 } 4763 4764 static void 4765 bnx_check_intr_rx(void *xintr) 4766 { 4767 struct bnx_intr_data *intr = xintr; 4768 struct bnx_rx_ret_ring *ret; 4769 struct ifnet *ifp; 4770 4771 lwkt_serialize_enter(intr->bnx_intr_serialize); 4772 4773 KKASSERT(mycpuid == intr->bnx_intr_cpuid); 4774 4775 ifp = &intr->bnx_sc->arpcom.ac_if; 4776 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) { 4777 lwkt_serialize_exit(intr->bnx_intr_serialize); 4778 return; 4779 } 4780 4781 ret = intr->bnx_ret; 4782 4783 if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx) { 4784 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx) { 4785 if (!intr->bnx_intr_maylose) { 4786 intr->bnx_intr_maylose = TRUE; 4787 goto done; 4788 } 4789 if (bootverbose) 4790 if_printf(ifp, "lost interrupt\n"); 4791 intr->bnx_intr_func(intr->bnx_intr_arg); 4792 } 4793 } 4794 intr->bnx_intr_maylose = FALSE; 4795 intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx; 4796 4797 done: 4798 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL, 4799 intr->bnx_intr_check, intr); 4800 lwkt_serialize_exit(intr->bnx_intr_serialize); 4801 } 4802 4803 static void 4804 bnx_enable_intr(struct bnx_softc *sc) 4805 { 4806 struct ifnet *ifp = &sc->arpcom.ac_if; 4807 int i; 4808 4809 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4810 lwkt_serialize_handler_enable( 4811 sc->bnx_intr_data[i].bnx_intr_serialize); 4812 } 4813 4814 /* 4815 * Enable interrupt. 4816 */ 4817 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4818 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4819 4820 bnx_writembx(sc, intr->bnx_intr_mbx, 4821 (*intr->bnx_saved_status_tag) << 24); 4822 /* XXX Linux driver */ 4823 bnx_writembx(sc, intr->bnx_intr_mbx, 4824 (*intr->bnx_saved_status_tag) << 24); 4825 } 4826 4827 /* 4828 * Unmask the interrupt when we stop polling. 4829 */ 4830 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, 4831 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4832 4833 /* 4834 * Trigger another interrupt, since above writing 4835 * to interrupt mailbox0 may acknowledge pending 4836 * interrupt. 4837 */ 4838 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4839 4840 if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) { 4841 if (bootverbose) 4842 if_printf(ifp, "status tag bug workaround\n"); 4843 4844 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4845 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4846 4847 if (intr->bnx_intr_check == NULL) 4848 continue; 4849 intr->bnx_intr_maylose = FALSE; 4850 intr->bnx_rx_check_considx = 0; 4851 intr->bnx_tx_check_considx = 0; 4852 callout_reset_bycpu(&intr->bnx_intr_timer, 4853 BNX_INTR_CKINTVL, intr->bnx_intr_check, intr, 4854 intr->bnx_intr_cpuid); 4855 } 4856 } 4857 } 4858 4859 static void 4860 bnx_disable_intr(struct bnx_softc *sc) 4861 { 4862 int i; 4863 4864 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4865 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 4866 4867 callout_stop(&intr->bnx_intr_timer); 4868 intr->bnx_intr_maylose = FALSE; 4869 intr->bnx_rx_check_considx = 0; 4870 intr->bnx_tx_check_considx = 0; 4871 } 4872 4873 /* 4874 * Mask the interrupt when we start polling. 4875 */ 4876 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, 4877 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4878 4879 /* 4880 * Acknowledge possible asserted interrupt. 4881 */ 4882 for (i = 0; i < BNX_INTR_MAX; ++i) 4883 bnx_writembx(sc, sc->bnx_intr_data[i].bnx_intr_mbx, 1); 4884 4885 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 4886 lwkt_serialize_handler_disable( 4887 sc->bnx_intr_data[i].bnx_intr_serialize); 4888 } 4889 } 4890 4891 static int 4892 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[]) 4893 { 4894 uint32_t mac_addr; 4895 int ret = 1; 4896 4897 mac_addr = bnx_readmem_ind(sc, 0x0c14); 4898 if ((mac_addr >> 16) == 0x484b) { 4899 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4900 ether_addr[1] = (uint8_t)mac_addr; 4901 mac_addr = bnx_readmem_ind(sc, 0x0c18); 4902 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4903 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4904 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4905 ether_addr[5] = (uint8_t)mac_addr; 4906 ret = 0; 4907 } 4908 return ret; 4909 } 4910 4911 static int 4912 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[]) 4913 { 4914 int mac_offset = BGE_EE_MAC_OFFSET; 4915 4916 if (BNX_IS_5717_PLUS(sc)) { 4917 int f; 4918 4919 f = pci_get_function(sc->bnx_dev); 4920 if (f & 1) 4921 mac_offset = BGE_EE_MAC_OFFSET_5717; 4922 if (f > 1) 4923 mac_offset += BGE_EE_MAC_OFFSET_5717_OFF; 4924 } 4925 4926 return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN); 4927 } 4928 4929 static int 4930 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[]) 4931 { 4932 if (sc->bnx_flags & BNX_FLAG_NO_EEPROM) 4933 return 1; 4934 4935 return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4936 ETHER_ADDR_LEN); 4937 } 4938 4939 static int 4940 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[]) 4941 { 4942 static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = { 4943 /* NOTE: Order is critical */ 4944 bnx_get_eaddr_mem, 4945 bnx_get_eaddr_nvram, 4946 bnx_get_eaddr_eeprom, 4947 NULL 4948 }; 4949 const bnx_eaddr_fcn_t *func; 4950 4951 for (func = bnx_eaddr_funcs; *func != NULL; ++func) { 4952 if ((*func)(sc, eaddr) == 0) 4953 break; 4954 } 4955 return (*func == NULL ? ENXIO : 0); 4956 } 4957 4958 /* 4959 * NOTE: 'm' is not freed upon failure 4960 */ 4961 static struct mbuf * 4962 bnx_defrag_shortdma(struct mbuf *m) 4963 { 4964 struct mbuf *n; 4965 int found; 4966 4967 /* 4968 * If device receive two back-to-back send BDs with less than 4969 * or equal to 8 total bytes then the device may hang. The two 4970 * back-to-back send BDs must in the same frame for this failure 4971 * to occur. Scan mbuf chains and see whether two back-to-back 4972 * send BDs are there. If this is the case, allocate new mbuf 4973 * and copy the frame to workaround the silicon bug. 4974 */ 4975 for (n = m, found = 0; n != NULL; n = n->m_next) { 4976 if (n->m_len < 8) { 4977 found++; 4978 if (found > 1) 4979 break; 4980 continue; 4981 } 4982 found = 0; 4983 } 4984 4985 if (found > 1) 4986 n = m_defrag(m, M_NOWAIT); 4987 else 4988 n = m; 4989 return n; 4990 } 4991 4992 static void 4993 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit) 4994 { 4995 int i; 4996 4997 BNX_CLRBIT(sc, reg, bit); 4998 for (i = 0; i < BNX_TIMEOUT; i++) { 4999 if ((CSR_READ_4(sc, reg) & bit) == 0) 5000 return; 5001 DELAY(100); 5002 } 5003 } 5004 5005 static void 5006 bnx_link_poll(struct bnx_softc *sc) 5007 { 5008 uint32_t status; 5009 5010 status = CSR_READ_4(sc, BGE_MAC_STS); 5011 if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) { 5012 sc->bnx_link_evt = 0; 5013 sc->bnx_link_upd(sc, status); 5014 } 5015 } 5016 5017 static void 5018 bnx_enable_msi(struct bnx_softc *sc, boolean_t is_msix) 5019 { 5020 uint32_t msi_mode; 5021 5022 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE); 5023 msi_mode |= BGE_MSIMODE_ENABLE; 5024 /* 5025 * NOTE: 5026 * 5718-PG105-R says that "one shot" mode does not work 5027 * if MSI is used, however, it obviously works. 5028 */ 5029 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE; 5030 if (is_msix) 5031 msi_mode |= BGE_MSIMODE_MSIX_MULTIMODE; 5032 else 5033 msi_mode &= ~BGE_MSIMODE_MSIX_MULTIMODE; 5034 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode); 5035 } 5036 5037 static uint32_t 5038 bnx_dma_swap_options(struct bnx_softc *sc) 5039 { 5040 uint32_t dma_options; 5041 5042 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 5043 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 5044 #if BYTE_ORDER == BIG_ENDIAN 5045 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 5046 #endif 5047 return dma_options; 5048 } 5049 5050 static int 5051 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp, 5052 uint16_t *mss0, uint16_t *flags0) 5053 { 5054 struct mbuf *m; 5055 struct ip *ip; 5056 struct tcphdr *th; 5057 int thoff, iphlen, hoff, hlen; 5058 uint16_t flags, mss; 5059 5060 m = *mp; 5061 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 5062 5063 hoff = m->m_pkthdr.csum_lhlen; 5064 iphlen = m->m_pkthdr.csum_iphlen; 5065 thoff = m->m_pkthdr.csum_thlen; 5066 5067 KASSERT(hoff > 0, ("invalid ether header len")); 5068 KASSERT(iphlen > 0, ("invalid ip header len")); 5069 KASSERT(thoff > 0, ("invalid tcp header len")); 5070 5071 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 5072 m = m_pullup(m, hoff + iphlen + thoff); 5073 if (m == NULL) { 5074 *mp = NULL; 5075 return ENOBUFS; 5076 } 5077 *mp = m; 5078 } 5079 ip = mtodoff(m, struct ip *, hoff); 5080 th = mtodoff(m, struct tcphdr *, hoff + iphlen); 5081 5082 mss = m->m_pkthdr.tso_segsz; 5083 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA; 5084 5085 ip->ip_len = htons(mss + iphlen + thoff); 5086 th->th_sum = 0; 5087 5088 hlen = (iphlen + thoff) >> 2; 5089 mss |= ((hlen & 0x3) << 14); 5090 flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2); 5091 5092 *mss0 = mss; 5093 *flags0 = flags; 5094 5095 return 0; 5096 } 5097 5098 static int 5099 bnx_create_tx_ring(struct bnx_tx_ring *txr) 5100 { 5101 bus_size_t txmaxsz, txmaxsegsz; 5102 int i, error; 5103 5104 lwkt_serialize_init(&txr->bnx_tx_serialize); 5105 5106 /* 5107 * Create DMA tag and maps for TX mbufs. 5108 */ 5109 if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO) 5110 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header); 5111 else 5112 txmaxsz = BNX_JUMBO_FRAMELEN; 5113 if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766) 5114 txmaxsegsz = MCLBYTES; 5115 else 5116 txmaxsegsz = PAGE_SIZE; 5117 error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag, 5118 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 5119 txmaxsz, BNX_NSEG_NEW, txmaxsegsz, 5120 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 5121 &txr->bnx_tx_mtag); 5122 if (error) { 5123 device_printf(txr->bnx_sc->bnx_dev, 5124 "could not create TX mbuf DMA tag\n"); 5125 return error; 5126 } 5127 5128 for (i = 0; i < BGE_TX_RING_CNT; i++) { 5129 error = bus_dmamap_create(txr->bnx_tx_mtag, 5130 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 5131 &txr->bnx_tx_buf[i].bnx_tx_dmamap); 5132 if (error) { 5133 int j; 5134 5135 for (j = 0; j < i; ++j) { 5136 bus_dmamap_destroy(txr->bnx_tx_mtag, 5137 txr->bnx_tx_buf[j].bnx_tx_dmamap); 5138 } 5139 bus_dma_tag_destroy(txr->bnx_tx_mtag); 5140 txr->bnx_tx_mtag = NULL; 5141 5142 device_printf(txr->bnx_sc->bnx_dev, 5143 "could not create TX mbuf DMA map\n"); 5144 return error; 5145 } 5146 } 5147 5148 /* 5149 * Create DMA stuffs for TX ring. 5150 */ 5151 error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ, 5152 &txr->bnx_tx_ring_tag, 5153 &txr->bnx_tx_ring_map, 5154 (void *)&txr->bnx_tx_ring, 5155 &txr->bnx_tx_ring_paddr); 5156 if (error) { 5157 device_printf(txr->bnx_sc->bnx_dev, 5158 "could not create TX ring\n"); 5159 return error; 5160 } 5161 5162 txr->bnx_tx_flags |= BNX_TX_FLAG_SHORTDMA; 5163 txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS; 5164 5165 return 0; 5166 } 5167 5168 static void 5169 bnx_destroy_tx_ring(struct bnx_tx_ring *txr) 5170 { 5171 /* Destroy TX mbuf DMA stuffs. */ 5172 if (txr->bnx_tx_mtag != NULL) { 5173 int i; 5174 5175 for (i = 0; i < BGE_TX_RING_CNT; i++) { 5176 KKASSERT(txr->bnx_tx_buf[i].bnx_tx_mbuf == NULL); 5177 bus_dmamap_destroy(txr->bnx_tx_mtag, 5178 txr->bnx_tx_buf[i].bnx_tx_dmamap); 5179 } 5180 bus_dma_tag_destroy(txr->bnx_tx_mtag); 5181 } 5182 5183 /* Destroy TX ring */ 5184 bnx_dma_block_free(txr->bnx_tx_ring_tag, 5185 txr->bnx_tx_ring_map, txr->bnx_tx_ring); 5186 } 5187 5188 static int 5189 bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS) 5190 { 5191 struct bnx_softc *sc = (void *)arg1; 5192 struct ifnet *ifp = &sc->arpcom.ac_if; 5193 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; 5194 int error, defrag, i; 5195 5196 if (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) 5197 defrag = 1; 5198 else 5199 defrag = 0; 5200 5201 error = sysctl_handle_int(oidp, &defrag, 0, req); 5202 if (error || req->newptr == NULL) 5203 return error; 5204 5205 ifnet_serialize_all(ifp); 5206 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) { 5207 txr = &sc->bnx_tx_ring[i]; 5208 if (defrag) 5209 txr->bnx_tx_flags |= BNX_TX_FLAG_FORCE_DEFRAG; 5210 else 5211 txr->bnx_tx_flags &= ~BNX_TX_FLAG_FORCE_DEFRAG; 5212 } 5213 ifnet_deserialize_all(ifp); 5214 5215 return 0; 5216 } 5217 5218 static int 5219 bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS) 5220 { 5221 struct bnx_softc *sc = (void *)arg1; 5222 struct ifnet *ifp = &sc->arpcom.ac_if; 5223 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; 5224 int error, tx_wreg, i; 5225 5226 tx_wreg = txr->bnx_tx_wreg; 5227 error = sysctl_handle_int(oidp, &tx_wreg, 0, req); 5228 if (error || req->newptr == NULL) 5229 return error; 5230 5231 ifnet_serialize_all(ifp); 5232 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 5233 sc->bnx_tx_ring[i].bnx_tx_wreg = tx_wreg; 5234 ifnet_deserialize_all(ifp); 5235 5236 return 0; 5237 } 5238 5239 static int 5240 bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *ret) 5241 { 5242 int error; 5243 5244 lwkt_serialize_init(&ret->bnx_rx_ret_serialize); 5245 5246 /* 5247 * Create DMA stuffs for RX return ring. 5248 */ 5249 error = bnx_dma_block_alloc(ret->bnx_sc, 5250 BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT), 5251 &ret->bnx_rx_ret_ring_tag, 5252 &ret->bnx_rx_ret_ring_map, 5253 (void *)&ret->bnx_rx_ret_ring, 5254 &ret->bnx_rx_ret_ring_paddr); 5255 if (error) { 5256 device_printf(ret->bnx_sc->bnx_dev, 5257 "could not create RX ret ring\n"); 5258 return error; 5259 } 5260 5261 /* Shadow standard ring's RX mbuf DMA tag */ 5262 ret->bnx_rx_mtag = ret->bnx_std->bnx_rx_mtag; 5263 5264 /* 5265 * Create tmp DMA map for RX mbufs. 5266 */ 5267 error = bus_dmamap_create(ret->bnx_rx_mtag, BUS_DMA_WAITOK, 5268 &ret->bnx_rx_tmpmap); 5269 if (error) { 5270 device_printf(ret->bnx_sc->bnx_dev, 5271 "could not create tmp RX mbuf DMA map\n"); 5272 ret->bnx_rx_mtag = NULL; 5273 return error; 5274 } 5275 return 0; 5276 } 5277 5278 static void 5279 bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *ret) 5280 { 5281 /* Destroy tmp RX mbuf DMA map */ 5282 if (ret->bnx_rx_mtag != NULL) 5283 bus_dmamap_destroy(ret->bnx_rx_mtag, ret->bnx_rx_tmpmap); 5284 5285 /* Destroy RX return ring */ 5286 bnx_dma_block_free(ret->bnx_rx_ret_ring_tag, 5287 ret->bnx_rx_ret_ring_map, ret->bnx_rx_ret_ring); 5288 } 5289 5290 static int 5291 bnx_alloc_intr(struct bnx_softc *sc) 5292 { 5293 struct bnx_intr_data *intr; 5294 u_int intr_flags; 5295 int error; 5296 5297 if (sc->bnx_intr_cnt > 1) { 5298 error = bnx_alloc_msix(sc); 5299 if (error) 5300 return error; 5301 KKASSERT(sc->bnx_intr_type == PCI_INTR_TYPE_MSIX); 5302 return 0; 5303 } 5304 5305 KKASSERT(sc->bnx_intr_cnt == 1); 5306 5307 intr = &sc->bnx_intr_data[0]; 5308 intr->bnx_ret = &sc->bnx_rx_ret_ring[0]; 5309 intr->bnx_txr = &sc->bnx_tx_ring[0]; 5310 intr->bnx_intr_serialize = &sc->bnx_main_serialize; 5311 intr->bnx_intr_check = bnx_check_intr_rxtx; 5312 intr->bnx_saved_status_tag = &intr->bnx_ret->bnx_saved_status_tag; 5313 5314 sc->bnx_intr_type = pci_alloc_1intr(sc->bnx_dev, bnx_msi_enable, 5315 &intr->bnx_intr_rid, &intr_flags); 5316 5317 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, SYS_RES_IRQ, 5318 &intr->bnx_intr_rid, intr_flags); 5319 if (intr->bnx_intr_res == NULL) { 5320 device_printf(sc->bnx_dev, "could not alloc interrupt\n"); 5321 return ENXIO; 5322 } 5323 5324 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) { 5325 bnx_enable_msi(sc, FALSE); 5326 intr->bnx_intr_func = bnx_msi; 5327 if (bootverbose) 5328 device_printf(sc->bnx_dev, "oneshot MSI\n"); 5329 } else { 5330 intr->bnx_intr_func = bnx_intr_legacy; 5331 } 5332 intr->bnx_intr_arg = sc; 5333 intr->bnx_intr_cpuid = rman_get_cpuid(intr->bnx_intr_res); 5334 5335 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid; 5336 5337 return 0; 5338 } 5339 5340 static int 5341 bnx_setup_intr(struct bnx_softc *sc) 5342 { 5343 int error, i; 5344 5345 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 5346 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 5347 5348 error = bus_setup_intr_descr(sc->bnx_dev, intr->bnx_intr_res, 5349 INTR_MPSAFE, intr->bnx_intr_func, intr->bnx_intr_arg, 5350 &intr->bnx_intr_hand, intr->bnx_intr_serialize, 5351 intr->bnx_intr_desc); 5352 if (error) { 5353 device_printf(sc->bnx_dev, 5354 "could not set up %dth intr\n", i); 5355 bnx_teardown_intr(sc, i); 5356 return error; 5357 } 5358 } 5359 return 0; 5360 } 5361 5362 static void 5363 bnx_teardown_intr(struct bnx_softc *sc, int cnt) 5364 { 5365 int i; 5366 5367 for (i = 0; i < cnt; ++i) { 5368 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 5369 5370 bus_teardown_intr(sc->bnx_dev, intr->bnx_intr_res, 5371 intr->bnx_intr_hand); 5372 } 5373 } 5374 5375 static void 5376 bnx_free_intr(struct bnx_softc *sc) 5377 { 5378 if (sc->bnx_intr_type != PCI_INTR_TYPE_MSIX) { 5379 struct bnx_intr_data *intr; 5380 5381 KKASSERT(sc->bnx_intr_cnt <= 1); 5382 intr = &sc->bnx_intr_data[0]; 5383 5384 if (intr->bnx_intr_res != NULL) { 5385 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ, 5386 intr->bnx_intr_rid, intr->bnx_intr_res); 5387 } 5388 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) 5389 pci_release_msi(sc->bnx_dev); 5390 } else { 5391 bnx_free_msix(sc, TRUE); 5392 } 5393 } 5394 5395 static void 5396 bnx_setup_serialize(struct bnx_softc *sc) 5397 { 5398 int i, j; 5399 5400 /* 5401 * Allocate serializer array 5402 */ 5403 5404 /* Main + RX STD + TX + RX RET */ 5405 sc->bnx_serialize_cnt = 1 + 1 + sc->bnx_tx_ringcnt + sc->bnx_rx_retcnt; 5406 5407 sc->bnx_serialize = 5408 kmalloc(sc->bnx_serialize_cnt * sizeof(struct lwkt_serialize *), 5409 M_DEVBUF, M_WAITOK | M_ZERO); 5410 5411 /* 5412 * Setup serializers 5413 * 5414 * NOTE: Order is critical 5415 */ 5416 5417 i = 0; 5418 5419 KKASSERT(i < sc->bnx_serialize_cnt); 5420 sc->bnx_serialize[i++] = &sc->bnx_main_serialize; 5421 5422 KKASSERT(i < sc->bnx_serialize_cnt); 5423 sc->bnx_serialize[i++] = &sc->bnx_rx_std_ring.bnx_rx_std_serialize; 5424 5425 for (j = 0; j < sc->bnx_rx_retcnt; ++j) { 5426 KKASSERT(i < sc->bnx_serialize_cnt); 5427 sc->bnx_serialize[i++] = 5428 &sc->bnx_rx_ret_ring[j].bnx_rx_ret_serialize; 5429 } 5430 5431 for (j = 0; j < sc->bnx_tx_ringcnt; ++j) { 5432 KKASSERT(i < sc->bnx_serialize_cnt); 5433 sc->bnx_serialize[i++] = 5434 &sc->bnx_tx_ring[j].bnx_tx_serialize; 5435 } 5436 5437 KKASSERT(i == sc->bnx_serialize_cnt); 5438 } 5439 5440 static void 5441 bnx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 5442 { 5443 struct bnx_softc *sc = ifp->if_softc; 5444 5445 ifnet_serialize_array_enter(sc->bnx_serialize, 5446 sc->bnx_serialize_cnt, slz); 5447 } 5448 5449 static void 5450 bnx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 5451 { 5452 struct bnx_softc *sc = ifp->if_softc; 5453 5454 ifnet_serialize_array_exit(sc->bnx_serialize, 5455 sc->bnx_serialize_cnt, slz); 5456 } 5457 5458 static int 5459 bnx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 5460 { 5461 struct bnx_softc *sc = ifp->if_softc; 5462 5463 return ifnet_serialize_array_try(sc->bnx_serialize, 5464 sc->bnx_serialize_cnt, slz); 5465 } 5466 5467 #ifdef INVARIANTS 5468 5469 static void 5470 bnx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 5471 boolean_t serialized) 5472 { 5473 struct bnx_softc *sc = ifp->if_softc; 5474 5475 ifnet_serialize_array_assert(sc->bnx_serialize, sc->bnx_serialize_cnt, 5476 slz, serialized); 5477 } 5478 5479 #endif /* INVARIANTS */ 5480 5481 static void 5482 bnx_set_tick_cpuid(struct bnx_softc *sc, boolean_t polling) 5483 { 5484 if (polling) 5485 sc->bnx_tick_cpuid = 0; /* XXX */ 5486 else 5487 sc->bnx_tick_cpuid = sc->bnx_intr_data[0].bnx_intr_cpuid; 5488 } 5489 5490 static void 5491 bnx_rx_std_refill_ithread(void *xstd) 5492 { 5493 struct bnx_rx_std_ring *std = xstd; 5494 struct globaldata *gd = mycpu; 5495 5496 crit_enter_gd(gd); 5497 5498 while (!std->bnx_rx_std_stop) { 5499 if (std->bnx_rx_std_refill) { 5500 lwkt_serialize_handler_call( 5501 &std->bnx_rx_std_serialize, 5502 bnx_rx_std_refill, std, NULL); 5503 } 5504 5505 crit_exit_gd(gd); 5506 crit_enter_gd(gd); 5507 5508 atomic_poll_release_int(&std->bnx_rx_std_running); 5509 cpu_mfence(); 5510 5511 if (!std->bnx_rx_std_refill && !std->bnx_rx_std_stop) { 5512 lwkt_deschedule_self(gd->gd_curthread); 5513 lwkt_switch(); 5514 } 5515 } 5516 5517 crit_exit_gd(gd); 5518 5519 wakeup(std); 5520 5521 lwkt_exit(); 5522 } 5523 5524 static void 5525 bnx_rx_std_refill(void *xstd, void *frame __unused) 5526 { 5527 struct bnx_rx_std_ring *std = xstd; 5528 int cnt, refill_mask; 5529 5530 again: 5531 cnt = 0; 5532 5533 cpu_lfence(); 5534 refill_mask = std->bnx_rx_std_refill; 5535 atomic_clear_int(&std->bnx_rx_std_refill, refill_mask); 5536 5537 while (refill_mask) { 5538 uint16_t check_idx = std->bnx_rx_std; 5539 int ret_idx; 5540 5541 ret_idx = bsfl(refill_mask); 5542 for (;;) { 5543 struct bnx_rx_buf *rb; 5544 int refilled; 5545 5546 BNX_INC(check_idx, BGE_STD_RX_RING_CNT); 5547 rb = &std->bnx_rx_std_buf[check_idx]; 5548 refilled = rb->bnx_rx_refilled; 5549 cpu_lfence(); 5550 if (refilled) { 5551 bnx_setup_rxdesc_std(std, check_idx); 5552 std->bnx_rx_std = check_idx; 5553 ++cnt; 5554 if (cnt >= 8) { 5555 atomic_subtract_int( 5556 &std->bnx_rx_std_used, cnt); 5557 bnx_writembx(std->bnx_sc, 5558 BGE_MBX_RX_STD_PROD_LO, 5559 std->bnx_rx_std); 5560 cnt = 0; 5561 } 5562 } else { 5563 break; 5564 } 5565 } 5566 refill_mask &= ~(1 << ret_idx); 5567 } 5568 5569 if (cnt) { 5570 atomic_subtract_int(&std->bnx_rx_std_used, cnt); 5571 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, 5572 std->bnx_rx_std); 5573 } 5574 5575 if (std->bnx_rx_std_refill) 5576 goto again; 5577 5578 atomic_poll_release_int(&std->bnx_rx_std_running); 5579 cpu_mfence(); 5580 5581 if (std->bnx_rx_std_refill) 5582 goto again; 5583 } 5584 5585 static int 5586 bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS) 5587 { 5588 struct bnx_softc *sc = (void *)arg1; 5589 struct ifnet *ifp = &sc->arpcom.ac_if; 5590 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; 5591 int error, cntmax, i; 5592 5593 cntmax = ret->bnx_rx_cntmax; 5594 error = sysctl_handle_int(oidp, &cntmax, 0, req); 5595 if (error || req->newptr == NULL) 5596 return error; 5597 5598 ifnet_serialize_all(ifp); 5599 5600 if ((cntmax * sc->bnx_rx_retcnt) >= BGE_STD_RX_RING_CNT / 2) { 5601 error = EINVAL; 5602 goto back; 5603 } 5604 5605 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) 5606 sc->bnx_rx_ret_ring[i].bnx_rx_cntmax = cntmax; 5607 error = 0; 5608 5609 back: 5610 ifnet_deserialize_all(ifp); 5611 5612 return error; 5613 } 5614 5615 static void 5616 bnx_init_rss(struct bnx_softc *sc) 5617 { 5618 uint8_t key[BGE_RSS_KEYREG_CNT * BGE_RSS_KEYREG_SIZE]; 5619 int i, j, r; 5620 5621 KKASSERT(BNX_RSS_ENABLED(sc)); 5622 5623 /* 5624 * Configure RSS redirect table. 5625 */ 5626 if_ringmap_rdrtable(sc->bnx_rx_rmap, sc->bnx_rdr_table, 5627 BNX_RDRTABLE_SIZE); 5628 r = 0; 5629 for (j = 0; j < BGE_RSS_INDIR_TBL_CNT; ++j) { 5630 uint32_t tbl = 0; 5631 5632 for (i = 0; i < BGE_RSS_INDIR_TBLENT_CNT; ++i) { 5633 uint32_t q; 5634 5635 q = sc->bnx_rdr_table[r]; 5636 tbl |= q << (BGE_RSS_INDIR_TBLENT_SHIFT * 5637 (BGE_RSS_INDIR_TBLENT_CNT - i - 1)); 5638 ++r; 5639 } 5640 5641 BNX_RSS_DPRINTF(sc, 1, "tbl%d %08x\n", j, tbl); 5642 CSR_WRITE_4(sc, BGE_RSS_INDIR_TBL(j), tbl); 5643 } 5644 5645 toeplitz_get_key(key, sizeof(key)); 5646 for (i = 0; i < BGE_RSS_KEYREG_CNT; ++i) { 5647 uint32_t keyreg; 5648 5649 keyreg = BGE_RSS_KEYREG_VAL(key, i); 5650 5651 BNX_RSS_DPRINTF(sc, 1, "key%d %08x\n", i, keyreg); 5652 CSR_WRITE_4(sc, BGE_RSS_KEYREG(i), keyreg); 5653 } 5654 } 5655 5656 static void 5657 bnx_setup_ring_cnt(struct bnx_softc *sc) 5658 { 5659 int msix_enable, msix_cnt, msix_ring, ring_max, ring_cnt; 5660 5661 /* One RX ring. */ 5662 sc->bnx_rx_rmap = if_ringmap_alloc(sc->bnx_dev, 1, 1); 5663 5664 if (netisr_ncpus == 1) 5665 goto skip_rx; 5666 5667 msix_enable = device_getenv_int(sc->bnx_dev, "msix.enable", 5668 bnx_msix_enable); 5669 if (!msix_enable) 5670 goto skip_rx; 5671 5672 /* 5673 * One MSI-X vector is dedicated to status or single TX queue, 5674 * so make sure that there are enough MSI-X vectors. 5675 */ 5676 msix_cnt = pci_msix_count(sc->bnx_dev); 5677 if (msix_cnt <= 1) 5678 goto skip_rx; 5679 if (bootverbose) 5680 device_printf(sc->bnx_dev, "MSI-X count %d\n", msix_cnt); 5681 msix_ring = msix_cnt - 1; 5682 5683 /* 5684 * Setup RX ring count 5685 */ 5686 ring_max = BNX_RX_RING_MAX; 5687 if (ring_max > msix_ring) 5688 ring_max = msix_ring; 5689 ring_cnt = device_getenv_int(sc->bnx_dev, "rx_rings", bnx_rx_rings); 5690 5691 if_ringmap_free(sc->bnx_rx_rmap); 5692 sc->bnx_rx_rmap = if_ringmap_alloc(sc->bnx_dev, ring_cnt, ring_max); 5693 5694 skip_rx: 5695 sc->bnx_rx_retcnt = if_ringmap_count(sc->bnx_rx_rmap); 5696 5697 /* 5698 * Setup TX ring count 5699 * 5700 * Currently only BCM5719 and BCM5720 support multiple TX rings 5701 * and the TX ring count must be less than the RX ring count. 5702 */ 5703 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 || 5704 sc->bnx_asicrev == BGE_ASICREV_BCM5720) { 5705 ring_max = BNX_TX_RING_MAX; 5706 if (ring_max > sc->bnx_rx_retcnt) 5707 ring_max = sc->bnx_rx_retcnt; 5708 ring_cnt = device_getenv_int(sc->bnx_dev, "tx_rings", 5709 bnx_tx_rings); 5710 } else { 5711 ring_max = 1; 5712 ring_cnt = 1; 5713 } 5714 sc->bnx_tx_rmap = if_ringmap_alloc(sc->bnx_dev, ring_cnt, ring_max); 5715 if_ringmap_align(sc->bnx_dev, sc->bnx_rx_rmap, sc->bnx_tx_rmap); 5716 5717 sc->bnx_tx_ringcnt = if_ringmap_count(sc->bnx_tx_rmap); 5718 KASSERT(sc->bnx_tx_ringcnt <= sc->bnx_rx_retcnt, 5719 ("invalid TX ring count %d and RX ring count %d", 5720 sc->bnx_tx_ringcnt, sc->bnx_rx_retcnt)); 5721 5722 /* 5723 * Setup interrupt count. 5724 */ 5725 if (sc->bnx_rx_retcnt == 1) { 5726 sc->bnx_intr_cnt = 1; 5727 } else { 5728 /* 5729 * We need one extra MSI-X vector for link status or 5730 * TX ring (if only one TX ring is enabled). 5731 */ 5732 sc->bnx_intr_cnt = sc->bnx_rx_retcnt + 1; 5733 } 5734 KKASSERT(sc->bnx_intr_cnt <= BNX_INTR_MAX); 5735 5736 if (bootverbose) { 5737 device_printf(sc->bnx_dev, "intr count %d, " 5738 "RX ring %d, TX ring %d\n", sc->bnx_intr_cnt, 5739 sc->bnx_rx_retcnt, sc->bnx_tx_ringcnt); 5740 } 5741 } 5742 5743 static int 5744 bnx_alloc_msix(struct bnx_softc *sc) 5745 { 5746 struct bnx_intr_data *intr; 5747 boolean_t setup = FALSE; 5748 int error, i; 5749 5750 KKASSERT(sc->bnx_intr_cnt > 1); 5751 KKASSERT(sc->bnx_intr_cnt == sc->bnx_rx_retcnt + 1); 5752 5753 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) { 5754 /* 5755 * Link status 5756 */ 5757 intr = &sc->bnx_intr_data[0]; 5758 5759 intr->bnx_intr_serialize = &sc->bnx_main_serialize; 5760 intr->bnx_saved_status_tag = &sc->bnx_saved_status_tag; 5761 5762 intr->bnx_intr_func = bnx_msix_status; 5763 intr->bnx_intr_arg = sc; 5764 intr->bnx_intr_cpuid = 0; /* XXX */ 5765 5766 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0), 5767 "%s sts", device_get_nameunit(sc->bnx_dev)); 5768 intr->bnx_intr_desc = intr->bnx_intr_desc0; 5769 5770 /* 5771 * RX/TX rings 5772 */ 5773 for (i = 1; i < sc->bnx_intr_cnt; ++i) { 5774 int idx = i - 1; 5775 5776 intr = &sc->bnx_intr_data[i]; 5777 5778 KKASSERT(idx < sc->bnx_rx_retcnt); 5779 intr->bnx_ret = &sc->bnx_rx_ret_ring[idx]; 5780 if (idx < sc->bnx_tx_ringcnt) { 5781 intr->bnx_txr = &sc->bnx_tx_ring[idx]; 5782 intr->bnx_ret->bnx_txr = intr->bnx_txr; 5783 } 5784 5785 intr->bnx_intr_serialize = 5786 &intr->bnx_ret->bnx_rx_ret_serialize; 5787 intr->bnx_saved_status_tag = 5788 &intr->bnx_ret->bnx_saved_status_tag; 5789 5790 intr->bnx_intr_arg = intr->bnx_ret; 5791 intr->bnx_intr_cpuid = 5792 if_ringmap_cpumap(sc->bnx_rx_rmap, idx); 5793 KKASSERT(intr->bnx_intr_cpuid < netisr_ncpus); 5794 5795 if (intr->bnx_txr == NULL) { 5796 intr->bnx_intr_check = bnx_check_intr_rx; 5797 intr->bnx_intr_func = bnx_msix_rx; 5798 ksnprintf(intr->bnx_intr_desc0, 5799 sizeof(intr->bnx_intr_desc0), "%s rx%d", 5800 device_get_nameunit(sc->bnx_dev), idx); 5801 } else { 5802 #ifdef INVARIANTS 5803 int tx_cpuid; 5804 #endif 5805 5806 intr->bnx_intr_check = bnx_check_intr_rxtx; 5807 intr->bnx_intr_func = bnx_msix_rxtx; 5808 ksnprintf(intr->bnx_intr_desc0, 5809 sizeof(intr->bnx_intr_desc0), "%s rxtx%d", 5810 device_get_nameunit(sc->bnx_dev), idx); 5811 5812 #ifdef INVARIANTS 5813 tx_cpuid = if_ringmap_cpumap(sc->bnx_tx_rmap, 5814 idx); 5815 KASSERT(intr->bnx_intr_cpuid == tx_cpuid, 5816 ("RX intr cpu%d, TX intr cpu%d, mismatch", 5817 intr->bnx_intr_cpuid, tx_cpuid)); 5818 #endif 5819 intr->bnx_txr->bnx_tx_cpuid = 5820 intr->bnx_intr_cpuid; 5821 } 5822 intr->bnx_intr_desc = intr->bnx_intr_desc0; 5823 5824 intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx; 5825 } 5826 } else { 5827 /* 5828 * TX ring0 and link status 5829 */ 5830 intr = &sc->bnx_intr_data[0]; 5831 5832 intr->bnx_txr = &sc->bnx_tx_ring[0]; 5833 intr->bnx_intr_serialize = &sc->bnx_main_serialize; 5834 intr->bnx_intr_check = bnx_check_intr_tx; 5835 intr->bnx_saved_status_tag = 5836 &intr->bnx_txr->bnx_saved_status_tag; 5837 5838 intr->bnx_intr_func = bnx_msix_tx_status; 5839 intr->bnx_intr_arg = intr->bnx_txr; 5840 intr->bnx_intr_cpuid = if_ringmap_cpumap(sc->bnx_tx_rmap, 0); 5841 KKASSERT(intr->bnx_intr_cpuid < netisr_ncpus); 5842 5843 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0), 5844 "%s ststx", device_get_nameunit(sc->bnx_dev)); 5845 intr->bnx_intr_desc = intr->bnx_intr_desc0; 5846 5847 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid; 5848 5849 /* 5850 * RX rings 5851 */ 5852 for (i = 1; i < sc->bnx_intr_cnt; ++i) { 5853 int idx = i - 1; 5854 5855 intr = &sc->bnx_intr_data[i]; 5856 5857 KKASSERT(idx < sc->bnx_rx_retcnt); 5858 intr->bnx_ret = &sc->bnx_rx_ret_ring[idx]; 5859 intr->bnx_intr_serialize = 5860 &intr->bnx_ret->bnx_rx_ret_serialize; 5861 intr->bnx_intr_check = bnx_check_intr_rx; 5862 intr->bnx_saved_status_tag = 5863 &intr->bnx_ret->bnx_saved_status_tag; 5864 5865 intr->bnx_intr_func = bnx_msix_rx; 5866 intr->bnx_intr_arg = intr->bnx_ret; 5867 intr->bnx_intr_cpuid = 5868 if_ringmap_cpumap(sc->bnx_rx_rmap, idx); 5869 KKASSERT(intr->bnx_intr_cpuid < netisr_ncpus); 5870 5871 ksnprintf(intr->bnx_intr_desc0, 5872 sizeof(intr->bnx_intr_desc0), "%s rx%d", 5873 device_get_nameunit(sc->bnx_dev), idx); 5874 intr->bnx_intr_desc = intr->bnx_intr_desc0; 5875 5876 intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx; 5877 } 5878 } 5879 5880 if (BNX_IS_5717_PLUS(sc)) { 5881 sc->bnx_msix_mem_rid = PCIR_BAR(4); 5882 } else { 5883 if (sc->bnx_res2 == NULL) 5884 sc->bnx_msix_mem_rid = PCIR_BAR(2); 5885 } 5886 if (sc->bnx_msix_mem_rid != 0) { 5887 sc->bnx_msix_mem_res = bus_alloc_resource_any(sc->bnx_dev, 5888 SYS_RES_MEMORY, &sc->bnx_msix_mem_rid, RF_ACTIVE); 5889 if (sc->bnx_msix_mem_res == NULL) { 5890 device_printf(sc->bnx_dev, 5891 "could not alloc MSI-X table\n"); 5892 return ENXIO; 5893 } 5894 } 5895 5896 bnx_enable_msi(sc, TRUE); 5897 5898 error = pci_setup_msix(sc->bnx_dev); 5899 if (error) { 5900 device_printf(sc->bnx_dev, "could not setup MSI-X\n"); 5901 goto back; 5902 } 5903 setup = TRUE; 5904 5905 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 5906 intr = &sc->bnx_intr_data[i]; 5907 5908 error = pci_alloc_msix_vector(sc->bnx_dev, i, 5909 &intr->bnx_intr_rid, intr->bnx_intr_cpuid); 5910 if (error) { 5911 device_printf(sc->bnx_dev, 5912 "could not alloc MSI-X %d on cpu%d\n", 5913 i, intr->bnx_intr_cpuid); 5914 goto back; 5915 } 5916 5917 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, 5918 SYS_RES_IRQ, &intr->bnx_intr_rid, RF_ACTIVE); 5919 if (intr->bnx_intr_res == NULL) { 5920 device_printf(sc->bnx_dev, 5921 "could not alloc MSI-X %d resource\n", i); 5922 error = ENXIO; 5923 goto back; 5924 } 5925 } 5926 5927 pci_enable_msix(sc->bnx_dev); 5928 sc->bnx_intr_type = PCI_INTR_TYPE_MSIX; 5929 back: 5930 if (error) 5931 bnx_free_msix(sc, setup); 5932 return error; 5933 } 5934 5935 static void 5936 bnx_free_msix(struct bnx_softc *sc, boolean_t setup) 5937 { 5938 int i; 5939 5940 KKASSERT(sc->bnx_intr_cnt > 1); 5941 5942 for (i = 0; i < sc->bnx_intr_cnt; ++i) { 5943 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; 5944 5945 if (intr->bnx_intr_res != NULL) { 5946 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ, 5947 intr->bnx_intr_rid, intr->bnx_intr_res); 5948 } 5949 if (intr->bnx_intr_rid >= 0) { 5950 pci_release_msix_vector(sc->bnx_dev, 5951 intr->bnx_intr_rid); 5952 } 5953 } 5954 if (setup) 5955 pci_teardown_msix(sc->bnx_dev); 5956 } 5957 5958 static void 5959 bnx_rx_std_refill_sched_ipi(void *xret) 5960 { 5961 struct bnx_rx_ret_ring *ret = xret; 5962 struct bnx_rx_std_ring *std = ret->bnx_std; 5963 struct globaldata *gd = mycpu; 5964 5965 crit_enter_gd(gd); 5966 5967 atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask); 5968 cpu_sfence(); 5969 5970 KKASSERT(std->bnx_rx_std_ithread->td_gd == gd); 5971 lwkt_schedule(std->bnx_rx_std_ithread); 5972 5973 crit_exit_gd(gd); 5974 } 5975 5976 static void 5977 bnx_rx_std_refill_stop(void *xstd) 5978 { 5979 struct bnx_rx_std_ring *std = xstd; 5980 struct globaldata *gd = mycpu; 5981 5982 crit_enter_gd(gd); 5983 5984 std->bnx_rx_std_stop = 1; 5985 cpu_sfence(); 5986 5987 KKASSERT(std->bnx_rx_std_ithread->td_gd == gd); 5988 lwkt_schedule(std->bnx_rx_std_ithread); 5989 5990 crit_exit_gd(gd); 5991 } 5992 5993 static void 5994 bnx_serialize_skipmain(struct bnx_softc *sc) 5995 { 5996 lwkt_serialize_array_enter(sc->bnx_serialize, 5997 sc->bnx_serialize_cnt, 1); 5998 } 5999 6000 static void 6001 bnx_deserialize_skipmain(struct bnx_softc *sc) 6002 { 6003 lwkt_serialize_array_exit(sc->bnx_serialize, 6004 sc->bnx_serialize_cnt, 1); 6005 } 6006 6007 static void 6008 bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *ret, 6009 struct bnx_rx_std_ring *std) 6010 { 6011 struct globaldata *gd = mycpu; 6012 6013 ret->bnx_rx_cnt = 0; 6014 cpu_sfence(); 6015 6016 crit_enter_gd(gd); 6017 6018 atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask); 6019 cpu_sfence(); 6020 if (atomic_poll_acquire_int(&std->bnx_rx_std_running)) { 6021 if (std->bnx_rx_std_ithread->td_gd == gd) { 6022 lwkt_schedule(std->bnx_rx_std_ithread); 6023 } else { 6024 lwkt_send_ipiq(std->bnx_rx_std_ithread->td_gd, 6025 bnx_rx_std_refill_sched_ipi, ret); 6026 } 6027 } 6028 6029 crit_exit_gd(gd); 6030 } 6031 6032 static struct pktinfo * 6033 bnx_rss_info(struct pktinfo *pi, const struct bge_rx_bd *cur_rx) 6034 { 6035 /* Don't pick up IPv6 packet */ 6036 if (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) 6037 return NULL; 6038 6039 /* Don't pick up IP packet w/o IP checksum */ 6040 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) == 0 || 6041 (cur_rx->bge_error_flag & BGE_RXERRFLAG_IP_CSUM_NOK)) 6042 return NULL; 6043 6044 /* Don't pick up IP packet w/o TCP/UDP checksum */ 6045 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) == 0) 6046 return NULL; 6047 6048 /* May be IP fragment */ 6049 if (cur_rx->bge_tcp_udp_csum != 0xffff) 6050 return NULL; 6051 6052 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_IS_TCP) 6053 pi->pi_l3proto = IPPROTO_TCP; 6054 else 6055 pi->pi_l3proto = IPPROTO_UDP; 6056 pi->pi_netisr = NETISR_IP; 6057 pi->pi_flags = 0; 6058 6059 return pi; 6060 } 6061 6062 static void 6063 bnx_sig_pre_reset(struct bnx_softc *sc, int type) 6064 { 6065 if (type == BNX_RESET_START || type == BNX_RESET_SUSPEND) 6066 bnx_ape_driver_state_change(sc, type); 6067 } 6068 6069 static void 6070 bnx_sig_post_reset(struct bnx_softc *sc, int type) 6071 { 6072 if (type == BNX_RESET_SHUTDOWN) 6073 bnx_ape_driver_state_change(sc, type); 6074 } 6075 6076 /* 6077 * Clear all stale locks and select the lock for this driver instance. 6078 */ 6079 static void 6080 bnx_ape_lock_init(struct bnx_softc *sc) 6081 { 6082 uint32_t bit, regbase; 6083 int i; 6084 6085 regbase = BGE_APE_PER_LOCK_GRANT; 6086 6087 /* Clear any stale locks. */ 6088 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 6089 switch (i) { 6090 case BGE_APE_LOCK_PHY0: 6091 case BGE_APE_LOCK_PHY1: 6092 case BGE_APE_LOCK_PHY2: 6093 case BGE_APE_LOCK_PHY3: 6094 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6095 break; 6096 6097 default: 6098 if (sc->bnx_func_addr == 0) 6099 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6100 else 6101 bit = 1 << sc->bnx_func_addr; 6102 break; 6103 } 6104 APE_WRITE_4(sc, regbase + 4 * i, bit); 6105 } 6106 6107 /* Select the PHY lock based on the device's function number. */ 6108 switch (sc->bnx_func_addr) { 6109 case 0: 6110 sc->bnx_phy_ape_lock = BGE_APE_LOCK_PHY0; 6111 break; 6112 6113 case 1: 6114 sc->bnx_phy_ape_lock = BGE_APE_LOCK_PHY1; 6115 break; 6116 6117 case 2: 6118 sc->bnx_phy_ape_lock = BGE_APE_LOCK_PHY2; 6119 break; 6120 6121 case 3: 6122 sc->bnx_phy_ape_lock = BGE_APE_LOCK_PHY3; 6123 break; 6124 6125 default: 6126 device_printf(sc->bnx_dev, 6127 "PHY lock not supported on this function\n"); 6128 break; 6129 } 6130 } 6131 6132 /* 6133 * Check for APE firmware, set flags, and print version info. 6134 */ 6135 static void 6136 bnx_ape_read_fw_ver(struct bnx_softc *sc) 6137 { 6138 const char *fwtype; 6139 uint32_t apedata, features; 6140 6141 /* Check for a valid APE signature in shared memory. */ 6142 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 6143 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 6144 device_printf(sc->bnx_dev, "no APE signature\n"); 6145 sc->bnx_mfw_flags &= ~BNX_MFW_ON_APE; 6146 return; 6147 } 6148 6149 /* Check if APE firmware is running. */ 6150 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 6151 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 6152 device_printf(sc->bnx_dev, "APE signature found " 6153 "but FW status not ready! 0x%08x\n", apedata); 6154 return; 6155 } 6156 6157 sc->bnx_mfw_flags |= BNX_MFW_ON_APE; 6158 6159 /* Fetch the APE firwmare type and version. */ 6160 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 6161 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 6162 if (features & BGE_APE_FW_FEATURE_NCSI) { 6163 sc->bnx_mfw_flags |= BNX_MFW_TYPE_NCSI; 6164 fwtype = "NCSI"; 6165 } else if (features & BGE_APE_FW_FEATURE_DASH) { 6166 sc->bnx_mfw_flags |= BNX_MFW_TYPE_DASH; 6167 fwtype = "DASH"; 6168 } else { 6169 fwtype = "UNKN"; 6170 } 6171 6172 /* Print the APE firmware version. */ 6173 device_printf(sc->bnx_dev, "APE FW version: %s v%d.%d.%d.%d\n", 6174 fwtype, 6175 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 6176 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 6177 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 6178 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 6179 } 6180 6181 static int 6182 bnx_ape_lock(struct bnx_softc *sc, int locknum) 6183 { 6184 uint32_t bit, gnt, req, status; 6185 int i, off; 6186 6187 if ((sc->bnx_mfw_flags & BNX_MFW_ON_APE) == 0) 6188 return 0; 6189 6190 /* Lock request/grant registers have different bases. */ 6191 req = BGE_APE_PER_LOCK_REQ; 6192 gnt = BGE_APE_PER_LOCK_GRANT; 6193 6194 off = 4 * locknum; 6195 6196 switch (locknum) { 6197 case BGE_APE_LOCK_GPIO: 6198 /* Lock required when using GPIO. */ 6199 if (sc->bnx_func_addr == 0) 6200 bit = BGE_APE_LOCK_REQ_DRIVER0; 6201 else 6202 bit = 1 << sc->bnx_func_addr; 6203 break; 6204 6205 case BGE_APE_LOCK_GRC: 6206 /* Lock required to reset the device. */ 6207 if (sc->bnx_func_addr == 0) 6208 bit = BGE_APE_LOCK_REQ_DRIVER0; 6209 else 6210 bit = 1 << sc->bnx_func_addr; 6211 break; 6212 6213 case BGE_APE_LOCK_MEM: 6214 /* Lock required when accessing certain APE memory. */ 6215 if (sc->bnx_func_addr == 0) 6216 bit = BGE_APE_LOCK_REQ_DRIVER0; 6217 else 6218 bit = 1 << sc->bnx_func_addr; 6219 break; 6220 6221 case BGE_APE_LOCK_PHY0: 6222 case BGE_APE_LOCK_PHY1: 6223 case BGE_APE_LOCK_PHY2: 6224 case BGE_APE_LOCK_PHY3: 6225 /* Lock required when accessing PHYs. */ 6226 bit = BGE_APE_LOCK_REQ_DRIVER0; 6227 break; 6228 6229 default: 6230 return EINVAL; 6231 } 6232 6233 /* Request a lock. */ 6234 APE_WRITE_4(sc, req + off, bit); 6235 6236 /* Wait up to 1 second to acquire lock. */ 6237 for (i = 0; i < 20000; i++) { 6238 status = APE_READ_4(sc, gnt + off); 6239 if (status == bit) 6240 break; 6241 DELAY(50); 6242 } 6243 6244 /* Handle any errors. */ 6245 if (status != bit) { 6246 if_printf(&sc->arpcom.ac_if, "APE lock %d request failed! " 6247 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 6248 locknum, req + off, bit & 0xFFFF, gnt + off, 6249 status & 0xFFFF); 6250 /* Revoke the lock request. */ 6251 APE_WRITE_4(sc, gnt + off, bit); 6252 return EBUSY; 6253 } 6254 6255 return 0; 6256 } 6257 6258 static void 6259 bnx_ape_unlock(struct bnx_softc *sc, int locknum) 6260 { 6261 uint32_t bit, gnt; 6262 int off; 6263 6264 if ((sc->bnx_mfw_flags & BNX_MFW_ON_APE) == 0) 6265 return; 6266 6267 gnt = BGE_APE_PER_LOCK_GRANT; 6268 6269 off = 4 * locknum; 6270 6271 switch (locknum) { 6272 case BGE_APE_LOCK_GPIO: 6273 if (sc->bnx_func_addr == 0) 6274 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6275 else 6276 bit = 1 << sc->bnx_func_addr; 6277 break; 6278 6279 case BGE_APE_LOCK_GRC: 6280 if (sc->bnx_func_addr == 0) 6281 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6282 else 6283 bit = 1 << sc->bnx_func_addr; 6284 break; 6285 6286 case BGE_APE_LOCK_MEM: 6287 if (sc->bnx_func_addr == 0) 6288 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6289 else 6290 bit = 1 << sc->bnx_func_addr; 6291 break; 6292 6293 case BGE_APE_LOCK_PHY0: 6294 case BGE_APE_LOCK_PHY1: 6295 case BGE_APE_LOCK_PHY2: 6296 case BGE_APE_LOCK_PHY3: 6297 bit = BGE_APE_LOCK_GRANT_DRIVER0; 6298 break; 6299 6300 default: 6301 return; 6302 } 6303 6304 APE_WRITE_4(sc, gnt + off, bit); 6305 } 6306 6307 /* 6308 * Send an event to the APE firmware. 6309 */ 6310 static void 6311 bnx_ape_send_event(struct bnx_softc *sc, uint32_t event) 6312 { 6313 uint32_t apedata; 6314 int i; 6315 6316 /* NCSI does not support APE events. */ 6317 if ((sc->bnx_mfw_flags & BNX_MFW_ON_APE) == 0) 6318 return; 6319 6320 /* Wait up to 1ms for APE to service previous event. */ 6321 for (i = 10; i > 0; i--) { 6322 if (bnx_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 6323 break; 6324 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 6325 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 6326 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 6327 BGE_APE_EVENT_STATUS_EVENT_PENDING); 6328 bnx_ape_unlock(sc, BGE_APE_LOCK_MEM); 6329 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 6330 break; 6331 } 6332 bnx_ape_unlock(sc, BGE_APE_LOCK_MEM); 6333 DELAY(100); 6334 } 6335 if (i == 0) { 6336 if_printf(&sc->arpcom.ac_if, 6337 "APE event 0x%08x send timed out\n", event); 6338 } 6339 } 6340 6341 static void 6342 bnx_ape_driver_state_change(struct bnx_softc *sc, int kind) 6343 { 6344 uint32_t apedata, event; 6345 6346 if ((sc->bnx_mfw_flags & BNX_MFW_ON_APE) == 0) 6347 return; 6348 6349 switch (kind) { 6350 case BNX_RESET_START: 6351 /* If this is the first load, clear the load counter. */ 6352 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 6353 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) { 6354 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 6355 } else { 6356 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 6357 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 6358 } 6359 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 6360 BGE_APE_HOST_SEG_SIG_MAGIC); 6361 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 6362 BGE_APE_HOST_SEG_LEN_MAGIC); 6363 6364 /* Add some version info if bnx(4) supports it. */ 6365 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 6366 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 6367 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 6368 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 6369 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 6370 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 6371 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 6372 BGE_APE_HOST_DRVR_STATE_START); 6373 event = BGE_APE_EVENT_STATUS_STATE_START; 6374 break; 6375 6376 case BNX_RESET_SHUTDOWN: 6377 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 6378 BGE_APE_HOST_DRVR_STATE_UNLOAD); 6379 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 6380 break; 6381 6382 case BNX_RESET_SUSPEND: 6383 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 6384 break; 6385 6386 default: 6387 return; 6388 } 6389 6390 bnx_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 6391 BGE_APE_EVENT_STATUS_STATE_CHNGE); 6392 } 6393