1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $ 35 */ 36 37 #ifndef _IF_BNXVAR_H_ 38 #define _IF_BNXVAR_H_ 39 40 /* 41 * Tigon general information block. This resides in host memory 42 * and contains the status counters, ring control blocks and 43 * producer pointers. 44 */ 45 46 struct bnx_gib { 47 struct bge_stats bnx_stats; 48 struct bge_rcb bnx_tx_rcb[16]; 49 struct bge_rcb bnx_std_rx_rcb; 50 struct bge_rcb bnx_jumbo_rx_rcb; 51 struct bge_rcb bnx_mini_rx_rcb; 52 struct bge_rcb bnx_return_rcb; 53 }; 54 55 #define BNX_MIN_FRAMELEN 60 56 #define BNX_MAX_FRAMELEN 1536 57 #define BNX_JUMBO_FRAMELEN 9018 58 #define BNX_JUMBO_MTU (BNX_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 59 60 #define BNX_TIMEOUT 5000 61 #define BNX_FIRMWARE_TIMEOUT 100000 62 #define BNX_TXCONS_UNSET 0xFFFF /* impossible value */ 63 64 /* 65 * Other utility macros. 66 */ 67 #define BNX_INC(x, y) (x) = ((x) + 1) % (y) 68 69 /* 70 * Register access macros. The Tigon always uses memory mapped register 71 * accesses and all registers must be accessed with 32 bit operations. 72 */ 73 74 #define CSR_WRITE_4(sc, reg, val) \ 75 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 76 77 #define CSR_READ_4(sc, reg) \ 78 bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 79 80 #define BNX_SETBIT(sc, reg, x) \ 81 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 82 83 #define BNX_CLRBIT(sc, reg, x) \ 84 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 85 86 #define BNX_MEMWIN_READ(sc, x, val) \ 87 do { \ 88 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \ 89 (0xFFFF0000 & x), 4); \ 90 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 91 } while(0) 92 93 #define BNX_MEMWIN_WRITE(sc, x, val) \ 94 do { \ 95 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \ 96 (0xFFFF0000 & x), 4); \ 97 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 98 } while(0) 99 100 #define RCB_WRITE_4(sc, rcb, offset, val) \ 101 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, \ 102 rcb + offsetof(struct bge_rcb, offset), val) 103 104 /* 105 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 106 * values are tuneable. They control the actual amount of buffers 107 * allocated for the standard, mini and jumbo receive rings. 108 */ 109 110 #define BNX_SSLOTS 256 111 #define BNX_MSLOTS 256 112 #define BNX_JSLOTS 384 113 114 #define BNX_JRAWLEN (BNX_JUMBO_FRAMELEN + ETHER_ALIGN) 115 #define BNX_JLEN (BNX_JRAWLEN + \ 116 (sizeof(uint64_t) - BNX_JRAWLEN % sizeof(uint64_t))) 117 #define BNX_JPAGESZ PAGE_SIZE 118 #define BNX_RESID (BNX_JPAGESZ - (BNX_JLEN * BNX_JSLOTS) % BNX_JPAGESZ) 119 #define BNX_JMEM ((BNX_JLEN * BNX_JSLOTS) + BNX_RESID) 120 121 struct bnx_softc; 122 123 struct bnx_jslot { 124 struct bnx_softc *bnx_sc; 125 void *bnx_buf; 126 bus_addr_t bnx_paddr; 127 int bnx_inuse; 128 int bnx_slot; 129 SLIST_ENTRY(bnx_jslot) jslot_link; 130 }; 131 132 /* 133 * Ring structures. Most of these reside in host memory and we tell 134 * the NIC where they are via the ring control blocks. The exceptions 135 * are the tx and command rings, which live in NIC memory and which 136 * we access via the shared memory window. 137 */ 138 struct bnx_ring_data { 139 struct bge_rx_bd *bnx_rx_std_ring; 140 bus_addr_t bnx_rx_std_ring_paddr; 141 struct bge_rx_bd *bnx_rx_jumbo_ring; 142 bus_addr_t bnx_rx_jumbo_ring_paddr; 143 struct bge_rx_bd *bnx_rx_return_ring; 144 bus_addr_t bnx_rx_return_ring_paddr; 145 struct bge_status_block *bnx_status_block; 146 bus_addr_t bnx_status_block_paddr; 147 void *bnx_jumbo_buf; 148 struct bnx_gib bnx_info; 149 }; 150 151 struct bnx_rxchain { 152 struct mbuf *bnx_mbuf; 153 bus_addr_t bnx_paddr; 154 }; 155 156 /* 157 * Mbuf pointers. We need these to keep track of the virtual addresses 158 * of our mbuf chains since we can only convert from physical to virtual, 159 * not the other way around. 160 */ 161 struct bnx_chain_data { 162 bus_dma_tag_t bnx_parent_tag; 163 bus_dma_tag_t bnx_rx_std_ring_tag; 164 bus_dma_tag_t bnx_rx_jumbo_ring_tag; 165 bus_dma_tag_t bnx_rx_return_ring_tag; 166 bus_dma_tag_t bnx_status_tag; 167 bus_dma_tag_t bnx_jumbo_tag; 168 bus_dma_tag_t bnx_rx_mtag; /* RX mbuf DMA tag */ 169 bus_dmamap_t bnx_rx_tmpmap; 170 bus_dmamap_t bnx_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 171 bus_dmamap_t bnx_rx_std_ring_map; 172 bus_dmamap_t bnx_rx_jumbo_ring_map; 173 bus_dmamap_t bnx_rx_return_ring_map; 174 bus_dmamap_t bnx_status_map; 175 bus_dmamap_t bnx_jumbo_map; 176 struct bnx_rxchain bnx_rx_std_chain[BGE_STD_RX_RING_CNT]; 177 struct bnx_rxchain bnx_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 178 /* Stick the jumbo mem management stuff here too. */ 179 struct bnx_jslot bnx_jslots[BNX_JSLOTS]; 180 }; 181 182 struct bnx_tx_buf { 183 bus_dmamap_t bnx_tx_dmamap; 184 struct mbuf *bnx_tx_mbuf; 185 }; 186 187 struct bnx_tx_ring { 188 struct bnx_softc *bnx_sc; 189 uint16_t bnx_tx_flags; 190 #define BNX_TX_FLAG_SHORTDMA 0x0001 191 #define BNX_TX_FLAG_FORCE_DEFRAG 0x0002 192 uint16_t bnx_tx_saved_considx; 193 int bnx_txcnt; 194 uint32_t bnx_tx_prodidx; 195 int bnx_tx_wreg; 196 int bnx_tx_mbx; 197 198 struct bge_tx_bd *bnx_tx_ring; 199 200 bus_dma_tag_t bnx_tx_mtag; /* TX mbuf DMA tag */ 201 struct bnx_tx_buf bnx_tx_buf[BGE_TX_RING_CNT]; 202 203 bus_dma_tag_t bnx_tx_ring_tag; 204 bus_dmamap_t bnx_tx_ring_map; 205 bus_addr_t bnx_tx_ring_paddr; 206 } __cachealign; 207 208 struct bnx_softc { 209 struct arpcom arpcom; /* interface info */ 210 device_t bnx_dev; 211 device_t bnx_miibus; 212 bus_space_handle_t bnx_bhandle; 213 bus_space_tag_t bnx_btag; 214 void *bnx_intrhand; 215 struct resource *bnx_irq; 216 int bnx_irq_type; 217 int bnx_irq_rid; 218 struct resource *bnx_res; 219 struct ifmedia bnx_ifmedia; /* TBI media info */ 220 int bnx_pciecap; 221 uint32_t bnx_status_tag; 222 uint32_t bnx_flags; /* BNX_FLAG_ */ 223 #define BNX_FLAG_TBI 0x00000001 224 #define BNX_FLAG_JUMBO 0x00000002 225 #define BNX_FLAG_ONESHOT_MSI 0x00000004 226 #define BNX_FLAG_5717_PLUS 0x00000008 227 #define BNX_FLAG_MII_SERDES 0x00000010 228 #define BNX_FLAG_CPMU 0x00000020 229 #define BNX_FLAG_57765_PLUS 0x00000040 230 #define BNX_FLAG_57765_FAMILY 0x00000080 231 #define BNX_FLAG_STATUSTAG_BUG 0x00000100 232 #define BNX_FLAG_TSO 0x00000200 233 #define BNX_FLAG_NO_EEPROM 0x10000000 234 235 uint32_t bnx_chipid; 236 uint32_t bnx_asicrev; 237 uint32_t bnx_chiprev; 238 struct bnx_ring_data bnx_ldata; /* rings */ 239 struct bnx_chain_data bnx_cdata; /* mbufs */ 240 int bnx_tx_ringcnt; 241 struct bnx_tx_ring *bnx_tx_ring; 242 uint16_t bnx_rx_saved_considx; 243 uint16_t bnx_std; /* current std ring head */ 244 uint16_t bnx_jumbo; /* current jumo ring head */ 245 SLIST_HEAD(__bnx_jfreehead, bnx_jslot) bnx_jfree_listhead; 246 struct lwkt_serialize bnx_jslot_serializer; 247 uint32_t bnx_rx_coal_ticks; 248 uint32_t bnx_tx_coal_ticks; 249 uint32_t bnx_rx_coal_bds; 250 uint32_t bnx_tx_coal_bds; 251 uint32_t bnx_rx_coal_bds_int; 252 uint32_t bnx_tx_coal_bds_int; 253 uint32_t bnx_mi_mode; 254 int bnx_if_flags; 255 int bnx_link; 256 int bnx_link_evt; 257 int bnx_stat_cpuid; 258 struct callout bnx_stat_timer; 259 struct ifpoll_compat bnx_npoll; 260 261 uint16_t bnx_rx_check_considx; 262 uint16_t bnx_tx_check_considx; 263 boolean_t bnx_intr_maylose; 264 int bnx_intr_cpuid; 265 struct callout bnx_intr_timer; 266 267 struct sysctl_ctx_list bnx_sysctl_ctx; 268 struct sysctl_oid *bnx_sysctl_tree; 269 270 int bnx_phyno; 271 uint32_t bnx_coal_chg; 272 #define BNX_RX_COAL_TICKS_CHG 0x01 273 #define BNX_TX_COAL_TICKS_CHG 0x02 274 #define BNX_RX_COAL_BDS_CHG 0x04 275 #define BNX_TX_COAL_BDS_CHG 0x08 276 #define BNX_RX_COAL_BDS_INT_CHG 0x40 277 #define BNX_TX_COAL_BDS_INT_CHG 0x80 278 279 void (*bnx_link_upd)(struct bnx_softc *, uint32_t); 280 uint32_t bnx_link_chg; 281 282 #define BNX_TSO_NSTATS 45 283 u_long bnx_tsosegs[BNX_TSO_NSTATS]; 284 }; 285 286 #define BNX_NSEG_NEW 40 287 #define BNX_NSEG_SPARE 33 /* enough for 64K TSO segment */ 288 #define BNX_NSEG_RSVD 4 289 290 /* RX coalesce ticks, unit: us */ 291 #define BNX_RX_COAL_TICKS_MIN 0 292 #define BNX_RX_COAL_TICKS_DEF 160 293 #define BNX_RX_COAL_TICKS_MAX 1023 294 295 /* TX coalesce ticks, unit: us */ 296 #define BNX_TX_COAL_TICKS_MIN 0 297 #define BNX_TX_COAL_TICKS_DEF 1023 298 #define BNX_TX_COAL_TICKS_MAX 1023 299 300 /* RX coalesce BDs */ 301 #define BNX_RX_COAL_BDS_MIN 0 302 #define BNX_RX_COAL_BDS_DEF 0 303 #define BNX_RX_COAL_BDS_INT_DEF 80 304 #define BNX_RX_COAL_BDS_MAX 255 305 306 /* TX coalesce BDs */ 307 #define BNX_TX_COAL_BDS_MIN 0 308 #define BNX_TX_COAL_BDS_DEF 64 309 #define BNX_TX_COAL_BDS_INT_DEF 64 310 #define BNX_TX_COAL_BDS_MAX 255 311 312 /* Number of segments sent before writing to TX related registers */ 313 #define BNX_TX_WREG_NSEGS 8 314 315 /* Return ring descriptor count */ 316 #define BNX_RETURN_RING_CNT 512 317 318 #endif /* !_IF_BNXVAR_H_ */ 319