1 /*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/bwn/if_bwnvar.h 228399 2011-12-10 21:05:06Z eadler $ 30 */ 31 32 #ifndef _IF_BWNVAR_H 33 #define _IF_BWNVAR_H 34 35 #include <netproto/802_11/ieee80211_amrr.h> 36 37 struct siba_dev_softc; 38 struct bwn_softc; 39 struct bwn_mac; 40 41 #define N(a) (sizeof(a) / sizeof(a[0])) 42 #define BWN_ALIGN 0x2000 43 #define BWN_BUS_SPACE_MAXADDR_30BIT 0x3fffffff 44 #define BWN_RETRY_SHORT 7 45 #define BWN_RETRY_LONG 4 46 #define BWN_STAID_MAX 64 47 #define BWN_TXPWR_IGNORE_TIME (1 << 0) 48 #define BWN_TXPWR_IGNORE_TSSI (1 << 1) 49 #define BWN_HAS_TXMAG(phy) \ 50 (((phy)->rev >= 2) && ((phy)->rf_ver == 0x2050) && \ 51 ((phy)->rf_rev == 8)) 52 #define BWN_HAS_LOOPBACK(phy) \ 53 (((phy)->rev > 1) || ((phy)->gmode)) 54 #define BWN_TXERROR_MAX 1000 55 #define BWN_GETTIME(v) do { \ 56 struct timespec ts; \ 57 nanouptime(&ts); \ 58 (v) = ts.tv_nsec / 1000000 + ts.tv_sec * 1000; \ 59 } while (0) 60 #define BWN_ISOLDFMT(mac) ((mac)->mac_fw.rev <= 351) 61 #define BWN_TSSI2DBM(num, den) \ 62 ((int32_t)((num < 0) ? num / den : (num + den / 2) / den)) 63 #define BWN_MAX_HDRSIZE(mac) (104 + sizeof(struct bwn_plcp6)) 64 #define BWN_HDRSIZE(mac) \ 65 ((BWN_ISOLDFMT(mac)) ? (100 + sizeof(struct bwn_plcp6)) : \ 66 (104 + sizeof(struct bwn_plcp6))) 67 #define BWN_PIO_COOKIE(tq, tp) \ 68 ((uint16_t)((((uint16_t)tq->tq_index + 1) << 12) | tp->tp_index)) 69 #define BWN_DMA_COOKIE(dr, slot) \ 70 ((uint16_t)(((uint16_t)dr->dr_index + 1) << 12) | (uint16_t)slot) 71 #define BWN_READ_2(mac, o) (siba_read_2(mac->mac_sc->sc_dev, o)) 72 #define BWN_READ_4(mac, o) (siba_read_4(mac->mac_sc->sc_dev, o)) 73 #define BWN_WRITE_2(mac, o, v) \ 74 (siba_write_2(mac->mac_sc->sc_dev, o, v)) 75 #define BWN_WRITE_4(mac, o, v) \ 76 (siba_write_4(mac->mac_sc->sc_dev, o, v)) 77 #define BWN_PIO_TXQOFFSET(mac) \ 78 ((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0) 79 #define BWN_PIO_RXQOFFSET(mac) \ 80 ((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8) 81 #define BWN_SEC_NEWAPI(mac) (mac->mac_fw.rev >= 351) 82 #define BWN_SEC_KEY2FW(mac, idx) \ 83 (BWN_SEC_NEWAPI(mac) ? idx : ((idx >= 4) ? idx - 4 : idx)) 84 #define BWN_RF_READ(mac, r) (mac->mac_phy.rf_read(mac, r)) 85 #define BWN_RF_WRITE(mac, r, v) (mac->mac_phy.rf_write(mac, r, v)) 86 #define BWN_RF_MASK(mac, o, m) \ 87 BWN_RF_WRITE(mac, o, BWN_RF_READ(mac, o) & m) 88 #define BWN_RF_SETMASK(mac, offset, mask, set) \ 89 BWN_RF_WRITE(mac, offset, (BWN_RF_READ(mac, offset) & mask) | set) 90 #define BWN_RF_SET(mac, offset, set) \ 91 BWN_RF_WRITE(mac, offset, BWN_RF_READ(mac, offset) | set) 92 #define BWN_PHY_READ(mac, r) (mac->mac_phy.phy_read(mac, r)) 93 #define BWN_PHY_WRITE(mac, r, v) \ 94 (mac->mac_phy.phy_write(mac, r, v)) 95 #define BWN_PHY_SET(mac, offset, set) do { \ 96 if (mac->mac_phy.phy_maskset != NULL) { \ 97 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ 98 mac->mac_suspended > 0, \ 99 ("dont access PHY or RF registers after turning on MAC")); \ 100 mac->mac_phy.phy_maskset(mac, offset, 0xffff, set); \ 101 } else \ 102 BWN_PHY_WRITE(mac, offset, \ 103 BWN_PHY_READ(mac, offset) | (set)); \ 104 } while (0) 105 #define BWN_PHY_SETMASK(mac, offset, mask, set) do { \ 106 if (mac->mac_phy.phy_maskset != NULL) { \ 107 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ 108 mac->mac_suspended > 0, \ 109 ("dont access PHY or RF registers after turning on MAC")); \ 110 mac->mac_phy.phy_maskset(mac, offset, mask, set); \ 111 } else \ 112 BWN_PHY_WRITE(mac, offset, \ 113 (BWN_PHY_READ(mac, offset) & (mask)) | (set)); \ 114 } while (0) 115 #define BWN_PHY_MASK(mac, offset, mask) do { \ 116 if (mac->mac_phy.phy_maskset != NULL) { \ 117 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ 118 mac->mac_suspended > 0, \ 119 ("dont access PHY or RF registers after turning on MAC")); \ 120 mac->mac_phy.phy_maskset(mac, offset, mask, 0); \ 121 } else \ 122 BWN_PHY_WRITE(mac, offset, \ 123 BWN_PHY_READ(mac, offset) & mask); \ 124 } while (0) 125 #define BWN_PHY_COPY(mac, dst, src) do { \ 126 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ 127 mac->mac_suspended > 0, \ 128 ("dont access PHY or RF registers after turning on MAC")); \ 129 BWN_PHY_WRITE(mac, dst, BWN_PHY_READ(mac, src)); \ 130 } while (0) 131 #define BWN_LO_CALIB_EXPIRE (1000 * (30 - 2)) 132 #define BWN_LO_PWRVEC_EXPIRE (1000 * (30 - 2)) 133 #define BWN_LO_TXCTL_EXPIRE (1000 * (180 - 4)) 134 #define BWN_DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) 135 #define BWN_LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0)) 136 #define BWN_BITREV4(tmp) (BWN_BITREV8(tmp) >> 4) 137 #define BWN_BITREV8(byte) (bwn_bitrev_table[byte]) 138 #define BWN_BBATTCMP(a, b) ((a)->att == (b)->att) 139 #define BWN_RFATTCMP(a, b) \ 140 (((a)->att == (b)->att) && ((a)->padmix == (b)->padmix)) 141 #define BWN_PIO_WRITE_2(mac, tq, offset, value) \ 142 BWN_WRITE_2(mac, (tq)->tq_base + offset, value) 143 #define BWN_PIO_READ_4(mac, tq, offset) \ 144 BWN_READ_4(mac, tq->tq_base + offset) 145 #define BWN_ISCCKRATE(rate) \ 146 (rate == BWN_CCK_RATE_1MB || rate == BWN_CCK_RATE_2MB || \ 147 rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB) 148 #define BWN_ISOFDMRATE(rate) (!BWN_ISCCKRATE(rate)) 149 #define BWN_BARRIER(mac, flags) siba_barrier(mac->mac_sc->sc_dev, flags) 150 #define BWN_DMA_READ(dr, offset) \ 151 (BWN_READ_4(dr->dr_mac, dr->dr_base + offset)) 152 #define BWN_DMA_WRITE(dr, offset, value) \ 153 (BWN_WRITE_4(dr->dr_mac, dr->dr_base + offset, value)) 154 155 struct bwn_rate { 156 uint16_t rateid; 157 uint32_t flags; 158 }; 159 160 #define BWN_ANT0 0 161 #define BWN_ANT1 1 162 #define BWN_ANTAUTO0 2 163 #define BWN_ANTAUTO1 3 164 #define BWN_ANT2 4 165 #define BWN_ANT3 8 166 #define BWN_ANTAUTO BWN_ANTAUTO0 167 #define BWN_ANT_DEFAULT BWN_ANTAUTO 168 #define BWN_TX_SLOTS_PER_FRAME 2 169 170 struct bwn_channel { 171 unsigned freq; 172 unsigned ieee; 173 unsigned maxTxPow; 174 }; 175 176 struct bwn_channelinfo { 177 struct bwn_channel channels[IEEE80211_CHAN_MAX]; 178 unsigned nchannels; 179 }; 180 181 struct bwn_bbatt { 182 uint8_t att; 183 }; 184 185 struct bwn_bbatt_list { 186 const struct bwn_bbatt *array; 187 uint8_t len; 188 uint8_t min; 189 uint8_t max; 190 }; 191 192 struct bwn_rfatt { 193 uint8_t att; 194 int padmix; 195 }; 196 197 struct bwn_rfatt_list { 198 const struct bwn_rfatt *array; 199 uint8_t len; 200 uint8_t min; 201 uint8_t max; 202 }; 203 204 #define BWN_DC_LT_SIZE 32 205 206 struct bwn_loctl { 207 int8_t i; 208 int8_t q; 209 }; 210 211 struct bwn_lo_calib { 212 struct bwn_bbatt bbatt; 213 struct bwn_rfatt rfatt; 214 struct bwn_loctl ctl; 215 unsigned long calib_time; 216 TAILQ_ENTRY(bwn_lo_calib) list; 217 }; 218 219 struct bwn_rxhdr4 { 220 uint16_t frame_len; 221 uint8_t pad1[2]; 222 uint16_t phy_status0; 223 union { 224 struct { 225 uint8_t rssi; 226 uint8_t sig_qual; 227 } __packed abg; 228 struct { 229 int8_t power0; 230 int8_t power1; 231 } __packed n; 232 } __packed phy; 233 uint16_t phy_status2; 234 uint16_t phy_status3; 235 uint32_t mac_status; 236 uint16_t mac_time; 237 uint16_t channel; 238 } __packed; 239 240 struct bwn_txstatus { 241 uint16_t cookie; 242 uint16_t seq; 243 uint8_t phy_stat; 244 uint8_t framecnt; 245 uint8_t rtscnt; 246 uint8_t sreason; 247 uint8_t pm; 248 uint8_t im; 249 uint8_t ampdu; 250 uint8_t ack; 251 }; 252 253 #define BWN_TXCTL_PA3DB 0x40 254 #define BWN_TXCTL_PA2DB 0x20 255 #define BWN_TXCTL_TXMIX 0x10 256 257 struct bwn_txpwr_loctl { 258 struct bwn_rfatt_list rfatt; 259 struct bwn_bbatt_list bbatt; 260 uint16_t dc_lt[BWN_DC_LT_SIZE]; 261 TAILQ_HEAD(, bwn_lo_calib) calib_list; 262 unsigned long pwr_vec_read_time; 263 unsigned long txctl_measured_time; 264 uint8_t tx_bias; 265 uint8_t tx_magn; 266 uint64_t power_vector; 267 }; 268 269 #define BWN_OFDMTAB_DIR_UNKNOWN 0 270 #define BWN_OFDMTAB_DIR_READ 1 271 #define BWN_OFDMTAB_DIR_WRITE 2 272 273 struct bwn_phy_g { 274 unsigned pg_flags; 275 #define BWN_PHY_G_FLAG_TSSITABLE_ALLOC (1 << 0) 276 #define BWN_PHY_G_FLAG_RADIOCTX_VALID (1 << 1) 277 int pg_aci_enable; 278 int pg_aci_wlan_automatic; 279 int pg_aci_hw_rssi; 280 int pg_rf_on; 281 uint16_t pg_radioctx_over; 282 uint16_t pg_radioctx_overval; 283 uint16_t pg_minlowsig[2]; 284 uint16_t pg_minlowsigpos[2]; 285 int8_t *pg_tssi2dbm; 286 int pg_idletssi; 287 int pg_curtssi; 288 uint8_t pg_avgtssi; 289 struct bwn_bbatt pg_bbatt; 290 struct bwn_rfatt pg_rfatt; 291 uint8_t pg_txctl; 292 int pg_bbatt_delta; 293 int pg_rfatt_delta; 294 295 struct bwn_txpwr_loctl pg_loctl; 296 int16_t pg_max_lb_gain; 297 int16_t pg_trsw_rx_gain; 298 int16_t pg_lna_lod_gain; 299 int16_t pg_lna_gain; 300 int16_t pg_pga_gain; 301 int pg_immode; 302 #define BWN_INTERFSTACK_SIZE 26 303 uint32_t pg_interfstack[BWN_INTERFSTACK_SIZE]; 304 305 int16_t pg_nrssi[2]; 306 int32_t pg_nrssi_slope; 307 int8_t pg_nrssi_lt[64]; 308 309 uint16_t pg_lofcal; 310 311 uint16_t pg_initval; 312 uint16_t pg_ofdmtab_addr; 313 unsigned pg_ofdmtab_dir; 314 }; 315 316 #define BWN_IMMODE_NONE 0 317 #define BWN_IMMODE_NONWLAN 1 318 #define BWN_IMMODE_MANUAL 2 319 #define BWN_IMMODE_AUTO 3 320 #define BWN_TXPWR_RES_NEED_ADJUST 0 321 #define BWN_TXPWR_RES_DONE 1 322 323 #define BWN_PHYLP_TXPCTL_UNKNOWN 0 324 #define BWN_PHYLP_TXPCTL_OFF 1 325 #define BWN_PHYLP_TXPCTL_ON_SW 2 326 #define BWN_PHYLP_TXPCTL_ON_HW 3 327 328 struct bwn_phy_lp { 329 uint8_t plp_chan; 330 uint8_t plp_chanfullcal; 331 int32_t plp_antenna; 332 uint8_t plp_txpctlmode; 333 uint8_t plp_txisoband_h; 334 uint8_t plp_txisoband_m; 335 uint8_t plp_txisoband_l; 336 uint8_t plp_rxpwroffset; 337 int8_t plp_txpwridx; 338 uint16_t plp_tssiidx; 339 uint16_t plp_tssinpt; 340 uint8_t plp_rssivf; 341 uint8_t plp_rssivc; 342 uint8_t plp_rssigs; 343 uint8_t plp_rccap; 344 uint8_t plp_bxarch; 345 uint8_t plp_crsusr_off; 346 uint8_t plp_crssys_off; 347 uint32_t plp_div; 348 int32_t plp_tonefreq; 349 uint16_t plp_digfilt[9]; 350 }; 351 352 /* for LP */ 353 struct bwn_txgain { 354 uint16_t tg_gm; 355 uint16_t tg_pga; 356 uint16_t tg_pad; 357 uint16_t tg_dac; 358 }; 359 360 struct bwn_rxcompco { 361 uint8_t rc_chan; 362 int8_t rc_c1; 363 int8_t rc_c0; 364 }; 365 366 struct bwn_phy_lp_iq_est { 367 uint32_t ie_iqprod; 368 uint32_t ie_ipwr; 369 uint32_t ie_qpwr; 370 }; 371 372 struct bwn_txgain_entry { 373 uint8_t te_gm; 374 uint8_t te_pga; 375 uint8_t te_pad; 376 uint8_t te_dac; 377 uint8_t te_bbmult; 378 }; 379 380 /* only for LP PHY */ 381 struct bwn_stxtable { 382 uint16_t st_phyoffset; 383 uint16_t st_physhift; 384 uint16_t st_rfaddr; 385 uint16_t st_rfshift; 386 uint16_t st_mask; 387 }; 388 389 struct bwn_b206x_chan { 390 uint8_t bc_chan; 391 uint16_t bc_freq; 392 const uint8_t *bc_data; 393 }; 394 395 struct bwn_b206x_rfinit_entry { 396 uint16_t br_offset; 397 uint16_t br_valuea; 398 uint16_t br_valueg; 399 uint8_t br_flags; 400 }; 401 402 struct bwn_phy { 403 uint8_t type; 404 uint8_t rev; 405 uint8_t analog; 406 407 int supports_2ghz; 408 int supports_5ghz; 409 410 int gmode; 411 struct bwn_phy_g phy_g; 412 struct bwn_phy_lp phy_lp; 413 414 uint16_t rf_manuf; 415 uint16_t rf_ver; 416 uint8_t rf_rev; 417 int rf_on; 418 419 int txpower; 420 int hwpctl; 421 unsigned long nexttime; 422 unsigned int chan; 423 int txerrors; 424 425 int (*attach)(struct bwn_mac *); 426 void (*detach)(struct bwn_mac *); 427 int (*prepare_hw)(struct bwn_mac *); 428 void (*init_pre)(struct bwn_mac *); 429 int (*init)(struct bwn_mac *); 430 void (*exit)(struct bwn_mac *); 431 uint16_t (*phy_read)(struct bwn_mac *, uint16_t); 432 void (*phy_write)(struct bwn_mac *, uint16_t, 433 uint16_t); 434 void (*phy_maskset)(struct bwn_mac *, 435 uint16_t, uint16_t, uint16_t); 436 uint16_t (*rf_read)(struct bwn_mac *, uint16_t); 437 void (*rf_write)(struct bwn_mac *, uint16_t, 438 uint16_t); 439 int (*use_hwpctl)(struct bwn_mac *); 440 void (*rf_onoff)(struct bwn_mac *, int); 441 void (*switch_analog)(struct bwn_mac *, int); 442 int (*switch_channel)(struct bwn_mac *, 443 unsigned int); 444 uint32_t (*get_default_chan)(struct bwn_mac *); 445 void (*set_antenna)(struct bwn_mac *, int); 446 int (*set_im)(struct bwn_mac *, int); 447 int (*recalc_txpwr)(struct bwn_mac *, int); 448 void (*set_txpwr)(struct bwn_mac *); 449 void (*task_15s)(struct bwn_mac *); 450 void (*task_60s)(struct bwn_mac *); 451 }; 452 453 struct bwn_chan_band { 454 uint32_t flags; 455 uint8_t nchan; 456 #define BWN_MAX_CHAN_PER_BAND 14 457 uint8_t chan[BWN_MAX_CHAN_PER_BAND]; 458 }; 459 460 #define BWN_NR_WMEPARAMS 16 461 enum { 462 BWN_WMEPARAM_TXOP = 0, 463 BWN_WMEPARAM_CWMIN, 464 BWN_WMEPARAM_CWMAX, 465 BWN_WMEPARAM_CWCUR, 466 BWN_WMEPARAM_AIFS, 467 BWN_WMEPARAM_BSLOTS, 468 BWN_WMEPARAM_REGGAP, 469 BWN_WMEPARAM_STATUS, 470 }; 471 472 #define BWN_WME_PARAMS(queue) \ 473 (BWN_SHARED_EDCFQ + (BWN_NR_WMEPARAMS * sizeof(uint16_t) * (queue))) 474 #define BWN_WME_BACKGROUND BWN_WME_PARAMS(0) 475 #define BWN_WME_BESTEFFORT BWN_WME_PARAMS(1) 476 #define BWN_WME_VIDEO BWN_WME_PARAMS(2) 477 #define BWN_WME_VOICE BWN_WME_PARAMS(3) 478 479 /* 480 * Radio capture format. 481 */ 482 #define BWN_RX_RADIOTAP_PRESENT ( \ 483 (1 << IEEE80211_RADIOTAP_TSFT) | \ 484 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 485 (1 << IEEE80211_RADIOTAP_RATE) | \ 486 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 487 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 488 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 489 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 490 0) 491 492 struct bwn_rx_radiotap_header { 493 struct ieee80211_radiotap_header wr_ihdr; 494 uint64_t wr_tsf; 495 u_int8_t wr_flags; 496 u_int8_t wr_rate; 497 u_int16_t wr_chan_freq; 498 u_int16_t wr_chan_flags; 499 int8_t wr_antsignal; 500 int8_t wr_antnoise; 501 u_int8_t wr_antenna; 502 }; 503 504 #define BWN_TX_RADIOTAP_PRESENT ( \ 505 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 506 (1 << IEEE80211_RADIOTAP_RATE) | \ 507 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 508 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 509 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 510 0) 511 512 struct bwn_tx_radiotap_header { 513 struct ieee80211_radiotap_header wt_ihdr; 514 u_int8_t wt_flags; 515 u_int8_t wt_rate; 516 u_int16_t wt_chan_freq; 517 u_int16_t wt_chan_flags; 518 u_int8_t wt_txpower; 519 u_int8_t wt_antenna; 520 }; 521 522 struct bwn_stats { 523 int32_t rtsfail; 524 int32_t rts; 525 int32_t link_noise; 526 }; 527 528 /* Noise Calculation (Link Quality) */ 529 struct bwn_noise { 530 uint8_t noi_running; 531 uint8_t noi_nsamples; 532 int8_t noi_samples[8][4]; 533 }; 534 535 #define BWN_DMA_30BIT 30 536 #define BWN_DMA_32BIT 32 537 #define BWN_DMA_64BIT 64 538 539 struct bwn_dmadesc_meta { 540 bus_dmamap_t mt_dmap; 541 bus_addr_t mt_paddr; 542 struct mbuf *mt_m; 543 struct ieee80211_node *mt_ni; 544 uint8_t mt_txtype; 545 #define BWN_DMADESC_METATYPE_HEADER 0 546 #define BWN_DMADESC_METATYPE_BODY 1 547 uint8_t mt_islast; 548 }; 549 550 #define BWN_DMAINTR_FATALMASK \ 551 ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 14) | (1 << 15)) 552 #define BWN_DMAINTR_RDESC_UFLOW (1 << 13) 553 #define BWN_DMAINTR_RX_DONE (1 << 16) 554 555 #define BWN_DMA32_DCTL_BYTECNT 0x00001fff 556 #define BWN_DMA32_DCTL_ADDREXT_MASK 0x00030000 557 #define BWN_DMA32_DCTL_ADDREXT_SHIFT 16 558 #define BWN_DMA32_DCTL_DTABLEEND 0x10000000 559 #define BWN_DMA32_DCTL_IRQ 0x20000000 560 #define BWN_DMA32_DCTL_FRAMEEND 0x40000000 561 #define BWN_DMA32_DCTL_FRAMESTART 0x80000000 562 struct bwn_dmadesc32 { 563 uint32_t control; 564 uint32_t address; 565 } __packed; 566 567 #define BWN_DMA64_DCTL0_DTABLEEND 0x10000000 568 #define BWN_DMA64_DCTL0_IRQ 0x20000000 569 #define BWN_DMA64_DCTL0_FRAMEEND 0x40000000 570 #define BWN_DMA64_DCTL0_FRAMESTART 0x80000000 571 #define BWN_DMA64_DCTL1_BYTECNT 0x00001fff 572 #define BWN_DMA64_DCTL1_ADDREXT_MASK 0x00030000 573 #define BWN_DMA64_DCTL1_ADDREXT_SHIFT 16 574 struct bwn_dmadesc64 { 575 uint32_t control0; 576 uint32_t control1; 577 uint32_t address_low; 578 uint32_t address_high; 579 } __packed; 580 581 struct bwn_dmadesc_generic { 582 union { 583 struct bwn_dmadesc32 dma32; 584 struct bwn_dmadesc64 dma64; 585 } __packed dma; 586 } __packed; 587 588 struct bwn_dma_ring; 589 590 struct bwn_dma_ring { 591 struct bwn_mac *dr_mac; 592 const struct bwn_dma_ops *dr_ops; 593 struct bwn_dmadesc_meta *dr_meta; 594 void *dr_txhdr_cache; 595 bus_dma_tag_t dr_ring_dtag; 596 bus_dma_tag_t dr_txring_dtag; 597 bus_dmamap_t dr_txring_dmap; 598 bus_dmamap_t dr_spare_dmap; /* only for RX */ 599 bus_dmamap_t dr_ring_dmap; 600 bus_addr_t dr_txring_paddr; 601 void *dr_ring_descbase; 602 bus_addr_t dr_ring_dmabase; 603 int dr_numslots; 604 int dr_usedslot; 605 int dr_curslot; 606 uint32_t dr_frameoffset; 607 uint16_t dr_rx_bufsize; 608 uint16_t dr_base; 609 int dr_index; 610 uint8_t dr_tx; 611 uint8_t dr_stop; 612 int dr_type; 613 614 void (*getdesc)(struct bwn_dma_ring *, 615 int, struct bwn_dmadesc_generic **, 616 struct bwn_dmadesc_meta **); 617 void (*setdesc)(struct bwn_dma_ring *, 618 struct bwn_dmadesc_generic *, 619 bus_addr_t, uint16_t, int, int, 620 int); 621 void (*start_transfer)(struct bwn_dma_ring *, 622 int); 623 void (*suspend)(struct bwn_dma_ring *); 624 void (*resume)(struct bwn_dma_ring *); 625 int (*get_curslot)(struct bwn_dma_ring *); 626 void (*set_curslot)(struct bwn_dma_ring *, 627 int); 628 }; 629 630 struct bwn_dma { 631 int dmatype; 632 bus_dma_tag_t parent_dtag; 633 bus_dma_tag_t rxbuf_dtag; 634 bus_dma_tag_t txbuf_dtag; 635 636 struct bwn_dma_ring *wme[5]; 637 struct bwn_dma_ring *mcast; 638 struct bwn_dma_ring *rx; 639 uint64_t lastseq; /* XXX FIXME */ 640 }; 641 642 struct bwn_pio_rxqueue { 643 struct bwn_mac *prq_mac; 644 uint16_t prq_base; 645 uint8_t prq_rev; 646 }; 647 648 struct bwn_pio_txqueue; 649 struct bwn_pio_txpkt { 650 struct bwn_pio_txqueue *tp_queue; 651 struct ieee80211_node *tp_ni; 652 struct mbuf *tp_m; 653 uint8_t tp_index; 654 TAILQ_ENTRY(bwn_pio_txpkt) tp_list; 655 }; 656 657 #define BWN_PIO_MAX_TXPACKETS 32 658 struct bwn_pio_txqueue { 659 uint16_t tq_base; 660 uint16_t tq_size; 661 uint16_t tq_used; 662 uint16_t tq_free; 663 uint8_t tq_stop; 664 uint8_t tq_index; 665 struct bwn_pio_txpkt tq_pkts[BWN_PIO_MAX_TXPACKETS]; 666 TAILQ_HEAD(, bwn_pio_txpkt) tq_pktlist; 667 }; 668 669 struct bwn_pio { 670 struct bwn_pio_txqueue wme[5]; 671 struct bwn_pio_txqueue mcast; 672 struct bwn_pio_rxqueue rx; 673 }; 674 675 struct bwn_plcp4 { 676 union { 677 uint32_t data; 678 uint8_t raw[4]; 679 } __packed o; 680 } __packed; 681 682 struct bwn_plcp6 { 683 union { 684 uint32_t data; 685 uint8_t raw[6]; 686 } __packed o; 687 } __packed; 688 689 struct bwn_txhdr { 690 uint32_t macctl; 691 uint8_t macfc[2]; 692 uint16_t tx_festime; 693 uint16_t phyctl; 694 uint16_t phyctl_1; 695 uint16_t phyctl_1fb; 696 uint16_t phyctl_1rts; 697 uint16_t phyctl_1rtsfb; 698 uint8_t phyrate; 699 uint8_t phyrate_rts; 700 uint8_t eftypes; /* extra frame types */ 701 uint8_t chan; 702 uint8_t iv[16]; 703 uint8_t addr1[IEEE80211_ADDR_LEN]; 704 uint16_t tx_festime_fb; 705 struct bwn_plcp6 rts_plcp_fb; 706 uint16_t rts_dur_fb; 707 struct bwn_plcp6 plcp_fb; 708 uint16_t dur_fb; 709 uint16_t mimo_modelen; 710 uint16_t mimo_ratelen_fb; 711 uint32_t timeout; 712 713 union { 714 /* format <= r351 */ 715 struct { 716 uint8_t pad0[2]; 717 uint16_t cookie; 718 uint16_t tx_status; 719 struct bwn_plcp6 rts_plcp; 720 uint8_t rts_frame[16]; 721 uint8_t pad1[2]; 722 struct bwn_plcp6 plcp; 723 } __packed old; 724 /* format > r410 */ 725 struct { 726 uint16_t mimo_antenna; 727 uint16_t preload_size; 728 uint8_t pad0[2]; 729 uint16_t cookie; 730 uint16_t tx_status; 731 struct bwn_plcp6 rts_plcp; 732 uint8_t rts_frame[16]; 733 uint8_t pad1[2]; 734 struct bwn_plcp6 plcp; 735 } __packed new; 736 } __packed body; 737 } __packed; 738 739 #define BWN_FWTYPE_UCODE 'u' 740 #define BWN_FWTYPE_PCM 'p' 741 #define BWN_FWTYPE_IV 'i' 742 struct bwn_fwhdr { 743 uint8_t type; 744 uint8_t ver; 745 uint8_t pad[2]; 746 uint32_t size; 747 } __packed; 748 749 #define BWN_FWINITVALS_OFFSET_MASK 0x7fff 750 #define BWN_FWINITVALS_32BIT 0x8000 751 struct bwn_fwinitvals { 752 uint16_t offset_size; 753 union { 754 uint16_t d16; 755 uint32_t d32; 756 } __packed data; 757 } __packed; 758 759 enum bwn_fwtype { 760 BWN_FWTYPE_DEFAULT, 761 BWN_FWTYPE_OPENSOURCE, 762 BWN_NR_FWTYPES, 763 }; 764 765 struct bwn_fwfile { 766 const char *filename; 767 const struct firmware *fw; 768 enum bwn_fwtype type; 769 }; 770 771 struct bwn_key { 772 void *keyconf; 773 uint8_t algorithm; 774 }; 775 776 struct bwn_fw { 777 struct bwn_fwfile ucode; 778 struct bwn_fwfile pcm; 779 struct bwn_fwfile initvals; 780 struct bwn_fwfile initvals_band; 781 782 uint16_t rev; 783 uint16_t patch; 784 uint8_t opensource; 785 uint8_t no_pcmfile; 786 }; 787 788 struct bwn_lo_g_sm { 789 int curstate; 790 int nmeasure; 791 int multipler; 792 uint16_t feedth; 793 struct bwn_loctl loctl; 794 }; 795 796 struct bwn_lo_g_value { 797 uint8_t old_channel; 798 uint16_t phy_lomask; 799 uint16_t phy_extg; 800 uint16_t phy_dacctl_hwpctl; 801 uint16_t phy_dacctl; 802 uint16_t phy_hpwr_tssictl; 803 uint16_t phy_analogover; 804 uint16_t phy_analogoverval; 805 uint16_t phy_rfover; 806 uint16_t phy_rfoverval; 807 uint16_t phy_classctl; 808 uint16_t phy_crs0; 809 uint16_t phy_pgactl; 810 uint16_t phy_syncctl; 811 uint16_t phy_cck0; 812 uint16_t phy_cck1; 813 uint16_t phy_cck2; 814 uint16_t phy_cck3; 815 uint16_t phy_cck4; 816 uint16_t reg0; 817 uint16_t reg1; 818 uint16_t rf0; 819 uint16_t rf1; 820 uint16_t rf2; 821 }; 822 823 #define BWN_LED_MAX 4 824 825 #define BWN_LED_EVENT_NONE -1 826 #define BWN_LED_EVENT_POLL 0 827 #define BWN_LED_EVENT_TX 1 828 #define BWN_LED_EVENT_RX 2 829 #define BWN_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2) 830 831 struct bwn_led { 832 uint8_t led_flags; /* BWN_LED_F_ */ 833 uint8_t led_act; /* BWN_LED_ACT_ */ 834 uint8_t led_mask; 835 }; 836 837 #define BWN_LED_F_ACTLOW 0x1 838 #define BWN_LED_F_BLINK 0x2 839 #define BWN_LED_F_POLLABLE 0x4 840 #define BWN_LED_F_SLOW 0x8 841 842 struct bwn_mac { 843 struct bwn_softc *mac_sc; 844 unsigned mac_status; 845 #define BWN_MAC_STATUS_UNINIT 0 846 #define BWN_MAC_STATUS_INITED 1 847 #define BWN_MAC_STATUS_STARTED 2 848 unsigned mac_flags; 849 /* use "Bad Frames Preemption" */ 850 #define BWN_MAC_FLAG_BADFRAME_PREEMP (1 << 0) 851 #define BWN_MAC_FLAG_DFQVALID (1 << 1) 852 #define BWN_MAC_FLAG_RADIO_ON (1 << 2) 853 #define BWN_MAC_FLAG_DMA (1 << 3) 854 #define BWN_MAC_FLAG_WME (1 << 4) 855 #define BWN_MAC_FLAG_HWCRYPTO (1 << 5) 856 857 struct bwn_noise mac_noise; 858 struct bwn_phy mac_phy; 859 struct bwn_stats mac_stats; 860 uint32_t mac_reason_intr; 861 uint32_t mac_reason[6]; 862 uint32_t mac_intr_mask; 863 int mac_suspended; 864 865 struct bwn_fw mac_fw; 866 867 union { 868 struct bwn_dma dma; 869 struct bwn_pio pio; 870 } mac_method; 871 872 uint16_t mac_ktp; /* Key table pointer */ 873 uint8_t mac_max_nr_keys; 874 struct bwn_key mac_key[58]; 875 876 unsigned int mac_task_state; 877 struct task mac_intrtask; 878 struct task mac_hwreset; 879 struct task mac_txpower; 880 881 TAILQ_ENTRY(bwn_mac) mac_list; 882 }; 883 884 /* 885 * Driver-specific vap state. 886 */ 887 struct bwn_vap { 888 struct ieee80211vap bv_vap; /* base class */ 889 int (*bv_newstate)(struct ieee80211vap *, 890 enum ieee80211_state, int); 891 }; 892 #define BWN_VAP(vap) ((struct bwn_vap *)(vap)) 893 #define BWN_VAP_CONST(vap) ((const struct mwl_vap *)(vap)) 894 895 struct bwn_softc { 896 device_t sc_dev; 897 struct ifnet *sc_ifp; 898 unsigned sc_flags; 899 #define BWN_FLAG_ATTACHED (1 << 0) 900 #define BWN_FLAG_INVALID (1 << 1) 901 #define BWN_FLAG_NEED_BEACON_TP (1 << 2) 902 struct sysctl_ctx_list sc_sysctl_ctx; 903 struct sysctl_oid *sc_sysctl_tree; 904 unsigned sc_debug; 905 906 struct bwn_mac *sc_curmac; 907 TAILQ_HEAD(, bwn_mac) sc_maclist; 908 909 uint8_t sc_macaddr[IEEE80211_ADDR_LEN]; 910 uint8_t sc_bssid[IEEE80211_ADDR_LEN]; 911 unsigned int sc_filters; 912 uint8_t sc_beacons[2]; 913 uint8_t sc_rf_enabled; 914 915 struct wmeParams sc_wmeParams[4]; 916 917 struct callout sc_rfswitch_ch; /* for laptop */ 918 struct callout sc_task_ch; 919 struct callout sc_watchdog_ch; 920 int sc_watchdog_timer; 921 struct taskqueue *sc_tq; /* private task queue */ 922 int (*sc_newstate)(struct ieee80211com *, 923 enum ieee80211_state, int); 924 void (*sc_node_cleanup)( 925 struct ieee80211_node *); 926 927 int sc_rx_rate; 928 int sc_tx_rate; 929 930 int sc_led_blinking; 931 int sc_led_ticks; 932 struct bwn_led *sc_blink_led; 933 struct callout sc_led_blink_ch; 934 int sc_led_blink_offdur; 935 struct bwn_led sc_leds[BWN_LED_MAX]; 936 int sc_led_idle; 937 int sc_led_blink; 938 939 struct resource *bwn_irq; 940 void *bwn_intr; 941 int bwn_irq_rid; 942 int bwn_irq_type; 943 944 struct bwn_tx_radiotap_header sc_tx_th; 945 struct bwn_rx_radiotap_header sc_rx_th; 946 }; 947 948 #endif /* !_IF_BWNVAR_H */ 949