1 /*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: head/sys/dev/siba/siba_core.c 257241 2013-10-28 07:29:16Z glebius $"); 32 33 /* 34 * the Sonics Silicon Backplane driver. 35 */ 36 37 #include "opt_siba.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/kernel.h> 44 #include <sys/endian.h> 45 #include <sys/errno.h> 46 #include <sys/bus.h> 47 #include <sys/bus_resource.h> 48 #include <sys/bus.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 52 #include <bus/pci/pcivar.h> 53 #include <bus/pci/pcireg.h> 54 55 #include "siba_ids.h" 56 #include "sibareg.h" 57 #include "sibavar.h" 58 59 #ifdef SIBA_DEBUG 60 enum { 61 SIBA_DEBUG_SCAN = 0x00000001, /* scan */ 62 SIBA_DEBUG_PMU = 0x00000002, /* PMU */ 63 SIBA_DEBUG_PLL = 0x00000004, /* PLL */ 64 SIBA_DEBUG_SWITCHCORE = 0x00000008, /* switching core */ 65 SIBA_DEBUG_SPROM = 0x00000010, /* SPROM */ 66 SIBA_DEBUG_CORE = 0x00000020, /* handling cores */ 67 SIBA_DEBUG_ANY = 0xffffffff 68 }; 69 #define DPRINTF(siba, m, fmt, ...) do { \ 70 if (m) \ 71 kprintf(fmt, __VA_ARGS__); \ 72 } while (0) 73 #else 74 #define DPRINTF(siba, m, fmt, ...) 75 #endif 76 #define N(a) (sizeof(a) / sizeof(a[0])) 77 78 static void siba_pci_gpio(struct siba_softc *, uint32_t, int); 79 static void siba_scan(struct siba_softc *); 80 static int siba_switchcore(struct siba_softc *, uint8_t); 81 static int siba_pci_switchcore_sub(struct siba_softc *, uint8_t); 82 static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t); 83 static uint16_t siba_dev2chipid(struct siba_softc *); 84 static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t); 85 static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t); 86 static void siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t); 87 static void siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t); 88 static void siba_cc_clock(struct siba_cc *, 89 enum siba_clock); 90 static void siba_cc_pmu_init(struct siba_cc *); 91 static void siba_cc_power_init(struct siba_cc *); 92 static void siba_cc_powerup_delay(struct siba_cc *); 93 static int siba_cc_clockfreq(struct siba_cc *, int); 94 static void siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t); 95 static void siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t); 96 static enum siba_clksrc siba_cc_clksrc(struct siba_cc *); 97 static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t); 98 static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t); 99 static void siba_cc_pll_write(struct siba_cc *, uint32_t, 100 uint32_t); 101 static const struct siba_cc_pmu0_plltab * 102 siba_cc_pmu0_plltab_findentry(uint32_t); 103 static int siba_pci_sprom(struct siba_softc *, struct siba_sprom *); 104 static int siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t); 105 static int sprom_check_crc(const uint16_t *, size_t); 106 static uint8_t siba_crc8(uint8_t, uint8_t); 107 static void siba_sprom_r123(struct siba_sprom *, const uint16_t *); 108 static void siba_sprom_r45(struct siba_sprom *, const uint16_t *); 109 static void siba_sprom_r8(struct siba_sprom *, const uint16_t *); 110 static int8_t siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t, 111 uint16_t); 112 static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *); 113 static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t); 114 static void siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t); 115 static uint32_t siba_pcie_read(struct siba_pci *, uint32_t); 116 static void siba_pcie_write(struct siba_pci *, uint32_t, uint32_t); 117 static void siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t, 118 uint16_t); 119 static void siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t, 120 uint16_t); 121 static void siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t, 122 uint16_t); 123 static void siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t, 124 uint16_t); 125 static void siba_pci_write_multi_1(struct siba_dev_softc *, const void *, 126 size_t, uint16_t); 127 static void siba_pci_write_multi_2(struct siba_dev_softc *, const void *, 128 size_t, uint16_t); 129 static void siba_pci_write_multi_4(struct siba_dev_softc *, const void *, 130 size_t, uint16_t); 131 static const char *siba_core_name(uint16_t); 132 static void siba_pcicore_init(struct siba_pci *); 133 static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t); 134 static void siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t); 135 static void siba_powerup_sub(struct siba_softc *, int); 136 static int siba_powerdown_sub(struct siba_softc *); 137 static int siba_dev_isup_sub(struct siba_dev_softc *); 138 static void siba_dev_up_sub(struct siba_dev_softc *, uint32_t); 139 static void siba_dev_down_sub(struct siba_dev_softc *, uint32_t); 140 int siba_core_attach(struct siba_softc *); 141 int siba_core_detach(struct siba_softc *); 142 int siba_core_suspend(struct siba_softc *); 143 int siba_core_resume(struct siba_softc *); 144 uint8_t siba_getncores(device_t, uint16_t); 145 146 static const struct siba_bus_ops siba_pci_ops = { 147 .read_2 = siba_pci_read_2, 148 .read_4 = siba_pci_read_4, 149 .write_2 = siba_pci_write_2, 150 .write_4 = siba_pci_write_4, 151 .read_multi_1 = siba_pci_read_multi_1, 152 .read_multi_2 = siba_pci_read_multi_2, 153 .read_multi_4 = siba_pci_read_multi_4, 154 .write_multi_1 = siba_pci_write_multi_1, 155 .write_multi_2 = siba_pci_write_multi_2, 156 .write_multi_4 = siba_pci_write_multi_4, 157 }; 158 159 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] = 160 SIBA_CC_PMU_4325_RES_UPDOWN; 161 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] = 162 SIBA_CC_PMU_4325_RES_DEPEND; 163 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] = 164 SIBA_CC_PMU_4328_RES_UPDOWN; 165 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] = 166 SIBA_CC_PMU_4328_RES_DEPEND; 167 static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] = 168 SIBA_CC_PMU0_PLLTAB_ENTRY; 169 static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] = 170 SIBA_CC_PMU1_PLLTAB_ENTRY; 171 172 int 173 siba_core_attach(struct siba_softc *siba) 174 { 175 struct siba_cc *scc; 176 int error; 177 178 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 179 ("unsupported BUS type (%#x)", siba->siba_type)); 180 181 siba->siba_ops = &siba_pci_ops; 182 183 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); 184 siba_scan(siba); 185 186 /* XXX init PCI or PCMCIA host devices */ 187 188 siba_powerup_sub(siba, 0); 189 190 /* init ChipCommon */ 191 scc = &siba->siba_cc; 192 if (scc->scc_dev != NULL) { 193 siba_cc_pmu_init(scc); 194 siba_cc_power_init(scc); 195 siba_cc_clock(scc, SIBA_CLOCK_FAST); 196 siba_cc_powerup_delay(scc); 197 } 198 199 error = siba_pci_sprom(siba, &siba->siba_sprom); 200 if (error) { 201 siba_powerdown_sub(siba); 202 return (error); 203 } 204 205 siba_pcicore_init(&siba->siba_pci); 206 siba_powerdown_sub(siba); 207 208 return (bus_generic_attach(siba->siba_dev)); 209 } 210 211 int 212 siba_core_detach(struct siba_softc *siba) 213 { 214 /* detach & delete all children */ 215 device_delete_children(siba->siba_dev); 216 return (0); 217 } 218 219 static void 220 siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on) 221 { 222 uint32_t in, out; 223 uint16_t status; 224 225 if (siba->siba_type != SIBA_TYPE_PCI) 226 return; 227 228 out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4); 229 if (on == 0) { 230 if (what & SIBA_GPIO_PLL) 231 out |= SIBA_GPIO_PLL; 232 if (what & SIBA_GPIO_CRYSTAL) 233 out &= ~SIBA_GPIO_CRYSTAL; 234 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 235 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN, 236 pci_read_config(siba->siba_dev, 237 SIBA_GPIO_OUT_EN, 4) | what, 4); 238 return; 239 } 240 241 in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4); 242 if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) { 243 if (what & SIBA_GPIO_CRYSTAL) { 244 out |= SIBA_GPIO_CRYSTAL; 245 if (what & SIBA_GPIO_PLL) 246 out |= SIBA_GPIO_PLL; 247 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 248 pci_write_config(siba->siba_dev, 249 SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev, 250 SIBA_GPIO_OUT_EN, 4) | what, 4); 251 DELAY(1000); 252 } 253 if (what & SIBA_GPIO_PLL) { 254 out &= ~SIBA_GPIO_PLL; 255 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 256 DELAY(5000); 257 } 258 } 259 260 status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2); 261 status &= ~PCIM_STATUS_STABORT; 262 pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2); 263 } 264 265 static void 266 siba_scan(struct siba_softc *siba) 267 { 268 struct siba_dev_softc *sd; 269 uint32_t idhi, tmp; 270 device_t child; 271 int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0, 272 n_pci = 0; 273 274 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 275 ("unsupported BUS type (%#x)", siba->siba_type)); 276 277 siba->siba_ndevs = 0; 278 error = siba_switchcore(siba, 0); /* need the first core */ 279 if (error) 280 return; 281 282 idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH); 283 if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) { 284 tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID); 285 siba->siba_chipid = SIBA_CC_ID(tmp); 286 siba->siba_chiprev = SIBA_CC_REV(tmp); 287 siba->siba_chippkg = SIBA_CC_PKG(tmp); 288 if (SIBA_IDHIGH_REV(idhi) >= 4) 289 siba->siba_ndevs = SIBA_CC_NCORES(tmp); 290 siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0, 291 SIBA_CC_CAPS); 292 } else { 293 if (siba->siba_type == SIBA_TYPE_PCI) { 294 siba->siba_chipid = siba_dev2chipid(siba); 295 siba->siba_chiprev = pci_read_config(siba->siba_dev, 296 PCIR_REVID, 2); 297 siba->siba_chippkg = 0; 298 } else { 299 siba->siba_chipid = 0x4710; 300 siba->siba_chiprev = 0; 301 siba->siba_chippkg = 0; 302 } 303 } 304 if (siba->siba_ndevs == 0) 305 siba->siba_ndevs = siba_getncores(siba->siba_dev, 306 siba->siba_chipid); 307 if (siba->siba_ndevs > SIBA_MAX_CORES) { 308 device_printf(siba->siba_dev, 309 "too many siba cores (max %d %d)\n", 310 SIBA_MAX_CORES, siba->siba_ndevs); 311 return; 312 } 313 314 /* looking basic information about each cores/devices */ 315 for (i = 0; i < siba->siba_ndevs; i++) { 316 error = siba_switchcore(siba, i); 317 if (error) 318 return; 319 sd = &(siba->siba_devs[dev_i]); 320 idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH); 321 sd->sd_bus = siba; 322 sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi); 323 sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi); 324 sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi); 325 sd->sd_ops = siba->siba_ops; 326 sd->sd_coreidx = i; 327 328 DPRINTF(siba, SIBA_DEBUG_SCAN, 329 "core %d (%s) found (cc %#xrev %#x vendor %#x)\n", 330 i, siba_core_name(sd->sd_id.sd_device), 331 sd->sd_id.sd_device, sd->sd_id.sd_rev, sd->sd_id.sd_vendor); 332 333 switch (sd->sd_id.sd_device) { 334 case SIBA_DEVID_CHIPCOMMON: 335 n_cc++; 336 if (n_cc > 1) { 337 device_printf(siba->siba_dev, 338 "warn: multiple ChipCommon\n"); 339 break; 340 } 341 siba->siba_cc.scc_dev = sd; 342 break; 343 case SIBA_DEVID_80211: 344 n_80211++; 345 if (n_80211 > 1) { 346 device_printf(siba->siba_dev, 347 "warn: multiple 802.11 core\n"); 348 continue; 349 } 350 break; 351 case SIBA_DEVID_PCI: 352 case SIBA_DEVID_PCIE: 353 n_pci++; 354 error = pci_find_extcap(siba->siba_dev, PCIY_EXPRESS, 355 &base); 356 is_pcie = (error == 0) ? 1 : 0; 357 358 if (n_pci > 1) { 359 device_printf(siba->siba_dev, 360 "warn: multiple PCI(E) cores\n"); 361 break; 362 } 363 if (sd->sd_id.sd_device == SIBA_DEVID_PCI && 364 is_pcie == 1) 365 continue; 366 if (sd->sd_id.sd_device == SIBA_DEVID_PCIE && 367 is_pcie == 0) 368 continue; 369 siba->siba_pci.spc_dev = sd; 370 break; 371 case SIBA_DEVID_MODEM: 372 case SIBA_DEVID_PCMCIA: 373 break; 374 default: 375 device_printf(siba->siba_dev, 376 "unsupported coreid (%s)\n", 377 siba_core_name(sd->sd_id.sd_device)); 378 break; 379 } 380 dev_i++; 381 382 child = device_add_child(siba->siba_dev, NULL, -1); 383 if (child == NULL) { 384 device_printf(siba->siba_dev, "child attach failed\n"); 385 continue; 386 } 387 388 device_set_ivars(child, sd); 389 } 390 siba->siba_ndevs = dev_i; 391 } 392 393 static int 394 siba_switchcore(struct siba_softc *siba, uint8_t idx) 395 { 396 397 switch (siba->siba_type) { 398 case SIBA_TYPE_PCI: 399 return (siba_pci_switchcore_sub(siba, idx)); 400 default: 401 KASSERT(0 == 1, 402 ("%s: unsupported bustype %#x", __func__, 403 siba->siba_type)); 404 } 405 return (0); 406 } 407 408 static int 409 siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx) 410 { 411 #define RETRY_MAX 50 412 int i; 413 uint32_t dir; 414 415 dir = SIBA_REGWIN(idx); 416 417 for (i = 0; i < RETRY_MAX; i++) { 418 pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4); 419 if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir) 420 return (0); 421 DELAY(10); 422 } 423 return (ENODEV); 424 #undef RETRY_MAX 425 } 426 427 static int 428 siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd) 429 { 430 int error; 431 432 DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n", 433 siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx); 434 435 error = siba_pci_switchcore_sub(siba, sd->sd_coreidx); 436 if (error == 0) 437 siba->siba_curdev = sd; 438 439 return (error); 440 } 441 442 static uint32_t 443 siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx, 444 uint16_t offset) 445 { 446 447 (void)coreidx; 448 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 449 ("unsupported BUS type (%#x)", siba->siba_type)); 450 451 return (SIBA_READ_4(siba, offset)); 452 } 453 454 static uint16_t 455 siba_dev2chipid(struct siba_softc *siba) 456 { 457 uint16_t chipid = 0; 458 459 switch (siba->siba_pci_did) { 460 case 0x4301: 461 chipid = 0x4301; 462 break; 463 case 0x4305: 464 case 0x4306: 465 case 0x4307: 466 chipid = 0x4307; 467 break; 468 case 0x4403: 469 chipid = 0x4402; 470 break; 471 case 0x4610: 472 case 0x4611: 473 case 0x4612: 474 case 0x4613: 475 case 0x4614: 476 case 0x4615: 477 chipid = 0x4610; 478 break; 479 case 0x4710: 480 case 0x4711: 481 case 0x4712: 482 case 0x4713: 483 case 0x4714: 484 case 0x4715: 485 chipid = 0x4710; 486 break; 487 case 0x4320: 488 case 0x4321: 489 case 0x4322: 490 case 0x4323: 491 case 0x4324: 492 case 0x4325: 493 chipid = 0x4309; 494 break; 495 case PCI_DEVICE_ID_BCM4401: 496 case PCI_DEVICE_ID_BCM4401B0: 497 case PCI_DEVICE_ID_BCM4401B1: 498 chipid = 0x4401; 499 break; 500 default: 501 device_printf(siba->siba_dev, "unknown PCI did (%d)\n", 502 siba->siba_pci_did); 503 } 504 505 return (chipid); 506 } 507 508 /* 509 * Earlier ChipCommon revisions have hardcoded number of cores 510 * present dependent on the ChipCommon ID. 511 */ 512 uint8_t 513 siba_getncores(device_t dev, uint16_t chipid) 514 { 515 switch (chipid) { 516 case 0x4401: 517 case 0x4402: 518 return (3); 519 case 0x4301: 520 case 0x4307: 521 return (5); 522 case 0x4306: 523 return (6); 524 case SIBA_CCID_SENTRY5: 525 return (7); 526 case 0x4310: 527 return (8); 528 case SIBA_CCID_BCM4710: 529 case 0x4610: 530 case SIBA_CCID_BCM4704: 531 return (9); 532 default: 533 device_printf(dev, "unknown the chipset ID %#x\n", chipid); 534 } 535 536 return (1); 537 } 538 539 static const char * 540 siba_core_name(uint16_t coreid) 541 { 542 543 switch (coreid) { 544 case SIBA_DEVID_CHIPCOMMON: 545 return ("ChipCommon"); 546 case SIBA_DEVID_ILINE20: 547 return ("ILine 20"); 548 case SIBA_DEVID_SDRAM: 549 return ("SDRAM"); 550 case SIBA_DEVID_PCI: 551 return ("PCI"); 552 case SIBA_DEVID_MIPS: 553 return ("MIPS"); 554 case SIBA_DEVID_ETHERNET: 555 return ("Fast Ethernet"); 556 case SIBA_DEVID_MODEM: 557 return ("Modem"); 558 case SIBA_DEVID_USB11_HOSTDEV: 559 return ("USB 1.1 Hostdev"); 560 case SIBA_DEVID_ADSL: 561 return ("ADSL"); 562 case SIBA_DEVID_ILINE100: 563 return ("ILine 100"); 564 case SIBA_DEVID_IPSEC: 565 return ("IPSEC"); 566 case SIBA_DEVID_PCMCIA: 567 return ("PCMCIA"); 568 case SIBA_DEVID_INTERNAL_MEM: 569 return ("Internal Memory"); 570 case SIBA_DEVID_SDRAMDDR: 571 return ("MEMC SDRAM"); 572 case SIBA_DEVID_EXTIF: 573 return ("EXTIF"); 574 case SIBA_DEVID_80211: 575 return ("IEEE 802.11"); 576 case SIBA_DEVID_MIPS_3302: 577 return ("MIPS 3302"); 578 case SIBA_DEVID_USB11_HOST: 579 return ("USB 1.1 Host"); 580 case SIBA_DEVID_USB11_DEV: 581 return ("USB 1.1 Device"); 582 case SIBA_DEVID_USB20_HOST: 583 return ("USB 2.0 Host"); 584 case SIBA_DEVID_USB20_DEV: 585 return ("USB 2.0 Device"); 586 case SIBA_DEVID_SDIO_HOST: 587 return ("SDIO Host"); 588 case SIBA_DEVID_ROBOSWITCH: 589 return ("Roboswitch"); 590 case SIBA_DEVID_PARA_ATA: 591 return ("PATA"); 592 case SIBA_DEVID_SATA_XORDMA: 593 return ("SATA XOR-DMA"); 594 case SIBA_DEVID_ETHERNET_GBIT: 595 return ("GBit Ethernet"); 596 case SIBA_DEVID_PCIE: 597 return ("PCI-Express"); 598 case SIBA_DEVID_MIMO_PHY: 599 return ("MIMO PHY"); 600 case SIBA_DEVID_SRAM_CTRLR: 601 return ("SRAM Controller"); 602 case SIBA_DEVID_MINI_MACPHY: 603 return ("Mini MACPHY"); 604 case SIBA_DEVID_ARM_1176: 605 return ("ARM 1176"); 606 case SIBA_DEVID_ARM_7TDMI: 607 return ("ARM 7TDMI"); 608 } 609 return ("unknown"); 610 } 611 612 static uint16_t 613 siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset) 614 { 615 struct siba_softc *siba = sd->sd_bus; 616 617 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 618 return (0xffff); 619 620 return (SIBA_READ_2(siba, offset)); 621 } 622 623 static uint32_t 624 siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset) 625 { 626 struct siba_softc *siba = sd->sd_bus; 627 628 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 629 return (0xffff); 630 631 return (SIBA_READ_4(siba, offset)); 632 } 633 634 static void 635 siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value) 636 { 637 struct siba_softc *siba = sd->sd_bus; 638 639 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 640 return; 641 642 SIBA_WRITE_2(siba, offset, value); 643 } 644 645 static void 646 siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) 647 { 648 struct siba_softc *siba = sd->sd_bus; 649 650 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 651 return; 652 653 SIBA_WRITE_4(siba, offset, value); 654 } 655 656 static void 657 siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count, 658 uint16_t offset) 659 { 660 struct siba_softc *siba = sd->sd_bus; 661 662 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 663 memset(buffer, 0xff, count); 664 return; 665 } 666 667 SIBA_READ_MULTI_1(siba, offset, buffer, count); 668 } 669 670 static void 671 siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count, 672 uint16_t offset) 673 { 674 struct siba_softc *siba = sd->sd_bus; 675 676 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 677 memset(buffer, 0xff, count); 678 return; 679 } 680 681 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); 682 SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1); 683 } 684 685 static void 686 siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count, 687 uint16_t offset) 688 { 689 struct siba_softc *siba = sd->sd_bus; 690 691 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 692 memset(buffer, 0xff, count); 693 return; 694 } 695 696 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); 697 SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2); 698 } 699 700 static void 701 siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer, 702 size_t count, uint16_t offset) 703 { 704 struct siba_softc *siba = sd->sd_bus; 705 706 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 707 return; 708 709 SIBA_WRITE_MULTI_1(siba, offset, buffer, count); 710 } 711 712 static void 713 siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer, 714 size_t count, uint16_t offset) 715 { 716 struct siba_softc *siba = sd->sd_bus; 717 718 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 719 return; 720 721 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); 722 SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1); 723 } 724 725 static void 726 siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer, 727 size_t count, uint16_t offset) 728 { 729 struct siba_softc *siba = sd->sd_bus; 730 731 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 732 return; 733 734 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); 735 SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2); 736 } 737 738 void 739 siba_powerup(device_t dev, int dynamic) 740 { 741 struct siba_dev_softc *sd = device_get_ivars(dev); 742 struct siba_softc *siba = sd->sd_bus; 743 744 siba_powerup_sub(siba, dynamic); 745 } 746 747 static void 748 siba_powerup_sub(struct siba_softc *siba, int dynamic) 749 { 750 751 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); 752 siba_cc_clock(&siba->siba_cc, 753 (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST); 754 } 755 756 static void 757 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock) 758 { 759 struct siba_dev_softc *sd = scc->scc_dev; 760 struct siba_softc *siba; 761 uint32_t tmp; 762 763 if (sd == NULL) 764 return; 765 siba = sd->sd_bus; 766 /* 767 * chipcommon < r6 (no dynamic clock control) 768 * chipcommon >= r10 (unknown) 769 */ 770 if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 || 771 (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) 772 return; 773 774 switch (clock) { 775 case SIBA_CLOCK_DYNAMIC: 776 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 777 ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW | 778 SIBA_CC_CLKSLOW_IPLL); 779 if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL) 780 tmp |= SIBA_CC_CLKSLOW_ENXTAL; 781 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp); 782 if (tmp & SIBA_CC_CLKSLOW_ENXTAL) 783 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0); 784 break; 785 case SIBA_CLOCK_SLOW: 786 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, 787 SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | 788 SIBA_CC_CLKSLOW_FSLOW); 789 break; 790 case SIBA_CLOCK_FAST: 791 /* crystal on */ 792 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1); 793 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, 794 (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | 795 SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW); 796 break; 797 default: 798 KASSERT(0 == 1, 799 ("%s: unsupported clock %#x", __func__, clock)); 800 } 801 } 802 803 uint16_t 804 siba_read_2(device_t dev, uint16_t offset) 805 { 806 struct siba_dev_softc *sd = device_get_ivars(dev); 807 808 return (sd->sd_ops->read_2(sd, offset)); 809 } 810 811 uint32_t 812 siba_read_4(device_t dev, uint16_t offset) 813 { 814 struct siba_dev_softc *sd = device_get_ivars(dev); 815 816 return (siba_read_4_sub(sd, offset)); 817 } 818 819 static uint32_t 820 siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset) 821 { 822 823 return (sd->sd_ops->read_4(sd, offset)); 824 } 825 826 void 827 siba_write_2(device_t dev, uint16_t offset, uint16_t value) 828 { 829 struct siba_dev_softc *sd = device_get_ivars(dev); 830 831 sd->sd_ops->write_2(sd, offset, value); 832 } 833 834 void 835 siba_write_4(device_t dev, uint16_t offset, uint32_t value) 836 { 837 struct siba_dev_softc *sd = device_get_ivars(dev); 838 839 return (siba_write_4_sub(sd, offset, value)); 840 } 841 842 static void 843 siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) 844 { 845 846 sd->sd_ops->write_4(sd, offset, value); 847 } 848 849 void 850 siba_read_multi_1(device_t dev, void *buffer, size_t count, 851 uint16_t offset) 852 { 853 struct siba_dev_softc *sd = device_get_ivars(dev); 854 855 sd->sd_ops->read_multi_1(sd, buffer, count, offset); 856 } 857 858 void 859 siba_read_multi_2(device_t dev, void *buffer, size_t count, 860 uint16_t offset) 861 { 862 struct siba_dev_softc *sd = device_get_ivars(dev); 863 864 sd->sd_ops->read_multi_2(sd, buffer, count, offset); 865 } 866 867 void 868 siba_read_multi_4(device_t dev, void *buffer, size_t count, 869 uint16_t offset) 870 { 871 struct siba_dev_softc *sd = device_get_ivars(dev); 872 873 sd->sd_ops->read_multi_4(sd, buffer, count, offset); 874 } 875 876 void 877 siba_write_multi_1(device_t dev, const void *buffer, size_t count, 878 uint16_t offset) 879 { 880 struct siba_dev_softc *sd = device_get_ivars(dev); 881 882 sd->sd_ops->write_multi_1(sd, buffer, count, offset); 883 } 884 885 void 886 siba_write_multi_2(device_t dev, const void *buffer, size_t count, 887 uint16_t offset) 888 { 889 struct siba_dev_softc *sd = device_get_ivars(dev); 890 891 sd->sd_ops->write_multi_2(sd, buffer, count, offset); 892 } 893 894 void 895 siba_write_multi_4(device_t dev, const void *buffer, size_t count, 896 uint16_t offset) 897 { 898 struct siba_dev_softc *sd = device_get_ivars(dev); 899 900 sd->sd_ops->write_multi_4(sd, buffer, count, offset); 901 } 902 903 static void 904 siba_cc_pmu_init(struct siba_cc *scc) 905 { 906 const struct siba_cc_pmu_res_updown *updown = NULL; 907 const struct siba_cc_pmu_res_depend *depend = NULL; 908 struct siba_dev_softc *sd = scc->scc_dev; 909 struct siba_softc *siba = sd->sd_bus; 910 uint32_t min = 0, max = 0, pmucap; 911 unsigned int i, updown_size, depend_size; 912 913 if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0) 914 return; 915 916 pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS); 917 scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV); 918 919 DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n", 920 scc->scc_pmu.rev, pmucap); 921 922 if (scc->scc_pmu.rev >= 1) { 923 if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325) 924 SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, 925 ~SIBA_CC_PMUCTL_NOILP); 926 else 927 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, 928 SIBA_CC_PMUCTL_NOILP); 929 } 930 931 /* initialize PLL & PMU resources */ 932 switch (siba->siba_chipid) { 933 case 0x4312: 934 siba_cc_pmu1_pll0_init(scc, 0 /* use default */); 935 /* use the default: min = 0xcbb max = 0x7ffff */ 936 break; 937 case 0x4325: 938 siba_cc_pmu1_pll0_init(scc, 0 /* use default */); 939 940 updown = siba_cc_pmu_4325_updown; 941 updown_size = N(siba_cc_pmu_4325_updown); 942 depend = siba_cc_pmu_4325_depend; 943 depend_size = N(siba_cc_pmu_4325_depend); 944 945 min = (1 << SIBA_CC_PMU_4325_BURST) | 946 (1 << SIBA_CC_PMU_4325_LN); 947 if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) & 948 SIBA_CC_CHST_4325_PMUTOP_2B) 949 min |= (1 << SIBA_CC_PMU_4325_CLBURST); 950 max = 0xfffff; 951 break; 952 case 0x4328: 953 siba_cc_pmu0_pll0_init(scc, 0 /* use default */); 954 955 updown = siba_cc_pmu_4328_updown; 956 updown_size = N(siba_cc_pmu_4328_updown); 957 depend = siba_cc_pmu_4328_depend; 958 depend_size = N(siba_cc_pmu_4328_depend); 959 960 min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | 961 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) | 962 (1 << SIBA_CC_PMU_4328_CRYSTAL_EN); 963 964 max = 0xfffff; 965 break; 966 case 0x5354: 967 siba_cc_pmu0_pll0_init(scc, 0 /* use default */); 968 969 max = 0xfffff; 970 break; 971 default: 972 device_printf(siba->siba_dev, 973 "unknown chipid %#x for PLL & PMU init\n", 974 siba->siba_chipid); 975 } 976 977 if (updown) { 978 for (i = 0; i < updown_size; i++) { 979 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, 980 updown[i].res); 981 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM, 982 updown[i].updown); 983 } 984 } 985 if (depend) { 986 for (i = 0; i < depend_size; i++) { 987 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, 988 depend[i].res); 989 switch (depend[i].task) { 990 case SIBA_CC_PMU_DEP_SET: 991 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK, 992 depend[i].depend); 993 break; 994 case SIBA_CC_PMU_DEP_ADD: 995 SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK, 996 depend[i].depend); 997 break; 998 case SIBA_CC_PMU_DEP_REMOVE: 999 SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK, 1000 ~(depend[i].depend)); 1001 break; 1002 default: 1003 KASSERT(0 == 1, 1004 ("%s:%d: assertion failed", 1005 __func__, __LINE__)); 1006 } 1007 } 1008 } 1009 1010 if (min) 1011 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min); 1012 if (max) 1013 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max); 1014 } 1015 1016 static void 1017 siba_cc_power_init(struct siba_cc *scc) 1018 { 1019 struct siba_softc *siba = scc->scc_dev->sd_bus; 1020 int maxfreq; 1021 1022 if (siba->siba_chipid == 0x4321) { 1023 if (siba->siba_chiprev == 0) 1024 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4); 1025 else if (siba->siba_chiprev == 1) 1026 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4); 1027 } 1028 1029 if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) 1030 return; 1031 1032 if (scc->scc_dev->sd_id.sd_rev >= 10) 1033 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL, 1034 (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) & 1035 0xffff) | 0x40000); 1036 else { 1037 maxfreq = siba_cc_clockfreq(scc, 1); 1038 SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY, 1039 (maxfreq * 150 + 999999) / 1000000); 1040 SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY, 1041 (maxfreq * 15 + 999999) / 1000000); 1042 } 1043 } 1044 1045 static void 1046 siba_cc_powerup_delay(struct siba_cc *scc) 1047 { 1048 struct siba_softc *siba = scc->scc_dev->sd_bus; 1049 int min; 1050 1051 if (siba->siba_type != SIBA_TYPE_PCI || 1052 !(scc->scc_caps & SIBA_CC_CAPS_PWCTL)) 1053 return; 1054 1055 min = siba_cc_clockfreq(scc, 0); 1056 scc->scc_powerup_delay = 1057 (((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000) + 1058 (min - 1)) / min; 1059 } 1060 1061 static int 1062 siba_cc_clockfreq(struct siba_cc *scc, int max) 1063 { 1064 enum siba_clksrc src; 1065 int div = 1, limit = 0; 1066 1067 src = siba_cc_clksrc(scc); 1068 if (scc->scc_dev->sd_id.sd_rev < 6) { 1069 div = (src == SIBA_CC_CLKSRC_PCI) ? 64 : 1070 (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1; 1071 KASSERT(div != 1, 1072 ("%s: unknown clock %d", __func__, src)); 1073 } else if (scc->scc_dev->sd_id.sd_rev < 10) { 1074 switch (src) { 1075 case SIBA_CC_CLKSRC_CRYSTAL: 1076 case SIBA_CC_CLKSRC_PCI: 1077 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) + 1078 1) * 4; 1079 break; 1080 case SIBA_CC_CLKSRC_LOWPW: 1081 break; 1082 } 1083 } else 1084 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4; 1085 1086 switch (src) { 1087 case SIBA_CC_CLKSRC_CRYSTAL: 1088 limit = (max) ? 20200000 : 19800000; 1089 break; 1090 case SIBA_CC_CLKSRC_LOWPW: 1091 limit = (max) ? 43000 : 25000; 1092 break; 1093 case SIBA_CC_CLKSRC_PCI: 1094 limit = (max) ? 34000000 : 25000000; 1095 break; 1096 } 1097 1098 return (limit / div); 1099 } 1100 1101 static void 1102 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq) 1103 { 1104 struct siba_dev_softc *sd = scc->scc_dev; 1105 struct siba_softc *siba = sd->sd_bus; 1106 const struct siba_cc_pmu1_plltab *e = NULL; 1107 uint32_t bufsth = 0, pll, pmu; 1108 unsigned int i; 1109 1110 KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__)); 1111 if (siba->siba_chipid == 0x4312) { 1112 scc->scc_pmu.freq = 20000; 1113 return; 1114 } 1115 1116 e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ); 1117 KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__)); 1118 scc->scc_pmu.freq = e->freq; 1119 1120 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1121 if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf) 1122 return; 1123 1124 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", 1125 (e->freq / 1000), (e->freq % 1000)); 1126 1127 /* turn PLL off */ 1128 switch (siba->siba_chipid) { 1129 case 0x4325: 1130 bufsth = 0x222222; 1131 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1132 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | 1133 (1 << SIBA_CC_PMU_4325_HT))); 1134 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1135 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | 1136 (1 << SIBA_CC_PMU_4325_HT))); 1137 break; 1138 default: 1139 KASSERT(0 == 1, 1140 ("%s:%d: assertion failed", __func__, __LINE__)); 1141 } 1142 for (i = 0; i < 1500; i++) { 1143 if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & 1144 SIBA_CC_CLKCTLSTATUS_HT)) 1145 break; 1146 DELAY(10); 1147 } 1148 if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT) 1149 device_printf(siba->siba_dev, "failed to turn PLL off!\n"); 1150 1151 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0); 1152 pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV); 1153 pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV; 1154 pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV; 1155 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll); 1156 1157 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2); 1158 pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE); 1159 pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT; 1160 pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE; 1161 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll); 1162 1163 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3); 1164 pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC; 1165 pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC; 1166 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll); 1167 1168 if (bufsth) { 1169 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5); 1170 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV; 1171 pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV; 1172 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll); 1173 } 1174 1175 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1176 pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF); 1177 pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) & 1178 SIBA_CC_PMUCTL_ILP; 1179 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; 1180 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); 1181 } 1182 1183 static void 1184 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq) 1185 { 1186 struct siba_dev_softc *sd = scc->scc_dev; 1187 struct siba_softc *siba = sd->sd_bus; 1188 const struct siba_cc_pmu0_plltab *e = NULL; 1189 uint32_t pmu, tmp, pll; 1190 unsigned int i; 1191 1192 if ((siba->siba_chipid == 0x5354) && !xtalfreq) 1193 xtalfreq = 25000; 1194 if (xtalfreq) 1195 e = siba_cc_pmu0_plltab_findentry(xtalfreq); 1196 if (e == NULL) 1197 e = siba_cc_pmu0_plltab_findentry( 1198 SIBA_CC_PMU0_DEFAULT_XTALFREQ); 1199 KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__)); 1200 xtalfreq = e->freq; 1201 scc->scc_pmu.freq = e->freq; 1202 1203 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1204 if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf) 1205 return; 1206 1207 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", 1208 (xtalfreq / 1000), (xtalfreq % 1000)); 1209 1210 KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354, 1211 ("%s:%d: fail", __func__, __LINE__)); 1212 1213 switch (siba->siba_chipid) { 1214 case 0x4328: 1215 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1216 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); 1217 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1218 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); 1219 break; 1220 case 0x5354: 1221 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1222 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); 1223 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1224 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); 1225 break; 1226 } 1227 for (i = 1500; i; i--) { 1228 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); 1229 if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT)) 1230 break; 1231 DELAY(10); 1232 } 1233 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); 1234 if (tmp & SIBA_CC_CLKCTLSTATUS_HT) 1235 device_printf(siba->siba_dev, "failed to turn PLL off!\n"); 1236 1237 /* set PDIV */ 1238 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0); 1239 if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ) 1240 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK; 1241 else 1242 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK; 1243 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll); 1244 1245 /* set WILD */ 1246 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1); 1247 pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK | 1248 SIBA_CC_PMU0_PLL1_FMSK); 1249 pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK; 1250 pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK; 1251 if (e->wb_frac == 0) 1252 pll |= SIBA_CC_PMU0_PLL1_STOPMOD; 1253 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll); 1254 1255 /* set WILD */ 1256 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2); 1257 pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI; 1258 pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI; 1259 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll); 1260 1261 /* set freq and divisor. */ 1262 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1263 pmu &= ~SIBA_CC_PMUCTL_ILP; 1264 pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP; 1265 pmu &= ~SIBA_CC_PMUCTL_XF; 1266 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; 1267 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); 1268 } 1269 1270 static enum siba_clksrc 1271 siba_cc_clksrc(struct siba_cc *scc) 1272 { 1273 struct siba_dev_softc *sd = scc->scc_dev; 1274 struct siba_softc *siba = sd->sd_bus; 1275 1276 if (sd->sd_id.sd_rev < 6) { 1277 if (siba->siba_type == SIBA_TYPE_PCI) { 1278 if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) & 1279 0x10) 1280 return (SIBA_CC_CLKSRC_PCI); 1281 return (SIBA_CC_CLKSRC_CRYSTAL); 1282 } 1283 if (siba->siba_type == SIBA_TYPE_SSB || 1284 siba->siba_type == SIBA_TYPE_PCMCIA) 1285 return (SIBA_CC_CLKSRC_CRYSTAL); 1286 } 1287 if (sd->sd_id.sd_rev < 10) { 1288 switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) { 1289 case 0: 1290 return (SIBA_CC_CLKSRC_LOWPW); 1291 case 1: 1292 return (SIBA_CC_CLKSRC_CRYSTAL); 1293 case 2: 1294 return (SIBA_CC_CLKSRC_PCI); 1295 default: 1296 break; 1297 } 1298 } 1299 1300 return (SIBA_CC_CLKSRC_CRYSTAL); 1301 } 1302 1303 static const struct siba_cc_pmu1_plltab * 1304 siba_cc_pmu1_plltab_find(uint32_t crystalfreq) 1305 { 1306 const struct siba_cc_pmu1_plltab *e; 1307 unsigned int i; 1308 1309 for (i = 0; i < N(siba_cc_pmu1_plltab); i++) { 1310 e = &siba_cc_pmu1_plltab[i]; 1311 if (crystalfreq == e->freq) 1312 return (e); 1313 } 1314 1315 return (NULL); 1316 } 1317 1318 static uint32_t 1319 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset) 1320 { 1321 1322 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); 1323 return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA)); 1324 } 1325 1326 static void 1327 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value) 1328 { 1329 1330 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); 1331 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value); 1332 } 1333 1334 static const struct siba_cc_pmu0_plltab * 1335 siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq) 1336 { 1337 const struct siba_cc_pmu0_plltab *e; 1338 unsigned int i; 1339 1340 for (i = 0; i < N(siba_cc_pmu0_plltab); i++) { 1341 e = &siba_cc_pmu0_plltab[i]; 1342 if (e->freq == crystalfreq) 1343 return (e); 1344 } 1345 1346 return (NULL); 1347 } 1348 1349 static int 1350 siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom) 1351 { 1352 int error = ENOMEM; 1353 uint16_t *buf; 1354 1355 buf = kmalloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t), 1356 M_DEVBUF, M_INTWAIT | M_ZERO); 1357 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123); 1358 error = sprom_check_crc(buf, siba->siba_spromsize); 1359 if (error) { 1360 kfree(buf, M_DEVBUF); 1361 buf = kmalloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t), 1362 M_DEVBUF, M_INTWAIT | M_ZERO); 1363 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4); 1364 error = sprom_check_crc(buf, siba->siba_spromsize); 1365 if (error) 1366 device_printf(siba->siba_dev, "warn: bad SPROM CRC\n"); 1367 } 1368 1369 bzero(sprom, sizeof(*sprom)); 1370 1371 sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF; 1372 DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n", 1373 sprom->rev); 1374 memset(sprom->mac_eth, 0xff, 6); 1375 memset(sprom->mac_80211a, 0xff, 6); 1376 if ((siba->siba_chipid & 0xff00) == 0x4400) { 1377 sprom->rev = 1; 1378 siba_sprom_r123(sprom, buf); 1379 } else if (siba->siba_chipid == 0x4321) { 1380 sprom->rev = 4; 1381 siba_sprom_r45(sprom, buf); 1382 } else { 1383 switch (sprom->rev) { 1384 case 1: 1385 case 2: 1386 case 3: 1387 siba_sprom_r123(sprom, buf); 1388 break; 1389 case 4: 1390 case 5: 1391 siba_sprom_r45(sprom, buf); 1392 break; 1393 case 8: 1394 siba_sprom_r8(sprom, buf); 1395 break; 1396 default: 1397 device_printf(siba->siba_dev, 1398 "unknown SPROM revision %d.\n", sprom->rev); 1399 siba_sprom_r123(sprom, buf); 1400 } 1401 } 1402 1403 if (sprom->bf_lo == 0xffff) 1404 sprom->bf_lo = 0; 1405 if (sprom->bf_hi == 0xffff) 1406 sprom->bf_hi = 0; 1407 1408 kfree(buf, M_DEVBUF); 1409 return (error); 1410 } 1411 1412 static int 1413 siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len) 1414 { 1415 int i; 1416 1417 for (i = 0; i < len; i++) 1418 sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2)); 1419 1420 siba->siba_spromsize = len; 1421 return (0); 1422 } 1423 1424 static int 1425 sprom_check_crc(const uint16_t *sprom, size_t size) 1426 { 1427 int word; 1428 uint8_t crc0, crc1 = 0xff; 1429 1430 crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8; 1431 for (word = 0; word < size - 1; word++) { 1432 crc1 = siba_crc8(crc1, sprom[word] & 0x00ff); 1433 crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8); 1434 } 1435 crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff); 1436 crc1 ^= 0xff; 1437 1438 return ((crc0 != crc1) ? EPROTO : 0); 1439 } 1440 1441 static uint8_t 1442 siba_crc8(uint8_t crc, uint8_t data) 1443 { 1444 static const uint8_t ct[] = { 1445 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b, 1446 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21, 1447 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff, 1448 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5, 1449 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14, 1450 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e, 1451 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80, 1452 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca, 1453 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95, 1454 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf, 1455 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01, 1456 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b, 1457 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea, 1458 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0, 1459 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e, 1460 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34, 1461 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0, 1462 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a, 1463 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54, 1464 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e, 1465 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf, 1466 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5, 1467 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b, 1468 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61, 1469 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e, 1470 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74, 1471 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa, 1472 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0, 1473 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41, 1474 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b, 1475 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5, 1476 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f, 1477 }; 1478 return (ct[crc ^ data]); 1479 } 1480 1481 #define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 1482 #define SIBA_OFFSET(offset) \ 1483 (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t)) 1484 #define SIBA_SHIFTOUT_SUB(__x, __mask) \ 1485 (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask)) 1486 #define SIBA_SHIFTOUT(_var, _offset, _mask) \ 1487 out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask)) 1488 #define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift) \ 1489 out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 | \ 1490 in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift)) 1491 1492 static void 1493 siba_sprom_r123(struct siba_sprom *out, const uint16_t *in) 1494 { 1495 int i; 1496 uint16_t v; 1497 int8_t gain; 1498 uint16_t loc[3]; 1499 1500 if (out->rev == 3) 1501 loc[0] = SIBA_SPROM3_MAC_80211BG; 1502 else { 1503 loc[0] = SIBA_SPROM1_MAC_80211BG; 1504 loc[1] = SIBA_SPROM1_MAC_ETH; 1505 loc[2] = SIBA_SPROM1_MAC_80211A; 1506 } 1507 for (i = 0; i < 3; i++) { 1508 v = in[SIBA_OFFSET(loc[0]) + i]; 1509 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1510 } 1511 if (out->rev < 3) { 1512 for (i = 0; i < 3; i++) { 1513 v = in[SIBA_OFFSET(loc[1]) + i]; 1514 *(((uint16_t *)out->mac_eth) + i) = htobe16(v); 1515 } 1516 for (i = 0; i < 3; i++) { 1517 v = in[SIBA_OFFSET(loc[2]) + i]; 1518 *(((uint16_t *)out->mac_80211a) + i) = htobe16(v); 1519 } 1520 } 1521 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY, 1522 SIBA_SPROM1_ETHPHY_MII_ETH0); 1523 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY, 1524 SIBA_SPROM1_ETHPHY_MII_ETH1); 1525 SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY, 1526 SIBA_SPROM1_ETHPHY_MDIO_ETH0); 1527 SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY, 1528 SIBA_SPROM1_ETHPHY_MDIO_ETH1); 1529 SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV); 1530 SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO, 1531 SIBA_SPROM1_BOARDINFO_CCODE); 1532 SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA); 1533 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO, 1534 SIBA_SPROM1_BOARDINFO_ANTBG); 1535 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff); 1536 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff); 1537 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff); 1538 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff); 1539 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff); 1540 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff); 1541 SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0); 1542 SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1); 1543 SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2); 1544 SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3); 1545 1546 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A); 1547 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG); 1548 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A); 1549 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG); 1550 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff); 1551 if (out->rev >= 2) 1552 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff); 1553 1554 /* antenna gain */ 1555 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0); 1556 out->again.ghz24.a0 = out->again.ghz24.a1 = gain; 1557 out->again.ghz24.a2 = out->again.ghz24.a3 = gain; 1558 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8); 1559 out->again.ghz5.a0 = out->again.ghz5.a1 = gain; 1560 out->again.ghz5.a2 = out->again.ghz5.a3 = gain; 1561 } 1562 1563 static void 1564 siba_sprom_r45(struct siba_sprom *out, const uint16_t *in) 1565 { 1566 int i; 1567 uint16_t v; 1568 uint16_t mac_80211bg_offset; 1569 1570 if (out->rev == 4) 1571 mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG; 1572 else 1573 mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG; 1574 for (i = 0; i < 3; i++) { 1575 v = in[SIBA_OFFSET(mac_80211bg_offset) + i]; 1576 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1577 } 1578 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A); 1579 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A); 1580 if (out->rev == 4) { 1581 SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff); 1582 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff); 1583 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff); 1584 } else { 1585 SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff); 1586 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff); 1587 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff); 1588 } 1589 SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A); 1590 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG); 1591 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK); 1592 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG); 1593 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK); 1594 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A); 1595 if (out->rev == 4) { 1596 SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0); 1597 SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1); 1598 SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2); 1599 SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3); 1600 } else { 1601 SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0); 1602 SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1); 1603 SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2); 1604 SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3); 1605 } 1606 1607 /* antenna gain */ 1608 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0); 1609 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1); 1610 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2); 1611 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3); 1612 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); 1613 } 1614 1615 static void 1616 siba_sprom_r8(struct siba_sprom *out, const uint16_t *in) 1617 { 1618 int i; 1619 uint16_t v; 1620 1621 for (i = 0; i < 3; i++) { 1622 v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i]; 1623 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1624 } 1625 SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff); 1626 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff); 1627 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff); 1628 SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff); 1629 SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff); 1630 SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A); 1631 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG); 1632 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK); 1633 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG); 1634 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK); 1635 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A); 1636 SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL, 1637 SIBA_SPROM8_MAXP_AH_MASK); 1638 SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL, 1639 SIBA_SPROM8_MAXP_AL_MASK); 1640 SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0); 1641 SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1); 1642 SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2); 1643 SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3); 1644 SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G); 1645 SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G); 1646 SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL); 1647 SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH); 1648 SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G); 1649 SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G); 1650 SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G); 1651 SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G); 1652 SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G); 1653 SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G); 1654 SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G); 1655 SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G); 1656 SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G); 1657 SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G); 1658 1659 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff); 1660 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff); 1661 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff); 1662 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff); 1663 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff); 1664 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff); 1665 SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff); 1666 SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff); 1667 SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff); 1668 SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff); 1669 SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff); 1670 SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff); 1671 SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff); 1672 1673 SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0); 1674 SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0); 1675 SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0); 1676 SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0); 1677 1678 /* antenna gain */ 1679 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0); 1680 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1); 1681 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2); 1682 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3); 1683 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); 1684 } 1685 1686 static int8_t 1687 siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in, 1688 uint16_t mask, uint16_t shift) 1689 { 1690 uint16_t v; 1691 uint8_t gain; 1692 1693 v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)]; 1694 gain = (v & mask) >> shift; 1695 gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 : 1696 ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2); 1697 1698 return ((int8_t)gain); 1699 } 1700 1701 #undef SIBA_LOWEST_SET_BIT 1702 #undef SIBA_OFFSET 1703 #undef SIBA_SHIFTOUT_SUB 1704 #undef SIBA_SHIFTOUT 1705 1706 int 1707 siba_powerdown(device_t dev) 1708 { 1709 struct siba_dev_softc *sd = device_get_ivars(dev); 1710 struct siba_softc *siba = sd->sd_bus; 1711 1712 return (siba_powerdown_sub(siba)); 1713 } 1714 1715 static int 1716 siba_powerdown_sub(struct siba_softc *siba) 1717 { 1718 struct siba_cc *scc; 1719 1720 if (siba->siba_type == SIBA_TYPE_SSB) 1721 return (0); 1722 1723 scc = &siba->siba_cc; 1724 if (scc->scc_dev == NULL || scc->scc_dev->sd_id.sd_rev < 5) 1725 return (0); 1726 siba_cc_clock(scc, SIBA_CLOCK_SLOW); 1727 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); 1728 return (0); 1729 } 1730 1731 static void 1732 siba_pcicore_init(struct siba_pci *spc) 1733 { 1734 struct siba_dev_softc *sd = spc->spc_dev; 1735 struct siba_softc *siba; 1736 1737 if (sd == NULL) 1738 return; 1739 1740 siba = sd->sd_bus; 1741 if (!siba_dev_isup_sub(sd)) 1742 siba_dev_up_sub(sd, 0); 1743 1744 KASSERT(spc->spc_hostmode == 0, 1745 ("%s:%d: hostmode", __func__, __LINE__)); 1746 /* disable PCI interrupt */ 1747 siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0); 1748 } 1749 1750 int 1751 siba_dev_isup(device_t dev) 1752 { 1753 struct siba_dev_softc *sd = device_get_ivars(dev); 1754 1755 return (siba_dev_isup_sub(sd)); 1756 } 1757 1758 static int 1759 siba_dev_isup_sub(struct siba_dev_softc *sd) 1760 { 1761 uint32_t reject, val; 1762 1763 reject = siba_tmslow_reject_bitmask(sd); 1764 val = siba_read_4_sub(sd, SIBA_TGSLOW); 1765 val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject; 1766 1767 return (val == SIBA_TGSLOW_CLOCK); 1768 } 1769 1770 void 1771 siba_dev_up(device_t dev, uint32_t flags) 1772 { 1773 struct siba_dev_softc *sd = device_get_ivars(dev); 1774 1775 siba_dev_up_sub(sd, flags); 1776 } 1777 1778 static void 1779 siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags) 1780 { 1781 uint32_t val; 1782 1783 siba_dev_down_sub(sd, flags); 1784 siba_write_4_sub(sd, SIBA_TGSLOW, 1785 SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); 1786 siba_read_4_sub(sd, SIBA_TGSLOW); 1787 DELAY(1); 1788 1789 if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR) 1790 siba_write_4_sub(sd, SIBA_TGSHIGH, 0); 1791 1792 val = siba_read_4_sub(sd, SIBA_IAS); 1793 if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) { 1794 val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT); 1795 siba_write_4_sub(sd, SIBA_IAS, val); 1796 } 1797 1798 siba_write_4_sub(sd, SIBA_TGSLOW, 1799 SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); 1800 siba_read_4_sub(sd, SIBA_TGSLOW); 1801 DELAY(1); 1802 1803 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags); 1804 siba_read_4_sub(sd, SIBA_TGSLOW); 1805 DELAY(1); 1806 } 1807 1808 static uint32_t 1809 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd) 1810 { 1811 uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV; 1812 1813 switch (rev) { 1814 case SIBA_IDLOW_SSBREV_22: 1815 return (SIBA_TGSLOW_REJECT_22); 1816 case SIBA_IDLOW_SSBREV_23: 1817 return (SIBA_TGSLOW_REJECT_23); 1818 case SIBA_IDLOW_SSBREV_24: 1819 case SIBA_IDLOW_SSBREV_25: 1820 case SIBA_IDLOW_SSBREV_26: 1821 case SIBA_IDLOW_SSBREV_27: 1822 return (SIBA_TGSLOW_REJECT_23); 1823 default: 1824 KASSERT(0 == 1, 1825 ("%s:%d: unknown backplane rev %#x\n", 1826 __func__, __LINE__, rev)); 1827 } 1828 return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23); 1829 } 1830 1831 void 1832 siba_dev_down(device_t dev, uint32_t flags) 1833 { 1834 struct siba_dev_softc *sd = device_get_ivars(dev); 1835 1836 siba_dev_down_sub(sd, flags); 1837 } 1838 1839 static void 1840 siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags) 1841 { 1842 struct siba_softc *siba = sd->sd_bus; 1843 uint32_t reject, val; 1844 int i; 1845 1846 if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET) 1847 return; 1848 1849 reject = siba_tmslow_reject_bitmask(sd); 1850 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK); 1851 1852 for (i = 0; i < 1000; i++) { 1853 val = siba_read_4_sub(sd, SIBA_TGSLOW); 1854 if (val & reject) 1855 break; 1856 DELAY(10); 1857 } 1858 if ((val & reject) == 0) { 1859 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", 1860 reject, SIBA_TGSLOW); 1861 } 1862 for (i = 0; i < 1000; i++) { 1863 val = siba_read_4_sub(sd, SIBA_TGSHIGH); 1864 if (!(val & SIBA_TGSHIGH_BUSY)) 1865 break; 1866 DELAY(10); 1867 } 1868 if ((val & SIBA_TGSHIGH_BUSY) != 0) { 1869 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", 1870 SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH); 1871 } 1872 1873 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK | 1874 reject | SIBA_TGSLOW_RESET | flags); 1875 siba_read_4_sub(sd, SIBA_TGSLOW); 1876 DELAY(1); 1877 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags); 1878 siba_read_4_sub(sd, SIBA_TGSLOW); 1879 DELAY(1); 1880 } 1881 1882 static void 1883 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd) 1884 { 1885 struct siba_dev_softc *psd = spc->spc_dev; 1886 struct siba_softc *siba = psd->sd_bus; 1887 uint32_t tmp; 1888 1889 if (psd->sd_id.sd_device == SIBA_DEVID_PCI) { 1890 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, 1891 siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) | 1892 SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST); 1893 1894 if (psd->sd_id.sd_rev < 5) { 1895 tmp = siba_read_4_sub(psd, SIBA_IMCFGLO); 1896 tmp &= ~SIBA_IMCFGLO_SERTO; 1897 tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO; 1898 tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */; 1899 siba_write_4_sub(psd, SIBA_IMCFGLO, tmp); 1900 1901 /* broadcast value */ 1902 sd = (siba->siba_cc.scc_dev != NULL) ? 1903 siba->siba_cc.scc_dev : siba->siba_pci.spc_dev; 1904 if (sd != NULL) { 1905 siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR, 1906 0xfd8); 1907 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR); 1908 siba_write_4_sub(sd, 1909 SIBA_PCICORE_BCAST_DATA, 0); 1910 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA); 1911 } 1912 } else if (psd->sd_id.sd_rev >= 11) { 1913 tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2); 1914 tmp |= SIBA_PCICORE_SBTOPCI_MRM; 1915 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp); 1916 } 1917 } else { 1918 KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE")); 1919 if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1)) 1920 siba_pcie_write(spc, 0x4, 1921 siba_pcie_read(spc, 0x4) | 0x8); 1922 if (psd->sd_id.sd_rev == 0) { 1923 siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */ 1924 siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */ 1925 siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */ 1926 } else if (psd->sd_id.sd_rev == 1) 1927 siba_pcie_write(spc, 0x100, 1928 siba_pcie_read(spc, 0x100) | 0x40); 1929 } 1930 spc->spc_inited = 1; 1931 } 1932 1933 void 1934 siba_pcicore_intr(device_t dev) 1935 { 1936 struct siba_dev_softc *sd = device_get_ivars(dev); 1937 struct siba_softc *siba = sd->sd_bus; 1938 struct siba_pci *spc = &siba->siba_pci; 1939 struct siba_dev_softc *psd = spc->spc_dev; 1940 uint32_t tmp; 1941 1942 if (siba->siba_type != SIBA_TYPE_PCI || !psd) 1943 return; 1944 1945 KASSERT(siba == psd->sd_bus, ("different pointers")); 1946 1947 /* enable interrupts */ 1948 if (siba->siba_dev != NULL && 1949 (psd->sd_id.sd_rev >= 6 || 1950 psd->sd_id.sd_device == SIBA_DEVID_PCIE)) { 1951 tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4); 1952 tmp |= (1 << sd->sd_coreidx) << 8; 1953 pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4); 1954 } else { 1955 tmp = siba_read_4_sub(sd, SIBA_TPS); 1956 tmp &= SIBA_TPS_BPFLAG; 1957 siba_write_4_sub(psd, SIBA_INTR_MASK, 1958 siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp)); 1959 } 1960 1961 /* setup PCIcore */ 1962 if (spc->spc_inited == 0) 1963 siba_pcicore_setup(spc, sd); 1964 } 1965 1966 static uint32_t 1967 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset) 1968 { 1969 1970 return (siba_read_4_sub(spc->spc_dev, offset)); 1971 } 1972 1973 static void 1974 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value) 1975 { 1976 1977 siba_write_4_sub(spc->spc_dev, offset, value); 1978 } 1979 1980 static uint32_t 1981 siba_pcie_read(struct siba_pci *spc, uint32_t address) 1982 { 1983 1984 siba_pcicore_write_4(spc, 0x130, address); 1985 return (siba_pcicore_read_4(spc, 0x134)); 1986 } 1987 1988 static void 1989 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data) 1990 { 1991 1992 siba_pcicore_write_4(spc, 0x130, address); 1993 siba_pcicore_write_4(spc, 0x134, data); 1994 } 1995 1996 static void 1997 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address, 1998 uint16_t data) 1999 { 2000 int i; 2001 2002 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2); 2003 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA, 2004 (1 << 30) | (1 << 28) | 2005 ((uint32_t)device << 22) | ((uint32_t)address << 18) | 2006 (1 << 17) | data); 2007 DELAY(10); 2008 for (i = 0; i < 10; i++) { 2009 if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100) 2010 break; 2011 DELAY(1000); 2012 } 2013 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0); 2014 } 2015 2016 uint32_t 2017 siba_dma_translation(device_t dev) 2018 { 2019 #ifdef INVARIANTS 2020 struct siba_dev_softc *sd = device_get_ivars(dev); 2021 struct siba_softc *siba = sd->sd_bus; 2022 2023 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 2024 ("unsupported bustype %d\n", siba->siba_type)); 2025 #endif 2026 return (SIBA_PCI_DMA); 2027 } 2028 2029 void 2030 siba_barrier(device_t dev, int flags) 2031 { 2032 struct siba_dev_softc *sd = device_get_ivars(dev); 2033 struct siba_softc *siba = sd->sd_bus; 2034 2035 SIBA_BARRIER(siba, flags); 2036 } 2037 2038 static void 2039 siba_cc_suspend(struct siba_cc *scc) 2040 { 2041 2042 siba_cc_clock(scc, SIBA_CLOCK_SLOW); 2043 } 2044 2045 static void 2046 siba_cc_resume(struct siba_cc *scc) 2047 { 2048 2049 siba_cc_power_init(scc); 2050 siba_cc_clock(scc, SIBA_CLOCK_FAST); 2051 } 2052 2053 int 2054 siba_core_suspend(struct siba_softc *siba) 2055 { 2056 2057 siba_cc_suspend(&siba->siba_cc); 2058 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); 2059 return (0); 2060 } 2061 2062 int 2063 siba_core_resume(struct siba_softc *siba) 2064 { 2065 2066 siba->siba_pci.spc_inited = 0; 2067 siba->siba_curdev = NULL; 2068 2069 siba_powerup_sub(siba, 0); 2070 /* XXX setup H/W for PCMCIA??? */ 2071 siba_cc_resume(&siba->siba_cc); 2072 siba_powerdown_sub(siba); 2073 2074 return (0); 2075 } 2076 2077 static void 2078 siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask, 2079 uint32_t set) 2080 { 2081 2082 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); 2083 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset); 2084 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); 2085 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA, 2086 (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set); 2087 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA); 2088 } 2089 2090 void 2091 siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt) 2092 { 2093 struct siba_dev_softc *sd = device_get_ivars(dev); 2094 struct siba_softc *siba = sd->sd_bus; 2095 struct siba_cc *scc = &siba->siba_cc; 2096 uint32_t *p = NULL, info[5][3] = { 2097 { 2, 25, 0xf }, 2098 { 3, 1, 0xf }, 2099 { 3, 9, 0xf }, 2100 { 3, 17, 0x3f }, 2101 { 0, 21, 0x3f } 2102 }; 2103 2104 if (siba->siba_chipid == 0x4312) { 2105 if (id != SIBA_LDO_PAREF) 2106 return; 2107 p = info[4]; 2108 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), 2109 (volt & p[2]) << p[1]); 2110 return; 2111 } 2112 if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) { 2113 switch (id) { 2114 case SIBA_LDO_PAREF: 2115 p = info[3]; 2116 break; 2117 case SIBA_LDO_VOLT1: 2118 p = info[0]; 2119 break; 2120 case SIBA_LDO_VOLT2: 2121 p = info[1]; 2122 break; 2123 case SIBA_LDO_VOLT3: 2124 p = info[2]; 2125 break; 2126 default: 2127 KASSERT(0 == 1, 2128 ("%s: unsupported voltage ID %#x", __func__, id)); 2129 return; 2130 } 2131 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), 2132 (volt & p[2]) << p[1]); 2133 } 2134 } 2135 2136 void 2137 siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on) 2138 { 2139 struct siba_dev_softc *sd = device_get_ivars(dev); 2140 struct siba_softc *siba = sd->sd_bus; 2141 struct siba_cc *scc = &siba->siba_cc; 2142 int ldo; 2143 2144 ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF : 2145 ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF : 2146 ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1))); 2147 if (ldo == -1) 2148 return; 2149 2150 if (on) 2151 SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo); 2152 else 2153 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo)); 2154 SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES); 2155 } 2156 2157 int 2158 siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result) 2159 { 2160 struct siba_dev_softc *sd = device_get_ivars(child); 2161 struct siba_softc *siba = sd->sd_bus; 2162 2163 switch (which) { 2164 case SIBA_SPROMVAR_REV: 2165 *result = siba->siba_sprom.rev; 2166 break; 2167 case SIBA_SPROMVAR_MAC_80211BG: 2168 *((uint8_t **) result) = siba->siba_sprom.mac_80211bg; 2169 break; 2170 case SIBA_SPROMVAR_MAC_ETH: 2171 *((uint8_t **) result) = siba->siba_sprom.mac_eth; 2172 break; 2173 case SIBA_SPROMVAR_MAC_80211A: 2174 *((uint8_t **) result) = siba->siba_sprom.mac_80211a; 2175 break; 2176 case SIBA_SPROMVAR_MII_ETH0: 2177 *result = siba->siba_sprom.mii_eth0; 2178 break; 2179 case SIBA_SPROMVAR_MII_ETH1: 2180 *result = siba->siba_sprom.mii_eth1; 2181 break; 2182 case SIBA_SPROMVAR_MDIO_ETH0: 2183 *result = siba->siba_sprom.mdio_eth0; 2184 break; 2185 case SIBA_SPROMVAR_MDIO_ETH1: 2186 *result = siba->siba_sprom.mdio_eth1; 2187 break; 2188 case SIBA_SPROMVAR_BREV: 2189 *result = siba->siba_sprom.brev; 2190 break; 2191 case SIBA_SPROMVAR_CCODE: 2192 *result = siba->siba_sprom.ccode; 2193 break; 2194 case SIBA_SPROMVAR_ANT_A: 2195 *result = siba->siba_sprom.ant_a; 2196 break; 2197 case SIBA_SPROMVAR_ANT_BG: 2198 *result = siba->siba_sprom.ant_bg; 2199 break; 2200 case SIBA_SPROMVAR_PA0B0: 2201 *result = siba->siba_sprom.pa0b0; 2202 break; 2203 case SIBA_SPROMVAR_PA0B1: 2204 *result = siba->siba_sprom.pa0b1; 2205 break; 2206 case SIBA_SPROMVAR_PA0B2: 2207 *result = siba->siba_sprom.pa0b2; 2208 break; 2209 case SIBA_SPROMVAR_PA1B0: 2210 *result = siba->siba_sprom.pa1b0; 2211 break; 2212 case SIBA_SPROMVAR_PA1B1: 2213 *result = siba->siba_sprom.pa1b1; 2214 break; 2215 case SIBA_SPROMVAR_PA1B2: 2216 *result = siba->siba_sprom.pa1b2; 2217 break; 2218 case SIBA_SPROMVAR_PA1LOB0: 2219 *result = siba->siba_sprom.pa1lob0; 2220 break; 2221 case SIBA_SPROMVAR_PA1LOB1: 2222 *result = siba->siba_sprom.pa1lob1; 2223 break; 2224 case SIBA_SPROMVAR_PA1LOB2: 2225 *result = siba->siba_sprom.pa1lob2; 2226 break; 2227 case SIBA_SPROMVAR_PA1HIB0: 2228 *result = siba->siba_sprom.pa1hib0; 2229 break; 2230 case SIBA_SPROMVAR_PA1HIB1: 2231 *result = siba->siba_sprom.pa1hib1; 2232 break; 2233 case SIBA_SPROMVAR_PA1HIB2: 2234 *result = siba->siba_sprom.pa1hib2; 2235 break; 2236 case SIBA_SPROMVAR_GPIO0: 2237 *result = siba->siba_sprom.gpio0; 2238 break; 2239 case SIBA_SPROMVAR_GPIO1: 2240 *result = siba->siba_sprom.gpio1; 2241 break; 2242 case SIBA_SPROMVAR_GPIO2: 2243 *result = siba->siba_sprom.gpio2; 2244 break; 2245 case SIBA_SPROMVAR_GPIO3: 2246 *result = siba->siba_sprom.gpio3; 2247 break; 2248 case SIBA_SPROMVAR_MAXPWR_AL: 2249 *result = siba->siba_sprom.maxpwr_al; 2250 break; 2251 case SIBA_SPROMVAR_MAXPWR_A: 2252 *result = siba->siba_sprom.maxpwr_a; 2253 break; 2254 case SIBA_SPROMVAR_MAXPWR_AH: 2255 *result = siba->siba_sprom.maxpwr_ah; 2256 break; 2257 case SIBA_SPROMVAR_MAXPWR_BG: 2258 *result = siba->siba_sprom.maxpwr_bg; 2259 break; 2260 case SIBA_SPROMVAR_RXPO2G: 2261 *result = siba->siba_sprom.rxpo2g; 2262 break; 2263 case SIBA_SPROMVAR_RXPO5G: 2264 *result = siba->siba_sprom.rxpo5g; 2265 break; 2266 case SIBA_SPROMVAR_TSSI_A: 2267 *result = siba->siba_sprom.tssi_a; 2268 break; 2269 case SIBA_SPROMVAR_TSSI_BG: 2270 *result = siba->siba_sprom.tssi_bg; 2271 break; 2272 case SIBA_SPROMVAR_TRI2G: 2273 *result = siba->siba_sprom.tri2g; 2274 break; 2275 case SIBA_SPROMVAR_TRI5GL: 2276 *result = siba->siba_sprom.tri5gl; 2277 break; 2278 case SIBA_SPROMVAR_TRI5G: 2279 *result = siba->siba_sprom.tri5g; 2280 break; 2281 case SIBA_SPROMVAR_TRI5GH: 2282 *result = siba->siba_sprom.tri5gh; 2283 break; 2284 case SIBA_SPROMVAR_RSSISAV2G: 2285 *result = siba->siba_sprom.rssisav2g; 2286 break; 2287 case SIBA_SPROMVAR_RSSISMC2G: 2288 *result = siba->siba_sprom.rssismc2g; 2289 break; 2290 case SIBA_SPROMVAR_RSSISMF2G: 2291 *result = siba->siba_sprom.rssismf2g; 2292 break; 2293 case SIBA_SPROMVAR_BXA2G: 2294 *result = siba->siba_sprom.bxa2g; 2295 break; 2296 case SIBA_SPROMVAR_RSSISAV5G: 2297 *result = siba->siba_sprom.rssisav5g; 2298 break; 2299 case SIBA_SPROMVAR_RSSISMC5G: 2300 *result = siba->siba_sprom.rssismc5g; 2301 break; 2302 case SIBA_SPROMVAR_RSSISMF5G: 2303 *result = siba->siba_sprom.rssismf5g; 2304 break; 2305 case SIBA_SPROMVAR_BXA5G: 2306 *result = siba->siba_sprom.bxa5g; 2307 break; 2308 case SIBA_SPROMVAR_CCK2GPO: 2309 *result = siba->siba_sprom.cck2gpo; 2310 break; 2311 case SIBA_SPROMVAR_OFDM2GPO: 2312 *result = siba->siba_sprom.ofdm2gpo; 2313 break; 2314 case SIBA_SPROMVAR_OFDM5GLPO: 2315 *result = siba->siba_sprom.ofdm5glpo; 2316 break; 2317 case SIBA_SPROMVAR_OFDM5GPO: 2318 *result = siba->siba_sprom.ofdm5gpo; 2319 break; 2320 case SIBA_SPROMVAR_OFDM5GHPO: 2321 *result = siba->siba_sprom.ofdm5ghpo; 2322 break; 2323 case SIBA_SPROMVAR_BF_LO: 2324 *result = siba->siba_sprom.bf_lo; 2325 break; 2326 case SIBA_SPROMVAR_BF_HI: 2327 *result = siba->siba_sprom.bf_hi; 2328 break; 2329 case SIBA_SPROMVAR_BF2_LO: 2330 *result = siba->siba_sprom.bf2_lo; 2331 break; 2332 case SIBA_SPROMVAR_BF2_HI: 2333 *result = siba->siba_sprom.bf2_hi; 2334 break; 2335 default: 2336 return (ENOENT); 2337 } 2338 return (0); 2339 } 2340 2341 int 2342 siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value) 2343 { 2344 struct siba_dev_softc *sd = device_get_ivars(child); 2345 struct siba_softc *siba = sd->sd_bus; 2346 2347 switch (which) { 2348 case SIBA_SPROMVAR_REV: 2349 siba->siba_sprom.rev = value; 2350 break; 2351 case SIBA_SPROMVAR_MII_ETH0: 2352 siba->siba_sprom.mii_eth0 = value; 2353 break; 2354 case SIBA_SPROMVAR_MII_ETH1: 2355 siba->siba_sprom.mii_eth1 = value; 2356 break; 2357 case SIBA_SPROMVAR_MDIO_ETH0: 2358 siba->siba_sprom.mdio_eth0 = value; 2359 break; 2360 case SIBA_SPROMVAR_MDIO_ETH1: 2361 siba->siba_sprom.mdio_eth1 = value; 2362 break; 2363 case SIBA_SPROMVAR_BREV: 2364 siba->siba_sprom.brev = value; 2365 break; 2366 case SIBA_SPROMVAR_CCODE: 2367 siba->siba_sprom.ccode = value; 2368 break; 2369 case SIBA_SPROMVAR_ANT_A: 2370 siba->siba_sprom.ant_a = value; 2371 break; 2372 case SIBA_SPROMVAR_ANT_BG: 2373 siba->siba_sprom.ant_bg = value; 2374 break; 2375 case SIBA_SPROMVAR_PA0B0: 2376 siba->siba_sprom.pa0b0 = value; 2377 break; 2378 case SIBA_SPROMVAR_PA0B1: 2379 siba->siba_sprom.pa0b1 = value; 2380 break; 2381 case SIBA_SPROMVAR_PA0B2: 2382 siba->siba_sprom.pa0b2 = value; 2383 break; 2384 case SIBA_SPROMVAR_PA1B0: 2385 siba->siba_sprom.pa1b0 = value; 2386 break; 2387 case SIBA_SPROMVAR_PA1B1: 2388 siba->siba_sprom.pa1b1 = value; 2389 break; 2390 case SIBA_SPROMVAR_PA1B2: 2391 siba->siba_sprom.pa1b2 = value; 2392 break; 2393 case SIBA_SPROMVAR_PA1LOB0: 2394 siba->siba_sprom.pa1lob0 = value; 2395 break; 2396 case SIBA_SPROMVAR_PA1LOB1: 2397 siba->siba_sprom.pa1lob1 = value; 2398 break; 2399 case SIBA_SPROMVAR_PA1LOB2: 2400 siba->siba_sprom.pa1lob2 = value; 2401 break; 2402 case SIBA_SPROMVAR_PA1HIB0: 2403 siba->siba_sprom.pa1hib0 = value; 2404 break; 2405 case SIBA_SPROMVAR_PA1HIB1: 2406 siba->siba_sprom.pa1hib1 = value; 2407 break; 2408 case SIBA_SPROMVAR_PA1HIB2: 2409 siba->siba_sprom.pa1hib2 = value; 2410 break; 2411 case SIBA_SPROMVAR_GPIO0: 2412 siba->siba_sprom.gpio0 = value; 2413 break; 2414 case SIBA_SPROMVAR_GPIO1: 2415 siba->siba_sprom.gpio1 = value; 2416 break; 2417 case SIBA_SPROMVAR_GPIO2: 2418 siba->siba_sprom.gpio2 = value; 2419 break; 2420 case SIBA_SPROMVAR_GPIO3: 2421 siba->siba_sprom.gpio3 = value; 2422 break; 2423 case SIBA_SPROMVAR_MAXPWR_AL: 2424 siba->siba_sprom.maxpwr_al = value; 2425 break; 2426 case SIBA_SPROMVAR_MAXPWR_A: 2427 siba->siba_sprom.maxpwr_a = value; 2428 break; 2429 case SIBA_SPROMVAR_MAXPWR_AH: 2430 siba->siba_sprom.maxpwr_ah = value; 2431 break; 2432 case SIBA_SPROMVAR_MAXPWR_BG: 2433 siba->siba_sprom.maxpwr_bg = value; 2434 break; 2435 case SIBA_SPROMVAR_RXPO2G: 2436 siba->siba_sprom.rxpo2g = value; 2437 break; 2438 case SIBA_SPROMVAR_RXPO5G: 2439 siba->siba_sprom.rxpo5g = value; 2440 break; 2441 case SIBA_SPROMVAR_TSSI_A: 2442 siba->siba_sprom.tssi_a = value; 2443 break; 2444 case SIBA_SPROMVAR_TSSI_BG: 2445 siba->siba_sprom.tssi_bg = value; 2446 break; 2447 case SIBA_SPROMVAR_TRI2G: 2448 siba->siba_sprom.tri2g = value; 2449 break; 2450 case SIBA_SPROMVAR_TRI5GL: 2451 siba->siba_sprom.tri5gl = value; 2452 break; 2453 case SIBA_SPROMVAR_TRI5G: 2454 siba->siba_sprom.tri5g = value; 2455 break; 2456 case SIBA_SPROMVAR_TRI5GH: 2457 siba->siba_sprom.tri5gh = value; 2458 break; 2459 case SIBA_SPROMVAR_RSSISAV2G: 2460 siba->siba_sprom.rssisav2g = value; 2461 break; 2462 case SIBA_SPROMVAR_RSSISMC2G: 2463 siba->siba_sprom.rssismc2g = value; 2464 break; 2465 case SIBA_SPROMVAR_RSSISMF2G: 2466 siba->siba_sprom.rssismf2g = value; 2467 break; 2468 case SIBA_SPROMVAR_BXA2G: 2469 siba->siba_sprom.bxa2g = value; 2470 break; 2471 case SIBA_SPROMVAR_RSSISAV5G: 2472 siba->siba_sprom.rssisav5g = value; 2473 break; 2474 case SIBA_SPROMVAR_RSSISMC5G: 2475 siba->siba_sprom.rssismc5g = value; 2476 break; 2477 case SIBA_SPROMVAR_RSSISMF5G: 2478 siba->siba_sprom.rssismf5g = value; 2479 break; 2480 case SIBA_SPROMVAR_BXA5G: 2481 siba->siba_sprom.bxa5g = value; 2482 break; 2483 case SIBA_SPROMVAR_CCK2GPO: 2484 siba->siba_sprom.cck2gpo = value; 2485 break; 2486 case SIBA_SPROMVAR_OFDM2GPO: 2487 siba->siba_sprom.ofdm2gpo = value; 2488 break; 2489 case SIBA_SPROMVAR_OFDM5GLPO: 2490 siba->siba_sprom.ofdm5glpo = value; 2491 break; 2492 case SIBA_SPROMVAR_OFDM5GPO: 2493 siba->siba_sprom.ofdm5gpo = value; 2494 break; 2495 case SIBA_SPROMVAR_OFDM5GHPO: 2496 siba->siba_sprom.ofdm5ghpo = value; 2497 break; 2498 case SIBA_SPROMVAR_BF_LO: 2499 siba->siba_sprom.bf_lo = value; 2500 break; 2501 case SIBA_SPROMVAR_BF_HI: 2502 siba->siba_sprom.bf_hi = value; 2503 break; 2504 case SIBA_SPROMVAR_BF2_LO: 2505 siba->siba_sprom.bf2_lo = value; 2506 break; 2507 case SIBA_SPROMVAR_BF2_HI: 2508 siba->siba_sprom.bf2_hi = value; 2509 break; 2510 default: 2511 return (ENOENT); 2512 } 2513 return (0); 2514 } 2515 2516 #define SIBA_GPIOCTL 0x06c 2517 2518 uint32_t 2519 siba_gpio_get(device_t dev) 2520 { 2521 struct siba_dev_softc *sd = device_get_ivars(dev); 2522 struct siba_softc *siba = sd->sd_bus; 2523 struct siba_dev_softc *gpiodev, *pcidev = NULL; 2524 2525 pcidev = siba->siba_pci.spc_dev; 2526 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; 2527 if (gpiodev == NULL) 2528 return (-1); 2529 return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL)); 2530 } 2531 2532 void 2533 siba_gpio_set(device_t dev, uint32_t value) 2534 { 2535 struct siba_dev_softc *sd = device_get_ivars(dev); 2536 struct siba_softc *siba = sd->sd_bus; 2537 struct siba_dev_softc *gpiodev, *pcidev = NULL; 2538 2539 pcidev = siba->siba_pci.spc_dev; 2540 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; 2541 if (gpiodev == NULL) 2542 return; 2543 siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value); 2544 } 2545 2546 void 2547 siba_fix_imcfglobug(device_t dev) 2548 { 2549 struct siba_dev_softc *sd = device_get_ivars(dev); 2550 struct siba_softc *siba = sd->sd_bus; 2551 uint32_t tmp; 2552 2553 if (siba->siba_pci.spc_dev == NULL) 2554 return; 2555 if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI || 2556 siba->siba_pci.spc_dev->sd_id.sd_rev > 5) 2557 return; 2558 2559 tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) & 2560 ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO); 2561 switch (siba->siba_type) { 2562 case SIBA_TYPE_PCI: 2563 case SIBA_TYPE_PCMCIA: 2564 tmp |= 0x32; 2565 break; 2566 case SIBA_TYPE_SSB: 2567 tmp |= 0x53; 2568 break; 2569 } 2570 siba_write_4_sub(sd, SIBA_IMCFGLO, tmp); 2571 } 2572