1 /*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: head/sys/dev/siba/siba_core.c 299541 2016-05-12 16:14:16Z adrian $"); 32 33 /* 34 * the Sonics Silicon Backplane driver. 35 */ 36 37 #include "opt_siba.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/kernel.h> 44 #include <sys/endian.h> 45 #include <sys/errno.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #if !defined(__DragonFly__) 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #endif 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <sys/socket.h> 55 56 #include <net/if.h> 57 #include <net/if_media.h> 58 #include <net/if_arp.h> 59 60 #if defined(__DragonFly__) 61 #include <bus/pci/pcivar.h> 62 #include <bus/pci/pcireg.h> 63 #else 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 #endif 67 68 #if defined(__DragonFly__) 69 #include "siba_ids.h" 70 #include "sibareg.h" 71 #include "sibavar.h" 72 #else 73 #include <dev/siba/siba_ids.h> 74 #include <dev/siba/sibareg.h> 75 #include <dev/siba/sibavar.h> 76 #endif 77 78 enum { 79 SIBA_DEBUG_SCAN = 0x00000001, /* scan */ 80 SIBA_DEBUG_PMU = 0x00000002, /* PMU */ 81 SIBA_DEBUG_PLL = 0x00000004, /* PLL */ 82 SIBA_DEBUG_SWITCHCORE = 0x00000008, /* switching core */ 83 SIBA_DEBUG_SPROM = 0x00000010, /* SPROM */ 84 SIBA_DEBUG_CORE = 0x00000020, /* handling cores */ 85 SIBA_DEBUG_ANY = 0xffffffff 86 }; 87 88 #ifdef SIBA_DEBUG 89 #define DPRINTF(siba, m, ...) do { \ 90 if (siba->siba_debug & (m)) \ 91 device_printf(siba->siba_dev, __VA_ARGS__); \ 92 } while (0) 93 #else 94 #define DPRINTF(siba, m, ...) do { (void) siba; } while (0) 95 #endif 96 #define N(a) (sizeof(a) / sizeof(a[0])) 97 98 static void siba_pci_gpio(struct siba_softc *, uint32_t, int); 99 static void siba_scan(struct siba_softc *); 100 static int siba_switchcore(struct siba_softc *, uint8_t); 101 static int siba_pci_switchcore_sub(struct siba_softc *, uint8_t); 102 static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t); 103 static uint16_t siba_dev2chipid(struct siba_softc *); 104 static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t); 105 static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t); 106 static void siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t); 107 static void siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t); 108 static void siba_cc_clock(struct siba_cc *, 109 enum siba_clock); 110 static void siba_cc_pmu_init(struct siba_cc *); 111 static void siba_cc_power_init(struct siba_cc *); 112 static void siba_cc_powerup_delay(struct siba_cc *); 113 static int siba_cc_clockfreq(struct siba_cc *, int); 114 static void siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t); 115 static void siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t); 116 static enum siba_clksrc siba_cc_clksrc(struct siba_cc *); 117 static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t); 118 static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t); 119 static void siba_cc_pll_write(struct siba_cc *, uint32_t, 120 uint32_t); 121 static const struct siba_cc_pmu0_plltab * 122 siba_cc_pmu0_plltab_findentry(uint32_t); 123 static int siba_pci_sprom(struct siba_softc *, struct siba_sprom *); 124 static int siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t); 125 static int sprom_check_crc(const uint16_t *, size_t); 126 static uint8_t siba_crc8(uint8_t, uint8_t); 127 static void siba_sprom_r123(struct siba_sprom *, const uint16_t *); 128 static void siba_sprom_r45(struct siba_sprom *, const uint16_t *); 129 static void siba_sprom_r8(struct siba_sprom *, const uint16_t *); 130 static int8_t siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t, 131 uint16_t); 132 static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *); 133 static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t); 134 static void siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t); 135 static uint32_t siba_pcie_read(struct siba_pci *, uint32_t); 136 static void siba_pcie_write(struct siba_pci *, uint32_t, uint32_t); 137 static void siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t, 138 uint16_t); 139 static void siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t, 140 uint16_t); 141 static void siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t, 142 uint16_t); 143 static void siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t, 144 uint16_t); 145 static void siba_pci_write_multi_1(struct siba_dev_softc *, const void *, 146 size_t, uint16_t); 147 static void siba_pci_write_multi_2(struct siba_dev_softc *, const void *, 148 size_t, uint16_t); 149 static void siba_pci_write_multi_4(struct siba_dev_softc *, const void *, 150 size_t, uint16_t); 151 static const char *siba_core_name(uint16_t); 152 static void siba_pcicore_init(struct siba_pci *); 153 static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t); 154 static void siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t); 155 static void siba_powerup_sub(struct siba_softc *, int); 156 static int siba_powerdown_sub(struct siba_softc *); 157 static int siba_dev_isup_sub(struct siba_dev_softc *); 158 static void siba_dev_up_sub(struct siba_dev_softc *, uint32_t); 159 static void siba_dev_down_sub(struct siba_dev_softc *, uint32_t); 160 int siba_core_attach(struct siba_softc *); 161 int siba_core_detach(struct siba_softc *); 162 int siba_core_suspend(struct siba_softc *); 163 int siba_core_resume(struct siba_softc *); 164 uint8_t siba_getncores(device_t, uint16_t); 165 166 static const struct siba_bus_ops siba_pci_ops = { 167 .read_2 = siba_pci_read_2, 168 .read_4 = siba_pci_read_4, 169 .write_2 = siba_pci_write_2, 170 .write_4 = siba_pci_write_4, 171 .read_multi_1 = siba_pci_read_multi_1, 172 .read_multi_2 = siba_pci_read_multi_2, 173 .read_multi_4 = siba_pci_read_multi_4, 174 .write_multi_1 = siba_pci_write_multi_1, 175 .write_multi_2 = siba_pci_write_multi_2, 176 .write_multi_4 = siba_pci_write_multi_4, 177 }; 178 179 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] = 180 SIBA_CC_PMU_4325_RES_UPDOWN; 181 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] = 182 SIBA_CC_PMU_4325_RES_DEPEND; 183 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] = 184 SIBA_CC_PMU_4328_RES_UPDOWN; 185 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] = 186 SIBA_CC_PMU_4328_RES_DEPEND; 187 static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] = 188 SIBA_CC_PMU0_PLLTAB_ENTRY; 189 static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] = 190 SIBA_CC_PMU1_PLLTAB_ENTRY; 191 192 int 193 siba_core_attach(struct siba_softc *siba) 194 { 195 struct siba_cc *scc; 196 int error; 197 198 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 199 ("unsupported BUS type (%#x)", siba->siba_type)); 200 201 siba->siba_ops = &siba_pci_ops; 202 203 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); 204 siba_scan(siba); 205 206 /* XXX init PCI or PCMCIA host devices */ 207 208 siba_powerup_sub(siba, 0); 209 210 /* init ChipCommon */ 211 scc = &siba->siba_cc; 212 if (scc->scc_dev != NULL) { 213 siba_cc_pmu_init(scc); 214 siba_cc_power_init(scc); 215 siba_cc_clock(scc, SIBA_CLOCK_FAST); 216 siba_cc_powerup_delay(scc); 217 } 218 219 error = siba_pci_sprom(siba, &siba->siba_sprom); 220 if (error) { 221 siba_powerdown_sub(siba); 222 return (error); 223 } 224 225 siba_pcicore_init(&siba->siba_pci); 226 siba_powerdown_sub(siba); 227 228 return (bus_generic_attach(siba->siba_dev)); 229 } 230 231 int 232 siba_core_detach(struct siba_softc *siba) 233 { 234 /* detach & delete all children */ 235 device_delete_children(siba->siba_dev); 236 return (0); 237 } 238 239 static void 240 siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on) 241 { 242 uint32_t in, out; 243 uint16_t status; 244 245 if (siba->siba_type != SIBA_TYPE_PCI) 246 return; 247 248 out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4); 249 if (on == 0) { 250 if (what & SIBA_GPIO_PLL) 251 out |= SIBA_GPIO_PLL; 252 if (what & SIBA_GPIO_CRYSTAL) 253 out &= ~SIBA_GPIO_CRYSTAL; 254 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 255 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN, 256 pci_read_config(siba->siba_dev, 257 SIBA_GPIO_OUT_EN, 4) | what, 4); 258 return; 259 } 260 261 in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4); 262 if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) { 263 if (what & SIBA_GPIO_CRYSTAL) { 264 out |= SIBA_GPIO_CRYSTAL; 265 if (what & SIBA_GPIO_PLL) 266 out |= SIBA_GPIO_PLL; 267 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 268 pci_write_config(siba->siba_dev, 269 SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev, 270 SIBA_GPIO_OUT_EN, 4) | what, 4); 271 DELAY(1000); 272 } 273 if (what & SIBA_GPIO_PLL) { 274 out &= ~SIBA_GPIO_PLL; 275 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 276 DELAY(5000); 277 } 278 } 279 280 status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2); 281 status &= ~PCIM_STATUS_STABORT; 282 pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2); 283 } 284 285 static void 286 siba_scan(struct siba_softc *siba) 287 { 288 struct siba_dev_softc *sd; 289 uint32_t idhi, tmp; 290 device_t child; 291 int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0, 292 n_pci = 0; 293 294 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 295 ("unsupported BUS type (%#x)", siba->siba_type)); 296 297 siba->siba_ndevs = 0; 298 error = siba_switchcore(siba, 0); /* need the first core */ 299 if (error) 300 return; 301 302 idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH); 303 if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) { 304 tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID); 305 siba->siba_chipid = SIBA_CC_ID(tmp); 306 siba->siba_chiprev = SIBA_CC_REV(tmp); 307 siba->siba_chippkg = SIBA_CC_PKG(tmp); 308 if (SIBA_IDHIGH_REV(idhi) >= 4) 309 siba->siba_ndevs = SIBA_CC_NCORES(tmp); 310 siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0, 311 SIBA_CC_CAPS); 312 } else { 313 if (siba->siba_type == SIBA_TYPE_PCI) { 314 siba->siba_chipid = siba_dev2chipid(siba); 315 siba->siba_chiprev = pci_read_config(siba->siba_dev, 316 PCIR_REVID, 2); 317 siba->siba_chippkg = 0; 318 } else { 319 siba->siba_chipid = 0x4710; 320 siba->siba_chiprev = 0; 321 siba->siba_chippkg = 0; 322 } 323 } 324 if (siba->siba_ndevs == 0) 325 siba->siba_ndevs = siba_getncores(siba->siba_dev, 326 siba->siba_chipid); 327 if (siba->siba_ndevs > SIBA_MAX_CORES) { 328 device_printf(siba->siba_dev, 329 "too many siba cores (max %d %d)\n", 330 SIBA_MAX_CORES, siba->siba_ndevs); 331 return; 332 } 333 334 /* looking basic information about each cores/devices */ 335 for (i = 0; i < siba->siba_ndevs; i++) { 336 error = siba_switchcore(siba, i); 337 if (error) 338 return; 339 sd = &(siba->siba_devs[dev_i]); 340 idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH); 341 sd->sd_bus = siba; 342 sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi); 343 sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi); 344 sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi); 345 sd->sd_ops = siba->siba_ops; 346 sd->sd_coreidx = i; 347 348 DPRINTF(siba, SIBA_DEBUG_SCAN, 349 "core %d (%s) found (cc %#xrev %#x vendor %#x)\n", 350 i, siba_core_name(sd->sd_id.sd_device), 351 sd->sd_id.sd_device, sd->sd_id.sd_rev, sd->sd_id.sd_vendor); 352 353 switch (sd->sd_id.sd_device) { 354 case SIBA_DEVID_CHIPCOMMON: 355 n_cc++; 356 if (n_cc > 1) { 357 device_printf(siba->siba_dev, 358 "warn: multiple ChipCommon\n"); 359 break; 360 } 361 siba->siba_cc.scc_dev = sd; 362 break; 363 case SIBA_DEVID_80211: 364 n_80211++; 365 if (n_80211 > 1) { 366 device_printf(siba->siba_dev, 367 "warn: multiple 802.11 core\n"); 368 continue; 369 } 370 break; 371 case SIBA_DEVID_PCI: 372 case SIBA_DEVID_PCIE: 373 n_pci++; 374 #if defined(__DragonFly__) 375 error = pci_find_extcap(siba->siba_dev, PCIY_EXPRESS, 376 &base); 377 #else 378 error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS, 379 &base); 380 #endif 381 is_pcie = (error == 0) ? 1 : 0; 382 383 if (n_pci > 1) { 384 device_printf(siba->siba_dev, 385 "warn: multiple PCI(E) cores\n"); 386 break; 387 } 388 if (sd->sd_id.sd_device == SIBA_DEVID_PCI && 389 is_pcie == 1) 390 continue; 391 if (sd->sd_id.sd_device == SIBA_DEVID_PCIE && 392 is_pcie == 0) 393 continue; 394 siba->siba_pci.spc_dev = sd; 395 break; 396 case SIBA_DEVID_MODEM: 397 case SIBA_DEVID_PCMCIA: 398 break; 399 default: 400 device_printf(siba->siba_dev, 401 "unsupported coreid (%s)\n", 402 siba_core_name(sd->sd_id.sd_device)); 403 break; 404 } 405 dev_i++; 406 407 child = device_add_child(siba->siba_dev, NULL, -1); 408 if (child == NULL) { 409 device_printf(siba->siba_dev, "child attach failed\n"); 410 continue; 411 } 412 413 device_set_ivars(child, sd); 414 } 415 siba->siba_ndevs = dev_i; 416 } 417 418 static int 419 siba_switchcore(struct siba_softc *siba, uint8_t idx) 420 { 421 422 switch (siba->siba_type) { 423 case SIBA_TYPE_PCI: 424 return (siba_pci_switchcore_sub(siba, idx)); 425 default: 426 KASSERT(0 == 1, 427 ("%s: unsupported bustype %#x", __func__, 428 siba->siba_type)); 429 } 430 return (0); 431 } 432 433 static int 434 siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx) 435 { 436 #define RETRY_MAX 50 437 int i; 438 uint32_t dir; 439 440 dir = SIBA_REGWIN(idx); 441 442 for (i = 0; i < RETRY_MAX; i++) { 443 pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4); 444 if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir) 445 return (0); 446 DELAY(10); 447 } 448 return (ENODEV); 449 #undef RETRY_MAX 450 } 451 452 static int 453 siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd) 454 { 455 int error; 456 457 DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n", 458 siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx); 459 460 error = siba_pci_switchcore_sub(siba, sd->sd_coreidx); 461 if (error == 0) 462 siba->siba_curdev = sd; 463 464 return (error); 465 } 466 467 static uint32_t 468 siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx, 469 uint16_t offset) 470 { 471 472 (void)coreidx; 473 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 474 ("unsupported BUS type (%#x)", siba->siba_type)); 475 476 return (SIBA_READ_4(siba, offset)); 477 } 478 479 static uint16_t 480 siba_dev2chipid(struct siba_softc *siba) 481 { 482 uint16_t chipid = 0; 483 484 switch (siba->siba_pci_did) { 485 case 0x4301: 486 chipid = 0x4301; 487 break; 488 case 0x4305: 489 case 0x4306: 490 case 0x4307: 491 chipid = 0x4307; 492 break; 493 case 0x4403: 494 chipid = 0x4402; 495 break; 496 case 0x4610: 497 case 0x4611: 498 case 0x4612: 499 case 0x4613: 500 case 0x4614: 501 case 0x4615: 502 chipid = 0x4610; 503 break; 504 case 0x4710: 505 case 0x4711: 506 case 0x4712: 507 case 0x4713: 508 case 0x4714: 509 case 0x4715: 510 chipid = 0x4710; 511 break; 512 case 0x4320: 513 case 0x4321: 514 case 0x4322: 515 case 0x4323: 516 case 0x4324: 517 case 0x4325: 518 chipid = 0x4309; 519 break; 520 case PCI_DEVICE_ID_BCM4401: 521 case PCI_DEVICE_ID_BCM4401B0: 522 case PCI_DEVICE_ID_BCM4401B1: 523 chipid = 0x4401; 524 break; 525 default: 526 device_printf(siba->siba_dev, "unknown PCI did (%d)\n", 527 siba->siba_pci_did); 528 } 529 530 return (chipid); 531 } 532 533 /* 534 * Earlier ChipCommon revisions have hardcoded number of cores 535 * present dependent on the ChipCommon ID. 536 */ 537 uint8_t 538 siba_getncores(device_t dev, uint16_t chipid) 539 { 540 switch (chipid) { 541 case 0x4401: 542 case 0x4402: 543 return (3); 544 case 0x4301: 545 case 0x4307: 546 return (5); 547 case 0x4306: 548 return (6); 549 case SIBA_CCID_SENTRY5: 550 return (7); 551 case 0x4310: 552 return (8); 553 case SIBA_CCID_BCM4710: 554 case 0x4610: 555 case SIBA_CCID_BCM4704: 556 return (9); 557 default: 558 device_printf(dev, "unknown the chipset ID %#x\n", chipid); 559 } 560 561 return (1); 562 } 563 564 static const char * 565 siba_core_name(uint16_t coreid) 566 { 567 568 switch (coreid) { 569 case SIBA_DEVID_CHIPCOMMON: 570 return ("ChipCommon"); 571 case SIBA_DEVID_ILINE20: 572 return ("ILine 20"); 573 case SIBA_DEVID_SDRAM: 574 return ("SDRAM"); 575 case SIBA_DEVID_PCI: 576 return ("PCI"); 577 case SIBA_DEVID_MIPS: 578 return ("MIPS"); 579 case SIBA_DEVID_ETHERNET: 580 return ("Fast Ethernet"); 581 case SIBA_DEVID_MODEM: 582 return ("Modem"); 583 case SIBA_DEVID_USB11_HOSTDEV: 584 return ("USB 1.1 Hostdev"); 585 case SIBA_DEVID_ADSL: 586 return ("ADSL"); 587 case SIBA_DEVID_ILINE100: 588 return ("ILine 100"); 589 case SIBA_DEVID_IPSEC: 590 return ("IPSEC"); 591 case SIBA_DEVID_PCMCIA: 592 return ("PCMCIA"); 593 case SIBA_DEVID_INTERNAL_MEM: 594 return ("Internal Memory"); 595 case SIBA_DEVID_SDRAMDDR: 596 return ("MEMC SDRAM"); 597 case SIBA_DEVID_EXTIF: 598 return ("EXTIF"); 599 case SIBA_DEVID_80211: 600 return ("IEEE 802.11"); 601 case SIBA_DEVID_MIPS_3302: 602 return ("MIPS 3302"); 603 case SIBA_DEVID_USB11_HOST: 604 return ("USB 1.1 Host"); 605 case SIBA_DEVID_USB11_DEV: 606 return ("USB 1.1 Device"); 607 case SIBA_DEVID_USB20_HOST: 608 return ("USB 2.0 Host"); 609 case SIBA_DEVID_USB20_DEV: 610 return ("USB 2.0 Device"); 611 case SIBA_DEVID_SDIO_HOST: 612 return ("SDIO Host"); 613 case SIBA_DEVID_ROBOSWITCH: 614 return ("Roboswitch"); 615 case SIBA_DEVID_PARA_ATA: 616 return ("PATA"); 617 case SIBA_DEVID_SATA_XORDMA: 618 return ("SATA XOR-DMA"); 619 case SIBA_DEVID_ETHERNET_GBIT: 620 return ("GBit Ethernet"); 621 case SIBA_DEVID_PCIE: 622 return ("PCI-Express"); 623 case SIBA_DEVID_MIMO_PHY: 624 return ("MIMO PHY"); 625 case SIBA_DEVID_SRAM_CTRLR: 626 return ("SRAM Controller"); 627 case SIBA_DEVID_MINI_MACPHY: 628 return ("Mini MACPHY"); 629 case SIBA_DEVID_ARM_1176: 630 return ("ARM 1176"); 631 case SIBA_DEVID_ARM_7TDMI: 632 return ("ARM 7TDMI"); 633 } 634 return ("unknown"); 635 } 636 637 static uint16_t 638 siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset) 639 { 640 struct siba_softc *siba = sd->sd_bus; 641 642 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 643 return (0xffff); 644 645 return (SIBA_READ_2(siba, offset)); 646 } 647 648 static uint32_t 649 siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset) 650 { 651 struct siba_softc *siba = sd->sd_bus; 652 653 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 654 return (0xffff); 655 656 return (SIBA_READ_4(siba, offset)); 657 } 658 659 static void 660 siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value) 661 { 662 struct siba_softc *siba = sd->sd_bus; 663 664 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 665 return; 666 667 SIBA_WRITE_2(siba, offset, value); 668 } 669 670 static void 671 siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) 672 { 673 struct siba_softc *siba = sd->sd_bus; 674 675 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 676 return; 677 678 SIBA_WRITE_4(siba, offset, value); 679 } 680 681 static void 682 siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count, 683 uint16_t offset) 684 { 685 struct siba_softc *siba = sd->sd_bus; 686 687 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 688 memset(buffer, 0xff, count); 689 return; 690 } 691 692 SIBA_READ_MULTI_1(siba, offset, buffer, count); 693 } 694 695 static void 696 siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count, 697 uint16_t offset) 698 { 699 struct siba_softc *siba = sd->sd_bus; 700 701 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 702 memset(buffer, 0xff, count); 703 return; 704 } 705 706 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); 707 SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1); 708 } 709 710 static void 711 siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count, 712 uint16_t offset) 713 { 714 struct siba_softc *siba = sd->sd_bus; 715 716 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 717 memset(buffer, 0xff, count); 718 return; 719 } 720 721 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); 722 SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2); 723 } 724 725 static void 726 siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer, 727 size_t count, uint16_t offset) 728 { 729 struct siba_softc *siba = sd->sd_bus; 730 731 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 732 return; 733 734 SIBA_WRITE_MULTI_1(siba, offset, buffer, count); 735 } 736 737 static void 738 siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer, 739 size_t count, uint16_t offset) 740 { 741 struct siba_softc *siba = sd->sd_bus; 742 743 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 744 return; 745 746 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); 747 SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1); 748 } 749 750 static void 751 siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer, 752 size_t count, uint16_t offset) 753 { 754 struct siba_softc *siba = sd->sd_bus; 755 756 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 757 return; 758 759 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); 760 SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2); 761 } 762 763 void 764 siba_powerup(device_t dev, int dynamic) 765 { 766 struct siba_dev_softc *sd = device_get_ivars(dev); 767 struct siba_softc *siba = sd->sd_bus; 768 769 siba_powerup_sub(siba, dynamic); 770 } 771 772 static void 773 siba_powerup_sub(struct siba_softc *siba, int dynamic) 774 { 775 776 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); 777 siba_cc_clock(&siba->siba_cc, 778 (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST); 779 } 780 781 static void 782 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock) 783 { 784 struct siba_dev_softc *sd = scc->scc_dev; 785 struct siba_softc *siba; 786 uint32_t tmp; 787 788 if (sd == NULL) 789 return; 790 siba = sd->sd_bus; 791 /* 792 * chipcommon < r6 (no dynamic clock control) 793 * chipcommon >= r10 (unknown) 794 */ 795 if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 || 796 (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) 797 return; 798 799 switch (clock) { 800 case SIBA_CLOCK_DYNAMIC: 801 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 802 ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW | 803 SIBA_CC_CLKSLOW_IPLL); 804 if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL) 805 tmp |= SIBA_CC_CLKSLOW_ENXTAL; 806 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp); 807 if (tmp & SIBA_CC_CLKSLOW_ENXTAL) 808 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0); 809 break; 810 case SIBA_CLOCK_SLOW: 811 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, 812 SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | 813 SIBA_CC_CLKSLOW_FSLOW); 814 break; 815 case SIBA_CLOCK_FAST: 816 /* crystal on */ 817 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1); 818 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, 819 (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | 820 SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW); 821 break; 822 default: 823 KASSERT(0 == 1, 824 ("%s: unsupported clock %#x", __func__, clock)); 825 } 826 } 827 828 uint16_t 829 siba_read_2(device_t dev, uint16_t offset) 830 { 831 struct siba_dev_softc *sd = device_get_ivars(dev); 832 833 return (sd->sd_ops->read_2(sd, offset)); 834 } 835 836 uint32_t 837 siba_read_4(device_t dev, uint16_t offset) 838 { 839 struct siba_dev_softc *sd = device_get_ivars(dev); 840 841 return (siba_read_4_sub(sd, offset)); 842 } 843 844 static uint32_t 845 siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset) 846 { 847 848 return (sd->sd_ops->read_4(sd, offset)); 849 } 850 851 void 852 siba_write_2(device_t dev, uint16_t offset, uint16_t value) 853 { 854 struct siba_dev_softc *sd = device_get_ivars(dev); 855 856 sd->sd_ops->write_2(sd, offset, value); 857 } 858 859 void 860 siba_write_4(device_t dev, uint16_t offset, uint32_t value) 861 { 862 struct siba_dev_softc *sd = device_get_ivars(dev); 863 864 return (siba_write_4_sub(sd, offset, value)); 865 } 866 867 static void 868 siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) 869 { 870 871 sd->sd_ops->write_4(sd, offset, value); 872 } 873 874 void 875 siba_read_multi_1(device_t dev, void *buffer, size_t count, 876 uint16_t offset) 877 { 878 struct siba_dev_softc *sd = device_get_ivars(dev); 879 880 sd->sd_ops->read_multi_1(sd, buffer, count, offset); 881 } 882 883 void 884 siba_read_multi_2(device_t dev, void *buffer, size_t count, 885 uint16_t offset) 886 { 887 struct siba_dev_softc *sd = device_get_ivars(dev); 888 889 sd->sd_ops->read_multi_2(sd, buffer, count, offset); 890 } 891 892 void 893 siba_read_multi_4(device_t dev, void *buffer, size_t count, 894 uint16_t offset) 895 { 896 struct siba_dev_softc *sd = device_get_ivars(dev); 897 898 sd->sd_ops->read_multi_4(sd, buffer, count, offset); 899 } 900 901 void 902 siba_write_multi_1(device_t dev, const void *buffer, size_t count, 903 uint16_t offset) 904 { 905 struct siba_dev_softc *sd = device_get_ivars(dev); 906 907 sd->sd_ops->write_multi_1(sd, buffer, count, offset); 908 } 909 910 void 911 siba_write_multi_2(device_t dev, const void *buffer, size_t count, 912 uint16_t offset) 913 { 914 struct siba_dev_softc *sd = device_get_ivars(dev); 915 916 sd->sd_ops->write_multi_2(sd, buffer, count, offset); 917 } 918 919 void 920 siba_write_multi_4(device_t dev, const void *buffer, size_t count, 921 uint16_t offset) 922 { 923 struct siba_dev_softc *sd = device_get_ivars(dev); 924 925 sd->sd_ops->write_multi_4(sd, buffer, count, offset); 926 } 927 928 static void 929 siba_cc_pmu_init(struct siba_cc *scc) 930 { 931 const struct siba_cc_pmu_res_updown *updown = NULL; 932 const struct siba_cc_pmu_res_depend *depend = NULL; 933 struct siba_dev_softc *sd = scc->scc_dev; 934 struct siba_softc *siba = sd->sd_bus; 935 uint32_t min = 0, max = 0, pmucap; 936 unsigned int i, updown_size, depend_size; 937 938 if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0) 939 return; 940 941 pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS); 942 scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV); 943 944 DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n", 945 scc->scc_pmu.rev, pmucap); 946 947 if (scc->scc_pmu.rev >= 1) { 948 if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325) 949 SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, 950 ~SIBA_CC_PMUCTL_NOILP); 951 else 952 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, 953 SIBA_CC_PMUCTL_NOILP); 954 } 955 956 /* initialize PLL & PMU resources */ 957 switch (siba->siba_chipid) { 958 case 0x4312: 959 siba_cc_pmu1_pll0_init(scc, 0 /* use default */); 960 /* use the default: min = 0xcbb max = 0x7ffff */ 961 break; 962 case 0x4325: 963 siba_cc_pmu1_pll0_init(scc, 0 /* use default */); 964 965 updown = siba_cc_pmu_4325_updown; 966 updown_size = N(siba_cc_pmu_4325_updown); 967 depend = siba_cc_pmu_4325_depend; 968 depend_size = N(siba_cc_pmu_4325_depend); 969 970 min = (1 << SIBA_CC_PMU_4325_BURST) | 971 (1 << SIBA_CC_PMU_4325_LN); 972 if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) & 973 SIBA_CC_CHST_4325_PMUTOP_2B) 974 min |= (1 << SIBA_CC_PMU_4325_CLBURST); 975 max = 0xfffff; 976 break; 977 case 0x4328: 978 siba_cc_pmu0_pll0_init(scc, 0 /* use default */); 979 980 updown = siba_cc_pmu_4328_updown; 981 updown_size = N(siba_cc_pmu_4328_updown); 982 depend = siba_cc_pmu_4328_depend; 983 depend_size = N(siba_cc_pmu_4328_depend); 984 985 min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | 986 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) | 987 (1 << SIBA_CC_PMU_4328_CRYSTAL_EN); 988 989 max = 0xfffff; 990 break; 991 case 0x5354: 992 siba_cc_pmu0_pll0_init(scc, 0 /* use default */); 993 994 max = 0xfffff; 995 break; 996 default: 997 device_printf(siba->siba_dev, 998 "unknown chipid %#x for PLL & PMU init\n", 999 siba->siba_chipid); 1000 } 1001 1002 if (updown) { 1003 for (i = 0; i < updown_size; i++) { 1004 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, 1005 updown[i].res); 1006 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM, 1007 updown[i].updown); 1008 } 1009 } 1010 if (depend) { 1011 for (i = 0; i < depend_size; i++) { 1012 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, 1013 depend[i].res); 1014 switch (depend[i].task) { 1015 case SIBA_CC_PMU_DEP_SET: 1016 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK, 1017 depend[i].depend); 1018 break; 1019 case SIBA_CC_PMU_DEP_ADD: 1020 SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK, 1021 depend[i].depend); 1022 break; 1023 case SIBA_CC_PMU_DEP_REMOVE: 1024 SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK, 1025 ~(depend[i].depend)); 1026 break; 1027 default: 1028 KASSERT(0 == 1, 1029 ("%s:%d: assertion failed", 1030 __func__, __LINE__)); 1031 } 1032 } 1033 } 1034 1035 if (min) 1036 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min); 1037 if (max) 1038 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max); 1039 } 1040 1041 static void 1042 siba_cc_power_init(struct siba_cc *scc) 1043 { 1044 struct siba_softc *siba = scc->scc_dev->sd_bus; 1045 int maxfreq; 1046 1047 if (siba->siba_chipid == 0x4321) { 1048 if (siba->siba_chiprev == 0) 1049 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4); 1050 else if (siba->siba_chiprev == 1) 1051 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4); 1052 } 1053 1054 if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) 1055 return; 1056 1057 if (scc->scc_dev->sd_id.sd_rev >= 10) 1058 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL, 1059 (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) & 1060 0xffff) | 0x40000); 1061 else { 1062 maxfreq = siba_cc_clockfreq(scc, 1); 1063 SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY, 1064 (maxfreq * 150 + 999999) / 1000000); 1065 SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY, 1066 (maxfreq * 15 + 999999) / 1000000); 1067 } 1068 } 1069 1070 static void 1071 siba_cc_powerup_delay(struct siba_cc *scc) 1072 { 1073 struct siba_softc *siba = scc->scc_dev->sd_bus; 1074 int min; 1075 1076 if (siba->siba_type != SIBA_TYPE_PCI || 1077 !(scc->scc_caps & SIBA_CC_CAPS_PWCTL)) 1078 return; 1079 1080 min = siba_cc_clockfreq(scc, 0); 1081 scc->scc_powerup_delay = 1082 howmany((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000, 1083 min); 1084 } 1085 1086 static int 1087 siba_cc_clockfreq(struct siba_cc *scc, int max) 1088 { 1089 enum siba_clksrc src; 1090 int div = 1, limit = 0; 1091 1092 src = siba_cc_clksrc(scc); 1093 if (scc->scc_dev->sd_id.sd_rev < 6) { 1094 div = (src == SIBA_CC_CLKSRC_PCI) ? 64 : 1095 (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1; 1096 KASSERT(div != 1, 1097 ("%s: unknown clock %d", __func__, src)); 1098 } else if (scc->scc_dev->sd_id.sd_rev < 10) { 1099 switch (src) { 1100 case SIBA_CC_CLKSRC_CRYSTAL: 1101 case SIBA_CC_CLKSRC_PCI: 1102 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) + 1103 1) * 4; 1104 break; 1105 case SIBA_CC_CLKSRC_LOWPW: 1106 break; 1107 } 1108 } else 1109 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4; 1110 1111 switch (src) { 1112 case SIBA_CC_CLKSRC_CRYSTAL: 1113 limit = (max) ? 20200000 : 19800000; 1114 break; 1115 case SIBA_CC_CLKSRC_LOWPW: 1116 limit = (max) ? 43000 : 25000; 1117 break; 1118 case SIBA_CC_CLKSRC_PCI: 1119 limit = (max) ? 34000000 : 25000000; 1120 break; 1121 } 1122 1123 return (limit / div); 1124 } 1125 1126 static void 1127 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq) 1128 { 1129 struct siba_dev_softc *sd = scc->scc_dev; 1130 struct siba_softc *siba = sd->sd_bus; 1131 const struct siba_cc_pmu1_plltab *e = NULL; 1132 uint32_t bufsth = 0, pll, pmu; 1133 unsigned int i; 1134 1135 KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__)); 1136 if (siba->siba_chipid == 0x4312) { 1137 scc->scc_pmu.freq = 20000; 1138 return; 1139 } 1140 1141 e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ); 1142 KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__)); 1143 scc->scc_pmu.freq = e->freq; 1144 1145 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1146 if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf) 1147 return; 1148 1149 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", 1150 (e->freq / 1000), (e->freq % 1000)); 1151 1152 /* turn PLL off */ 1153 switch (siba->siba_chipid) { 1154 case 0x4325: 1155 bufsth = 0x222222; 1156 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1157 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | 1158 (1 << SIBA_CC_PMU_4325_HT))); 1159 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1160 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | 1161 (1 << SIBA_CC_PMU_4325_HT))); 1162 break; 1163 default: 1164 KASSERT(0 == 1, 1165 ("%s:%d: assertion failed", __func__, __LINE__)); 1166 } 1167 for (i = 0; i < 1500; i++) { 1168 if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & 1169 SIBA_CC_CLKCTLSTATUS_HT)) 1170 break; 1171 DELAY(10); 1172 } 1173 if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT) 1174 device_printf(siba->siba_dev, "failed to turn PLL off!\n"); 1175 1176 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0); 1177 pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV); 1178 pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV; 1179 pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV; 1180 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll); 1181 1182 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2); 1183 pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE); 1184 pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT; 1185 pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE; 1186 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll); 1187 1188 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3); 1189 pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC; 1190 pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC; 1191 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll); 1192 1193 if (bufsth) { 1194 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5); 1195 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV; 1196 pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV; 1197 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll); 1198 } 1199 1200 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1201 pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF); 1202 pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) & 1203 SIBA_CC_PMUCTL_ILP; 1204 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; 1205 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); 1206 } 1207 1208 static void 1209 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq) 1210 { 1211 struct siba_dev_softc *sd = scc->scc_dev; 1212 struct siba_softc *siba = sd->sd_bus; 1213 const struct siba_cc_pmu0_plltab *e = NULL; 1214 uint32_t pmu, tmp, pll; 1215 unsigned int i; 1216 1217 if ((siba->siba_chipid == 0x5354) && !xtalfreq) 1218 xtalfreq = 25000; 1219 if (xtalfreq) 1220 e = siba_cc_pmu0_plltab_findentry(xtalfreq); 1221 if (!e) 1222 e = siba_cc_pmu0_plltab_findentry( 1223 SIBA_CC_PMU0_DEFAULT_XTALFREQ); 1224 KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__)); 1225 xtalfreq = e->freq; 1226 scc->scc_pmu.freq = e->freq; 1227 1228 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1229 if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf) 1230 return; 1231 1232 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", 1233 (xtalfreq / 1000), (xtalfreq % 1000)); 1234 1235 KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354, 1236 ("%s:%d: fail", __func__, __LINE__)); 1237 1238 switch (siba->siba_chipid) { 1239 case 0x4328: 1240 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1241 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); 1242 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1243 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); 1244 break; 1245 case 0x5354: 1246 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1247 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); 1248 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1249 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); 1250 break; 1251 } 1252 for (i = 1500; i; i--) { 1253 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); 1254 if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT)) 1255 break; 1256 DELAY(10); 1257 } 1258 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); 1259 if (tmp & SIBA_CC_CLKCTLSTATUS_HT) 1260 device_printf(siba->siba_dev, "failed to turn PLL off!\n"); 1261 1262 /* set PDIV */ 1263 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0); 1264 if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ) 1265 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK; 1266 else 1267 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK; 1268 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll); 1269 1270 /* set WILD */ 1271 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1); 1272 pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK | 1273 SIBA_CC_PMU0_PLL1_FMSK); 1274 pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK; 1275 pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK; 1276 if (e->wb_frac == 0) 1277 pll |= SIBA_CC_PMU0_PLL1_STOPMOD; 1278 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll); 1279 1280 /* set WILD */ 1281 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2); 1282 pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI; 1283 pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI; 1284 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll); 1285 1286 /* set freq and divisor. */ 1287 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1288 pmu &= ~SIBA_CC_PMUCTL_ILP; 1289 pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP; 1290 pmu &= ~SIBA_CC_PMUCTL_XF; 1291 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; 1292 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); 1293 } 1294 1295 static enum siba_clksrc 1296 siba_cc_clksrc(struct siba_cc *scc) 1297 { 1298 struct siba_dev_softc *sd = scc->scc_dev; 1299 struct siba_softc *siba = sd->sd_bus; 1300 1301 if (sd->sd_id.sd_rev < 6) { 1302 if (siba->siba_type == SIBA_TYPE_PCI) { 1303 if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) & 1304 0x10) 1305 return (SIBA_CC_CLKSRC_PCI); 1306 return (SIBA_CC_CLKSRC_CRYSTAL); 1307 } 1308 if (siba->siba_type == SIBA_TYPE_SSB || 1309 siba->siba_type == SIBA_TYPE_PCMCIA) 1310 return (SIBA_CC_CLKSRC_CRYSTAL); 1311 } 1312 if (sd->sd_id.sd_rev < 10) { 1313 switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) { 1314 case 0: 1315 return (SIBA_CC_CLKSRC_LOWPW); 1316 case 1: 1317 return (SIBA_CC_CLKSRC_CRYSTAL); 1318 case 2: 1319 return (SIBA_CC_CLKSRC_PCI); 1320 default: 1321 break; 1322 } 1323 } 1324 1325 return (SIBA_CC_CLKSRC_CRYSTAL); 1326 } 1327 1328 static const struct siba_cc_pmu1_plltab * 1329 siba_cc_pmu1_plltab_find(uint32_t crystalfreq) 1330 { 1331 const struct siba_cc_pmu1_plltab *e; 1332 unsigned int i; 1333 1334 for (i = 0; i < N(siba_cc_pmu1_plltab); i++) { 1335 e = &siba_cc_pmu1_plltab[i]; 1336 if (crystalfreq == e->freq) 1337 return (e); 1338 } 1339 1340 return (NULL); 1341 } 1342 1343 static uint32_t 1344 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset) 1345 { 1346 1347 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); 1348 return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA)); 1349 } 1350 1351 static void 1352 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value) 1353 { 1354 1355 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); 1356 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value); 1357 } 1358 1359 static const struct siba_cc_pmu0_plltab * 1360 siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq) 1361 { 1362 const struct siba_cc_pmu0_plltab *e; 1363 unsigned int i; 1364 1365 for (i = 0; i < N(siba_cc_pmu0_plltab); i++) { 1366 e = &siba_cc_pmu0_plltab[i]; 1367 if (e->freq == crystalfreq) 1368 return (e); 1369 } 1370 1371 return (NULL); 1372 } 1373 1374 static int 1375 siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom) 1376 { 1377 int error = ENOMEM; 1378 uint16_t *buf; 1379 1380 buf = kmalloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t), 1381 M_DEVBUF, M_INTWAIT | M_ZERO); 1382 if (buf == NULL) 1383 return (ENOMEM); 1384 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123); 1385 error = sprom_check_crc(buf, siba->siba_spromsize); 1386 if (error) { 1387 kfree(buf, M_DEVBUF); 1388 buf = kmalloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t), 1389 M_DEVBUF, M_INTWAIT | M_ZERO); 1390 if (buf == NULL) 1391 return (ENOMEM); 1392 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4); 1393 error = sprom_check_crc(buf, siba->siba_spromsize); 1394 if (error) 1395 device_printf(siba->siba_dev, "warn: bad SPROM CRC\n"); 1396 } 1397 1398 bzero(sprom, sizeof(*sprom)); 1399 1400 sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF; 1401 DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n", 1402 sprom->rev); 1403 memset(sprom->mac_eth, 0xff, 6); 1404 memset(sprom->mac_80211a, 0xff, 6); 1405 if ((siba->siba_chipid & 0xff00) == 0x4400) { 1406 sprom->rev = 1; 1407 siba_sprom_r123(sprom, buf); 1408 } else if (siba->siba_chipid == 0x4321) { 1409 sprom->rev = 4; 1410 siba_sprom_r45(sprom, buf); 1411 } else { 1412 switch (sprom->rev) { 1413 case 1: 1414 case 2: 1415 case 3: 1416 siba_sprom_r123(sprom, buf); 1417 break; 1418 case 4: 1419 case 5: 1420 siba_sprom_r45(sprom, buf); 1421 break; 1422 case 8: 1423 siba_sprom_r8(sprom, buf); 1424 break; 1425 default: 1426 device_printf(siba->siba_dev, 1427 "unknown SPROM revision %d.\n", sprom->rev); 1428 siba_sprom_r123(sprom, buf); 1429 } 1430 } 1431 1432 if (sprom->bf_lo == 0xffff) 1433 sprom->bf_lo = 0; 1434 if (sprom->bf_hi == 0xffff) 1435 sprom->bf_hi = 0; 1436 1437 kfree(buf, M_DEVBUF); 1438 return (error); 1439 } 1440 1441 static int 1442 siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len) 1443 { 1444 int i; 1445 1446 for (i = 0; i < len; i++) 1447 sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2)); 1448 1449 siba->siba_spromsize = len; 1450 return (0); 1451 } 1452 1453 static int 1454 sprom_check_crc(const uint16_t *sprom, size_t size) 1455 { 1456 int word; 1457 uint8_t crc0, crc1 = 0xff; 1458 1459 crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8; 1460 for (word = 0; word < size - 1; word++) { 1461 crc1 = siba_crc8(crc1, sprom[word] & 0x00ff); 1462 crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8); 1463 } 1464 crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff); 1465 crc1 ^= 0xff; 1466 1467 return ((crc0 != crc1) ? EPROTO : 0); 1468 } 1469 1470 static uint8_t 1471 siba_crc8(uint8_t crc, uint8_t data) 1472 { 1473 static const uint8_t ct[] = { 1474 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b, 1475 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21, 1476 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff, 1477 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5, 1478 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14, 1479 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e, 1480 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80, 1481 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca, 1482 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95, 1483 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf, 1484 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01, 1485 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b, 1486 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea, 1487 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0, 1488 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e, 1489 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34, 1490 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0, 1491 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a, 1492 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54, 1493 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e, 1494 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf, 1495 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5, 1496 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b, 1497 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61, 1498 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e, 1499 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74, 1500 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa, 1501 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0, 1502 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41, 1503 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b, 1504 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5, 1505 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f, 1506 }; 1507 return (ct[crc ^ data]); 1508 } 1509 1510 #define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 1511 #define SIBA_OFFSET(offset) \ 1512 (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t)) 1513 #define SIBA_SHIFTOUT_SUB(__x, __mask) \ 1514 (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask)) 1515 #define SIBA_SHIFTOUT(_var, _offset, _mask) \ 1516 out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask)) 1517 #define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift) \ 1518 out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 | \ 1519 in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift)) 1520 1521 static void 1522 siba_sprom_r123(struct siba_sprom *out, const uint16_t *in) 1523 { 1524 int i; 1525 uint16_t v; 1526 int8_t gain; 1527 uint16_t loc[3]; 1528 1529 if (out->rev == 3) 1530 loc[0] = SIBA_SPROM3_MAC_80211BG; 1531 else { 1532 loc[0] = SIBA_SPROM1_MAC_80211BG; 1533 loc[1] = SIBA_SPROM1_MAC_ETH; 1534 loc[2] = SIBA_SPROM1_MAC_80211A; 1535 } 1536 for (i = 0; i < 3; i++) { 1537 v = in[SIBA_OFFSET(loc[0]) + i]; 1538 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1539 } 1540 if (out->rev < 3) { 1541 for (i = 0; i < 3; i++) { 1542 v = in[SIBA_OFFSET(loc[1]) + i]; 1543 *(((uint16_t *)out->mac_eth) + i) = htobe16(v); 1544 } 1545 for (i = 0; i < 3; i++) { 1546 v = in[SIBA_OFFSET(loc[2]) + i]; 1547 *(((uint16_t *)out->mac_80211a) + i) = htobe16(v); 1548 } 1549 } 1550 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY, 1551 SIBA_SPROM1_ETHPHY_MII_ETH0); 1552 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY, 1553 SIBA_SPROM1_ETHPHY_MII_ETH1); 1554 SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY, 1555 SIBA_SPROM1_ETHPHY_MDIO_ETH0); 1556 SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY, 1557 SIBA_SPROM1_ETHPHY_MDIO_ETH1); 1558 SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV); 1559 SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO, 1560 SIBA_SPROM1_BOARDINFO_CCODE); 1561 SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA); 1562 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO, 1563 SIBA_SPROM1_BOARDINFO_ANTBG); 1564 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff); 1565 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff); 1566 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff); 1567 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff); 1568 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff); 1569 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff); 1570 SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0); 1571 SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1); 1572 SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2); 1573 SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3); 1574 1575 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A); 1576 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG); 1577 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A); 1578 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG); 1579 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff); 1580 if (out->rev >= 2) 1581 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff); 1582 1583 /* antenna gain */ 1584 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0); 1585 out->again.ghz24.a0 = out->again.ghz24.a1 = gain; 1586 out->again.ghz24.a2 = out->again.ghz24.a3 = gain; 1587 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8); 1588 out->again.ghz5.a0 = out->again.ghz5.a1 = gain; 1589 out->again.ghz5.a2 = out->again.ghz5.a3 = gain; 1590 } 1591 1592 static void 1593 siba_sprom_r458(struct siba_sprom *out, const uint16_t *in) 1594 { 1595 1596 SIBA_SHIFTOUT(txpid2g[0], SIBA_SPROM4_TXPID2G01, 1597 SIBA_SPROM4_TXPID2G0); 1598 SIBA_SHIFTOUT(txpid2g[1], SIBA_SPROM4_TXPID2G01, 1599 SIBA_SPROM4_TXPID2G1); 1600 SIBA_SHIFTOUT(txpid2g[2], SIBA_SPROM4_TXPID2G23, 1601 SIBA_SPROM4_TXPID2G2); 1602 SIBA_SHIFTOUT(txpid2g[3], SIBA_SPROM4_TXPID2G23, 1603 SIBA_SPROM4_TXPID2G3); 1604 1605 SIBA_SHIFTOUT(txpid5gl[0], SIBA_SPROM4_TXPID5GL01, 1606 SIBA_SPROM4_TXPID5GL0); 1607 SIBA_SHIFTOUT(txpid5gl[1], SIBA_SPROM4_TXPID5GL01, 1608 SIBA_SPROM4_TXPID5GL1); 1609 SIBA_SHIFTOUT(txpid5gl[2], SIBA_SPROM4_TXPID5GL23, 1610 SIBA_SPROM4_TXPID5GL2); 1611 SIBA_SHIFTOUT(txpid5gl[3], SIBA_SPROM4_TXPID5GL23, 1612 SIBA_SPROM4_TXPID5GL3); 1613 1614 SIBA_SHIFTOUT(txpid5g[0], SIBA_SPROM4_TXPID5G01, 1615 SIBA_SPROM4_TXPID5G0); 1616 SIBA_SHIFTOUT(txpid5g[1], SIBA_SPROM4_TXPID5G01, 1617 SIBA_SPROM4_TXPID5G1); 1618 SIBA_SHIFTOUT(txpid5g[2], SIBA_SPROM4_TXPID5G23, 1619 SIBA_SPROM4_TXPID5G2); 1620 SIBA_SHIFTOUT(txpid5g[3], SIBA_SPROM4_TXPID5G23, 1621 SIBA_SPROM4_TXPID5G3); 1622 1623 SIBA_SHIFTOUT(txpid5gh[0], SIBA_SPROM4_TXPID5GH01, 1624 SIBA_SPROM4_TXPID5GH0); 1625 SIBA_SHIFTOUT(txpid5gh[1], SIBA_SPROM4_TXPID5GH01, 1626 SIBA_SPROM4_TXPID5GH1); 1627 SIBA_SHIFTOUT(txpid5gh[2], SIBA_SPROM4_TXPID5GH23, 1628 SIBA_SPROM4_TXPID5GH2); 1629 SIBA_SHIFTOUT(txpid5gh[3], SIBA_SPROM4_TXPID5GH23, 1630 SIBA_SPROM4_TXPID5GH3); 1631 } 1632 1633 static void 1634 siba_sprom_r45(struct siba_sprom *out, const uint16_t *in) 1635 { 1636 int i; 1637 uint16_t v; 1638 uint16_t mac_80211bg_offset; 1639 const uint16_t pwr_info_offset[] = { 1640 SIBA_SPROM4_PWR_INFO_CORE0, SIBA_SPROM4_PWR_INFO_CORE1, 1641 SIBA_SPROM4_PWR_INFO_CORE2, SIBA_SPROM4_PWR_INFO_CORE3 1642 }; 1643 1644 if (out->rev == 4) 1645 mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG; 1646 else 1647 mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG; 1648 for (i = 0; i < 3; i++) { 1649 v = in[SIBA_OFFSET(mac_80211bg_offset) + i]; 1650 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1651 } 1652 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A); 1653 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A); 1654 if (out->rev == 4) { 1655 SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff); 1656 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff); 1657 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff); 1658 } else { 1659 SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff); 1660 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff); 1661 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff); 1662 } 1663 SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A); 1664 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG); 1665 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK); 1666 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG); 1667 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK); 1668 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A); 1669 if (out->rev == 4) { 1670 SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0); 1671 SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1); 1672 SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2); 1673 SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3); 1674 } else { 1675 SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0); 1676 SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1); 1677 SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2); 1678 SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3); 1679 } 1680 1681 /* antenna gain */ 1682 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0); 1683 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1); 1684 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2); 1685 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3); 1686 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); 1687 1688 /* Extract core power info */ 1689 for (i = 0; i < nitems(pwr_info_offset); i++) { 1690 uint16_t o = pwr_info_offset[i]; 1691 1692 SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, 1693 SIBA_SPROM4_2G_ITSSI); 1694 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, 1695 SIBA_SPROM4_2G_MAXP); 1696 1697 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SPROM4_2G_PA_0, ~0); 1698 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SPROM4_2G_PA_1, ~0); 1699 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SPROM4_2G_PA_2, ~0); 1700 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[3], o + SIBA_SPROM4_2G_PA_3, ~0); 1701 1702 SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, 1703 SIBA_SPROM4_5G_ITSSI); 1704 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, 1705 SIBA_SPROM4_5G_MAXP); 1706 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM4_5GHL_MAXP, 1707 SIBA_SPROM4_5GH_MAXP); 1708 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM4_5GHL_MAXP, 1709 SIBA_SPROM4_5GL_MAXP); 1710 1711 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SPROM4_5GL_PA_0, ~0); 1712 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SPROM4_5GL_PA_1, ~0); 1713 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SPROM4_5GL_PA_2, ~0); 1714 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[3], o + SIBA_SPROM4_5GL_PA_3, ~0); 1715 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SPROM4_5G_PA_0, ~0); 1716 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SPROM4_5G_PA_1, ~0); 1717 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SPROM4_5G_PA_2, ~0); 1718 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[3], o + SIBA_SPROM4_5G_PA_3, ~0); 1719 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SPROM4_5GH_PA_0, ~0); 1720 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SPROM4_5GH_PA_1, ~0); 1721 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SPROM4_5GH_PA_2, ~0); 1722 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[3], o + SIBA_SPROM4_5GH_PA_3, ~0); 1723 } 1724 1725 siba_sprom_r458(out, in); 1726 } 1727 1728 static void 1729 siba_sprom_r8(struct siba_sprom *out, const uint16_t *in) 1730 { 1731 int i; 1732 uint16_t v; 1733 uint16_t pwr_info_offset[] = { 1734 SIBA_SROM8_PWR_INFO_CORE0, SIBA_SROM8_PWR_INFO_CORE1, 1735 SIBA_SROM8_PWR_INFO_CORE2, SIBA_SROM8_PWR_INFO_CORE3 1736 }; 1737 1738 for (i = 0; i < 3; i++) { 1739 v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i]; 1740 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1741 } 1742 SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff); 1743 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff); 1744 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff); 1745 SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff); 1746 SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff); 1747 SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A); 1748 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG); 1749 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK); 1750 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG); 1751 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK); 1752 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A); 1753 SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL, 1754 SIBA_SPROM8_MAXP_AH_MASK); 1755 SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL, 1756 SIBA_SPROM8_MAXP_AL_MASK); 1757 SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0); 1758 SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1); 1759 SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2); 1760 SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3); 1761 SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G); 1762 SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G); 1763 SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL); 1764 SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH); 1765 SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G); 1766 SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G); 1767 1768 SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G); 1769 SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G); 1770 SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G); 1771 SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G); 1772 SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G); 1773 SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G); 1774 SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G); 1775 SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G); 1776 1777 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff); 1778 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff); 1779 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff); 1780 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff); 1781 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff); 1782 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff); 1783 SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff); 1784 SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff); 1785 SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff); 1786 SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff); 1787 SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff); 1788 SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff); 1789 SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff); 1790 1791 SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0); 1792 SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0); 1793 SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0); 1794 SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0); 1795 1796 /* antenna gain */ 1797 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0); 1798 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1); 1799 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2); 1800 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3); 1801 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); 1802 1803 /* FEM */ 1804 SIBA_SHIFTOUT(fem.ghz2.tssipos, SIBA_SPROM8_FEM2G, 1805 SSB_SROM8_FEM_TSSIPOS); 1806 SIBA_SHIFTOUT(fem.ghz2.extpa_gain, SIBA_SPROM8_FEM2G, 1807 SSB_SROM8_FEM_EXTPA_GAIN); 1808 SIBA_SHIFTOUT(fem.ghz2.pdet_range, SIBA_SPROM8_FEM2G, 1809 SSB_SROM8_FEM_PDET_RANGE); 1810 SIBA_SHIFTOUT(fem.ghz2.tr_iso, SIBA_SPROM8_FEM2G, 1811 SSB_SROM8_FEM_TR_ISO); 1812 SIBA_SHIFTOUT(fem.ghz2.antswlut, SIBA_SPROM8_FEM2G, 1813 SSB_SROM8_FEM_ANTSWLUT); 1814 1815 SIBA_SHIFTOUT(fem.ghz5.tssipos, SIBA_SPROM8_FEM5G, 1816 SSB_SROM8_FEM_TSSIPOS); 1817 SIBA_SHIFTOUT(fem.ghz5.extpa_gain, SIBA_SPROM8_FEM5G, 1818 SSB_SROM8_FEM_EXTPA_GAIN); 1819 SIBA_SHIFTOUT(fem.ghz5.pdet_range, SIBA_SPROM8_FEM5G, 1820 SSB_SROM8_FEM_PDET_RANGE); 1821 SIBA_SHIFTOUT(fem.ghz5.tr_iso, SIBA_SPROM8_FEM5G, 1822 SSB_SROM8_FEM_TR_ISO); 1823 SIBA_SHIFTOUT(fem.ghz5.antswlut, SIBA_SPROM8_FEM5G, 1824 SSB_SROM8_FEM_ANTSWLUT); 1825 1826 /* Extract cores power info info */ 1827 for (i = 0; i < nitems(pwr_info_offset); i++) { 1828 uint16_t o = pwr_info_offset[i]; 1829 SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, 1830 SIBA_SPROM8_2G_ITSSI); 1831 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, 1832 SIBA_SPROM8_2G_MAXP); 1833 1834 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SROM8_2G_PA_0, ~0); 1835 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SROM8_2G_PA_1, ~0); 1836 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SROM8_2G_PA_2, ~0); 1837 1838 SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, 1839 SIBA_SPROM8_5G_ITSSI); 1840 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, 1841 SIBA_SPROM8_5G_MAXP); 1842 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM8_5GHL_MAXP, 1843 SIBA_SPROM8_5GH_MAXP); 1844 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM8_5GHL_MAXP, 1845 SIBA_SPROM8_5GL_MAXP); 1846 1847 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SROM8_5GL_PA_0, ~0); 1848 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SROM8_5GL_PA_1, ~0); 1849 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SROM8_5GL_PA_2, ~0); 1850 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SROM8_5G_PA_0, ~0); 1851 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SROM8_5G_PA_1, ~0); 1852 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SROM8_5G_PA_2, ~0); 1853 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SROM8_5GH_PA_0, ~0); 1854 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SROM8_5GH_PA_1, ~0); 1855 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SROM8_5GH_PA_2, ~0); 1856 } 1857 1858 SIBA_SHIFTOUT(cddpo, SIBA_SPROM8_CDDPO, ~0); 1859 SIBA_SHIFTOUT(stbcpo, SIBA_SPROM8_STBCPO, ~0); 1860 1861 siba_sprom_r458(out, in); 1862 } 1863 1864 static int8_t 1865 siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in, 1866 uint16_t mask, uint16_t shift) 1867 { 1868 uint16_t v; 1869 uint8_t gain; 1870 1871 v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)]; 1872 gain = (v & mask) >> shift; 1873 gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 : 1874 ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2); 1875 1876 return ((int8_t)gain); 1877 } 1878 1879 #undef SIBA_LOWEST_SET_BIT 1880 #undef SIBA_OFFSET 1881 #undef SIBA_SHIFTOUT_SUB 1882 #undef SIBA_SHIFTOUT 1883 1884 int 1885 siba_powerdown(device_t dev) 1886 { 1887 struct siba_dev_softc *sd = device_get_ivars(dev); 1888 struct siba_softc *siba = sd->sd_bus; 1889 1890 return (siba_powerdown_sub(siba)); 1891 } 1892 1893 static int 1894 siba_powerdown_sub(struct siba_softc *siba) 1895 { 1896 struct siba_cc *scc; 1897 1898 if (siba->siba_type == SIBA_TYPE_SSB) 1899 return (0); 1900 1901 scc = &siba->siba_cc; 1902 if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5) 1903 return (0); 1904 siba_cc_clock(scc, SIBA_CLOCK_SLOW); 1905 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); 1906 return (0); 1907 } 1908 1909 static void 1910 siba_pcicore_init(struct siba_pci *spc) 1911 { 1912 struct siba_dev_softc *sd = spc->spc_dev; 1913 1914 if (sd == NULL) 1915 return; 1916 1917 if (!siba_dev_isup_sub(sd)) 1918 siba_dev_up_sub(sd, 0); 1919 1920 KASSERT(spc->spc_hostmode == 0, 1921 ("%s:%d: hostmode", __func__, __LINE__)); 1922 /* disable PCI interrupt */ 1923 siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0); 1924 } 1925 1926 int 1927 siba_dev_isup(device_t dev) 1928 { 1929 struct siba_dev_softc *sd = device_get_ivars(dev); 1930 1931 return (siba_dev_isup_sub(sd)); 1932 } 1933 1934 static int 1935 siba_dev_isup_sub(struct siba_dev_softc *sd) 1936 { 1937 uint32_t reject, val; 1938 1939 reject = siba_tmslow_reject_bitmask(sd); 1940 val = siba_read_4_sub(sd, SIBA_TGSLOW); 1941 val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject; 1942 1943 return (val == SIBA_TGSLOW_CLOCK); 1944 } 1945 1946 void 1947 siba_dev_up(device_t dev, uint32_t flags) 1948 { 1949 struct siba_dev_softc *sd = device_get_ivars(dev); 1950 1951 siba_dev_up_sub(sd, flags); 1952 } 1953 1954 static void 1955 siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags) 1956 { 1957 uint32_t val; 1958 1959 siba_dev_down_sub(sd, flags); 1960 siba_write_4_sub(sd, SIBA_TGSLOW, 1961 SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); 1962 siba_read_4_sub(sd, SIBA_TGSLOW); 1963 DELAY(1); 1964 1965 if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR) 1966 siba_write_4_sub(sd, SIBA_TGSHIGH, 0); 1967 1968 val = siba_read_4_sub(sd, SIBA_IAS); 1969 if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) { 1970 val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT); 1971 siba_write_4_sub(sd, SIBA_IAS, val); 1972 } 1973 1974 siba_write_4_sub(sd, SIBA_TGSLOW, 1975 SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); 1976 siba_read_4_sub(sd, SIBA_TGSLOW); 1977 DELAY(1); 1978 1979 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags); 1980 siba_read_4_sub(sd, SIBA_TGSLOW); 1981 DELAY(1); 1982 } 1983 1984 static uint32_t 1985 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd) 1986 { 1987 uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV; 1988 1989 switch (rev) { 1990 case SIBA_IDLOW_SSBREV_22: 1991 return (SIBA_TGSLOW_REJECT_22); 1992 case SIBA_IDLOW_SSBREV_23: 1993 return (SIBA_TGSLOW_REJECT_23); 1994 case SIBA_IDLOW_SSBREV_24: 1995 case SIBA_IDLOW_SSBREV_25: 1996 case SIBA_IDLOW_SSBREV_26: 1997 case SIBA_IDLOW_SSBREV_27: 1998 return (SIBA_TGSLOW_REJECT_23); 1999 default: 2000 KASSERT(0 == 1, 2001 ("%s:%d: unknown backplane rev %#x\n", 2002 __func__, __LINE__, rev)); 2003 } 2004 return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23); 2005 } 2006 2007 void 2008 siba_dev_down(device_t dev, uint32_t flags) 2009 { 2010 struct siba_dev_softc *sd = device_get_ivars(dev); 2011 2012 siba_dev_down_sub(sd, flags); 2013 } 2014 2015 static void 2016 siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags) 2017 { 2018 struct siba_softc *siba = sd->sd_bus; 2019 uint32_t reject, val; 2020 int i; 2021 2022 if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET) 2023 return; 2024 2025 reject = siba_tmslow_reject_bitmask(sd); 2026 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK); 2027 2028 for (i = 0; i < 1000; i++) { 2029 val = siba_read_4_sub(sd, SIBA_TGSLOW); 2030 if (val & reject) 2031 break; 2032 DELAY(10); 2033 } 2034 if ((val & reject) == 0) { 2035 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", 2036 reject, SIBA_TGSLOW); 2037 } 2038 for (i = 0; i < 1000; i++) { 2039 val = siba_read_4_sub(sd, SIBA_TGSHIGH); 2040 if (!(val & SIBA_TGSHIGH_BUSY)) 2041 break; 2042 DELAY(10); 2043 } 2044 if ((val & SIBA_TGSHIGH_BUSY) != 0) { 2045 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", 2046 SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH); 2047 } 2048 2049 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK | 2050 reject | SIBA_TGSLOW_RESET | flags); 2051 siba_read_4_sub(sd, SIBA_TGSLOW); 2052 DELAY(1); 2053 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags); 2054 siba_read_4_sub(sd, SIBA_TGSLOW); 2055 DELAY(1); 2056 } 2057 2058 static void 2059 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd) 2060 { 2061 struct siba_dev_softc *psd = spc->spc_dev; 2062 struct siba_softc *siba = psd->sd_bus; 2063 uint32_t tmp; 2064 2065 if (psd->sd_id.sd_device == SIBA_DEVID_PCI) { 2066 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, 2067 siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) | 2068 SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST); 2069 2070 if (psd->sd_id.sd_rev < 5) { 2071 tmp = siba_read_4_sub(psd, SIBA_IMCFGLO); 2072 tmp &= ~SIBA_IMCFGLO_SERTO; 2073 tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO; 2074 tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */; 2075 siba_write_4_sub(psd, SIBA_IMCFGLO, tmp); 2076 2077 /* broadcast value */ 2078 sd = (siba->siba_cc.scc_dev != NULL) ? 2079 siba->siba_cc.scc_dev : siba->siba_pci.spc_dev; 2080 if (sd != NULL) { 2081 siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR, 2082 0xfd8); 2083 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR); 2084 siba_write_4_sub(sd, 2085 SIBA_PCICORE_BCAST_DATA, 0); 2086 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA); 2087 } 2088 } else if (psd->sd_id.sd_rev >= 11) { 2089 tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2); 2090 tmp |= SIBA_PCICORE_SBTOPCI_MRM; 2091 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp); 2092 } 2093 } else { 2094 KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE")); 2095 if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1)) 2096 siba_pcie_write(spc, 0x4, 2097 siba_pcie_read(spc, 0x4) | 0x8); 2098 if (psd->sd_id.sd_rev == 0) { 2099 siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */ 2100 siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */ 2101 siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */ 2102 } else if (psd->sd_id.sd_rev == 1) 2103 siba_pcie_write(spc, 0x100, 2104 siba_pcie_read(spc, 0x100) | 0x40); 2105 } 2106 spc->spc_inited = 1; 2107 } 2108 2109 void 2110 siba_pcicore_intr(device_t dev) 2111 { 2112 struct siba_dev_softc *sd = device_get_ivars(dev); 2113 struct siba_softc *siba = sd->sd_bus; 2114 struct siba_pci *spc = &siba->siba_pci; 2115 struct siba_dev_softc *psd = spc->spc_dev; 2116 uint32_t tmp; 2117 2118 if (siba->siba_type != SIBA_TYPE_PCI || !psd) 2119 return; 2120 2121 KASSERT(siba == psd->sd_bus, ("different pointers")); 2122 2123 /* enable interrupts */ 2124 if (siba->siba_dev != NULL && 2125 (psd->sd_id.sd_rev >= 6 || 2126 psd->sd_id.sd_device == SIBA_DEVID_PCIE)) { 2127 tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4); 2128 tmp |= (1 << sd->sd_coreidx) << 8; 2129 pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4); 2130 } else { 2131 tmp = siba_read_4_sub(sd, SIBA_TPS); 2132 tmp &= SIBA_TPS_BPFLAG; 2133 siba_write_4_sub(psd, SIBA_INTR_MASK, 2134 siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp)); 2135 } 2136 2137 /* setup PCIcore */ 2138 if (spc->spc_inited == 0) 2139 siba_pcicore_setup(spc, sd); 2140 } 2141 2142 static uint32_t 2143 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset) 2144 { 2145 2146 return (siba_read_4_sub(spc->spc_dev, offset)); 2147 } 2148 2149 static void 2150 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value) 2151 { 2152 2153 siba_write_4_sub(spc->spc_dev, offset, value); 2154 } 2155 2156 static uint32_t 2157 siba_pcie_read(struct siba_pci *spc, uint32_t address) 2158 { 2159 2160 siba_pcicore_write_4(spc, 0x130, address); 2161 return (siba_pcicore_read_4(spc, 0x134)); 2162 } 2163 2164 static void 2165 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data) 2166 { 2167 2168 siba_pcicore_write_4(spc, 0x130, address); 2169 siba_pcicore_write_4(spc, 0x134, data); 2170 } 2171 2172 static void 2173 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address, 2174 uint16_t data) 2175 { 2176 int i; 2177 2178 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2); 2179 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA, 2180 (1 << 30) | (1 << 28) | 2181 ((uint32_t)device << 22) | ((uint32_t)address << 18) | 2182 (1 << 17) | data); 2183 DELAY(10); 2184 for (i = 0; i < 10; i++) { 2185 if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100) 2186 break; 2187 DELAY(1000); 2188 } 2189 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0); 2190 } 2191 2192 uint32_t 2193 siba_dma_translation(device_t dev) 2194 { 2195 #ifdef INVARIANTS 2196 struct siba_dev_softc *sd = device_get_ivars(dev); 2197 struct siba_softc *siba = sd->sd_bus; 2198 2199 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 2200 ("unsupported bustype %d\n", siba->siba_type)); 2201 #endif 2202 return (SIBA_PCI_DMA); 2203 } 2204 2205 void 2206 siba_barrier(device_t dev, int flags) 2207 { 2208 struct siba_dev_softc *sd = device_get_ivars(dev); 2209 struct siba_softc *siba = sd->sd_bus; 2210 2211 SIBA_BARRIER(siba, flags); 2212 } 2213 2214 static void 2215 siba_cc_suspend(struct siba_cc *scc) 2216 { 2217 2218 siba_cc_clock(scc, SIBA_CLOCK_SLOW); 2219 } 2220 2221 static void 2222 siba_cc_resume(struct siba_cc *scc) 2223 { 2224 2225 siba_cc_power_init(scc); 2226 siba_cc_clock(scc, SIBA_CLOCK_FAST); 2227 } 2228 2229 int 2230 siba_core_suspend(struct siba_softc *siba) 2231 { 2232 2233 siba_cc_suspend(&siba->siba_cc); 2234 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); 2235 return (0); 2236 } 2237 2238 int 2239 siba_core_resume(struct siba_softc *siba) 2240 { 2241 2242 siba->siba_pci.spc_inited = 0; 2243 siba->siba_curdev = NULL; 2244 2245 siba_powerup_sub(siba, 0); 2246 /* XXX setup H/W for PCMCIA??? */ 2247 siba_cc_resume(&siba->siba_cc); 2248 siba_powerdown_sub(siba); 2249 2250 return (0); 2251 } 2252 2253 static void 2254 siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask, 2255 uint32_t set) 2256 { 2257 2258 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); 2259 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset); 2260 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); 2261 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA, 2262 (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set); 2263 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA); 2264 } 2265 2266 void 2267 siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt) 2268 { 2269 struct siba_dev_softc *sd = device_get_ivars(dev); 2270 struct siba_softc *siba = sd->sd_bus; 2271 struct siba_cc *scc = &siba->siba_cc; 2272 uint32_t *p = NULL, info[5][3] = { 2273 { 2, 25, 0xf }, 2274 { 3, 1, 0xf }, 2275 { 3, 9, 0xf }, 2276 { 3, 17, 0x3f }, 2277 { 0, 21, 0x3f } 2278 }; 2279 2280 if (siba->siba_chipid == 0x4312) { 2281 if (id != SIBA_LDO_PAREF) 2282 return; 2283 p = info[4]; 2284 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), 2285 (volt & p[2]) << p[1]); 2286 return; 2287 } 2288 if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) { 2289 switch (id) { 2290 case SIBA_LDO_PAREF: 2291 p = info[3]; 2292 break; 2293 case SIBA_LDO_VOLT1: 2294 p = info[0]; 2295 break; 2296 case SIBA_LDO_VOLT2: 2297 p = info[1]; 2298 break; 2299 case SIBA_LDO_VOLT3: 2300 p = info[2]; 2301 break; 2302 default: 2303 KASSERT(0 == 1, 2304 ("%s: unsupported voltage ID %#x", __func__, id)); 2305 return; 2306 } 2307 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), 2308 (volt & p[2]) << p[1]); 2309 } 2310 } 2311 2312 void 2313 siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on) 2314 { 2315 struct siba_dev_softc *sd = device_get_ivars(dev); 2316 struct siba_softc *siba = sd->sd_bus; 2317 struct siba_cc *scc = &siba->siba_cc; 2318 int ldo; 2319 2320 ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF : 2321 ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF : 2322 ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1))); 2323 if (ldo == -1) 2324 return; 2325 2326 if (on) 2327 SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo); 2328 else 2329 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo)); 2330 SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES); 2331 } 2332 2333 int 2334 siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result) 2335 { 2336 struct siba_dev_softc *sd = device_get_ivars(child); 2337 struct siba_softc *siba = sd->sd_bus; 2338 2339 switch (which) { 2340 case SIBA_SPROMVAR_REV: 2341 *result = siba->siba_sprom.rev; 2342 break; 2343 case SIBA_SPROMVAR_MAC_80211BG: 2344 *((uint8_t **) result) = siba->siba_sprom.mac_80211bg; 2345 break; 2346 case SIBA_SPROMVAR_MAC_ETH: 2347 *((uint8_t **) result) = siba->siba_sprom.mac_eth; 2348 break; 2349 case SIBA_SPROMVAR_MAC_80211A: 2350 *((uint8_t **) result) = siba->siba_sprom.mac_80211a; 2351 break; 2352 case SIBA_SPROMVAR_MII_ETH0: 2353 *result = siba->siba_sprom.mii_eth0; 2354 break; 2355 case SIBA_SPROMVAR_MII_ETH1: 2356 *result = siba->siba_sprom.mii_eth1; 2357 break; 2358 case SIBA_SPROMVAR_MDIO_ETH0: 2359 *result = siba->siba_sprom.mdio_eth0; 2360 break; 2361 case SIBA_SPROMVAR_MDIO_ETH1: 2362 *result = siba->siba_sprom.mdio_eth1; 2363 break; 2364 case SIBA_SPROMVAR_BREV: 2365 *result = siba->siba_sprom.brev; 2366 break; 2367 case SIBA_SPROMVAR_CCODE: 2368 *result = siba->siba_sprom.ccode; 2369 break; 2370 case SIBA_SPROMVAR_ANT_A: 2371 *result = siba->siba_sprom.ant_a; 2372 break; 2373 case SIBA_SPROMVAR_ANT_BG: 2374 *result = siba->siba_sprom.ant_bg; 2375 break; 2376 case SIBA_SPROMVAR_PA0B0: 2377 *result = siba->siba_sprom.pa0b0; 2378 break; 2379 case SIBA_SPROMVAR_PA0B1: 2380 *result = siba->siba_sprom.pa0b1; 2381 break; 2382 case SIBA_SPROMVAR_PA0B2: 2383 *result = siba->siba_sprom.pa0b2; 2384 break; 2385 case SIBA_SPROMVAR_PA1B0: 2386 *result = siba->siba_sprom.pa1b0; 2387 break; 2388 case SIBA_SPROMVAR_PA1B1: 2389 *result = siba->siba_sprom.pa1b1; 2390 break; 2391 case SIBA_SPROMVAR_PA1B2: 2392 *result = siba->siba_sprom.pa1b2; 2393 break; 2394 case SIBA_SPROMVAR_PA1LOB0: 2395 *result = siba->siba_sprom.pa1lob0; 2396 break; 2397 case SIBA_SPROMVAR_PA1LOB1: 2398 *result = siba->siba_sprom.pa1lob1; 2399 break; 2400 case SIBA_SPROMVAR_PA1LOB2: 2401 *result = siba->siba_sprom.pa1lob2; 2402 break; 2403 case SIBA_SPROMVAR_PA1HIB0: 2404 *result = siba->siba_sprom.pa1hib0; 2405 break; 2406 case SIBA_SPROMVAR_PA1HIB1: 2407 *result = siba->siba_sprom.pa1hib1; 2408 break; 2409 case SIBA_SPROMVAR_PA1HIB2: 2410 *result = siba->siba_sprom.pa1hib2; 2411 break; 2412 case SIBA_SPROMVAR_GPIO0: 2413 *result = siba->siba_sprom.gpio0; 2414 break; 2415 case SIBA_SPROMVAR_GPIO1: 2416 *result = siba->siba_sprom.gpio1; 2417 break; 2418 case SIBA_SPROMVAR_GPIO2: 2419 *result = siba->siba_sprom.gpio2; 2420 break; 2421 case SIBA_SPROMVAR_GPIO3: 2422 *result = siba->siba_sprom.gpio3; 2423 break; 2424 case SIBA_SPROMVAR_MAXPWR_AL: 2425 *result = siba->siba_sprom.maxpwr_al; 2426 break; 2427 case SIBA_SPROMVAR_MAXPWR_A: 2428 *result = siba->siba_sprom.maxpwr_a; 2429 break; 2430 case SIBA_SPROMVAR_MAXPWR_AH: 2431 *result = siba->siba_sprom.maxpwr_ah; 2432 break; 2433 case SIBA_SPROMVAR_MAXPWR_BG: 2434 *result = siba->siba_sprom.maxpwr_bg; 2435 break; 2436 case SIBA_SPROMVAR_RXPO2G: 2437 *result = siba->siba_sprom.rxpo2g; 2438 break; 2439 case SIBA_SPROMVAR_RXPO5G: 2440 *result = siba->siba_sprom.rxpo5g; 2441 break; 2442 case SIBA_SPROMVAR_TSSI_A: 2443 *result = siba->siba_sprom.tssi_a; 2444 break; 2445 case SIBA_SPROMVAR_TSSI_BG: 2446 *result = siba->siba_sprom.tssi_bg; 2447 break; 2448 case SIBA_SPROMVAR_TRI2G: 2449 *result = siba->siba_sprom.tri2g; 2450 break; 2451 case SIBA_SPROMVAR_TRI5GL: 2452 *result = siba->siba_sprom.tri5gl; 2453 break; 2454 case SIBA_SPROMVAR_TRI5G: 2455 *result = siba->siba_sprom.tri5g; 2456 break; 2457 case SIBA_SPROMVAR_TRI5GH: 2458 *result = siba->siba_sprom.tri5gh; 2459 break; 2460 case SIBA_SPROMVAR_RSSISAV2G: 2461 *result = siba->siba_sprom.rssisav2g; 2462 break; 2463 case SIBA_SPROMVAR_RSSISMC2G: 2464 *result = siba->siba_sprom.rssismc2g; 2465 break; 2466 case SIBA_SPROMVAR_RSSISMF2G: 2467 *result = siba->siba_sprom.rssismf2g; 2468 break; 2469 case SIBA_SPROMVAR_BXA2G: 2470 *result = siba->siba_sprom.bxa2g; 2471 break; 2472 case SIBA_SPROMVAR_RSSISAV5G: 2473 *result = siba->siba_sprom.rssisav5g; 2474 break; 2475 case SIBA_SPROMVAR_RSSISMC5G: 2476 *result = siba->siba_sprom.rssismc5g; 2477 break; 2478 case SIBA_SPROMVAR_RSSISMF5G: 2479 *result = siba->siba_sprom.rssismf5g; 2480 break; 2481 case SIBA_SPROMVAR_BXA5G: 2482 *result = siba->siba_sprom.bxa5g; 2483 break; 2484 case SIBA_SPROMVAR_CCK2GPO: 2485 *result = siba->siba_sprom.cck2gpo; 2486 break; 2487 case SIBA_SPROMVAR_OFDM2GPO: 2488 *result = siba->siba_sprom.ofdm2gpo; 2489 break; 2490 case SIBA_SPROMVAR_OFDM5GLPO: 2491 *result = siba->siba_sprom.ofdm5glpo; 2492 break; 2493 case SIBA_SPROMVAR_OFDM5GPO: 2494 *result = siba->siba_sprom.ofdm5gpo; 2495 break; 2496 case SIBA_SPROMVAR_OFDM5GHPO: 2497 *result = siba->siba_sprom.ofdm5ghpo; 2498 break; 2499 case SIBA_SPROMVAR_BF_LO: 2500 *result = siba->siba_sprom.bf_lo; 2501 break; 2502 case SIBA_SPROMVAR_BF_HI: 2503 *result = siba->siba_sprom.bf_hi; 2504 break; 2505 case SIBA_SPROMVAR_BF2_LO: 2506 *result = siba->siba_sprom.bf2_lo; 2507 break; 2508 case SIBA_SPROMVAR_BF2_HI: 2509 *result = siba->siba_sprom.bf2_hi; 2510 break; 2511 case SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS: 2512 *result = siba->siba_sprom.fem.ghz2.tssipos; 2513 break; 2514 case SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN: 2515 *result = siba->siba_sprom.fem.ghz2.extpa_gain; 2516 break; 2517 case SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE: 2518 *result = siba->siba_sprom.fem.ghz2.pdet_range; 2519 break; 2520 case SIBA_SPROMVAR_FEM_2GHZ_TR_ISO: 2521 *result = siba->siba_sprom.fem.ghz2.tr_iso; 2522 break; 2523 case SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT: 2524 *result = siba->siba_sprom.fem.ghz2.antswlut; 2525 break; 2526 case SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS: 2527 *result = siba->siba_sprom.fem.ghz5.tssipos; 2528 break; 2529 case SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN: 2530 *result = siba->siba_sprom.fem.ghz5.extpa_gain; 2531 break; 2532 case SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE: 2533 *result = siba->siba_sprom.fem.ghz5.pdet_range; 2534 break; 2535 case SIBA_SPROMVAR_FEM_5GHZ_TR_ISO: 2536 *result = siba->siba_sprom.fem.ghz5.tr_iso; 2537 break; 2538 case SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT: 2539 *result = siba->siba_sprom.fem.ghz5.antswlut; 2540 break; 2541 case SIBA_SPROMVAR_TXPID_2G_0: 2542 *result = siba->siba_sprom.txpid2g[0]; 2543 break; 2544 case SIBA_SPROMVAR_TXPID_2G_1: 2545 *result = siba->siba_sprom.txpid2g[1]; 2546 break; 2547 case SIBA_SPROMVAR_TXPID_2G_2: 2548 *result = siba->siba_sprom.txpid2g[2]; 2549 break; 2550 case SIBA_SPROMVAR_TXPID_2G_3: 2551 *result = siba->siba_sprom.txpid2g[3]; 2552 break; 2553 case SIBA_SPROMVAR_TXPID_5GL_0: 2554 *result = siba->siba_sprom.txpid5gl[0]; 2555 break; 2556 case SIBA_SPROMVAR_TXPID_5GL_1: 2557 *result = siba->siba_sprom.txpid5gl[1]; 2558 break; 2559 case SIBA_SPROMVAR_TXPID_5GL_2: 2560 *result = siba->siba_sprom.txpid5gl[2]; 2561 break; 2562 case SIBA_SPROMVAR_TXPID_5GL_3: 2563 *result = siba->siba_sprom.txpid5gl[3]; 2564 break; 2565 case SIBA_SPROMVAR_TXPID_5G_0: 2566 *result = siba->siba_sprom.txpid5g[0]; 2567 break; 2568 case SIBA_SPROMVAR_TXPID_5G_1: 2569 *result = siba->siba_sprom.txpid5g[1]; 2570 break; 2571 case SIBA_SPROMVAR_TXPID_5G_2: 2572 *result = siba->siba_sprom.txpid5g[2]; 2573 break; 2574 case SIBA_SPROMVAR_TXPID_5G_3: 2575 *result = siba->siba_sprom.txpid5g[3]; 2576 break; 2577 case SIBA_SPROMVAR_TXPID_5GH_0: 2578 *result = siba->siba_sprom.txpid5gh[0]; 2579 break; 2580 case SIBA_SPROMVAR_TXPID_5GH_1: 2581 *result = siba->siba_sprom.txpid5gh[1]; 2582 break; 2583 case SIBA_SPROMVAR_TXPID_5GH_2: 2584 *result = siba->siba_sprom.txpid5gh[2]; 2585 break; 2586 case SIBA_SPROMVAR_TXPID_5GH_3: 2587 *result = siba->siba_sprom.txpid5gh[3]; 2588 break; 2589 case SIBA_SPROMVAR_STBCPO: 2590 *result = siba->siba_sprom.stbcpo; 2591 break; 2592 case SIBA_SPROMVAR_CDDPO: 2593 *result = siba->siba_sprom.cddpo; 2594 break; 2595 default: 2596 return (ENOENT); 2597 } 2598 return (0); 2599 } 2600 2601 int 2602 siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value) 2603 { 2604 struct siba_dev_softc *sd = device_get_ivars(child); 2605 struct siba_softc *siba = sd->sd_bus; 2606 2607 switch (which) { 2608 case SIBA_SPROMVAR_REV: 2609 siba->siba_sprom.rev = value; 2610 break; 2611 case SIBA_SPROMVAR_MII_ETH0: 2612 siba->siba_sprom.mii_eth0 = value; 2613 break; 2614 case SIBA_SPROMVAR_MII_ETH1: 2615 siba->siba_sprom.mii_eth1 = value; 2616 break; 2617 case SIBA_SPROMVAR_MDIO_ETH0: 2618 siba->siba_sprom.mdio_eth0 = value; 2619 break; 2620 case SIBA_SPROMVAR_MDIO_ETH1: 2621 siba->siba_sprom.mdio_eth1 = value; 2622 break; 2623 case SIBA_SPROMVAR_BREV: 2624 siba->siba_sprom.brev = value; 2625 break; 2626 case SIBA_SPROMVAR_CCODE: 2627 siba->siba_sprom.ccode = value; 2628 break; 2629 case SIBA_SPROMVAR_ANT_A: 2630 siba->siba_sprom.ant_a = value; 2631 break; 2632 case SIBA_SPROMVAR_ANT_BG: 2633 siba->siba_sprom.ant_bg = value; 2634 break; 2635 case SIBA_SPROMVAR_PA0B0: 2636 siba->siba_sprom.pa0b0 = value; 2637 break; 2638 case SIBA_SPROMVAR_PA0B1: 2639 siba->siba_sprom.pa0b1 = value; 2640 break; 2641 case SIBA_SPROMVAR_PA0B2: 2642 siba->siba_sprom.pa0b2 = value; 2643 break; 2644 case SIBA_SPROMVAR_PA1B0: 2645 siba->siba_sprom.pa1b0 = value; 2646 break; 2647 case SIBA_SPROMVAR_PA1B1: 2648 siba->siba_sprom.pa1b1 = value; 2649 break; 2650 case SIBA_SPROMVAR_PA1B2: 2651 siba->siba_sprom.pa1b2 = value; 2652 break; 2653 case SIBA_SPROMVAR_PA1LOB0: 2654 siba->siba_sprom.pa1lob0 = value; 2655 break; 2656 case SIBA_SPROMVAR_PA1LOB1: 2657 siba->siba_sprom.pa1lob1 = value; 2658 break; 2659 case SIBA_SPROMVAR_PA1LOB2: 2660 siba->siba_sprom.pa1lob2 = value; 2661 break; 2662 case SIBA_SPROMVAR_PA1HIB0: 2663 siba->siba_sprom.pa1hib0 = value; 2664 break; 2665 case SIBA_SPROMVAR_PA1HIB1: 2666 siba->siba_sprom.pa1hib1 = value; 2667 break; 2668 case SIBA_SPROMVAR_PA1HIB2: 2669 siba->siba_sprom.pa1hib2 = value; 2670 break; 2671 case SIBA_SPROMVAR_GPIO0: 2672 siba->siba_sprom.gpio0 = value; 2673 break; 2674 case SIBA_SPROMVAR_GPIO1: 2675 siba->siba_sprom.gpio1 = value; 2676 break; 2677 case SIBA_SPROMVAR_GPIO2: 2678 siba->siba_sprom.gpio2 = value; 2679 break; 2680 case SIBA_SPROMVAR_GPIO3: 2681 siba->siba_sprom.gpio3 = value; 2682 break; 2683 case SIBA_SPROMVAR_MAXPWR_AL: 2684 siba->siba_sprom.maxpwr_al = value; 2685 break; 2686 case SIBA_SPROMVAR_MAXPWR_A: 2687 siba->siba_sprom.maxpwr_a = value; 2688 break; 2689 case SIBA_SPROMVAR_MAXPWR_AH: 2690 siba->siba_sprom.maxpwr_ah = value; 2691 break; 2692 case SIBA_SPROMVAR_MAXPWR_BG: 2693 siba->siba_sprom.maxpwr_bg = value; 2694 break; 2695 case SIBA_SPROMVAR_RXPO2G: 2696 siba->siba_sprom.rxpo2g = value; 2697 break; 2698 case SIBA_SPROMVAR_RXPO5G: 2699 siba->siba_sprom.rxpo5g = value; 2700 break; 2701 case SIBA_SPROMVAR_TSSI_A: 2702 siba->siba_sprom.tssi_a = value; 2703 break; 2704 case SIBA_SPROMVAR_TSSI_BG: 2705 siba->siba_sprom.tssi_bg = value; 2706 break; 2707 case SIBA_SPROMVAR_TRI2G: 2708 siba->siba_sprom.tri2g = value; 2709 break; 2710 case SIBA_SPROMVAR_TRI5GL: 2711 siba->siba_sprom.tri5gl = value; 2712 break; 2713 case SIBA_SPROMVAR_TRI5G: 2714 siba->siba_sprom.tri5g = value; 2715 break; 2716 case SIBA_SPROMVAR_TRI5GH: 2717 siba->siba_sprom.tri5gh = value; 2718 break; 2719 case SIBA_SPROMVAR_RSSISAV2G: 2720 siba->siba_sprom.rssisav2g = value; 2721 break; 2722 case SIBA_SPROMVAR_RSSISMC2G: 2723 siba->siba_sprom.rssismc2g = value; 2724 break; 2725 case SIBA_SPROMVAR_RSSISMF2G: 2726 siba->siba_sprom.rssismf2g = value; 2727 break; 2728 case SIBA_SPROMVAR_BXA2G: 2729 siba->siba_sprom.bxa2g = value; 2730 break; 2731 case SIBA_SPROMVAR_RSSISAV5G: 2732 siba->siba_sprom.rssisav5g = value; 2733 break; 2734 case SIBA_SPROMVAR_RSSISMC5G: 2735 siba->siba_sprom.rssismc5g = value; 2736 break; 2737 case SIBA_SPROMVAR_RSSISMF5G: 2738 siba->siba_sprom.rssismf5g = value; 2739 break; 2740 case SIBA_SPROMVAR_BXA5G: 2741 siba->siba_sprom.bxa5g = value; 2742 break; 2743 case SIBA_SPROMVAR_CCK2GPO: 2744 siba->siba_sprom.cck2gpo = value; 2745 break; 2746 case SIBA_SPROMVAR_OFDM2GPO: 2747 siba->siba_sprom.ofdm2gpo = value; 2748 break; 2749 case SIBA_SPROMVAR_OFDM5GLPO: 2750 siba->siba_sprom.ofdm5glpo = value; 2751 break; 2752 case SIBA_SPROMVAR_OFDM5GPO: 2753 siba->siba_sprom.ofdm5gpo = value; 2754 break; 2755 case SIBA_SPROMVAR_OFDM5GHPO: 2756 siba->siba_sprom.ofdm5ghpo = value; 2757 break; 2758 case SIBA_SPROMVAR_BF_LO: 2759 siba->siba_sprom.bf_lo = value; 2760 break; 2761 case SIBA_SPROMVAR_BF_HI: 2762 siba->siba_sprom.bf_hi = value; 2763 break; 2764 case SIBA_SPROMVAR_BF2_LO: 2765 siba->siba_sprom.bf2_lo = value; 2766 break; 2767 case SIBA_SPROMVAR_BF2_HI: 2768 siba->siba_sprom.bf2_hi = value; 2769 break; 2770 default: 2771 return (ENOENT); 2772 } 2773 return (0); 2774 } 2775 2776 #define SIBA_GPIOCTL 0x06c 2777 2778 uint32_t 2779 siba_gpio_get(device_t dev) 2780 { 2781 struct siba_dev_softc *sd = device_get_ivars(dev); 2782 struct siba_softc *siba = sd->sd_bus; 2783 struct siba_dev_softc *gpiodev, *pcidev = NULL; 2784 2785 pcidev = siba->siba_pci.spc_dev; 2786 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; 2787 if (!gpiodev) 2788 return (-1); 2789 return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL)); 2790 } 2791 2792 void 2793 siba_gpio_set(device_t dev, uint32_t value) 2794 { 2795 struct siba_dev_softc *sd = device_get_ivars(dev); 2796 struct siba_softc *siba = sd->sd_bus; 2797 struct siba_dev_softc *gpiodev, *pcidev = NULL; 2798 2799 pcidev = siba->siba_pci.spc_dev; 2800 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; 2801 if (!gpiodev) 2802 return; 2803 siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value); 2804 } 2805 2806 void 2807 siba_fix_imcfglobug(device_t dev) 2808 { 2809 struct siba_dev_softc *sd = device_get_ivars(dev); 2810 struct siba_softc *siba = sd->sd_bus; 2811 uint32_t tmp; 2812 2813 if (siba->siba_pci.spc_dev == NULL) 2814 return; 2815 if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI || 2816 siba->siba_pci.spc_dev->sd_id.sd_rev > 5) 2817 return; 2818 2819 tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) & 2820 ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO); 2821 switch (siba->siba_type) { 2822 case SIBA_TYPE_PCI: 2823 case SIBA_TYPE_PCMCIA: 2824 tmp |= 0x32; 2825 break; 2826 case SIBA_TYPE_SSB: 2827 tmp |= 0x53; 2828 break; 2829 } 2830 siba_write_4_sub(sd, SIBA_IMCFGLO, tmp); 2831 } 2832 2833 int 2834 siba_sprom_get_core_power_info(device_t dev, int core, 2835 struct siba_sprom_core_pwr_info *c) 2836 { 2837 struct siba_dev_softc *sd = device_get_ivars(dev); 2838 struct siba_softc *siba = sd->sd_bus; 2839 2840 if (core < 0 || core > 3) { 2841 return (EINVAL); 2842 } 2843 memcpy(c, &siba->siba_sprom.core_pwr_info[core], sizeof(*c)); 2844 return (0); 2845 } 2846 2847 int 2848 siba_sprom_get_mcs2gpo(device_t dev, uint16_t *c) 2849 { 2850 struct siba_dev_softc *sd = device_get_ivars(dev); 2851 struct siba_softc *siba = sd->sd_bus; 2852 2853 memcpy(c, &siba->siba_sprom.mcs2gpo, sizeof(uint16_t) * 8); 2854 return (0); 2855 } 2856 2857 int 2858 siba_sprom_get_mcs5glpo(device_t dev, uint16_t *c) 2859 { 2860 struct siba_dev_softc *sd = device_get_ivars(dev); 2861 struct siba_softc *siba = sd->sd_bus; 2862 2863 memcpy(c, &siba->siba_sprom.mcs5glpo, sizeof(uint16_t) * 8); 2864 return (0); 2865 } 2866 2867 int 2868 siba_sprom_get_mcs5gpo(device_t dev, uint16_t *c) 2869 { 2870 struct siba_dev_softc *sd = device_get_ivars(dev); 2871 struct siba_softc *siba = sd->sd_bus; 2872 2873 memcpy(c, &siba->siba_sprom.mcs5gpo, sizeof(uint16_t) * 8); 2874 return (0); 2875 } 2876 2877 int 2878 siba_sprom_get_mcs5ghpo(device_t dev, uint16_t *c) 2879 { 2880 struct siba_dev_softc *sd = device_get_ivars(dev); 2881 struct siba_softc *siba = sd->sd_bus; 2882 2883 memcpy(c, &siba->siba_sprom.mcs5ghpo, sizeof(uint16_t) * 8); 2884 return (0); 2885 } 2886 2887 void 2888 siba_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid) 2889 { 2890 struct siba_dev_softc *sd = device_get_ivars(dev); 2891 struct siba_softc *siba = sd->sd_bus; 2892 struct siba_cc *scc; 2893 2894 scc = &siba->siba_cc; 2895 2896 if (scc->scc_dev == NULL) { 2897 device_printf(dev, "%s: called; no pmu\n", __func__); 2898 return; 2899 } 2900 2901 switch (siba_get_chipid(dev)) { 2902 case 0x4322: 2903 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100070); 2904 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x1014140a); 2905 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888854); 2906 if (spur_avoid == 1) 2907 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05201828); 2908 else 2909 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05001828); 2910 break; 2911 case 43222: 2912 if (spur_avoid == 1) { 2913 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11500008); 2914 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0C000C06); 2915 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x0F600a08); 2916 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000); 2917 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x2001E920); 2918 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888815); 2919 } else { 2920 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100008); 2921 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0c000c06); 2922 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x03000a08); 2923 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000); 2924 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x200005c0); 2925 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888855); 2926 } 2927 break; 2928 default: 2929 device_printf(dev, 2930 "%s: unknown spur avoidance settings for chip 0x%04x\n", 2931 __func__, 2932 siba_get_chipid(dev)); 2933 return; 2934 } 2935 2936 /* Both chips above use the same update */ 2937 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_PLL_UPD); 2938 } 2939 2940 void 2941 siba_cc_set32(device_t dev, uint32_t reg, uint32_t val) 2942 { 2943 struct siba_dev_softc *sd = device_get_ivars(dev); 2944 struct siba_softc *siba = sd->sd_bus; 2945 struct siba_cc *scc; 2946 2947 scc = &siba->siba_cc; 2948 2949 if (scc->scc_dev == NULL) { 2950 device_printf(dev, "%s: called; no pmu\n", __func__); 2951 return; 2952 } 2953 2954 SIBA_CC_SET32(scc, reg, val); 2955 } 2956 2957 void 2958 siba_cc_mask32(device_t dev, uint32_t reg, uint32_t mask) 2959 { 2960 struct siba_dev_softc *sd = device_get_ivars(dev); 2961 struct siba_softc *siba = sd->sd_bus; 2962 struct siba_cc *scc; 2963 2964 scc = &siba->siba_cc; 2965 2966 if (scc->scc_dev == NULL) { 2967 device_printf(dev, "%s: called; no pmu\n", __func__); 2968 return; 2969 } 2970 2971 SIBA_CC_MASK32(scc, reg, mask); 2972 } 2973 2974 uint32_t 2975 siba_cc_read32(device_t dev, uint32_t reg) 2976 { 2977 struct siba_dev_softc *sd = device_get_ivars(dev); 2978 struct siba_softc *siba = sd->sd_bus; 2979 struct siba_cc *scc; 2980 2981 scc = &siba->siba_cc; 2982 2983 if (scc->scc_dev == NULL) { 2984 device_printf(dev, "%s: called; no pmu\n", __func__); 2985 return 0xffffffff; 2986 } 2987 2988 return SIBA_CC_READ32(scc, reg); 2989 } 2990 2991 void 2992 siba_cc_write32(device_t dev, uint32_t reg, uint32_t val) 2993 { 2994 struct siba_dev_softc *sd = device_get_ivars(dev); 2995 struct siba_softc *siba = sd->sd_bus; 2996 struct siba_cc *scc; 2997 2998 scc = &siba->siba_cc; 2999 3000 if (scc->scc_dev == NULL) { 3001 device_printf(dev, "%s: called; no pmu\n", __func__); 3002 return; 3003 } 3004 3005 SIBA_CC_WRITE32(scc, reg, val); 3006 } 3007