1 /*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: head/sys/dev/siba/siba_core.c 299541 2016-05-12 16:14:16Z adrian $"); 32 33 /* 34 * the Sonics Silicon Backplane driver. 35 */ 36 37 #include "opt_siba.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/kernel.h> 44 #include <sys/endian.h> 45 #include <sys/errno.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #if !defined(__DragonFly__) 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #endif 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <sys/socket.h> 55 56 #include <net/if.h> 57 #include <net/if_media.h> 58 #include <net/if_arp.h> 59 60 #if defined(__DragonFly__) 61 #include <bus/pci/pcivar.h> 62 #include <bus/pci/pcireg.h> 63 #else 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 #endif 67 68 #if defined(__DragonFly__) 69 #include "siba_ids.h" 70 #include "sibareg.h" 71 #include "sibavar.h" 72 #else 73 #include <dev/siba/siba_ids.h> 74 #include <dev/siba/sibareg.h> 75 #include <dev/siba/sibavar.h> 76 #endif 77 78 enum { 79 SIBA_DEBUG_SCAN = 0x00000001, /* scan */ 80 SIBA_DEBUG_PMU = 0x00000002, /* PMU */ 81 SIBA_DEBUG_PLL = 0x00000004, /* PLL */ 82 SIBA_DEBUG_SWITCHCORE = 0x00000008, /* switching core */ 83 SIBA_DEBUG_SPROM = 0x00000010, /* SPROM */ 84 SIBA_DEBUG_CORE = 0x00000020, /* handling cores */ 85 SIBA_DEBUG_ANY = 0xffffffff 86 }; 87 88 #ifdef SIBA_DEBUG 89 #define DPRINTF(siba, m, ...) do { \ 90 if (siba->siba_debug & (m)) \ 91 device_printf(siba->siba_dev, __VA_ARGS__); \ 92 } while (0) 93 #else 94 #define DPRINTF(siba, m, ...) do { (void) siba; } while (0) 95 #endif 96 97 static void siba_pci_gpio(struct siba_softc *, uint32_t, int); 98 static void siba_scan(struct siba_softc *); 99 static int siba_switchcore(struct siba_softc *, uint8_t); 100 static int siba_pci_switchcore_sub(struct siba_softc *, uint8_t); 101 static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t); 102 static uint16_t siba_dev2chipid(struct siba_softc *); 103 static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t); 104 static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t); 105 static void siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t); 106 static void siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t); 107 static void siba_cc_clock(struct siba_cc *, 108 enum siba_clock); 109 static void siba_cc_pmu_init(struct siba_cc *); 110 static void siba_cc_power_init(struct siba_cc *); 111 static void siba_cc_powerup_delay(struct siba_cc *); 112 static int siba_cc_clockfreq(struct siba_cc *, int); 113 static void siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t); 114 static void siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t); 115 static enum siba_clksrc siba_cc_clksrc(struct siba_cc *); 116 static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t); 117 static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t); 118 static void siba_cc_pll_write(struct siba_cc *, uint32_t, 119 uint32_t); 120 static const struct siba_cc_pmu0_plltab * 121 siba_cc_pmu0_plltab_findentry(uint32_t); 122 static int siba_pci_sprom(struct siba_softc *, struct siba_sprom *); 123 static int siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t); 124 static int sprom_check_crc(const uint16_t *, size_t); 125 static uint8_t siba_crc8(uint8_t, uint8_t); 126 static void siba_sprom_r123(struct siba_sprom *, const uint16_t *); 127 static void siba_sprom_r45(struct siba_sprom *, const uint16_t *); 128 static void siba_sprom_r8(struct siba_sprom *, const uint16_t *); 129 static int8_t siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t, 130 uint16_t); 131 static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *); 132 static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t); 133 static void siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t); 134 static uint32_t siba_pcie_read(struct siba_pci *, uint32_t); 135 static void siba_pcie_write(struct siba_pci *, uint32_t, uint32_t); 136 static void siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t, 137 uint16_t); 138 static void siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t, 139 uint16_t); 140 static void siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t, 141 uint16_t); 142 static void siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t, 143 uint16_t); 144 static void siba_pci_write_multi_1(struct siba_dev_softc *, const void *, 145 size_t, uint16_t); 146 static void siba_pci_write_multi_2(struct siba_dev_softc *, const void *, 147 size_t, uint16_t); 148 static void siba_pci_write_multi_4(struct siba_dev_softc *, const void *, 149 size_t, uint16_t); 150 static const char *siba_core_name(uint16_t); 151 static void siba_pcicore_init(struct siba_pci *); 152 static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t); 153 static void siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t); 154 static void siba_powerup_sub(struct siba_softc *, int); 155 static int siba_powerdown_sub(struct siba_softc *); 156 static int siba_dev_isup_sub(struct siba_dev_softc *); 157 static void siba_dev_up_sub(struct siba_dev_softc *, uint32_t); 158 static void siba_dev_down_sub(struct siba_dev_softc *, uint32_t); 159 int siba_core_attach(struct siba_softc *); 160 int siba_core_detach(struct siba_softc *); 161 int siba_core_suspend(struct siba_softc *); 162 int siba_core_resume(struct siba_softc *); 163 uint8_t siba_getncores(device_t, uint16_t); 164 165 static const struct siba_bus_ops siba_pci_ops = { 166 .read_2 = siba_pci_read_2, 167 .read_4 = siba_pci_read_4, 168 .write_2 = siba_pci_write_2, 169 .write_4 = siba_pci_write_4, 170 .read_multi_1 = siba_pci_read_multi_1, 171 .read_multi_2 = siba_pci_read_multi_2, 172 .read_multi_4 = siba_pci_read_multi_4, 173 .write_multi_1 = siba_pci_write_multi_1, 174 .write_multi_2 = siba_pci_write_multi_2, 175 .write_multi_4 = siba_pci_write_multi_4, 176 }; 177 178 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] = 179 SIBA_CC_PMU_4325_RES_UPDOWN; 180 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] = 181 SIBA_CC_PMU_4325_RES_DEPEND; 182 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] = 183 SIBA_CC_PMU_4328_RES_UPDOWN; 184 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] = 185 SIBA_CC_PMU_4328_RES_DEPEND; 186 static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] = 187 SIBA_CC_PMU0_PLLTAB_ENTRY; 188 static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] = 189 SIBA_CC_PMU1_PLLTAB_ENTRY; 190 191 int 192 siba_core_attach(struct siba_softc *siba) 193 { 194 struct siba_cc *scc; 195 int error; 196 197 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 198 ("unsupported BUS type (%#x)", siba->siba_type)); 199 200 siba->siba_ops = &siba_pci_ops; 201 202 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); 203 siba_scan(siba); 204 205 /* XXX init PCI or PCMCIA host devices */ 206 207 siba_powerup_sub(siba, 0); 208 209 /* init ChipCommon */ 210 scc = &siba->siba_cc; 211 if (scc->scc_dev != NULL) { 212 siba_cc_pmu_init(scc); 213 siba_cc_power_init(scc); 214 siba_cc_clock(scc, SIBA_CLOCK_FAST); 215 siba_cc_powerup_delay(scc); 216 } 217 218 error = siba_pci_sprom(siba, &siba->siba_sprom); 219 if (error) { 220 siba_powerdown_sub(siba); 221 return (error); 222 } 223 224 siba_pcicore_init(&siba->siba_pci); 225 siba_powerdown_sub(siba); 226 227 return (bus_generic_attach(siba->siba_dev)); 228 } 229 230 int 231 siba_core_detach(struct siba_softc *siba) 232 { 233 /* detach & delete all children */ 234 device_delete_children(siba->siba_dev); 235 return (0); 236 } 237 238 static void 239 siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on) 240 { 241 uint32_t in, out; 242 uint16_t status; 243 244 if (siba->siba_type != SIBA_TYPE_PCI) 245 return; 246 247 out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4); 248 if (on == 0) { 249 if (what & SIBA_GPIO_PLL) 250 out |= SIBA_GPIO_PLL; 251 if (what & SIBA_GPIO_CRYSTAL) 252 out &= ~SIBA_GPIO_CRYSTAL; 253 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 254 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN, 255 pci_read_config(siba->siba_dev, 256 SIBA_GPIO_OUT_EN, 4) | what, 4); 257 return; 258 } 259 260 in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4); 261 if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) { 262 if (what & SIBA_GPIO_CRYSTAL) { 263 out |= SIBA_GPIO_CRYSTAL; 264 if (what & SIBA_GPIO_PLL) 265 out |= SIBA_GPIO_PLL; 266 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 267 pci_write_config(siba->siba_dev, 268 SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev, 269 SIBA_GPIO_OUT_EN, 4) | what, 4); 270 DELAY(1000); 271 } 272 if (what & SIBA_GPIO_PLL) { 273 out &= ~SIBA_GPIO_PLL; 274 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 275 DELAY(5000); 276 } 277 } 278 279 status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2); 280 status &= ~PCIM_STATUS_STABORT; 281 pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2); 282 } 283 284 static void 285 siba_scan(struct siba_softc *siba) 286 { 287 struct siba_dev_softc *sd; 288 uint32_t idhi, tmp; 289 device_t child; 290 int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0, 291 n_pci = 0; 292 293 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 294 ("unsupported BUS type (%#x)", siba->siba_type)); 295 296 siba->siba_ndevs = 0; 297 error = siba_switchcore(siba, 0); /* need the first core */ 298 if (error) 299 return; 300 301 idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH); 302 if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) { 303 tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID); 304 siba->siba_chipid = SIBA_CC_ID(tmp); 305 siba->siba_chiprev = SIBA_CC_REV(tmp); 306 siba->siba_chippkg = SIBA_CC_PKG(tmp); 307 if (SIBA_IDHIGH_REV(idhi) >= 4) 308 siba->siba_ndevs = SIBA_CC_NCORES(tmp); 309 siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0, 310 SIBA_CC_CAPS); 311 } else { 312 if (siba->siba_type == SIBA_TYPE_PCI) { 313 siba->siba_chipid = siba_dev2chipid(siba); 314 siba->siba_chiprev = pci_read_config(siba->siba_dev, 315 PCIR_REVID, 2); 316 siba->siba_chippkg = 0; 317 } else { 318 siba->siba_chipid = 0x4710; 319 siba->siba_chiprev = 0; 320 siba->siba_chippkg = 0; 321 } 322 } 323 if (siba->siba_ndevs == 0) 324 siba->siba_ndevs = siba_getncores(siba->siba_dev, 325 siba->siba_chipid); 326 if (siba->siba_ndevs > SIBA_MAX_CORES) { 327 device_printf(siba->siba_dev, 328 "too many siba cores (max %d %d)\n", 329 SIBA_MAX_CORES, siba->siba_ndevs); 330 return; 331 } 332 333 /* looking basic information about each cores/devices */ 334 for (i = 0; i < siba->siba_ndevs; i++) { 335 error = siba_switchcore(siba, i); 336 if (error) 337 return; 338 sd = &(siba->siba_devs[dev_i]); 339 idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH); 340 sd->sd_bus = siba; 341 sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi); 342 sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi); 343 sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi); 344 sd->sd_ops = siba->siba_ops; 345 sd->sd_coreidx = i; 346 347 DPRINTF(siba, SIBA_DEBUG_SCAN, 348 "core %d (%s) found (cc %#xrev %#x vendor %#x)\n", 349 i, siba_core_name(sd->sd_id.sd_device), 350 sd->sd_id.sd_device, sd->sd_id.sd_rev, sd->sd_id.sd_vendor); 351 352 switch (sd->sd_id.sd_device) { 353 case SIBA_DEVID_CHIPCOMMON: 354 n_cc++; 355 if (n_cc > 1) { 356 device_printf(siba->siba_dev, 357 "warn: multiple ChipCommon\n"); 358 break; 359 } 360 siba->siba_cc.scc_dev = sd; 361 break; 362 case SIBA_DEVID_80211: 363 n_80211++; 364 if (n_80211 > 1) { 365 device_printf(siba->siba_dev, 366 "warn: multiple 802.11 core\n"); 367 continue; 368 } 369 break; 370 case SIBA_DEVID_PCI: 371 case SIBA_DEVID_PCIE: 372 n_pci++; 373 #if defined(__DragonFly__) 374 error = pci_find_extcap(siba->siba_dev, PCIY_EXPRESS, 375 &base); 376 #else 377 error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS, 378 &base); 379 #endif 380 is_pcie = (error == 0) ? 1 : 0; 381 382 if (n_pci > 1) { 383 device_printf(siba->siba_dev, 384 "warn: multiple PCI(E) cores\n"); 385 break; 386 } 387 if (sd->sd_id.sd_device == SIBA_DEVID_PCI && 388 is_pcie == 1) 389 continue; 390 if (sd->sd_id.sd_device == SIBA_DEVID_PCIE && 391 is_pcie == 0) 392 continue; 393 siba->siba_pci.spc_dev = sd; 394 break; 395 case SIBA_DEVID_MODEM: 396 case SIBA_DEVID_PCMCIA: 397 break; 398 default: 399 device_printf(siba->siba_dev, 400 "unsupported coreid (%s)\n", 401 siba_core_name(sd->sd_id.sd_device)); 402 break; 403 } 404 dev_i++; 405 406 child = device_add_child(siba->siba_dev, NULL, -1); 407 if (child == NULL) { 408 device_printf(siba->siba_dev, "child attach failed\n"); 409 continue; 410 } 411 412 device_set_ivars(child, sd); 413 } 414 siba->siba_ndevs = dev_i; 415 } 416 417 static int 418 siba_switchcore(struct siba_softc *siba, uint8_t idx) 419 { 420 421 switch (siba->siba_type) { 422 case SIBA_TYPE_PCI: 423 return (siba_pci_switchcore_sub(siba, idx)); 424 default: 425 KASSERT(0 == 1, 426 ("%s: unsupported bustype %#x", __func__, 427 siba->siba_type)); 428 } 429 return (0); 430 } 431 432 static int 433 siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx) 434 { 435 #define RETRY_MAX 50 436 int i; 437 uint32_t dir; 438 439 dir = SIBA_REGWIN(idx); 440 441 for (i = 0; i < RETRY_MAX; i++) { 442 pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4); 443 if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir) 444 return (0); 445 DELAY(10); 446 } 447 return (ENODEV); 448 #undef RETRY_MAX 449 } 450 451 static int 452 siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd) 453 { 454 int error; 455 456 DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n", 457 siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx); 458 459 error = siba_pci_switchcore_sub(siba, sd->sd_coreidx); 460 if (error == 0) 461 siba->siba_curdev = sd; 462 463 return (error); 464 } 465 466 static uint32_t 467 siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx, 468 uint16_t offset) 469 { 470 471 (void)coreidx; 472 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 473 ("unsupported BUS type (%#x)", siba->siba_type)); 474 475 return (SIBA_READ_4(siba, offset)); 476 } 477 478 static uint16_t 479 siba_dev2chipid(struct siba_softc *siba) 480 { 481 uint16_t chipid = 0; 482 483 switch (siba->siba_pci_did) { 484 case 0x4301: 485 chipid = 0x4301; 486 break; 487 case 0x4305: 488 case 0x4306: 489 case 0x4307: 490 chipid = 0x4307; 491 break; 492 case 0x4403: 493 chipid = 0x4402; 494 break; 495 case 0x4610: 496 case 0x4611: 497 case 0x4612: 498 case 0x4613: 499 case 0x4614: 500 case 0x4615: 501 chipid = 0x4610; 502 break; 503 case 0x4710: 504 case 0x4711: 505 case 0x4712: 506 case 0x4713: 507 case 0x4714: 508 case 0x4715: 509 chipid = 0x4710; 510 break; 511 case 0x4320: 512 case 0x4321: 513 case 0x4322: 514 case 0x4323: 515 case 0x4324: 516 case 0x4325: 517 chipid = 0x4309; 518 break; 519 case PCI_DEVICE_ID_BCM4401: 520 case PCI_DEVICE_ID_BCM4401B0: 521 case PCI_DEVICE_ID_BCM4401B1: 522 chipid = 0x4401; 523 break; 524 default: 525 device_printf(siba->siba_dev, "unknown PCI did (%d)\n", 526 siba->siba_pci_did); 527 } 528 529 return (chipid); 530 } 531 532 /* 533 * Earlier ChipCommon revisions have hardcoded number of cores 534 * present dependent on the ChipCommon ID. 535 */ 536 uint8_t 537 siba_getncores(device_t dev, uint16_t chipid) 538 { 539 switch (chipid) { 540 case 0x4401: 541 case 0x4402: 542 return (3); 543 case 0x4301: 544 case 0x4307: 545 return (5); 546 case 0x4306: 547 return (6); 548 case SIBA_CCID_SENTRY5: 549 return (7); 550 case 0x4310: 551 return (8); 552 case SIBA_CCID_BCM4710: 553 case 0x4610: 554 case SIBA_CCID_BCM4704: 555 return (9); 556 default: 557 device_printf(dev, "unknown the chipset ID %#x\n", chipid); 558 } 559 560 return (1); 561 } 562 563 static const char * 564 siba_core_name(uint16_t coreid) 565 { 566 567 switch (coreid) { 568 case SIBA_DEVID_CHIPCOMMON: 569 return ("ChipCommon"); 570 case SIBA_DEVID_ILINE20: 571 return ("ILine 20"); 572 case SIBA_DEVID_SDRAM: 573 return ("SDRAM"); 574 case SIBA_DEVID_PCI: 575 return ("PCI"); 576 case SIBA_DEVID_MIPS: 577 return ("MIPS"); 578 case SIBA_DEVID_ETHERNET: 579 return ("Fast Ethernet"); 580 case SIBA_DEVID_MODEM: 581 return ("Modem"); 582 case SIBA_DEVID_USB11_HOSTDEV: 583 return ("USB 1.1 Hostdev"); 584 case SIBA_DEVID_ADSL: 585 return ("ADSL"); 586 case SIBA_DEVID_ILINE100: 587 return ("ILine 100"); 588 case SIBA_DEVID_IPSEC: 589 return ("IPSEC"); 590 case SIBA_DEVID_PCMCIA: 591 return ("PCMCIA"); 592 case SIBA_DEVID_INTERNAL_MEM: 593 return ("Internal Memory"); 594 case SIBA_DEVID_SDRAMDDR: 595 return ("MEMC SDRAM"); 596 case SIBA_DEVID_EXTIF: 597 return ("EXTIF"); 598 case SIBA_DEVID_80211: 599 return ("IEEE 802.11"); 600 case SIBA_DEVID_MIPS_3302: 601 return ("MIPS 3302"); 602 case SIBA_DEVID_USB11_HOST: 603 return ("USB 1.1 Host"); 604 case SIBA_DEVID_USB11_DEV: 605 return ("USB 1.1 Device"); 606 case SIBA_DEVID_USB20_HOST: 607 return ("USB 2.0 Host"); 608 case SIBA_DEVID_USB20_DEV: 609 return ("USB 2.0 Device"); 610 case SIBA_DEVID_SDIO_HOST: 611 return ("SDIO Host"); 612 case SIBA_DEVID_ROBOSWITCH: 613 return ("Roboswitch"); 614 case SIBA_DEVID_PARA_ATA: 615 return ("PATA"); 616 case SIBA_DEVID_SATA_XORDMA: 617 return ("SATA XOR-DMA"); 618 case SIBA_DEVID_ETHERNET_GBIT: 619 return ("GBit Ethernet"); 620 case SIBA_DEVID_PCIE: 621 return ("PCI-Express"); 622 case SIBA_DEVID_MIMO_PHY: 623 return ("MIMO PHY"); 624 case SIBA_DEVID_SRAM_CTRLR: 625 return ("SRAM Controller"); 626 case SIBA_DEVID_MINI_MACPHY: 627 return ("Mini MACPHY"); 628 case SIBA_DEVID_ARM_1176: 629 return ("ARM 1176"); 630 case SIBA_DEVID_ARM_7TDMI: 631 return ("ARM 7TDMI"); 632 } 633 return ("unknown"); 634 } 635 636 static uint16_t 637 siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset) 638 { 639 struct siba_softc *siba = sd->sd_bus; 640 641 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 642 return (0xffff); 643 644 return (SIBA_READ_2(siba, offset)); 645 } 646 647 static uint32_t 648 siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset) 649 { 650 struct siba_softc *siba = sd->sd_bus; 651 652 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 653 return (0xffff); 654 655 return (SIBA_READ_4(siba, offset)); 656 } 657 658 static void 659 siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value) 660 { 661 struct siba_softc *siba = sd->sd_bus; 662 663 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 664 return; 665 666 SIBA_WRITE_2(siba, offset, value); 667 } 668 669 static void 670 siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) 671 { 672 struct siba_softc *siba = sd->sd_bus; 673 674 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 675 return; 676 677 SIBA_WRITE_4(siba, offset, value); 678 } 679 680 static void 681 siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count, 682 uint16_t offset) 683 { 684 struct siba_softc *siba = sd->sd_bus; 685 686 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 687 memset(buffer, 0xff, count); 688 return; 689 } 690 691 SIBA_READ_MULTI_1(siba, offset, buffer, count); 692 } 693 694 static void 695 siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count, 696 uint16_t offset) 697 { 698 struct siba_softc *siba = sd->sd_bus; 699 700 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 701 memset(buffer, 0xff, count); 702 return; 703 } 704 705 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); 706 SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1); 707 } 708 709 static void 710 siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count, 711 uint16_t offset) 712 { 713 struct siba_softc *siba = sd->sd_bus; 714 715 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 716 memset(buffer, 0xff, count); 717 return; 718 } 719 720 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); 721 SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2); 722 } 723 724 static void 725 siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer, 726 size_t count, uint16_t offset) 727 { 728 struct siba_softc *siba = sd->sd_bus; 729 730 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 731 return; 732 733 SIBA_WRITE_MULTI_1(siba, offset, buffer, count); 734 } 735 736 static void 737 siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer, 738 size_t count, uint16_t offset) 739 { 740 struct siba_softc *siba = sd->sd_bus; 741 742 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 743 return; 744 745 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); 746 SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1); 747 } 748 749 static void 750 siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer, 751 size_t count, uint16_t offset) 752 { 753 struct siba_softc *siba = sd->sd_bus; 754 755 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 756 return; 757 758 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); 759 SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2); 760 } 761 762 void 763 siba_powerup(device_t dev, int dynamic) 764 { 765 struct siba_dev_softc *sd = device_get_ivars(dev); 766 struct siba_softc *siba = sd->sd_bus; 767 768 siba_powerup_sub(siba, dynamic); 769 } 770 771 static void 772 siba_powerup_sub(struct siba_softc *siba, int dynamic) 773 { 774 775 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); 776 siba_cc_clock(&siba->siba_cc, 777 (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST); 778 } 779 780 static void 781 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock) 782 { 783 struct siba_dev_softc *sd = scc->scc_dev; 784 struct siba_softc *siba; 785 uint32_t tmp; 786 787 if (sd == NULL) 788 return; 789 siba = sd->sd_bus; 790 /* 791 * chipcommon < r6 (no dynamic clock control) 792 * chipcommon >= r10 (unknown) 793 */ 794 if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 || 795 (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) 796 return; 797 798 switch (clock) { 799 case SIBA_CLOCK_DYNAMIC: 800 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 801 ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW | 802 SIBA_CC_CLKSLOW_IPLL); 803 if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL) 804 tmp |= SIBA_CC_CLKSLOW_ENXTAL; 805 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp); 806 if (tmp & SIBA_CC_CLKSLOW_ENXTAL) 807 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0); 808 break; 809 case SIBA_CLOCK_SLOW: 810 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, 811 SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | 812 SIBA_CC_CLKSLOW_FSLOW); 813 break; 814 case SIBA_CLOCK_FAST: 815 /* crystal on */ 816 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1); 817 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, 818 (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | 819 SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW); 820 break; 821 default: 822 KASSERT(0 == 1, 823 ("%s: unsupported clock %#x", __func__, clock)); 824 } 825 } 826 827 uint16_t 828 siba_read_2(device_t dev, uint16_t offset) 829 { 830 struct siba_dev_softc *sd = device_get_ivars(dev); 831 832 return (sd->sd_ops->read_2(sd, offset)); 833 } 834 835 uint32_t 836 siba_read_4(device_t dev, uint16_t offset) 837 { 838 struct siba_dev_softc *sd = device_get_ivars(dev); 839 840 return (siba_read_4_sub(sd, offset)); 841 } 842 843 static uint32_t 844 siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset) 845 { 846 847 return (sd->sd_ops->read_4(sd, offset)); 848 } 849 850 void 851 siba_write_2(device_t dev, uint16_t offset, uint16_t value) 852 { 853 struct siba_dev_softc *sd = device_get_ivars(dev); 854 855 sd->sd_ops->write_2(sd, offset, value); 856 } 857 858 void 859 siba_write_4(device_t dev, uint16_t offset, uint32_t value) 860 { 861 struct siba_dev_softc *sd = device_get_ivars(dev); 862 863 return (siba_write_4_sub(sd, offset, value)); 864 } 865 866 static void 867 siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) 868 { 869 870 sd->sd_ops->write_4(sd, offset, value); 871 } 872 873 void 874 siba_read_multi_1(device_t dev, void *buffer, size_t count, 875 uint16_t offset) 876 { 877 struct siba_dev_softc *sd = device_get_ivars(dev); 878 879 sd->sd_ops->read_multi_1(sd, buffer, count, offset); 880 } 881 882 void 883 siba_read_multi_2(device_t dev, void *buffer, size_t count, 884 uint16_t offset) 885 { 886 struct siba_dev_softc *sd = device_get_ivars(dev); 887 888 sd->sd_ops->read_multi_2(sd, buffer, count, offset); 889 } 890 891 void 892 siba_read_multi_4(device_t dev, void *buffer, size_t count, 893 uint16_t offset) 894 { 895 struct siba_dev_softc *sd = device_get_ivars(dev); 896 897 sd->sd_ops->read_multi_4(sd, buffer, count, offset); 898 } 899 900 void 901 siba_write_multi_1(device_t dev, const void *buffer, size_t count, 902 uint16_t offset) 903 { 904 struct siba_dev_softc *sd = device_get_ivars(dev); 905 906 sd->sd_ops->write_multi_1(sd, buffer, count, offset); 907 } 908 909 void 910 siba_write_multi_2(device_t dev, const void *buffer, size_t count, 911 uint16_t offset) 912 { 913 struct siba_dev_softc *sd = device_get_ivars(dev); 914 915 sd->sd_ops->write_multi_2(sd, buffer, count, offset); 916 } 917 918 void 919 siba_write_multi_4(device_t dev, const void *buffer, size_t count, 920 uint16_t offset) 921 { 922 struct siba_dev_softc *sd = device_get_ivars(dev); 923 924 sd->sd_ops->write_multi_4(sd, buffer, count, offset); 925 } 926 927 static void 928 siba_cc_pmu_init(struct siba_cc *scc) 929 { 930 const struct siba_cc_pmu_res_updown *updown = NULL; 931 const struct siba_cc_pmu_res_depend *depend = NULL; 932 struct siba_dev_softc *sd = scc->scc_dev; 933 struct siba_softc *siba = sd->sd_bus; 934 uint32_t min = 0, max = 0, pmucap; 935 unsigned int i, updown_size, depend_size; 936 937 if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0) 938 return; 939 940 pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS); 941 scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV); 942 943 DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n", 944 scc->scc_pmu.rev, pmucap); 945 946 if (scc->scc_pmu.rev >= 1) { 947 if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325) 948 SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, 949 ~SIBA_CC_PMUCTL_NOILP); 950 else 951 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, 952 SIBA_CC_PMUCTL_NOILP); 953 } 954 955 /* initialize PLL & PMU resources */ 956 switch (siba->siba_chipid) { 957 case 0x4312: 958 siba_cc_pmu1_pll0_init(scc, 0 /* use default */); 959 /* use the default: min = 0xcbb max = 0x7ffff */ 960 break; 961 case 0x4325: 962 siba_cc_pmu1_pll0_init(scc, 0 /* use default */); 963 964 updown = siba_cc_pmu_4325_updown; 965 updown_size = nitems(siba_cc_pmu_4325_updown); 966 depend = siba_cc_pmu_4325_depend; 967 depend_size = nitems(siba_cc_pmu_4325_depend); 968 969 min = (1 << SIBA_CC_PMU_4325_BURST) | 970 (1 << SIBA_CC_PMU_4325_LN); 971 if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) & 972 SIBA_CC_CHST_4325_PMUTOP_2B) 973 min |= (1 << SIBA_CC_PMU_4325_CLBURST); 974 max = 0xfffff; 975 break; 976 case 0x4328: 977 siba_cc_pmu0_pll0_init(scc, 0 /* use default */); 978 979 updown = siba_cc_pmu_4328_updown; 980 updown_size = nitems(siba_cc_pmu_4328_updown); 981 depend = siba_cc_pmu_4328_depend; 982 depend_size = nitems(siba_cc_pmu_4328_depend); 983 984 min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | 985 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) | 986 (1 << SIBA_CC_PMU_4328_CRYSTAL_EN); 987 988 max = 0xfffff; 989 break; 990 case 0x5354: 991 siba_cc_pmu0_pll0_init(scc, 0 /* use default */); 992 993 max = 0xfffff; 994 break; 995 default: 996 device_printf(siba->siba_dev, 997 "unknown chipid %#x for PLL & PMU init\n", 998 siba->siba_chipid); 999 } 1000 1001 if (updown) { 1002 for (i = 0; i < updown_size; i++) { 1003 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, 1004 updown[i].res); 1005 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM, 1006 updown[i].updown); 1007 } 1008 } 1009 if (depend) { 1010 for (i = 0; i < depend_size; i++) { 1011 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, 1012 depend[i].res); 1013 switch (depend[i].task) { 1014 case SIBA_CC_PMU_DEP_SET: 1015 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK, 1016 depend[i].depend); 1017 break; 1018 case SIBA_CC_PMU_DEP_ADD: 1019 SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK, 1020 depend[i].depend); 1021 break; 1022 case SIBA_CC_PMU_DEP_REMOVE: 1023 SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK, 1024 ~(depend[i].depend)); 1025 break; 1026 default: 1027 KASSERT(0 == 1, 1028 ("%s:%d: assertion failed", 1029 __func__, __LINE__)); 1030 } 1031 } 1032 } 1033 1034 if (min) 1035 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min); 1036 if (max) 1037 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max); 1038 } 1039 1040 static void 1041 siba_cc_power_init(struct siba_cc *scc) 1042 { 1043 struct siba_softc *siba = scc->scc_dev->sd_bus; 1044 int maxfreq; 1045 1046 if (siba->siba_chipid == 0x4321) { 1047 if (siba->siba_chiprev == 0) 1048 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4); 1049 else if (siba->siba_chiprev == 1) 1050 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4); 1051 } 1052 1053 if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) 1054 return; 1055 1056 if (scc->scc_dev->sd_id.sd_rev >= 10) 1057 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL, 1058 (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) & 1059 0xffff) | 0x40000); 1060 else { 1061 maxfreq = siba_cc_clockfreq(scc, 1); 1062 SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY, 1063 (maxfreq * 150 + 999999) / 1000000); 1064 SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY, 1065 (maxfreq * 15 + 999999) / 1000000); 1066 } 1067 } 1068 1069 static void 1070 siba_cc_powerup_delay(struct siba_cc *scc) 1071 { 1072 struct siba_softc *siba = scc->scc_dev->sd_bus; 1073 int min; 1074 1075 if (siba->siba_type != SIBA_TYPE_PCI || 1076 !(scc->scc_caps & SIBA_CC_CAPS_PWCTL)) 1077 return; 1078 1079 min = siba_cc_clockfreq(scc, 0); 1080 scc->scc_powerup_delay = 1081 howmany((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000, 1082 min); 1083 } 1084 1085 static int 1086 siba_cc_clockfreq(struct siba_cc *scc, int max) 1087 { 1088 enum siba_clksrc src; 1089 int div = 1, limit = 0; 1090 1091 src = siba_cc_clksrc(scc); 1092 if (scc->scc_dev->sd_id.sd_rev < 6) { 1093 div = (src == SIBA_CC_CLKSRC_PCI) ? 64 : 1094 (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1; 1095 KASSERT(div != 1, 1096 ("%s: unknown clock %d", __func__, src)); 1097 } else if (scc->scc_dev->sd_id.sd_rev < 10) { 1098 switch (src) { 1099 case SIBA_CC_CLKSRC_CRYSTAL: 1100 case SIBA_CC_CLKSRC_PCI: 1101 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) + 1102 1) * 4; 1103 break; 1104 case SIBA_CC_CLKSRC_LOWPW: 1105 break; 1106 } 1107 } else 1108 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4; 1109 1110 switch (src) { 1111 case SIBA_CC_CLKSRC_CRYSTAL: 1112 limit = (max) ? 20200000 : 19800000; 1113 break; 1114 case SIBA_CC_CLKSRC_LOWPW: 1115 limit = (max) ? 43000 : 25000; 1116 break; 1117 case SIBA_CC_CLKSRC_PCI: 1118 limit = (max) ? 34000000 : 25000000; 1119 break; 1120 } 1121 1122 return (limit / div); 1123 } 1124 1125 static void 1126 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq) 1127 { 1128 struct siba_dev_softc *sd = scc->scc_dev; 1129 struct siba_softc *siba = sd->sd_bus; 1130 const struct siba_cc_pmu1_plltab *e = NULL; 1131 uint32_t bufsth = 0, pll, pmu; 1132 unsigned int i; 1133 1134 KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__)); 1135 if (siba->siba_chipid == 0x4312) { 1136 scc->scc_pmu.freq = 20000; 1137 return; 1138 } 1139 1140 e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ); 1141 KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__)); 1142 scc->scc_pmu.freq = e->freq; 1143 1144 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1145 if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf) 1146 return; 1147 1148 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", 1149 (e->freq / 1000), (e->freq % 1000)); 1150 1151 /* turn PLL off */ 1152 switch (siba->siba_chipid) { 1153 case 0x4325: 1154 bufsth = 0x222222; 1155 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1156 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | 1157 (1 << SIBA_CC_PMU_4325_HT))); 1158 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1159 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | 1160 (1 << SIBA_CC_PMU_4325_HT))); 1161 break; 1162 default: 1163 KASSERT(0 == 1, 1164 ("%s:%d: assertion failed", __func__, __LINE__)); 1165 } 1166 for (i = 0; i < 1500; i++) { 1167 if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & 1168 SIBA_CC_CLKCTLSTATUS_HT)) 1169 break; 1170 DELAY(10); 1171 } 1172 if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT) 1173 device_printf(siba->siba_dev, "failed to turn PLL off!\n"); 1174 1175 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0); 1176 pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV); 1177 pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV; 1178 pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV; 1179 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll); 1180 1181 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2); 1182 pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE); 1183 pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT; 1184 pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE; 1185 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll); 1186 1187 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3); 1188 pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC; 1189 pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC; 1190 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll); 1191 1192 if (bufsth) { 1193 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5); 1194 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV; 1195 pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV; 1196 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll); 1197 } 1198 1199 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1200 pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF); 1201 pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) & 1202 SIBA_CC_PMUCTL_ILP; 1203 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; 1204 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); 1205 } 1206 1207 static void 1208 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq) 1209 { 1210 struct siba_dev_softc *sd = scc->scc_dev; 1211 struct siba_softc *siba = sd->sd_bus; 1212 const struct siba_cc_pmu0_plltab *e = NULL; 1213 uint32_t pmu, tmp, pll; 1214 unsigned int i; 1215 1216 if ((siba->siba_chipid == 0x5354) && !xtalfreq) 1217 xtalfreq = 25000; 1218 if (xtalfreq) 1219 e = siba_cc_pmu0_plltab_findentry(xtalfreq); 1220 if (!e) 1221 e = siba_cc_pmu0_plltab_findentry( 1222 SIBA_CC_PMU0_DEFAULT_XTALFREQ); 1223 KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__)); 1224 xtalfreq = e->freq; 1225 scc->scc_pmu.freq = e->freq; 1226 1227 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1228 if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf) 1229 return; 1230 1231 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", 1232 (xtalfreq / 1000), (xtalfreq % 1000)); 1233 1234 KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354, 1235 ("%s:%d: fail", __func__, __LINE__)); 1236 1237 switch (siba->siba_chipid) { 1238 case 0x4328: 1239 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1240 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); 1241 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1242 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); 1243 break; 1244 case 0x5354: 1245 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1246 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); 1247 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1248 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); 1249 break; 1250 } 1251 for (i = 1500; i; i--) { 1252 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); 1253 if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT)) 1254 break; 1255 DELAY(10); 1256 } 1257 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); 1258 if (tmp & SIBA_CC_CLKCTLSTATUS_HT) 1259 device_printf(siba->siba_dev, "failed to turn PLL off!\n"); 1260 1261 /* set PDIV */ 1262 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0); 1263 if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ) 1264 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK; 1265 else 1266 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK; 1267 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll); 1268 1269 /* set WILD */ 1270 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1); 1271 pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK | 1272 SIBA_CC_PMU0_PLL1_FMSK); 1273 pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK; 1274 pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK; 1275 if (e->wb_frac == 0) 1276 pll |= SIBA_CC_PMU0_PLL1_STOPMOD; 1277 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll); 1278 1279 /* set WILD */ 1280 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2); 1281 pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI; 1282 pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI; 1283 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll); 1284 1285 /* set freq and divisor. */ 1286 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1287 pmu &= ~SIBA_CC_PMUCTL_ILP; 1288 pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP; 1289 pmu &= ~SIBA_CC_PMUCTL_XF; 1290 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; 1291 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); 1292 } 1293 1294 static enum siba_clksrc 1295 siba_cc_clksrc(struct siba_cc *scc) 1296 { 1297 struct siba_dev_softc *sd = scc->scc_dev; 1298 struct siba_softc *siba = sd->sd_bus; 1299 1300 if (sd->sd_id.sd_rev < 6) { 1301 if (siba->siba_type == SIBA_TYPE_PCI) { 1302 if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) & 1303 0x10) 1304 return (SIBA_CC_CLKSRC_PCI); 1305 return (SIBA_CC_CLKSRC_CRYSTAL); 1306 } 1307 if (siba->siba_type == SIBA_TYPE_SSB || 1308 siba->siba_type == SIBA_TYPE_PCMCIA) 1309 return (SIBA_CC_CLKSRC_CRYSTAL); 1310 } 1311 if (sd->sd_id.sd_rev < 10) { 1312 switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) { 1313 case 0: 1314 return (SIBA_CC_CLKSRC_LOWPW); 1315 case 1: 1316 return (SIBA_CC_CLKSRC_CRYSTAL); 1317 case 2: 1318 return (SIBA_CC_CLKSRC_PCI); 1319 default: 1320 break; 1321 } 1322 } 1323 1324 return (SIBA_CC_CLKSRC_CRYSTAL); 1325 } 1326 1327 static const struct siba_cc_pmu1_plltab * 1328 siba_cc_pmu1_plltab_find(uint32_t crystalfreq) 1329 { 1330 const struct siba_cc_pmu1_plltab *e; 1331 unsigned int i; 1332 1333 for (i = 0; i < nitems(siba_cc_pmu1_plltab); i++) { 1334 e = &siba_cc_pmu1_plltab[i]; 1335 if (crystalfreq == e->freq) 1336 return (e); 1337 } 1338 1339 return (NULL); 1340 } 1341 1342 static uint32_t 1343 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset) 1344 { 1345 1346 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); 1347 return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA)); 1348 } 1349 1350 static void 1351 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value) 1352 { 1353 1354 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); 1355 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value); 1356 } 1357 1358 static const struct siba_cc_pmu0_plltab * 1359 siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq) 1360 { 1361 const struct siba_cc_pmu0_plltab *e; 1362 unsigned int i; 1363 1364 for (i = 0; i < nitems(siba_cc_pmu0_plltab); i++) { 1365 e = &siba_cc_pmu0_plltab[i]; 1366 if (e->freq == crystalfreq) 1367 return (e); 1368 } 1369 1370 return (NULL); 1371 } 1372 1373 static int 1374 siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom) 1375 { 1376 int error = ENOMEM; 1377 uint16_t *buf; 1378 1379 buf = kmalloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t), 1380 M_DEVBUF, M_INTWAIT | M_ZERO); 1381 if (buf == NULL) 1382 return (ENOMEM); 1383 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123); 1384 error = sprom_check_crc(buf, siba->siba_spromsize); 1385 if (error) { 1386 kfree(buf, M_DEVBUF); 1387 buf = kmalloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t), 1388 M_DEVBUF, M_INTWAIT | M_ZERO); 1389 if (buf == NULL) 1390 return (ENOMEM); 1391 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4); 1392 error = sprom_check_crc(buf, siba->siba_spromsize); 1393 if (error) 1394 device_printf(siba->siba_dev, "warn: bad SPROM CRC\n"); 1395 } 1396 1397 bzero(sprom, sizeof(*sprom)); 1398 1399 sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF; 1400 DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n", 1401 sprom->rev); 1402 memset(sprom->mac_eth, 0xff, 6); 1403 memset(sprom->mac_80211a, 0xff, 6); 1404 if ((siba->siba_chipid & 0xff00) == 0x4400) { 1405 sprom->rev = 1; 1406 siba_sprom_r123(sprom, buf); 1407 } else if (siba->siba_chipid == 0x4321) { 1408 sprom->rev = 4; 1409 siba_sprom_r45(sprom, buf); 1410 } else { 1411 switch (sprom->rev) { 1412 case 1: 1413 case 2: 1414 case 3: 1415 siba_sprom_r123(sprom, buf); 1416 break; 1417 case 4: 1418 case 5: 1419 siba_sprom_r45(sprom, buf); 1420 break; 1421 case 8: 1422 siba_sprom_r8(sprom, buf); 1423 break; 1424 default: 1425 device_printf(siba->siba_dev, 1426 "unknown SPROM revision %d.\n", sprom->rev); 1427 siba_sprom_r123(sprom, buf); 1428 } 1429 } 1430 1431 if (sprom->bf_lo == 0xffff) 1432 sprom->bf_lo = 0; 1433 if (sprom->bf_hi == 0xffff) 1434 sprom->bf_hi = 0; 1435 1436 kfree(buf, M_DEVBUF); 1437 return (error); 1438 } 1439 1440 static int 1441 siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len) 1442 { 1443 int i; 1444 1445 for (i = 0; i < len; i++) 1446 sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2)); 1447 1448 siba->siba_spromsize = len; 1449 return (0); 1450 } 1451 1452 static int 1453 sprom_check_crc(const uint16_t *sprom, size_t size) 1454 { 1455 int word; 1456 uint8_t crc0, crc1 = 0xff; 1457 1458 crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8; 1459 for (word = 0; word < size - 1; word++) { 1460 crc1 = siba_crc8(crc1, sprom[word] & 0x00ff); 1461 crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8); 1462 } 1463 crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff); 1464 crc1 ^= 0xff; 1465 1466 return ((crc0 != crc1) ? EPROTO : 0); 1467 } 1468 1469 static uint8_t 1470 siba_crc8(uint8_t crc, uint8_t data) 1471 { 1472 static const uint8_t ct[] = { 1473 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b, 1474 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21, 1475 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff, 1476 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5, 1477 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14, 1478 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e, 1479 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80, 1480 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca, 1481 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95, 1482 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf, 1483 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01, 1484 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b, 1485 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea, 1486 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0, 1487 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e, 1488 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34, 1489 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0, 1490 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a, 1491 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54, 1492 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e, 1493 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf, 1494 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5, 1495 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b, 1496 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61, 1497 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e, 1498 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74, 1499 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa, 1500 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0, 1501 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41, 1502 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b, 1503 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5, 1504 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f, 1505 }; 1506 return (ct[crc ^ data]); 1507 } 1508 1509 #define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 1510 #define SIBA_OFFSET(offset) \ 1511 (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t)) 1512 #define SIBA_SHIFTOUT_SUB(__x, __mask) \ 1513 (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask)) 1514 #define SIBA_SHIFTOUT(_var, _offset, _mask) \ 1515 out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask)) 1516 #define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift) \ 1517 out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 | \ 1518 in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift)) 1519 1520 static void 1521 siba_sprom_r123(struct siba_sprom *out, const uint16_t *in) 1522 { 1523 int i; 1524 uint16_t v; 1525 int8_t gain; 1526 uint16_t loc[3]; 1527 1528 if (out->rev == 3) 1529 loc[0] = SIBA_SPROM3_MAC_80211BG; 1530 else { 1531 loc[0] = SIBA_SPROM1_MAC_80211BG; 1532 loc[1] = SIBA_SPROM1_MAC_ETH; 1533 loc[2] = SIBA_SPROM1_MAC_80211A; 1534 } 1535 for (i = 0; i < 3; i++) { 1536 v = in[SIBA_OFFSET(loc[0]) + i]; 1537 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1538 } 1539 if (out->rev < 3) { 1540 for (i = 0; i < 3; i++) { 1541 v = in[SIBA_OFFSET(loc[1]) + i]; 1542 *(((uint16_t *)out->mac_eth) + i) = htobe16(v); 1543 } 1544 for (i = 0; i < 3; i++) { 1545 v = in[SIBA_OFFSET(loc[2]) + i]; 1546 *(((uint16_t *)out->mac_80211a) + i) = htobe16(v); 1547 } 1548 } 1549 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY, 1550 SIBA_SPROM1_ETHPHY_MII_ETH0); 1551 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY, 1552 SIBA_SPROM1_ETHPHY_MII_ETH1); 1553 SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY, 1554 SIBA_SPROM1_ETHPHY_MDIO_ETH0); 1555 SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY, 1556 SIBA_SPROM1_ETHPHY_MDIO_ETH1); 1557 SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV); 1558 SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO, 1559 SIBA_SPROM1_BOARDINFO_CCODE); 1560 SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA); 1561 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO, 1562 SIBA_SPROM1_BOARDINFO_ANTBG); 1563 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff); 1564 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff); 1565 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff); 1566 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff); 1567 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff); 1568 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff); 1569 SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0); 1570 SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1); 1571 SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2); 1572 SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3); 1573 1574 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A); 1575 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG); 1576 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A); 1577 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG); 1578 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff); 1579 if (out->rev >= 2) 1580 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff); 1581 1582 /* antenna gain */ 1583 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0); 1584 out->again.ghz24.a0 = out->again.ghz24.a1 = gain; 1585 out->again.ghz24.a2 = out->again.ghz24.a3 = gain; 1586 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8); 1587 out->again.ghz5.a0 = out->again.ghz5.a1 = gain; 1588 out->again.ghz5.a2 = out->again.ghz5.a3 = gain; 1589 } 1590 1591 static void 1592 siba_sprom_r458(struct siba_sprom *out, const uint16_t *in) 1593 { 1594 1595 SIBA_SHIFTOUT(txpid2g[0], SIBA_SPROM4_TXPID2G01, 1596 SIBA_SPROM4_TXPID2G0); 1597 SIBA_SHIFTOUT(txpid2g[1], SIBA_SPROM4_TXPID2G01, 1598 SIBA_SPROM4_TXPID2G1); 1599 SIBA_SHIFTOUT(txpid2g[2], SIBA_SPROM4_TXPID2G23, 1600 SIBA_SPROM4_TXPID2G2); 1601 SIBA_SHIFTOUT(txpid2g[3], SIBA_SPROM4_TXPID2G23, 1602 SIBA_SPROM4_TXPID2G3); 1603 1604 SIBA_SHIFTOUT(txpid5gl[0], SIBA_SPROM4_TXPID5GL01, 1605 SIBA_SPROM4_TXPID5GL0); 1606 SIBA_SHIFTOUT(txpid5gl[1], SIBA_SPROM4_TXPID5GL01, 1607 SIBA_SPROM4_TXPID5GL1); 1608 SIBA_SHIFTOUT(txpid5gl[2], SIBA_SPROM4_TXPID5GL23, 1609 SIBA_SPROM4_TXPID5GL2); 1610 SIBA_SHIFTOUT(txpid5gl[3], SIBA_SPROM4_TXPID5GL23, 1611 SIBA_SPROM4_TXPID5GL3); 1612 1613 SIBA_SHIFTOUT(txpid5g[0], SIBA_SPROM4_TXPID5G01, 1614 SIBA_SPROM4_TXPID5G0); 1615 SIBA_SHIFTOUT(txpid5g[1], SIBA_SPROM4_TXPID5G01, 1616 SIBA_SPROM4_TXPID5G1); 1617 SIBA_SHIFTOUT(txpid5g[2], SIBA_SPROM4_TXPID5G23, 1618 SIBA_SPROM4_TXPID5G2); 1619 SIBA_SHIFTOUT(txpid5g[3], SIBA_SPROM4_TXPID5G23, 1620 SIBA_SPROM4_TXPID5G3); 1621 1622 SIBA_SHIFTOUT(txpid5gh[0], SIBA_SPROM4_TXPID5GH01, 1623 SIBA_SPROM4_TXPID5GH0); 1624 SIBA_SHIFTOUT(txpid5gh[1], SIBA_SPROM4_TXPID5GH01, 1625 SIBA_SPROM4_TXPID5GH1); 1626 SIBA_SHIFTOUT(txpid5gh[2], SIBA_SPROM4_TXPID5GH23, 1627 SIBA_SPROM4_TXPID5GH2); 1628 SIBA_SHIFTOUT(txpid5gh[3], SIBA_SPROM4_TXPID5GH23, 1629 SIBA_SPROM4_TXPID5GH3); 1630 } 1631 1632 static void 1633 siba_sprom_r45(struct siba_sprom *out, const uint16_t *in) 1634 { 1635 int i; 1636 uint16_t v; 1637 uint16_t mac_80211bg_offset; 1638 const uint16_t pwr_info_offset[] = { 1639 SIBA_SPROM4_PWR_INFO_CORE0, SIBA_SPROM4_PWR_INFO_CORE1, 1640 SIBA_SPROM4_PWR_INFO_CORE2, SIBA_SPROM4_PWR_INFO_CORE3 1641 }; 1642 1643 if (out->rev == 4) 1644 mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG; 1645 else 1646 mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG; 1647 for (i = 0; i < 3; i++) { 1648 v = in[SIBA_OFFSET(mac_80211bg_offset) + i]; 1649 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1650 } 1651 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A); 1652 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A); 1653 if (out->rev == 4) { 1654 SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff); 1655 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff); 1656 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff); 1657 } else { 1658 SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff); 1659 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff); 1660 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff); 1661 } 1662 SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A); 1663 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG); 1664 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK); 1665 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG); 1666 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK); 1667 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A); 1668 if (out->rev == 4) { 1669 SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0); 1670 SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1); 1671 SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2); 1672 SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3); 1673 } else { 1674 SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0); 1675 SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1); 1676 SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2); 1677 SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3); 1678 } 1679 1680 /* antenna gain */ 1681 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0); 1682 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1); 1683 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2); 1684 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3); 1685 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); 1686 1687 /* Extract core power info */ 1688 for (i = 0; i < nitems(pwr_info_offset); i++) { 1689 uint16_t o = pwr_info_offset[i]; 1690 1691 SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, 1692 SIBA_SPROM4_2G_ITSSI); 1693 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, 1694 SIBA_SPROM4_2G_MAXP); 1695 1696 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SPROM4_2G_PA_0, ~0); 1697 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SPROM4_2G_PA_1, ~0); 1698 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SPROM4_2G_PA_2, ~0); 1699 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[3], o + SIBA_SPROM4_2G_PA_3, ~0); 1700 1701 SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, 1702 SIBA_SPROM4_5G_ITSSI); 1703 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, 1704 SIBA_SPROM4_5G_MAXP); 1705 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM4_5GHL_MAXP, 1706 SIBA_SPROM4_5GH_MAXP); 1707 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM4_5GHL_MAXP, 1708 SIBA_SPROM4_5GL_MAXP); 1709 1710 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SPROM4_5GL_PA_0, ~0); 1711 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SPROM4_5GL_PA_1, ~0); 1712 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SPROM4_5GL_PA_2, ~0); 1713 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[3], o + SIBA_SPROM4_5GL_PA_3, ~0); 1714 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SPROM4_5G_PA_0, ~0); 1715 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SPROM4_5G_PA_1, ~0); 1716 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SPROM4_5G_PA_2, ~0); 1717 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[3], o + SIBA_SPROM4_5G_PA_3, ~0); 1718 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SPROM4_5GH_PA_0, ~0); 1719 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SPROM4_5GH_PA_1, ~0); 1720 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SPROM4_5GH_PA_2, ~0); 1721 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[3], o + SIBA_SPROM4_5GH_PA_3, ~0); 1722 } 1723 1724 siba_sprom_r458(out, in); 1725 } 1726 1727 static void 1728 siba_sprom_r8(struct siba_sprom *out, const uint16_t *in) 1729 { 1730 int i; 1731 uint16_t v; 1732 uint16_t pwr_info_offset[] = { 1733 SIBA_SROM8_PWR_INFO_CORE0, SIBA_SROM8_PWR_INFO_CORE1, 1734 SIBA_SROM8_PWR_INFO_CORE2, SIBA_SROM8_PWR_INFO_CORE3 1735 }; 1736 1737 for (i = 0; i < 3; i++) { 1738 v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i]; 1739 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1740 } 1741 SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff); 1742 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff); 1743 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff); 1744 SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff); 1745 SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff); 1746 SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A); 1747 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG); 1748 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK); 1749 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG); 1750 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK); 1751 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A); 1752 SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL, 1753 SIBA_SPROM8_MAXP_AH_MASK); 1754 SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL, 1755 SIBA_SPROM8_MAXP_AL_MASK); 1756 SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0); 1757 SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1); 1758 SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2); 1759 SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3); 1760 SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G); 1761 SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G); 1762 SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL); 1763 SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH); 1764 SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G); 1765 SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G); 1766 1767 SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G); 1768 SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G); 1769 SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G); 1770 SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G); 1771 SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G); 1772 SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G); 1773 SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G); 1774 SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G); 1775 1776 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff); 1777 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff); 1778 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff); 1779 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff); 1780 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff); 1781 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff); 1782 SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff); 1783 SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff); 1784 SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff); 1785 SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff); 1786 SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff); 1787 SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff); 1788 SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff); 1789 1790 SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0); 1791 SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0); 1792 SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0); 1793 SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0); 1794 1795 /* antenna gain */ 1796 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0); 1797 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1); 1798 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2); 1799 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3); 1800 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); 1801 1802 /* FEM */ 1803 SIBA_SHIFTOUT(fem.ghz2.tssipos, SIBA_SPROM8_FEM2G, 1804 SSB_SROM8_FEM_TSSIPOS); 1805 SIBA_SHIFTOUT(fem.ghz2.extpa_gain, SIBA_SPROM8_FEM2G, 1806 SSB_SROM8_FEM_EXTPA_GAIN); 1807 SIBA_SHIFTOUT(fem.ghz2.pdet_range, SIBA_SPROM8_FEM2G, 1808 SSB_SROM8_FEM_PDET_RANGE); 1809 SIBA_SHIFTOUT(fem.ghz2.tr_iso, SIBA_SPROM8_FEM2G, 1810 SSB_SROM8_FEM_TR_ISO); 1811 SIBA_SHIFTOUT(fem.ghz2.antswlut, SIBA_SPROM8_FEM2G, 1812 SSB_SROM8_FEM_ANTSWLUT); 1813 1814 SIBA_SHIFTOUT(fem.ghz5.tssipos, SIBA_SPROM8_FEM5G, 1815 SSB_SROM8_FEM_TSSIPOS); 1816 SIBA_SHIFTOUT(fem.ghz5.extpa_gain, SIBA_SPROM8_FEM5G, 1817 SSB_SROM8_FEM_EXTPA_GAIN); 1818 SIBA_SHIFTOUT(fem.ghz5.pdet_range, SIBA_SPROM8_FEM5G, 1819 SSB_SROM8_FEM_PDET_RANGE); 1820 SIBA_SHIFTOUT(fem.ghz5.tr_iso, SIBA_SPROM8_FEM5G, 1821 SSB_SROM8_FEM_TR_ISO); 1822 SIBA_SHIFTOUT(fem.ghz5.antswlut, SIBA_SPROM8_FEM5G, 1823 SSB_SROM8_FEM_ANTSWLUT); 1824 1825 /* Extract cores power info info */ 1826 for (i = 0; i < nitems(pwr_info_offset); i++) { 1827 uint16_t o = pwr_info_offset[i]; 1828 SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, 1829 SIBA_SPROM8_2G_ITSSI); 1830 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, 1831 SIBA_SPROM8_2G_MAXP); 1832 1833 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SROM8_2G_PA_0, ~0); 1834 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SROM8_2G_PA_1, ~0); 1835 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SROM8_2G_PA_2, ~0); 1836 1837 SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, 1838 SIBA_SPROM8_5G_ITSSI); 1839 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, 1840 SIBA_SPROM8_5G_MAXP); 1841 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM8_5GHL_MAXP, 1842 SIBA_SPROM8_5GH_MAXP); 1843 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM8_5GHL_MAXP, 1844 SIBA_SPROM8_5GL_MAXP); 1845 1846 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SROM8_5GL_PA_0, ~0); 1847 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SROM8_5GL_PA_1, ~0); 1848 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SROM8_5GL_PA_2, ~0); 1849 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SROM8_5G_PA_0, ~0); 1850 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SROM8_5G_PA_1, ~0); 1851 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SROM8_5G_PA_2, ~0); 1852 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SROM8_5GH_PA_0, ~0); 1853 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SROM8_5GH_PA_1, ~0); 1854 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SROM8_5GH_PA_2, ~0); 1855 } 1856 1857 SIBA_SHIFTOUT(cddpo, SIBA_SPROM8_CDDPO, ~0); 1858 SIBA_SHIFTOUT(stbcpo, SIBA_SPROM8_STBCPO, ~0); 1859 1860 siba_sprom_r458(out, in); 1861 } 1862 1863 static int8_t 1864 siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in, 1865 uint16_t mask, uint16_t shift) 1866 { 1867 uint16_t v; 1868 uint8_t gain; 1869 1870 v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)]; 1871 gain = (v & mask) >> shift; 1872 gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 : 1873 ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2); 1874 1875 return ((int8_t)gain); 1876 } 1877 1878 #undef SIBA_LOWEST_SET_BIT 1879 #undef SIBA_OFFSET 1880 #undef SIBA_SHIFTOUT_SUB 1881 #undef SIBA_SHIFTOUT 1882 1883 int 1884 siba_powerdown(device_t dev) 1885 { 1886 struct siba_dev_softc *sd = device_get_ivars(dev); 1887 struct siba_softc *siba = sd->sd_bus; 1888 1889 return (siba_powerdown_sub(siba)); 1890 } 1891 1892 static int 1893 siba_powerdown_sub(struct siba_softc *siba) 1894 { 1895 struct siba_cc *scc; 1896 1897 if (siba->siba_type == SIBA_TYPE_SSB) 1898 return (0); 1899 1900 scc = &siba->siba_cc; 1901 if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5) 1902 return (0); 1903 siba_cc_clock(scc, SIBA_CLOCK_SLOW); 1904 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); 1905 return (0); 1906 } 1907 1908 static void 1909 siba_pcicore_init(struct siba_pci *spc) 1910 { 1911 struct siba_dev_softc *sd = spc->spc_dev; 1912 1913 if (sd == NULL) 1914 return; 1915 1916 if (!siba_dev_isup_sub(sd)) 1917 siba_dev_up_sub(sd, 0); 1918 1919 KASSERT(spc->spc_hostmode == 0, 1920 ("%s:%d: hostmode", __func__, __LINE__)); 1921 /* disable PCI interrupt */ 1922 siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0); 1923 } 1924 1925 int 1926 siba_dev_isup(device_t dev) 1927 { 1928 struct siba_dev_softc *sd = device_get_ivars(dev); 1929 1930 return (siba_dev_isup_sub(sd)); 1931 } 1932 1933 static int 1934 siba_dev_isup_sub(struct siba_dev_softc *sd) 1935 { 1936 uint32_t reject, val; 1937 1938 reject = siba_tmslow_reject_bitmask(sd); 1939 val = siba_read_4_sub(sd, SIBA_TGSLOW); 1940 val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject; 1941 1942 return (val == SIBA_TGSLOW_CLOCK); 1943 } 1944 1945 void 1946 siba_dev_up(device_t dev, uint32_t flags) 1947 { 1948 struct siba_dev_softc *sd = device_get_ivars(dev); 1949 1950 siba_dev_up_sub(sd, flags); 1951 } 1952 1953 static void 1954 siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags) 1955 { 1956 uint32_t val; 1957 1958 siba_dev_down_sub(sd, flags); 1959 siba_write_4_sub(sd, SIBA_TGSLOW, 1960 SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); 1961 siba_read_4_sub(sd, SIBA_TGSLOW); 1962 DELAY(1); 1963 1964 if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR) 1965 siba_write_4_sub(sd, SIBA_TGSHIGH, 0); 1966 1967 val = siba_read_4_sub(sd, SIBA_IAS); 1968 if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) { 1969 val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT); 1970 siba_write_4_sub(sd, SIBA_IAS, val); 1971 } 1972 1973 siba_write_4_sub(sd, SIBA_TGSLOW, 1974 SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); 1975 siba_read_4_sub(sd, SIBA_TGSLOW); 1976 DELAY(1); 1977 1978 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags); 1979 siba_read_4_sub(sd, SIBA_TGSLOW); 1980 DELAY(1); 1981 } 1982 1983 static uint32_t 1984 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd) 1985 { 1986 uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV; 1987 1988 switch (rev) { 1989 case SIBA_IDLOW_SSBREV_22: 1990 return (SIBA_TGSLOW_REJECT_22); 1991 case SIBA_IDLOW_SSBREV_23: 1992 return (SIBA_TGSLOW_REJECT_23); 1993 case SIBA_IDLOW_SSBREV_24: 1994 case SIBA_IDLOW_SSBREV_25: 1995 case SIBA_IDLOW_SSBREV_26: 1996 case SIBA_IDLOW_SSBREV_27: 1997 return (SIBA_TGSLOW_REJECT_23); 1998 default: 1999 KASSERT(0 == 1, 2000 ("%s:%d: unknown backplane rev %#x\n", 2001 __func__, __LINE__, rev)); 2002 } 2003 return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23); 2004 } 2005 2006 void 2007 siba_dev_down(device_t dev, uint32_t flags) 2008 { 2009 struct siba_dev_softc *sd = device_get_ivars(dev); 2010 2011 siba_dev_down_sub(sd, flags); 2012 } 2013 2014 static void 2015 siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags) 2016 { 2017 struct siba_softc *siba = sd->sd_bus; 2018 uint32_t reject, val; 2019 int i; 2020 2021 if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET) 2022 return; 2023 2024 reject = siba_tmslow_reject_bitmask(sd); 2025 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK); 2026 2027 for (i = 0; i < 1000; i++) { 2028 val = siba_read_4_sub(sd, SIBA_TGSLOW); 2029 if (val & reject) 2030 break; 2031 DELAY(10); 2032 } 2033 if ((val & reject) == 0) { 2034 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", 2035 reject, SIBA_TGSLOW); 2036 } 2037 for (i = 0; i < 1000; i++) { 2038 val = siba_read_4_sub(sd, SIBA_TGSHIGH); 2039 if (!(val & SIBA_TGSHIGH_BUSY)) 2040 break; 2041 DELAY(10); 2042 } 2043 if ((val & SIBA_TGSHIGH_BUSY) != 0) { 2044 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", 2045 SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH); 2046 } 2047 2048 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK | 2049 reject | SIBA_TGSLOW_RESET | flags); 2050 siba_read_4_sub(sd, SIBA_TGSLOW); 2051 DELAY(1); 2052 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags); 2053 siba_read_4_sub(sd, SIBA_TGSLOW); 2054 DELAY(1); 2055 } 2056 2057 static void 2058 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd) 2059 { 2060 struct siba_dev_softc *psd = spc->spc_dev; 2061 struct siba_softc *siba = psd->sd_bus; 2062 uint32_t tmp; 2063 2064 if (psd->sd_id.sd_device == SIBA_DEVID_PCI) { 2065 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, 2066 siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) | 2067 SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST); 2068 2069 if (psd->sd_id.sd_rev < 5) { 2070 tmp = siba_read_4_sub(psd, SIBA_IMCFGLO); 2071 tmp &= ~SIBA_IMCFGLO_SERTO; 2072 tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO; 2073 tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */; 2074 siba_write_4_sub(psd, SIBA_IMCFGLO, tmp); 2075 2076 /* broadcast value */ 2077 sd = (siba->siba_cc.scc_dev != NULL) ? 2078 siba->siba_cc.scc_dev : siba->siba_pci.spc_dev; 2079 if (sd != NULL) { 2080 siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR, 2081 0xfd8); 2082 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR); 2083 siba_write_4_sub(sd, 2084 SIBA_PCICORE_BCAST_DATA, 0); 2085 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA); 2086 } 2087 } else if (psd->sd_id.sd_rev >= 11) { 2088 tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2); 2089 tmp |= SIBA_PCICORE_SBTOPCI_MRM; 2090 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp); 2091 } 2092 } else { 2093 KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE")); 2094 if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1)) 2095 siba_pcie_write(spc, 0x4, 2096 siba_pcie_read(spc, 0x4) | 0x8); 2097 if (psd->sd_id.sd_rev == 0) { 2098 siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */ 2099 siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */ 2100 siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */ 2101 } else if (psd->sd_id.sd_rev == 1) 2102 siba_pcie_write(spc, 0x100, 2103 siba_pcie_read(spc, 0x100) | 0x40); 2104 } 2105 spc->spc_inited = 1; 2106 } 2107 2108 void 2109 siba_pcicore_intr(device_t dev) 2110 { 2111 struct siba_dev_softc *sd = device_get_ivars(dev); 2112 struct siba_softc *siba = sd->sd_bus; 2113 struct siba_pci *spc = &siba->siba_pci; 2114 struct siba_dev_softc *psd = spc->spc_dev; 2115 uint32_t tmp; 2116 2117 if (siba->siba_type != SIBA_TYPE_PCI || !psd) 2118 return; 2119 2120 KASSERT(siba == psd->sd_bus, ("different pointers")); 2121 2122 /* enable interrupts */ 2123 if (siba->siba_dev != NULL && 2124 (psd->sd_id.sd_rev >= 6 || 2125 psd->sd_id.sd_device == SIBA_DEVID_PCIE)) { 2126 tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4); 2127 tmp |= (1 << sd->sd_coreidx) << 8; 2128 pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4); 2129 } else { 2130 tmp = siba_read_4_sub(sd, SIBA_TPS); 2131 tmp &= SIBA_TPS_BPFLAG; 2132 siba_write_4_sub(psd, SIBA_INTR_MASK, 2133 siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp)); 2134 } 2135 2136 /* setup PCIcore */ 2137 if (spc->spc_inited == 0) 2138 siba_pcicore_setup(spc, sd); 2139 } 2140 2141 static uint32_t 2142 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset) 2143 { 2144 2145 return (siba_read_4_sub(spc->spc_dev, offset)); 2146 } 2147 2148 static void 2149 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value) 2150 { 2151 2152 siba_write_4_sub(spc->spc_dev, offset, value); 2153 } 2154 2155 static uint32_t 2156 siba_pcie_read(struct siba_pci *spc, uint32_t address) 2157 { 2158 2159 siba_pcicore_write_4(spc, 0x130, address); 2160 return (siba_pcicore_read_4(spc, 0x134)); 2161 } 2162 2163 static void 2164 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data) 2165 { 2166 2167 siba_pcicore_write_4(spc, 0x130, address); 2168 siba_pcicore_write_4(spc, 0x134, data); 2169 } 2170 2171 static void 2172 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address, 2173 uint16_t data) 2174 { 2175 int i; 2176 2177 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2); 2178 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA, 2179 (1 << 30) | (1 << 28) | 2180 ((uint32_t)device << 22) | ((uint32_t)address << 18) | 2181 (1 << 17) | data); 2182 DELAY(10); 2183 for (i = 0; i < 10; i++) { 2184 if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100) 2185 break; 2186 DELAY(1000); 2187 } 2188 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0); 2189 } 2190 2191 uint32_t 2192 siba_dma_translation(device_t dev) 2193 { 2194 #ifdef INVARIANTS 2195 struct siba_dev_softc *sd = device_get_ivars(dev); 2196 struct siba_softc *siba = sd->sd_bus; 2197 2198 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 2199 ("unsupported bustype %d\n", siba->siba_type)); 2200 #endif 2201 return (SIBA_PCI_DMA); 2202 } 2203 2204 void 2205 siba_barrier(device_t dev, int flags) 2206 { 2207 struct siba_dev_softc *sd = device_get_ivars(dev); 2208 struct siba_softc *siba = sd->sd_bus; 2209 2210 SIBA_BARRIER(siba, flags); 2211 } 2212 2213 static void 2214 siba_cc_suspend(struct siba_cc *scc) 2215 { 2216 2217 siba_cc_clock(scc, SIBA_CLOCK_SLOW); 2218 } 2219 2220 static void 2221 siba_cc_resume(struct siba_cc *scc) 2222 { 2223 2224 siba_cc_power_init(scc); 2225 siba_cc_clock(scc, SIBA_CLOCK_FAST); 2226 } 2227 2228 int 2229 siba_core_suspend(struct siba_softc *siba) 2230 { 2231 2232 siba_cc_suspend(&siba->siba_cc); 2233 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); 2234 return (0); 2235 } 2236 2237 int 2238 siba_core_resume(struct siba_softc *siba) 2239 { 2240 2241 siba->siba_pci.spc_inited = 0; 2242 siba->siba_curdev = NULL; 2243 2244 siba_powerup_sub(siba, 0); 2245 /* XXX setup H/W for PCMCIA??? */ 2246 siba_cc_resume(&siba->siba_cc); 2247 siba_powerdown_sub(siba); 2248 2249 return (0); 2250 } 2251 2252 static void 2253 siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask, 2254 uint32_t set) 2255 { 2256 2257 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); 2258 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset); 2259 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); 2260 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA, 2261 (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set); 2262 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA); 2263 } 2264 2265 void 2266 siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt) 2267 { 2268 struct siba_dev_softc *sd = device_get_ivars(dev); 2269 struct siba_softc *siba = sd->sd_bus; 2270 struct siba_cc *scc = &siba->siba_cc; 2271 uint32_t *p = NULL, info[5][3] = { 2272 { 2, 25, 0xf }, 2273 { 3, 1, 0xf }, 2274 { 3, 9, 0xf }, 2275 { 3, 17, 0x3f }, 2276 { 0, 21, 0x3f } 2277 }; 2278 2279 if (siba->siba_chipid == 0x4312) { 2280 if (id != SIBA_LDO_PAREF) 2281 return; 2282 p = info[4]; 2283 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), 2284 (volt & p[2]) << p[1]); 2285 return; 2286 } 2287 if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) { 2288 switch (id) { 2289 case SIBA_LDO_PAREF: 2290 p = info[3]; 2291 break; 2292 case SIBA_LDO_VOLT1: 2293 p = info[0]; 2294 break; 2295 case SIBA_LDO_VOLT2: 2296 p = info[1]; 2297 break; 2298 case SIBA_LDO_VOLT3: 2299 p = info[2]; 2300 break; 2301 default: 2302 KASSERT(0 == 1, 2303 ("%s: unsupported voltage ID %#x", __func__, id)); 2304 return; 2305 } 2306 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), 2307 (volt & p[2]) << p[1]); 2308 } 2309 } 2310 2311 void 2312 siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on) 2313 { 2314 struct siba_dev_softc *sd = device_get_ivars(dev); 2315 struct siba_softc *siba = sd->sd_bus; 2316 struct siba_cc *scc = &siba->siba_cc; 2317 int ldo; 2318 2319 ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF : 2320 ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF : 2321 ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1))); 2322 if (ldo == -1) 2323 return; 2324 2325 if (on) 2326 SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo); 2327 else 2328 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo)); 2329 SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES); 2330 } 2331 2332 int 2333 siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result) 2334 { 2335 struct siba_dev_softc *sd = device_get_ivars(child); 2336 struct siba_softc *siba = sd->sd_bus; 2337 2338 switch (which) { 2339 case SIBA_SPROMVAR_REV: 2340 *result = siba->siba_sprom.rev; 2341 break; 2342 case SIBA_SPROMVAR_MAC_80211BG: 2343 *((uint8_t **) result) = siba->siba_sprom.mac_80211bg; 2344 break; 2345 case SIBA_SPROMVAR_MAC_ETH: 2346 *((uint8_t **) result) = siba->siba_sprom.mac_eth; 2347 break; 2348 case SIBA_SPROMVAR_MAC_80211A: 2349 *((uint8_t **) result) = siba->siba_sprom.mac_80211a; 2350 break; 2351 case SIBA_SPROMVAR_MII_ETH0: 2352 *result = siba->siba_sprom.mii_eth0; 2353 break; 2354 case SIBA_SPROMVAR_MII_ETH1: 2355 *result = siba->siba_sprom.mii_eth1; 2356 break; 2357 case SIBA_SPROMVAR_MDIO_ETH0: 2358 *result = siba->siba_sprom.mdio_eth0; 2359 break; 2360 case SIBA_SPROMVAR_MDIO_ETH1: 2361 *result = siba->siba_sprom.mdio_eth1; 2362 break; 2363 case SIBA_SPROMVAR_BREV: 2364 *result = siba->siba_sprom.brev; 2365 break; 2366 case SIBA_SPROMVAR_CCODE: 2367 *result = siba->siba_sprom.ccode; 2368 break; 2369 case SIBA_SPROMVAR_ANT_A: 2370 *result = siba->siba_sprom.ant_a; 2371 break; 2372 case SIBA_SPROMVAR_ANT_BG: 2373 *result = siba->siba_sprom.ant_bg; 2374 break; 2375 case SIBA_SPROMVAR_PA0B0: 2376 *result = siba->siba_sprom.pa0b0; 2377 break; 2378 case SIBA_SPROMVAR_PA0B1: 2379 *result = siba->siba_sprom.pa0b1; 2380 break; 2381 case SIBA_SPROMVAR_PA0B2: 2382 *result = siba->siba_sprom.pa0b2; 2383 break; 2384 case SIBA_SPROMVAR_PA1B0: 2385 *result = siba->siba_sprom.pa1b0; 2386 break; 2387 case SIBA_SPROMVAR_PA1B1: 2388 *result = siba->siba_sprom.pa1b1; 2389 break; 2390 case SIBA_SPROMVAR_PA1B2: 2391 *result = siba->siba_sprom.pa1b2; 2392 break; 2393 case SIBA_SPROMVAR_PA1LOB0: 2394 *result = siba->siba_sprom.pa1lob0; 2395 break; 2396 case SIBA_SPROMVAR_PA1LOB1: 2397 *result = siba->siba_sprom.pa1lob1; 2398 break; 2399 case SIBA_SPROMVAR_PA1LOB2: 2400 *result = siba->siba_sprom.pa1lob2; 2401 break; 2402 case SIBA_SPROMVAR_PA1HIB0: 2403 *result = siba->siba_sprom.pa1hib0; 2404 break; 2405 case SIBA_SPROMVAR_PA1HIB1: 2406 *result = siba->siba_sprom.pa1hib1; 2407 break; 2408 case SIBA_SPROMVAR_PA1HIB2: 2409 *result = siba->siba_sprom.pa1hib2; 2410 break; 2411 case SIBA_SPROMVAR_GPIO0: 2412 *result = siba->siba_sprom.gpio0; 2413 break; 2414 case SIBA_SPROMVAR_GPIO1: 2415 *result = siba->siba_sprom.gpio1; 2416 break; 2417 case SIBA_SPROMVAR_GPIO2: 2418 *result = siba->siba_sprom.gpio2; 2419 break; 2420 case SIBA_SPROMVAR_GPIO3: 2421 *result = siba->siba_sprom.gpio3; 2422 break; 2423 case SIBA_SPROMVAR_MAXPWR_AL: 2424 *result = siba->siba_sprom.maxpwr_al; 2425 break; 2426 case SIBA_SPROMVAR_MAXPWR_A: 2427 *result = siba->siba_sprom.maxpwr_a; 2428 break; 2429 case SIBA_SPROMVAR_MAXPWR_AH: 2430 *result = siba->siba_sprom.maxpwr_ah; 2431 break; 2432 case SIBA_SPROMVAR_MAXPWR_BG: 2433 *result = siba->siba_sprom.maxpwr_bg; 2434 break; 2435 case SIBA_SPROMVAR_RXPO2G: 2436 *result = siba->siba_sprom.rxpo2g; 2437 break; 2438 case SIBA_SPROMVAR_RXPO5G: 2439 *result = siba->siba_sprom.rxpo5g; 2440 break; 2441 case SIBA_SPROMVAR_TSSI_A: 2442 *result = siba->siba_sprom.tssi_a; 2443 break; 2444 case SIBA_SPROMVAR_TSSI_BG: 2445 *result = siba->siba_sprom.tssi_bg; 2446 break; 2447 case SIBA_SPROMVAR_TRI2G: 2448 *result = siba->siba_sprom.tri2g; 2449 break; 2450 case SIBA_SPROMVAR_TRI5GL: 2451 *result = siba->siba_sprom.tri5gl; 2452 break; 2453 case SIBA_SPROMVAR_TRI5G: 2454 *result = siba->siba_sprom.tri5g; 2455 break; 2456 case SIBA_SPROMVAR_TRI5GH: 2457 *result = siba->siba_sprom.tri5gh; 2458 break; 2459 case SIBA_SPROMVAR_RSSISAV2G: 2460 *result = siba->siba_sprom.rssisav2g; 2461 break; 2462 case SIBA_SPROMVAR_RSSISMC2G: 2463 *result = siba->siba_sprom.rssismc2g; 2464 break; 2465 case SIBA_SPROMVAR_RSSISMF2G: 2466 *result = siba->siba_sprom.rssismf2g; 2467 break; 2468 case SIBA_SPROMVAR_BXA2G: 2469 *result = siba->siba_sprom.bxa2g; 2470 break; 2471 case SIBA_SPROMVAR_RSSISAV5G: 2472 *result = siba->siba_sprom.rssisav5g; 2473 break; 2474 case SIBA_SPROMVAR_RSSISMC5G: 2475 *result = siba->siba_sprom.rssismc5g; 2476 break; 2477 case SIBA_SPROMVAR_RSSISMF5G: 2478 *result = siba->siba_sprom.rssismf5g; 2479 break; 2480 case SIBA_SPROMVAR_BXA5G: 2481 *result = siba->siba_sprom.bxa5g; 2482 break; 2483 case SIBA_SPROMVAR_CCK2GPO: 2484 *result = siba->siba_sprom.cck2gpo; 2485 break; 2486 case SIBA_SPROMVAR_OFDM2GPO: 2487 *result = siba->siba_sprom.ofdm2gpo; 2488 break; 2489 case SIBA_SPROMVAR_OFDM5GLPO: 2490 *result = siba->siba_sprom.ofdm5glpo; 2491 break; 2492 case SIBA_SPROMVAR_OFDM5GPO: 2493 *result = siba->siba_sprom.ofdm5gpo; 2494 break; 2495 case SIBA_SPROMVAR_OFDM5GHPO: 2496 *result = siba->siba_sprom.ofdm5ghpo; 2497 break; 2498 case SIBA_SPROMVAR_BF_LO: 2499 *result = siba->siba_sprom.bf_lo; 2500 break; 2501 case SIBA_SPROMVAR_BF_HI: 2502 *result = siba->siba_sprom.bf_hi; 2503 break; 2504 case SIBA_SPROMVAR_BF2_LO: 2505 *result = siba->siba_sprom.bf2_lo; 2506 break; 2507 case SIBA_SPROMVAR_BF2_HI: 2508 *result = siba->siba_sprom.bf2_hi; 2509 break; 2510 case SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS: 2511 *result = siba->siba_sprom.fem.ghz2.tssipos; 2512 break; 2513 case SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN: 2514 *result = siba->siba_sprom.fem.ghz2.extpa_gain; 2515 break; 2516 case SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE: 2517 *result = siba->siba_sprom.fem.ghz2.pdet_range; 2518 break; 2519 case SIBA_SPROMVAR_FEM_2GHZ_TR_ISO: 2520 *result = siba->siba_sprom.fem.ghz2.tr_iso; 2521 break; 2522 case SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT: 2523 *result = siba->siba_sprom.fem.ghz2.antswlut; 2524 break; 2525 case SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS: 2526 *result = siba->siba_sprom.fem.ghz5.tssipos; 2527 break; 2528 case SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN: 2529 *result = siba->siba_sprom.fem.ghz5.extpa_gain; 2530 break; 2531 case SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE: 2532 *result = siba->siba_sprom.fem.ghz5.pdet_range; 2533 break; 2534 case SIBA_SPROMVAR_FEM_5GHZ_TR_ISO: 2535 *result = siba->siba_sprom.fem.ghz5.tr_iso; 2536 break; 2537 case SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT: 2538 *result = siba->siba_sprom.fem.ghz5.antswlut; 2539 break; 2540 case SIBA_SPROMVAR_TXPID_2G_0: 2541 *result = siba->siba_sprom.txpid2g[0]; 2542 break; 2543 case SIBA_SPROMVAR_TXPID_2G_1: 2544 *result = siba->siba_sprom.txpid2g[1]; 2545 break; 2546 case SIBA_SPROMVAR_TXPID_2G_2: 2547 *result = siba->siba_sprom.txpid2g[2]; 2548 break; 2549 case SIBA_SPROMVAR_TXPID_2G_3: 2550 *result = siba->siba_sprom.txpid2g[3]; 2551 break; 2552 case SIBA_SPROMVAR_TXPID_5GL_0: 2553 *result = siba->siba_sprom.txpid5gl[0]; 2554 break; 2555 case SIBA_SPROMVAR_TXPID_5GL_1: 2556 *result = siba->siba_sprom.txpid5gl[1]; 2557 break; 2558 case SIBA_SPROMVAR_TXPID_5GL_2: 2559 *result = siba->siba_sprom.txpid5gl[2]; 2560 break; 2561 case SIBA_SPROMVAR_TXPID_5GL_3: 2562 *result = siba->siba_sprom.txpid5gl[3]; 2563 break; 2564 case SIBA_SPROMVAR_TXPID_5G_0: 2565 *result = siba->siba_sprom.txpid5g[0]; 2566 break; 2567 case SIBA_SPROMVAR_TXPID_5G_1: 2568 *result = siba->siba_sprom.txpid5g[1]; 2569 break; 2570 case SIBA_SPROMVAR_TXPID_5G_2: 2571 *result = siba->siba_sprom.txpid5g[2]; 2572 break; 2573 case SIBA_SPROMVAR_TXPID_5G_3: 2574 *result = siba->siba_sprom.txpid5g[3]; 2575 break; 2576 case SIBA_SPROMVAR_TXPID_5GH_0: 2577 *result = siba->siba_sprom.txpid5gh[0]; 2578 break; 2579 case SIBA_SPROMVAR_TXPID_5GH_1: 2580 *result = siba->siba_sprom.txpid5gh[1]; 2581 break; 2582 case SIBA_SPROMVAR_TXPID_5GH_2: 2583 *result = siba->siba_sprom.txpid5gh[2]; 2584 break; 2585 case SIBA_SPROMVAR_TXPID_5GH_3: 2586 *result = siba->siba_sprom.txpid5gh[3]; 2587 break; 2588 case SIBA_SPROMVAR_STBCPO: 2589 *result = siba->siba_sprom.stbcpo; 2590 break; 2591 case SIBA_SPROMVAR_CDDPO: 2592 *result = siba->siba_sprom.cddpo; 2593 break; 2594 default: 2595 return (ENOENT); 2596 } 2597 return (0); 2598 } 2599 2600 int 2601 siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value) 2602 { 2603 struct siba_dev_softc *sd = device_get_ivars(child); 2604 struct siba_softc *siba = sd->sd_bus; 2605 2606 switch (which) { 2607 case SIBA_SPROMVAR_REV: 2608 siba->siba_sprom.rev = value; 2609 break; 2610 case SIBA_SPROMVAR_MII_ETH0: 2611 siba->siba_sprom.mii_eth0 = value; 2612 break; 2613 case SIBA_SPROMVAR_MII_ETH1: 2614 siba->siba_sprom.mii_eth1 = value; 2615 break; 2616 case SIBA_SPROMVAR_MDIO_ETH0: 2617 siba->siba_sprom.mdio_eth0 = value; 2618 break; 2619 case SIBA_SPROMVAR_MDIO_ETH1: 2620 siba->siba_sprom.mdio_eth1 = value; 2621 break; 2622 case SIBA_SPROMVAR_BREV: 2623 siba->siba_sprom.brev = value; 2624 break; 2625 case SIBA_SPROMVAR_CCODE: 2626 siba->siba_sprom.ccode = value; 2627 break; 2628 case SIBA_SPROMVAR_ANT_A: 2629 siba->siba_sprom.ant_a = value; 2630 break; 2631 case SIBA_SPROMVAR_ANT_BG: 2632 siba->siba_sprom.ant_bg = value; 2633 break; 2634 case SIBA_SPROMVAR_PA0B0: 2635 siba->siba_sprom.pa0b0 = value; 2636 break; 2637 case SIBA_SPROMVAR_PA0B1: 2638 siba->siba_sprom.pa0b1 = value; 2639 break; 2640 case SIBA_SPROMVAR_PA0B2: 2641 siba->siba_sprom.pa0b2 = value; 2642 break; 2643 case SIBA_SPROMVAR_PA1B0: 2644 siba->siba_sprom.pa1b0 = value; 2645 break; 2646 case SIBA_SPROMVAR_PA1B1: 2647 siba->siba_sprom.pa1b1 = value; 2648 break; 2649 case SIBA_SPROMVAR_PA1B2: 2650 siba->siba_sprom.pa1b2 = value; 2651 break; 2652 case SIBA_SPROMVAR_PA1LOB0: 2653 siba->siba_sprom.pa1lob0 = value; 2654 break; 2655 case SIBA_SPROMVAR_PA1LOB1: 2656 siba->siba_sprom.pa1lob1 = value; 2657 break; 2658 case SIBA_SPROMVAR_PA1LOB2: 2659 siba->siba_sprom.pa1lob2 = value; 2660 break; 2661 case SIBA_SPROMVAR_PA1HIB0: 2662 siba->siba_sprom.pa1hib0 = value; 2663 break; 2664 case SIBA_SPROMVAR_PA1HIB1: 2665 siba->siba_sprom.pa1hib1 = value; 2666 break; 2667 case SIBA_SPROMVAR_PA1HIB2: 2668 siba->siba_sprom.pa1hib2 = value; 2669 break; 2670 case SIBA_SPROMVAR_GPIO0: 2671 siba->siba_sprom.gpio0 = value; 2672 break; 2673 case SIBA_SPROMVAR_GPIO1: 2674 siba->siba_sprom.gpio1 = value; 2675 break; 2676 case SIBA_SPROMVAR_GPIO2: 2677 siba->siba_sprom.gpio2 = value; 2678 break; 2679 case SIBA_SPROMVAR_GPIO3: 2680 siba->siba_sprom.gpio3 = value; 2681 break; 2682 case SIBA_SPROMVAR_MAXPWR_AL: 2683 siba->siba_sprom.maxpwr_al = value; 2684 break; 2685 case SIBA_SPROMVAR_MAXPWR_A: 2686 siba->siba_sprom.maxpwr_a = value; 2687 break; 2688 case SIBA_SPROMVAR_MAXPWR_AH: 2689 siba->siba_sprom.maxpwr_ah = value; 2690 break; 2691 case SIBA_SPROMVAR_MAXPWR_BG: 2692 siba->siba_sprom.maxpwr_bg = value; 2693 break; 2694 case SIBA_SPROMVAR_RXPO2G: 2695 siba->siba_sprom.rxpo2g = value; 2696 break; 2697 case SIBA_SPROMVAR_RXPO5G: 2698 siba->siba_sprom.rxpo5g = value; 2699 break; 2700 case SIBA_SPROMVAR_TSSI_A: 2701 siba->siba_sprom.tssi_a = value; 2702 break; 2703 case SIBA_SPROMVAR_TSSI_BG: 2704 siba->siba_sprom.tssi_bg = value; 2705 break; 2706 case SIBA_SPROMVAR_TRI2G: 2707 siba->siba_sprom.tri2g = value; 2708 break; 2709 case SIBA_SPROMVAR_TRI5GL: 2710 siba->siba_sprom.tri5gl = value; 2711 break; 2712 case SIBA_SPROMVAR_TRI5G: 2713 siba->siba_sprom.tri5g = value; 2714 break; 2715 case SIBA_SPROMVAR_TRI5GH: 2716 siba->siba_sprom.tri5gh = value; 2717 break; 2718 case SIBA_SPROMVAR_RSSISAV2G: 2719 siba->siba_sprom.rssisav2g = value; 2720 break; 2721 case SIBA_SPROMVAR_RSSISMC2G: 2722 siba->siba_sprom.rssismc2g = value; 2723 break; 2724 case SIBA_SPROMVAR_RSSISMF2G: 2725 siba->siba_sprom.rssismf2g = value; 2726 break; 2727 case SIBA_SPROMVAR_BXA2G: 2728 siba->siba_sprom.bxa2g = value; 2729 break; 2730 case SIBA_SPROMVAR_RSSISAV5G: 2731 siba->siba_sprom.rssisav5g = value; 2732 break; 2733 case SIBA_SPROMVAR_RSSISMC5G: 2734 siba->siba_sprom.rssismc5g = value; 2735 break; 2736 case SIBA_SPROMVAR_RSSISMF5G: 2737 siba->siba_sprom.rssismf5g = value; 2738 break; 2739 case SIBA_SPROMVAR_BXA5G: 2740 siba->siba_sprom.bxa5g = value; 2741 break; 2742 case SIBA_SPROMVAR_CCK2GPO: 2743 siba->siba_sprom.cck2gpo = value; 2744 break; 2745 case SIBA_SPROMVAR_OFDM2GPO: 2746 siba->siba_sprom.ofdm2gpo = value; 2747 break; 2748 case SIBA_SPROMVAR_OFDM5GLPO: 2749 siba->siba_sprom.ofdm5glpo = value; 2750 break; 2751 case SIBA_SPROMVAR_OFDM5GPO: 2752 siba->siba_sprom.ofdm5gpo = value; 2753 break; 2754 case SIBA_SPROMVAR_OFDM5GHPO: 2755 siba->siba_sprom.ofdm5ghpo = value; 2756 break; 2757 case SIBA_SPROMVAR_BF_LO: 2758 siba->siba_sprom.bf_lo = value; 2759 break; 2760 case SIBA_SPROMVAR_BF_HI: 2761 siba->siba_sprom.bf_hi = value; 2762 break; 2763 case SIBA_SPROMVAR_BF2_LO: 2764 siba->siba_sprom.bf2_lo = value; 2765 break; 2766 case SIBA_SPROMVAR_BF2_HI: 2767 siba->siba_sprom.bf2_hi = value; 2768 break; 2769 default: 2770 return (ENOENT); 2771 } 2772 return (0); 2773 } 2774 2775 #define SIBA_GPIOCTL 0x06c 2776 2777 uint32_t 2778 siba_gpio_get(device_t dev) 2779 { 2780 struct siba_dev_softc *sd = device_get_ivars(dev); 2781 struct siba_softc *siba = sd->sd_bus; 2782 struct siba_dev_softc *gpiodev, *pcidev = NULL; 2783 2784 pcidev = siba->siba_pci.spc_dev; 2785 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; 2786 if (!gpiodev) 2787 return (-1); 2788 return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL)); 2789 } 2790 2791 void 2792 siba_gpio_set(device_t dev, uint32_t value) 2793 { 2794 struct siba_dev_softc *sd = device_get_ivars(dev); 2795 struct siba_softc *siba = sd->sd_bus; 2796 struct siba_dev_softc *gpiodev, *pcidev = NULL; 2797 2798 pcidev = siba->siba_pci.spc_dev; 2799 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; 2800 if (!gpiodev) 2801 return; 2802 siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value); 2803 } 2804 2805 void 2806 siba_fix_imcfglobug(device_t dev) 2807 { 2808 struct siba_dev_softc *sd = device_get_ivars(dev); 2809 struct siba_softc *siba = sd->sd_bus; 2810 uint32_t tmp; 2811 2812 if (siba->siba_pci.spc_dev == NULL) 2813 return; 2814 if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI || 2815 siba->siba_pci.spc_dev->sd_id.sd_rev > 5) 2816 return; 2817 2818 tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) & 2819 ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO); 2820 switch (siba->siba_type) { 2821 case SIBA_TYPE_PCI: 2822 case SIBA_TYPE_PCMCIA: 2823 tmp |= 0x32; 2824 break; 2825 case SIBA_TYPE_SSB: 2826 tmp |= 0x53; 2827 break; 2828 } 2829 siba_write_4_sub(sd, SIBA_IMCFGLO, tmp); 2830 } 2831 2832 int 2833 siba_sprom_get_core_power_info(device_t dev, int core, 2834 struct siba_sprom_core_pwr_info *c) 2835 { 2836 struct siba_dev_softc *sd = device_get_ivars(dev); 2837 struct siba_softc *siba = sd->sd_bus; 2838 2839 if (core < 0 || core > 3) { 2840 return (EINVAL); 2841 } 2842 memcpy(c, &siba->siba_sprom.core_pwr_info[core], sizeof(*c)); 2843 return (0); 2844 } 2845 2846 int 2847 siba_sprom_get_mcs2gpo(device_t dev, uint16_t *c) 2848 { 2849 struct siba_dev_softc *sd = device_get_ivars(dev); 2850 struct siba_softc *siba = sd->sd_bus; 2851 2852 memcpy(c, &siba->siba_sprom.mcs2gpo, sizeof(uint16_t) * 8); 2853 return (0); 2854 } 2855 2856 int 2857 siba_sprom_get_mcs5glpo(device_t dev, uint16_t *c) 2858 { 2859 struct siba_dev_softc *sd = device_get_ivars(dev); 2860 struct siba_softc *siba = sd->sd_bus; 2861 2862 memcpy(c, &siba->siba_sprom.mcs5glpo, sizeof(uint16_t) * 8); 2863 return (0); 2864 } 2865 2866 int 2867 siba_sprom_get_mcs5gpo(device_t dev, uint16_t *c) 2868 { 2869 struct siba_dev_softc *sd = device_get_ivars(dev); 2870 struct siba_softc *siba = sd->sd_bus; 2871 2872 memcpy(c, &siba->siba_sprom.mcs5gpo, sizeof(uint16_t) * 8); 2873 return (0); 2874 } 2875 2876 int 2877 siba_sprom_get_mcs5ghpo(device_t dev, uint16_t *c) 2878 { 2879 struct siba_dev_softc *sd = device_get_ivars(dev); 2880 struct siba_softc *siba = sd->sd_bus; 2881 2882 memcpy(c, &siba->siba_sprom.mcs5ghpo, sizeof(uint16_t) * 8); 2883 return (0); 2884 } 2885 2886 void 2887 siba_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid) 2888 { 2889 struct siba_dev_softc *sd = device_get_ivars(dev); 2890 struct siba_softc *siba = sd->sd_bus; 2891 struct siba_cc *scc; 2892 2893 scc = &siba->siba_cc; 2894 2895 if (scc->scc_dev == NULL) { 2896 device_printf(dev, "%s: called; no pmu\n", __func__); 2897 return; 2898 } 2899 2900 switch (siba_get_chipid(dev)) { 2901 case 0x4322: 2902 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100070); 2903 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x1014140a); 2904 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888854); 2905 if (spur_avoid == 1) 2906 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05201828); 2907 else 2908 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05001828); 2909 break; 2910 case 43222: 2911 if (spur_avoid == 1) { 2912 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11500008); 2913 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0C000C06); 2914 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x0F600a08); 2915 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000); 2916 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x2001E920); 2917 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888815); 2918 } else { 2919 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100008); 2920 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0c000c06); 2921 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x03000a08); 2922 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000); 2923 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x200005c0); 2924 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888855); 2925 } 2926 break; 2927 default: 2928 device_printf(dev, 2929 "%s: unknown spur avoidance settings for chip 0x%04x\n", 2930 __func__, 2931 siba_get_chipid(dev)); 2932 return; 2933 } 2934 2935 /* Both chips above use the same update */ 2936 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_PLL_UPD); 2937 } 2938 2939 void 2940 siba_cc_set32(device_t dev, uint32_t reg, uint32_t val) 2941 { 2942 struct siba_dev_softc *sd = device_get_ivars(dev); 2943 struct siba_softc *siba = sd->sd_bus; 2944 struct siba_cc *scc; 2945 2946 scc = &siba->siba_cc; 2947 2948 if (scc->scc_dev == NULL) { 2949 device_printf(dev, "%s: called; no pmu\n", __func__); 2950 return; 2951 } 2952 2953 SIBA_CC_SET32(scc, reg, val); 2954 } 2955 2956 void 2957 siba_cc_mask32(device_t dev, uint32_t reg, uint32_t mask) 2958 { 2959 struct siba_dev_softc *sd = device_get_ivars(dev); 2960 struct siba_softc *siba = sd->sd_bus; 2961 struct siba_cc *scc; 2962 2963 scc = &siba->siba_cc; 2964 2965 if (scc->scc_dev == NULL) { 2966 device_printf(dev, "%s: called; no pmu\n", __func__); 2967 return; 2968 } 2969 2970 SIBA_CC_MASK32(scc, reg, mask); 2971 } 2972 2973 uint32_t 2974 siba_cc_read32(device_t dev, uint32_t reg) 2975 { 2976 struct siba_dev_softc *sd = device_get_ivars(dev); 2977 struct siba_softc *siba = sd->sd_bus; 2978 struct siba_cc *scc; 2979 2980 scc = &siba->siba_cc; 2981 2982 if (scc->scc_dev == NULL) { 2983 device_printf(dev, "%s: called; no pmu\n", __func__); 2984 return 0xffffffff; 2985 } 2986 2987 return SIBA_CC_READ32(scc, reg); 2988 } 2989 2990 void 2991 siba_cc_write32(device_t dev, uint32_t reg, uint32_t val) 2992 { 2993 struct siba_dev_softc *sd = device_get_ivars(dev); 2994 struct siba_softc *siba = sd->sd_bus; 2995 struct siba_cc *scc; 2996 2997 scc = &siba->siba_cc; 2998 2999 if (scc->scc_dev == NULL) { 3000 device_printf(dev, "%s: called; no pmu\n", __func__); 3001 return; 3002 } 3003 3004 SIBA_CC_WRITE32(scc, reg, val); 3005 } 3006