1 /*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: head/sys/dev/siba/siba_core.c 299541 2016-05-12 16:14:16Z adrian $"); 32 33 /* 34 * the Sonics Silicon Backplane driver. 35 */ 36 37 #include "opt_siba.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/kernel.h> 44 #include <sys/endian.h> 45 #include <sys/errno.h> 46 #include <sys/lock.h> 47 #if !defined(__DragonFly__) 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #endif 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 55 #include <net/if.h> 56 #include <net/if_media.h> 57 #include <net/if_arp.h> 58 59 #if defined(__DragonFly__) 60 #include <bus/pci/pcivar.h> 61 #include <bus/pci/pcireg.h> 62 #else 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #endif 66 67 #if defined(__DragonFly__) 68 #include "siba_ids.h" 69 #include "sibareg.h" 70 #include "sibavar.h" 71 #else 72 #include <dev/siba/siba_ids.h> 73 #include <dev/siba/sibareg.h> 74 #include <dev/siba/sibavar.h> 75 #endif 76 77 enum { 78 SIBA_DEBUG_SCAN = 0x00000001, /* scan */ 79 SIBA_DEBUG_PMU = 0x00000002, /* PMU */ 80 SIBA_DEBUG_PLL = 0x00000004, /* PLL */ 81 SIBA_DEBUG_SWITCHCORE = 0x00000008, /* switching core */ 82 SIBA_DEBUG_SPROM = 0x00000010, /* SPROM */ 83 SIBA_DEBUG_CORE = 0x00000020, /* handling cores */ 84 SIBA_DEBUG_ANY = 0xffffffff 85 }; 86 87 #ifdef SIBA_DEBUG 88 #define DPRINTF(siba, m, ...) do { \ 89 if (siba->siba_debug & (m)) \ 90 device_printf(siba->siba_dev, __VA_ARGS__); \ 91 } while (0) 92 #else 93 #define DPRINTF(siba, m, ...) do { (void) siba; } while (0) 94 #endif 95 96 static void siba_pci_gpio(struct siba_softc *, uint32_t, int); 97 static void siba_scan(struct siba_softc *); 98 static int siba_switchcore(struct siba_softc *, uint8_t); 99 static int siba_pci_switchcore_sub(struct siba_softc *, uint8_t); 100 static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t); 101 static uint16_t siba_dev2chipid(struct siba_softc *); 102 static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t); 103 static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t); 104 static void siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t); 105 static void siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t); 106 static void siba_cc_clock(struct siba_cc *, 107 enum siba_clock); 108 static void siba_cc_pmu_init(struct siba_cc *); 109 static void siba_cc_power_init(struct siba_cc *); 110 static void siba_cc_powerup_delay(struct siba_cc *); 111 static int siba_cc_clockfreq(struct siba_cc *, int); 112 static void siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t); 113 static void siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t); 114 static enum siba_clksrc siba_cc_clksrc(struct siba_cc *); 115 static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t); 116 static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t); 117 static void siba_cc_pll_write(struct siba_cc *, uint32_t, 118 uint32_t); 119 static const struct siba_cc_pmu0_plltab * 120 siba_cc_pmu0_plltab_findentry(uint32_t); 121 static int siba_pci_sprom(struct siba_softc *, struct siba_sprom *); 122 static int siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t); 123 static int sprom_check_crc(const uint16_t *, size_t); 124 static uint8_t siba_crc8(uint8_t, uint8_t); 125 static void siba_sprom_r123(struct siba_sprom *, const uint16_t *); 126 static void siba_sprom_r45(struct siba_sprom *, const uint16_t *); 127 static void siba_sprom_r8(struct siba_sprom *, const uint16_t *); 128 static int8_t siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t, 129 uint16_t); 130 static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *); 131 static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t); 132 static void siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t); 133 static uint32_t siba_pcie_read(struct siba_pci *, uint32_t); 134 static void siba_pcie_write(struct siba_pci *, uint32_t, uint32_t); 135 static void siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t, 136 uint16_t); 137 static void siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t, 138 uint16_t); 139 static void siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t, 140 uint16_t); 141 static void siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t, 142 uint16_t); 143 static void siba_pci_write_multi_1(struct siba_dev_softc *, const void *, 144 size_t, uint16_t); 145 static void siba_pci_write_multi_2(struct siba_dev_softc *, const void *, 146 size_t, uint16_t); 147 static void siba_pci_write_multi_4(struct siba_dev_softc *, const void *, 148 size_t, uint16_t); 149 static const char *siba_core_name(uint16_t); 150 static void siba_pcicore_init(struct siba_pci *); 151 static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t); 152 static void siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t); 153 static void siba_powerup_sub(struct siba_softc *, int); 154 static int siba_powerdown_sub(struct siba_softc *); 155 static int siba_dev_isup_sub(struct siba_dev_softc *); 156 static void siba_dev_up_sub(struct siba_dev_softc *, uint32_t); 157 static void siba_dev_down_sub(struct siba_dev_softc *, uint32_t); 158 int siba_core_attach(struct siba_softc *); 159 int siba_core_detach(struct siba_softc *); 160 int siba_core_suspend(struct siba_softc *); 161 int siba_core_resume(struct siba_softc *); 162 uint8_t siba_getncores(device_t, uint16_t); 163 164 static const struct siba_bus_ops siba_pci_ops = { 165 .read_2 = siba_pci_read_2, 166 .read_4 = siba_pci_read_4, 167 .write_2 = siba_pci_write_2, 168 .write_4 = siba_pci_write_4, 169 .read_multi_1 = siba_pci_read_multi_1, 170 .read_multi_2 = siba_pci_read_multi_2, 171 .read_multi_4 = siba_pci_read_multi_4, 172 .write_multi_1 = siba_pci_write_multi_1, 173 .write_multi_2 = siba_pci_write_multi_2, 174 .write_multi_4 = siba_pci_write_multi_4, 175 }; 176 177 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] = 178 SIBA_CC_PMU_4325_RES_UPDOWN; 179 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] = 180 SIBA_CC_PMU_4325_RES_DEPEND; 181 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] = 182 SIBA_CC_PMU_4328_RES_UPDOWN; 183 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] = 184 SIBA_CC_PMU_4328_RES_DEPEND; 185 static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] = 186 SIBA_CC_PMU0_PLLTAB_ENTRY; 187 static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] = 188 SIBA_CC_PMU1_PLLTAB_ENTRY; 189 190 int 191 siba_core_attach(struct siba_softc *siba) 192 { 193 struct siba_cc *scc; 194 int error; 195 196 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 197 ("unsupported BUS type (%#x)", siba->siba_type)); 198 199 siba->siba_ops = &siba_pci_ops; 200 201 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); 202 siba_scan(siba); 203 204 /* XXX init PCI or PCMCIA host devices */ 205 206 siba_powerup_sub(siba, 0); 207 208 /* init ChipCommon */ 209 scc = &siba->siba_cc; 210 if (scc->scc_dev != NULL) { 211 siba_cc_pmu_init(scc); 212 siba_cc_power_init(scc); 213 siba_cc_clock(scc, SIBA_CLOCK_FAST); 214 siba_cc_powerup_delay(scc); 215 } 216 217 error = siba_pci_sprom(siba, &siba->siba_sprom); 218 if (error) { 219 siba_powerdown_sub(siba); 220 return (error); 221 } 222 223 siba_pcicore_init(&siba->siba_pci); 224 siba_powerdown_sub(siba); 225 226 return (bus_generic_attach(siba->siba_dev)); 227 } 228 229 int 230 siba_core_detach(struct siba_softc *siba) 231 { 232 /* detach & delete all children */ 233 device_delete_children(siba->siba_dev); 234 return (0); 235 } 236 237 static void 238 siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on) 239 { 240 uint32_t in, out; 241 uint16_t status; 242 243 if (siba->siba_type != SIBA_TYPE_PCI) 244 return; 245 246 out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4); 247 if (on == 0) { 248 if (what & SIBA_GPIO_PLL) 249 out |= SIBA_GPIO_PLL; 250 if (what & SIBA_GPIO_CRYSTAL) 251 out &= ~SIBA_GPIO_CRYSTAL; 252 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 253 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN, 254 pci_read_config(siba->siba_dev, 255 SIBA_GPIO_OUT_EN, 4) | what, 4); 256 return; 257 } 258 259 in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4); 260 if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) { 261 if (what & SIBA_GPIO_CRYSTAL) { 262 out |= SIBA_GPIO_CRYSTAL; 263 if (what & SIBA_GPIO_PLL) 264 out |= SIBA_GPIO_PLL; 265 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 266 pci_write_config(siba->siba_dev, 267 SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev, 268 SIBA_GPIO_OUT_EN, 4) | what, 4); 269 DELAY(1000); 270 } 271 if (what & SIBA_GPIO_PLL) { 272 out &= ~SIBA_GPIO_PLL; 273 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); 274 DELAY(5000); 275 } 276 } 277 278 status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2); 279 status &= ~PCIM_STATUS_STABORT; 280 pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2); 281 } 282 283 static void 284 siba_scan(struct siba_softc *siba) 285 { 286 struct siba_dev_softc *sd; 287 uint32_t idhi, tmp; 288 device_t child; 289 int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0, 290 n_pci = 0; 291 292 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 293 ("unsupported BUS type (%#x)", siba->siba_type)); 294 295 siba->siba_ndevs = 0; 296 error = siba_switchcore(siba, 0); /* need the first core */ 297 if (error) 298 return; 299 300 idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH); 301 if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) { 302 tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID); 303 siba->siba_chipid = SIBA_CC_ID(tmp); 304 siba->siba_chiprev = SIBA_CC_REV(tmp); 305 siba->siba_chippkg = SIBA_CC_PKG(tmp); 306 if (SIBA_IDHIGH_REV(idhi) >= 4) 307 siba->siba_ndevs = SIBA_CC_NCORES(tmp); 308 siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0, 309 SIBA_CC_CAPS); 310 } else { 311 if (siba->siba_type == SIBA_TYPE_PCI) { 312 siba->siba_chipid = siba_dev2chipid(siba); 313 siba->siba_chiprev = pci_read_config(siba->siba_dev, 314 PCIR_REVID, 2); 315 siba->siba_chippkg = 0; 316 } else { 317 siba->siba_chipid = 0x4710; 318 siba->siba_chiprev = 0; 319 siba->siba_chippkg = 0; 320 } 321 } 322 if (siba->siba_ndevs == 0) 323 siba->siba_ndevs = siba_getncores(siba->siba_dev, 324 siba->siba_chipid); 325 if (siba->siba_ndevs > SIBA_MAX_CORES) { 326 device_printf(siba->siba_dev, 327 "too many siba cores (max %d %d)\n", 328 SIBA_MAX_CORES, siba->siba_ndevs); 329 return; 330 } 331 332 /* looking basic information about each cores/devices */ 333 for (i = 0; i < siba->siba_ndevs; i++) { 334 error = siba_switchcore(siba, i); 335 if (error) 336 return; 337 sd = &(siba->siba_devs[dev_i]); 338 idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH); 339 sd->sd_bus = siba; 340 sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi); 341 sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi); 342 sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi); 343 sd->sd_ops = siba->siba_ops; 344 sd->sd_coreidx = i; 345 346 DPRINTF(siba, SIBA_DEBUG_SCAN, 347 "core %d (%s) found (cc %#xrev %#x vendor %#x)\n", 348 i, siba_core_name(sd->sd_id.sd_device), 349 sd->sd_id.sd_device, sd->sd_id.sd_rev, sd->sd_id.sd_vendor); 350 351 switch (sd->sd_id.sd_device) { 352 case SIBA_DEVID_CHIPCOMMON: 353 n_cc++; 354 if (n_cc > 1) { 355 device_printf(siba->siba_dev, 356 "warn: multiple ChipCommon\n"); 357 break; 358 } 359 siba->siba_cc.scc_dev = sd; 360 break; 361 case SIBA_DEVID_80211: 362 n_80211++; 363 if (n_80211 > 1) { 364 device_printf(siba->siba_dev, 365 "warn: multiple 802.11 core\n"); 366 continue; 367 } 368 break; 369 case SIBA_DEVID_PCI: 370 case SIBA_DEVID_PCIE: 371 n_pci++; 372 #if defined(__DragonFly__) 373 error = pci_find_extcap(siba->siba_dev, PCIY_EXPRESS, 374 &base); 375 #else 376 error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS, 377 &base); 378 #endif 379 is_pcie = (error == 0) ? 1 : 0; 380 381 if (n_pci > 1) { 382 device_printf(siba->siba_dev, 383 "warn: multiple PCI(E) cores\n"); 384 break; 385 } 386 if (sd->sd_id.sd_device == SIBA_DEVID_PCI && 387 is_pcie == 1) 388 continue; 389 if (sd->sd_id.sd_device == SIBA_DEVID_PCIE && 390 is_pcie == 0) 391 continue; 392 siba->siba_pci.spc_dev = sd; 393 break; 394 case SIBA_DEVID_MODEM: 395 case SIBA_DEVID_PCMCIA: 396 break; 397 default: 398 device_printf(siba->siba_dev, 399 "unsupported coreid (%s)\n", 400 siba_core_name(sd->sd_id.sd_device)); 401 break; 402 } 403 dev_i++; 404 405 child = device_add_child(siba->siba_dev, NULL, -1); 406 if (child == NULL) { 407 device_printf(siba->siba_dev, "child attach failed\n"); 408 continue; 409 } 410 411 device_set_ivars(child, sd); 412 } 413 siba->siba_ndevs = dev_i; 414 } 415 416 static int 417 siba_switchcore(struct siba_softc *siba, uint8_t idx) 418 { 419 420 switch (siba->siba_type) { 421 case SIBA_TYPE_PCI: 422 return (siba_pci_switchcore_sub(siba, idx)); 423 default: 424 KASSERT(0 == 1, 425 ("%s: unsupported bustype %#x", __func__, 426 siba->siba_type)); 427 } 428 return (0); 429 } 430 431 static int 432 siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx) 433 { 434 #define RETRY_MAX 50 435 int i; 436 uint32_t dir; 437 438 dir = SIBA_REGWIN(idx); 439 440 for (i = 0; i < RETRY_MAX; i++) { 441 pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4); 442 if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir) 443 return (0); 444 DELAY(10); 445 } 446 return (ENODEV); 447 #undef RETRY_MAX 448 } 449 450 static int 451 siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd) 452 { 453 int error; 454 455 DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n", 456 siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx); 457 458 error = siba_pci_switchcore_sub(siba, sd->sd_coreidx); 459 if (error == 0) 460 siba->siba_curdev = sd; 461 462 return (error); 463 } 464 465 static uint32_t 466 siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx, 467 uint16_t offset) 468 { 469 470 (void)coreidx; 471 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 472 ("unsupported BUS type (%#x)", siba->siba_type)); 473 474 return (SIBA_READ_4(siba, offset)); 475 } 476 477 static uint16_t 478 siba_dev2chipid(struct siba_softc *siba) 479 { 480 uint16_t chipid = 0; 481 482 switch (siba->siba_pci_did) { 483 case 0x4301: 484 chipid = 0x4301; 485 break; 486 case 0x4305: 487 case 0x4306: 488 case 0x4307: 489 chipid = 0x4307; 490 break; 491 case 0x4403: 492 chipid = 0x4402; 493 break; 494 case 0x4610: 495 case 0x4611: 496 case 0x4612: 497 case 0x4613: 498 case 0x4614: 499 case 0x4615: 500 chipid = 0x4610; 501 break; 502 case 0x4710: 503 case 0x4711: 504 case 0x4712: 505 case 0x4713: 506 case 0x4714: 507 case 0x4715: 508 chipid = 0x4710; 509 break; 510 case 0x4320: 511 case 0x4321: 512 case 0x4322: 513 case 0x4323: 514 case 0x4324: 515 case 0x4325: 516 chipid = 0x4309; 517 break; 518 case PCI_DEVICE_ID_BCM4401: 519 case PCI_DEVICE_ID_BCM4401B0: 520 case PCI_DEVICE_ID_BCM4401B1: 521 chipid = 0x4401; 522 break; 523 default: 524 device_printf(siba->siba_dev, "unknown PCI did (%d)\n", 525 siba->siba_pci_did); 526 } 527 528 return (chipid); 529 } 530 531 /* 532 * Earlier ChipCommon revisions have hardcoded number of cores 533 * present dependent on the ChipCommon ID. 534 */ 535 uint8_t 536 siba_getncores(device_t dev, uint16_t chipid) 537 { 538 switch (chipid) { 539 case 0x4401: 540 case 0x4402: 541 return (3); 542 case 0x4301: 543 case 0x4307: 544 return (5); 545 case 0x4306: 546 return (6); 547 case SIBA_CCID_SENTRY5: 548 return (7); 549 case 0x4310: 550 return (8); 551 case SIBA_CCID_BCM4710: 552 case 0x4610: 553 case SIBA_CCID_BCM4704: 554 return (9); 555 default: 556 device_printf(dev, "unknown the chipset ID %#x\n", chipid); 557 } 558 559 return (1); 560 } 561 562 static const char * 563 siba_core_name(uint16_t coreid) 564 { 565 566 switch (coreid) { 567 case SIBA_DEVID_CHIPCOMMON: 568 return ("ChipCommon"); 569 case SIBA_DEVID_ILINE20: 570 return ("ILine 20"); 571 case SIBA_DEVID_SDRAM: 572 return ("SDRAM"); 573 case SIBA_DEVID_PCI: 574 return ("PCI"); 575 case SIBA_DEVID_MIPS: 576 return ("MIPS"); 577 case SIBA_DEVID_ETHERNET: 578 return ("Fast Ethernet"); 579 case SIBA_DEVID_MODEM: 580 return ("Modem"); 581 case SIBA_DEVID_USB11_HOSTDEV: 582 return ("USB 1.1 Hostdev"); 583 case SIBA_DEVID_ADSL: 584 return ("ADSL"); 585 case SIBA_DEVID_ILINE100: 586 return ("ILine 100"); 587 case SIBA_DEVID_IPSEC: 588 return ("IPSEC"); 589 case SIBA_DEVID_PCMCIA: 590 return ("PCMCIA"); 591 case SIBA_DEVID_INTERNAL_MEM: 592 return ("Internal Memory"); 593 case SIBA_DEVID_SDRAMDDR: 594 return ("MEMC SDRAM"); 595 case SIBA_DEVID_EXTIF: 596 return ("EXTIF"); 597 case SIBA_DEVID_80211: 598 return ("IEEE 802.11"); 599 case SIBA_DEVID_MIPS_3302: 600 return ("MIPS 3302"); 601 case SIBA_DEVID_USB11_HOST: 602 return ("USB 1.1 Host"); 603 case SIBA_DEVID_USB11_DEV: 604 return ("USB 1.1 Device"); 605 case SIBA_DEVID_USB20_HOST: 606 return ("USB 2.0 Host"); 607 case SIBA_DEVID_USB20_DEV: 608 return ("USB 2.0 Device"); 609 case SIBA_DEVID_SDIO_HOST: 610 return ("SDIO Host"); 611 case SIBA_DEVID_ROBOSWITCH: 612 return ("Roboswitch"); 613 case SIBA_DEVID_PARA_ATA: 614 return ("PATA"); 615 case SIBA_DEVID_SATA_XORDMA: 616 return ("SATA XOR-DMA"); 617 case SIBA_DEVID_ETHERNET_GBIT: 618 return ("GBit Ethernet"); 619 case SIBA_DEVID_PCIE: 620 return ("PCI-Express"); 621 case SIBA_DEVID_MIMO_PHY: 622 return ("MIMO PHY"); 623 case SIBA_DEVID_SRAM_CTRLR: 624 return ("SRAM Controller"); 625 case SIBA_DEVID_MINI_MACPHY: 626 return ("Mini MACPHY"); 627 case SIBA_DEVID_ARM_1176: 628 return ("ARM 1176"); 629 case SIBA_DEVID_ARM_7TDMI: 630 return ("ARM 7TDMI"); 631 } 632 return ("unknown"); 633 } 634 635 static uint16_t 636 siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset) 637 { 638 struct siba_softc *siba = sd->sd_bus; 639 640 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 641 return (0xffff); 642 643 return (SIBA_READ_2(siba, offset)); 644 } 645 646 static uint32_t 647 siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset) 648 { 649 struct siba_softc *siba = sd->sd_bus; 650 651 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 652 return (0xffff); 653 654 return (SIBA_READ_4(siba, offset)); 655 } 656 657 static void 658 siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value) 659 { 660 struct siba_softc *siba = sd->sd_bus; 661 662 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 663 return; 664 665 SIBA_WRITE_2(siba, offset, value); 666 } 667 668 static void 669 siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) 670 { 671 struct siba_softc *siba = sd->sd_bus; 672 673 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 674 return; 675 676 SIBA_WRITE_4(siba, offset, value); 677 } 678 679 static void 680 siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count, 681 uint16_t offset) 682 { 683 struct siba_softc *siba = sd->sd_bus; 684 685 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 686 memset(buffer, 0xff, count); 687 return; 688 } 689 690 SIBA_READ_MULTI_1(siba, offset, buffer, count); 691 } 692 693 static void 694 siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count, 695 uint16_t offset) 696 { 697 struct siba_softc *siba = sd->sd_bus; 698 699 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 700 memset(buffer, 0xff, count); 701 return; 702 } 703 704 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); 705 SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1); 706 } 707 708 static void 709 siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count, 710 uint16_t offset) 711 { 712 struct siba_softc *siba = sd->sd_bus; 713 714 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { 715 memset(buffer, 0xff, count); 716 return; 717 } 718 719 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); 720 SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2); 721 } 722 723 static void 724 siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer, 725 size_t count, uint16_t offset) 726 { 727 struct siba_softc *siba = sd->sd_bus; 728 729 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 730 return; 731 732 SIBA_WRITE_MULTI_1(siba, offset, buffer, count); 733 } 734 735 static void 736 siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer, 737 size_t count, uint16_t offset) 738 { 739 struct siba_softc *siba = sd->sd_bus; 740 741 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 742 return; 743 744 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); 745 SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1); 746 } 747 748 static void 749 siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer, 750 size_t count, uint16_t offset) 751 { 752 struct siba_softc *siba = sd->sd_bus; 753 754 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) 755 return; 756 757 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); 758 SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2); 759 } 760 761 void 762 siba_powerup(device_t dev, int dynamic) 763 { 764 struct siba_dev_softc *sd = device_get_ivars(dev); 765 struct siba_softc *siba = sd->sd_bus; 766 767 siba_powerup_sub(siba, dynamic); 768 } 769 770 static void 771 siba_powerup_sub(struct siba_softc *siba, int dynamic) 772 { 773 774 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); 775 siba_cc_clock(&siba->siba_cc, 776 (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST); 777 } 778 779 static void 780 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock) 781 { 782 struct siba_dev_softc *sd = scc->scc_dev; 783 struct siba_softc *siba; 784 uint32_t tmp; 785 786 if (sd == NULL) 787 return; 788 siba = sd->sd_bus; 789 /* 790 * chipcommon < r6 (no dynamic clock control) 791 * chipcommon >= r10 (unknown) 792 */ 793 if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 || 794 (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) 795 return; 796 797 switch (clock) { 798 case SIBA_CLOCK_DYNAMIC: 799 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 800 ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW | 801 SIBA_CC_CLKSLOW_IPLL); 802 if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL) 803 tmp |= SIBA_CC_CLKSLOW_ENXTAL; 804 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp); 805 if (tmp & SIBA_CC_CLKSLOW_ENXTAL) 806 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0); 807 break; 808 case SIBA_CLOCK_SLOW: 809 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, 810 SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | 811 SIBA_CC_CLKSLOW_FSLOW); 812 break; 813 case SIBA_CLOCK_FAST: 814 /* crystal on */ 815 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1); 816 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, 817 (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | 818 SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW); 819 break; 820 default: 821 KASSERT(0 == 1, 822 ("%s: unsupported clock %#x", __func__, clock)); 823 } 824 } 825 826 uint16_t 827 siba_read_2(device_t dev, uint16_t offset) 828 { 829 struct siba_dev_softc *sd = device_get_ivars(dev); 830 831 return (sd->sd_ops->read_2(sd, offset)); 832 } 833 834 uint32_t 835 siba_read_4(device_t dev, uint16_t offset) 836 { 837 struct siba_dev_softc *sd = device_get_ivars(dev); 838 839 return (siba_read_4_sub(sd, offset)); 840 } 841 842 static uint32_t 843 siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset) 844 { 845 846 return (sd->sd_ops->read_4(sd, offset)); 847 } 848 849 void 850 siba_write_2(device_t dev, uint16_t offset, uint16_t value) 851 { 852 struct siba_dev_softc *sd = device_get_ivars(dev); 853 854 sd->sd_ops->write_2(sd, offset, value); 855 } 856 857 void 858 siba_write_4(device_t dev, uint16_t offset, uint32_t value) 859 { 860 struct siba_dev_softc *sd = device_get_ivars(dev); 861 862 return (siba_write_4_sub(sd, offset, value)); 863 } 864 865 static void 866 siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) 867 { 868 869 sd->sd_ops->write_4(sd, offset, value); 870 } 871 872 void 873 siba_read_multi_1(device_t dev, void *buffer, size_t count, 874 uint16_t offset) 875 { 876 struct siba_dev_softc *sd = device_get_ivars(dev); 877 878 sd->sd_ops->read_multi_1(sd, buffer, count, offset); 879 } 880 881 void 882 siba_read_multi_2(device_t dev, void *buffer, size_t count, 883 uint16_t offset) 884 { 885 struct siba_dev_softc *sd = device_get_ivars(dev); 886 887 sd->sd_ops->read_multi_2(sd, buffer, count, offset); 888 } 889 890 void 891 siba_read_multi_4(device_t dev, void *buffer, size_t count, 892 uint16_t offset) 893 { 894 struct siba_dev_softc *sd = device_get_ivars(dev); 895 896 sd->sd_ops->read_multi_4(sd, buffer, count, offset); 897 } 898 899 void 900 siba_write_multi_1(device_t dev, const void *buffer, size_t count, 901 uint16_t offset) 902 { 903 struct siba_dev_softc *sd = device_get_ivars(dev); 904 905 sd->sd_ops->write_multi_1(sd, buffer, count, offset); 906 } 907 908 void 909 siba_write_multi_2(device_t dev, const void *buffer, size_t count, 910 uint16_t offset) 911 { 912 struct siba_dev_softc *sd = device_get_ivars(dev); 913 914 sd->sd_ops->write_multi_2(sd, buffer, count, offset); 915 } 916 917 void 918 siba_write_multi_4(device_t dev, const void *buffer, size_t count, 919 uint16_t offset) 920 { 921 struct siba_dev_softc *sd = device_get_ivars(dev); 922 923 sd->sd_ops->write_multi_4(sd, buffer, count, offset); 924 } 925 926 static void 927 siba_cc_pmu_init(struct siba_cc *scc) 928 { 929 const struct siba_cc_pmu_res_updown *updown = NULL; 930 const struct siba_cc_pmu_res_depend *depend = NULL; 931 struct siba_dev_softc *sd = scc->scc_dev; 932 struct siba_softc *siba = sd->sd_bus; 933 uint32_t min = 0, max = 0, pmucap; 934 unsigned int i, updown_size, depend_size; 935 936 if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0) 937 return; 938 939 pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS); 940 scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV); 941 942 DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n", 943 scc->scc_pmu.rev, pmucap); 944 945 if (scc->scc_pmu.rev >= 1) { 946 if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325) 947 SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, 948 ~SIBA_CC_PMUCTL_NOILP); 949 else 950 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, 951 SIBA_CC_PMUCTL_NOILP); 952 } 953 954 /* initialize PLL & PMU resources */ 955 switch (siba->siba_chipid) { 956 case 0x4312: 957 siba_cc_pmu1_pll0_init(scc, 0 /* use default */); 958 /* use the default: min = 0xcbb max = 0x7ffff */ 959 break; 960 case 0x4325: 961 siba_cc_pmu1_pll0_init(scc, 0 /* use default */); 962 963 updown = siba_cc_pmu_4325_updown; 964 updown_size = nitems(siba_cc_pmu_4325_updown); 965 depend = siba_cc_pmu_4325_depend; 966 depend_size = nitems(siba_cc_pmu_4325_depend); 967 968 min = (1 << SIBA_CC_PMU_4325_BURST) | 969 (1 << SIBA_CC_PMU_4325_LN); 970 if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) & 971 SIBA_CC_CHST_4325_PMUTOP_2B) 972 min |= (1 << SIBA_CC_PMU_4325_CLBURST); 973 max = 0xfffff; 974 break; 975 case 0x4328: 976 siba_cc_pmu0_pll0_init(scc, 0 /* use default */); 977 978 updown = siba_cc_pmu_4328_updown; 979 updown_size = nitems(siba_cc_pmu_4328_updown); 980 depend = siba_cc_pmu_4328_depend; 981 depend_size = nitems(siba_cc_pmu_4328_depend); 982 983 min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | 984 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) | 985 (1 << SIBA_CC_PMU_4328_CRYSTAL_EN); 986 987 max = 0xfffff; 988 break; 989 case 0x5354: 990 siba_cc_pmu0_pll0_init(scc, 0 /* use default */); 991 992 max = 0xfffff; 993 break; 994 default: 995 device_printf(siba->siba_dev, 996 "unknown chipid %#x for PLL & PMU init\n", 997 siba->siba_chipid); 998 } 999 1000 if (updown) { 1001 for (i = 0; i < updown_size; i++) { 1002 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, 1003 updown[i].res); 1004 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM, 1005 updown[i].updown); 1006 } 1007 } 1008 if (depend) { 1009 for (i = 0; i < depend_size; i++) { 1010 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, 1011 depend[i].res); 1012 switch (depend[i].task) { 1013 case SIBA_CC_PMU_DEP_SET: 1014 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK, 1015 depend[i].depend); 1016 break; 1017 case SIBA_CC_PMU_DEP_ADD: 1018 SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK, 1019 depend[i].depend); 1020 break; 1021 case SIBA_CC_PMU_DEP_REMOVE: 1022 SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK, 1023 ~(depend[i].depend)); 1024 break; 1025 default: 1026 KASSERT(0 == 1, 1027 ("%s:%d: assertion failed", 1028 __func__, __LINE__)); 1029 } 1030 } 1031 } 1032 1033 if (min) 1034 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min); 1035 if (max) 1036 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max); 1037 } 1038 1039 static void 1040 siba_cc_power_init(struct siba_cc *scc) 1041 { 1042 struct siba_softc *siba = scc->scc_dev->sd_bus; 1043 int maxfreq; 1044 1045 if (siba->siba_chipid == 0x4321) { 1046 if (siba->siba_chiprev == 0) 1047 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4); 1048 else if (siba->siba_chiprev == 1) 1049 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4); 1050 } 1051 1052 if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) 1053 return; 1054 1055 if (scc->scc_dev->sd_id.sd_rev >= 10) 1056 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL, 1057 (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) & 1058 0xffff) | 0x40000); 1059 else { 1060 maxfreq = siba_cc_clockfreq(scc, 1); 1061 SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY, 1062 (maxfreq * 150 + 999999) / 1000000); 1063 SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY, 1064 (maxfreq * 15 + 999999) / 1000000); 1065 } 1066 } 1067 1068 static void 1069 siba_cc_powerup_delay(struct siba_cc *scc) 1070 { 1071 struct siba_softc *siba = scc->scc_dev->sd_bus; 1072 int min; 1073 1074 if (siba->siba_type != SIBA_TYPE_PCI || 1075 !(scc->scc_caps & SIBA_CC_CAPS_PWCTL)) 1076 return; 1077 1078 min = siba_cc_clockfreq(scc, 0); 1079 scc->scc_powerup_delay = 1080 howmany((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000, 1081 min); 1082 } 1083 1084 static int 1085 siba_cc_clockfreq(struct siba_cc *scc, int max) 1086 { 1087 enum siba_clksrc src; 1088 int div = 1, limit = 0; 1089 1090 src = siba_cc_clksrc(scc); 1091 if (scc->scc_dev->sd_id.sd_rev < 6) { 1092 div = (src == SIBA_CC_CLKSRC_PCI) ? 64 : 1093 (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1; 1094 KASSERT(div != 1, 1095 ("%s: unknown clock %d", __func__, src)); 1096 } else if (scc->scc_dev->sd_id.sd_rev < 10) { 1097 switch (src) { 1098 case SIBA_CC_CLKSRC_CRYSTAL: 1099 case SIBA_CC_CLKSRC_PCI: 1100 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) + 1101 1) * 4; 1102 break; 1103 case SIBA_CC_CLKSRC_LOWPW: 1104 break; 1105 } 1106 } else 1107 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4; 1108 1109 switch (src) { 1110 case SIBA_CC_CLKSRC_CRYSTAL: 1111 limit = (max) ? 20200000 : 19800000; 1112 break; 1113 case SIBA_CC_CLKSRC_LOWPW: 1114 limit = (max) ? 43000 : 25000; 1115 break; 1116 case SIBA_CC_CLKSRC_PCI: 1117 limit = (max) ? 34000000 : 25000000; 1118 break; 1119 } 1120 1121 return (limit / div); 1122 } 1123 1124 static void 1125 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq) 1126 { 1127 struct siba_dev_softc *sd = scc->scc_dev; 1128 struct siba_softc *siba = sd->sd_bus; 1129 const struct siba_cc_pmu1_plltab *e = NULL; 1130 uint32_t bufsth = 0, pll, pmu; 1131 unsigned int i; 1132 1133 KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__)); 1134 if (siba->siba_chipid == 0x4312) { 1135 scc->scc_pmu.freq = 20000; 1136 return; 1137 } 1138 1139 e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ); 1140 KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__)); 1141 scc->scc_pmu.freq = e->freq; 1142 1143 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1144 if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf) 1145 return; 1146 1147 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", 1148 (e->freq / 1000), (e->freq % 1000)); 1149 1150 /* turn PLL off */ 1151 switch (siba->siba_chipid) { 1152 case 0x4325: 1153 bufsth = 0x222222; 1154 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1155 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | 1156 (1 << SIBA_CC_PMU_4325_HT))); 1157 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1158 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | 1159 (1 << SIBA_CC_PMU_4325_HT))); 1160 break; 1161 default: 1162 KASSERT(0 == 1, 1163 ("%s:%d: assertion failed", __func__, __LINE__)); 1164 } 1165 for (i = 0; i < 1500; i++) { 1166 if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & 1167 SIBA_CC_CLKCTLSTATUS_HT)) 1168 break; 1169 DELAY(10); 1170 } 1171 if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT) 1172 device_printf(siba->siba_dev, "failed to turn PLL off!\n"); 1173 1174 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0); 1175 pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV); 1176 pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV; 1177 pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV; 1178 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll); 1179 1180 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2); 1181 pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE); 1182 pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT; 1183 pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE; 1184 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll); 1185 1186 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3); 1187 pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC; 1188 pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC; 1189 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll); 1190 1191 if (bufsth) { 1192 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5); 1193 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV; 1194 pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV; 1195 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll); 1196 } 1197 1198 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1199 pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF); 1200 pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) & 1201 SIBA_CC_PMUCTL_ILP; 1202 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; 1203 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); 1204 } 1205 1206 static void 1207 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq) 1208 { 1209 struct siba_dev_softc *sd = scc->scc_dev; 1210 struct siba_softc *siba = sd->sd_bus; 1211 const struct siba_cc_pmu0_plltab *e = NULL; 1212 uint32_t pmu, tmp, pll; 1213 unsigned int i; 1214 1215 if ((siba->siba_chipid == 0x5354) && !xtalfreq) 1216 xtalfreq = 25000; 1217 if (xtalfreq) 1218 e = siba_cc_pmu0_plltab_findentry(xtalfreq); 1219 if (!e) 1220 e = siba_cc_pmu0_plltab_findentry( 1221 SIBA_CC_PMU0_DEFAULT_XTALFREQ); 1222 KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__)); 1223 xtalfreq = e->freq; 1224 scc->scc_pmu.freq = e->freq; 1225 1226 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1227 if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf) 1228 return; 1229 1230 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", 1231 (xtalfreq / 1000), (xtalfreq % 1000)); 1232 1233 KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354, 1234 ("%s:%d: fail", __func__, __LINE__)); 1235 1236 switch (siba->siba_chipid) { 1237 case 0x4328: 1238 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1239 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); 1240 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1241 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); 1242 break; 1243 case 0x5354: 1244 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, 1245 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); 1246 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, 1247 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); 1248 break; 1249 } 1250 for (i = 1500; i; i--) { 1251 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); 1252 if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT)) 1253 break; 1254 DELAY(10); 1255 } 1256 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); 1257 if (tmp & SIBA_CC_CLKCTLSTATUS_HT) 1258 device_printf(siba->siba_dev, "failed to turn PLL off!\n"); 1259 1260 /* set PDIV */ 1261 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0); 1262 if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ) 1263 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK; 1264 else 1265 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK; 1266 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll); 1267 1268 /* set WILD */ 1269 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1); 1270 pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK | 1271 SIBA_CC_PMU0_PLL1_FMSK); 1272 pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK; 1273 pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK; 1274 if (e->wb_frac == 0) 1275 pll |= SIBA_CC_PMU0_PLL1_STOPMOD; 1276 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll); 1277 1278 /* set WILD */ 1279 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2); 1280 pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI; 1281 pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI; 1282 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll); 1283 1284 /* set freq and divisor. */ 1285 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); 1286 pmu &= ~SIBA_CC_PMUCTL_ILP; 1287 pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP; 1288 pmu &= ~SIBA_CC_PMUCTL_XF; 1289 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; 1290 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); 1291 } 1292 1293 static enum siba_clksrc 1294 siba_cc_clksrc(struct siba_cc *scc) 1295 { 1296 struct siba_dev_softc *sd = scc->scc_dev; 1297 struct siba_softc *siba = sd->sd_bus; 1298 1299 if (sd->sd_id.sd_rev < 6) { 1300 if (siba->siba_type == SIBA_TYPE_PCI) { 1301 if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) & 1302 0x10) 1303 return (SIBA_CC_CLKSRC_PCI); 1304 return (SIBA_CC_CLKSRC_CRYSTAL); 1305 } 1306 if (siba->siba_type == SIBA_TYPE_SSB || 1307 siba->siba_type == SIBA_TYPE_PCMCIA) 1308 return (SIBA_CC_CLKSRC_CRYSTAL); 1309 } 1310 if (sd->sd_id.sd_rev < 10) { 1311 switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) { 1312 case 0: 1313 return (SIBA_CC_CLKSRC_LOWPW); 1314 case 1: 1315 return (SIBA_CC_CLKSRC_CRYSTAL); 1316 case 2: 1317 return (SIBA_CC_CLKSRC_PCI); 1318 default: 1319 break; 1320 } 1321 } 1322 1323 return (SIBA_CC_CLKSRC_CRYSTAL); 1324 } 1325 1326 static const struct siba_cc_pmu1_plltab * 1327 siba_cc_pmu1_plltab_find(uint32_t crystalfreq) 1328 { 1329 const struct siba_cc_pmu1_plltab *e; 1330 unsigned int i; 1331 1332 for (i = 0; i < nitems(siba_cc_pmu1_plltab); i++) { 1333 e = &siba_cc_pmu1_plltab[i]; 1334 if (crystalfreq == e->freq) 1335 return (e); 1336 } 1337 1338 return (NULL); 1339 } 1340 1341 static uint32_t 1342 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset) 1343 { 1344 1345 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); 1346 return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA)); 1347 } 1348 1349 static void 1350 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value) 1351 { 1352 1353 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); 1354 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value); 1355 } 1356 1357 static const struct siba_cc_pmu0_plltab * 1358 siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq) 1359 { 1360 const struct siba_cc_pmu0_plltab *e; 1361 unsigned int i; 1362 1363 for (i = 0; i < nitems(siba_cc_pmu0_plltab); i++) { 1364 e = &siba_cc_pmu0_plltab[i]; 1365 if (e->freq == crystalfreq) 1366 return (e); 1367 } 1368 1369 return (NULL); 1370 } 1371 1372 static int 1373 siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom) 1374 { 1375 int error = ENOMEM; 1376 uint16_t *buf; 1377 1378 buf = kmalloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t), 1379 M_DEVBUF, M_INTWAIT | M_ZERO); 1380 if (buf == NULL) 1381 return (ENOMEM); 1382 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123); 1383 error = sprom_check_crc(buf, siba->siba_spromsize); 1384 if (error) { 1385 kfree(buf, M_DEVBUF); 1386 buf = kmalloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t), 1387 M_DEVBUF, M_INTWAIT | M_ZERO); 1388 if (buf == NULL) 1389 return (ENOMEM); 1390 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4); 1391 error = sprom_check_crc(buf, siba->siba_spromsize); 1392 if (error) 1393 device_printf(siba->siba_dev, "warn: bad SPROM CRC\n"); 1394 } 1395 1396 bzero(sprom, sizeof(*sprom)); 1397 1398 sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF; 1399 DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n", 1400 sprom->rev); 1401 memset(sprom->mac_eth, 0xff, 6); 1402 memset(sprom->mac_80211a, 0xff, 6); 1403 if ((siba->siba_chipid & 0xff00) == 0x4400) { 1404 sprom->rev = 1; 1405 siba_sprom_r123(sprom, buf); 1406 } else if (siba->siba_chipid == 0x4321) { 1407 sprom->rev = 4; 1408 siba_sprom_r45(sprom, buf); 1409 } else { 1410 switch (sprom->rev) { 1411 case 1: 1412 case 2: 1413 case 3: 1414 siba_sprom_r123(sprom, buf); 1415 break; 1416 case 4: 1417 case 5: 1418 siba_sprom_r45(sprom, buf); 1419 break; 1420 case 8: 1421 siba_sprom_r8(sprom, buf); 1422 break; 1423 default: 1424 device_printf(siba->siba_dev, 1425 "unknown SPROM revision %d.\n", sprom->rev); 1426 siba_sprom_r123(sprom, buf); 1427 } 1428 } 1429 1430 if (sprom->bf_lo == 0xffff) 1431 sprom->bf_lo = 0; 1432 if (sprom->bf_hi == 0xffff) 1433 sprom->bf_hi = 0; 1434 1435 kfree(buf, M_DEVBUF); 1436 return (error); 1437 } 1438 1439 static int 1440 siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len) 1441 { 1442 int i; 1443 1444 for (i = 0; i < len; i++) 1445 sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2)); 1446 1447 siba->siba_spromsize = len; 1448 return (0); 1449 } 1450 1451 static int 1452 sprom_check_crc(const uint16_t *sprom, size_t size) 1453 { 1454 int word; 1455 uint8_t crc0, crc1 = 0xff; 1456 1457 crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8; 1458 for (word = 0; word < size - 1; word++) { 1459 crc1 = siba_crc8(crc1, sprom[word] & 0x00ff); 1460 crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8); 1461 } 1462 crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff); 1463 crc1 ^= 0xff; 1464 1465 return ((crc0 != crc1) ? EPROTO : 0); 1466 } 1467 1468 static uint8_t 1469 siba_crc8(uint8_t crc, uint8_t data) 1470 { 1471 static const uint8_t ct[] = { 1472 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b, 1473 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21, 1474 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff, 1475 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5, 1476 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14, 1477 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e, 1478 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80, 1479 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca, 1480 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95, 1481 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf, 1482 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01, 1483 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b, 1484 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea, 1485 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0, 1486 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e, 1487 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34, 1488 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0, 1489 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a, 1490 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54, 1491 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e, 1492 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf, 1493 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5, 1494 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b, 1495 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61, 1496 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e, 1497 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74, 1498 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa, 1499 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0, 1500 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41, 1501 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b, 1502 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5, 1503 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f, 1504 }; 1505 return (ct[crc ^ data]); 1506 } 1507 1508 #define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 1509 #define SIBA_OFFSET(offset) \ 1510 (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t)) 1511 #define SIBA_SHIFTOUT_SUB(__x, __mask) \ 1512 (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask)) 1513 #define SIBA_SHIFTOUT(_var, _offset, _mask) \ 1514 out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask)) 1515 #define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift) \ 1516 out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 | \ 1517 in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift)) 1518 1519 static void 1520 siba_sprom_r123(struct siba_sprom *out, const uint16_t *in) 1521 { 1522 int i; 1523 uint16_t v; 1524 int8_t gain; 1525 uint16_t loc[3]; 1526 1527 if (out->rev == 3) 1528 loc[0] = SIBA_SPROM3_MAC_80211BG; 1529 else { 1530 loc[0] = SIBA_SPROM1_MAC_80211BG; 1531 loc[1] = SIBA_SPROM1_MAC_ETH; 1532 loc[2] = SIBA_SPROM1_MAC_80211A; 1533 } 1534 for (i = 0; i < 3; i++) { 1535 v = in[SIBA_OFFSET(loc[0]) + i]; 1536 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1537 } 1538 if (out->rev < 3) { 1539 for (i = 0; i < 3; i++) { 1540 v = in[SIBA_OFFSET(loc[1]) + i]; 1541 *(((uint16_t *)out->mac_eth) + i) = htobe16(v); 1542 } 1543 for (i = 0; i < 3; i++) { 1544 v = in[SIBA_OFFSET(loc[2]) + i]; 1545 *(((uint16_t *)out->mac_80211a) + i) = htobe16(v); 1546 } 1547 } 1548 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY, 1549 SIBA_SPROM1_ETHPHY_MII_ETH0); 1550 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY, 1551 SIBA_SPROM1_ETHPHY_MII_ETH1); 1552 SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY, 1553 SIBA_SPROM1_ETHPHY_MDIO_ETH0); 1554 SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY, 1555 SIBA_SPROM1_ETHPHY_MDIO_ETH1); 1556 SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV); 1557 SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO, 1558 SIBA_SPROM1_BOARDINFO_CCODE); 1559 SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA); 1560 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO, 1561 SIBA_SPROM1_BOARDINFO_ANTBG); 1562 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff); 1563 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff); 1564 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff); 1565 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff); 1566 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff); 1567 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff); 1568 SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0); 1569 SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1); 1570 SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2); 1571 SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3); 1572 1573 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A); 1574 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG); 1575 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A); 1576 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG); 1577 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff); 1578 if (out->rev >= 2) 1579 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff); 1580 1581 /* antenna gain */ 1582 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0); 1583 out->again.ghz24.a0 = out->again.ghz24.a1 = gain; 1584 out->again.ghz24.a2 = out->again.ghz24.a3 = gain; 1585 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8); 1586 out->again.ghz5.a0 = out->again.ghz5.a1 = gain; 1587 out->again.ghz5.a2 = out->again.ghz5.a3 = gain; 1588 } 1589 1590 static void 1591 siba_sprom_r458(struct siba_sprom *out, const uint16_t *in) 1592 { 1593 1594 SIBA_SHIFTOUT(txpid2g[0], SIBA_SPROM4_TXPID2G01, 1595 SIBA_SPROM4_TXPID2G0); 1596 SIBA_SHIFTOUT(txpid2g[1], SIBA_SPROM4_TXPID2G01, 1597 SIBA_SPROM4_TXPID2G1); 1598 SIBA_SHIFTOUT(txpid2g[2], SIBA_SPROM4_TXPID2G23, 1599 SIBA_SPROM4_TXPID2G2); 1600 SIBA_SHIFTOUT(txpid2g[3], SIBA_SPROM4_TXPID2G23, 1601 SIBA_SPROM4_TXPID2G3); 1602 1603 SIBA_SHIFTOUT(txpid5gl[0], SIBA_SPROM4_TXPID5GL01, 1604 SIBA_SPROM4_TXPID5GL0); 1605 SIBA_SHIFTOUT(txpid5gl[1], SIBA_SPROM4_TXPID5GL01, 1606 SIBA_SPROM4_TXPID5GL1); 1607 SIBA_SHIFTOUT(txpid5gl[2], SIBA_SPROM4_TXPID5GL23, 1608 SIBA_SPROM4_TXPID5GL2); 1609 SIBA_SHIFTOUT(txpid5gl[3], SIBA_SPROM4_TXPID5GL23, 1610 SIBA_SPROM4_TXPID5GL3); 1611 1612 SIBA_SHIFTOUT(txpid5g[0], SIBA_SPROM4_TXPID5G01, 1613 SIBA_SPROM4_TXPID5G0); 1614 SIBA_SHIFTOUT(txpid5g[1], SIBA_SPROM4_TXPID5G01, 1615 SIBA_SPROM4_TXPID5G1); 1616 SIBA_SHIFTOUT(txpid5g[2], SIBA_SPROM4_TXPID5G23, 1617 SIBA_SPROM4_TXPID5G2); 1618 SIBA_SHIFTOUT(txpid5g[3], SIBA_SPROM4_TXPID5G23, 1619 SIBA_SPROM4_TXPID5G3); 1620 1621 SIBA_SHIFTOUT(txpid5gh[0], SIBA_SPROM4_TXPID5GH01, 1622 SIBA_SPROM4_TXPID5GH0); 1623 SIBA_SHIFTOUT(txpid5gh[1], SIBA_SPROM4_TXPID5GH01, 1624 SIBA_SPROM4_TXPID5GH1); 1625 SIBA_SHIFTOUT(txpid5gh[2], SIBA_SPROM4_TXPID5GH23, 1626 SIBA_SPROM4_TXPID5GH2); 1627 SIBA_SHIFTOUT(txpid5gh[3], SIBA_SPROM4_TXPID5GH23, 1628 SIBA_SPROM4_TXPID5GH3); 1629 } 1630 1631 static void 1632 siba_sprom_r45(struct siba_sprom *out, const uint16_t *in) 1633 { 1634 int i; 1635 uint16_t v; 1636 uint16_t mac_80211bg_offset; 1637 const uint16_t pwr_info_offset[] = { 1638 SIBA_SPROM4_PWR_INFO_CORE0, SIBA_SPROM4_PWR_INFO_CORE1, 1639 SIBA_SPROM4_PWR_INFO_CORE2, SIBA_SPROM4_PWR_INFO_CORE3 1640 }; 1641 1642 if (out->rev == 4) 1643 mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG; 1644 else 1645 mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG; 1646 for (i = 0; i < 3; i++) { 1647 v = in[SIBA_OFFSET(mac_80211bg_offset) + i]; 1648 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1649 } 1650 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A); 1651 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A); 1652 if (out->rev == 4) { 1653 SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff); 1654 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff); 1655 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff); 1656 } else { 1657 SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff); 1658 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff); 1659 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff); 1660 } 1661 SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A); 1662 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG); 1663 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK); 1664 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG); 1665 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK); 1666 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A); 1667 if (out->rev == 4) { 1668 SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0); 1669 SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1); 1670 SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2); 1671 SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3); 1672 } else { 1673 SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0); 1674 SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1); 1675 SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2); 1676 SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3); 1677 } 1678 1679 /* antenna gain */ 1680 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0); 1681 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1); 1682 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2); 1683 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3); 1684 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); 1685 1686 /* Extract core power info */ 1687 for (i = 0; i < nitems(pwr_info_offset); i++) { 1688 uint16_t o = pwr_info_offset[i]; 1689 1690 SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, 1691 SIBA_SPROM4_2G_ITSSI); 1692 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, 1693 SIBA_SPROM4_2G_MAXP); 1694 1695 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SPROM4_2G_PA_0, ~0); 1696 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SPROM4_2G_PA_1, ~0); 1697 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SPROM4_2G_PA_2, ~0); 1698 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[3], o + SIBA_SPROM4_2G_PA_3, ~0); 1699 1700 SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, 1701 SIBA_SPROM4_5G_ITSSI); 1702 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, 1703 SIBA_SPROM4_5G_MAXP); 1704 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM4_5GHL_MAXP, 1705 SIBA_SPROM4_5GH_MAXP); 1706 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM4_5GHL_MAXP, 1707 SIBA_SPROM4_5GL_MAXP); 1708 1709 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SPROM4_5GL_PA_0, ~0); 1710 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SPROM4_5GL_PA_1, ~0); 1711 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SPROM4_5GL_PA_2, ~0); 1712 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[3], o + SIBA_SPROM4_5GL_PA_3, ~0); 1713 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SPROM4_5G_PA_0, ~0); 1714 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SPROM4_5G_PA_1, ~0); 1715 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SPROM4_5G_PA_2, ~0); 1716 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[3], o + SIBA_SPROM4_5G_PA_3, ~0); 1717 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SPROM4_5GH_PA_0, ~0); 1718 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SPROM4_5GH_PA_1, ~0); 1719 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SPROM4_5GH_PA_2, ~0); 1720 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[3], o + SIBA_SPROM4_5GH_PA_3, ~0); 1721 } 1722 1723 siba_sprom_r458(out, in); 1724 } 1725 1726 static void 1727 siba_sprom_r8(struct siba_sprom *out, const uint16_t *in) 1728 { 1729 int i; 1730 uint16_t v; 1731 uint16_t pwr_info_offset[] = { 1732 SIBA_SROM8_PWR_INFO_CORE0, SIBA_SROM8_PWR_INFO_CORE1, 1733 SIBA_SROM8_PWR_INFO_CORE2, SIBA_SROM8_PWR_INFO_CORE3 1734 }; 1735 1736 for (i = 0; i < 3; i++) { 1737 v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i]; 1738 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); 1739 } 1740 SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff); 1741 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff); 1742 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff); 1743 SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff); 1744 SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff); 1745 SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A); 1746 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG); 1747 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK); 1748 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG); 1749 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK); 1750 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A); 1751 SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL, 1752 SIBA_SPROM8_MAXP_AH_MASK); 1753 SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL, 1754 SIBA_SPROM8_MAXP_AL_MASK); 1755 SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0); 1756 SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1); 1757 SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2); 1758 SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3); 1759 SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G); 1760 SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G); 1761 SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL); 1762 SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH); 1763 SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G); 1764 SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G); 1765 1766 SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G); 1767 SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G); 1768 SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G); 1769 SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G); 1770 SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G); 1771 SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G); 1772 SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G); 1773 SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G); 1774 1775 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff); 1776 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff); 1777 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff); 1778 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff); 1779 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff); 1780 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff); 1781 SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff); 1782 SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff); 1783 SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff); 1784 SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff); 1785 SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff); 1786 SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff); 1787 SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff); 1788 1789 SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0); 1790 SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0); 1791 SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0); 1792 SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0); 1793 1794 /* antenna gain */ 1795 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0); 1796 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1); 1797 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2); 1798 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3); 1799 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); 1800 1801 /* FEM */ 1802 SIBA_SHIFTOUT(fem.ghz2.tssipos, SIBA_SPROM8_FEM2G, 1803 SSB_SROM8_FEM_TSSIPOS); 1804 SIBA_SHIFTOUT(fem.ghz2.extpa_gain, SIBA_SPROM8_FEM2G, 1805 SSB_SROM8_FEM_EXTPA_GAIN); 1806 SIBA_SHIFTOUT(fem.ghz2.pdet_range, SIBA_SPROM8_FEM2G, 1807 SSB_SROM8_FEM_PDET_RANGE); 1808 SIBA_SHIFTOUT(fem.ghz2.tr_iso, SIBA_SPROM8_FEM2G, 1809 SSB_SROM8_FEM_TR_ISO); 1810 SIBA_SHIFTOUT(fem.ghz2.antswlut, SIBA_SPROM8_FEM2G, 1811 SSB_SROM8_FEM_ANTSWLUT); 1812 1813 SIBA_SHIFTOUT(fem.ghz5.tssipos, SIBA_SPROM8_FEM5G, 1814 SSB_SROM8_FEM_TSSIPOS); 1815 SIBA_SHIFTOUT(fem.ghz5.extpa_gain, SIBA_SPROM8_FEM5G, 1816 SSB_SROM8_FEM_EXTPA_GAIN); 1817 SIBA_SHIFTOUT(fem.ghz5.pdet_range, SIBA_SPROM8_FEM5G, 1818 SSB_SROM8_FEM_PDET_RANGE); 1819 SIBA_SHIFTOUT(fem.ghz5.tr_iso, SIBA_SPROM8_FEM5G, 1820 SSB_SROM8_FEM_TR_ISO); 1821 SIBA_SHIFTOUT(fem.ghz5.antswlut, SIBA_SPROM8_FEM5G, 1822 SSB_SROM8_FEM_ANTSWLUT); 1823 1824 /* Extract cores power info info */ 1825 for (i = 0; i < nitems(pwr_info_offset); i++) { 1826 uint16_t o = pwr_info_offset[i]; 1827 SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, 1828 SIBA_SPROM8_2G_ITSSI); 1829 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, 1830 SIBA_SPROM8_2G_MAXP); 1831 1832 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SROM8_2G_PA_0, ~0); 1833 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SROM8_2G_PA_1, ~0); 1834 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SROM8_2G_PA_2, ~0); 1835 1836 SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, 1837 SIBA_SPROM8_5G_ITSSI); 1838 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, 1839 SIBA_SPROM8_5G_MAXP); 1840 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM8_5GHL_MAXP, 1841 SIBA_SPROM8_5GH_MAXP); 1842 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM8_5GHL_MAXP, 1843 SIBA_SPROM8_5GL_MAXP); 1844 1845 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SROM8_5GL_PA_0, ~0); 1846 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SROM8_5GL_PA_1, ~0); 1847 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SROM8_5GL_PA_2, ~0); 1848 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SROM8_5G_PA_0, ~0); 1849 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SROM8_5G_PA_1, ~0); 1850 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SROM8_5G_PA_2, ~0); 1851 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SROM8_5GH_PA_0, ~0); 1852 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SROM8_5GH_PA_1, ~0); 1853 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SROM8_5GH_PA_2, ~0); 1854 } 1855 1856 SIBA_SHIFTOUT(cddpo, SIBA_SPROM8_CDDPO, ~0); 1857 SIBA_SHIFTOUT(stbcpo, SIBA_SPROM8_STBCPO, ~0); 1858 1859 siba_sprom_r458(out, in); 1860 } 1861 1862 static int8_t 1863 siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in, 1864 uint16_t mask, uint16_t shift) 1865 { 1866 uint16_t v; 1867 uint8_t gain; 1868 1869 v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)]; 1870 gain = (v & mask) >> shift; 1871 gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 : 1872 ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2); 1873 1874 return ((int8_t)gain); 1875 } 1876 1877 #undef SIBA_LOWEST_SET_BIT 1878 #undef SIBA_OFFSET 1879 #undef SIBA_SHIFTOUT_SUB 1880 #undef SIBA_SHIFTOUT 1881 1882 int 1883 siba_powerdown(device_t dev) 1884 { 1885 struct siba_dev_softc *sd = device_get_ivars(dev); 1886 struct siba_softc *siba = sd->sd_bus; 1887 1888 return (siba_powerdown_sub(siba)); 1889 } 1890 1891 static int 1892 siba_powerdown_sub(struct siba_softc *siba) 1893 { 1894 struct siba_cc *scc; 1895 1896 if (siba->siba_type == SIBA_TYPE_SSB) 1897 return (0); 1898 1899 scc = &siba->siba_cc; 1900 if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5) 1901 return (0); 1902 siba_cc_clock(scc, SIBA_CLOCK_SLOW); 1903 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); 1904 return (0); 1905 } 1906 1907 static void 1908 siba_pcicore_init(struct siba_pci *spc) 1909 { 1910 struct siba_dev_softc *sd = spc->spc_dev; 1911 1912 if (sd == NULL) 1913 return; 1914 1915 if (!siba_dev_isup_sub(sd)) 1916 siba_dev_up_sub(sd, 0); 1917 1918 KASSERT(spc->spc_hostmode == 0, 1919 ("%s:%d: hostmode", __func__, __LINE__)); 1920 /* disable PCI interrupt */ 1921 siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0); 1922 } 1923 1924 int 1925 siba_dev_isup(device_t dev) 1926 { 1927 struct siba_dev_softc *sd = device_get_ivars(dev); 1928 1929 return (siba_dev_isup_sub(sd)); 1930 } 1931 1932 static int 1933 siba_dev_isup_sub(struct siba_dev_softc *sd) 1934 { 1935 uint32_t reject, val; 1936 1937 reject = siba_tmslow_reject_bitmask(sd); 1938 val = siba_read_4_sub(sd, SIBA_TGSLOW); 1939 val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject; 1940 1941 return (val == SIBA_TGSLOW_CLOCK); 1942 } 1943 1944 void 1945 siba_dev_up(device_t dev, uint32_t flags) 1946 { 1947 struct siba_dev_softc *sd = device_get_ivars(dev); 1948 1949 siba_dev_up_sub(sd, flags); 1950 } 1951 1952 static void 1953 siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags) 1954 { 1955 uint32_t val; 1956 1957 siba_dev_down_sub(sd, flags); 1958 siba_write_4_sub(sd, SIBA_TGSLOW, 1959 SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); 1960 siba_read_4_sub(sd, SIBA_TGSLOW); 1961 DELAY(1); 1962 1963 if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR) 1964 siba_write_4_sub(sd, SIBA_TGSHIGH, 0); 1965 1966 val = siba_read_4_sub(sd, SIBA_IAS); 1967 if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) { 1968 val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT); 1969 siba_write_4_sub(sd, SIBA_IAS, val); 1970 } 1971 1972 siba_write_4_sub(sd, SIBA_TGSLOW, 1973 SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); 1974 siba_read_4_sub(sd, SIBA_TGSLOW); 1975 DELAY(1); 1976 1977 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags); 1978 siba_read_4_sub(sd, SIBA_TGSLOW); 1979 DELAY(1); 1980 } 1981 1982 static uint32_t 1983 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd) 1984 { 1985 uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV; 1986 1987 switch (rev) { 1988 case SIBA_IDLOW_SSBREV_22: 1989 return (SIBA_TGSLOW_REJECT_22); 1990 case SIBA_IDLOW_SSBREV_23: 1991 return (SIBA_TGSLOW_REJECT_23); 1992 case SIBA_IDLOW_SSBREV_24: 1993 case SIBA_IDLOW_SSBREV_25: 1994 case SIBA_IDLOW_SSBREV_26: 1995 case SIBA_IDLOW_SSBREV_27: 1996 return (SIBA_TGSLOW_REJECT_23); 1997 default: 1998 KASSERT(0 == 1, 1999 ("%s:%d: unknown backplane rev %#x\n", 2000 __func__, __LINE__, rev)); 2001 } 2002 return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23); 2003 } 2004 2005 void 2006 siba_dev_down(device_t dev, uint32_t flags) 2007 { 2008 struct siba_dev_softc *sd = device_get_ivars(dev); 2009 2010 siba_dev_down_sub(sd, flags); 2011 } 2012 2013 static void 2014 siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags) 2015 { 2016 struct siba_softc *siba = sd->sd_bus; 2017 uint32_t reject, val; 2018 int i; 2019 2020 if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET) 2021 return; 2022 2023 reject = siba_tmslow_reject_bitmask(sd); 2024 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK); 2025 2026 for (i = 0; i < 1000; i++) { 2027 val = siba_read_4_sub(sd, SIBA_TGSLOW); 2028 if (val & reject) 2029 break; 2030 DELAY(10); 2031 } 2032 if ((val & reject) == 0) { 2033 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", 2034 reject, SIBA_TGSLOW); 2035 } 2036 for (i = 0; i < 1000; i++) { 2037 val = siba_read_4_sub(sd, SIBA_TGSHIGH); 2038 if (!(val & SIBA_TGSHIGH_BUSY)) 2039 break; 2040 DELAY(10); 2041 } 2042 if ((val & SIBA_TGSHIGH_BUSY) != 0) { 2043 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", 2044 SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH); 2045 } 2046 2047 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK | 2048 reject | SIBA_TGSLOW_RESET | flags); 2049 siba_read_4_sub(sd, SIBA_TGSLOW); 2050 DELAY(1); 2051 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags); 2052 siba_read_4_sub(sd, SIBA_TGSLOW); 2053 DELAY(1); 2054 } 2055 2056 static void 2057 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd) 2058 { 2059 struct siba_dev_softc *psd = spc->spc_dev; 2060 struct siba_softc *siba = psd->sd_bus; 2061 uint32_t tmp; 2062 2063 if (psd->sd_id.sd_device == SIBA_DEVID_PCI) { 2064 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, 2065 siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) | 2066 SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST); 2067 2068 if (psd->sd_id.sd_rev < 5) { 2069 tmp = siba_read_4_sub(psd, SIBA_IMCFGLO); 2070 tmp &= ~SIBA_IMCFGLO_SERTO; 2071 tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO; 2072 tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */; 2073 siba_write_4_sub(psd, SIBA_IMCFGLO, tmp); 2074 2075 /* broadcast value */ 2076 sd = (siba->siba_cc.scc_dev != NULL) ? 2077 siba->siba_cc.scc_dev : siba->siba_pci.spc_dev; 2078 if (sd != NULL) { 2079 siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR, 2080 0xfd8); 2081 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR); 2082 siba_write_4_sub(sd, 2083 SIBA_PCICORE_BCAST_DATA, 0); 2084 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA); 2085 } 2086 } else if (psd->sd_id.sd_rev >= 11) { 2087 tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2); 2088 tmp |= SIBA_PCICORE_SBTOPCI_MRM; 2089 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp); 2090 } 2091 } else { 2092 KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE")); 2093 if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1)) 2094 siba_pcie_write(spc, 0x4, 2095 siba_pcie_read(spc, 0x4) | 0x8); 2096 if (psd->sd_id.sd_rev == 0) { 2097 siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */ 2098 siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */ 2099 siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */ 2100 } else if (psd->sd_id.sd_rev == 1) 2101 siba_pcie_write(spc, 0x100, 2102 siba_pcie_read(spc, 0x100) | 0x40); 2103 } 2104 spc->spc_inited = 1; 2105 } 2106 2107 void 2108 siba_pcicore_intr(device_t dev) 2109 { 2110 struct siba_dev_softc *sd = device_get_ivars(dev); 2111 struct siba_softc *siba = sd->sd_bus; 2112 struct siba_pci *spc = &siba->siba_pci; 2113 struct siba_dev_softc *psd = spc->spc_dev; 2114 uint32_t tmp; 2115 2116 if (siba->siba_type != SIBA_TYPE_PCI || !psd) 2117 return; 2118 2119 KASSERT(siba == psd->sd_bus, ("different pointers")); 2120 2121 /* enable interrupts */ 2122 if (siba->siba_dev != NULL && 2123 (psd->sd_id.sd_rev >= 6 || 2124 psd->sd_id.sd_device == SIBA_DEVID_PCIE)) { 2125 tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4); 2126 tmp |= (1 << sd->sd_coreidx) << 8; 2127 pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4); 2128 } else { 2129 tmp = siba_read_4_sub(sd, SIBA_TPS); 2130 tmp &= SIBA_TPS_BPFLAG; 2131 siba_write_4_sub(psd, SIBA_INTR_MASK, 2132 siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp)); 2133 } 2134 2135 /* setup PCIcore */ 2136 if (spc->spc_inited == 0) 2137 siba_pcicore_setup(spc, sd); 2138 } 2139 2140 static uint32_t 2141 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset) 2142 { 2143 2144 return (siba_read_4_sub(spc->spc_dev, offset)); 2145 } 2146 2147 static void 2148 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value) 2149 { 2150 2151 siba_write_4_sub(spc->spc_dev, offset, value); 2152 } 2153 2154 static uint32_t 2155 siba_pcie_read(struct siba_pci *spc, uint32_t address) 2156 { 2157 2158 siba_pcicore_write_4(spc, 0x130, address); 2159 return (siba_pcicore_read_4(spc, 0x134)); 2160 } 2161 2162 static void 2163 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data) 2164 { 2165 2166 siba_pcicore_write_4(spc, 0x130, address); 2167 siba_pcicore_write_4(spc, 0x134, data); 2168 } 2169 2170 static void 2171 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address, 2172 uint16_t data) 2173 { 2174 int i; 2175 2176 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2); 2177 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA, 2178 (1 << 30) | (1 << 28) | 2179 ((uint32_t)device << 22) | ((uint32_t)address << 18) | 2180 (1 << 17) | data); 2181 DELAY(10); 2182 for (i = 0; i < 10; i++) { 2183 if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100) 2184 break; 2185 DELAY(1000); 2186 } 2187 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0); 2188 } 2189 2190 uint32_t 2191 siba_dma_translation(device_t dev) 2192 { 2193 #ifdef INVARIANTS 2194 struct siba_dev_softc *sd = device_get_ivars(dev); 2195 struct siba_softc *siba = sd->sd_bus; 2196 2197 KASSERT(siba->siba_type == SIBA_TYPE_PCI, 2198 ("unsupported bustype %d\n", siba->siba_type)); 2199 #endif 2200 return (SIBA_PCI_DMA); 2201 } 2202 2203 void 2204 siba_barrier(device_t dev, int flags) 2205 { 2206 struct siba_dev_softc *sd = device_get_ivars(dev); 2207 struct siba_softc *siba = sd->sd_bus; 2208 2209 SIBA_BARRIER(siba, flags); 2210 } 2211 2212 static void 2213 siba_cc_suspend(struct siba_cc *scc) 2214 { 2215 2216 siba_cc_clock(scc, SIBA_CLOCK_SLOW); 2217 } 2218 2219 static void 2220 siba_cc_resume(struct siba_cc *scc) 2221 { 2222 2223 siba_cc_power_init(scc); 2224 siba_cc_clock(scc, SIBA_CLOCK_FAST); 2225 } 2226 2227 int 2228 siba_core_suspend(struct siba_softc *siba) 2229 { 2230 2231 siba_cc_suspend(&siba->siba_cc); 2232 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); 2233 return (0); 2234 } 2235 2236 int 2237 siba_core_resume(struct siba_softc *siba) 2238 { 2239 2240 siba->siba_pci.spc_inited = 0; 2241 siba->siba_curdev = NULL; 2242 2243 siba_powerup_sub(siba, 0); 2244 /* XXX setup H/W for PCMCIA??? */ 2245 siba_cc_resume(&siba->siba_cc); 2246 siba_powerdown_sub(siba); 2247 2248 return (0); 2249 } 2250 2251 static void 2252 siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask, 2253 uint32_t set) 2254 { 2255 2256 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); 2257 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset); 2258 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); 2259 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA, 2260 (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set); 2261 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA); 2262 } 2263 2264 void 2265 siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt) 2266 { 2267 struct siba_dev_softc *sd = device_get_ivars(dev); 2268 struct siba_softc *siba = sd->sd_bus; 2269 struct siba_cc *scc = &siba->siba_cc; 2270 uint32_t *p = NULL, info[5][3] = { 2271 { 2, 25, 0xf }, 2272 { 3, 1, 0xf }, 2273 { 3, 9, 0xf }, 2274 { 3, 17, 0x3f }, 2275 { 0, 21, 0x3f } 2276 }; 2277 2278 if (siba->siba_chipid == 0x4312) { 2279 if (id != SIBA_LDO_PAREF) 2280 return; 2281 p = info[4]; 2282 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), 2283 (volt & p[2]) << p[1]); 2284 return; 2285 } 2286 if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) { 2287 switch (id) { 2288 case SIBA_LDO_PAREF: 2289 p = info[3]; 2290 break; 2291 case SIBA_LDO_VOLT1: 2292 p = info[0]; 2293 break; 2294 case SIBA_LDO_VOLT2: 2295 p = info[1]; 2296 break; 2297 case SIBA_LDO_VOLT3: 2298 p = info[2]; 2299 break; 2300 default: 2301 KASSERT(0 == 1, 2302 ("%s: unsupported voltage ID %#x", __func__, id)); 2303 return; 2304 } 2305 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), 2306 (volt & p[2]) << p[1]); 2307 } 2308 } 2309 2310 void 2311 siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on) 2312 { 2313 struct siba_dev_softc *sd = device_get_ivars(dev); 2314 struct siba_softc *siba = sd->sd_bus; 2315 struct siba_cc *scc = &siba->siba_cc; 2316 int ldo; 2317 2318 ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF : 2319 ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF : 2320 ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1))); 2321 if (ldo == -1) 2322 return; 2323 2324 if (on) 2325 SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo); 2326 else 2327 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo)); 2328 SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES); 2329 } 2330 2331 int 2332 siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result) 2333 { 2334 struct siba_dev_softc *sd = device_get_ivars(child); 2335 struct siba_softc *siba = sd->sd_bus; 2336 2337 switch (which) { 2338 case SIBA_SPROMVAR_REV: 2339 *result = siba->siba_sprom.rev; 2340 break; 2341 case SIBA_SPROMVAR_MAC_80211BG: 2342 *((uint8_t **) result) = siba->siba_sprom.mac_80211bg; 2343 break; 2344 case SIBA_SPROMVAR_MAC_ETH: 2345 *((uint8_t **) result) = siba->siba_sprom.mac_eth; 2346 break; 2347 case SIBA_SPROMVAR_MAC_80211A: 2348 *((uint8_t **) result) = siba->siba_sprom.mac_80211a; 2349 break; 2350 case SIBA_SPROMVAR_MII_ETH0: 2351 *result = siba->siba_sprom.mii_eth0; 2352 break; 2353 case SIBA_SPROMVAR_MII_ETH1: 2354 *result = siba->siba_sprom.mii_eth1; 2355 break; 2356 case SIBA_SPROMVAR_MDIO_ETH0: 2357 *result = siba->siba_sprom.mdio_eth0; 2358 break; 2359 case SIBA_SPROMVAR_MDIO_ETH1: 2360 *result = siba->siba_sprom.mdio_eth1; 2361 break; 2362 case SIBA_SPROMVAR_BREV: 2363 *result = siba->siba_sprom.brev; 2364 break; 2365 case SIBA_SPROMVAR_CCODE: 2366 *result = siba->siba_sprom.ccode; 2367 break; 2368 case SIBA_SPROMVAR_ANT_A: 2369 *result = siba->siba_sprom.ant_a; 2370 break; 2371 case SIBA_SPROMVAR_ANT_BG: 2372 *result = siba->siba_sprom.ant_bg; 2373 break; 2374 case SIBA_SPROMVAR_PA0B0: 2375 *result = siba->siba_sprom.pa0b0; 2376 break; 2377 case SIBA_SPROMVAR_PA0B1: 2378 *result = siba->siba_sprom.pa0b1; 2379 break; 2380 case SIBA_SPROMVAR_PA0B2: 2381 *result = siba->siba_sprom.pa0b2; 2382 break; 2383 case SIBA_SPROMVAR_PA1B0: 2384 *result = siba->siba_sprom.pa1b0; 2385 break; 2386 case SIBA_SPROMVAR_PA1B1: 2387 *result = siba->siba_sprom.pa1b1; 2388 break; 2389 case SIBA_SPROMVAR_PA1B2: 2390 *result = siba->siba_sprom.pa1b2; 2391 break; 2392 case SIBA_SPROMVAR_PA1LOB0: 2393 *result = siba->siba_sprom.pa1lob0; 2394 break; 2395 case SIBA_SPROMVAR_PA1LOB1: 2396 *result = siba->siba_sprom.pa1lob1; 2397 break; 2398 case SIBA_SPROMVAR_PA1LOB2: 2399 *result = siba->siba_sprom.pa1lob2; 2400 break; 2401 case SIBA_SPROMVAR_PA1HIB0: 2402 *result = siba->siba_sprom.pa1hib0; 2403 break; 2404 case SIBA_SPROMVAR_PA1HIB1: 2405 *result = siba->siba_sprom.pa1hib1; 2406 break; 2407 case SIBA_SPROMVAR_PA1HIB2: 2408 *result = siba->siba_sprom.pa1hib2; 2409 break; 2410 case SIBA_SPROMVAR_GPIO0: 2411 *result = siba->siba_sprom.gpio0; 2412 break; 2413 case SIBA_SPROMVAR_GPIO1: 2414 *result = siba->siba_sprom.gpio1; 2415 break; 2416 case SIBA_SPROMVAR_GPIO2: 2417 *result = siba->siba_sprom.gpio2; 2418 break; 2419 case SIBA_SPROMVAR_GPIO3: 2420 *result = siba->siba_sprom.gpio3; 2421 break; 2422 case SIBA_SPROMVAR_MAXPWR_AL: 2423 *result = siba->siba_sprom.maxpwr_al; 2424 break; 2425 case SIBA_SPROMVAR_MAXPWR_A: 2426 *result = siba->siba_sprom.maxpwr_a; 2427 break; 2428 case SIBA_SPROMVAR_MAXPWR_AH: 2429 *result = siba->siba_sprom.maxpwr_ah; 2430 break; 2431 case SIBA_SPROMVAR_MAXPWR_BG: 2432 *result = siba->siba_sprom.maxpwr_bg; 2433 break; 2434 case SIBA_SPROMVAR_RXPO2G: 2435 *result = siba->siba_sprom.rxpo2g; 2436 break; 2437 case SIBA_SPROMVAR_RXPO5G: 2438 *result = siba->siba_sprom.rxpo5g; 2439 break; 2440 case SIBA_SPROMVAR_TSSI_A: 2441 *result = siba->siba_sprom.tssi_a; 2442 break; 2443 case SIBA_SPROMVAR_TSSI_BG: 2444 *result = siba->siba_sprom.tssi_bg; 2445 break; 2446 case SIBA_SPROMVAR_TRI2G: 2447 *result = siba->siba_sprom.tri2g; 2448 break; 2449 case SIBA_SPROMVAR_TRI5GL: 2450 *result = siba->siba_sprom.tri5gl; 2451 break; 2452 case SIBA_SPROMVAR_TRI5G: 2453 *result = siba->siba_sprom.tri5g; 2454 break; 2455 case SIBA_SPROMVAR_TRI5GH: 2456 *result = siba->siba_sprom.tri5gh; 2457 break; 2458 case SIBA_SPROMVAR_RSSISAV2G: 2459 *result = siba->siba_sprom.rssisav2g; 2460 break; 2461 case SIBA_SPROMVAR_RSSISMC2G: 2462 *result = siba->siba_sprom.rssismc2g; 2463 break; 2464 case SIBA_SPROMVAR_RSSISMF2G: 2465 *result = siba->siba_sprom.rssismf2g; 2466 break; 2467 case SIBA_SPROMVAR_BXA2G: 2468 *result = siba->siba_sprom.bxa2g; 2469 break; 2470 case SIBA_SPROMVAR_RSSISAV5G: 2471 *result = siba->siba_sprom.rssisav5g; 2472 break; 2473 case SIBA_SPROMVAR_RSSISMC5G: 2474 *result = siba->siba_sprom.rssismc5g; 2475 break; 2476 case SIBA_SPROMVAR_RSSISMF5G: 2477 *result = siba->siba_sprom.rssismf5g; 2478 break; 2479 case SIBA_SPROMVAR_BXA5G: 2480 *result = siba->siba_sprom.bxa5g; 2481 break; 2482 case SIBA_SPROMVAR_CCK2GPO: 2483 *result = siba->siba_sprom.cck2gpo; 2484 break; 2485 case SIBA_SPROMVAR_OFDM2GPO: 2486 *result = siba->siba_sprom.ofdm2gpo; 2487 break; 2488 case SIBA_SPROMVAR_OFDM5GLPO: 2489 *result = siba->siba_sprom.ofdm5glpo; 2490 break; 2491 case SIBA_SPROMVAR_OFDM5GPO: 2492 *result = siba->siba_sprom.ofdm5gpo; 2493 break; 2494 case SIBA_SPROMVAR_OFDM5GHPO: 2495 *result = siba->siba_sprom.ofdm5ghpo; 2496 break; 2497 case SIBA_SPROMVAR_BF_LO: 2498 *result = siba->siba_sprom.bf_lo; 2499 break; 2500 case SIBA_SPROMVAR_BF_HI: 2501 *result = siba->siba_sprom.bf_hi; 2502 break; 2503 case SIBA_SPROMVAR_BF2_LO: 2504 *result = siba->siba_sprom.bf2_lo; 2505 break; 2506 case SIBA_SPROMVAR_BF2_HI: 2507 *result = siba->siba_sprom.bf2_hi; 2508 break; 2509 case SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS: 2510 *result = siba->siba_sprom.fem.ghz2.tssipos; 2511 break; 2512 case SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN: 2513 *result = siba->siba_sprom.fem.ghz2.extpa_gain; 2514 break; 2515 case SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE: 2516 *result = siba->siba_sprom.fem.ghz2.pdet_range; 2517 break; 2518 case SIBA_SPROMVAR_FEM_2GHZ_TR_ISO: 2519 *result = siba->siba_sprom.fem.ghz2.tr_iso; 2520 break; 2521 case SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT: 2522 *result = siba->siba_sprom.fem.ghz2.antswlut; 2523 break; 2524 case SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS: 2525 *result = siba->siba_sprom.fem.ghz5.tssipos; 2526 break; 2527 case SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN: 2528 *result = siba->siba_sprom.fem.ghz5.extpa_gain; 2529 break; 2530 case SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE: 2531 *result = siba->siba_sprom.fem.ghz5.pdet_range; 2532 break; 2533 case SIBA_SPROMVAR_FEM_5GHZ_TR_ISO: 2534 *result = siba->siba_sprom.fem.ghz5.tr_iso; 2535 break; 2536 case SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT: 2537 *result = siba->siba_sprom.fem.ghz5.antswlut; 2538 break; 2539 case SIBA_SPROMVAR_TXPID_2G_0: 2540 *result = siba->siba_sprom.txpid2g[0]; 2541 break; 2542 case SIBA_SPROMVAR_TXPID_2G_1: 2543 *result = siba->siba_sprom.txpid2g[1]; 2544 break; 2545 case SIBA_SPROMVAR_TXPID_2G_2: 2546 *result = siba->siba_sprom.txpid2g[2]; 2547 break; 2548 case SIBA_SPROMVAR_TXPID_2G_3: 2549 *result = siba->siba_sprom.txpid2g[3]; 2550 break; 2551 case SIBA_SPROMVAR_TXPID_5GL_0: 2552 *result = siba->siba_sprom.txpid5gl[0]; 2553 break; 2554 case SIBA_SPROMVAR_TXPID_5GL_1: 2555 *result = siba->siba_sprom.txpid5gl[1]; 2556 break; 2557 case SIBA_SPROMVAR_TXPID_5GL_2: 2558 *result = siba->siba_sprom.txpid5gl[2]; 2559 break; 2560 case SIBA_SPROMVAR_TXPID_5GL_3: 2561 *result = siba->siba_sprom.txpid5gl[3]; 2562 break; 2563 case SIBA_SPROMVAR_TXPID_5G_0: 2564 *result = siba->siba_sprom.txpid5g[0]; 2565 break; 2566 case SIBA_SPROMVAR_TXPID_5G_1: 2567 *result = siba->siba_sprom.txpid5g[1]; 2568 break; 2569 case SIBA_SPROMVAR_TXPID_5G_2: 2570 *result = siba->siba_sprom.txpid5g[2]; 2571 break; 2572 case SIBA_SPROMVAR_TXPID_5G_3: 2573 *result = siba->siba_sprom.txpid5g[3]; 2574 break; 2575 case SIBA_SPROMVAR_TXPID_5GH_0: 2576 *result = siba->siba_sprom.txpid5gh[0]; 2577 break; 2578 case SIBA_SPROMVAR_TXPID_5GH_1: 2579 *result = siba->siba_sprom.txpid5gh[1]; 2580 break; 2581 case SIBA_SPROMVAR_TXPID_5GH_2: 2582 *result = siba->siba_sprom.txpid5gh[2]; 2583 break; 2584 case SIBA_SPROMVAR_TXPID_5GH_3: 2585 *result = siba->siba_sprom.txpid5gh[3]; 2586 break; 2587 case SIBA_SPROMVAR_STBCPO: 2588 *result = siba->siba_sprom.stbcpo; 2589 break; 2590 case SIBA_SPROMVAR_CDDPO: 2591 *result = siba->siba_sprom.cddpo; 2592 break; 2593 default: 2594 return (ENOENT); 2595 } 2596 return (0); 2597 } 2598 2599 int 2600 siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value) 2601 { 2602 struct siba_dev_softc *sd = device_get_ivars(child); 2603 struct siba_softc *siba = sd->sd_bus; 2604 2605 switch (which) { 2606 case SIBA_SPROMVAR_REV: 2607 siba->siba_sprom.rev = value; 2608 break; 2609 case SIBA_SPROMVAR_MII_ETH0: 2610 siba->siba_sprom.mii_eth0 = value; 2611 break; 2612 case SIBA_SPROMVAR_MII_ETH1: 2613 siba->siba_sprom.mii_eth1 = value; 2614 break; 2615 case SIBA_SPROMVAR_MDIO_ETH0: 2616 siba->siba_sprom.mdio_eth0 = value; 2617 break; 2618 case SIBA_SPROMVAR_MDIO_ETH1: 2619 siba->siba_sprom.mdio_eth1 = value; 2620 break; 2621 case SIBA_SPROMVAR_BREV: 2622 siba->siba_sprom.brev = value; 2623 break; 2624 case SIBA_SPROMVAR_CCODE: 2625 siba->siba_sprom.ccode = value; 2626 break; 2627 case SIBA_SPROMVAR_ANT_A: 2628 siba->siba_sprom.ant_a = value; 2629 break; 2630 case SIBA_SPROMVAR_ANT_BG: 2631 siba->siba_sprom.ant_bg = value; 2632 break; 2633 case SIBA_SPROMVAR_PA0B0: 2634 siba->siba_sprom.pa0b0 = value; 2635 break; 2636 case SIBA_SPROMVAR_PA0B1: 2637 siba->siba_sprom.pa0b1 = value; 2638 break; 2639 case SIBA_SPROMVAR_PA0B2: 2640 siba->siba_sprom.pa0b2 = value; 2641 break; 2642 case SIBA_SPROMVAR_PA1B0: 2643 siba->siba_sprom.pa1b0 = value; 2644 break; 2645 case SIBA_SPROMVAR_PA1B1: 2646 siba->siba_sprom.pa1b1 = value; 2647 break; 2648 case SIBA_SPROMVAR_PA1B2: 2649 siba->siba_sprom.pa1b2 = value; 2650 break; 2651 case SIBA_SPROMVAR_PA1LOB0: 2652 siba->siba_sprom.pa1lob0 = value; 2653 break; 2654 case SIBA_SPROMVAR_PA1LOB1: 2655 siba->siba_sprom.pa1lob1 = value; 2656 break; 2657 case SIBA_SPROMVAR_PA1LOB2: 2658 siba->siba_sprom.pa1lob2 = value; 2659 break; 2660 case SIBA_SPROMVAR_PA1HIB0: 2661 siba->siba_sprom.pa1hib0 = value; 2662 break; 2663 case SIBA_SPROMVAR_PA1HIB1: 2664 siba->siba_sprom.pa1hib1 = value; 2665 break; 2666 case SIBA_SPROMVAR_PA1HIB2: 2667 siba->siba_sprom.pa1hib2 = value; 2668 break; 2669 case SIBA_SPROMVAR_GPIO0: 2670 siba->siba_sprom.gpio0 = value; 2671 break; 2672 case SIBA_SPROMVAR_GPIO1: 2673 siba->siba_sprom.gpio1 = value; 2674 break; 2675 case SIBA_SPROMVAR_GPIO2: 2676 siba->siba_sprom.gpio2 = value; 2677 break; 2678 case SIBA_SPROMVAR_GPIO3: 2679 siba->siba_sprom.gpio3 = value; 2680 break; 2681 case SIBA_SPROMVAR_MAXPWR_AL: 2682 siba->siba_sprom.maxpwr_al = value; 2683 break; 2684 case SIBA_SPROMVAR_MAXPWR_A: 2685 siba->siba_sprom.maxpwr_a = value; 2686 break; 2687 case SIBA_SPROMVAR_MAXPWR_AH: 2688 siba->siba_sprom.maxpwr_ah = value; 2689 break; 2690 case SIBA_SPROMVAR_MAXPWR_BG: 2691 siba->siba_sprom.maxpwr_bg = value; 2692 break; 2693 case SIBA_SPROMVAR_RXPO2G: 2694 siba->siba_sprom.rxpo2g = value; 2695 break; 2696 case SIBA_SPROMVAR_RXPO5G: 2697 siba->siba_sprom.rxpo5g = value; 2698 break; 2699 case SIBA_SPROMVAR_TSSI_A: 2700 siba->siba_sprom.tssi_a = value; 2701 break; 2702 case SIBA_SPROMVAR_TSSI_BG: 2703 siba->siba_sprom.tssi_bg = value; 2704 break; 2705 case SIBA_SPROMVAR_TRI2G: 2706 siba->siba_sprom.tri2g = value; 2707 break; 2708 case SIBA_SPROMVAR_TRI5GL: 2709 siba->siba_sprom.tri5gl = value; 2710 break; 2711 case SIBA_SPROMVAR_TRI5G: 2712 siba->siba_sprom.tri5g = value; 2713 break; 2714 case SIBA_SPROMVAR_TRI5GH: 2715 siba->siba_sprom.tri5gh = value; 2716 break; 2717 case SIBA_SPROMVAR_RSSISAV2G: 2718 siba->siba_sprom.rssisav2g = value; 2719 break; 2720 case SIBA_SPROMVAR_RSSISMC2G: 2721 siba->siba_sprom.rssismc2g = value; 2722 break; 2723 case SIBA_SPROMVAR_RSSISMF2G: 2724 siba->siba_sprom.rssismf2g = value; 2725 break; 2726 case SIBA_SPROMVAR_BXA2G: 2727 siba->siba_sprom.bxa2g = value; 2728 break; 2729 case SIBA_SPROMVAR_RSSISAV5G: 2730 siba->siba_sprom.rssisav5g = value; 2731 break; 2732 case SIBA_SPROMVAR_RSSISMC5G: 2733 siba->siba_sprom.rssismc5g = value; 2734 break; 2735 case SIBA_SPROMVAR_RSSISMF5G: 2736 siba->siba_sprom.rssismf5g = value; 2737 break; 2738 case SIBA_SPROMVAR_BXA5G: 2739 siba->siba_sprom.bxa5g = value; 2740 break; 2741 case SIBA_SPROMVAR_CCK2GPO: 2742 siba->siba_sprom.cck2gpo = value; 2743 break; 2744 case SIBA_SPROMVAR_OFDM2GPO: 2745 siba->siba_sprom.ofdm2gpo = value; 2746 break; 2747 case SIBA_SPROMVAR_OFDM5GLPO: 2748 siba->siba_sprom.ofdm5glpo = value; 2749 break; 2750 case SIBA_SPROMVAR_OFDM5GPO: 2751 siba->siba_sprom.ofdm5gpo = value; 2752 break; 2753 case SIBA_SPROMVAR_OFDM5GHPO: 2754 siba->siba_sprom.ofdm5ghpo = value; 2755 break; 2756 case SIBA_SPROMVAR_BF_LO: 2757 siba->siba_sprom.bf_lo = value; 2758 break; 2759 case SIBA_SPROMVAR_BF_HI: 2760 siba->siba_sprom.bf_hi = value; 2761 break; 2762 case SIBA_SPROMVAR_BF2_LO: 2763 siba->siba_sprom.bf2_lo = value; 2764 break; 2765 case SIBA_SPROMVAR_BF2_HI: 2766 siba->siba_sprom.bf2_hi = value; 2767 break; 2768 default: 2769 return (ENOENT); 2770 } 2771 return (0); 2772 } 2773 2774 #define SIBA_GPIOCTL 0x06c 2775 2776 uint32_t 2777 siba_gpio_get(device_t dev) 2778 { 2779 struct siba_dev_softc *sd = device_get_ivars(dev); 2780 struct siba_softc *siba = sd->sd_bus; 2781 struct siba_dev_softc *gpiodev, *pcidev = NULL; 2782 2783 pcidev = siba->siba_pci.spc_dev; 2784 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; 2785 if (!gpiodev) 2786 return (-1); 2787 return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL)); 2788 } 2789 2790 void 2791 siba_gpio_set(device_t dev, uint32_t value) 2792 { 2793 struct siba_dev_softc *sd = device_get_ivars(dev); 2794 struct siba_softc *siba = sd->sd_bus; 2795 struct siba_dev_softc *gpiodev, *pcidev = NULL; 2796 2797 pcidev = siba->siba_pci.spc_dev; 2798 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; 2799 if (!gpiodev) 2800 return; 2801 siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value); 2802 } 2803 2804 void 2805 siba_fix_imcfglobug(device_t dev) 2806 { 2807 struct siba_dev_softc *sd = device_get_ivars(dev); 2808 struct siba_softc *siba = sd->sd_bus; 2809 uint32_t tmp; 2810 2811 if (siba->siba_pci.spc_dev == NULL) 2812 return; 2813 if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI || 2814 siba->siba_pci.spc_dev->sd_id.sd_rev > 5) 2815 return; 2816 2817 tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) & 2818 ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO); 2819 switch (siba->siba_type) { 2820 case SIBA_TYPE_PCI: 2821 case SIBA_TYPE_PCMCIA: 2822 tmp |= 0x32; 2823 break; 2824 case SIBA_TYPE_SSB: 2825 tmp |= 0x53; 2826 break; 2827 } 2828 siba_write_4_sub(sd, SIBA_IMCFGLO, tmp); 2829 } 2830 2831 int 2832 siba_sprom_get_core_power_info(device_t dev, int core, 2833 struct siba_sprom_core_pwr_info *c) 2834 { 2835 struct siba_dev_softc *sd = device_get_ivars(dev); 2836 struct siba_softc *siba = sd->sd_bus; 2837 2838 if (core < 0 || core > 3) { 2839 return (EINVAL); 2840 } 2841 memcpy(c, &siba->siba_sprom.core_pwr_info[core], sizeof(*c)); 2842 return (0); 2843 } 2844 2845 int 2846 siba_sprom_get_mcs2gpo(device_t dev, uint16_t *c) 2847 { 2848 struct siba_dev_softc *sd = device_get_ivars(dev); 2849 struct siba_softc *siba = sd->sd_bus; 2850 2851 memcpy(c, &siba->siba_sprom.mcs2gpo, sizeof(uint16_t) * 8); 2852 return (0); 2853 } 2854 2855 int 2856 siba_sprom_get_mcs5glpo(device_t dev, uint16_t *c) 2857 { 2858 struct siba_dev_softc *sd = device_get_ivars(dev); 2859 struct siba_softc *siba = sd->sd_bus; 2860 2861 memcpy(c, &siba->siba_sprom.mcs5glpo, sizeof(uint16_t) * 8); 2862 return (0); 2863 } 2864 2865 int 2866 siba_sprom_get_mcs5gpo(device_t dev, uint16_t *c) 2867 { 2868 struct siba_dev_softc *sd = device_get_ivars(dev); 2869 struct siba_softc *siba = sd->sd_bus; 2870 2871 memcpy(c, &siba->siba_sprom.mcs5gpo, sizeof(uint16_t) * 8); 2872 return (0); 2873 } 2874 2875 int 2876 siba_sprom_get_mcs5ghpo(device_t dev, uint16_t *c) 2877 { 2878 struct siba_dev_softc *sd = device_get_ivars(dev); 2879 struct siba_softc *siba = sd->sd_bus; 2880 2881 memcpy(c, &siba->siba_sprom.mcs5ghpo, sizeof(uint16_t) * 8); 2882 return (0); 2883 } 2884 2885 void 2886 siba_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid) 2887 { 2888 struct siba_dev_softc *sd = device_get_ivars(dev); 2889 struct siba_softc *siba = sd->sd_bus; 2890 struct siba_cc *scc; 2891 2892 scc = &siba->siba_cc; 2893 2894 if (scc->scc_dev == NULL) { 2895 device_printf(dev, "%s: called; no pmu\n", __func__); 2896 return; 2897 } 2898 2899 switch (siba_get_chipid(dev)) { 2900 case 0x4322: 2901 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100070); 2902 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x1014140a); 2903 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888854); 2904 if (spur_avoid == 1) 2905 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05201828); 2906 else 2907 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05001828); 2908 break; 2909 case 43222: 2910 if (spur_avoid == 1) { 2911 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11500008); 2912 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0C000C06); 2913 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x0F600a08); 2914 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000); 2915 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x2001E920); 2916 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888815); 2917 } else { 2918 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100008); 2919 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0c000c06); 2920 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x03000a08); 2921 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000); 2922 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x200005c0); 2923 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888855); 2924 } 2925 break; 2926 default: 2927 device_printf(dev, 2928 "%s: unknown spur avoidance settings for chip 0x%04x\n", 2929 __func__, 2930 siba_get_chipid(dev)); 2931 return; 2932 } 2933 2934 /* Both chips above use the same update */ 2935 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_PLL_UPD); 2936 } 2937 2938 void 2939 siba_cc_set32(device_t dev, uint32_t reg, uint32_t val) 2940 { 2941 struct siba_dev_softc *sd = device_get_ivars(dev); 2942 struct siba_softc *siba = sd->sd_bus; 2943 struct siba_cc *scc; 2944 2945 scc = &siba->siba_cc; 2946 2947 if (scc->scc_dev == NULL) { 2948 device_printf(dev, "%s: called; no pmu\n", __func__); 2949 return; 2950 } 2951 2952 SIBA_CC_SET32(scc, reg, val); 2953 } 2954 2955 void 2956 siba_cc_mask32(device_t dev, uint32_t reg, uint32_t mask) 2957 { 2958 struct siba_dev_softc *sd = device_get_ivars(dev); 2959 struct siba_softc *siba = sd->sd_bus; 2960 struct siba_cc *scc; 2961 2962 scc = &siba->siba_cc; 2963 2964 if (scc->scc_dev == NULL) { 2965 device_printf(dev, "%s: called; no pmu\n", __func__); 2966 return; 2967 } 2968 2969 SIBA_CC_MASK32(scc, reg, mask); 2970 } 2971 2972 uint32_t 2973 siba_cc_read32(device_t dev, uint32_t reg) 2974 { 2975 struct siba_dev_softc *sd = device_get_ivars(dev); 2976 struct siba_softc *siba = sd->sd_bus; 2977 struct siba_cc *scc; 2978 2979 scc = &siba->siba_cc; 2980 2981 if (scc->scc_dev == NULL) { 2982 device_printf(dev, "%s: called; no pmu\n", __func__); 2983 return 0xffffffff; 2984 } 2985 2986 return SIBA_CC_READ32(scc, reg); 2987 } 2988 2989 void 2990 siba_cc_write32(device_t dev, uint32_t reg, uint32_t val) 2991 { 2992 struct siba_dev_softc *sd = device_get_ivars(dev); 2993 struct siba_softc *siba = sd->sd_bus; 2994 struct siba_cc *scc; 2995 2996 scc = &siba->siba_cc; 2997 2998 if (scc->scc_dev == NULL) { 2999 device_printf(dev, "%s: called; no pmu\n", __func__); 3000 return; 3001 } 3002 3003 SIBA_CC_WRITE32(scc, reg, val); 3004 } 3005