1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.8 2004/01/06 01:40:47 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 36 */ 37 38 /* 39 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 40 * series chips and several workalikes including the following: 41 * 42 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 43 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 44 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 45 * ASIX Electronics AX88140A (www.asix.com.tw) 46 * ASIX Electronics AX88141 (www.asix.com.tw) 47 * ADMtek AL981 (www.admtek.com.tw) 48 * ADMtek AN985 (www.admtek.com.tw) 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Conexant LANfinity (www.conexant.com) 52 * 53 * Datasheets for the 21143 are available at developer.intel.com. 54 * Datasheets for the clone parts can be found at their respective sites. 55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 56 * The PNIC II is essentially a Macronix 98715A chip; the only difference 57 * worth noting is that its multicast hash table is only 128 bits wide 58 * instead of 512. 59 * 60 * Written by Bill Paul <wpaul@ee.columbia.edu> 61 * Electrical Engineering Department 62 * Columbia University, New York City 63 */ 64 65 /* 66 * The Intel 21143 is the successor to the DEC 21140. It is basically 67 * the same as the 21140 but with a few new features. The 21143 supports 68 * three kinds of media attachments: 69 * 70 * o MII port, for 10Mbps and 100Mbps support and NWAY 71 * autonegotiation provided by an external PHY. 72 * o SYM port, for symbol mode 100Mbps support. 73 * o 10baseT port. 74 * o AUI/BNC port. 75 * 76 * The 100Mbps SYM port and 10baseT port can be used together in 77 * combination with the internal NWAY support to create a 10/100 78 * autosensing configuration. 79 * 80 * Note that not all tulip workalikes are handled in this driver: we only 81 * deal with those which are relatively well behaved. The Winbond is 82 * handled separately due to its different register offsets and the 83 * special handling needed for its various bugs. The PNIC is handled 84 * here, but I'm not thrilled about it. 85 * 86 * All of the workalike chips use some form of MII transceiver support 87 * with the exception of the Macronix chips, which also have a SYM port. 88 * The ASIX AX88140A is also documented to have a SYM port, but all 89 * the cards I've seen use an MII transceiver, probably because the 90 * AX88140A doesn't support internal NWAY. 91 */ 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/sysctl.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/vlan/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/clock.h> /* for DELAY */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include "../mii_layer/mii.h" 123 #include "../mii_layer/miivar.h" 124 125 #include <bus/pci/pcireg.h> 126 #include <bus/pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include "if_dcreg.h" 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct dc_type dc_devs[] = { 142 { DC_VENDORID_DEC, DC_DEVICEID_21143, 143 "Intel 21143 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 145 "Davicom DM9009 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 147 "Davicom DM9100 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 149 "Davicom DM9102 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 151 "Davicom DM9102A 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 153 "ADMtek AL981 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 155 "ADMtek AN985 10/100BaseTX" }, 156 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 157 "ASIX AX88140A 10/100BaseTX" }, 158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 159 "ASIX AX88141 10/100BaseTX" }, 160 { DC_VENDORID_MX, DC_DEVICEID_98713, 161 "Macronix 98713 10/100BaseTX" }, 162 { DC_VENDORID_MX, DC_DEVICEID_98713, 163 "Macronix 98713A 10/100BaseTX" }, 164 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 165 "Compex RL100-TX 10/100BaseTX" }, 166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 167 "Compex RL100-TX 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98715/98715A 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98715AEC-C 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98725 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_98727, 175 "Macronix 98727/98732 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C115, 177 "LC82C115 PNIC II 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C168, 179 "82c168 PNIC 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C168, 181 "82c169 PNIC 10/100BaseTX" }, 182 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 183 "Accton EN1217 10/100BaseTX" }, 184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 185 "Accton EN2242 MiniPCI 10/100BaseTX" }, 186 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 187 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 188 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 189 "3Com OfficeConnect 10/100B" }, 190 { 0, 0, NULL } 191 }; 192 193 static int dc_probe (device_t); 194 static int dc_attach (device_t); 195 static int dc_detach (device_t); 196 static int dc_suspend (device_t); 197 static int dc_resume (device_t); 198 static void dc_acpi (device_t); 199 static struct dc_type *dc_devtype (device_t); 200 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 201 static int dc_encap (struct dc_softc *, struct mbuf *, 202 u_int32_t *); 203 static int dc_coal (struct dc_softc *, struct mbuf **); 204 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 205 static int dc_rx_resync (struct dc_softc *); 206 static void dc_rxeof (struct dc_softc *); 207 static void dc_txeof (struct dc_softc *); 208 static void dc_tick (void *); 209 static void dc_tx_underrun (struct dc_softc *); 210 static void dc_intr (void *); 211 static void dc_start (struct ifnet *); 212 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 213 static void dc_init (void *); 214 static void dc_stop (struct dc_softc *); 215 static void dc_watchdog (struct ifnet *); 216 static void dc_shutdown (device_t); 217 static int dc_ifmedia_upd (struct ifnet *); 218 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 219 220 static void dc_delay (struct dc_softc *); 221 static void dc_eeprom_idle (struct dc_softc *); 222 static void dc_eeprom_putbyte (struct dc_softc *, int); 223 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 224 static void dc_eeprom_getword_pnic 225 (struct dc_softc *, int, u_int16_t *); 226 static void dc_eeprom_width (struct dc_softc *); 227 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 228 int, int); 229 230 static void dc_mii_writebit (struct dc_softc *, int); 231 static int dc_mii_readbit (struct dc_softc *); 232 static void dc_mii_sync (struct dc_softc *); 233 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 234 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 235 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 236 static int dc_miibus_readreg (device_t, int, int); 237 static int dc_miibus_writereg (device_t, int, int, int); 238 static void dc_miibus_statchg (device_t); 239 static void dc_miibus_mediainit (device_t); 240 241 static void dc_setcfg (struct dc_softc *, int); 242 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 243 static u_int32_t dc_crc_be (caddr_t); 244 static void dc_setfilt_21143 (struct dc_softc *); 245 static void dc_setfilt_asix (struct dc_softc *); 246 static void dc_setfilt_admtek (struct dc_softc *); 247 248 static void dc_setfilt (struct dc_softc *); 249 250 static void dc_reset (struct dc_softc *); 251 static int dc_list_rx_init (struct dc_softc *); 252 static int dc_list_tx_init (struct dc_softc *); 253 254 static void dc_read_srom (struct dc_softc *, int); 255 static void dc_parse_21143_srom (struct dc_softc *); 256 static void dc_decode_leaf_sia (struct dc_softc *, 257 struct dc_eblock_sia *); 258 static void dc_decode_leaf_mii (struct dc_softc *, 259 struct dc_eblock_mii *); 260 static void dc_decode_leaf_sym (struct dc_softc *, 261 struct dc_eblock_sym *); 262 static void dc_apply_fixup (struct dc_softc *, int); 263 264 #ifdef DC_USEIOSPACE 265 #define DC_RES SYS_RES_IOPORT 266 #define DC_RID DC_PCI_CFBIO 267 #else 268 #define DC_RES SYS_RES_MEMORY 269 #define DC_RID DC_PCI_CFBMA 270 #endif 271 272 static device_method_t dc_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, dc_probe), 275 DEVMETHOD(device_attach, dc_attach), 276 DEVMETHOD(device_detach, dc_detach), 277 DEVMETHOD(device_suspend, dc_suspend), 278 DEVMETHOD(device_resume, dc_resume), 279 DEVMETHOD(device_shutdown, dc_shutdown), 280 281 /* bus interface */ 282 DEVMETHOD(bus_print_child, bus_generic_print_child), 283 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 284 285 /* MII interface */ 286 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 287 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 288 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 289 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 290 291 { 0, 0 } 292 }; 293 294 static driver_t dc_driver = { 295 "dc", 296 dc_methods, 297 sizeof(struct dc_softc) 298 }; 299 300 static devclass_t dc_devclass; 301 302 #ifdef __i386__ 303 static int dc_quick=1; 304 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 305 &dc_quick,0,"do not mdevget in dc driver"); 306 #endif 307 308 DECLARE_DUMMY_MODULE(if_dc); 309 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 310 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 311 312 #define DC_SETBIT(sc, reg, x) \ 313 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 314 315 #define DC_CLRBIT(sc, reg, x) \ 316 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 317 318 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 319 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 320 321 static void dc_delay(sc) 322 struct dc_softc *sc; 323 { 324 int idx; 325 326 for (idx = (300 / 33) + 1; idx > 0; idx--) 327 CSR_READ_4(sc, DC_BUSCTL); 328 } 329 330 static void dc_eeprom_width(sc) 331 struct dc_softc *sc; 332 { 333 int i; 334 335 /* Force EEPROM to idle state. */ 336 dc_eeprom_idle(sc); 337 338 /* Enter EEPROM access mode. */ 339 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 340 dc_delay(sc); 341 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 342 dc_delay(sc); 343 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 344 dc_delay(sc); 345 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 346 dc_delay(sc); 347 348 for (i = 3; i--;) { 349 if (6 & (1 << i)) 350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 351 else 352 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 353 dc_delay(sc); 354 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 355 dc_delay(sc); 356 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 357 dc_delay(sc); 358 } 359 360 for (i = 1; i <= 12; i++) { 361 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 362 dc_delay(sc); 363 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 364 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 365 dc_delay(sc); 366 break; 367 } 368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 369 dc_delay(sc); 370 } 371 372 /* Turn off EEPROM access mode. */ 373 dc_eeprom_idle(sc); 374 375 if (i < 4 || i > 12) 376 sc->dc_romwidth = 6; 377 else 378 sc->dc_romwidth = i; 379 380 /* Enter EEPROM access mode. */ 381 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 382 dc_delay(sc); 383 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 384 dc_delay(sc); 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 386 dc_delay(sc); 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 388 dc_delay(sc); 389 390 /* Turn off EEPROM access mode. */ 391 dc_eeprom_idle(sc); 392 } 393 394 static void dc_eeprom_idle(sc) 395 struct dc_softc *sc; 396 { 397 int i; 398 399 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 400 dc_delay(sc); 401 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 402 dc_delay(sc); 403 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 404 dc_delay(sc); 405 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 406 dc_delay(sc); 407 408 for (i = 0; i < 25; i++) { 409 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 410 dc_delay(sc); 411 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 } 414 415 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 416 dc_delay(sc); 417 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 418 dc_delay(sc); 419 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 420 421 return; 422 } 423 424 /* 425 * Send a read command and address to the EEPROM, check for ACK. 426 */ 427 static void dc_eeprom_putbyte(sc, addr) 428 struct dc_softc *sc; 429 int addr; 430 { 431 int d, i; 432 433 d = DC_EECMD_READ >> 6; 434 for (i = 3; i--; ) { 435 if (d & (1 << i)) 436 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 437 else 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 439 dc_delay(sc); 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 441 dc_delay(sc); 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 } 445 446 /* 447 * Feed in each bit and strobe the clock. 448 */ 449 for (i = sc->dc_romwidth; i--;) { 450 if (addr & (1 << i)) { 451 SIO_SET(DC_SIO_EE_DATAIN); 452 } else { 453 SIO_CLR(DC_SIO_EE_DATAIN); 454 } 455 dc_delay(sc); 456 SIO_SET(DC_SIO_EE_CLK); 457 dc_delay(sc); 458 SIO_CLR(DC_SIO_EE_CLK); 459 dc_delay(sc); 460 } 461 462 return; 463 } 464 465 /* 466 * Read a word of data stored in the EEPROM at address 'addr.' 467 * The PNIC 82c168/82c169 has its own non-standard way to read 468 * the EEPROM. 469 */ 470 static void dc_eeprom_getword_pnic(sc, addr, dest) 471 struct dc_softc *sc; 472 int addr; 473 u_int16_t *dest; 474 { 475 int i; 476 u_int32_t r; 477 478 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 479 480 for (i = 0; i < DC_TIMEOUT; i++) { 481 DELAY(1); 482 r = CSR_READ_4(sc, DC_SIO); 483 if (!(r & DC_PN_SIOCTL_BUSY)) { 484 *dest = (u_int16_t)(r & 0xFFFF); 485 return; 486 } 487 } 488 489 return; 490 } 491 492 /* 493 * Read a word of data stored in the EEPROM at address 'addr.' 494 */ 495 static void dc_eeprom_getword(sc, addr, dest) 496 struct dc_softc *sc; 497 int addr; 498 u_int16_t *dest; 499 { 500 int i; 501 u_int16_t word = 0; 502 503 /* Force EEPROM to idle state. */ 504 dc_eeprom_idle(sc); 505 506 /* Enter EEPROM access mode. */ 507 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 508 dc_delay(sc); 509 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 510 dc_delay(sc); 511 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 512 dc_delay(sc); 513 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 514 dc_delay(sc); 515 516 /* 517 * Send address of word we want to read. 518 */ 519 dc_eeprom_putbyte(sc, addr); 520 521 /* 522 * Start reading bits from EEPROM. 523 */ 524 for (i = 0x8000; i; i >>= 1) { 525 SIO_SET(DC_SIO_EE_CLK); 526 dc_delay(sc); 527 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 528 word |= i; 529 dc_delay(sc); 530 SIO_CLR(DC_SIO_EE_CLK); 531 dc_delay(sc); 532 } 533 534 /* Turn off EEPROM access mode. */ 535 dc_eeprom_idle(sc); 536 537 *dest = word; 538 539 return; 540 } 541 542 /* 543 * Read a sequence of words from the EEPROM. 544 */ 545 static void dc_read_eeprom(sc, dest, off, cnt, swap) 546 struct dc_softc *sc; 547 caddr_t dest; 548 int off; 549 int cnt; 550 int swap; 551 { 552 int i; 553 u_int16_t word = 0, *ptr; 554 555 for (i = 0; i < cnt; i++) { 556 if (DC_IS_PNIC(sc)) 557 dc_eeprom_getword_pnic(sc, off + i, &word); 558 else 559 dc_eeprom_getword(sc, off + i, &word); 560 ptr = (u_int16_t *)(dest + (i * 2)); 561 if (swap) 562 *ptr = ntohs(word); 563 else 564 *ptr = word; 565 } 566 567 return; 568 } 569 570 /* 571 * The following two routines are taken from the Macronix 98713 572 * Application Notes pp.19-21. 573 */ 574 /* 575 * Write a bit to the MII bus. 576 */ 577 static void dc_mii_writebit(sc, bit) 578 struct dc_softc *sc; 579 int bit; 580 { 581 if (bit) 582 CSR_WRITE_4(sc, DC_SIO, 583 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 584 else 585 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 586 587 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 588 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 589 590 return; 591 } 592 593 /* 594 * Read a bit from the MII bus. 595 */ 596 static int dc_mii_readbit(sc) 597 struct dc_softc *sc; 598 { 599 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 600 CSR_READ_4(sc, DC_SIO); 601 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 602 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 603 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 604 return(1); 605 606 return(0); 607 } 608 609 /* 610 * Sync the PHYs by setting data bit and strobing the clock 32 times. 611 */ 612 static void dc_mii_sync(sc) 613 struct dc_softc *sc; 614 { 615 int i; 616 617 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 618 619 for (i = 0; i < 32; i++) 620 dc_mii_writebit(sc, 1); 621 622 return; 623 } 624 625 /* 626 * Clock a series of bits through the MII. 627 */ 628 static void dc_mii_send(sc, bits, cnt) 629 struct dc_softc *sc; 630 u_int32_t bits; 631 int cnt; 632 { 633 int i; 634 635 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 636 dc_mii_writebit(sc, bits & i); 637 } 638 639 /* 640 * Read an PHY register through the MII. 641 */ 642 static int dc_mii_readreg(sc, frame) 643 struct dc_softc *sc; 644 struct dc_mii_frame *frame; 645 646 { 647 int i, ack, s; 648 649 s = splimp(); 650 651 /* 652 * Set up frame for RX. 653 */ 654 frame->mii_stdelim = DC_MII_STARTDELIM; 655 frame->mii_opcode = DC_MII_READOP; 656 frame->mii_turnaround = 0; 657 frame->mii_data = 0; 658 659 /* 660 * Sync the PHYs. 661 */ 662 dc_mii_sync(sc); 663 664 /* 665 * Send command/address info. 666 */ 667 dc_mii_send(sc, frame->mii_stdelim, 2); 668 dc_mii_send(sc, frame->mii_opcode, 2); 669 dc_mii_send(sc, frame->mii_phyaddr, 5); 670 dc_mii_send(sc, frame->mii_regaddr, 5); 671 672 #ifdef notdef 673 /* Idle bit */ 674 dc_mii_writebit(sc, 1); 675 dc_mii_writebit(sc, 0); 676 #endif 677 678 /* Check for ack */ 679 ack = dc_mii_readbit(sc); 680 681 /* 682 * Now try reading data bits. If the ack failed, we still 683 * need to clock through 16 cycles to keep the PHY(s) in sync. 684 */ 685 if (ack) { 686 for(i = 0; i < 16; i++) { 687 dc_mii_readbit(sc); 688 } 689 goto fail; 690 } 691 692 for (i = 0x8000; i; i >>= 1) { 693 if (!ack) { 694 if (dc_mii_readbit(sc)) 695 frame->mii_data |= i; 696 } 697 } 698 699 fail: 700 701 dc_mii_writebit(sc, 0); 702 dc_mii_writebit(sc, 0); 703 704 splx(s); 705 706 if (ack) 707 return(1); 708 return(0); 709 } 710 711 /* 712 * Write to a PHY register through the MII. 713 */ 714 static int dc_mii_writereg(sc, frame) 715 struct dc_softc *sc; 716 struct dc_mii_frame *frame; 717 718 { 719 int s; 720 721 s = splimp(); 722 /* 723 * Set up frame for TX. 724 */ 725 726 frame->mii_stdelim = DC_MII_STARTDELIM; 727 frame->mii_opcode = DC_MII_WRITEOP; 728 frame->mii_turnaround = DC_MII_TURNAROUND; 729 730 /* 731 * Sync the PHYs. 732 */ 733 dc_mii_sync(sc); 734 735 dc_mii_send(sc, frame->mii_stdelim, 2); 736 dc_mii_send(sc, frame->mii_opcode, 2); 737 dc_mii_send(sc, frame->mii_phyaddr, 5); 738 dc_mii_send(sc, frame->mii_regaddr, 5); 739 dc_mii_send(sc, frame->mii_turnaround, 2); 740 dc_mii_send(sc, frame->mii_data, 16); 741 742 /* Idle bit. */ 743 dc_mii_writebit(sc, 0); 744 dc_mii_writebit(sc, 0); 745 746 splx(s); 747 748 return(0); 749 } 750 751 static int dc_miibus_readreg(dev, phy, reg) 752 device_t dev; 753 int phy, reg; 754 { 755 struct dc_mii_frame frame; 756 struct dc_softc *sc; 757 int i, rval, phy_reg = 0; 758 759 sc = device_get_softc(dev); 760 bzero((char *)&frame, sizeof(frame)); 761 762 /* 763 * Note: both the AL981 and AN985 have internal PHYs, 764 * however the AL981 provides direct access to the PHY 765 * registers while the AN985 uses a serial MII interface. 766 * The AN985's MII interface is also buggy in that you 767 * can read from any MII address (0 to 31), but only address 1 768 * behaves normally. To deal with both cases, we pretend 769 * that the PHY is at MII address 1. 770 */ 771 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 772 return(0); 773 774 /* 775 * Note: the ukphy probes of the RS7112 report a PHY at 776 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 777 * so we only respond to correct one. 778 */ 779 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 780 return(0); 781 782 if (sc->dc_pmode != DC_PMODE_MII) { 783 if (phy == (MII_NPHY - 1)) { 784 switch(reg) { 785 case MII_BMSR: 786 /* 787 * Fake something to make the probe 788 * code think there's a PHY here. 789 */ 790 return(BMSR_MEDIAMASK); 791 break; 792 case MII_PHYIDR1: 793 if (DC_IS_PNIC(sc)) 794 return(DC_VENDORID_LO); 795 return(DC_VENDORID_DEC); 796 break; 797 case MII_PHYIDR2: 798 if (DC_IS_PNIC(sc)) 799 return(DC_DEVICEID_82C168); 800 return(DC_DEVICEID_21143); 801 break; 802 default: 803 return(0); 804 break; 805 } 806 } else 807 return(0); 808 } 809 810 if (DC_IS_PNIC(sc)) { 811 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 812 (phy << 23) | (reg << 18)); 813 for (i = 0; i < DC_TIMEOUT; i++) { 814 DELAY(1); 815 rval = CSR_READ_4(sc, DC_PN_MII); 816 if (!(rval & DC_PN_MII_BUSY)) { 817 rval &= 0xFFFF; 818 return(rval == 0xFFFF ? 0 : rval); 819 } 820 } 821 return(0); 822 } 823 824 if (DC_IS_COMET(sc)) { 825 switch(reg) { 826 case MII_BMCR: 827 phy_reg = DC_AL_BMCR; 828 break; 829 case MII_BMSR: 830 phy_reg = DC_AL_BMSR; 831 break; 832 case MII_PHYIDR1: 833 phy_reg = DC_AL_VENID; 834 break; 835 case MII_PHYIDR2: 836 phy_reg = DC_AL_DEVID; 837 break; 838 case MII_ANAR: 839 phy_reg = DC_AL_ANAR; 840 break; 841 case MII_ANLPAR: 842 phy_reg = DC_AL_LPAR; 843 break; 844 case MII_ANER: 845 phy_reg = DC_AL_ANER; 846 break; 847 default: 848 printf("dc%d: phy_read: bad phy register %x\n", 849 sc->dc_unit, reg); 850 return(0); 851 break; 852 } 853 854 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 855 856 if (rval == 0xFFFF) 857 return(0); 858 return(rval); 859 } 860 861 frame.mii_phyaddr = phy; 862 frame.mii_regaddr = reg; 863 if (sc->dc_type == DC_TYPE_98713) { 864 phy_reg = CSR_READ_4(sc, DC_NETCFG); 865 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 866 } 867 dc_mii_readreg(sc, &frame); 868 if (sc->dc_type == DC_TYPE_98713) 869 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 870 871 return(frame.mii_data); 872 } 873 874 static int dc_miibus_writereg(dev, phy, reg, data) 875 device_t dev; 876 int phy, reg, data; 877 { 878 struct dc_softc *sc; 879 struct dc_mii_frame frame; 880 int i, phy_reg = 0; 881 882 sc = device_get_softc(dev); 883 bzero((char *)&frame, sizeof(frame)); 884 885 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 886 return(0); 887 888 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 889 return(0); 890 891 if (DC_IS_PNIC(sc)) { 892 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 893 (phy << 23) | (reg << 10) | data); 894 for (i = 0; i < DC_TIMEOUT; i++) { 895 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 896 break; 897 } 898 return(0); 899 } 900 901 if (DC_IS_COMET(sc)) { 902 switch(reg) { 903 case MII_BMCR: 904 phy_reg = DC_AL_BMCR; 905 break; 906 case MII_BMSR: 907 phy_reg = DC_AL_BMSR; 908 break; 909 case MII_PHYIDR1: 910 phy_reg = DC_AL_VENID; 911 break; 912 case MII_PHYIDR2: 913 phy_reg = DC_AL_DEVID; 914 break; 915 case MII_ANAR: 916 phy_reg = DC_AL_ANAR; 917 break; 918 case MII_ANLPAR: 919 phy_reg = DC_AL_LPAR; 920 break; 921 case MII_ANER: 922 phy_reg = DC_AL_ANER; 923 break; 924 default: 925 printf("dc%d: phy_write: bad phy register %x\n", 926 sc->dc_unit, reg); 927 return(0); 928 break; 929 } 930 931 CSR_WRITE_4(sc, phy_reg, data); 932 return(0); 933 } 934 935 frame.mii_phyaddr = phy; 936 frame.mii_regaddr = reg; 937 frame.mii_data = data; 938 939 if (sc->dc_type == DC_TYPE_98713) { 940 phy_reg = CSR_READ_4(sc, DC_NETCFG); 941 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 942 } 943 dc_mii_writereg(sc, &frame); 944 if (sc->dc_type == DC_TYPE_98713) 945 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 946 947 return(0); 948 } 949 950 static void dc_miibus_statchg(dev) 951 device_t dev; 952 { 953 struct dc_softc *sc; 954 struct mii_data *mii; 955 struct ifmedia *ifm; 956 957 sc = device_get_softc(dev); 958 if (DC_IS_ADMTEK(sc)) 959 return; 960 961 mii = device_get_softc(sc->dc_miibus); 962 ifm = &mii->mii_media; 963 if (DC_IS_DAVICOM(sc) && 964 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 965 dc_setcfg(sc, ifm->ifm_media); 966 sc->dc_if_media = ifm->ifm_media; 967 } else { 968 dc_setcfg(sc, mii->mii_media_active); 969 sc->dc_if_media = mii->mii_media_active; 970 } 971 972 return; 973 } 974 975 /* 976 * Special support for DM9102A cards with HomePNA PHYs. Note: 977 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 978 * to be impossible to talk to the management interface of the DM9801 979 * PHY (its MDIO pin is not connected to anything). Consequently, 980 * the driver has to just 'know' about the additional mode and deal 981 * with it itself. *sigh* 982 */ 983 static void dc_miibus_mediainit(dev) 984 device_t dev; 985 { 986 struct dc_softc *sc; 987 struct mii_data *mii; 988 struct ifmedia *ifm; 989 int rev; 990 991 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 992 993 sc = device_get_softc(dev); 994 mii = device_get_softc(sc->dc_miibus); 995 ifm = &mii->mii_media; 996 997 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 998 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 999 1000 return; 1001 } 1002 1003 #define DC_POLY 0xEDB88320 1004 #define DC_BITS_512 9 1005 #define DC_BITS_128 7 1006 #define DC_BITS_64 6 1007 1008 static u_int32_t dc_crc_le(sc, addr) 1009 struct dc_softc *sc; 1010 caddr_t addr; 1011 { 1012 u_int32_t idx, bit, data, crc; 1013 1014 /* Compute CRC for the address value. */ 1015 crc = 0xFFFFFFFF; /* initial value */ 1016 1017 for (idx = 0; idx < 6; idx++) { 1018 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1019 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1020 } 1021 1022 /* 1023 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1024 * chips is only 128 bits wide. 1025 */ 1026 if (sc->dc_flags & DC_128BIT_HASH) 1027 return (crc & ((1 << DC_BITS_128) - 1)); 1028 1029 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1030 if (sc->dc_flags & DC_64BIT_HASH) 1031 return (crc & ((1 << DC_BITS_64) - 1)); 1032 1033 return (crc & ((1 << DC_BITS_512) - 1)); 1034 } 1035 1036 /* 1037 * Calculate CRC of a multicast group address, return the lower 6 bits. 1038 */ 1039 static u_int32_t dc_crc_be(addr) 1040 caddr_t addr; 1041 { 1042 u_int32_t crc, carry; 1043 int i, j; 1044 u_int8_t c; 1045 1046 /* Compute CRC for the address value. */ 1047 crc = 0xFFFFFFFF; /* initial value */ 1048 1049 for (i = 0; i < 6; i++) { 1050 c = *(addr + i); 1051 for (j = 0; j < 8; j++) { 1052 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1053 crc <<= 1; 1054 c >>= 1; 1055 if (carry) 1056 crc = (crc ^ 0x04c11db6) | carry; 1057 } 1058 } 1059 1060 /* return the filter bit position */ 1061 return((crc >> 26) & 0x0000003F); 1062 } 1063 1064 /* 1065 * 21143-style RX filter setup routine. Filter programming is done by 1066 * downloading a special setup frame into the TX engine. 21143, Macronix, 1067 * PNIC, PNIC II and Davicom chips are programmed this way. 1068 * 1069 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1070 * address (our node address) and a 512-bit hash filter for multicast 1071 * frames. We also sneak the broadcast address into the hash filter since 1072 * we need that too. 1073 */ 1074 void dc_setfilt_21143(sc) 1075 struct dc_softc *sc; 1076 { 1077 struct dc_desc *sframe; 1078 u_int32_t h, *sp; 1079 struct ifmultiaddr *ifma; 1080 struct ifnet *ifp; 1081 int i; 1082 1083 ifp = &sc->arpcom.ac_if; 1084 1085 i = sc->dc_cdata.dc_tx_prod; 1086 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1087 sc->dc_cdata.dc_tx_cnt++; 1088 sframe = &sc->dc_ldata->dc_tx_list[i]; 1089 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1090 bzero((char *)sp, DC_SFRAME_LEN); 1091 1092 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1093 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1094 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1095 1096 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1097 1098 /* If we want promiscuous mode, set the allframes bit. */ 1099 if (ifp->if_flags & IFF_PROMISC) 1100 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1101 else 1102 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1103 1104 if (ifp->if_flags & IFF_ALLMULTI) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1108 1109 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1110 ifma = ifma->ifma_link.le_next) { 1111 if (ifma->ifma_addr->sa_family != AF_LINK) 1112 continue; 1113 h = dc_crc_le(sc, 1114 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1115 sp[h >> 4] |= 1 << (h & 0xF); 1116 } 1117 1118 if (ifp->if_flags & IFF_BROADCAST) { 1119 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1120 sp[h >> 4] |= 1 << (h & 0xF); 1121 } 1122 1123 /* Set our MAC address */ 1124 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1125 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1126 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1127 1128 sframe->dc_status = DC_TXSTAT_OWN; 1129 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1130 1131 /* 1132 * The PNIC takes an exceedingly long time to process its 1133 * setup frame; wait 10ms after posting the setup frame 1134 * before proceeding, just so it has time to swallow its 1135 * medicine. 1136 */ 1137 DELAY(10000); 1138 1139 ifp->if_timer = 5; 1140 1141 return; 1142 } 1143 1144 void dc_setfilt_admtek(sc) 1145 struct dc_softc *sc; 1146 { 1147 struct ifnet *ifp; 1148 int h = 0; 1149 u_int32_t hashes[2] = { 0, 0 }; 1150 struct ifmultiaddr *ifma; 1151 1152 ifp = &sc->arpcom.ac_if; 1153 1154 /* Init our MAC address */ 1155 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1156 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1157 1158 /* If we want promiscuous mode, set the allframes bit. */ 1159 if (ifp->if_flags & IFF_PROMISC) 1160 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1161 else 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 1164 if (ifp->if_flags & IFF_ALLMULTI) 1165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1166 else 1167 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 1169 /* first, zot all the existing hash bits */ 1170 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1171 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1172 1173 /* 1174 * If we're already in promisc or allmulti mode, we 1175 * don't have to bother programming the multicast filter. 1176 */ 1177 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1178 return; 1179 1180 /* now program new ones */ 1181 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1182 ifma = ifma->ifma_link.le_next) { 1183 if (ifma->ifma_addr->sa_family != AF_LINK) 1184 continue; 1185 if (DC_IS_CENTAUR(sc)) 1186 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1187 else 1188 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1189 if (h < 32) 1190 hashes[0] |= (1 << h); 1191 else 1192 hashes[1] |= (1 << (h - 32)); 1193 } 1194 1195 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1196 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1197 1198 return; 1199 } 1200 1201 void dc_setfilt_asix(sc) 1202 struct dc_softc *sc; 1203 { 1204 struct ifnet *ifp; 1205 int h = 0; 1206 u_int32_t hashes[2] = { 0, 0 }; 1207 struct ifmultiaddr *ifma; 1208 1209 ifp = &sc->arpcom.ac_if; 1210 1211 /* Init our MAC address */ 1212 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1213 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1214 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1215 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1216 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1217 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1218 1219 /* If we want promiscuous mode, set the allframes bit. */ 1220 if (ifp->if_flags & IFF_PROMISC) 1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1222 else 1223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1224 1225 if (ifp->if_flags & IFF_ALLMULTI) 1226 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1227 else 1228 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1229 1230 /* 1231 * The ASIX chip has a special bit to enable reception 1232 * of broadcast frames. 1233 */ 1234 if (ifp->if_flags & IFF_BROADCAST) 1235 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1238 1239 /* first, zot all the existing hash bits */ 1240 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1241 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1242 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1243 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1244 1245 /* 1246 * If we're already in promisc or allmulti mode, we 1247 * don't have to bother programming the multicast filter. 1248 */ 1249 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1250 return; 1251 1252 /* now program new ones */ 1253 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1254 ifma = ifma->ifma_link.le_next) { 1255 if (ifma->ifma_addr->sa_family != AF_LINK) 1256 continue; 1257 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1258 if (h < 32) 1259 hashes[0] |= (1 << h); 1260 else 1261 hashes[1] |= (1 << (h - 32)); 1262 } 1263 1264 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1265 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1266 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1267 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1268 1269 return; 1270 } 1271 1272 static void dc_setfilt(sc) 1273 struct dc_softc *sc; 1274 { 1275 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1276 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1277 dc_setfilt_21143(sc); 1278 1279 if (DC_IS_ASIX(sc)) 1280 dc_setfilt_asix(sc); 1281 1282 if (DC_IS_ADMTEK(sc)) 1283 dc_setfilt_admtek(sc); 1284 1285 return; 1286 } 1287 1288 /* 1289 * In order to fiddle with the 1290 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1291 * first have to put the transmit and/or receive logic in the idle state. 1292 */ 1293 static void dc_setcfg(sc, media) 1294 struct dc_softc *sc; 1295 int media; 1296 { 1297 int i, restart = 0; 1298 u_int32_t isr; 1299 1300 if (IFM_SUBTYPE(media) == IFM_NONE) 1301 return; 1302 1303 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1304 restart = 1; 1305 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1306 1307 for (i = 0; i < DC_TIMEOUT; i++) { 1308 isr = CSR_READ_4(sc, DC_ISR); 1309 if (isr & DC_ISR_TX_IDLE || 1310 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1311 break; 1312 DELAY(10); 1313 } 1314 1315 if (i == DC_TIMEOUT) 1316 printf("dc%d: failed to force tx and " 1317 "rx to idle state\n", sc->dc_unit); 1318 } 1319 1320 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1321 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1322 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1323 if (sc->dc_pmode == DC_PMODE_MII) { 1324 int watchdogreg; 1325 1326 if (DC_IS_INTEL(sc)) { 1327 /* there's a write enable bit here that reads as 1 */ 1328 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1329 watchdogreg &= ~DC_WDOG_CTLWREN; 1330 watchdogreg |= DC_WDOG_JABBERDIS; 1331 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1332 } else { 1333 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1334 } 1335 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1336 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1337 if (sc->dc_type == DC_TYPE_98713) 1338 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1339 DC_NETCFG_SCRAMBLER)); 1340 if (!DC_IS_DAVICOM(sc)) 1341 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1342 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1343 if (DC_IS_INTEL(sc)) 1344 dc_apply_fixup(sc, IFM_AUTO); 1345 } else { 1346 if (DC_IS_PNIC(sc)) { 1347 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1348 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1349 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1350 } 1351 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1353 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1354 if (DC_IS_INTEL(sc)) 1355 dc_apply_fixup(sc, 1356 (media & IFM_GMASK) == IFM_FDX ? 1357 IFM_100_TX|IFM_FDX : IFM_100_TX); 1358 } 1359 } 1360 1361 if (IFM_SUBTYPE(media) == IFM_10_T) { 1362 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1363 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1364 if (sc->dc_pmode == DC_PMODE_MII) { 1365 int watchdogreg; 1366 1367 /* there's a write enable bit here that reads as 1 */ 1368 if (DC_IS_INTEL(sc)) { 1369 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1370 watchdogreg &= ~DC_WDOG_CTLWREN; 1371 watchdogreg |= DC_WDOG_JABBERDIS; 1372 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1373 } else { 1374 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1375 } 1376 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1377 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1378 if (sc->dc_type == DC_TYPE_98713) 1379 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1380 if (!DC_IS_DAVICOM(sc)) 1381 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1382 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1383 if (DC_IS_INTEL(sc)) 1384 dc_apply_fixup(sc, IFM_AUTO); 1385 } else { 1386 if (DC_IS_PNIC(sc)) { 1387 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1388 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1389 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1390 } 1391 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1393 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1394 if (DC_IS_INTEL(sc)) { 1395 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1396 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1397 if ((media & IFM_GMASK) == IFM_FDX) 1398 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1399 else 1400 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1401 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1402 DC_CLRBIT(sc, DC_10BTCTRL, 1403 DC_TCTL_AUTONEGENBL); 1404 dc_apply_fixup(sc, 1405 (media & IFM_GMASK) == IFM_FDX ? 1406 IFM_10_T|IFM_FDX : IFM_10_T); 1407 DELAY(20000); 1408 } 1409 } 1410 } 1411 1412 /* 1413 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1414 * PHY and we want HomePNA mode, set the portsel bit to turn 1415 * on the external MII port. 1416 */ 1417 if (DC_IS_DAVICOM(sc)) { 1418 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1420 sc->dc_link = 1; 1421 } else { 1422 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1423 } 1424 } 1425 1426 if ((media & IFM_GMASK) == IFM_FDX) { 1427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1428 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1429 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1430 } else { 1431 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1432 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1433 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1434 } 1435 1436 if (restart) 1437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1438 1439 return; 1440 } 1441 1442 static void dc_reset(sc) 1443 struct dc_softc *sc; 1444 { 1445 int i; 1446 1447 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1448 1449 for (i = 0; i < DC_TIMEOUT; i++) { 1450 DELAY(10); 1451 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1452 break; 1453 } 1454 1455 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1456 DELAY(10000); 1457 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1458 i = 0; 1459 } 1460 1461 if (i == DC_TIMEOUT) 1462 printf("dc%d: reset never completed!\n", sc->dc_unit); 1463 1464 /* Wait a little while for the chip to get its brains in order. */ 1465 DELAY(1000); 1466 1467 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1468 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1469 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1470 1471 /* 1472 * Bring the SIA out of reset. In some cases, it looks 1473 * like failing to unreset the SIA soon enough gets it 1474 * into a state where it will never come out of reset 1475 * until we reset the whole chip again. 1476 */ 1477 if (DC_IS_INTEL(sc)) { 1478 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1479 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1480 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1481 } 1482 1483 return; 1484 } 1485 1486 static struct dc_type *dc_devtype(dev) 1487 device_t dev; 1488 { 1489 struct dc_type *t; 1490 u_int32_t rev; 1491 1492 t = dc_devs; 1493 1494 while(t->dc_name != NULL) { 1495 if ((pci_get_vendor(dev) == t->dc_vid) && 1496 (pci_get_device(dev) == t->dc_did)) { 1497 /* Check the PCI revision */ 1498 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1499 if (t->dc_did == DC_DEVICEID_98713 && 1500 rev >= DC_REVISION_98713A) 1501 t++; 1502 if (t->dc_did == DC_DEVICEID_98713_CP && 1503 rev >= DC_REVISION_98713A) 1504 t++; 1505 if (t->dc_did == DC_DEVICEID_987x5 && 1506 rev >= DC_REVISION_98715AEC_C) 1507 t++; 1508 if (t->dc_did == DC_DEVICEID_987x5 && 1509 rev >= DC_REVISION_98725) 1510 t++; 1511 if (t->dc_did == DC_DEVICEID_AX88140A && 1512 rev >= DC_REVISION_88141) 1513 t++; 1514 if (t->dc_did == DC_DEVICEID_82C168 && 1515 rev >= DC_REVISION_82C169) 1516 t++; 1517 if (t->dc_did == DC_DEVICEID_DM9102 && 1518 rev >= DC_REVISION_DM9102A) 1519 t++; 1520 return(t); 1521 } 1522 t++; 1523 } 1524 1525 return(NULL); 1526 } 1527 1528 /* 1529 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1530 * IDs against our list and return a device name if we find a match. 1531 * We do a little bit of extra work to identify the exact type of 1532 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1533 * but different revision IDs. The same is true for 98715/98715A 1534 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1535 * cases, the exact chip revision affects driver behavior. 1536 */ 1537 static int dc_probe(dev) 1538 device_t dev; 1539 { 1540 struct dc_type *t; 1541 1542 t = dc_devtype(dev); 1543 1544 if (t != NULL) { 1545 device_set_desc(dev, t->dc_name); 1546 return(0); 1547 } 1548 1549 return(ENXIO); 1550 } 1551 1552 static void dc_acpi(dev) 1553 device_t dev; 1554 { 1555 u_int32_t r, cptr; 1556 int unit; 1557 1558 unit = device_get_unit(dev); 1559 1560 /* Find the location of the capabilities block */ 1561 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1562 1563 r = pci_read_config(dev, cptr, 4) & 0xFF; 1564 if (r == 0x01) { 1565 1566 r = pci_read_config(dev, cptr + 4, 4); 1567 if (r & DC_PSTATE_D3) { 1568 u_int32_t iobase, membase, irq; 1569 1570 /* Save important PCI config data. */ 1571 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1572 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1573 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1574 1575 /* Reset the power state. */ 1576 printf("dc%d: chip is in D%d power mode " 1577 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1578 r &= 0xFFFFFFFC; 1579 pci_write_config(dev, cptr + 4, r, 4); 1580 1581 /* Restore PCI config data. */ 1582 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1583 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1584 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1585 } 1586 } 1587 return; 1588 } 1589 1590 static void dc_apply_fixup(sc, media) 1591 struct dc_softc *sc; 1592 int media; 1593 { 1594 struct dc_mediainfo *m; 1595 u_int8_t *p; 1596 int i; 1597 u_int32_t reg; 1598 1599 m = sc->dc_mi; 1600 1601 while (m != NULL) { 1602 if (m->dc_media == media) 1603 break; 1604 m = m->dc_next; 1605 } 1606 1607 if (m == NULL) 1608 return; 1609 1610 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1611 reg = (p[0] | (p[1] << 8)) << 16; 1612 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1613 } 1614 1615 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1616 reg = (p[0] | (p[1] << 8)) << 16; 1617 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1618 } 1619 1620 return; 1621 } 1622 1623 static void dc_decode_leaf_sia(sc, l) 1624 struct dc_softc *sc; 1625 struct dc_eblock_sia *l; 1626 { 1627 struct dc_mediainfo *m; 1628 1629 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1630 bzero(m, sizeof(struct dc_mediainfo)); 1631 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1632 m->dc_media = IFM_10_T; 1633 1634 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1635 m->dc_media = IFM_10_T|IFM_FDX; 1636 1637 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1638 m->dc_media = IFM_10_2; 1639 1640 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1641 m->dc_media = IFM_10_5; 1642 1643 m->dc_gp_len = 2; 1644 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1645 1646 m->dc_next = sc->dc_mi; 1647 sc->dc_mi = m; 1648 1649 sc->dc_pmode = DC_PMODE_SIA; 1650 1651 return; 1652 } 1653 1654 static void dc_decode_leaf_sym(sc, l) 1655 struct dc_softc *sc; 1656 struct dc_eblock_sym *l; 1657 { 1658 struct dc_mediainfo *m; 1659 1660 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1661 bzero(m, sizeof(struct dc_mediainfo)); 1662 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1663 m->dc_media = IFM_100_TX; 1664 1665 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1666 m->dc_media = IFM_100_TX|IFM_FDX; 1667 1668 m->dc_gp_len = 2; 1669 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1670 1671 m->dc_next = sc->dc_mi; 1672 sc->dc_mi = m; 1673 1674 sc->dc_pmode = DC_PMODE_SYM; 1675 1676 return; 1677 } 1678 1679 static void dc_decode_leaf_mii(sc, l) 1680 struct dc_softc *sc; 1681 struct dc_eblock_mii *l; 1682 { 1683 u_int8_t *p; 1684 struct dc_mediainfo *m; 1685 1686 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1687 bzero(m, sizeof(struct dc_mediainfo)); 1688 /* We abuse IFM_AUTO to represent MII. */ 1689 m->dc_media = IFM_AUTO; 1690 m->dc_gp_len = l->dc_gpr_len; 1691 1692 p = (u_int8_t *)l; 1693 p += sizeof(struct dc_eblock_mii); 1694 m->dc_gp_ptr = p; 1695 p += 2 * l->dc_gpr_len; 1696 m->dc_reset_len = *p; 1697 p++; 1698 m->dc_reset_ptr = p; 1699 1700 m->dc_next = sc->dc_mi; 1701 sc->dc_mi = m; 1702 1703 return; 1704 } 1705 1706 static void dc_read_srom(sc, bits) 1707 struct dc_softc *sc; 1708 int bits; 1709 { 1710 int size; 1711 1712 size = 2 << bits; 1713 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1714 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1715 } 1716 1717 static void dc_parse_21143_srom(sc) 1718 struct dc_softc *sc; 1719 { 1720 struct dc_leaf_hdr *lhdr; 1721 struct dc_eblock_hdr *hdr; 1722 int i, loff; 1723 char *ptr; 1724 int have_mii; 1725 1726 have_mii = 0; 1727 loff = sc->dc_srom[27]; 1728 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1729 1730 ptr = (char *)lhdr; 1731 ptr += sizeof(struct dc_leaf_hdr) - 1; 1732 /* 1733 * Look if we got a MII media block. 1734 */ 1735 for (i = 0; i < lhdr->dc_mcnt; i++) { 1736 hdr = (struct dc_eblock_hdr *)ptr; 1737 if (hdr->dc_type == DC_EBLOCK_MII) 1738 have_mii++; 1739 1740 ptr += (hdr->dc_len & 0x7F); 1741 ptr++; 1742 } 1743 1744 /* 1745 * Do the same thing again. Only use SIA and SYM media 1746 * blocks if no MII media block is available. 1747 */ 1748 ptr = (char *)lhdr; 1749 ptr += sizeof(struct dc_leaf_hdr) - 1; 1750 for (i = 0; i < lhdr->dc_mcnt; i++) { 1751 hdr = (struct dc_eblock_hdr *)ptr; 1752 switch(hdr->dc_type) { 1753 case DC_EBLOCK_MII: 1754 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1755 break; 1756 case DC_EBLOCK_SIA: 1757 if (! have_mii) 1758 dc_decode_leaf_sia(sc, 1759 (struct dc_eblock_sia *)hdr); 1760 break; 1761 case DC_EBLOCK_SYM: 1762 if (! have_mii) 1763 dc_decode_leaf_sym(sc, 1764 (struct dc_eblock_sym *)hdr); 1765 break; 1766 default: 1767 /* Don't care. Yet. */ 1768 break; 1769 } 1770 ptr += (hdr->dc_len & 0x7F); 1771 ptr++; 1772 } 1773 1774 return; 1775 } 1776 1777 /* 1778 * Attach the interface. Allocate softc structures, do ifmedia 1779 * setup and ethernet/BPF attach. 1780 */ 1781 static int dc_attach(dev) 1782 device_t dev; 1783 { 1784 int s, tmp = 0; 1785 u_char eaddr[ETHER_ADDR_LEN]; 1786 u_int32_t command; 1787 struct dc_softc *sc; 1788 struct ifnet *ifp; 1789 u_int32_t revision; 1790 int unit, error = 0, rid, mac_offset; 1791 1792 s = splimp(); 1793 1794 sc = device_get_softc(dev); 1795 unit = device_get_unit(dev); 1796 bzero(sc, sizeof(struct dc_softc)); 1797 1798 /* 1799 * Handle power management nonsense. 1800 */ 1801 dc_acpi(dev); 1802 1803 /* 1804 * Map control/status registers. 1805 */ 1806 command = pci_read_config(dev, PCIR_COMMAND, 4); 1807 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1808 pci_write_config(dev, PCIR_COMMAND, command, 4); 1809 command = pci_read_config(dev, PCIR_COMMAND, 4); 1810 1811 #ifdef DC_USEIOSPACE 1812 if (!(command & PCIM_CMD_PORTEN)) { 1813 printf("dc%d: failed to enable I/O ports!\n", unit); 1814 error = ENXIO; 1815 goto fail; 1816 } 1817 #else 1818 if (!(command & PCIM_CMD_MEMEN)) { 1819 printf("dc%d: failed to enable memory mapping!\n", unit); 1820 error = ENXIO; 1821 goto fail; 1822 } 1823 #endif 1824 1825 rid = DC_RID; 1826 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1827 0, ~0, 1, RF_ACTIVE); 1828 1829 if (sc->dc_res == NULL) { 1830 printf("dc%d: couldn't map ports/memory\n", unit); 1831 error = ENXIO; 1832 goto fail; 1833 } 1834 1835 sc->dc_btag = rman_get_bustag(sc->dc_res); 1836 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1837 1838 /* Allocate interrupt */ 1839 rid = 0; 1840 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1841 RF_SHAREABLE | RF_ACTIVE); 1842 1843 if (sc->dc_irq == NULL) { 1844 printf("dc%d: couldn't map interrupt\n", unit); 1845 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1846 error = ENXIO; 1847 goto fail; 1848 } 1849 1850 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1851 dc_intr, sc, &sc->dc_intrhand); 1852 1853 if (error) { 1854 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1855 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1856 printf("dc%d: couldn't set up irq\n", unit); 1857 goto fail; 1858 } 1859 1860 /* Need this info to decide on a chip type. */ 1861 sc->dc_info = dc_devtype(dev); 1862 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1863 1864 /* Get the eeprom width, but PNIC has diff eeprom */ 1865 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1866 dc_eeprom_width(sc); 1867 1868 switch(sc->dc_info->dc_did) { 1869 case DC_DEVICEID_21143: 1870 sc->dc_type = DC_TYPE_21143; 1871 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1872 sc->dc_flags |= DC_REDUCED_MII_POLL; 1873 /* Save EEPROM contents so we can parse them later. */ 1874 dc_read_srom(sc, sc->dc_romwidth); 1875 break; 1876 case DC_DEVICEID_DM9009: 1877 case DC_DEVICEID_DM9100: 1878 case DC_DEVICEID_DM9102: 1879 sc->dc_type = DC_TYPE_DM9102; 1880 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1881 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1882 sc->dc_pmode = DC_PMODE_MII; 1883 /* Increase the latency timer value. */ 1884 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1885 command &= 0xFFFF00FF; 1886 command |= 0x00008000; 1887 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1888 break; 1889 case DC_DEVICEID_AL981: 1890 sc->dc_type = DC_TYPE_AL981; 1891 sc->dc_flags |= DC_TX_USE_TX_INTR; 1892 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1893 sc->dc_pmode = DC_PMODE_MII; 1894 dc_read_srom(sc, sc->dc_romwidth); 1895 break; 1896 case DC_DEVICEID_AN985: 1897 case DC_DEVICEID_EN2242: 1898 case DC_DEVICEID_3CSOHOB: 1899 sc->dc_type = DC_TYPE_AN985; 1900 sc->dc_flags |= DC_64BIT_HASH; 1901 sc->dc_flags |= DC_TX_USE_TX_INTR; 1902 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1903 sc->dc_pmode = DC_PMODE_MII; 1904 dc_read_srom(sc, sc->dc_romwidth); 1905 break; 1906 case DC_DEVICEID_98713: 1907 case DC_DEVICEID_98713_CP: 1908 if (revision < DC_REVISION_98713A) { 1909 sc->dc_type = DC_TYPE_98713; 1910 } 1911 if (revision >= DC_REVISION_98713A) { 1912 sc->dc_type = DC_TYPE_98713A; 1913 sc->dc_flags |= DC_21143_NWAY; 1914 } 1915 sc->dc_flags |= DC_REDUCED_MII_POLL; 1916 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1917 break; 1918 case DC_DEVICEID_987x5: 1919 case DC_DEVICEID_EN1217: 1920 /* 1921 * Macronix MX98715AEC-C/D/E parts have only a 1922 * 128-bit hash table. We need to deal with these 1923 * in the same manner as the PNIC II so that we 1924 * get the right number of bits out of the 1925 * CRC routine. 1926 */ 1927 if (revision >= DC_REVISION_98715AEC_C && 1928 revision < DC_REVISION_98725) 1929 sc->dc_flags |= DC_128BIT_HASH; 1930 sc->dc_type = DC_TYPE_987x5; 1931 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1932 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1933 break; 1934 case DC_DEVICEID_98727: 1935 sc->dc_type = DC_TYPE_987x5; 1936 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1937 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1938 break; 1939 case DC_DEVICEID_82C115: 1940 sc->dc_type = DC_TYPE_PNICII; 1941 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1942 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1943 break; 1944 case DC_DEVICEID_82C168: 1945 sc->dc_type = DC_TYPE_PNIC; 1946 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1947 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1948 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1949 if (revision < DC_REVISION_82C169) 1950 sc->dc_pmode = DC_PMODE_SYM; 1951 break; 1952 case DC_DEVICEID_AX88140A: 1953 sc->dc_type = DC_TYPE_ASIX; 1954 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1955 sc->dc_flags |= DC_REDUCED_MII_POLL; 1956 sc->dc_pmode = DC_PMODE_MII; 1957 break; 1958 case DC_DEVICEID_RS7112: 1959 sc->dc_type = DC_TYPE_CONEXANT; 1960 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1961 sc->dc_flags |= DC_REDUCED_MII_POLL; 1962 sc->dc_pmode = DC_PMODE_MII; 1963 dc_read_srom(sc, sc->dc_romwidth); 1964 break; 1965 default: 1966 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1967 sc->dc_info->dc_did); 1968 break; 1969 } 1970 1971 /* Save the cache line size. */ 1972 if (DC_IS_DAVICOM(sc)) 1973 sc->dc_cachesize = 0; 1974 else 1975 sc->dc_cachesize = pci_read_config(dev, 1976 DC_PCI_CFLT, 4) & 0xFF; 1977 1978 /* Reset the adapter. */ 1979 dc_reset(sc); 1980 1981 /* Take 21143 out of snooze mode */ 1982 if (DC_IS_INTEL(sc)) { 1983 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1984 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1985 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1986 } 1987 1988 /* 1989 * Try to learn something about the supported media. 1990 * We know that ASIX and ADMtek and Davicom devices 1991 * will *always* be using MII media, so that's a no-brainer. 1992 * The tricky ones are the Macronix/PNIC II and the 1993 * Intel 21143. 1994 */ 1995 if (DC_IS_INTEL(sc)) 1996 dc_parse_21143_srom(sc); 1997 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1998 if (sc->dc_type == DC_TYPE_98713) 1999 sc->dc_pmode = DC_PMODE_MII; 2000 else 2001 sc->dc_pmode = DC_PMODE_SYM; 2002 } else if (!sc->dc_pmode) 2003 sc->dc_pmode = DC_PMODE_MII; 2004 2005 /* 2006 * Get station address from the EEPROM. 2007 */ 2008 switch(sc->dc_type) { 2009 case DC_TYPE_98713: 2010 case DC_TYPE_98713A: 2011 case DC_TYPE_987x5: 2012 case DC_TYPE_PNICII: 2013 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2014 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2015 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2016 break; 2017 case DC_TYPE_PNIC: 2018 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2019 break; 2020 case DC_TYPE_DM9102: 2021 case DC_TYPE_21143: 2022 case DC_TYPE_ASIX: 2023 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2024 break; 2025 case DC_TYPE_AL981: 2026 case DC_TYPE_AN985: 2027 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2028 ETHER_ADDR_LEN); 2029 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2030 break; 2031 case DC_TYPE_CONEXANT: 2032 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2033 break; 2034 default: 2035 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2036 break; 2037 } 2038 2039 /* 2040 * A 21143 or clone chip was detected. Inform the world. 2041 */ 2042 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2043 2044 sc->dc_unit = unit; 2045 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2046 2047 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2048 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2049 2050 if (sc->dc_ldata == NULL) { 2051 printf("dc%d: no memory for list buffers!\n", unit); 2052 if (sc->dc_pnic_rx_buf != NULL) 2053 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2054 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2055 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2056 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2057 error = ENXIO; 2058 goto fail; 2059 } 2060 2061 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2062 2063 ifp = &sc->arpcom.ac_if; 2064 ifp->if_softc = sc; 2065 if_initname(ifp, "dc", unit); 2066 ifp->if_mtu = ETHERMTU; 2067 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2068 ifp->if_ioctl = dc_ioctl; 2069 ifp->if_output = ether_output; 2070 ifp->if_start = dc_start; 2071 ifp->if_watchdog = dc_watchdog; 2072 ifp->if_init = dc_init; 2073 ifp->if_baudrate = 10000000; 2074 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2075 2076 /* 2077 * Do MII setup. If this is a 21143, check for a PHY on the 2078 * MII bus after applying any necessary fixups to twiddle the 2079 * GPIO bits. If we don't end up finding a PHY, restore the 2080 * old selection (SIA only or SIA/SYM) and attach the dcphy 2081 * driver instead. 2082 */ 2083 if (DC_IS_INTEL(sc)) { 2084 dc_apply_fixup(sc, IFM_AUTO); 2085 tmp = sc->dc_pmode; 2086 sc->dc_pmode = DC_PMODE_MII; 2087 } 2088 2089 error = mii_phy_probe(dev, &sc->dc_miibus, 2090 dc_ifmedia_upd, dc_ifmedia_sts); 2091 2092 if (error && DC_IS_INTEL(sc)) { 2093 sc->dc_pmode = tmp; 2094 if (sc->dc_pmode != DC_PMODE_SIA) 2095 sc->dc_pmode = DC_PMODE_SYM; 2096 sc->dc_flags |= DC_21143_NWAY; 2097 mii_phy_probe(dev, &sc->dc_miibus, 2098 dc_ifmedia_upd, dc_ifmedia_sts); 2099 /* 2100 * For non-MII cards, we need to have the 21143 2101 * drive the LEDs. Except there are some systems 2102 * like the NEC VersaPro NoteBook PC which have no 2103 * LEDs, and twiddling these bits has adverse effects 2104 * on them. (I.e. you suddenly can't get a link.) 2105 */ 2106 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2107 sc->dc_flags |= DC_TULIP_LEDS; 2108 error = 0; 2109 } 2110 2111 if (error) { 2112 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2113 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), 2114 M_DEVBUF); 2115 if (sc->dc_pnic_rx_buf != NULL) 2116 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2117 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2118 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2119 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2120 error = ENXIO; 2121 goto fail; 2122 } 2123 2124 /* 2125 * Call MI attach routine. 2126 */ 2127 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2128 callout_handle_init(&sc->dc_stat_ch); 2129 2130 if (DC_IS_ADMTEK(sc)) { 2131 /* 2132 * Set automatic TX underrun recovery for the ADMtek chips 2133 */ 2134 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2135 } 2136 2137 /* 2138 * Tell the upper layer(s) we support long frames. 2139 */ 2140 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2141 2142 #ifdef SRM_MEDIA 2143 sc->dc_srm_media = 0; 2144 2145 /* Remember the SRM console media setting */ 2146 if (DC_IS_INTEL(sc)) { 2147 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2148 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2149 switch ((command >> 8) & 0xff) { 2150 case 3: 2151 sc->dc_srm_media = IFM_10_T; 2152 break; 2153 case 4: 2154 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2155 break; 2156 case 5: 2157 sc->dc_srm_media = IFM_100_TX; 2158 break; 2159 case 6: 2160 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2161 break; 2162 } 2163 if (sc->dc_srm_media) 2164 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2165 } 2166 #endif 2167 2168 2169 fail: 2170 splx(s); 2171 2172 return(error); 2173 } 2174 2175 static int dc_detach(dev) 2176 device_t dev; 2177 { 2178 struct dc_softc *sc; 2179 struct ifnet *ifp; 2180 int s; 2181 struct dc_mediainfo *m; 2182 2183 s = splimp(); 2184 2185 sc = device_get_softc(dev); 2186 ifp = &sc->arpcom.ac_if; 2187 2188 dc_stop(sc); 2189 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2190 2191 bus_generic_detach(dev); 2192 device_delete_child(dev, sc->dc_miibus); 2193 2194 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2195 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2196 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2197 2198 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2199 if (sc->dc_pnic_rx_buf != NULL) 2200 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2201 2202 while(sc->dc_mi != NULL) { 2203 m = sc->dc_mi->dc_next; 2204 free(sc->dc_mi, M_DEVBUF); 2205 sc->dc_mi = m; 2206 } 2207 free(sc->dc_srom, M_DEVBUF); 2208 2209 splx(s); 2210 2211 return(0); 2212 } 2213 2214 /* 2215 * Initialize the transmit descriptors. 2216 */ 2217 static int dc_list_tx_init(sc) 2218 struct dc_softc *sc; 2219 { 2220 struct dc_chain_data *cd; 2221 struct dc_list_data *ld; 2222 int i; 2223 2224 cd = &sc->dc_cdata; 2225 ld = sc->dc_ldata; 2226 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2227 if (i == (DC_TX_LIST_CNT - 1)) { 2228 ld->dc_tx_list[i].dc_next = 2229 vtophys(&ld->dc_tx_list[0]); 2230 } else { 2231 ld->dc_tx_list[i].dc_next = 2232 vtophys(&ld->dc_tx_list[i + 1]); 2233 } 2234 cd->dc_tx_chain[i] = NULL; 2235 ld->dc_tx_list[i].dc_data = 0; 2236 ld->dc_tx_list[i].dc_ctl = 0; 2237 } 2238 2239 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2240 2241 return(0); 2242 } 2243 2244 2245 /* 2246 * Initialize the RX descriptors and allocate mbufs for them. Note that 2247 * we arrange the descriptors in a closed ring, so that the last descriptor 2248 * points back to the first. 2249 */ 2250 static int dc_list_rx_init(sc) 2251 struct dc_softc *sc; 2252 { 2253 struct dc_chain_data *cd; 2254 struct dc_list_data *ld; 2255 int i; 2256 2257 cd = &sc->dc_cdata; 2258 ld = sc->dc_ldata; 2259 2260 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2261 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2262 return(ENOBUFS); 2263 if (i == (DC_RX_LIST_CNT - 1)) { 2264 ld->dc_rx_list[i].dc_next = 2265 vtophys(&ld->dc_rx_list[0]); 2266 } else { 2267 ld->dc_rx_list[i].dc_next = 2268 vtophys(&ld->dc_rx_list[i + 1]); 2269 } 2270 } 2271 2272 cd->dc_rx_prod = 0; 2273 2274 return(0); 2275 } 2276 2277 /* 2278 * Initialize an RX descriptor and attach an MBUF cluster. 2279 */ 2280 static int dc_newbuf(sc, i, m) 2281 struct dc_softc *sc; 2282 int i; 2283 struct mbuf *m; 2284 { 2285 struct mbuf *m_new = NULL; 2286 struct dc_desc *c; 2287 2288 c = &sc->dc_ldata->dc_rx_list[i]; 2289 2290 if (m == NULL) { 2291 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2292 if (m_new == NULL) 2293 return(ENOBUFS); 2294 2295 MCLGET(m_new, M_DONTWAIT); 2296 if (!(m_new->m_flags & M_EXT)) { 2297 m_freem(m_new); 2298 return(ENOBUFS); 2299 } 2300 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2301 } else { 2302 m_new = m; 2303 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2304 m_new->m_data = m_new->m_ext.ext_buf; 2305 } 2306 2307 m_adj(m_new, sizeof(u_int64_t)); 2308 2309 /* 2310 * If this is a PNIC chip, zero the buffer. This is part 2311 * of the workaround for the receive bug in the 82c168 and 2312 * 82c169 chips. 2313 */ 2314 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2315 bzero((char *)mtod(m_new, char *), m_new->m_len); 2316 2317 sc->dc_cdata.dc_rx_chain[i] = m_new; 2318 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2319 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2320 c->dc_status = DC_RXSTAT_OWN; 2321 2322 return(0); 2323 } 2324 2325 /* 2326 * Grrrrr. 2327 * The PNIC chip has a terrible bug in it that manifests itself during 2328 * periods of heavy activity. The exact mode of failure if difficult to 2329 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2330 * will happen on slow machines. The bug is that sometimes instead of 2331 * uploading one complete frame during reception, it uploads what looks 2332 * like the entire contents of its FIFO memory. The frame we want is at 2333 * the end of the whole mess, but we never know exactly how much data has 2334 * been uploaded, so salvaging the frame is hard. 2335 * 2336 * There is only one way to do it reliably, and it's disgusting. 2337 * Here's what we know: 2338 * 2339 * - We know there will always be somewhere between one and three extra 2340 * descriptors uploaded. 2341 * 2342 * - We know the desired received frame will always be at the end of the 2343 * total data upload. 2344 * 2345 * - We know the size of the desired received frame because it will be 2346 * provided in the length field of the status word in the last descriptor. 2347 * 2348 * Here's what we do: 2349 * 2350 * - When we allocate buffers for the receive ring, we bzero() them. 2351 * This means that we know that the buffer contents should be all 2352 * zeros, except for data uploaded by the chip. 2353 * 2354 * - We also force the PNIC chip to upload frames that include the 2355 * ethernet CRC at the end. 2356 * 2357 * - We gather all of the bogus frame data into a single buffer. 2358 * 2359 * - We then position a pointer at the end of this buffer and scan 2360 * backwards until we encounter the first non-zero byte of data. 2361 * This is the end of the received frame. We know we will encounter 2362 * some data at the end of the frame because the CRC will always be 2363 * there, so even if the sender transmits a packet of all zeros, 2364 * we won't be fooled. 2365 * 2366 * - We know the size of the actual received frame, so we subtract 2367 * that value from the current pointer location. This brings us 2368 * to the start of the actual received packet. 2369 * 2370 * - We copy this into an mbuf and pass it on, along with the actual 2371 * frame length. 2372 * 2373 * The performance hit is tremendous, but it beats dropping frames all 2374 * the time. 2375 */ 2376 2377 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2378 static void dc_pnic_rx_bug_war(sc, idx) 2379 struct dc_softc *sc; 2380 int idx; 2381 { 2382 struct dc_desc *cur_rx; 2383 struct dc_desc *c = NULL; 2384 struct mbuf *m = NULL; 2385 unsigned char *ptr; 2386 int i, total_len; 2387 u_int32_t rxstat = 0; 2388 2389 i = sc->dc_pnic_rx_bug_save; 2390 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2391 ptr = sc->dc_pnic_rx_buf; 2392 bzero(ptr, DC_RXLEN * 5); 2393 2394 /* Copy all the bytes from the bogus buffers. */ 2395 while (1) { 2396 c = &sc->dc_ldata->dc_rx_list[i]; 2397 rxstat = c->dc_status; 2398 m = sc->dc_cdata.dc_rx_chain[i]; 2399 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2400 ptr += DC_RXLEN; 2401 /* If this is the last buffer, break out. */ 2402 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2403 break; 2404 dc_newbuf(sc, i, m); 2405 DC_INC(i, DC_RX_LIST_CNT); 2406 } 2407 2408 /* Find the length of the actual receive frame. */ 2409 total_len = DC_RXBYTES(rxstat); 2410 2411 /* Scan backwards until we hit a non-zero byte. */ 2412 while(*ptr == 0x00) 2413 ptr--; 2414 2415 /* Round off. */ 2416 if ((uintptr_t)(ptr) & 0x3) 2417 ptr -= 1; 2418 2419 /* Now find the start of the frame. */ 2420 ptr -= total_len; 2421 if (ptr < sc->dc_pnic_rx_buf) 2422 ptr = sc->dc_pnic_rx_buf; 2423 2424 /* 2425 * Now copy the salvaged frame to the last mbuf and fake up 2426 * the status word to make it look like a successful 2427 * frame reception. 2428 */ 2429 dc_newbuf(sc, i, m); 2430 bcopy(ptr, mtod(m, char *), total_len); 2431 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2432 2433 return; 2434 } 2435 2436 /* 2437 * This routine searches the RX ring for dirty descriptors in the 2438 * event that the rxeof routine falls out of sync with the chip's 2439 * current descriptor pointer. This may happen sometimes as a result 2440 * of a "no RX buffer available" condition that happens when the chip 2441 * consumes all of the RX buffers before the driver has a chance to 2442 * process the RX ring. This routine may need to be called more than 2443 * once to bring the driver back in sync with the chip, however we 2444 * should still be getting RX DONE interrupts to drive the search 2445 * for new packets in the RX ring, so we should catch up eventually. 2446 */ 2447 static int dc_rx_resync(sc) 2448 struct dc_softc *sc; 2449 { 2450 int i, pos; 2451 struct dc_desc *cur_rx; 2452 2453 pos = sc->dc_cdata.dc_rx_prod; 2454 2455 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2456 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2457 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2458 break; 2459 DC_INC(pos, DC_RX_LIST_CNT); 2460 } 2461 2462 /* If the ring really is empty, then just return. */ 2463 if (i == DC_RX_LIST_CNT) 2464 return(0); 2465 2466 /* We've fallen behing the chip: catch it. */ 2467 sc->dc_cdata.dc_rx_prod = pos; 2468 2469 return(EAGAIN); 2470 } 2471 2472 /* 2473 * A frame has been uploaded: pass the resulting mbuf chain up to 2474 * the higher level protocols. 2475 */ 2476 static void dc_rxeof(sc) 2477 struct dc_softc *sc; 2478 { 2479 struct ether_header *eh; 2480 struct mbuf *m; 2481 struct ifnet *ifp; 2482 struct dc_desc *cur_rx; 2483 int i, total_len = 0; 2484 u_int32_t rxstat; 2485 2486 ifp = &sc->arpcom.ac_if; 2487 i = sc->dc_cdata.dc_rx_prod; 2488 2489 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2490 2491 #ifdef DEVICE_POLLING 2492 if (ifp->if_ipending & IFF_POLLING) { 2493 if (sc->rxcycles <= 0) 2494 break; 2495 sc->rxcycles--; 2496 } 2497 #endif /* DEVICE_POLLING */ 2498 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2499 rxstat = cur_rx->dc_status; 2500 m = sc->dc_cdata.dc_rx_chain[i]; 2501 total_len = DC_RXBYTES(rxstat); 2502 2503 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2504 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2505 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2506 sc->dc_pnic_rx_bug_save = i; 2507 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2508 DC_INC(i, DC_RX_LIST_CNT); 2509 continue; 2510 } 2511 dc_pnic_rx_bug_war(sc, i); 2512 rxstat = cur_rx->dc_status; 2513 total_len = DC_RXBYTES(rxstat); 2514 } 2515 } 2516 2517 sc->dc_cdata.dc_rx_chain[i] = NULL; 2518 2519 /* 2520 * If an error occurs, update stats, clear the 2521 * status word and leave the mbuf cluster in place: 2522 * it should simply get re-used next time this descriptor 2523 * comes up in the ring. However, don't report long 2524 * frames as errors since they could be vlans 2525 */ 2526 if ((rxstat & DC_RXSTAT_RXERR)){ 2527 if (!(rxstat & DC_RXSTAT_GIANT) || 2528 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2529 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2530 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2531 ifp->if_ierrors++; 2532 if (rxstat & DC_RXSTAT_COLLSEEN) 2533 ifp->if_collisions++; 2534 dc_newbuf(sc, i, m); 2535 if (rxstat & DC_RXSTAT_CRCERR) { 2536 DC_INC(i, DC_RX_LIST_CNT); 2537 continue; 2538 } else { 2539 dc_init(sc); 2540 return; 2541 } 2542 } 2543 } 2544 2545 /* No errors; receive the packet. */ 2546 total_len -= ETHER_CRC_LEN; 2547 2548 #ifdef __i386__ 2549 /* 2550 * On the x86 we do not have alignment problems, so try to 2551 * allocate a new buffer for the receive ring, and pass up 2552 * the one where the packet is already, saving the expensive 2553 * copy done in m_devget(). 2554 * If we are on an architecture with alignment problems, or 2555 * if the allocation fails, then use m_devget and leave the 2556 * existing buffer in the receive ring. 2557 */ 2558 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2559 m->m_pkthdr.rcvif = ifp; 2560 m->m_pkthdr.len = m->m_len = total_len; 2561 DC_INC(i, DC_RX_LIST_CNT); 2562 } else 2563 #endif 2564 { 2565 struct mbuf *m0; 2566 2567 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2568 total_len + ETHER_ALIGN, 0, ifp, NULL); 2569 dc_newbuf(sc, i, m); 2570 DC_INC(i, DC_RX_LIST_CNT); 2571 if (m0 == NULL) { 2572 ifp->if_ierrors++; 2573 continue; 2574 } 2575 m_adj(m0, ETHER_ALIGN); 2576 m = m0; 2577 } 2578 2579 ifp->if_ipackets++; 2580 eh = mtod(m, struct ether_header *); 2581 2582 /* Remove header from mbuf and pass it on. */ 2583 m_adj(m, sizeof(struct ether_header)); 2584 ether_input(ifp, eh, m); 2585 } 2586 2587 sc->dc_cdata.dc_rx_prod = i; 2588 } 2589 2590 /* 2591 * A frame was downloaded to the chip. It's safe for us to clean up 2592 * the list buffers. 2593 */ 2594 2595 static void 2596 dc_txeof(sc) 2597 struct dc_softc *sc; 2598 { 2599 struct dc_desc *cur_tx = NULL; 2600 struct ifnet *ifp; 2601 int idx; 2602 2603 ifp = &sc->arpcom.ac_if; 2604 2605 /* 2606 * Go through our tx list and free mbufs for those 2607 * frames that have been transmitted. 2608 */ 2609 idx = sc->dc_cdata.dc_tx_cons; 2610 while(idx != sc->dc_cdata.dc_tx_prod) { 2611 u_int32_t txstat; 2612 2613 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2614 txstat = cur_tx->dc_status; 2615 2616 if (txstat & DC_TXSTAT_OWN) 2617 break; 2618 2619 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2620 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2621 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2622 /* 2623 * Yes, the PNIC is so brain damaged 2624 * that it will sometimes generate a TX 2625 * underrun error while DMAing the RX 2626 * filter setup frame. If we detect this, 2627 * we have to send the setup frame again, 2628 * or else the filter won't be programmed 2629 * correctly. 2630 */ 2631 if (DC_IS_PNIC(sc)) { 2632 if (txstat & DC_TXSTAT_ERRSUM) 2633 dc_setfilt(sc); 2634 } 2635 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2636 } 2637 sc->dc_cdata.dc_tx_cnt--; 2638 DC_INC(idx, DC_TX_LIST_CNT); 2639 continue; 2640 } 2641 2642 if (DC_IS_CONEXANT(sc)) { 2643 /* 2644 * For some reason Conexant chips like 2645 * setting the CARRLOST flag even when 2646 * the carrier is there. In CURRENT we 2647 * have the same problem for Xircom 2648 * cards ! 2649 */ 2650 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2651 sc->dc_pmode == DC_PMODE_MII && 2652 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2653 DC_TXSTAT_NOCARRIER))) 2654 txstat &= ~DC_TXSTAT_ERRSUM; 2655 } else { 2656 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2657 sc->dc_pmode == DC_PMODE_MII && 2658 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2659 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2660 txstat &= ~DC_TXSTAT_ERRSUM; 2661 } 2662 2663 if (txstat & DC_TXSTAT_ERRSUM) { 2664 ifp->if_oerrors++; 2665 if (txstat & DC_TXSTAT_EXCESSCOLL) 2666 ifp->if_collisions++; 2667 if (txstat & DC_TXSTAT_LATECOLL) 2668 ifp->if_collisions++; 2669 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2670 dc_init(sc); 2671 return; 2672 } 2673 } 2674 2675 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2676 2677 ifp->if_opackets++; 2678 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2679 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2680 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2681 } 2682 2683 sc->dc_cdata.dc_tx_cnt--; 2684 DC_INC(idx, DC_TX_LIST_CNT); 2685 } 2686 2687 if (idx != sc->dc_cdata.dc_tx_cons) { 2688 /* some buffers have been freed */ 2689 sc->dc_cdata.dc_tx_cons = idx; 2690 ifp->if_flags &= ~IFF_OACTIVE; 2691 } 2692 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2693 2694 return; 2695 } 2696 2697 static void dc_tick(xsc) 2698 void *xsc; 2699 { 2700 struct dc_softc *sc; 2701 struct mii_data *mii; 2702 struct ifnet *ifp; 2703 int s; 2704 u_int32_t r; 2705 2706 s = splimp(); 2707 2708 sc = xsc; 2709 ifp = &sc->arpcom.ac_if; 2710 mii = device_get_softc(sc->dc_miibus); 2711 2712 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2713 if (sc->dc_flags & DC_21143_NWAY) { 2714 r = CSR_READ_4(sc, DC_10BTSTAT); 2715 if (IFM_SUBTYPE(mii->mii_media_active) == 2716 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2717 sc->dc_link = 0; 2718 mii_mediachg(mii); 2719 } 2720 if (IFM_SUBTYPE(mii->mii_media_active) == 2721 IFM_10_T && (r & DC_TSTAT_LS10)) { 2722 sc->dc_link = 0; 2723 mii_mediachg(mii); 2724 } 2725 if (sc->dc_link == 0) 2726 mii_tick(mii); 2727 } else { 2728 r = CSR_READ_4(sc, DC_ISR); 2729 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2730 sc->dc_cdata.dc_tx_cnt == 0) 2731 mii_tick(mii); 2732 if (!(mii->mii_media_status & IFM_ACTIVE)) 2733 sc->dc_link = 0; 2734 } 2735 } else 2736 mii_tick(mii); 2737 2738 /* 2739 * When the init routine completes, we expect to be able to send 2740 * packets right away, and in fact the network code will send a 2741 * gratuitous ARP the moment the init routine marks the interface 2742 * as running. However, even though the MAC may have been initialized, 2743 * there may be a delay of a few seconds before the PHY completes 2744 * autonegotiation and the link is brought up. Any transmissions 2745 * made during that delay will be lost. Dealing with this is tricky: 2746 * we can't just pause in the init routine while waiting for the 2747 * PHY to come ready since that would bring the whole system to 2748 * a screeching halt for several seconds. 2749 * 2750 * What we do here is prevent the TX start routine from sending 2751 * any packets until a link has been established. After the 2752 * interface has been initialized, the tick routine will poll 2753 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2754 * that time, packets will stay in the send queue, and once the 2755 * link comes up, they will be flushed out to the wire. 2756 */ 2757 if (!sc->dc_link) { 2758 mii_pollstat(mii); 2759 if (mii->mii_media_status & IFM_ACTIVE && 2760 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2761 sc->dc_link++; 2762 if (ifp->if_snd.ifq_head != NULL) 2763 dc_start(ifp); 2764 } 2765 } 2766 2767 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2768 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2769 else 2770 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2771 2772 splx(s); 2773 2774 return; 2775 } 2776 2777 /* 2778 * A transmit underrun has occurred. Back off the transmit threshold, 2779 * or switch to store and forward mode if we have to. 2780 */ 2781 static void dc_tx_underrun(sc) 2782 struct dc_softc *sc; 2783 { 2784 u_int32_t isr; 2785 int i; 2786 2787 if (DC_IS_DAVICOM(sc)) 2788 dc_init(sc); 2789 2790 if (DC_IS_INTEL(sc)) { 2791 /* 2792 * The real 21143 requires that the transmitter be idle 2793 * in order to change the transmit threshold or store 2794 * and forward state. 2795 */ 2796 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2797 2798 for (i = 0; i < DC_TIMEOUT; i++) { 2799 isr = CSR_READ_4(sc, DC_ISR); 2800 if (isr & DC_ISR_TX_IDLE) 2801 break; 2802 DELAY(10); 2803 } 2804 if (i == DC_TIMEOUT) { 2805 printf("dc%d: failed to force tx to idle state\n", 2806 sc->dc_unit); 2807 dc_init(sc); 2808 } 2809 } 2810 2811 printf("dc%d: TX underrun -- ", sc->dc_unit); 2812 sc->dc_txthresh += DC_TXTHRESH_INC; 2813 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2814 printf("using store and forward mode\n"); 2815 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2816 } else { 2817 printf("increasing TX threshold\n"); 2818 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2819 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2820 } 2821 2822 if (DC_IS_INTEL(sc)) 2823 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2824 2825 return; 2826 } 2827 2828 #ifdef DEVICE_POLLING 2829 static poll_handler_t dc_poll; 2830 2831 static void 2832 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2833 { 2834 struct dc_softc *sc = ifp->if_softc; 2835 2836 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2837 /* Re-enable interrupts. */ 2838 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2839 return; 2840 } 2841 sc->rxcycles = count; 2842 dc_rxeof(sc); 2843 dc_txeof(sc); 2844 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2845 dc_start(ifp); 2846 2847 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2848 u_int32_t status; 2849 2850 status = CSR_READ_4(sc, DC_ISR); 2851 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2852 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2853 DC_ISR_BUS_ERR); 2854 if (!status) 2855 return ; 2856 /* ack what we have */ 2857 CSR_WRITE_4(sc, DC_ISR, status); 2858 2859 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2860 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2861 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2862 2863 if (dc_rx_resync(sc)) 2864 dc_rxeof(sc); 2865 } 2866 /* restart transmit unit if necessary */ 2867 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2868 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2869 2870 if (status & DC_ISR_TX_UNDERRUN) 2871 dc_tx_underrun(sc); 2872 2873 if (status & DC_ISR_BUS_ERR) { 2874 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2875 dc_reset(sc); 2876 dc_init(sc); 2877 } 2878 } 2879 } 2880 #endif /* DEVICE_POLLING */ 2881 2882 static void dc_intr(arg) 2883 void *arg; 2884 { 2885 struct dc_softc *sc; 2886 struct ifnet *ifp; 2887 u_int32_t status; 2888 2889 sc = arg; 2890 2891 if (sc->suspended) { 2892 return; 2893 } 2894 2895 ifp = &sc->arpcom.ac_if; 2896 2897 #ifdef DEVICE_POLLING 2898 if (ifp->if_ipending & IFF_POLLING) 2899 return; 2900 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2901 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2902 return; 2903 } 2904 #endif /* DEVICE_POLLING */ 2905 2906 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2907 return ; 2908 2909 /* Suppress unwanted interrupts */ 2910 if (!(ifp->if_flags & IFF_UP)) { 2911 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2912 dc_stop(sc); 2913 return; 2914 } 2915 2916 /* Disable interrupts. */ 2917 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2918 2919 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2920 2921 CSR_WRITE_4(sc, DC_ISR, status); 2922 2923 if (status & DC_ISR_RX_OK) { 2924 int curpkts; 2925 curpkts = ifp->if_ipackets; 2926 dc_rxeof(sc); 2927 if (curpkts == ifp->if_ipackets) { 2928 while(dc_rx_resync(sc)) 2929 dc_rxeof(sc); 2930 } 2931 } 2932 2933 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2934 dc_txeof(sc); 2935 2936 if (status & DC_ISR_TX_IDLE) { 2937 dc_txeof(sc); 2938 if (sc->dc_cdata.dc_tx_cnt) { 2939 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2940 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2941 } 2942 } 2943 2944 if (status & DC_ISR_TX_UNDERRUN) 2945 dc_tx_underrun(sc); 2946 2947 if ((status & DC_ISR_RX_WATDOGTIMEO) 2948 || (status & DC_ISR_RX_NOBUF)) { 2949 int curpkts; 2950 curpkts = ifp->if_ipackets; 2951 dc_rxeof(sc); 2952 if (curpkts == ifp->if_ipackets) { 2953 while(dc_rx_resync(sc)) 2954 dc_rxeof(sc); 2955 } 2956 } 2957 2958 if (status & DC_ISR_BUS_ERR) { 2959 dc_reset(sc); 2960 dc_init(sc); 2961 } 2962 } 2963 2964 /* Re-enable interrupts. */ 2965 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2966 2967 if (ifp->if_snd.ifq_head != NULL) 2968 dc_start(ifp); 2969 2970 return; 2971 } 2972 2973 /* 2974 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2975 * pointers to the fragment pointers. 2976 */ 2977 static int dc_encap(sc, m_head, txidx) 2978 struct dc_softc *sc; 2979 struct mbuf *m_head; 2980 u_int32_t *txidx; 2981 { 2982 struct dc_desc *f = NULL; 2983 struct mbuf *m; 2984 int frag, cur, cnt = 0; 2985 2986 /* 2987 * Start packing the mbufs in this chain into 2988 * the fragment pointers. Stop when we run out 2989 * of fragments or hit the end of the mbuf chain. 2990 */ 2991 m = m_head; 2992 cur = frag = *txidx; 2993 2994 for (m = m_head; m != NULL; m = m->m_next) { 2995 if (m->m_len != 0) { 2996 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2997 if (*txidx != sc->dc_cdata.dc_tx_prod && 2998 frag == (DC_TX_LIST_CNT - 1)) 2999 return(ENOBUFS); 3000 } 3001 if ((DC_TX_LIST_CNT - 3002 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3003 return(ENOBUFS); 3004 3005 f = &sc->dc_ldata->dc_tx_list[frag]; 3006 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3007 if (cnt == 0) { 3008 f->dc_status = 0; 3009 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3010 } else 3011 f->dc_status = DC_TXSTAT_OWN; 3012 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3013 cur = frag; 3014 DC_INC(frag, DC_TX_LIST_CNT); 3015 cnt++; 3016 } 3017 } 3018 3019 if (m != NULL) 3020 return(ENOBUFS); 3021 3022 sc->dc_cdata.dc_tx_cnt += cnt; 3023 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3024 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3025 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3026 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3027 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3028 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3029 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3030 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3031 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3032 *txidx = frag; 3033 3034 return(0); 3035 } 3036 3037 /* 3038 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3039 * Needed for some really badly behaved chips that just can't 3040 * do scatter/gather correctly. 3041 */ 3042 static int dc_coal(sc, m_head) 3043 struct dc_softc *sc; 3044 struct mbuf **m_head; 3045 { 3046 struct mbuf *m_new, *m; 3047 3048 m = *m_head; 3049 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3050 if (m_new == NULL) 3051 return(ENOBUFS); 3052 if (m->m_pkthdr.len > MHLEN) { 3053 MCLGET(m_new, M_DONTWAIT); 3054 if (!(m_new->m_flags & M_EXT)) { 3055 m_freem(m_new); 3056 return(ENOBUFS); 3057 } 3058 } 3059 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3060 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3061 m_freem(m); 3062 *m_head = m_new; 3063 3064 return(0); 3065 } 3066 3067 /* 3068 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3069 * to the mbuf data regions directly in the transmit lists. We also save a 3070 * copy of the pointers since the transmit list fragment pointers are 3071 * physical addresses. 3072 */ 3073 3074 static void dc_start(ifp) 3075 struct ifnet *ifp; 3076 { 3077 struct dc_softc *sc; 3078 struct mbuf *m_head = NULL; 3079 int idx; 3080 3081 sc = ifp->if_softc; 3082 3083 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3084 return; 3085 3086 if (ifp->if_flags & IFF_OACTIVE) 3087 return; 3088 3089 idx = sc->dc_cdata.dc_tx_prod; 3090 3091 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3092 IF_DEQUEUE(&ifp->if_snd, m_head); 3093 if (m_head == NULL) 3094 break; 3095 3096 if (sc->dc_flags & DC_TX_COALESCE && 3097 m_head->m_next != NULL) { 3098 /* only coalesce if have >1 mbufs */ 3099 if (dc_coal(sc, &m_head)) { 3100 IF_PREPEND(&ifp->if_snd, m_head); 3101 ifp->if_flags |= IFF_OACTIVE; 3102 break; 3103 } 3104 } 3105 3106 if (dc_encap(sc, m_head, &idx)) { 3107 IF_PREPEND(&ifp->if_snd, m_head); 3108 ifp->if_flags |= IFF_OACTIVE; 3109 break; 3110 } 3111 3112 /* 3113 * If there's a BPF listener, bounce a copy of this frame 3114 * to him. 3115 */ 3116 if (ifp->if_bpf) 3117 bpf_mtap(ifp, m_head); 3118 3119 if (sc->dc_flags & DC_TX_ONE) { 3120 ifp->if_flags |= IFF_OACTIVE; 3121 break; 3122 } 3123 } 3124 3125 /* Transmit */ 3126 sc->dc_cdata.dc_tx_prod = idx; 3127 if (!(sc->dc_flags & DC_TX_POLL)) 3128 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3129 3130 /* 3131 * Set a timeout in case the chip goes out to lunch. 3132 */ 3133 ifp->if_timer = 5; 3134 3135 return; 3136 } 3137 3138 static void dc_init(xsc) 3139 void *xsc; 3140 { 3141 struct dc_softc *sc = xsc; 3142 struct ifnet *ifp = &sc->arpcom.ac_if; 3143 struct mii_data *mii; 3144 int s; 3145 3146 s = splimp(); 3147 3148 mii = device_get_softc(sc->dc_miibus); 3149 3150 /* 3151 * Cancel pending I/O and free all RX/TX buffers. 3152 */ 3153 dc_stop(sc); 3154 dc_reset(sc); 3155 3156 /* 3157 * Set cache alignment and burst length. 3158 */ 3159 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3160 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3161 else 3162 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3163 /* 3164 * Evenly share the bus between receive and transmit process. 3165 */ 3166 if (DC_IS_INTEL(sc)) 3167 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3168 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3169 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3170 } else { 3171 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3172 } 3173 if (sc->dc_flags & DC_TX_POLL) 3174 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3175 switch(sc->dc_cachesize) { 3176 case 32: 3177 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3178 break; 3179 case 16: 3180 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3181 break; 3182 case 8: 3183 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3184 break; 3185 case 0: 3186 default: 3187 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3188 break; 3189 } 3190 3191 if (sc->dc_flags & DC_TX_STORENFWD) 3192 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3193 else { 3194 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3195 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3196 } else { 3197 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3198 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3199 } 3200 } 3201 3202 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3203 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3204 3205 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3206 /* 3207 * The app notes for the 98713 and 98715A say that 3208 * in order to have the chips operate properly, a magic 3209 * number must be written to CSR16. Macronix does not 3210 * document the meaning of these bits so there's no way 3211 * to know exactly what they do. The 98713 has a magic 3212 * number all its own; the rest all use a different one. 3213 */ 3214 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3215 if (sc->dc_type == DC_TYPE_98713) 3216 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3217 else 3218 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3219 } 3220 3221 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3222 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3223 3224 /* Init circular RX list. */ 3225 if (dc_list_rx_init(sc) == ENOBUFS) { 3226 printf("dc%d: initialization failed: no " 3227 "memory for rx buffers\n", sc->dc_unit); 3228 dc_stop(sc); 3229 (void)splx(s); 3230 return; 3231 } 3232 3233 /* 3234 * Init tx descriptors. 3235 */ 3236 dc_list_tx_init(sc); 3237 3238 /* 3239 * Load the address of the RX list. 3240 */ 3241 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3242 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3243 3244 /* 3245 * Enable interrupts. 3246 */ 3247 #ifdef DEVICE_POLLING 3248 /* 3249 * ... but only if we are not polling, and make sure they are off in 3250 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3251 * after a reset. 3252 */ 3253 if (ifp->if_ipending & IFF_POLLING) 3254 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3255 else 3256 #endif 3257 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3258 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3259 3260 /* Enable transmitter. */ 3261 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3262 3263 /* 3264 * If this is an Intel 21143 and we're not using the 3265 * MII port, program the LED control pins so we get 3266 * link and activity indications. 3267 */ 3268 if (sc->dc_flags & DC_TULIP_LEDS) { 3269 CSR_WRITE_4(sc, DC_WATCHDOG, 3270 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3271 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3272 } 3273 3274 /* 3275 * Load the RX/multicast filter. We do this sort of late 3276 * because the filter programming scheme on the 21143 and 3277 * some clones requires DMAing a setup frame via the TX 3278 * engine, and we need the transmitter enabled for that. 3279 */ 3280 dc_setfilt(sc); 3281 3282 /* Enable receiver. */ 3283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3284 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3285 3286 mii_mediachg(mii); 3287 dc_setcfg(sc, sc->dc_if_media); 3288 3289 ifp->if_flags |= IFF_RUNNING; 3290 ifp->if_flags &= ~IFF_OACTIVE; 3291 3292 (void)splx(s); 3293 3294 /* Don't start the ticker if this is a homePNA link. */ 3295 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3296 sc->dc_link = 1; 3297 else { 3298 if (sc->dc_flags & DC_21143_NWAY) 3299 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 3300 else 3301 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 3302 } 3303 3304 #ifdef SRM_MEDIA 3305 if(sc->dc_srm_media) { 3306 struct ifreq ifr; 3307 3308 ifr.ifr_media = sc->dc_srm_media; 3309 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3310 sc->dc_srm_media = 0; 3311 } 3312 #endif 3313 return; 3314 } 3315 3316 /* 3317 * Set media options. 3318 */ 3319 static int dc_ifmedia_upd(ifp) 3320 struct ifnet *ifp; 3321 { 3322 struct dc_softc *sc; 3323 struct mii_data *mii; 3324 struct ifmedia *ifm; 3325 3326 sc = ifp->if_softc; 3327 mii = device_get_softc(sc->dc_miibus); 3328 mii_mediachg(mii); 3329 ifm = &mii->mii_media; 3330 3331 if (DC_IS_DAVICOM(sc) && 3332 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3333 dc_setcfg(sc, ifm->ifm_media); 3334 else 3335 sc->dc_link = 0; 3336 3337 return(0); 3338 } 3339 3340 /* 3341 * Report current media status. 3342 */ 3343 static void dc_ifmedia_sts(ifp, ifmr) 3344 struct ifnet *ifp; 3345 struct ifmediareq *ifmr; 3346 { 3347 struct dc_softc *sc; 3348 struct mii_data *mii; 3349 struct ifmedia *ifm; 3350 3351 sc = ifp->if_softc; 3352 mii = device_get_softc(sc->dc_miibus); 3353 mii_pollstat(mii); 3354 ifm = &mii->mii_media; 3355 if (DC_IS_DAVICOM(sc)) { 3356 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3357 ifmr->ifm_active = ifm->ifm_media; 3358 ifmr->ifm_status = 0; 3359 return; 3360 } 3361 } 3362 ifmr->ifm_active = mii->mii_media_active; 3363 ifmr->ifm_status = mii->mii_media_status; 3364 3365 return; 3366 } 3367 3368 static int dc_ioctl(ifp, command, data) 3369 struct ifnet *ifp; 3370 u_long command; 3371 caddr_t data; 3372 { 3373 struct dc_softc *sc = ifp->if_softc; 3374 struct ifreq *ifr = (struct ifreq *) data; 3375 struct mii_data *mii; 3376 int s, error = 0; 3377 3378 s = splimp(); 3379 3380 switch(command) { 3381 case SIOCSIFADDR: 3382 case SIOCGIFADDR: 3383 case SIOCSIFMTU: 3384 error = ether_ioctl(ifp, command, data); 3385 break; 3386 case SIOCSIFFLAGS: 3387 if (ifp->if_flags & IFF_UP) { 3388 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3389 (IFF_PROMISC | IFF_ALLMULTI); 3390 if (ifp->if_flags & IFF_RUNNING) { 3391 if (need_setfilt) 3392 dc_setfilt(sc); 3393 } else { 3394 sc->dc_txthresh = 0; 3395 dc_init(sc); 3396 } 3397 } else { 3398 if (ifp->if_flags & IFF_RUNNING) 3399 dc_stop(sc); 3400 } 3401 sc->dc_if_flags = ifp->if_flags; 3402 error = 0; 3403 break; 3404 case SIOCADDMULTI: 3405 case SIOCDELMULTI: 3406 dc_setfilt(sc); 3407 error = 0; 3408 break; 3409 case SIOCGIFMEDIA: 3410 case SIOCSIFMEDIA: 3411 mii = device_get_softc(sc->dc_miibus); 3412 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3413 #ifdef SRM_MEDIA 3414 if (sc->dc_srm_media) 3415 sc->dc_srm_media = 0; 3416 #endif 3417 break; 3418 default: 3419 error = EINVAL; 3420 break; 3421 } 3422 3423 (void)splx(s); 3424 3425 return(error); 3426 } 3427 3428 static void dc_watchdog(ifp) 3429 struct ifnet *ifp; 3430 { 3431 struct dc_softc *sc; 3432 3433 sc = ifp->if_softc; 3434 3435 ifp->if_oerrors++; 3436 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3437 3438 dc_stop(sc); 3439 dc_reset(sc); 3440 dc_init(sc); 3441 3442 if (ifp->if_snd.ifq_head != NULL) 3443 dc_start(ifp); 3444 3445 return; 3446 } 3447 3448 /* 3449 * Stop the adapter and free any mbufs allocated to the 3450 * RX and TX lists. 3451 */ 3452 static void dc_stop(sc) 3453 struct dc_softc *sc; 3454 { 3455 int i; 3456 struct ifnet *ifp; 3457 3458 ifp = &sc->arpcom.ac_if; 3459 ifp->if_timer = 0; 3460 3461 untimeout(dc_tick, sc, sc->dc_stat_ch); 3462 3463 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3464 #ifdef DEVICE_POLLING 3465 ether_poll_deregister(ifp); 3466 #endif 3467 3468 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3469 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3470 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3471 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3472 sc->dc_link = 0; 3473 3474 /* 3475 * Free data in the RX lists. 3476 */ 3477 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3478 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3479 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3480 sc->dc_cdata.dc_rx_chain[i] = NULL; 3481 } 3482 } 3483 bzero((char *)&sc->dc_ldata->dc_rx_list, 3484 sizeof(sc->dc_ldata->dc_rx_list)); 3485 3486 /* 3487 * Free the TX list buffers. 3488 */ 3489 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3490 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3491 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3492 DC_TXCTL_SETUP) || 3493 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3494 DC_TXCTL_LASTFRAG)) { 3495 sc->dc_cdata.dc_tx_chain[i] = NULL; 3496 continue; 3497 } 3498 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3499 sc->dc_cdata.dc_tx_chain[i] = NULL; 3500 } 3501 } 3502 3503 bzero((char *)&sc->dc_ldata->dc_tx_list, 3504 sizeof(sc->dc_ldata->dc_tx_list)); 3505 3506 return; 3507 } 3508 3509 /* 3510 * Stop all chip I/O so that the kernel's probe routines don't 3511 * get confused by errant DMAs when rebooting. 3512 */ 3513 static void dc_shutdown(dev) 3514 device_t dev; 3515 { 3516 struct dc_softc *sc; 3517 3518 sc = device_get_softc(dev); 3519 3520 dc_stop(sc); 3521 3522 return; 3523 } 3524 3525 /* 3526 * Device suspend routine. Stop the interface and save some PCI 3527 * settings in case the BIOS doesn't restore them properly on 3528 * resume. 3529 */ 3530 static int dc_suspend(dev) 3531 device_t dev; 3532 { 3533 int i; 3534 int s; 3535 struct dc_softc *sc; 3536 3537 s = splimp(); 3538 3539 sc = device_get_softc(dev); 3540 3541 dc_stop(sc); 3542 3543 for (i = 0; i < 5; i++) 3544 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3545 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3546 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3547 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3548 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3549 3550 sc->suspended = 1; 3551 3552 splx(s); 3553 return (0); 3554 } 3555 3556 /* 3557 * Device resume routine. Restore some PCI settings in case the BIOS 3558 * doesn't, re-enable busmastering, and restart the interface if 3559 * appropriate. 3560 */ 3561 static int dc_resume(dev) 3562 device_t dev; 3563 { 3564 int i; 3565 int s; 3566 struct dc_softc *sc; 3567 struct ifnet *ifp; 3568 3569 s = splimp(); 3570 3571 sc = device_get_softc(dev); 3572 ifp = &sc->arpcom.ac_if; 3573 3574 dc_acpi(dev); 3575 3576 /* better way to do this? */ 3577 for (i = 0; i < 5; i++) 3578 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3579 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3580 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3581 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3582 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3583 3584 /* reenable busmastering */ 3585 pci_enable_busmaster(dev); 3586 pci_enable_io(dev, DC_RES); 3587 3588 /* reinitialize interface if necessary */ 3589 if (ifp->if_flags & IFF_UP) 3590 dc_init(sc); 3591 3592 sc->suspended = 0; 3593 3594 splx(s); 3595 return (0); 3596 } 3597