1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.46 2005/11/22 00:24:25 dillon Exp $ 34 */ 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 48 * Accton EN1217 (www.accton.com) 49 * Conexant LANfinity (www.conexant.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include "opt_polling.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/sysctl.h> 101 #include <sys/thread2.h> 102 103 #include <net/if.h> 104 #include <net/ifq_var.h> 105 #include <net/if_arp.h> 106 #include <net/ethernet.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_types.h> 110 #include <net/vlan/if_vlan_var.h> 111 112 #include <net/bpf.h> 113 114 #include <vm/vm.h> /* for vtophys */ 115 #include <vm/pmap.h> /* for vtophys */ 116 #include <machine/bus_pio.h> 117 #include <machine/bus_memio.h> 118 #include <machine/bus.h> 119 #include <machine/resource.h> 120 #include <sys/bus.h> 121 #include <sys/rman.h> 122 123 #include "../mii_layer/mii.h" 124 #include "../mii_layer/miivar.h" 125 126 #include <bus/pci/pcireg.h> 127 #include <bus/pci/pcivar.h> 128 129 #define DC_USEIOSPACE 130 131 #include "if_dcreg.h" 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 static const struct dc_type dc_devs[] = { 140 { DC_VENDORID_DEC, DC_DEVICEID_21143, 141 "Intel 21143 10/100BaseTX" }, 142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 143 "Davicom DM9009 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 145 "Davicom DM9100 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 147 "Davicom DM9102 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 149 "Davicom DM9102A 10/100BaseTX" }, 150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 151 "ADMtek AL981 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 153 "ADMtek AN985 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 155 "ADMtek ADM9511 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 157 "ADMtek ADM9513 10/100BaseTX" }, 158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 159 "ASIX AX88140A 10/100BaseTX" }, 160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 161 "ASIX AX88141 10/100BaseTX" }, 162 { DC_VENDORID_MX, DC_DEVICEID_98713, 163 "Macronix 98713 10/100BaseTX" }, 164 { DC_VENDORID_MX, DC_DEVICEID_98713, 165 "Macronix 98713A 10/100BaseTX" }, 166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 167 "Compex RL100-TX 10/100BaseTX" }, 168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 169 "Compex RL100-TX 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98715/98715A 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98715AEC-C 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_987x5, 175 "Macronix 98725 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_98727, 177 "Macronix 98727/98732 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C115, 179 "LC82C115 PNIC II 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C168, 181 "82c168 PNIC 10/100BaseTX" }, 182 { DC_VENDORID_LO, DC_DEVICEID_82C168, 183 "82c169 PNIC 10/100BaseTX" }, 184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 185 "Accton EN1217 10/100BaseTX" }, 186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 187 "Accton EN2242 MiniPCI 10/100BaseTX" }, 188 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 189 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 190 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 191 "3Com OfficeConnect 10/100B" }, 192 { 0, 0, NULL } 193 }; 194 195 static int dc_probe (device_t); 196 static int dc_attach (device_t); 197 static int dc_detach (device_t); 198 static int dc_suspend (device_t); 199 static int dc_resume (device_t); 200 static void dc_acpi (device_t); 201 static const struct dc_type *dc_devtype (device_t); 202 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 203 static int dc_encap (struct dc_softc *, struct mbuf *, 204 u_int32_t *); 205 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 206 static int dc_rx_resync (struct dc_softc *); 207 static void dc_rxeof (struct dc_softc *); 208 static void dc_txeof (struct dc_softc *); 209 static void dc_tick (void *); 210 static void dc_tx_underrun (struct dc_softc *); 211 static void dc_intr (void *); 212 static void dc_start (struct ifnet *); 213 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 214 struct ucred *); 215 #ifdef DEVICE_POLLING 216 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd, 217 int count); 218 #endif 219 static void dc_init (void *); 220 static void dc_stop (struct dc_softc *); 221 static void dc_watchdog (struct ifnet *); 222 static void dc_shutdown (device_t); 223 static int dc_ifmedia_upd (struct ifnet *); 224 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 225 226 static void dc_delay (struct dc_softc *); 227 static void dc_eeprom_idle (struct dc_softc *); 228 static void dc_eeprom_putbyte (struct dc_softc *, int); 229 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 230 static void dc_eeprom_getword_pnic 231 (struct dc_softc *, int, u_int16_t *); 232 static void dc_eeprom_width (struct dc_softc *); 233 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 234 int, int); 235 236 static void dc_mii_writebit (struct dc_softc *, int); 237 static int dc_mii_readbit (struct dc_softc *); 238 static void dc_mii_sync (struct dc_softc *); 239 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 240 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 241 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 242 static int dc_miibus_readreg (device_t, int, int); 243 static int dc_miibus_writereg (device_t, int, int, int); 244 static void dc_miibus_statchg (device_t); 245 static void dc_miibus_mediainit (device_t); 246 247 static u_int32_t dc_crc_mask (struct dc_softc *); 248 static void dc_setcfg (struct dc_softc *, int); 249 static void dc_setfilt_21143 (struct dc_softc *); 250 static void dc_setfilt_asix (struct dc_softc *); 251 static void dc_setfilt_admtek (struct dc_softc *); 252 253 static void dc_setfilt (struct dc_softc *); 254 255 static void dc_reset (struct dc_softc *); 256 static int dc_list_rx_init (struct dc_softc *); 257 static int dc_list_tx_init (struct dc_softc *); 258 259 static void dc_read_srom (struct dc_softc *, int); 260 static void dc_parse_21143_srom (struct dc_softc *); 261 static void dc_decode_leaf_sia (struct dc_softc *, 262 struct dc_eblock_sia *); 263 static void dc_decode_leaf_mii (struct dc_softc *, 264 struct dc_eblock_mii *); 265 static void dc_decode_leaf_sym (struct dc_softc *, 266 struct dc_eblock_sym *); 267 static void dc_apply_fixup (struct dc_softc *, int); 268 269 #ifdef DC_USEIOSPACE 270 #define DC_RES SYS_RES_IOPORT 271 #define DC_RID DC_PCI_CFBIO 272 #else 273 #define DC_RES SYS_RES_MEMORY 274 #define DC_RID DC_PCI_CFBMA 275 #endif 276 277 static device_method_t dc_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, dc_probe), 280 DEVMETHOD(device_attach, dc_attach), 281 DEVMETHOD(device_detach, dc_detach), 282 DEVMETHOD(device_suspend, dc_suspend), 283 DEVMETHOD(device_resume, dc_resume), 284 DEVMETHOD(device_shutdown, dc_shutdown), 285 286 /* bus interface */ 287 DEVMETHOD(bus_print_child, bus_generic_print_child), 288 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 292 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 293 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 294 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 295 296 { 0, 0 } 297 }; 298 299 static driver_t dc_driver = { 300 "dc", 301 dc_methods, 302 sizeof(struct dc_softc) 303 }; 304 305 static devclass_t dc_devclass; 306 307 #ifdef __i386__ 308 static int dc_quick=1; 309 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 310 &dc_quick,0,"do not mdevget in dc driver"); 311 #endif 312 313 DECLARE_DUMMY_MODULE(if_dc); 314 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 315 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 316 317 #define DC_SETBIT(sc, reg, x) \ 318 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 319 320 #define DC_CLRBIT(sc, reg, x) \ 321 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 322 323 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 324 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 325 326 static void 327 dc_delay(struct dc_softc *sc) 328 { 329 int idx; 330 331 for (idx = (300 / 33) + 1; idx > 0; idx--) 332 CSR_READ_4(sc, DC_BUSCTL); 333 } 334 335 static void 336 dc_eeprom_width(struct dc_softc *sc) 337 { 338 int i; 339 340 /* Force EEPROM to idle state. */ 341 dc_eeprom_idle(sc); 342 343 /* Enter EEPROM access mode. */ 344 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 345 dc_delay(sc); 346 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 347 dc_delay(sc); 348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 349 dc_delay(sc); 350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 351 dc_delay(sc); 352 353 for (i = 3; i--;) { 354 if (6 & (1 << i)) 355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 356 else 357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 358 dc_delay(sc); 359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 360 dc_delay(sc); 361 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 362 dc_delay(sc); 363 } 364 365 for (i = 1; i <= 12; i++) { 366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 367 dc_delay(sc); 368 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 break; 372 } 373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 } 376 377 /* Turn off EEPROM access mode. */ 378 dc_eeprom_idle(sc); 379 380 if (i < 4 || i > 12) 381 sc->dc_romwidth = 6; 382 else 383 sc->dc_romwidth = i; 384 385 /* Enter EEPROM access mode. */ 386 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 387 dc_delay(sc); 388 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 389 dc_delay(sc); 390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 393 dc_delay(sc); 394 395 /* Turn off EEPROM access mode. */ 396 dc_eeprom_idle(sc); 397 } 398 399 static void 400 dc_eeprom_idle(struct dc_softc *sc) 401 { 402 int i; 403 404 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 405 dc_delay(sc); 406 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 407 dc_delay(sc); 408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 409 dc_delay(sc); 410 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 411 dc_delay(sc); 412 413 for (i = 0; i < 25; i++) { 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 } 419 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 421 dc_delay(sc); 422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 423 dc_delay(sc); 424 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 425 426 return; 427 } 428 429 /* 430 * Send a read command and address to the EEPROM, check for ACK. 431 */ 432 static void 433 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 434 { 435 int d, i; 436 437 d = DC_EECMD_READ >> 6; 438 for (i = 3; i--; ) { 439 if (d & (1 << i)) 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 441 else 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 443 dc_delay(sc); 444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 447 dc_delay(sc); 448 } 449 450 /* 451 * Feed in each bit and strobe the clock. 452 */ 453 for (i = sc->dc_romwidth; i--;) { 454 if (addr & (1 << i)) { 455 SIO_SET(DC_SIO_EE_DATAIN); 456 } else { 457 SIO_CLR(DC_SIO_EE_DATAIN); 458 } 459 dc_delay(sc); 460 SIO_SET(DC_SIO_EE_CLK); 461 dc_delay(sc); 462 SIO_CLR(DC_SIO_EE_CLK); 463 dc_delay(sc); 464 } 465 466 return; 467 } 468 469 /* 470 * Read a word of data stored in the EEPROM at address 'addr.' 471 * The PNIC 82c168/82c169 has its own non-standard way to read 472 * the EEPROM. 473 */ 474 static void 475 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 476 { 477 int i; 478 u_int32_t r; 479 480 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 481 482 for (i = 0; i < DC_TIMEOUT; i++) { 483 DELAY(1); 484 r = CSR_READ_4(sc, DC_SIO); 485 if (!(r & DC_PN_SIOCTL_BUSY)) { 486 *dest = (u_int16_t)(r & 0xFFFF); 487 return; 488 } 489 } 490 491 return; 492 } 493 494 /* 495 * Read a word of data stored in the EEPROM at address 'addr.' 496 */ 497 static void 498 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 499 { 500 int i; 501 u_int16_t word = 0; 502 503 /* Force EEPROM to idle state. */ 504 dc_eeprom_idle(sc); 505 506 /* Enter EEPROM access mode. */ 507 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 508 dc_delay(sc); 509 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 510 dc_delay(sc); 511 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 512 dc_delay(sc); 513 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 514 dc_delay(sc); 515 516 /* 517 * Send address of word we want to read. 518 */ 519 dc_eeprom_putbyte(sc, addr); 520 521 /* 522 * Start reading bits from EEPROM. 523 */ 524 for (i = 0x8000; i; i >>= 1) { 525 SIO_SET(DC_SIO_EE_CLK); 526 dc_delay(sc); 527 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 528 word |= i; 529 dc_delay(sc); 530 SIO_CLR(DC_SIO_EE_CLK); 531 dc_delay(sc); 532 } 533 534 /* Turn off EEPROM access mode. */ 535 dc_eeprom_idle(sc); 536 537 *dest = word; 538 539 return; 540 } 541 542 /* 543 * Read a sequence of words from the EEPROM. 544 */ 545 static void 546 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 547 { 548 int i; 549 u_int16_t word = 0, *ptr; 550 551 for (i = 0; i < cnt; i++) { 552 if (DC_IS_PNIC(sc)) 553 dc_eeprom_getword_pnic(sc, off + i, &word); 554 else 555 dc_eeprom_getword(sc, off + i, &word); 556 ptr = (u_int16_t *)(dest + (i * 2)); 557 if (swap) 558 *ptr = ntohs(word); 559 else 560 *ptr = word; 561 } 562 563 return; 564 } 565 566 /* 567 * The following two routines are taken from the Macronix 98713 568 * Application Notes pp.19-21. 569 */ 570 /* 571 * Write a bit to the MII bus. 572 */ 573 static void 574 dc_mii_writebit(struct dc_softc *sc, int bit) 575 { 576 if (bit) 577 CSR_WRITE_4(sc, DC_SIO, 578 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 579 else 580 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 581 582 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 583 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 584 585 return; 586 } 587 588 /* 589 * Read a bit from the MII bus. 590 */ 591 static int 592 dc_mii_readbit(struct dc_softc *sc) 593 { 594 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 595 CSR_READ_4(sc, DC_SIO); 596 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 597 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 598 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 599 return(1); 600 601 return(0); 602 } 603 604 /* 605 * Sync the PHYs by setting data bit and strobing the clock 32 times. 606 */ 607 static void 608 dc_mii_sync(struct dc_softc *sc) 609 { 610 int i; 611 612 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 613 614 for (i = 0; i < 32; i++) 615 dc_mii_writebit(sc, 1); 616 617 return; 618 } 619 620 /* 621 * Clock a series of bits through the MII. 622 */ 623 static void 624 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 625 { 626 int i; 627 628 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 629 dc_mii_writebit(sc, bits & i); 630 } 631 632 /* 633 * Read an PHY register through the MII. 634 */ 635 static int 636 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 637 { 638 int ack, i; 639 640 crit_enter(); 641 642 /* 643 * Set up frame for RX. 644 */ 645 frame->mii_stdelim = DC_MII_STARTDELIM; 646 frame->mii_opcode = DC_MII_READOP; 647 frame->mii_turnaround = 0; 648 frame->mii_data = 0; 649 650 /* 651 * Sync the PHYs. 652 */ 653 dc_mii_sync(sc); 654 655 /* 656 * Send command/address info. 657 */ 658 dc_mii_send(sc, frame->mii_stdelim, 2); 659 dc_mii_send(sc, frame->mii_opcode, 2); 660 dc_mii_send(sc, frame->mii_phyaddr, 5); 661 dc_mii_send(sc, frame->mii_regaddr, 5); 662 663 #ifdef notdef 664 /* Idle bit */ 665 dc_mii_writebit(sc, 1); 666 dc_mii_writebit(sc, 0); 667 #endif 668 669 /* Check for ack */ 670 ack = dc_mii_readbit(sc); 671 672 /* 673 * Now try reading data bits. If the ack failed, we still 674 * need to clock through 16 cycles to keep the PHY(s) in sync. 675 */ 676 if (ack) { 677 for(i = 0; i < 16; i++) { 678 dc_mii_readbit(sc); 679 } 680 goto fail; 681 } 682 683 for (i = 0x8000; i; i >>= 1) { 684 if (!ack) { 685 if (dc_mii_readbit(sc)) 686 frame->mii_data |= i; 687 } 688 } 689 690 fail: 691 692 dc_mii_writebit(sc, 0); 693 dc_mii_writebit(sc, 0); 694 695 crit_exit(); 696 697 if (ack) 698 return(1); 699 return(0); 700 } 701 702 /* 703 * Write to a PHY register through the MII. 704 */ 705 static int 706 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 707 { 708 crit_enter(); 709 710 /* 711 * Set up frame for TX. 712 */ 713 714 frame->mii_stdelim = DC_MII_STARTDELIM; 715 frame->mii_opcode = DC_MII_WRITEOP; 716 frame->mii_turnaround = DC_MII_TURNAROUND; 717 718 /* 719 * Sync the PHYs. 720 */ 721 dc_mii_sync(sc); 722 723 dc_mii_send(sc, frame->mii_stdelim, 2); 724 dc_mii_send(sc, frame->mii_opcode, 2); 725 dc_mii_send(sc, frame->mii_phyaddr, 5); 726 dc_mii_send(sc, frame->mii_regaddr, 5); 727 dc_mii_send(sc, frame->mii_turnaround, 2); 728 dc_mii_send(sc, frame->mii_data, 16); 729 730 /* Idle bit. */ 731 dc_mii_writebit(sc, 0); 732 dc_mii_writebit(sc, 0); 733 734 crit_exit(); 735 736 return(0); 737 } 738 739 static int 740 dc_miibus_readreg(device_t dev, int phy, int reg) 741 { 742 struct dc_mii_frame frame; 743 struct dc_softc *sc; 744 int i, rval, phy_reg = 0; 745 746 sc = device_get_softc(dev); 747 bzero((char *)&frame, sizeof(frame)); 748 749 /* 750 * Note: both the AL981 and AN985 have internal PHYs, 751 * however the AL981 provides direct access to the PHY 752 * registers while the AN985 uses a serial MII interface. 753 * The AN985's MII interface is also buggy in that you 754 * can read from any MII address (0 to 31), but only address 1 755 * behaves normally. To deal with both cases, we pretend 756 * that the PHY is at MII address 1. 757 */ 758 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 759 return(0); 760 761 /* 762 * Note: the ukphy probes of the RS7112 report a PHY at 763 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 764 * so we only respond to correct one. 765 */ 766 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 767 return(0); 768 769 if (sc->dc_pmode != DC_PMODE_MII) { 770 if (phy == (MII_NPHY - 1)) { 771 switch(reg) { 772 case MII_BMSR: 773 /* 774 * Fake something to make the probe 775 * code think there's a PHY here. 776 */ 777 return(BMSR_MEDIAMASK); 778 break; 779 case MII_PHYIDR1: 780 if (DC_IS_PNIC(sc)) 781 return(DC_VENDORID_LO); 782 return(DC_VENDORID_DEC); 783 break; 784 case MII_PHYIDR2: 785 if (DC_IS_PNIC(sc)) 786 return(DC_DEVICEID_82C168); 787 return(DC_DEVICEID_21143); 788 break; 789 default: 790 return(0); 791 break; 792 } 793 } else 794 return(0); 795 } 796 797 if (DC_IS_PNIC(sc)) { 798 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 799 (phy << 23) | (reg << 18)); 800 for (i = 0; i < DC_TIMEOUT; i++) { 801 DELAY(1); 802 rval = CSR_READ_4(sc, DC_PN_MII); 803 if (!(rval & DC_PN_MII_BUSY)) { 804 rval &= 0xFFFF; 805 return(rval == 0xFFFF ? 0 : rval); 806 } 807 } 808 return(0); 809 } 810 811 if (DC_IS_COMET(sc)) { 812 switch(reg) { 813 case MII_BMCR: 814 phy_reg = DC_AL_BMCR; 815 break; 816 case MII_BMSR: 817 phy_reg = DC_AL_BMSR; 818 break; 819 case MII_PHYIDR1: 820 phy_reg = DC_AL_VENID; 821 break; 822 case MII_PHYIDR2: 823 phy_reg = DC_AL_DEVID; 824 break; 825 case MII_ANAR: 826 phy_reg = DC_AL_ANAR; 827 break; 828 case MII_ANLPAR: 829 phy_reg = DC_AL_LPAR; 830 break; 831 case MII_ANER: 832 phy_reg = DC_AL_ANER; 833 break; 834 default: 835 if_printf(&sc->arpcom.ac_if, 836 "phy_read: bad phy register %x\n", reg); 837 return(0); 838 break; 839 } 840 841 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 842 843 if (rval == 0xFFFF) 844 return(0); 845 return(rval); 846 } 847 848 frame.mii_phyaddr = phy; 849 frame.mii_regaddr = reg; 850 if (sc->dc_type == DC_TYPE_98713) { 851 phy_reg = CSR_READ_4(sc, DC_NETCFG); 852 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 853 } 854 dc_mii_readreg(sc, &frame); 855 if (sc->dc_type == DC_TYPE_98713) 856 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 857 858 return(frame.mii_data); 859 } 860 861 static int 862 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 863 { 864 struct dc_softc *sc; 865 struct dc_mii_frame frame; 866 int i, phy_reg = 0; 867 868 sc = device_get_softc(dev); 869 bzero((char *)&frame, sizeof(frame)); 870 871 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 872 return(0); 873 874 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 875 return(0); 876 877 if (DC_IS_PNIC(sc)) { 878 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 879 (phy << 23) | (reg << 10) | data); 880 for (i = 0; i < DC_TIMEOUT; i++) { 881 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 882 break; 883 } 884 return(0); 885 } 886 887 if (DC_IS_COMET(sc)) { 888 switch(reg) { 889 case MII_BMCR: 890 phy_reg = DC_AL_BMCR; 891 break; 892 case MII_BMSR: 893 phy_reg = DC_AL_BMSR; 894 break; 895 case MII_PHYIDR1: 896 phy_reg = DC_AL_VENID; 897 break; 898 case MII_PHYIDR2: 899 phy_reg = DC_AL_DEVID; 900 break; 901 case MII_ANAR: 902 phy_reg = DC_AL_ANAR; 903 break; 904 case MII_ANLPAR: 905 phy_reg = DC_AL_LPAR; 906 break; 907 case MII_ANER: 908 phy_reg = DC_AL_ANER; 909 break; 910 default: 911 if_printf(&sc->arpcom.ac_if, 912 "phy_write: bad phy register %x\n", reg); 913 return(0); 914 break; 915 } 916 917 CSR_WRITE_4(sc, phy_reg, data); 918 return(0); 919 } 920 921 frame.mii_phyaddr = phy; 922 frame.mii_regaddr = reg; 923 frame.mii_data = data; 924 925 if (sc->dc_type == DC_TYPE_98713) { 926 phy_reg = CSR_READ_4(sc, DC_NETCFG); 927 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 928 } 929 dc_mii_writereg(sc, &frame); 930 if (sc->dc_type == DC_TYPE_98713) 931 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 932 933 return(0); 934 } 935 936 static void 937 dc_miibus_statchg(device_t dev) 938 { 939 struct dc_softc *sc; 940 struct mii_data *mii; 941 struct ifmedia *ifm; 942 943 sc = device_get_softc(dev); 944 if (DC_IS_ADMTEK(sc)) 945 return; 946 947 mii = device_get_softc(sc->dc_miibus); 948 ifm = &mii->mii_media; 949 if (DC_IS_DAVICOM(sc) && 950 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 951 dc_setcfg(sc, ifm->ifm_media); 952 sc->dc_if_media = ifm->ifm_media; 953 } else { 954 dc_setcfg(sc, mii->mii_media_active); 955 sc->dc_if_media = mii->mii_media_active; 956 } 957 958 return; 959 } 960 961 /* 962 * Special support for DM9102A cards with HomePNA PHYs. Note: 963 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 964 * to be impossible to talk to the management interface of the DM9801 965 * PHY (its MDIO pin is not connected to anything). Consequently, 966 * the driver has to just 'know' about the additional mode and deal 967 * with it itself. *sigh* 968 */ 969 static void 970 dc_miibus_mediainit(device_t dev) 971 { 972 struct dc_softc *sc; 973 struct mii_data *mii; 974 struct ifmedia *ifm; 975 int rev; 976 977 rev = pci_get_revid(dev); 978 979 sc = device_get_softc(dev); 980 mii = device_get_softc(sc->dc_miibus); 981 ifm = &mii->mii_media; 982 983 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 984 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 985 986 return; 987 } 988 989 #define DC_BITS_512 9 990 #define DC_BITS_128 7 991 #define DC_BITS_64 6 992 993 static u_int32_t 994 dc_crc_mask(struct dc_softc *sc) 995 { 996 /* 997 * The hash table on the PNIC II and the MX98715AEC-C/D/E 998 * chips is only 128 bits wide. 999 */ 1000 if (sc->dc_flags & DC_128BIT_HASH) 1001 return ((1 << DC_BITS_128) - 1); 1002 1003 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1004 if (sc->dc_flags & DC_64BIT_HASH) 1005 return ((1 << DC_BITS_64) - 1); 1006 1007 return ((1 << DC_BITS_512) - 1); 1008 } 1009 1010 /* 1011 * 21143-style RX filter setup routine. Filter programming is done by 1012 * downloading a special setup frame into the TX engine. 21143, Macronix, 1013 * PNIC, PNIC II and Davicom chips are programmed this way. 1014 * 1015 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1016 * address (our node address) and a 512-bit hash filter for multicast 1017 * frames. We also sneak the broadcast address into the hash filter since 1018 * we need that too. 1019 */ 1020 void 1021 dc_setfilt_21143(struct dc_softc *sc) 1022 { 1023 struct dc_desc *sframe; 1024 u_int32_t h, crc_mask, *sp; 1025 struct ifmultiaddr *ifma; 1026 struct ifnet *ifp; 1027 int i; 1028 1029 ifp = &sc->arpcom.ac_if; 1030 1031 i = sc->dc_cdata.dc_tx_prod; 1032 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1033 sc->dc_cdata.dc_tx_cnt++; 1034 sframe = &sc->dc_ldata->dc_tx_list[i]; 1035 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1036 bzero((char *)sp, DC_SFRAME_LEN); 1037 1038 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1039 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1040 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1041 1042 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1043 1044 /* If we want promiscuous mode, set the allframes bit. */ 1045 if (ifp->if_flags & IFF_PROMISC) 1046 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1047 else 1048 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1049 1050 if (ifp->if_flags & IFF_ALLMULTI) 1051 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1052 else 1053 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1054 1055 crc_mask = dc_crc_mask(sc); 1056 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1057 if (ifma->ifma_addr->sa_family != AF_LINK) 1058 continue; 1059 h = ether_crc32_le( 1060 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1061 ETHER_ADDR_LEN) & crc_mask; 1062 sp[h >> 4] |= 1 << (h & 0xF); 1063 } 1064 1065 if (ifp->if_flags & IFF_BROADCAST) { 1066 h = ether_crc32_le(ifp->if_broadcastaddr, 1067 ETHER_ADDR_LEN) & crc_mask; 1068 sp[h >> 4] |= 1 << (h & 0xF); 1069 } 1070 1071 /* Set our MAC address */ 1072 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1073 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1074 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1075 1076 sframe->dc_status = DC_TXSTAT_OWN; 1077 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1078 1079 /* 1080 * The PNIC takes an exceedingly long time to process its 1081 * setup frame; wait 10ms after posting the setup frame 1082 * before proceeding, just so it has time to swallow its 1083 * medicine. 1084 */ 1085 DELAY(10000); 1086 1087 ifp->if_timer = 5; 1088 1089 return; 1090 } 1091 1092 void 1093 dc_setfilt_admtek(struct dc_softc *sc) 1094 { 1095 struct ifnet *ifp; 1096 int h = 0; 1097 u_int32_t crc_mask; 1098 u_int32_t hashes[2] = { 0, 0 }; 1099 struct ifmultiaddr *ifma; 1100 1101 ifp = &sc->arpcom.ac_if; 1102 1103 /* Init our MAC address */ 1104 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1105 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1106 1107 /* If we want promiscuous mode, set the allframes bit. */ 1108 if (ifp->if_flags & IFF_PROMISC) 1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1110 else 1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1112 1113 if (ifp->if_flags & IFF_ALLMULTI) 1114 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1115 else 1116 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1117 1118 /* first, zot all the existing hash bits */ 1119 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1120 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1121 1122 /* 1123 * If we're already in promisc or allmulti mode, we 1124 * don't have to bother programming the multicast filter. 1125 */ 1126 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1127 return; 1128 1129 /* now program new ones */ 1130 if (DC_IS_CENTAUR(sc)) 1131 crc_mask = dc_crc_mask(sc); 1132 else 1133 crc_mask = 0x3f; 1134 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1135 if (ifma->ifma_addr->sa_family != AF_LINK) 1136 continue; 1137 if (DC_IS_CENTAUR(sc)) { 1138 h = ether_crc32_le( 1139 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1140 ETHER_ADDR_LEN) & crc_mask; 1141 } else { 1142 h = ether_crc32_be( 1143 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1144 ETHER_ADDR_LEN); 1145 h = (h >> 26) & crc_mask; 1146 } 1147 if (h < 32) 1148 hashes[0] |= (1 << h); 1149 else 1150 hashes[1] |= (1 << (h - 32)); 1151 } 1152 1153 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1154 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1155 1156 return; 1157 } 1158 1159 void 1160 dc_setfilt_asix(struct dc_softc *sc) 1161 { 1162 struct ifnet *ifp; 1163 int h = 0; 1164 u_int32_t hashes[2] = { 0, 0 }; 1165 struct ifmultiaddr *ifma; 1166 1167 ifp = &sc->arpcom.ac_if; 1168 1169 /* Init our MAC address */ 1170 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1171 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1172 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1173 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1174 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1175 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1176 1177 /* If we want promiscuous mode, set the allframes bit. */ 1178 if (ifp->if_flags & IFF_PROMISC) 1179 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1180 else 1181 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1182 1183 if (ifp->if_flags & IFF_ALLMULTI) 1184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1185 else 1186 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1187 1188 /* 1189 * The ASIX chip has a special bit to enable reception 1190 * of broadcast frames. 1191 */ 1192 if (ifp->if_flags & IFF_BROADCAST) 1193 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1194 else 1195 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1196 1197 /* first, zot all the existing hash bits */ 1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1199 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1200 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1201 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1202 1203 /* 1204 * If we're already in promisc or allmulti mode, we 1205 * don't have to bother programming the multicast filter. 1206 */ 1207 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1208 return; 1209 1210 /* now program new ones */ 1211 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1212 if (ifma->ifma_addr->sa_family != AF_LINK) 1213 continue; 1214 h = ether_crc32_be( 1215 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1216 ETHER_ADDR_LEN); 1217 h = (h >> 26) & 0x3f; 1218 if (h < 32) 1219 hashes[0] |= (1 << h); 1220 else 1221 hashes[1] |= (1 << (h - 32)); 1222 } 1223 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1228 1229 return; 1230 } 1231 1232 static void 1233 dc_setfilt(struct dc_softc *sc) 1234 { 1235 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1236 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1237 dc_setfilt_21143(sc); 1238 1239 if (DC_IS_ASIX(sc)) 1240 dc_setfilt_asix(sc); 1241 1242 if (DC_IS_ADMTEK(sc)) 1243 dc_setfilt_admtek(sc); 1244 1245 return; 1246 } 1247 1248 /* 1249 * In order to fiddle with the 1250 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1251 * first have to put the transmit and/or receive logic in the idle state. 1252 */ 1253 static void 1254 dc_setcfg(struct dc_softc *sc, int media) 1255 { 1256 int i, restart = 0; 1257 u_int32_t isr; 1258 1259 if (IFM_SUBTYPE(media) == IFM_NONE) 1260 return; 1261 1262 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1263 restart = 1; 1264 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1265 1266 for (i = 0; i < DC_TIMEOUT; i++) { 1267 isr = CSR_READ_4(sc, DC_ISR); 1268 if ((isr & DC_ISR_TX_IDLE) && 1269 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1270 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1271 break; 1272 DELAY(10); 1273 } 1274 1275 if (i == DC_TIMEOUT) { 1276 if_printf(&sc->arpcom.ac_if, 1277 "failed to force tx and rx to idle state\n"); 1278 } 1279 } 1280 1281 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1282 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1284 if (sc->dc_pmode == DC_PMODE_MII) { 1285 int watchdogreg; 1286 1287 if (DC_IS_INTEL(sc)) { 1288 /* there's a write enable bit here that reads as 1 */ 1289 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1290 watchdogreg &= ~DC_WDOG_CTLWREN; 1291 watchdogreg |= DC_WDOG_JABBERDIS; 1292 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1293 } else { 1294 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1295 } 1296 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1297 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1298 if (sc->dc_type == DC_TYPE_98713) 1299 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1300 DC_NETCFG_SCRAMBLER)); 1301 if (!DC_IS_DAVICOM(sc)) 1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1303 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1304 if (DC_IS_INTEL(sc)) 1305 dc_apply_fixup(sc, IFM_AUTO); 1306 } else { 1307 if (DC_IS_PNIC(sc)) { 1308 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1309 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1310 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1311 } 1312 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1315 if (DC_IS_INTEL(sc)) 1316 dc_apply_fixup(sc, 1317 (media & IFM_GMASK) == IFM_FDX ? 1318 IFM_100_TX|IFM_FDX : IFM_100_TX); 1319 } 1320 } 1321 1322 if (IFM_SUBTYPE(media) == IFM_10_T) { 1323 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1324 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1325 if (sc->dc_pmode == DC_PMODE_MII) { 1326 int watchdogreg; 1327 1328 /* there's a write enable bit here that reads as 1 */ 1329 if (DC_IS_INTEL(sc)) { 1330 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1331 watchdogreg &= ~DC_WDOG_CTLWREN; 1332 watchdogreg |= DC_WDOG_JABBERDIS; 1333 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1334 } else { 1335 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1336 } 1337 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1338 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1339 if (sc->dc_type == DC_TYPE_98713) 1340 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1341 if (!DC_IS_DAVICOM(sc)) 1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1343 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1344 if (DC_IS_INTEL(sc)) 1345 dc_apply_fixup(sc, IFM_AUTO); 1346 } else { 1347 if (DC_IS_PNIC(sc)) { 1348 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1349 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1350 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1351 } 1352 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1353 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1354 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1355 if (DC_IS_INTEL(sc)) { 1356 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1357 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1358 if ((media & IFM_GMASK) == IFM_FDX) 1359 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1360 else 1361 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1362 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1363 DC_CLRBIT(sc, DC_10BTCTRL, 1364 DC_TCTL_AUTONEGENBL); 1365 dc_apply_fixup(sc, 1366 (media & IFM_GMASK) == IFM_FDX ? 1367 IFM_10_T|IFM_FDX : IFM_10_T); 1368 DELAY(20000); 1369 } 1370 } 1371 } 1372 1373 /* 1374 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1375 * PHY and we want HomePNA mode, set the portsel bit to turn 1376 * on the external MII port. 1377 */ 1378 if (DC_IS_DAVICOM(sc)) { 1379 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1381 sc->dc_link = 1; 1382 } else { 1383 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1384 } 1385 } 1386 1387 if ((media & IFM_GMASK) == IFM_FDX) { 1388 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1389 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1390 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1391 } else { 1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1393 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1394 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1395 } 1396 1397 if (restart) 1398 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1399 1400 return; 1401 } 1402 1403 static void 1404 dc_reset(struct dc_softc *sc) 1405 { 1406 int i; 1407 1408 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1409 1410 for (i = 0; i < DC_TIMEOUT; i++) { 1411 DELAY(10); 1412 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1413 break; 1414 } 1415 1416 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1417 DELAY(10000); 1418 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1419 i = 0; 1420 } 1421 1422 if (i == DC_TIMEOUT) 1423 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 1424 1425 /* Wait a little while for the chip to get its brains in order. */ 1426 DELAY(1000); 1427 1428 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1429 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1430 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1431 1432 /* 1433 * Bring the SIA out of reset. In some cases, it looks 1434 * like failing to unreset the SIA soon enough gets it 1435 * into a state where it will never come out of reset 1436 * until we reset the whole chip again. 1437 */ 1438 if (DC_IS_INTEL(sc)) { 1439 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1440 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1441 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1442 } 1443 1444 return; 1445 } 1446 1447 static const struct dc_type * 1448 dc_devtype(device_t dev) 1449 { 1450 const struct dc_type *t; 1451 u_int32_t rev; 1452 1453 t = dc_devs; 1454 1455 while(t->dc_name != NULL) { 1456 if ((pci_get_vendor(dev) == t->dc_vid) && 1457 (pci_get_device(dev) == t->dc_did)) { 1458 /* Check the PCI revision */ 1459 rev = pci_get_revid(dev); 1460 if (t->dc_did == DC_DEVICEID_98713 && 1461 rev >= DC_REVISION_98713A) 1462 t++; 1463 if (t->dc_did == DC_DEVICEID_98713_CP && 1464 rev >= DC_REVISION_98713A) 1465 t++; 1466 if (t->dc_did == DC_DEVICEID_987x5 && 1467 rev >= DC_REVISION_98715AEC_C) 1468 t++; 1469 if (t->dc_did == DC_DEVICEID_987x5 && 1470 rev >= DC_REVISION_98725) 1471 t++; 1472 if (t->dc_did == DC_DEVICEID_AX88140A && 1473 rev >= DC_REVISION_88141) 1474 t++; 1475 if (t->dc_did == DC_DEVICEID_82C168 && 1476 rev >= DC_REVISION_82C169) 1477 t++; 1478 if (t->dc_did == DC_DEVICEID_DM9102 && 1479 rev >= DC_REVISION_DM9102A) 1480 t++; 1481 return(t); 1482 } 1483 t++; 1484 } 1485 1486 return(NULL); 1487 } 1488 1489 /* 1490 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1491 * IDs against our list and return a device name if we find a match. 1492 * We do a little bit of extra work to identify the exact type of 1493 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1494 * but different revision IDs. The same is true for 98715/98715A 1495 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1496 * cases, the exact chip revision affects driver behavior. 1497 */ 1498 static int 1499 dc_probe(device_t dev) 1500 { 1501 const struct dc_type *t; 1502 1503 t = dc_devtype(dev); 1504 if (t != NULL) { 1505 struct dc_softc *sc = device_get_softc(dev); 1506 1507 /* Need this info to decide on a chip type. */ 1508 sc->dc_info = t; 1509 device_set_desc(dev, t->dc_name); 1510 return(0); 1511 } 1512 1513 return(ENXIO); 1514 } 1515 1516 static void 1517 dc_acpi(device_t dev) 1518 { 1519 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1520 uint32_t iobase, membase, irq; 1521 struct dc_softc *sc; 1522 1523 /* Save important PCI config data. */ 1524 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1525 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1526 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1527 1528 sc = device_get_softc(dev); 1529 /* Reset the power state. */ 1530 if_printf(&sc->arpcom.ac_if, 1531 "chip is in D%d power mode " 1532 "-- setting to D0\n", pci_get_powerstate(dev)); 1533 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1534 1535 /* Restore PCI config data. */ 1536 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1537 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1538 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1539 } 1540 } 1541 1542 static void 1543 dc_apply_fixup(struct dc_softc *sc, int media) 1544 { 1545 struct dc_mediainfo *m; 1546 u_int8_t *p; 1547 int i; 1548 u_int32_t reg; 1549 1550 m = sc->dc_mi; 1551 1552 while (m != NULL) { 1553 if (m->dc_media == media) 1554 break; 1555 m = m->dc_next; 1556 } 1557 1558 if (m == NULL) 1559 return; 1560 1561 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1562 reg = (p[0] | (p[1] << 8)) << 16; 1563 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1564 } 1565 1566 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1567 reg = (p[0] | (p[1] << 8)) << 16; 1568 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1569 } 1570 1571 return; 1572 } 1573 1574 static void 1575 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1576 { 1577 struct dc_mediainfo *m; 1578 1579 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1580 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){ 1581 case DC_SIA_CODE_10BT: 1582 m->dc_media = IFM_10_T; 1583 break; 1584 1585 case DC_SIA_CODE_10BT_FDX: 1586 m->dc_media = IFM_10_T|IFM_FDX; 1587 break; 1588 1589 case DC_SIA_CODE_10B2: 1590 m->dc_media = IFM_10_2; 1591 break; 1592 1593 case DC_SIA_CODE_10B5: 1594 m->dc_media = IFM_10_5; 1595 break; 1596 } 1597 if (l->dc_sia_code & DC_SIA_CODE_EXT){ 1598 m->dc_gp_len = 2; 1599 m->dc_gp_ptr = 1600 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1601 } else { 1602 m->dc_gp_len = 2; 1603 m->dc_gp_ptr = 1604 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1605 } 1606 1607 m->dc_next = sc->dc_mi; 1608 sc->dc_mi = m; 1609 1610 sc->dc_pmode = DC_PMODE_SIA; 1611 1612 return; 1613 } 1614 1615 static void 1616 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1617 { 1618 struct dc_mediainfo *m; 1619 1620 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1621 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1622 m->dc_media = IFM_100_TX; 1623 1624 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1625 m->dc_media = IFM_100_TX|IFM_FDX; 1626 1627 m->dc_gp_len = 2; 1628 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1629 1630 m->dc_next = sc->dc_mi; 1631 sc->dc_mi = m; 1632 1633 sc->dc_pmode = DC_PMODE_SYM; 1634 1635 return; 1636 } 1637 1638 static void 1639 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1640 { 1641 u_int8_t *p; 1642 struct dc_mediainfo *m; 1643 1644 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1645 /* We abuse IFM_AUTO to represent MII. */ 1646 m->dc_media = IFM_AUTO; 1647 m->dc_gp_len = l->dc_gpr_len; 1648 1649 p = (u_int8_t *)l; 1650 p += sizeof(struct dc_eblock_mii); 1651 m->dc_gp_ptr = p; 1652 p += 2 * l->dc_gpr_len; 1653 m->dc_reset_len = *p; 1654 p++; 1655 m->dc_reset_ptr = p; 1656 1657 m->dc_next = sc->dc_mi; 1658 sc->dc_mi = m; 1659 1660 return; 1661 } 1662 1663 static void 1664 dc_read_srom(struct dc_softc *sc, int bits) 1665 { 1666 int size; 1667 1668 size = 2 << bits; 1669 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT); 1670 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1671 } 1672 1673 static void 1674 dc_parse_21143_srom(struct dc_softc *sc) 1675 { 1676 struct dc_leaf_hdr *lhdr; 1677 struct dc_eblock_hdr *hdr; 1678 int i, loff; 1679 char *ptr; 1680 int have_mii; 1681 1682 have_mii = 0; 1683 loff = sc->dc_srom[27]; 1684 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1685 1686 ptr = (char *)lhdr; 1687 ptr += sizeof(struct dc_leaf_hdr) - 1; 1688 /* 1689 * Look if we got a MII media block. 1690 */ 1691 for (i = 0; i < lhdr->dc_mcnt; i++) { 1692 hdr = (struct dc_eblock_hdr *)ptr; 1693 if (hdr->dc_type == DC_EBLOCK_MII) 1694 have_mii++; 1695 1696 ptr += (hdr->dc_len & 0x7F); 1697 ptr++; 1698 } 1699 1700 /* 1701 * Do the same thing again. Only use SIA and SYM media 1702 * blocks if no MII media block is available. 1703 */ 1704 ptr = (char *)lhdr; 1705 ptr += sizeof(struct dc_leaf_hdr) - 1; 1706 for (i = 0; i < lhdr->dc_mcnt; i++) { 1707 hdr = (struct dc_eblock_hdr *)ptr; 1708 switch(hdr->dc_type) { 1709 case DC_EBLOCK_MII: 1710 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1711 break; 1712 case DC_EBLOCK_SIA: 1713 if (! have_mii) 1714 dc_decode_leaf_sia(sc, 1715 (struct dc_eblock_sia *)hdr); 1716 break; 1717 case DC_EBLOCK_SYM: 1718 if (! have_mii) 1719 dc_decode_leaf_sym(sc, 1720 (struct dc_eblock_sym *)hdr); 1721 break; 1722 default: 1723 /* Don't care. Yet. */ 1724 break; 1725 } 1726 ptr += (hdr->dc_len & 0x7F); 1727 ptr++; 1728 } 1729 1730 return; 1731 } 1732 1733 /* 1734 * Attach the interface. Allocate softc structures, do ifmedia 1735 * setup and ethernet/BPF attach. 1736 */ 1737 static int 1738 dc_attach(device_t dev) 1739 { 1740 int tmp = 0; 1741 u_char eaddr[ETHER_ADDR_LEN]; 1742 u_int32_t command; 1743 struct dc_softc *sc; 1744 struct ifnet *ifp; 1745 u_int32_t revision; 1746 int error = 0, rid, mac_offset; 1747 1748 sc = device_get_softc(dev); 1749 callout_init(&sc->dc_stat_timer); 1750 1751 ifp = &sc->arpcom.ac_if; 1752 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1753 1754 /* 1755 * Handle power management nonsense. 1756 */ 1757 dc_acpi(dev); 1758 1759 /* 1760 * Map control/status registers. 1761 */ 1762 pci_enable_busmaster(dev); 1763 1764 rid = DC_RID; 1765 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1766 1767 if (sc->dc_res == NULL) { 1768 device_printf(dev, "couldn't map ports/memory\n"); 1769 error = ENXIO; 1770 goto fail; 1771 } 1772 1773 sc->dc_btag = rman_get_bustag(sc->dc_res); 1774 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1775 1776 /* Allocate interrupt */ 1777 rid = 0; 1778 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1779 RF_SHAREABLE | RF_ACTIVE); 1780 1781 if (sc->dc_irq == NULL) { 1782 device_printf(dev, "couldn't map interrupt\n"); 1783 error = ENXIO; 1784 goto fail; 1785 } 1786 1787 revision = pci_get_revid(dev); 1788 1789 /* Get the eeprom width, but PNIC has diff eeprom */ 1790 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1791 dc_eeprom_width(sc); 1792 1793 switch(sc->dc_info->dc_did) { 1794 case DC_DEVICEID_21143: 1795 sc->dc_type = DC_TYPE_21143; 1796 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1797 sc->dc_flags |= DC_REDUCED_MII_POLL; 1798 /* Save EEPROM contents so we can parse them later. */ 1799 dc_read_srom(sc, sc->dc_romwidth); 1800 break; 1801 case DC_DEVICEID_DM9009: 1802 case DC_DEVICEID_DM9100: 1803 case DC_DEVICEID_DM9102: 1804 sc->dc_type = DC_TYPE_DM9102; 1805 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1806 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1807 sc->dc_flags |= DC_TX_ALIGN; 1808 sc->dc_pmode = DC_PMODE_MII; 1809 /* Increase the latency timer value. */ 1810 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1811 command &= 0xFFFF00FF; 1812 command |= 0x00008000; 1813 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1814 break; 1815 case DC_DEVICEID_AL981: 1816 sc->dc_type = DC_TYPE_AL981; 1817 sc->dc_flags |= DC_TX_USE_TX_INTR; 1818 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1819 sc->dc_pmode = DC_PMODE_MII; 1820 dc_read_srom(sc, sc->dc_romwidth); 1821 break; 1822 case DC_DEVICEID_AN985: 1823 case DC_DEVICEID_ADM9511: 1824 case DC_DEVICEID_ADM9513: 1825 case DC_DEVICEID_EN2242: 1826 case DC_DEVICEID_3CSOHOB: 1827 sc->dc_type = DC_TYPE_AN985; 1828 sc->dc_flags |= DC_64BIT_HASH; 1829 sc->dc_flags |= DC_TX_USE_TX_INTR; 1830 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1831 sc->dc_pmode = DC_PMODE_MII; 1832 break; 1833 case DC_DEVICEID_98713: 1834 case DC_DEVICEID_98713_CP: 1835 if (revision < DC_REVISION_98713A) { 1836 sc->dc_type = DC_TYPE_98713; 1837 } 1838 if (revision >= DC_REVISION_98713A) { 1839 sc->dc_type = DC_TYPE_98713A; 1840 sc->dc_flags |= DC_21143_NWAY; 1841 } 1842 sc->dc_flags |= DC_REDUCED_MII_POLL; 1843 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1844 break; 1845 case DC_DEVICEID_987x5: 1846 case DC_DEVICEID_EN1217: 1847 /* 1848 * Macronix MX98715AEC-C/D/E parts have only a 1849 * 128-bit hash table. We need to deal with these 1850 * in the same manner as the PNIC II so that we 1851 * get the right number of bits out of the 1852 * CRC routine. 1853 */ 1854 if (revision >= DC_REVISION_98715AEC_C && 1855 revision < DC_REVISION_98725) 1856 sc->dc_flags |= DC_128BIT_HASH; 1857 sc->dc_type = DC_TYPE_987x5; 1858 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1859 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1860 break; 1861 case DC_DEVICEID_98727: 1862 sc->dc_type = DC_TYPE_987x5; 1863 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1864 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1865 break; 1866 case DC_DEVICEID_82C115: 1867 sc->dc_type = DC_TYPE_PNICII; 1868 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1869 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1870 break; 1871 case DC_DEVICEID_82C168: 1872 sc->dc_type = DC_TYPE_PNIC; 1873 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1874 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1875 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1876 if (revision < DC_REVISION_82C169) 1877 sc->dc_pmode = DC_PMODE_SYM; 1878 break; 1879 case DC_DEVICEID_AX88140A: 1880 sc->dc_type = DC_TYPE_ASIX; 1881 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1882 sc->dc_flags |= DC_REDUCED_MII_POLL; 1883 sc->dc_pmode = DC_PMODE_MII; 1884 break; 1885 case DC_DEVICEID_RS7112: 1886 sc->dc_type = DC_TYPE_CONEXANT; 1887 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1888 sc->dc_flags |= DC_REDUCED_MII_POLL; 1889 sc->dc_pmode = DC_PMODE_MII; 1890 dc_read_srom(sc, sc->dc_romwidth); 1891 break; 1892 default: 1893 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 1894 break; 1895 } 1896 1897 /* Save the cache line size. */ 1898 if (DC_IS_DAVICOM(sc)) 1899 sc->dc_cachesize = 0; 1900 else 1901 sc->dc_cachesize = pci_read_config(dev, 1902 DC_PCI_CFLT, 4) & 0xFF; 1903 1904 /* Reset the adapter. */ 1905 dc_reset(sc); 1906 1907 /* Take 21143 out of snooze mode */ 1908 if (DC_IS_INTEL(sc)) { 1909 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1910 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1911 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1912 } 1913 1914 /* 1915 * Try to learn something about the supported media. 1916 * We know that ASIX and ADMtek and Davicom devices 1917 * will *always* be using MII media, so that's a no-brainer. 1918 * The tricky ones are the Macronix/PNIC II and the 1919 * Intel 21143. 1920 */ 1921 if (DC_IS_INTEL(sc)) 1922 dc_parse_21143_srom(sc); 1923 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1924 if (sc->dc_type == DC_TYPE_98713) 1925 sc->dc_pmode = DC_PMODE_MII; 1926 else 1927 sc->dc_pmode = DC_PMODE_SYM; 1928 } else if (!sc->dc_pmode) 1929 sc->dc_pmode = DC_PMODE_MII; 1930 1931 /* 1932 * Get station address from the EEPROM. 1933 */ 1934 switch(sc->dc_type) { 1935 case DC_TYPE_98713: 1936 case DC_TYPE_98713A: 1937 case DC_TYPE_987x5: 1938 case DC_TYPE_PNICII: 1939 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1940 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1941 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1942 break; 1943 case DC_TYPE_PNIC: 1944 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1945 break; 1946 case DC_TYPE_DM9102: 1947 case DC_TYPE_21143: 1948 case DC_TYPE_ASIX: 1949 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1950 break; 1951 case DC_TYPE_AL981: 1952 case DC_TYPE_AN985: 1953 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0); 1954 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1); 1955 break; 1956 case DC_TYPE_CONEXANT: 1957 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 1958 break; 1959 default: 1960 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1961 break; 1962 } 1963 1964 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1965 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1966 1967 if (sc->dc_ldata == NULL) { 1968 device_printf(dev, "no memory for list buffers!\n"); 1969 error = ENXIO; 1970 goto fail; 1971 } 1972 1973 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1974 1975 ifp->if_softc = sc; 1976 ifp->if_mtu = ETHERMTU; 1977 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1978 ifp->if_ioctl = dc_ioctl; 1979 ifp->if_start = dc_start; 1980 #ifdef DEVICE_POLLING 1981 ifp->if_poll = dc_poll; 1982 #endif 1983 ifp->if_watchdog = dc_watchdog; 1984 ifp->if_init = dc_init; 1985 ifp->if_baudrate = 10000000; 1986 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); 1987 ifq_set_ready(&ifp->if_snd); 1988 1989 /* 1990 * Do MII setup. If this is a 21143, check for a PHY on the 1991 * MII bus after applying any necessary fixups to twiddle the 1992 * GPIO bits. If we don't end up finding a PHY, restore the 1993 * old selection (SIA only or SIA/SYM) and attach the dcphy 1994 * driver instead. 1995 */ 1996 if (DC_IS_INTEL(sc)) { 1997 dc_apply_fixup(sc, IFM_AUTO); 1998 tmp = sc->dc_pmode; 1999 sc->dc_pmode = DC_PMODE_MII; 2000 } 2001 2002 error = mii_phy_probe(dev, &sc->dc_miibus, 2003 dc_ifmedia_upd, dc_ifmedia_sts); 2004 2005 if (error && DC_IS_INTEL(sc)) { 2006 sc->dc_pmode = tmp; 2007 if (sc->dc_pmode != DC_PMODE_SIA) 2008 sc->dc_pmode = DC_PMODE_SYM; 2009 sc->dc_flags |= DC_21143_NWAY; 2010 mii_phy_probe(dev, &sc->dc_miibus, 2011 dc_ifmedia_upd, dc_ifmedia_sts); 2012 /* 2013 * For non-MII cards, we need to have the 21143 2014 * drive the LEDs. Except there are some systems 2015 * like the NEC VersaPro NoteBook PC which have no 2016 * LEDs, and twiddling these bits has adverse effects 2017 * on them. (I.e. you suddenly can't get a link.) 2018 */ 2019 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2020 sc->dc_flags |= DC_TULIP_LEDS; 2021 error = 0; 2022 } 2023 2024 if (error) { 2025 device_printf(dev, "MII without any PHY!\n"); 2026 error = ENXIO; 2027 goto fail; 2028 } 2029 2030 /* 2031 * Call MI attach routine. 2032 */ 2033 ether_ifattach(ifp, eaddr); 2034 2035 if (DC_IS_ADMTEK(sc)) { 2036 /* 2037 * Set automatic TX underrun recovery for the ADMtek chips 2038 */ 2039 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2040 } 2041 2042 /* 2043 * Tell the upper layer(s) we support long frames. 2044 */ 2045 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2046 2047 error = bus_setup_intr(dev, sc->dc_irq, 0, 2048 dc_intr, sc, &sc->dc_intrhand, NULL); 2049 if (error) { 2050 ether_ifdetach(ifp); 2051 device_printf(dev, "couldn't set up irq\n"); 2052 goto fail; 2053 } 2054 2055 return(0); 2056 2057 fail: 2058 dc_detach(dev); 2059 return(error); 2060 } 2061 2062 static int 2063 dc_detach(device_t dev) 2064 { 2065 struct dc_softc *sc = device_get_softc(dev); 2066 struct ifnet *ifp = &sc->arpcom.ac_if; 2067 struct dc_mediainfo *m; 2068 2069 crit_enter(); 2070 2071 if (device_is_attached(dev)) { 2072 dc_stop(sc); 2073 ether_ifdetach(ifp); 2074 } 2075 2076 if (sc->dc_miibus) 2077 device_delete_child(dev, sc->dc_miibus); 2078 bus_generic_detach(dev); 2079 2080 if (sc->dc_intrhand) 2081 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2082 2083 crit_exit(); 2084 2085 if (sc->dc_irq) 2086 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2087 if (sc->dc_res) 2088 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2089 2090 if (sc->dc_ldata) 2091 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2092 if (sc->dc_pnic_rx_buf != NULL) 2093 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2094 2095 while(sc->dc_mi != NULL) { 2096 m = sc->dc_mi->dc_next; 2097 free(sc->dc_mi, M_DEVBUF); 2098 sc->dc_mi = m; 2099 } 2100 2101 if (sc->dc_srom) 2102 free(sc->dc_srom, M_DEVBUF); 2103 2104 return(0); 2105 } 2106 2107 /* 2108 * Initialize the transmit descriptors. 2109 */ 2110 static int 2111 dc_list_tx_init(struct dc_softc *sc) 2112 { 2113 struct dc_chain_data *cd; 2114 struct dc_list_data *ld; 2115 int i; 2116 2117 cd = &sc->dc_cdata; 2118 ld = sc->dc_ldata; 2119 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2120 if (i == (DC_TX_LIST_CNT - 1)) { 2121 ld->dc_tx_list[i].dc_next = 2122 vtophys(&ld->dc_tx_list[0]); 2123 } else { 2124 ld->dc_tx_list[i].dc_next = 2125 vtophys(&ld->dc_tx_list[i + 1]); 2126 } 2127 cd->dc_tx_chain[i] = NULL; 2128 ld->dc_tx_list[i].dc_data = 0; 2129 ld->dc_tx_list[i].dc_ctl = 0; 2130 } 2131 2132 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2133 2134 return(0); 2135 } 2136 2137 2138 /* 2139 * Initialize the RX descriptors and allocate mbufs for them. Note that 2140 * we arrange the descriptors in a closed ring, so that the last descriptor 2141 * points back to the first. 2142 */ 2143 static int 2144 dc_list_rx_init(struct dc_softc *sc) 2145 { 2146 struct dc_chain_data *cd; 2147 struct dc_list_data *ld; 2148 int i; 2149 2150 cd = &sc->dc_cdata; 2151 ld = sc->dc_ldata; 2152 2153 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2154 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2155 return(ENOBUFS); 2156 if (i == (DC_RX_LIST_CNT - 1)) { 2157 ld->dc_rx_list[i].dc_next = 2158 vtophys(&ld->dc_rx_list[0]); 2159 } else { 2160 ld->dc_rx_list[i].dc_next = 2161 vtophys(&ld->dc_rx_list[i + 1]); 2162 } 2163 } 2164 2165 cd->dc_rx_prod = 0; 2166 2167 return(0); 2168 } 2169 2170 /* 2171 * Initialize an RX descriptor and attach an MBUF cluster. 2172 */ 2173 static int 2174 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) 2175 { 2176 struct mbuf *m_new = NULL; 2177 struct dc_desc *c; 2178 2179 c = &sc->dc_ldata->dc_rx_list[i]; 2180 2181 if (m == NULL) { 2182 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2183 if (m_new == NULL) 2184 return (ENOBUFS); 2185 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2186 } else { 2187 m_new = m; 2188 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2189 m_new->m_data = m_new->m_ext.ext_buf; 2190 } 2191 2192 m_adj(m_new, sizeof(u_int64_t)); 2193 2194 /* 2195 * If this is a PNIC chip, zero the buffer. This is part 2196 * of the workaround for the receive bug in the 82c168 and 2197 * 82c169 chips. 2198 */ 2199 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2200 bzero((char *)mtod(m_new, char *), m_new->m_len); 2201 2202 sc->dc_cdata.dc_rx_chain[i] = m_new; 2203 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2204 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2205 c->dc_status = DC_RXSTAT_OWN; 2206 2207 return(0); 2208 } 2209 2210 /* 2211 * Grrrrr. 2212 * The PNIC chip has a terrible bug in it that manifests itself during 2213 * periods of heavy activity. The exact mode of failure if difficult to 2214 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2215 * will happen on slow machines. The bug is that sometimes instead of 2216 * uploading one complete frame during reception, it uploads what looks 2217 * like the entire contents of its FIFO memory. The frame we want is at 2218 * the end of the whole mess, but we never know exactly how much data has 2219 * been uploaded, so salvaging the frame is hard. 2220 * 2221 * There is only one way to do it reliably, and it's disgusting. 2222 * Here's what we know: 2223 * 2224 * - We know there will always be somewhere between one and three extra 2225 * descriptors uploaded. 2226 * 2227 * - We know the desired received frame will always be at the end of the 2228 * total data upload. 2229 * 2230 * - We know the size of the desired received frame because it will be 2231 * provided in the length field of the status word in the last descriptor. 2232 * 2233 * Here's what we do: 2234 * 2235 * - When we allocate buffers for the receive ring, we bzero() them. 2236 * This means that we know that the buffer contents should be all 2237 * zeros, except for data uploaded by the chip. 2238 * 2239 * - We also force the PNIC chip to upload frames that include the 2240 * ethernet CRC at the end. 2241 * 2242 * - We gather all of the bogus frame data into a single buffer. 2243 * 2244 * - We then position a pointer at the end of this buffer and scan 2245 * backwards until we encounter the first non-zero byte of data. 2246 * This is the end of the received frame. We know we will encounter 2247 * some data at the end of the frame because the CRC will always be 2248 * there, so even if the sender transmits a packet of all zeros, 2249 * we won't be fooled. 2250 * 2251 * - We know the size of the actual received frame, so we subtract 2252 * that value from the current pointer location. This brings us 2253 * to the start of the actual received packet. 2254 * 2255 * - We copy this into an mbuf and pass it on, along with the actual 2256 * frame length. 2257 * 2258 * The performance hit is tremendous, but it beats dropping frames all 2259 * the time. 2260 */ 2261 2262 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2263 static void 2264 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2265 { 2266 struct dc_desc *cur_rx; 2267 struct dc_desc *c = NULL; 2268 struct mbuf *m = NULL; 2269 unsigned char *ptr; 2270 int i, total_len; 2271 u_int32_t rxstat = 0; 2272 2273 i = sc->dc_pnic_rx_bug_save; 2274 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2275 ptr = sc->dc_pnic_rx_buf; 2276 bzero(ptr, DC_RXLEN * 5); 2277 2278 /* Copy all the bytes from the bogus buffers. */ 2279 while (1) { 2280 c = &sc->dc_ldata->dc_rx_list[i]; 2281 rxstat = c->dc_status; 2282 m = sc->dc_cdata.dc_rx_chain[i]; 2283 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2284 ptr += DC_RXLEN; 2285 /* If this is the last buffer, break out. */ 2286 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2287 break; 2288 dc_newbuf(sc, i, m); 2289 DC_INC(i, DC_RX_LIST_CNT); 2290 } 2291 2292 /* Find the length of the actual receive frame. */ 2293 total_len = DC_RXBYTES(rxstat); 2294 2295 /* Scan backwards until we hit a non-zero byte. */ 2296 while(*ptr == 0x00) 2297 ptr--; 2298 2299 /* Round off. */ 2300 if ((uintptr_t)(ptr) & 0x3) 2301 ptr -= 1; 2302 2303 /* Now find the start of the frame. */ 2304 ptr -= total_len; 2305 if (ptr < sc->dc_pnic_rx_buf) 2306 ptr = sc->dc_pnic_rx_buf; 2307 2308 /* 2309 * Now copy the salvaged frame to the last mbuf and fake up 2310 * the status word to make it look like a successful 2311 * frame reception. 2312 */ 2313 dc_newbuf(sc, i, m); 2314 bcopy(ptr, mtod(m, char *), total_len); 2315 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2316 2317 return; 2318 } 2319 2320 /* 2321 * This routine searches the RX ring for dirty descriptors in the 2322 * event that the rxeof routine falls out of sync with the chip's 2323 * current descriptor pointer. This may happen sometimes as a result 2324 * of a "no RX buffer available" condition that happens when the chip 2325 * consumes all of the RX buffers before the driver has a chance to 2326 * process the RX ring. This routine may need to be called more than 2327 * once to bring the driver back in sync with the chip, however we 2328 * should still be getting RX DONE interrupts to drive the search 2329 * for new packets in the RX ring, so we should catch up eventually. 2330 */ 2331 static int 2332 dc_rx_resync(struct dc_softc *sc) 2333 { 2334 int i, pos; 2335 struct dc_desc *cur_rx; 2336 2337 pos = sc->dc_cdata.dc_rx_prod; 2338 2339 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2340 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2341 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2342 break; 2343 DC_INC(pos, DC_RX_LIST_CNT); 2344 } 2345 2346 /* If the ring really is empty, then just return. */ 2347 if (i == DC_RX_LIST_CNT) 2348 return(0); 2349 2350 /* We've fallen behing the chip: catch it. */ 2351 sc->dc_cdata.dc_rx_prod = pos; 2352 2353 return(EAGAIN); 2354 } 2355 2356 /* 2357 * A frame has been uploaded: pass the resulting mbuf chain up to 2358 * the higher level protocols. 2359 */ 2360 static void 2361 dc_rxeof(struct dc_softc *sc) 2362 { 2363 struct mbuf *m; 2364 struct ifnet *ifp; 2365 struct dc_desc *cur_rx; 2366 int i, total_len = 0; 2367 u_int32_t rxstat; 2368 2369 ifp = &sc->arpcom.ac_if; 2370 i = sc->dc_cdata.dc_rx_prod; 2371 2372 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2373 2374 #ifdef DEVICE_POLLING 2375 if (ifp->if_flags & IFF_POLLING) { 2376 if (sc->rxcycles <= 0) 2377 break; 2378 sc->rxcycles--; 2379 } 2380 #endif /* DEVICE_POLLING */ 2381 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2382 rxstat = cur_rx->dc_status; 2383 m = sc->dc_cdata.dc_rx_chain[i]; 2384 total_len = DC_RXBYTES(rxstat); 2385 2386 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2387 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2388 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2389 sc->dc_pnic_rx_bug_save = i; 2390 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2391 DC_INC(i, DC_RX_LIST_CNT); 2392 continue; 2393 } 2394 dc_pnic_rx_bug_war(sc, i); 2395 rxstat = cur_rx->dc_status; 2396 total_len = DC_RXBYTES(rxstat); 2397 } 2398 } 2399 2400 sc->dc_cdata.dc_rx_chain[i] = NULL; 2401 2402 /* 2403 * If an error occurs, update stats, clear the 2404 * status word and leave the mbuf cluster in place: 2405 * it should simply get re-used next time this descriptor 2406 * comes up in the ring. However, don't report long 2407 * frames as errors since they could be vlans 2408 */ 2409 if ((rxstat & DC_RXSTAT_RXERR)){ 2410 if (!(rxstat & DC_RXSTAT_GIANT) || 2411 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2412 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2413 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2414 ifp->if_ierrors++; 2415 if (rxstat & DC_RXSTAT_COLLSEEN) 2416 ifp->if_collisions++; 2417 dc_newbuf(sc, i, m); 2418 if (rxstat & DC_RXSTAT_CRCERR) { 2419 DC_INC(i, DC_RX_LIST_CNT); 2420 continue; 2421 } else { 2422 dc_init(sc); 2423 return; 2424 } 2425 } 2426 } 2427 2428 /* No errors; receive the packet. */ 2429 total_len -= ETHER_CRC_LEN; 2430 2431 #ifdef __i386__ 2432 /* 2433 * On the x86 we do not have alignment problems, so try to 2434 * allocate a new buffer for the receive ring, and pass up 2435 * the one where the packet is already, saving the expensive 2436 * copy done in m_devget(). 2437 * If we are on an architecture with alignment problems, or 2438 * if the allocation fails, then use m_devget and leave the 2439 * existing buffer in the receive ring. 2440 */ 2441 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2442 m->m_pkthdr.rcvif = ifp; 2443 m->m_pkthdr.len = m->m_len = total_len; 2444 DC_INC(i, DC_RX_LIST_CNT); 2445 } else 2446 #endif 2447 { 2448 struct mbuf *m0; 2449 2450 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2451 total_len + ETHER_ALIGN, 0, ifp, NULL); 2452 dc_newbuf(sc, i, m); 2453 DC_INC(i, DC_RX_LIST_CNT); 2454 if (m0 == NULL) { 2455 ifp->if_ierrors++; 2456 continue; 2457 } 2458 m_adj(m0, ETHER_ALIGN); 2459 m = m0; 2460 } 2461 2462 ifp->if_ipackets++; 2463 (*ifp->if_input)(ifp, m); 2464 } 2465 2466 sc->dc_cdata.dc_rx_prod = i; 2467 } 2468 2469 /* 2470 * A frame was downloaded to the chip. It's safe for us to clean up 2471 * the list buffers. 2472 */ 2473 2474 static void 2475 dc_txeof(struct dc_softc *sc) 2476 { 2477 struct dc_desc *cur_tx = NULL; 2478 struct ifnet *ifp; 2479 int idx; 2480 2481 ifp = &sc->arpcom.ac_if; 2482 2483 /* 2484 * Go through our tx list and free mbufs for those 2485 * frames that have been transmitted. 2486 */ 2487 idx = sc->dc_cdata.dc_tx_cons; 2488 while(idx != sc->dc_cdata.dc_tx_prod) { 2489 u_int32_t txstat; 2490 2491 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2492 txstat = cur_tx->dc_status; 2493 2494 if (txstat & DC_TXSTAT_OWN) 2495 break; 2496 2497 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2498 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2499 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2500 /* 2501 * Yes, the PNIC is so brain damaged 2502 * that it will sometimes generate a TX 2503 * underrun error while DMAing the RX 2504 * filter setup frame. If we detect this, 2505 * we have to send the setup frame again, 2506 * or else the filter won't be programmed 2507 * correctly. 2508 */ 2509 if (DC_IS_PNIC(sc)) { 2510 if (txstat & DC_TXSTAT_ERRSUM) 2511 dc_setfilt(sc); 2512 } 2513 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2514 } 2515 sc->dc_cdata.dc_tx_cnt--; 2516 DC_INC(idx, DC_TX_LIST_CNT); 2517 continue; 2518 } 2519 2520 if (DC_IS_CONEXANT(sc)) { 2521 /* 2522 * For some reason Conexant chips like 2523 * setting the CARRLOST flag even when 2524 * the carrier is there. In CURRENT we 2525 * have the same problem for Xircom 2526 * cards ! 2527 */ 2528 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2529 sc->dc_pmode == DC_PMODE_MII && 2530 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2531 DC_TXSTAT_NOCARRIER))) 2532 txstat &= ~DC_TXSTAT_ERRSUM; 2533 } else { 2534 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2535 sc->dc_pmode == DC_PMODE_MII && 2536 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2537 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2538 txstat &= ~DC_TXSTAT_ERRSUM; 2539 } 2540 2541 if (txstat & DC_TXSTAT_ERRSUM) { 2542 ifp->if_oerrors++; 2543 if (txstat & DC_TXSTAT_EXCESSCOLL) 2544 ifp->if_collisions++; 2545 if (txstat & DC_TXSTAT_LATECOLL) 2546 ifp->if_collisions++; 2547 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2548 dc_init(sc); 2549 return; 2550 } 2551 } 2552 2553 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2554 2555 ifp->if_opackets++; 2556 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2557 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2558 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2559 } 2560 2561 sc->dc_cdata.dc_tx_cnt--; 2562 DC_INC(idx, DC_TX_LIST_CNT); 2563 } 2564 2565 if (idx != sc->dc_cdata.dc_tx_cons) { 2566 /* some buffers have been freed */ 2567 sc->dc_cdata.dc_tx_cons = idx; 2568 ifp->if_flags &= ~IFF_OACTIVE; 2569 } 2570 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2571 2572 return; 2573 } 2574 2575 static void 2576 dc_tick(void *xsc) 2577 { 2578 struct dc_softc *sc = xsc; 2579 struct ifnet *ifp = &sc->arpcom.ac_if; 2580 struct mii_data *mii; 2581 u_int32_t r; 2582 2583 crit_enter(); 2584 2585 mii = device_get_softc(sc->dc_miibus); 2586 2587 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2588 if (sc->dc_flags & DC_21143_NWAY) { 2589 r = CSR_READ_4(sc, DC_10BTSTAT); 2590 if (IFM_SUBTYPE(mii->mii_media_active) == 2591 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2592 sc->dc_link = 0; 2593 mii_mediachg(mii); 2594 } 2595 if (IFM_SUBTYPE(mii->mii_media_active) == 2596 IFM_10_T && (r & DC_TSTAT_LS10)) { 2597 sc->dc_link = 0; 2598 mii_mediachg(mii); 2599 } 2600 if (sc->dc_link == 0) 2601 mii_tick(mii); 2602 } else { 2603 r = CSR_READ_4(sc, DC_ISR); 2604 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2605 sc->dc_cdata.dc_tx_cnt == 0) { 2606 mii_tick(mii); 2607 if (!(mii->mii_media_status & IFM_ACTIVE)) 2608 sc->dc_link = 0; 2609 } 2610 } 2611 } else 2612 mii_tick(mii); 2613 2614 /* 2615 * When the init routine completes, we expect to be able to send 2616 * packets right away, and in fact the network code will send a 2617 * gratuitous ARP the moment the init routine marks the interface 2618 * as running. However, even though the MAC may have been initialized, 2619 * there may be a delay of a few seconds before the PHY completes 2620 * autonegotiation and the link is brought up. Any transmissions 2621 * made during that delay will be lost. Dealing with this is tricky: 2622 * we can't just pause in the init routine while waiting for the 2623 * PHY to come ready since that would bring the whole system to 2624 * a screeching halt for several seconds. 2625 * 2626 * What we do here is prevent the TX start routine from sending 2627 * any packets until a link has been established. After the 2628 * interface has been initialized, the tick routine will poll 2629 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2630 * that time, packets will stay in the send queue, and once the 2631 * link comes up, they will be flushed out to the wire. 2632 */ 2633 if (!sc->dc_link) { 2634 mii_pollstat(mii); 2635 if (mii->mii_media_status & IFM_ACTIVE && 2636 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2637 sc->dc_link++; 2638 if (!ifq_is_empty(&ifp->if_snd)) 2639 dc_start(ifp); 2640 } 2641 } 2642 2643 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2644 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2645 else 2646 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2647 2648 crit_exit(); 2649 } 2650 2651 /* 2652 * A transmit underrun has occurred. Back off the transmit threshold, 2653 * or switch to store and forward mode if we have to. 2654 */ 2655 static void 2656 dc_tx_underrun(struct dc_softc *sc) 2657 { 2658 u_int32_t isr; 2659 int i; 2660 2661 if (DC_IS_DAVICOM(sc)) 2662 dc_init(sc); 2663 2664 if (DC_IS_INTEL(sc)) { 2665 /* 2666 * The real 21143 requires that the transmitter be idle 2667 * in order to change the transmit threshold or store 2668 * and forward state. 2669 */ 2670 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2671 2672 for (i = 0; i < DC_TIMEOUT; i++) { 2673 isr = CSR_READ_4(sc, DC_ISR); 2674 if (isr & DC_ISR_TX_IDLE) 2675 break; 2676 DELAY(10); 2677 } 2678 if (i == DC_TIMEOUT) { 2679 if_printf(&sc->arpcom.ac_if, 2680 "failed to force tx to idle state\n"); 2681 dc_init(sc); 2682 } 2683 } 2684 2685 if_printf(&sc->arpcom.ac_if, "TX underrun -- "); 2686 sc->dc_txthresh += DC_TXTHRESH_INC; 2687 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2688 printf("using store and forward mode\n"); 2689 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2690 } else { 2691 printf("increasing TX threshold\n"); 2692 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2693 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2694 } 2695 2696 if (DC_IS_INTEL(sc)) 2697 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2698 2699 return; 2700 } 2701 2702 #ifdef DEVICE_POLLING 2703 2704 static void 2705 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2706 { 2707 struct dc_softc *sc = ifp->if_softc; 2708 u_int32_t status; 2709 2710 switch(cmd) { 2711 case POLL_REGISTER: 2712 /* Disable interrupts */ 2713 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2714 break; 2715 case POLL_DEREGISTER: 2716 /* Re-enable interrupts. */ 2717 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2718 break; 2719 case POLL_ONLY: 2720 sc->rxcycles = count; 2721 dc_rxeof(sc); 2722 dc_txeof(sc); 2723 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2724 dc_start(ifp); 2725 break; 2726 case POLL_AND_CHECK_STATUS: 2727 sc->rxcycles = count; 2728 dc_rxeof(sc); 2729 dc_txeof(sc); 2730 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2731 dc_start(ifp); 2732 status = CSR_READ_4(sc, DC_ISR); 2733 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2734 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2735 DC_ISR_BUS_ERR); 2736 if (!status) 2737 break; 2738 /* ack what we have */ 2739 CSR_WRITE_4(sc, DC_ISR, status); 2740 2741 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2742 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2743 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2744 2745 if (dc_rx_resync(sc)) 2746 dc_rxeof(sc); 2747 } 2748 /* restart transmit unit if necessary */ 2749 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2750 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2751 2752 if (status & DC_ISR_TX_UNDERRUN) 2753 dc_tx_underrun(sc); 2754 2755 if (status & DC_ISR_BUS_ERR) { 2756 if_printf(ifp, "dc_poll: bus error\n"); 2757 dc_reset(sc); 2758 dc_init(sc); 2759 } 2760 break; 2761 } 2762 } 2763 #endif /* DEVICE_POLLING */ 2764 2765 static void 2766 dc_intr(void *arg) 2767 { 2768 struct dc_softc *sc; 2769 struct ifnet *ifp; 2770 u_int32_t status; 2771 2772 sc = arg; 2773 2774 if (sc->suspended) { 2775 return; 2776 } 2777 2778 ifp = &sc->arpcom.ac_if; 2779 2780 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2781 return ; 2782 2783 /* Suppress unwanted interrupts */ 2784 if (!(ifp->if_flags & IFF_UP)) { 2785 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2786 dc_stop(sc); 2787 return; 2788 } 2789 2790 /* Disable interrupts. */ 2791 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2792 2793 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2794 2795 CSR_WRITE_4(sc, DC_ISR, status); 2796 2797 if (status & DC_ISR_RX_OK) { 2798 int curpkts; 2799 curpkts = ifp->if_ipackets; 2800 dc_rxeof(sc); 2801 if (curpkts == ifp->if_ipackets) { 2802 while(dc_rx_resync(sc)) 2803 dc_rxeof(sc); 2804 } 2805 } 2806 2807 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2808 dc_txeof(sc); 2809 2810 if (status & DC_ISR_TX_IDLE) { 2811 dc_txeof(sc); 2812 if (sc->dc_cdata.dc_tx_cnt) { 2813 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2814 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2815 } 2816 } 2817 2818 if (status & DC_ISR_TX_UNDERRUN) 2819 dc_tx_underrun(sc); 2820 2821 if ((status & DC_ISR_RX_WATDOGTIMEO) 2822 || (status & DC_ISR_RX_NOBUF)) { 2823 int curpkts; 2824 curpkts = ifp->if_ipackets; 2825 dc_rxeof(sc); 2826 if (curpkts == ifp->if_ipackets) { 2827 while(dc_rx_resync(sc)) 2828 dc_rxeof(sc); 2829 } 2830 } 2831 2832 if (status & DC_ISR_BUS_ERR) { 2833 dc_reset(sc); 2834 dc_init(sc); 2835 } 2836 } 2837 2838 /* Re-enable interrupts. */ 2839 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2840 2841 if (!ifq_is_empty(&ifp->if_snd)) 2842 dc_start(ifp); 2843 2844 return; 2845 } 2846 2847 /* 2848 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2849 * pointers to the fragment pointers. 2850 */ 2851 static int 2852 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2853 { 2854 struct dc_desc *f = NULL; 2855 struct mbuf *m; 2856 int frag, cur, cnt = 0; 2857 2858 /* 2859 * Start packing the mbufs in this chain into 2860 * the fragment pointers. Stop when we run out 2861 * of fragments or hit the end of the mbuf chain. 2862 */ 2863 m = m_head; 2864 cur = frag = *txidx; 2865 2866 for (m = m_head; m != NULL; m = m->m_next) { 2867 if (m->m_len != 0) { 2868 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2869 if (*txidx != sc->dc_cdata.dc_tx_prod && 2870 frag == (DC_TX_LIST_CNT - 1)) 2871 return(ENOBUFS); 2872 } 2873 if ((DC_TX_LIST_CNT - 2874 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2875 return(ENOBUFS); 2876 2877 f = &sc->dc_ldata->dc_tx_list[frag]; 2878 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2879 if (cnt == 0) { 2880 f->dc_status = 0; 2881 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2882 } else 2883 f->dc_status = DC_TXSTAT_OWN; 2884 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2885 cur = frag; 2886 DC_INC(frag, DC_TX_LIST_CNT); 2887 cnt++; 2888 } 2889 } 2890 2891 if (m != NULL) 2892 return(ENOBUFS); 2893 2894 sc->dc_cdata.dc_tx_cnt += cnt; 2895 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2896 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2897 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2898 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2899 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2900 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2901 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2902 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2903 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2904 *txidx = frag; 2905 2906 return(0); 2907 } 2908 2909 /* 2910 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2911 * to the mbuf data regions directly in the transmit lists. We also save a 2912 * copy of the pointers since the transmit list fragment pointers are 2913 * physical addresses. 2914 */ 2915 2916 static void 2917 dc_start(struct ifnet *ifp) 2918 { 2919 struct dc_softc *sc; 2920 struct mbuf *m_head; 2921 struct mbuf *m_defragged; 2922 int idx, need_trans; 2923 2924 sc = ifp->if_softc; 2925 2926 if (!sc->dc_link) 2927 return; 2928 2929 if (ifp->if_flags & IFF_OACTIVE) 2930 return; 2931 2932 idx = sc->dc_cdata.dc_tx_prod; 2933 2934 need_trans = 0; 2935 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2936 m_defragged = NULL; 2937 m_head = ifq_poll(&ifp->if_snd); 2938 if (m_head == NULL) 2939 break; 2940 2941 if (sc->dc_flags & DC_TX_COALESCE && 2942 (m_head->m_next != NULL || 2943 sc->dc_flags & DC_TX_ALIGN)){ 2944 /* 2945 * Check first if coalescing allows us to queue 2946 * the packet. We don't want to loose it if 2947 * the TX queue is full. 2948 */ 2949 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 2950 idx != sc->dc_cdata.dc_tx_prod && 2951 idx == (DC_TX_LIST_CNT - 1)) { 2952 ifp->if_flags |= IFF_OACTIVE; 2953 break; 2954 } 2955 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { 2956 ifp->if_flags |= IFF_OACTIVE; 2957 break; 2958 } 2959 2960 /* only coalesce if have >1 mbufs */ 2961 m_defragged = m_defrag_nofree(m_head, MB_DONTWAIT); 2962 if (m_defragged == NULL) { 2963 ifp->if_flags |= IFF_OACTIVE; 2964 break; 2965 } 2966 } 2967 2968 if (dc_encap(sc, (m_defragged ? m_defragged : m_head), &idx)) { 2969 if (m_defragged) { 2970 /* 2971 * Throw away the original packet if the 2972 * defragged packet could not be encapsulated, 2973 * as well as the defragged packet. 2974 */ 2975 ifq_dequeue(&ifp->if_snd, m_head); 2976 m_freem(m_head); 2977 m_freem(m_defragged); 2978 } 2979 ifp->if_flags |= IFF_OACTIVE; 2980 break; 2981 } 2982 2983 ifq_dequeue(&ifp->if_snd, m_head); 2984 2985 need_trans = 1; 2986 2987 /* 2988 * If there's a BPF listener, bounce a copy of this frame 2989 * to him. 2990 */ 2991 BPF_MTAP(ifp, (m_defragged ? m_defragged : m_head)); 2992 2993 /* 2994 * If we defragged the packet, m_head is not the one we 2995 * encapsulated so we can throw it away. 2996 */ 2997 if (m_defragged) 2998 m_freem(m_head); 2999 3000 if (sc->dc_flags & DC_TX_ONE) { 3001 ifp->if_flags |= IFF_OACTIVE; 3002 break; 3003 } 3004 } 3005 3006 if (!need_trans) 3007 return; 3008 3009 /* Transmit */ 3010 sc->dc_cdata.dc_tx_prod = idx; 3011 if (!(sc->dc_flags & DC_TX_POLL)) 3012 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3013 3014 /* 3015 * Set a timeout in case the chip goes out to lunch. 3016 */ 3017 ifp->if_timer = 5; 3018 } 3019 3020 static void 3021 dc_init(void *xsc) 3022 { 3023 struct dc_softc *sc = xsc; 3024 struct ifnet *ifp = &sc->arpcom.ac_if; 3025 struct mii_data *mii; 3026 3027 crit_enter(); 3028 3029 mii = device_get_softc(sc->dc_miibus); 3030 3031 /* 3032 * Cancel pending I/O and free all RX/TX buffers. 3033 */ 3034 dc_stop(sc); 3035 dc_reset(sc); 3036 3037 /* 3038 * Set cache alignment and burst length. 3039 */ 3040 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3041 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3042 else 3043 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3044 /* 3045 * Evenly share the bus between receive and transmit process. 3046 */ 3047 if (DC_IS_INTEL(sc)) 3048 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3049 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3050 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3051 } else { 3052 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3053 } 3054 if (sc->dc_flags & DC_TX_POLL) 3055 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3056 switch(sc->dc_cachesize) { 3057 case 32: 3058 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3059 break; 3060 case 16: 3061 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3062 break; 3063 case 8: 3064 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3065 break; 3066 case 0: 3067 default: 3068 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3069 break; 3070 } 3071 3072 if (sc->dc_flags & DC_TX_STORENFWD) 3073 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3074 else { 3075 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3076 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3077 } else { 3078 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3079 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3080 } 3081 } 3082 3083 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3084 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3085 3086 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3087 /* 3088 * The app notes for the 98713 and 98715A say that 3089 * in order to have the chips operate properly, a magic 3090 * number must be written to CSR16. Macronix does not 3091 * document the meaning of these bits so there's no way 3092 * to know exactly what they do. The 98713 has a magic 3093 * number all its own; the rest all use a different one. 3094 */ 3095 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3096 if (sc->dc_type == DC_TYPE_98713) 3097 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3098 else 3099 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3100 } 3101 3102 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3103 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3104 3105 /* Init circular RX list. */ 3106 if (dc_list_rx_init(sc) == ENOBUFS) { 3107 if_printf(ifp, "initialization failed: no " 3108 "memory for rx buffers\n"); 3109 dc_stop(sc); 3110 crit_exit(); 3111 return; 3112 } 3113 3114 /* 3115 * Init tx descriptors. 3116 */ 3117 dc_list_tx_init(sc); 3118 3119 /* 3120 * Load the address of the RX list. 3121 */ 3122 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3123 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3124 3125 /* 3126 * Enable interrupts. 3127 */ 3128 #ifdef DEVICE_POLLING 3129 /* 3130 * ... but only if we are not polling, and make sure they are off in 3131 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3132 * after a reset. 3133 */ 3134 if (ifp->if_flags & IFF_POLLING) 3135 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3136 else 3137 #endif 3138 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3139 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3140 3141 /* Enable transmitter. */ 3142 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3143 3144 /* 3145 * If this is an Intel 21143 and we're not using the 3146 * MII port, program the LED control pins so we get 3147 * link and activity indications. 3148 */ 3149 if (sc->dc_flags & DC_TULIP_LEDS) { 3150 CSR_WRITE_4(sc, DC_WATCHDOG, 3151 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3152 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3153 } 3154 3155 /* 3156 * Load the RX/multicast filter. We do this sort of late 3157 * because the filter programming scheme on the 21143 and 3158 * some clones requires DMAing a setup frame via the TX 3159 * engine, and we need the transmitter enabled for that. 3160 */ 3161 dc_setfilt(sc); 3162 3163 /* Enable receiver. */ 3164 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3165 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3166 3167 mii_mediachg(mii); 3168 dc_setcfg(sc, sc->dc_if_media); 3169 3170 ifp->if_flags |= IFF_RUNNING; 3171 ifp->if_flags &= ~IFF_OACTIVE; 3172 3173 crit_exit(); 3174 3175 /* Don't start the ticker if this is a homePNA link. */ 3176 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3177 sc->dc_link = 1; 3178 else { 3179 if (sc->dc_flags & DC_21143_NWAY) 3180 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3181 else 3182 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3183 } 3184 3185 return; 3186 } 3187 3188 /* 3189 * Set media options. 3190 */ 3191 static int 3192 dc_ifmedia_upd(struct ifnet *ifp) 3193 { 3194 struct dc_softc *sc; 3195 struct mii_data *mii; 3196 struct ifmedia *ifm; 3197 3198 sc = ifp->if_softc; 3199 mii = device_get_softc(sc->dc_miibus); 3200 mii_mediachg(mii); 3201 ifm = &mii->mii_media; 3202 3203 if (DC_IS_DAVICOM(sc) && 3204 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3205 dc_setcfg(sc, ifm->ifm_media); 3206 else 3207 sc->dc_link = 0; 3208 3209 return(0); 3210 } 3211 3212 /* 3213 * Report current media status. 3214 */ 3215 static void 3216 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3217 { 3218 struct dc_softc *sc; 3219 struct mii_data *mii; 3220 struct ifmedia *ifm; 3221 3222 sc = ifp->if_softc; 3223 mii = device_get_softc(sc->dc_miibus); 3224 mii_pollstat(mii); 3225 ifm = &mii->mii_media; 3226 if (DC_IS_DAVICOM(sc)) { 3227 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3228 ifmr->ifm_active = ifm->ifm_media; 3229 ifmr->ifm_status = 0; 3230 return; 3231 } 3232 } 3233 ifmr->ifm_active = mii->mii_media_active; 3234 ifmr->ifm_status = mii->mii_media_status; 3235 3236 return; 3237 } 3238 3239 static int 3240 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3241 { 3242 struct dc_softc *sc = ifp->if_softc; 3243 struct ifreq *ifr = (struct ifreq *) data; 3244 struct mii_data *mii; 3245 int error = 0; 3246 3247 crit_enter(); 3248 3249 switch(command) { 3250 case SIOCSIFFLAGS: 3251 if (ifp->if_flags & IFF_UP) { 3252 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3253 (IFF_PROMISC | IFF_ALLMULTI); 3254 if (ifp->if_flags & IFF_RUNNING) { 3255 if (need_setfilt) 3256 dc_setfilt(sc); 3257 } else { 3258 sc->dc_txthresh = 0; 3259 dc_init(sc); 3260 } 3261 } else { 3262 if (ifp->if_flags & IFF_RUNNING) 3263 dc_stop(sc); 3264 } 3265 sc->dc_if_flags = ifp->if_flags; 3266 error = 0; 3267 break; 3268 case SIOCADDMULTI: 3269 case SIOCDELMULTI: 3270 dc_setfilt(sc); 3271 error = 0; 3272 break; 3273 case SIOCGIFMEDIA: 3274 case SIOCSIFMEDIA: 3275 mii = device_get_softc(sc->dc_miibus); 3276 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3277 break; 3278 default: 3279 error = ether_ioctl(ifp, command, data); 3280 break; 3281 } 3282 3283 crit_exit(); 3284 3285 return(error); 3286 } 3287 3288 static void 3289 dc_watchdog(struct ifnet *ifp) 3290 { 3291 struct dc_softc *sc; 3292 3293 sc = ifp->if_softc; 3294 3295 ifp->if_oerrors++; 3296 if_printf(ifp, "watchdog timeout\n"); 3297 3298 dc_stop(sc); 3299 dc_reset(sc); 3300 dc_init(sc); 3301 3302 if (!ifq_is_empty(&ifp->if_snd)) 3303 dc_start(ifp); 3304 3305 return; 3306 } 3307 3308 /* 3309 * Stop the adapter and free any mbufs allocated to the 3310 * RX and TX lists. 3311 */ 3312 static void 3313 dc_stop(struct dc_softc *sc) 3314 { 3315 int i; 3316 struct ifnet *ifp; 3317 3318 ifp = &sc->arpcom.ac_if; 3319 ifp->if_timer = 0; 3320 3321 callout_stop(&sc->dc_stat_timer); 3322 3323 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3324 3325 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3326 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3327 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3328 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3329 sc->dc_link = 0; 3330 3331 /* 3332 * Free data in the RX lists. 3333 */ 3334 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3335 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3336 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3337 sc->dc_cdata.dc_rx_chain[i] = NULL; 3338 } 3339 } 3340 bzero((char *)&sc->dc_ldata->dc_rx_list, 3341 sizeof(sc->dc_ldata->dc_rx_list)); 3342 3343 /* 3344 * Free the TX list buffers. 3345 */ 3346 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3347 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3348 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3349 DC_TXCTL_SETUP) || 3350 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3351 DC_TXCTL_LASTFRAG)) { 3352 sc->dc_cdata.dc_tx_chain[i] = NULL; 3353 continue; 3354 } 3355 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3356 sc->dc_cdata.dc_tx_chain[i] = NULL; 3357 } 3358 } 3359 3360 bzero((char *)&sc->dc_ldata->dc_tx_list, 3361 sizeof(sc->dc_ldata->dc_tx_list)); 3362 3363 return; 3364 } 3365 3366 /* 3367 * Stop all chip I/O so that the kernel's probe routines don't 3368 * get confused by errant DMAs when rebooting. 3369 */ 3370 static void 3371 dc_shutdown(device_t dev) 3372 { 3373 struct dc_softc *sc; 3374 3375 sc = device_get_softc(dev); 3376 3377 dc_stop(sc); 3378 3379 return; 3380 } 3381 3382 /* 3383 * Device suspend routine. Stop the interface and save some PCI 3384 * settings in case the BIOS doesn't restore them properly on 3385 * resume. 3386 */ 3387 static int 3388 dc_suspend(device_t dev) 3389 { 3390 struct dc_softc *sc = device_get_softc(dev); 3391 int i; 3392 3393 crit_enter(); 3394 3395 dc_stop(sc); 3396 3397 for (i = 0; i < 5; i++) 3398 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3399 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3400 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3401 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3402 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3403 3404 sc->suspended = 1; 3405 3406 crit_exit(); 3407 return (0); 3408 } 3409 3410 /* 3411 * Device resume routine. Restore some PCI settings in case the BIOS 3412 * doesn't, re-enable busmastering, and restart the interface if 3413 * appropriate. 3414 */ 3415 static int 3416 dc_resume(device_t dev) 3417 { 3418 struct dc_softc *sc = device_get_softc(dev); 3419 struct ifnet *ifp = &sc->arpcom.ac_if; 3420 int i; 3421 3422 crit_enter(); 3423 3424 dc_acpi(dev); 3425 3426 /* better way to do this? */ 3427 for (i = 0; i < 5; i++) 3428 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3429 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3430 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3431 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3432 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3433 3434 /* reenable busmastering */ 3435 pci_enable_busmaster(dev); 3436 pci_enable_io(dev, DC_RES); 3437 3438 /* reinitialize interface if necessary */ 3439 if (ifp->if_flags & IFF_UP) 3440 dc_init(sc); 3441 3442 sc->suspended = 0; 3443 3444 crit_exit(); 3445 return (0); 3446 } 3447