1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.36 2005/07/16 17:11:39 dillon Exp $ 34 */ 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 48 * Accton EN1217 (www.accton.com) 49 * Conexant LANfinity (www.conexant.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/sysctl.h> 99 #include <sys/thread2.h> 100 101 #include <net/if.h> 102 #include <net/ifq_var.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/vlan/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include "../mii_layer/mii.h" 122 #include "../mii_layer/miivar.h" 123 124 #include <bus/pci/pcireg.h> 125 #include <bus/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 129 #include "if_dcreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 static struct dc_type dc_devs[] = { 138 { DC_VENDORID_DEC, DC_DEVICEID_21143, 139 "Intel 21143 10/100BaseTX" }, 140 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 141 "Davicom DM9009 10/100BaseTX" }, 142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 143 "Davicom DM9100 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 145 "Davicom DM9102 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 147 "Davicom DM9102A 10/100BaseTX" }, 148 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 149 "ADMtek AL981 10/100BaseTX" }, 150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 151 "ADMtek AN985 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 153 "ADMtek ADM9511 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 155 "ADMtek ADM9513 10/100BaseTX" }, 156 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 157 "ASIX AX88140A 10/100BaseTX" }, 158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 159 "ASIX AX88141 10/100BaseTX" }, 160 { DC_VENDORID_MX, DC_DEVICEID_98713, 161 "Macronix 98713 10/100BaseTX" }, 162 { DC_VENDORID_MX, DC_DEVICEID_98713, 163 "Macronix 98713A 10/100BaseTX" }, 164 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 165 "Compex RL100-TX 10/100BaseTX" }, 166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 167 "Compex RL100-TX 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98715/98715A 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98715AEC-C 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98725 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_98727, 175 "Macronix 98727/98732 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C115, 177 "LC82C115 PNIC II 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C168, 179 "82c168 PNIC 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C168, 181 "82c169 PNIC 10/100BaseTX" }, 182 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 183 "Accton EN1217 10/100BaseTX" }, 184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 185 "Accton EN2242 MiniPCI 10/100BaseTX" }, 186 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 187 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 188 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 189 "3Com OfficeConnect 10/100B" }, 190 { 0, 0, NULL } 191 }; 192 193 static int dc_probe (device_t); 194 static int dc_attach (device_t); 195 static int dc_detach (device_t); 196 static int dc_suspend (device_t); 197 static int dc_resume (device_t); 198 static void dc_acpi (device_t); 199 static struct dc_type *dc_devtype (device_t); 200 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 201 static int dc_encap (struct dc_softc *, struct mbuf *, 202 u_int32_t *); 203 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 204 static int dc_rx_resync (struct dc_softc *); 205 static void dc_rxeof (struct dc_softc *); 206 static void dc_txeof (struct dc_softc *); 207 static void dc_tick (void *); 208 static void dc_tx_underrun (struct dc_softc *); 209 static void dc_intr (void *); 210 static void dc_start (struct ifnet *); 211 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 212 struct ucred *); 213 #ifdef DEVICE_POLLING 214 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd, 215 int count); 216 #endif 217 static void dc_init (void *); 218 static void dc_stop (struct dc_softc *); 219 static void dc_watchdog (struct ifnet *); 220 static void dc_shutdown (device_t); 221 static int dc_ifmedia_upd (struct ifnet *); 222 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 223 224 static void dc_delay (struct dc_softc *); 225 static void dc_eeprom_idle (struct dc_softc *); 226 static void dc_eeprom_putbyte (struct dc_softc *, int); 227 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 228 static void dc_eeprom_getword_pnic 229 (struct dc_softc *, int, u_int16_t *); 230 static void dc_eeprom_width (struct dc_softc *); 231 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 232 int, int); 233 234 static void dc_mii_writebit (struct dc_softc *, int); 235 static int dc_mii_readbit (struct dc_softc *); 236 static void dc_mii_sync (struct dc_softc *); 237 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 238 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 239 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 240 static int dc_miibus_readreg (device_t, int, int); 241 static int dc_miibus_writereg (device_t, int, int, int); 242 static void dc_miibus_statchg (device_t); 243 static void dc_miibus_mediainit (device_t); 244 245 static u_int32_t dc_crc_mask (struct dc_softc *); 246 static void dc_setcfg (struct dc_softc *, int); 247 static void dc_setfilt_21143 (struct dc_softc *); 248 static void dc_setfilt_asix (struct dc_softc *); 249 static void dc_setfilt_admtek (struct dc_softc *); 250 251 static void dc_setfilt (struct dc_softc *); 252 253 static void dc_reset (struct dc_softc *); 254 static int dc_list_rx_init (struct dc_softc *); 255 static int dc_list_tx_init (struct dc_softc *); 256 257 static void dc_read_srom (struct dc_softc *, int); 258 static void dc_parse_21143_srom (struct dc_softc *); 259 static void dc_decode_leaf_sia (struct dc_softc *, 260 struct dc_eblock_sia *); 261 static void dc_decode_leaf_mii (struct dc_softc *, 262 struct dc_eblock_mii *); 263 static void dc_decode_leaf_sym (struct dc_softc *, 264 struct dc_eblock_sym *); 265 static void dc_apply_fixup (struct dc_softc *, int); 266 267 #ifdef DC_USEIOSPACE 268 #define DC_RES SYS_RES_IOPORT 269 #define DC_RID DC_PCI_CFBIO 270 #else 271 #define DC_RES SYS_RES_MEMORY 272 #define DC_RID DC_PCI_CFBMA 273 #endif 274 275 static device_method_t dc_methods[] = { 276 /* Device interface */ 277 DEVMETHOD(device_probe, dc_probe), 278 DEVMETHOD(device_attach, dc_attach), 279 DEVMETHOD(device_detach, dc_detach), 280 DEVMETHOD(device_suspend, dc_suspend), 281 DEVMETHOD(device_resume, dc_resume), 282 DEVMETHOD(device_shutdown, dc_shutdown), 283 284 /* bus interface */ 285 DEVMETHOD(bus_print_child, bus_generic_print_child), 286 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 287 288 /* MII interface */ 289 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 290 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 291 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 292 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 293 294 { 0, 0 } 295 }; 296 297 static driver_t dc_driver = { 298 "dc", 299 dc_methods, 300 sizeof(struct dc_softc) 301 }; 302 303 static devclass_t dc_devclass; 304 305 #ifdef __i386__ 306 static int dc_quick=1; 307 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 308 &dc_quick,0,"do not mdevget in dc driver"); 309 #endif 310 311 DECLARE_DUMMY_MODULE(if_dc); 312 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 313 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 314 315 #define DC_SETBIT(sc, reg, x) \ 316 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 317 318 #define DC_CLRBIT(sc, reg, x) \ 319 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 320 321 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 322 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 323 324 static void dc_delay(sc) 325 struct dc_softc *sc; 326 { 327 int idx; 328 329 for (idx = (300 / 33) + 1; idx > 0; idx--) 330 CSR_READ_4(sc, DC_BUSCTL); 331 } 332 333 static void dc_eeprom_width(sc) 334 struct dc_softc *sc; 335 { 336 int i; 337 338 /* Force EEPROM to idle state. */ 339 dc_eeprom_idle(sc); 340 341 /* Enter EEPROM access mode. */ 342 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 343 dc_delay(sc); 344 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 345 dc_delay(sc); 346 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 347 dc_delay(sc); 348 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 349 dc_delay(sc); 350 351 for (i = 3; i--;) { 352 if (6 & (1 << i)) 353 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 354 else 355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 356 dc_delay(sc); 357 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 358 dc_delay(sc); 359 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 360 dc_delay(sc); 361 } 362 363 for (i = 1; i <= 12; i++) { 364 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 365 dc_delay(sc); 366 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 367 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 368 dc_delay(sc); 369 break; 370 } 371 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 372 dc_delay(sc); 373 } 374 375 /* Turn off EEPROM access mode. */ 376 dc_eeprom_idle(sc); 377 378 if (i < 4 || i > 12) 379 sc->dc_romwidth = 6; 380 else 381 sc->dc_romwidth = i; 382 383 /* Enter EEPROM access mode. */ 384 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 385 dc_delay(sc); 386 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 387 dc_delay(sc); 388 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 389 dc_delay(sc); 390 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 391 dc_delay(sc); 392 393 /* Turn off EEPROM access mode. */ 394 dc_eeprom_idle(sc); 395 } 396 397 static void dc_eeprom_idle(sc) 398 struct dc_softc *sc; 399 { 400 int i; 401 402 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 403 dc_delay(sc); 404 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 405 dc_delay(sc); 406 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 407 dc_delay(sc); 408 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 409 dc_delay(sc); 410 411 for (i = 0; i < 25; i++) { 412 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 } 417 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 421 dc_delay(sc); 422 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 423 424 return; 425 } 426 427 /* 428 * Send a read command and address to the EEPROM, check for ACK. 429 */ 430 static void dc_eeprom_putbyte(sc, addr) 431 struct dc_softc *sc; 432 int addr; 433 { 434 int d, i; 435 436 d = DC_EECMD_READ >> 6; 437 for (i = 3; i--; ) { 438 if (d & (1 << i)) 439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 440 else 441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 442 dc_delay(sc); 443 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 444 dc_delay(sc); 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 446 dc_delay(sc); 447 } 448 449 /* 450 * Feed in each bit and strobe the clock. 451 */ 452 for (i = sc->dc_romwidth; i--;) { 453 if (addr & (1 << i)) { 454 SIO_SET(DC_SIO_EE_DATAIN); 455 } else { 456 SIO_CLR(DC_SIO_EE_DATAIN); 457 } 458 dc_delay(sc); 459 SIO_SET(DC_SIO_EE_CLK); 460 dc_delay(sc); 461 SIO_CLR(DC_SIO_EE_CLK); 462 dc_delay(sc); 463 } 464 465 return; 466 } 467 468 /* 469 * Read a word of data stored in the EEPROM at address 'addr.' 470 * The PNIC 82c168/82c169 has its own non-standard way to read 471 * the EEPROM. 472 */ 473 static void dc_eeprom_getword_pnic(sc, addr, dest) 474 struct dc_softc *sc; 475 int addr; 476 u_int16_t *dest; 477 { 478 int i; 479 u_int32_t r; 480 481 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 482 483 for (i = 0; i < DC_TIMEOUT; i++) { 484 DELAY(1); 485 r = CSR_READ_4(sc, DC_SIO); 486 if (!(r & DC_PN_SIOCTL_BUSY)) { 487 *dest = (u_int16_t)(r & 0xFFFF); 488 return; 489 } 490 } 491 492 return; 493 } 494 495 /* 496 * Read a word of data stored in the EEPROM at address 'addr.' 497 */ 498 static void dc_eeprom_getword(sc, addr, dest) 499 struct dc_softc *sc; 500 int addr; 501 u_int16_t *dest; 502 { 503 int i; 504 u_int16_t word = 0; 505 506 /* Force EEPROM to idle state. */ 507 dc_eeprom_idle(sc); 508 509 /* Enter EEPROM access mode. */ 510 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 511 dc_delay(sc); 512 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 513 dc_delay(sc); 514 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 515 dc_delay(sc); 516 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 517 dc_delay(sc); 518 519 /* 520 * Send address of word we want to read. 521 */ 522 dc_eeprom_putbyte(sc, addr); 523 524 /* 525 * Start reading bits from EEPROM. 526 */ 527 for (i = 0x8000; i; i >>= 1) { 528 SIO_SET(DC_SIO_EE_CLK); 529 dc_delay(sc); 530 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 531 word |= i; 532 dc_delay(sc); 533 SIO_CLR(DC_SIO_EE_CLK); 534 dc_delay(sc); 535 } 536 537 /* Turn off EEPROM access mode. */ 538 dc_eeprom_idle(sc); 539 540 *dest = word; 541 542 return; 543 } 544 545 /* 546 * Read a sequence of words from the EEPROM. 547 */ 548 static void dc_read_eeprom(sc, dest, off, cnt, swap) 549 struct dc_softc *sc; 550 caddr_t dest; 551 int off; 552 int cnt; 553 int swap; 554 { 555 int i; 556 u_int16_t word = 0, *ptr; 557 558 for (i = 0; i < cnt; i++) { 559 if (DC_IS_PNIC(sc)) 560 dc_eeprom_getword_pnic(sc, off + i, &word); 561 else 562 dc_eeprom_getword(sc, off + i, &word); 563 ptr = (u_int16_t *)(dest + (i * 2)); 564 if (swap) 565 *ptr = ntohs(word); 566 else 567 *ptr = word; 568 } 569 570 return; 571 } 572 573 /* 574 * The following two routines are taken from the Macronix 98713 575 * Application Notes pp.19-21. 576 */ 577 /* 578 * Write a bit to the MII bus. 579 */ 580 static void dc_mii_writebit(sc, bit) 581 struct dc_softc *sc; 582 int bit; 583 { 584 if (bit) 585 CSR_WRITE_4(sc, DC_SIO, 586 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 587 else 588 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 589 590 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 591 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 592 593 return; 594 } 595 596 /* 597 * Read a bit from the MII bus. 598 */ 599 static int dc_mii_readbit(sc) 600 struct dc_softc *sc; 601 { 602 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 603 CSR_READ_4(sc, DC_SIO); 604 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 605 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 606 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 607 return(1); 608 609 return(0); 610 } 611 612 /* 613 * Sync the PHYs by setting data bit and strobing the clock 32 times. 614 */ 615 static void dc_mii_sync(sc) 616 struct dc_softc *sc; 617 { 618 int i; 619 620 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 621 622 for (i = 0; i < 32; i++) 623 dc_mii_writebit(sc, 1); 624 625 return; 626 } 627 628 /* 629 * Clock a series of bits through the MII. 630 */ 631 static void dc_mii_send(sc, bits, cnt) 632 struct dc_softc *sc; 633 u_int32_t bits; 634 int cnt; 635 { 636 int i; 637 638 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 639 dc_mii_writebit(sc, bits & i); 640 } 641 642 /* 643 * Read an PHY register through the MII. 644 */ 645 static int dc_mii_readreg(sc, frame) 646 struct dc_softc *sc; 647 struct dc_mii_frame *frame; 648 649 { 650 int ack, i; 651 652 crit_enter(); 653 654 /* 655 * Set up frame for RX. 656 */ 657 frame->mii_stdelim = DC_MII_STARTDELIM; 658 frame->mii_opcode = DC_MII_READOP; 659 frame->mii_turnaround = 0; 660 frame->mii_data = 0; 661 662 /* 663 * Sync the PHYs. 664 */ 665 dc_mii_sync(sc); 666 667 /* 668 * Send command/address info. 669 */ 670 dc_mii_send(sc, frame->mii_stdelim, 2); 671 dc_mii_send(sc, frame->mii_opcode, 2); 672 dc_mii_send(sc, frame->mii_phyaddr, 5); 673 dc_mii_send(sc, frame->mii_regaddr, 5); 674 675 #ifdef notdef 676 /* Idle bit */ 677 dc_mii_writebit(sc, 1); 678 dc_mii_writebit(sc, 0); 679 #endif 680 681 /* Check for ack */ 682 ack = dc_mii_readbit(sc); 683 684 /* 685 * Now try reading data bits. If the ack failed, we still 686 * need to clock through 16 cycles to keep the PHY(s) in sync. 687 */ 688 if (ack) { 689 for(i = 0; i < 16; i++) { 690 dc_mii_readbit(sc); 691 } 692 goto fail; 693 } 694 695 for (i = 0x8000; i; i >>= 1) { 696 if (!ack) { 697 if (dc_mii_readbit(sc)) 698 frame->mii_data |= i; 699 } 700 } 701 702 fail: 703 704 dc_mii_writebit(sc, 0); 705 dc_mii_writebit(sc, 0); 706 707 crit_exit(); 708 709 if (ack) 710 return(1); 711 return(0); 712 } 713 714 /* 715 * Write to a PHY register through the MII. 716 */ 717 static int dc_mii_writereg(sc, frame) 718 struct dc_softc *sc; 719 struct dc_mii_frame *frame; 720 721 { 722 crit_enter(); 723 724 /* 725 * Set up frame for TX. 726 */ 727 728 frame->mii_stdelim = DC_MII_STARTDELIM; 729 frame->mii_opcode = DC_MII_WRITEOP; 730 frame->mii_turnaround = DC_MII_TURNAROUND; 731 732 /* 733 * Sync the PHYs. 734 */ 735 dc_mii_sync(sc); 736 737 dc_mii_send(sc, frame->mii_stdelim, 2); 738 dc_mii_send(sc, frame->mii_opcode, 2); 739 dc_mii_send(sc, frame->mii_phyaddr, 5); 740 dc_mii_send(sc, frame->mii_regaddr, 5); 741 dc_mii_send(sc, frame->mii_turnaround, 2); 742 dc_mii_send(sc, frame->mii_data, 16); 743 744 /* Idle bit. */ 745 dc_mii_writebit(sc, 0); 746 dc_mii_writebit(sc, 0); 747 748 crit_exit(); 749 750 return(0); 751 } 752 753 static int dc_miibus_readreg(dev, phy, reg) 754 device_t dev; 755 int phy, reg; 756 { 757 struct dc_mii_frame frame; 758 struct dc_softc *sc; 759 int i, rval, phy_reg = 0; 760 761 sc = device_get_softc(dev); 762 bzero((char *)&frame, sizeof(frame)); 763 764 /* 765 * Note: both the AL981 and AN985 have internal PHYs, 766 * however the AL981 provides direct access to the PHY 767 * registers while the AN985 uses a serial MII interface. 768 * The AN985's MII interface is also buggy in that you 769 * can read from any MII address (0 to 31), but only address 1 770 * behaves normally. To deal with both cases, we pretend 771 * that the PHY is at MII address 1. 772 */ 773 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 774 return(0); 775 776 /* 777 * Note: the ukphy probes of the RS7112 report a PHY at 778 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 779 * so we only respond to correct one. 780 */ 781 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 782 return(0); 783 784 if (sc->dc_pmode != DC_PMODE_MII) { 785 if (phy == (MII_NPHY - 1)) { 786 switch(reg) { 787 case MII_BMSR: 788 /* 789 * Fake something to make the probe 790 * code think there's a PHY here. 791 */ 792 return(BMSR_MEDIAMASK); 793 break; 794 case MII_PHYIDR1: 795 if (DC_IS_PNIC(sc)) 796 return(DC_VENDORID_LO); 797 return(DC_VENDORID_DEC); 798 break; 799 case MII_PHYIDR2: 800 if (DC_IS_PNIC(sc)) 801 return(DC_DEVICEID_82C168); 802 return(DC_DEVICEID_21143); 803 break; 804 default: 805 return(0); 806 break; 807 } 808 } else 809 return(0); 810 } 811 812 if (DC_IS_PNIC(sc)) { 813 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 814 (phy << 23) | (reg << 18)); 815 for (i = 0; i < DC_TIMEOUT; i++) { 816 DELAY(1); 817 rval = CSR_READ_4(sc, DC_PN_MII); 818 if (!(rval & DC_PN_MII_BUSY)) { 819 rval &= 0xFFFF; 820 return(rval == 0xFFFF ? 0 : rval); 821 } 822 } 823 return(0); 824 } 825 826 if (DC_IS_COMET(sc)) { 827 switch(reg) { 828 case MII_BMCR: 829 phy_reg = DC_AL_BMCR; 830 break; 831 case MII_BMSR: 832 phy_reg = DC_AL_BMSR; 833 break; 834 case MII_PHYIDR1: 835 phy_reg = DC_AL_VENID; 836 break; 837 case MII_PHYIDR2: 838 phy_reg = DC_AL_DEVID; 839 break; 840 case MII_ANAR: 841 phy_reg = DC_AL_ANAR; 842 break; 843 case MII_ANLPAR: 844 phy_reg = DC_AL_LPAR; 845 break; 846 case MII_ANER: 847 phy_reg = DC_AL_ANER; 848 break; 849 default: 850 if_printf(&sc->arpcom.ac_if, 851 "phy_read: bad phy register %x\n", reg); 852 return(0); 853 break; 854 } 855 856 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 857 858 if (rval == 0xFFFF) 859 return(0); 860 return(rval); 861 } 862 863 frame.mii_phyaddr = phy; 864 frame.mii_regaddr = reg; 865 if (sc->dc_type == DC_TYPE_98713) { 866 phy_reg = CSR_READ_4(sc, DC_NETCFG); 867 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 868 } 869 dc_mii_readreg(sc, &frame); 870 if (sc->dc_type == DC_TYPE_98713) 871 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 872 873 return(frame.mii_data); 874 } 875 876 static int dc_miibus_writereg(dev, phy, reg, data) 877 device_t dev; 878 int phy, reg, data; 879 { 880 struct dc_softc *sc; 881 struct dc_mii_frame frame; 882 int i, phy_reg = 0; 883 884 sc = device_get_softc(dev); 885 bzero((char *)&frame, sizeof(frame)); 886 887 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 888 return(0); 889 890 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 891 return(0); 892 893 if (DC_IS_PNIC(sc)) { 894 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 895 (phy << 23) | (reg << 10) | data); 896 for (i = 0; i < DC_TIMEOUT; i++) { 897 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 898 break; 899 } 900 return(0); 901 } 902 903 if (DC_IS_COMET(sc)) { 904 switch(reg) { 905 case MII_BMCR: 906 phy_reg = DC_AL_BMCR; 907 break; 908 case MII_BMSR: 909 phy_reg = DC_AL_BMSR; 910 break; 911 case MII_PHYIDR1: 912 phy_reg = DC_AL_VENID; 913 break; 914 case MII_PHYIDR2: 915 phy_reg = DC_AL_DEVID; 916 break; 917 case MII_ANAR: 918 phy_reg = DC_AL_ANAR; 919 break; 920 case MII_ANLPAR: 921 phy_reg = DC_AL_LPAR; 922 break; 923 case MII_ANER: 924 phy_reg = DC_AL_ANER; 925 break; 926 default: 927 if_printf(&sc->arpcom.ac_if, 928 "phy_write: bad phy register %x\n", reg); 929 return(0); 930 break; 931 } 932 933 CSR_WRITE_4(sc, phy_reg, data); 934 return(0); 935 } 936 937 frame.mii_phyaddr = phy; 938 frame.mii_regaddr = reg; 939 frame.mii_data = data; 940 941 if (sc->dc_type == DC_TYPE_98713) { 942 phy_reg = CSR_READ_4(sc, DC_NETCFG); 943 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 944 } 945 dc_mii_writereg(sc, &frame); 946 if (sc->dc_type == DC_TYPE_98713) 947 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 948 949 return(0); 950 } 951 952 static void dc_miibus_statchg(dev) 953 device_t dev; 954 { 955 struct dc_softc *sc; 956 struct mii_data *mii; 957 struct ifmedia *ifm; 958 959 sc = device_get_softc(dev); 960 if (DC_IS_ADMTEK(sc)) 961 return; 962 963 mii = device_get_softc(sc->dc_miibus); 964 ifm = &mii->mii_media; 965 if (DC_IS_DAVICOM(sc) && 966 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 967 dc_setcfg(sc, ifm->ifm_media); 968 sc->dc_if_media = ifm->ifm_media; 969 } else { 970 dc_setcfg(sc, mii->mii_media_active); 971 sc->dc_if_media = mii->mii_media_active; 972 } 973 974 return; 975 } 976 977 /* 978 * Special support for DM9102A cards with HomePNA PHYs. Note: 979 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 980 * to be impossible to talk to the management interface of the DM9801 981 * PHY (its MDIO pin is not connected to anything). Consequently, 982 * the driver has to just 'know' about the additional mode and deal 983 * with it itself. *sigh* 984 */ 985 static void dc_miibus_mediainit(dev) 986 device_t dev; 987 { 988 struct dc_softc *sc; 989 struct mii_data *mii; 990 struct ifmedia *ifm; 991 int rev; 992 993 rev = pci_get_revid(dev); 994 995 sc = device_get_softc(dev); 996 mii = device_get_softc(sc->dc_miibus); 997 ifm = &mii->mii_media; 998 999 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1000 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1001 1002 return; 1003 } 1004 1005 #define DC_BITS_512 9 1006 #define DC_BITS_128 7 1007 #define DC_BITS_64 6 1008 1009 static u_int32_t 1010 dc_crc_mask(struct dc_softc *sc) 1011 { 1012 /* 1013 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1014 * chips is only 128 bits wide. 1015 */ 1016 if (sc->dc_flags & DC_128BIT_HASH) 1017 return ((1 << DC_BITS_128) - 1); 1018 1019 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1020 if (sc->dc_flags & DC_64BIT_HASH) 1021 return ((1 << DC_BITS_64) - 1); 1022 1023 return ((1 << DC_BITS_512) - 1); 1024 } 1025 1026 /* 1027 * 21143-style RX filter setup routine. Filter programming is done by 1028 * downloading a special setup frame into the TX engine. 21143, Macronix, 1029 * PNIC, PNIC II and Davicom chips are programmed this way. 1030 * 1031 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1032 * address (our node address) and a 512-bit hash filter for multicast 1033 * frames. We also sneak the broadcast address into the hash filter since 1034 * we need that too. 1035 */ 1036 void dc_setfilt_21143(sc) 1037 struct dc_softc *sc; 1038 { 1039 struct dc_desc *sframe; 1040 u_int32_t h, crc_mask, *sp; 1041 struct ifmultiaddr *ifma; 1042 struct ifnet *ifp; 1043 int i; 1044 1045 ifp = &sc->arpcom.ac_if; 1046 1047 i = sc->dc_cdata.dc_tx_prod; 1048 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1049 sc->dc_cdata.dc_tx_cnt++; 1050 sframe = &sc->dc_ldata->dc_tx_list[i]; 1051 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1052 bzero((char *)sp, DC_SFRAME_LEN); 1053 1054 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1055 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1056 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1057 1058 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1059 1060 /* If we want promiscuous mode, set the allframes bit. */ 1061 if (ifp->if_flags & IFF_PROMISC) 1062 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1063 else 1064 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1065 1066 if (ifp->if_flags & IFF_ALLMULTI) 1067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1068 else 1069 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1070 1071 crc_mask = dc_crc_mask(sc); 1072 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1073 if (ifma->ifma_addr->sa_family != AF_LINK) 1074 continue; 1075 h = ether_crc32_le( 1076 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1077 ETHER_ADDR_LEN) & crc_mask; 1078 sp[h >> 4] |= 1 << (h & 0xF); 1079 } 1080 1081 if (ifp->if_flags & IFF_BROADCAST) { 1082 h = ether_crc32_le(ifp->if_broadcastaddr, 1083 ETHER_ADDR_LEN) & crc_mask; 1084 sp[h >> 4] |= 1 << (h & 0xF); 1085 } 1086 1087 /* Set our MAC address */ 1088 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1089 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1090 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1091 1092 sframe->dc_status = DC_TXSTAT_OWN; 1093 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1094 1095 /* 1096 * The PNIC takes an exceedingly long time to process its 1097 * setup frame; wait 10ms after posting the setup frame 1098 * before proceeding, just so it has time to swallow its 1099 * medicine. 1100 */ 1101 DELAY(10000); 1102 1103 ifp->if_timer = 5; 1104 1105 return; 1106 } 1107 1108 void dc_setfilt_admtek(sc) 1109 struct dc_softc *sc; 1110 { 1111 struct ifnet *ifp; 1112 int h = 0; 1113 u_int32_t crc_mask; 1114 u_int32_t hashes[2] = { 0, 0 }; 1115 struct ifmultiaddr *ifma; 1116 1117 ifp = &sc->arpcom.ac_if; 1118 1119 /* Init our MAC address */ 1120 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1121 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1122 1123 /* If we want promiscuous mode, set the allframes bit. */ 1124 if (ifp->if_flags & IFF_PROMISC) 1125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1126 else 1127 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1128 1129 if (ifp->if_flags & IFF_ALLMULTI) 1130 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1131 else 1132 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1133 1134 /* first, zot all the existing hash bits */ 1135 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1136 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1137 1138 /* 1139 * If we're already in promisc or allmulti mode, we 1140 * don't have to bother programming the multicast filter. 1141 */ 1142 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1143 return; 1144 1145 /* now program new ones */ 1146 if (DC_IS_CENTAUR(sc)) 1147 crc_mask = dc_crc_mask(sc); 1148 else 1149 crc_mask = 0x3f; 1150 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1151 if (ifma->ifma_addr->sa_family != AF_LINK) 1152 continue; 1153 if (DC_IS_CENTAUR(sc)) { 1154 h = ether_crc32_le( 1155 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1156 ETHER_ADDR_LEN) & crc_mask; 1157 } else { 1158 h = ether_crc32_be( 1159 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1160 ETHER_ADDR_LEN); 1161 h = (h >> 26) & crc_mask; 1162 } 1163 if (h < 32) 1164 hashes[0] |= (1 << h); 1165 else 1166 hashes[1] |= (1 << (h - 32)); 1167 } 1168 1169 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1170 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1171 1172 return; 1173 } 1174 1175 void dc_setfilt_asix(sc) 1176 struct dc_softc *sc; 1177 { 1178 struct ifnet *ifp; 1179 int h = 0; 1180 u_int32_t hashes[2] = { 0, 0 }; 1181 struct ifmultiaddr *ifma; 1182 1183 ifp = &sc->arpcom.ac_if; 1184 1185 /* Init our MAC address */ 1186 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1187 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1188 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1189 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1190 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1191 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1192 1193 /* If we want promiscuous mode, set the allframes bit. */ 1194 if (ifp->if_flags & IFF_PROMISC) 1195 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1196 else 1197 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1198 1199 if (ifp->if_flags & IFF_ALLMULTI) 1200 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1201 else 1202 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1203 1204 /* 1205 * The ASIX chip has a special bit to enable reception 1206 * of broadcast frames. 1207 */ 1208 if (ifp->if_flags & IFF_BROADCAST) 1209 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1210 else 1211 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1212 1213 /* first, zot all the existing hash bits */ 1214 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1215 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1217 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1218 1219 /* 1220 * If we're already in promisc or allmulti mode, we 1221 * don't have to bother programming the multicast filter. 1222 */ 1223 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1224 return; 1225 1226 /* now program new ones */ 1227 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1228 if (ifma->ifma_addr->sa_family != AF_LINK) 1229 continue; 1230 h = ether_crc32_be( 1231 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1232 ETHER_ADDR_LEN); 1233 h = (h >> 26) & 0x3f; 1234 if (h < 32) 1235 hashes[0] |= (1 << h); 1236 else 1237 hashes[1] |= (1 << (h - 32)); 1238 } 1239 1240 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1241 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1242 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1243 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1244 1245 return; 1246 } 1247 1248 static void dc_setfilt(sc) 1249 struct dc_softc *sc; 1250 { 1251 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1252 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1253 dc_setfilt_21143(sc); 1254 1255 if (DC_IS_ASIX(sc)) 1256 dc_setfilt_asix(sc); 1257 1258 if (DC_IS_ADMTEK(sc)) 1259 dc_setfilt_admtek(sc); 1260 1261 return; 1262 } 1263 1264 /* 1265 * In order to fiddle with the 1266 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1267 * first have to put the transmit and/or receive logic in the idle state. 1268 */ 1269 static void dc_setcfg(sc, media) 1270 struct dc_softc *sc; 1271 int media; 1272 { 1273 int i, restart = 0; 1274 u_int32_t isr; 1275 1276 if (IFM_SUBTYPE(media) == IFM_NONE) 1277 return; 1278 1279 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1280 restart = 1; 1281 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1282 1283 for (i = 0; i < DC_TIMEOUT; i++) { 1284 isr = CSR_READ_4(sc, DC_ISR); 1285 if (isr & DC_ISR_TX_IDLE || 1286 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1287 break; 1288 DELAY(10); 1289 } 1290 1291 if (i == DC_TIMEOUT) { 1292 if_printf(&sc->arpcom.ac_if, 1293 "failed to force tx and rx to idle state\n"); 1294 } 1295 } 1296 1297 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1298 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1299 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1300 if (sc->dc_pmode == DC_PMODE_MII) { 1301 int watchdogreg; 1302 1303 if (DC_IS_INTEL(sc)) { 1304 /* there's a write enable bit here that reads as 1 */ 1305 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1306 watchdogreg &= ~DC_WDOG_CTLWREN; 1307 watchdogreg |= DC_WDOG_JABBERDIS; 1308 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1309 } else { 1310 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1311 } 1312 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1313 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1314 if (sc->dc_type == DC_TYPE_98713) 1315 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1316 DC_NETCFG_SCRAMBLER)); 1317 if (!DC_IS_DAVICOM(sc)) 1318 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1319 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1320 if (DC_IS_INTEL(sc)) 1321 dc_apply_fixup(sc, IFM_AUTO); 1322 } else { 1323 if (DC_IS_PNIC(sc)) { 1324 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1325 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1326 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1327 } 1328 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1331 if (DC_IS_INTEL(sc)) 1332 dc_apply_fixup(sc, 1333 (media & IFM_GMASK) == IFM_FDX ? 1334 IFM_100_TX|IFM_FDX : IFM_100_TX); 1335 } 1336 } 1337 1338 if (IFM_SUBTYPE(media) == IFM_10_T) { 1339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1340 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1341 if (sc->dc_pmode == DC_PMODE_MII) { 1342 int watchdogreg; 1343 1344 /* there's a write enable bit here that reads as 1 */ 1345 if (DC_IS_INTEL(sc)) { 1346 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1347 watchdogreg &= ~DC_WDOG_CTLWREN; 1348 watchdogreg |= DC_WDOG_JABBERDIS; 1349 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1350 } else { 1351 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1352 } 1353 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1354 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1355 if (sc->dc_type == DC_TYPE_98713) 1356 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1357 if (!DC_IS_DAVICOM(sc)) 1358 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1359 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1360 if (DC_IS_INTEL(sc)) 1361 dc_apply_fixup(sc, IFM_AUTO); 1362 } else { 1363 if (DC_IS_PNIC(sc)) { 1364 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1365 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1366 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1367 } 1368 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1369 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1370 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1371 if (DC_IS_INTEL(sc)) { 1372 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1373 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1374 if ((media & IFM_GMASK) == IFM_FDX) 1375 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1376 else 1377 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1378 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1379 DC_CLRBIT(sc, DC_10BTCTRL, 1380 DC_TCTL_AUTONEGENBL); 1381 dc_apply_fixup(sc, 1382 (media & IFM_GMASK) == IFM_FDX ? 1383 IFM_10_T|IFM_FDX : IFM_10_T); 1384 DELAY(20000); 1385 } 1386 } 1387 } 1388 1389 /* 1390 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1391 * PHY and we want HomePNA mode, set the portsel bit to turn 1392 * on the external MII port. 1393 */ 1394 if (DC_IS_DAVICOM(sc)) { 1395 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1396 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1397 sc->dc_link = 1; 1398 } else { 1399 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1400 } 1401 } 1402 1403 if ((media & IFM_GMASK) == IFM_FDX) { 1404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1405 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1406 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1407 } else { 1408 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1409 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1410 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1411 } 1412 1413 if (restart) 1414 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1415 1416 return; 1417 } 1418 1419 static void dc_reset(sc) 1420 struct dc_softc *sc; 1421 { 1422 int i; 1423 1424 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1425 1426 for (i = 0; i < DC_TIMEOUT; i++) { 1427 DELAY(10); 1428 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1429 break; 1430 } 1431 1432 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1433 DELAY(10000); 1434 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1435 i = 0; 1436 } 1437 1438 if (i == DC_TIMEOUT) 1439 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 1440 1441 /* Wait a little while for the chip to get its brains in order. */ 1442 DELAY(1000); 1443 1444 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1445 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1446 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1447 1448 /* 1449 * Bring the SIA out of reset. In some cases, it looks 1450 * like failing to unreset the SIA soon enough gets it 1451 * into a state where it will never come out of reset 1452 * until we reset the whole chip again. 1453 */ 1454 if (DC_IS_INTEL(sc)) { 1455 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1456 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1457 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1458 } 1459 1460 return; 1461 } 1462 1463 static struct dc_type *dc_devtype(dev) 1464 device_t dev; 1465 { 1466 struct dc_type *t; 1467 u_int32_t rev; 1468 1469 t = dc_devs; 1470 1471 while(t->dc_name != NULL) { 1472 if ((pci_get_vendor(dev) == t->dc_vid) && 1473 (pci_get_device(dev) == t->dc_did)) { 1474 /* Check the PCI revision */ 1475 rev = pci_get_revid(dev); 1476 if (t->dc_did == DC_DEVICEID_98713 && 1477 rev >= DC_REVISION_98713A) 1478 t++; 1479 if (t->dc_did == DC_DEVICEID_98713_CP && 1480 rev >= DC_REVISION_98713A) 1481 t++; 1482 if (t->dc_did == DC_DEVICEID_987x5 && 1483 rev >= DC_REVISION_98715AEC_C) 1484 t++; 1485 if (t->dc_did == DC_DEVICEID_987x5 && 1486 rev >= DC_REVISION_98725) 1487 t++; 1488 if (t->dc_did == DC_DEVICEID_AX88140A && 1489 rev >= DC_REVISION_88141) 1490 t++; 1491 if (t->dc_did == DC_DEVICEID_82C168 && 1492 rev >= DC_REVISION_82C169) 1493 t++; 1494 if (t->dc_did == DC_DEVICEID_DM9102 && 1495 rev >= DC_REVISION_DM9102A) 1496 t++; 1497 return(t); 1498 } 1499 t++; 1500 } 1501 1502 return(NULL); 1503 } 1504 1505 /* 1506 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1507 * IDs against our list and return a device name if we find a match. 1508 * We do a little bit of extra work to identify the exact type of 1509 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1510 * but different revision IDs. The same is true for 98715/98715A 1511 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1512 * cases, the exact chip revision affects driver behavior. 1513 */ 1514 static int dc_probe(dev) 1515 device_t dev; 1516 { 1517 struct dc_type *t; 1518 1519 t = dc_devtype(dev); 1520 1521 if (t != NULL) { 1522 device_set_desc(dev, t->dc_name); 1523 return(0); 1524 } 1525 1526 return(ENXIO); 1527 } 1528 1529 static void dc_acpi(dev) 1530 device_t dev; 1531 { 1532 u_int32_t r, cptr; 1533 1534 /* Find the location of the capabilities block */ 1535 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1536 1537 r = pci_read_config(dev, cptr, 4) & 0xFF; 1538 if (r == 0x01) { 1539 1540 r = pci_read_config(dev, cptr + 4, 4); 1541 if (r & DC_PSTATE_D3) { 1542 u_int32_t iobase, membase, irq; 1543 struct dc_softc *sc; 1544 1545 /* Save important PCI config data. */ 1546 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1547 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1548 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1549 1550 sc = device_get_softc(dev); 1551 /* Reset the power state. */ 1552 if_printf(&sc->arpcom.ac_if, 1553 "chip is in D%d power mode " 1554 "-- setting to D0\n", r & DC_PSTATE_D3); 1555 r &= 0xFFFFFFFC; 1556 pci_write_config(dev, cptr + 4, r, 4); 1557 1558 /* Restore PCI config data. */ 1559 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1560 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1561 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1562 } 1563 } 1564 } 1565 1566 static void dc_apply_fixup(sc, media) 1567 struct dc_softc *sc; 1568 int media; 1569 { 1570 struct dc_mediainfo *m; 1571 u_int8_t *p; 1572 int i; 1573 u_int32_t reg; 1574 1575 m = sc->dc_mi; 1576 1577 while (m != NULL) { 1578 if (m->dc_media == media) 1579 break; 1580 m = m->dc_next; 1581 } 1582 1583 if (m == NULL) 1584 return; 1585 1586 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1587 reg = (p[0] | (p[1] << 8)) << 16; 1588 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1589 } 1590 1591 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1592 reg = (p[0] | (p[1] << 8)) << 16; 1593 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1594 } 1595 1596 return; 1597 } 1598 1599 static void dc_decode_leaf_sia(sc, l) 1600 struct dc_softc *sc; 1601 struct dc_eblock_sia *l; 1602 { 1603 struct dc_mediainfo *m; 1604 1605 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1606 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){ 1607 case DC_SIA_CODE_10BT: 1608 m->dc_media = IFM_10_T; 1609 break; 1610 1611 case DC_SIA_CODE_10BT_FDX: 1612 m->dc_media = IFM_10_T|IFM_FDX; 1613 break; 1614 1615 case DC_SIA_CODE_10B2: 1616 m->dc_media = IFM_10_2; 1617 break; 1618 1619 case DC_SIA_CODE_10B5: 1620 m->dc_media = IFM_10_5; 1621 break; 1622 } 1623 if (l->dc_sia_code & DC_SIA_CODE_EXT){ 1624 m->dc_gp_len = 2; 1625 m->dc_gp_ptr = 1626 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1627 } else { 1628 m->dc_gp_len = 2; 1629 m->dc_gp_ptr = 1630 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1631 } 1632 1633 m->dc_next = sc->dc_mi; 1634 sc->dc_mi = m; 1635 1636 sc->dc_pmode = DC_PMODE_SIA; 1637 1638 return; 1639 } 1640 1641 static void dc_decode_leaf_sym(sc, l) 1642 struct dc_softc *sc; 1643 struct dc_eblock_sym *l; 1644 { 1645 struct dc_mediainfo *m; 1646 1647 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1648 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1649 m->dc_media = IFM_100_TX; 1650 1651 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1652 m->dc_media = IFM_100_TX|IFM_FDX; 1653 1654 m->dc_gp_len = 2; 1655 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1656 1657 m->dc_next = sc->dc_mi; 1658 sc->dc_mi = m; 1659 1660 sc->dc_pmode = DC_PMODE_SYM; 1661 1662 return; 1663 } 1664 1665 static void dc_decode_leaf_mii(sc, l) 1666 struct dc_softc *sc; 1667 struct dc_eblock_mii *l; 1668 { 1669 u_int8_t *p; 1670 struct dc_mediainfo *m; 1671 1672 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1673 /* We abuse IFM_AUTO to represent MII. */ 1674 m->dc_media = IFM_AUTO; 1675 m->dc_gp_len = l->dc_gpr_len; 1676 1677 p = (u_int8_t *)l; 1678 p += sizeof(struct dc_eblock_mii); 1679 m->dc_gp_ptr = p; 1680 p += 2 * l->dc_gpr_len; 1681 m->dc_reset_len = *p; 1682 p++; 1683 m->dc_reset_ptr = p; 1684 1685 m->dc_next = sc->dc_mi; 1686 sc->dc_mi = m; 1687 1688 return; 1689 } 1690 1691 static void dc_read_srom(sc, bits) 1692 struct dc_softc *sc; 1693 int bits; 1694 { 1695 int size; 1696 1697 size = 2 << bits; 1698 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT); 1699 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1700 } 1701 1702 static void dc_parse_21143_srom(sc) 1703 struct dc_softc *sc; 1704 { 1705 struct dc_leaf_hdr *lhdr; 1706 struct dc_eblock_hdr *hdr; 1707 int i, loff; 1708 char *ptr; 1709 int have_mii; 1710 1711 have_mii = 0; 1712 loff = sc->dc_srom[27]; 1713 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1714 1715 ptr = (char *)lhdr; 1716 ptr += sizeof(struct dc_leaf_hdr) - 1; 1717 /* 1718 * Look if we got a MII media block. 1719 */ 1720 for (i = 0; i < lhdr->dc_mcnt; i++) { 1721 hdr = (struct dc_eblock_hdr *)ptr; 1722 if (hdr->dc_type == DC_EBLOCK_MII) 1723 have_mii++; 1724 1725 ptr += (hdr->dc_len & 0x7F); 1726 ptr++; 1727 } 1728 1729 /* 1730 * Do the same thing again. Only use SIA and SYM media 1731 * blocks if no MII media block is available. 1732 */ 1733 ptr = (char *)lhdr; 1734 ptr += sizeof(struct dc_leaf_hdr) - 1; 1735 for (i = 0; i < lhdr->dc_mcnt; i++) { 1736 hdr = (struct dc_eblock_hdr *)ptr; 1737 switch(hdr->dc_type) { 1738 case DC_EBLOCK_MII: 1739 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1740 break; 1741 case DC_EBLOCK_SIA: 1742 if (! have_mii) 1743 dc_decode_leaf_sia(sc, 1744 (struct dc_eblock_sia *)hdr); 1745 break; 1746 case DC_EBLOCK_SYM: 1747 if (! have_mii) 1748 dc_decode_leaf_sym(sc, 1749 (struct dc_eblock_sym *)hdr); 1750 break; 1751 default: 1752 /* Don't care. Yet. */ 1753 break; 1754 } 1755 ptr += (hdr->dc_len & 0x7F); 1756 ptr++; 1757 } 1758 1759 return; 1760 } 1761 1762 /* 1763 * Attach the interface. Allocate softc structures, do ifmedia 1764 * setup and ethernet/BPF attach. 1765 */ 1766 static int dc_attach(dev) 1767 device_t dev; 1768 { 1769 int tmp = 0; 1770 u_char eaddr[ETHER_ADDR_LEN]; 1771 u_int32_t command; 1772 struct dc_softc *sc; 1773 struct ifnet *ifp; 1774 u_int32_t revision; 1775 int error = 0, rid, mac_offset; 1776 1777 sc = device_get_softc(dev); 1778 callout_init(&sc->dc_stat_timer); 1779 1780 ifp = &sc->arpcom.ac_if; 1781 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1782 1783 /* 1784 * Handle power management nonsense. 1785 */ 1786 dc_acpi(dev); 1787 1788 /* 1789 * Map control/status registers. 1790 */ 1791 pci_enable_busmaster(dev); 1792 1793 rid = DC_RID; 1794 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1795 1796 if (sc->dc_res == NULL) { 1797 device_printf(dev, "couldn't map ports/memory\n"); 1798 error = ENXIO; 1799 goto fail; 1800 } 1801 1802 sc->dc_btag = rman_get_bustag(sc->dc_res); 1803 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1804 1805 /* Allocate interrupt */ 1806 rid = 0; 1807 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1808 RF_SHAREABLE | RF_ACTIVE); 1809 1810 if (sc->dc_irq == NULL) { 1811 device_printf(dev, "couldn't map interrupt\n"); 1812 error = ENXIO; 1813 goto fail; 1814 } 1815 1816 /* Need this info to decide on a chip type. */ 1817 sc->dc_info = dc_devtype(dev); 1818 revision = pci_get_revid(dev); 1819 1820 /* Get the eeprom width, but PNIC has diff eeprom */ 1821 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1822 dc_eeprom_width(sc); 1823 1824 switch(sc->dc_info->dc_did) { 1825 case DC_DEVICEID_21143: 1826 sc->dc_type = DC_TYPE_21143; 1827 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1828 sc->dc_flags |= DC_REDUCED_MII_POLL; 1829 /* Save EEPROM contents so we can parse them later. */ 1830 dc_read_srom(sc, sc->dc_romwidth); 1831 break; 1832 case DC_DEVICEID_DM9009: 1833 case DC_DEVICEID_DM9100: 1834 case DC_DEVICEID_DM9102: 1835 sc->dc_type = DC_TYPE_DM9102; 1836 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1837 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1838 sc->dc_flags |= DC_TX_ALIGN; 1839 sc->dc_pmode = DC_PMODE_MII; 1840 /* Increase the latency timer value. */ 1841 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1842 command &= 0xFFFF00FF; 1843 command |= 0x00008000; 1844 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1845 break; 1846 case DC_DEVICEID_AL981: 1847 sc->dc_type = DC_TYPE_AL981; 1848 sc->dc_flags |= DC_TX_USE_TX_INTR; 1849 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1850 sc->dc_pmode = DC_PMODE_MII; 1851 dc_read_srom(sc, sc->dc_romwidth); 1852 break; 1853 case DC_DEVICEID_AN985: 1854 case DC_DEVICEID_EN2242: 1855 case DC_DEVICEID_3CSOHOB: 1856 sc->dc_type = DC_TYPE_AN985; 1857 sc->dc_flags |= DC_64BIT_HASH; 1858 sc->dc_flags |= DC_TX_USE_TX_INTR; 1859 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1860 sc->dc_pmode = DC_PMODE_MII; 1861 1862 break; 1863 case DC_DEVICEID_98713: 1864 case DC_DEVICEID_98713_CP: 1865 if (revision < DC_REVISION_98713A) { 1866 sc->dc_type = DC_TYPE_98713; 1867 } 1868 if (revision >= DC_REVISION_98713A) { 1869 sc->dc_type = DC_TYPE_98713A; 1870 sc->dc_flags |= DC_21143_NWAY; 1871 } 1872 sc->dc_flags |= DC_REDUCED_MII_POLL; 1873 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1874 break; 1875 case DC_DEVICEID_987x5: 1876 case DC_DEVICEID_EN1217: 1877 /* 1878 * Macronix MX98715AEC-C/D/E parts have only a 1879 * 128-bit hash table. We need to deal with these 1880 * in the same manner as the PNIC II so that we 1881 * get the right number of bits out of the 1882 * CRC routine. 1883 */ 1884 if (revision >= DC_REVISION_98715AEC_C && 1885 revision < DC_REVISION_98725) 1886 sc->dc_flags |= DC_128BIT_HASH; 1887 sc->dc_type = DC_TYPE_987x5; 1888 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1889 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1890 break; 1891 case DC_DEVICEID_98727: 1892 sc->dc_type = DC_TYPE_987x5; 1893 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1894 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1895 break; 1896 case DC_DEVICEID_82C115: 1897 sc->dc_type = DC_TYPE_PNICII; 1898 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1899 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1900 break; 1901 case DC_DEVICEID_82C168: 1902 sc->dc_type = DC_TYPE_PNIC; 1903 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1904 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1905 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1906 if (revision < DC_REVISION_82C169) 1907 sc->dc_pmode = DC_PMODE_SYM; 1908 break; 1909 case DC_DEVICEID_AX88140A: 1910 sc->dc_type = DC_TYPE_ASIX; 1911 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1912 sc->dc_flags |= DC_REDUCED_MII_POLL; 1913 sc->dc_pmode = DC_PMODE_MII; 1914 break; 1915 case DC_DEVICEID_RS7112: 1916 sc->dc_type = DC_TYPE_CONEXANT; 1917 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1918 sc->dc_flags |= DC_REDUCED_MII_POLL; 1919 sc->dc_pmode = DC_PMODE_MII; 1920 dc_read_srom(sc, sc->dc_romwidth); 1921 break; 1922 default: 1923 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 1924 break; 1925 } 1926 1927 /* Save the cache line size. */ 1928 if (DC_IS_DAVICOM(sc)) 1929 sc->dc_cachesize = 0; 1930 else 1931 sc->dc_cachesize = pci_read_config(dev, 1932 DC_PCI_CFLT, 4) & 0xFF; 1933 1934 /* Reset the adapter. */ 1935 dc_reset(sc); 1936 1937 /* Take 21143 out of snooze mode */ 1938 if (DC_IS_INTEL(sc)) { 1939 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1940 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1941 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1942 } 1943 1944 /* 1945 * Try to learn something about the supported media. 1946 * We know that ASIX and ADMtek and Davicom devices 1947 * will *always* be using MII media, so that's a no-brainer. 1948 * The tricky ones are the Macronix/PNIC II and the 1949 * Intel 21143. 1950 */ 1951 if (DC_IS_INTEL(sc)) 1952 dc_parse_21143_srom(sc); 1953 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1954 if (sc->dc_type == DC_TYPE_98713) 1955 sc->dc_pmode = DC_PMODE_MII; 1956 else 1957 sc->dc_pmode = DC_PMODE_SYM; 1958 } else if (!sc->dc_pmode) 1959 sc->dc_pmode = DC_PMODE_MII; 1960 1961 /* 1962 * Get station address from the EEPROM. 1963 */ 1964 switch(sc->dc_type) { 1965 case DC_TYPE_98713: 1966 case DC_TYPE_98713A: 1967 case DC_TYPE_987x5: 1968 case DC_TYPE_PNICII: 1969 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1970 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1971 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1972 break; 1973 case DC_TYPE_PNIC: 1974 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1975 break; 1976 case DC_TYPE_DM9102: 1977 case DC_TYPE_21143: 1978 case DC_TYPE_ASIX: 1979 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1980 break; 1981 case DC_TYPE_AL981: 1982 case DC_TYPE_AN985: 1983 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0); 1984 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1); 1985 break; 1986 case DC_TYPE_CONEXANT: 1987 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 1988 break; 1989 default: 1990 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1991 break; 1992 } 1993 1994 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1995 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1996 1997 if (sc->dc_ldata == NULL) { 1998 device_printf(dev, "no memory for list buffers!\n"); 1999 error = ENXIO; 2000 goto fail; 2001 } 2002 2003 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2004 2005 ifp->if_softc = sc; 2006 ifp->if_mtu = ETHERMTU; 2007 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2008 ifp->if_ioctl = dc_ioctl; 2009 ifp->if_start = dc_start; 2010 #ifdef DEVICE_POLLING 2011 ifp->if_poll = dc_poll; 2012 #endif 2013 ifp->if_watchdog = dc_watchdog; 2014 ifp->if_init = dc_init; 2015 ifp->if_baudrate = 10000000; 2016 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2017 ifq_set_ready(&ifp->if_snd); 2018 2019 /* 2020 * Do MII setup. If this is a 21143, check for a PHY on the 2021 * MII bus after applying any necessary fixups to twiddle the 2022 * GPIO bits. If we don't end up finding a PHY, restore the 2023 * old selection (SIA only or SIA/SYM) and attach the dcphy 2024 * driver instead. 2025 */ 2026 if (DC_IS_INTEL(sc)) { 2027 dc_apply_fixup(sc, IFM_AUTO); 2028 tmp = sc->dc_pmode; 2029 sc->dc_pmode = DC_PMODE_MII; 2030 } 2031 2032 error = mii_phy_probe(dev, &sc->dc_miibus, 2033 dc_ifmedia_upd, dc_ifmedia_sts); 2034 2035 if (error && DC_IS_INTEL(sc)) { 2036 sc->dc_pmode = tmp; 2037 if (sc->dc_pmode != DC_PMODE_SIA) 2038 sc->dc_pmode = DC_PMODE_SYM; 2039 sc->dc_flags |= DC_21143_NWAY; 2040 mii_phy_probe(dev, &sc->dc_miibus, 2041 dc_ifmedia_upd, dc_ifmedia_sts); 2042 /* 2043 * For non-MII cards, we need to have the 21143 2044 * drive the LEDs. Except there are some systems 2045 * like the NEC VersaPro NoteBook PC which have no 2046 * LEDs, and twiddling these bits has adverse effects 2047 * on them. (I.e. you suddenly can't get a link.) 2048 */ 2049 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2050 sc->dc_flags |= DC_TULIP_LEDS; 2051 error = 0; 2052 } 2053 2054 if (error) { 2055 device_printf(dev, "MII without any PHY!\n"); 2056 error = ENXIO; 2057 goto fail; 2058 } 2059 2060 /* 2061 * Call MI attach routine. 2062 */ 2063 ether_ifattach(ifp, eaddr); 2064 2065 if (DC_IS_ADMTEK(sc)) { 2066 /* 2067 * Set automatic TX underrun recovery for the ADMtek chips 2068 */ 2069 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2070 } 2071 2072 /* 2073 * Tell the upper layer(s) we support long frames. 2074 */ 2075 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2076 2077 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 2078 dc_intr, sc, &sc->dc_intrhand, NULL); 2079 if (error) { 2080 ether_ifdetach(ifp); 2081 device_printf(dev, "couldn't set up irq\n"); 2082 goto fail; 2083 } 2084 2085 return(0); 2086 2087 fail: 2088 dc_detach(dev); 2089 return(error); 2090 } 2091 2092 static int dc_detach(dev) 2093 device_t dev; 2094 { 2095 struct dc_softc *sc = device_get_softc(dev); 2096 struct ifnet *ifp = &sc->arpcom.ac_if; 2097 struct dc_mediainfo *m; 2098 2099 crit_enter(); 2100 2101 if (device_is_attached(dev)) { 2102 dc_stop(sc); 2103 ether_ifdetach(ifp); 2104 } 2105 2106 if (sc->dc_miibus) 2107 device_delete_child(dev, sc->dc_miibus); 2108 bus_generic_detach(dev); 2109 2110 if (sc->dc_intrhand) 2111 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2112 2113 crit_exit(); 2114 2115 if (sc->dc_irq) 2116 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2117 if (sc->dc_res) 2118 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2119 2120 if (sc->dc_ldata) 2121 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2122 if (sc->dc_pnic_rx_buf != NULL) 2123 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2124 2125 while(sc->dc_mi != NULL) { 2126 m = sc->dc_mi->dc_next; 2127 free(sc->dc_mi, M_DEVBUF); 2128 sc->dc_mi = m; 2129 } 2130 2131 if (sc->dc_srom) 2132 free(sc->dc_srom, M_DEVBUF); 2133 2134 return(0); 2135 } 2136 2137 /* 2138 * Initialize the transmit descriptors. 2139 */ 2140 static int dc_list_tx_init(sc) 2141 struct dc_softc *sc; 2142 { 2143 struct dc_chain_data *cd; 2144 struct dc_list_data *ld; 2145 int i; 2146 2147 cd = &sc->dc_cdata; 2148 ld = sc->dc_ldata; 2149 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2150 if (i == (DC_TX_LIST_CNT - 1)) { 2151 ld->dc_tx_list[i].dc_next = 2152 vtophys(&ld->dc_tx_list[0]); 2153 } else { 2154 ld->dc_tx_list[i].dc_next = 2155 vtophys(&ld->dc_tx_list[i + 1]); 2156 } 2157 cd->dc_tx_chain[i] = NULL; 2158 ld->dc_tx_list[i].dc_data = 0; 2159 ld->dc_tx_list[i].dc_ctl = 0; 2160 } 2161 2162 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2163 2164 return(0); 2165 } 2166 2167 2168 /* 2169 * Initialize the RX descriptors and allocate mbufs for them. Note that 2170 * we arrange the descriptors in a closed ring, so that the last descriptor 2171 * points back to the first. 2172 */ 2173 static int dc_list_rx_init(sc) 2174 struct dc_softc *sc; 2175 { 2176 struct dc_chain_data *cd; 2177 struct dc_list_data *ld; 2178 int i; 2179 2180 cd = &sc->dc_cdata; 2181 ld = sc->dc_ldata; 2182 2183 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2184 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2185 return(ENOBUFS); 2186 if (i == (DC_RX_LIST_CNT - 1)) { 2187 ld->dc_rx_list[i].dc_next = 2188 vtophys(&ld->dc_rx_list[0]); 2189 } else { 2190 ld->dc_rx_list[i].dc_next = 2191 vtophys(&ld->dc_rx_list[i + 1]); 2192 } 2193 } 2194 2195 cd->dc_rx_prod = 0; 2196 2197 return(0); 2198 } 2199 2200 /* 2201 * Initialize an RX descriptor and attach an MBUF cluster. 2202 */ 2203 static int dc_newbuf(sc, i, m) 2204 struct dc_softc *sc; 2205 int i; 2206 struct mbuf *m; 2207 { 2208 struct mbuf *m_new = NULL; 2209 struct dc_desc *c; 2210 2211 c = &sc->dc_ldata->dc_rx_list[i]; 2212 2213 if (m == NULL) { 2214 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2215 if (m_new == NULL) 2216 return (ENOBUFS); 2217 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2218 } else { 2219 m_new = m; 2220 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2221 m_new->m_data = m_new->m_ext.ext_buf; 2222 } 2223 2224 m_adj(m_new, sizeof(u_int64_t)); 2225 2226 /* 2227 * If this is a PNIC chip, zero the buffer. This is part 2228 * of the workaround for the receive bug in the 82c168 and 2229 * 82c169 chips. 2230 */ 2231 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2232 bzero((char *)mtod(m_new, char *), m_new->m_len); 2233 2234 sc->dc_cdata.dc_rx_chain[i] = m_new; 2235 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2236 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2237 c->dc_status = DC_RXSTAT_OWN; 2238 2239 return(0); 2240 } 2241 2242 /* 2243 * Grrrrr. 2244 * The PNIC chip has a terrible bug in it that manifests itself during 2245 * periods of heavy activity. The exact mode of failure if difficult to 2246 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2247 * will happen on slow machines. The bug is that sometimes instead of 2248 * uploading one complete frame during reception, it uploads what looks 2249 * like the entire contents of its FIFO memory. The frame we want is at 2250 * the end of the whole mess, but we never know exactly how much data has 2251 * been uploaded, so salvaging the frame is hard. 2252 * 2253 * There is only one way to do it reliably, and it's disgusting. 2254 * Here's what we know: 2255 * 2256 * - We know there will always be somewhere between one and three extra 2257 * descriptors uploaded. 2258 * 2259 * - We know the desired received frame will always be at the end of the 2260 * total data upload. 2261 * 2262 * - We know the size of the desired received frame because it will be 2263 * provided in the length field of the status word in the last descriptor. 2264 * 2265 * Here's what we do: 2266 * 2267 * - When we allocate buffers for the receive ring, we bzero() them. 2268 * This means that we know that the buffer contents should be all 2269 * zeros, except for data uploaded by the chip. 2270 * 2271 * - We also force the PNIC chip to upload frames that include the 2272 * ethernet CRC at the end. 2273 * 2274 * - We gather all of the bogus frame data into a single buffer. 2275 * 2276 * - We then position a pointer at the end of this buffer and scan 2277 * backwards until we encounter the first non-zero byte of data. 2278 * This is the end of the received frame. We know we will encounter 2279 * some data at the end of the frame because the CRC will always be 2280 * there, so even if the sender transmits a packet of all zeros, 2281 * we won't be fooled. 2282 * 2283 * - We know the size of the actual received frame, so we subtract 2284 * that value from the current pointer location. This brings us 2285 * to the start of the actual received packet. 2286 * 2287 * - We copy this into an mbuf and pass it on, along with the actual 2288 * frame length. 2289 * 2290 * The performance hit is tremendous, but it beats dropping frames all 2291 * the time. 2292 */ 2293 2294 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2295 static void dc_pnic_rx_bug_war(sc, idx) 2296 struct dc_softc *sc; 2297 int idx; 2298 { 2299 struct dc_desc *cur_rx; 2300 struct dc_desc *c = NULL; 2301 struct mbuf *m = NULL; 2302 unsigned char *ptr; 2303 int i, total_len; 2304 u_int32_t rxstat = 0; 2305 2306 i = sc->dc_pnic_rx_bug_save; 2307 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2308 ptr = sc->dc_pnic_rx_buf; 2309 bzero(ptr, DC_RXLEN * 5); 2310 2311 /* Copy all the bytes from the bogus buffers. */ 2312 while (1) { 2313 c = &sc->dc_ldata->dc_rx_list[i]; 2314 rxstat = c->dc_status; 2315 m = sc->dc_cdata.dc_rx_chain[i]; 2316 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2317 ptr += DC_RXLEN; 2318 /* If this is the last buffer, break out. */ 2319 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2320 break; 2321 dc_newbuf(sc, i, m); 2322 DC_INC(i, DC_RX_LIST_CNT); 2323 } 2324 2325 /* Find the length of the actual receive frame. */ 2326 total_len = DC_RXBYTES(rxstat); 2327 2328 /* Scan backwards until we hit a non-zero byte. */ 2329 while(*ptr == 0x00) 2330 ptr--; 2331 2332 /* Round off. */ 2333 if ((uintptr_t)(ptr) & 0x3) 2334 ptr -= 1; 2335 2336 /* Now find the start of the frame. */ 2337 ptr -= total_len; 2338 if (ptr < sc->dc_pnic_rx_buf) 2339 ptr = sc->dc_pnic_rx_buf; 2340 2341 /* 2342 * Now copy the salvaged frame to the last mbuf and fake up 2343 * the status word to make it look like a successful 2344 * frame reception. 2345 */ 2346 dc_newbuf(sc, i, m); 2347 bcopy(ptr, mtod(m, char *), total_len); 2348 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2349 2350 return; 2351 } 2352 2353 /* 2354 * This routine searches the RX ring for dirty descriptors in the 2355 * event that the rxeof routine falls out of sync with the chip's 2356 * current descriptor pointer. This may happen sometimes as a result 2357 * of a "no RX buffer available" condition that happens when the chip 2358 * consumes all of the RX buffers before the driver has a chance to 2359 * process the RX ring. This routine may need to be called more than 2360 * once to bring the driver back in sync with the chip, however we 2361 * should still be getting RX DONE interrupts to drive the search 2362 * for new packets in the RX ring, so we should catch up eventually. 2363 */ 2364 static int dc_rx_resync(sc) 2365 struct dc_softc *sc; 2366 { 2367 int i, pos; 2368 struct dc_desc *cur_rx; 2369 2370 pos = sc->dc_cdata.dc_rx_prod; 2371 2372 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2373 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2374 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2375 break; 2376 DC_INC(pos, DC_RX_LIST_CNT); 2377 } 2378 2379 /* If the ring really is empty, then just return. */ 2380 if (i == DC_RX_LIST_CNT) 2381 return(0); 2382 2383 /* We've fallen behing the chip: catch it. */ 2384 sc->dc_cdata.dc_rx_prod = pos; 2385 2386 return(EAGAIN); 2387 } 2388 2389 /* 2390 * A frame has been uploaded: pass the resulting mbuf chain up to 2391 * the higher level protocols. 2392 */ 2393 static void dc_rxeof(sc) 2394 struct dc_softc *sc; 2395 { 2396 struct mbuf *m; 2397 struct ifnet *ifp; 2398 struct dc_desc *cur_rx; 2399 int i, total_len = 0; 2400 u_int32_t rxstat; 2401 2402 ifp = &sc->arpcom.ac_if; 2403 i = sc->dc_cdata.dc_rx_prod; 2404 2405 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2406 2407 #ifdef DEVICE_POLLING 2408 if (ifp->if_flags & IFF_POLLING) { 2409 if (sc->rxcycles <= 0) 2410 break; 2411 sc->rxcycles--; 2412 } 2413 #endif /* DEVICE_POLLING */ 2414 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2415 rxstat = cur_rx->dc_status; 2416 m = sc->dc_cdata.dc_rx_chain[i]; 2417 total_len = DC_RXBYTES(rxstat); 2418 2419 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2420 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2421 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2422 sc->dc_pnic_rx_bug_save = i; 2423 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2424 DC_INC(i, DC_RX_LIST_CNT); 2425 continue; 2426 } 2427 dc_pnic_rx_bug_war(sc, i); 2428 rxstat = cur_rx->dc_status; 2429 total_len = DC_RXBYTES(rxstat); 2430 } 2431 } 2432 2433 sc->dc_cdata.dc_rx_chain[i] = NULL; 2434 2435 /* 2436 * If an error occurs, update stats, clear the 2437 * status word and leave the mbuf cluster in place: 2438 * it should simply get re-used next time this descriptor 2439 * comes up in the ring. However, don't report long 2440 * frames as errors since they could be vlans 2441 */ 2442 if ((rxstat & DC_RXSTAT_RXERR)){ 2443 if (!(rxstat & DC_RXSTAT_GIANT) || 2444 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2445 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2446 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2447 ifp->if_ierrors++; 2448 if (rxstat & DC_RXSTAT_COLLSEEN) 2449 ifp->if_collisions++; 2450 dc_newbuf(sc, i, m); 2451 if (rxstat & DC_RXSTAT_CRCERR) { 2452 DC_INC(i, DC_RX_LIST_CNT); 2453 continue; 2454 } else { 2455 dc_init(sc); 2456 return; 2457 } 2458 } 2459 } 2460 2461 /* No errors; receive the packet. */ 2462 total_len -= ETHER_CRC_LEN; 2463 2464 #ifdef __i386__ 2465 /* 2466 * On the x86 we do not have alignment problems, so try to 2467 * allocate a new buffer for the receive ring, and pass up 2468 * the one where the packet is already, saving the expensive 2469 * copy done in m_devget(). 2470 * If we are on an architecture with alignment problems, or 2471 * if the allocation fails, then use m_devget and leave the 2472 * existing buffer in the receive ring. 2473 */ 2474 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2475 m->m_pkthdr.rcvif = ifp; 2476 m->m_pkthdr.len = m->m_len = total_len; 2477 DC_INC(i, DC_RX_LIST_CNT); 2478 } else 2479 #endif 2480 { 2481 struct mbuf *m0; 2482 2483 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2484 total_len + ETHER_ALIGN, 0, ifp, NULL); 2485 dc_newbuf(sc, i, m); 2486 DC_INC(i, DC_RX_LIST_CNT); 2487 if (m0 == NULL) { 2488 ifp->if_ierrors++; 2489 continue; 2490 } 2491 m_adj(m0, ETHER_ALIGN); 2492 m = m0; 2493 } 2494 2495 ifp->if_ipackets++; 2496 (*ifp->if_input)(ifp, m); 2497 } 2498 2499 sc->dc_cdata.dc_rx_prod = i; 2500 } 2501 2502 /* 2503 * A frame was downloaded to the chip. It's safe for us to clean up 2504 * the list buffers. 2505 */ 2506 2507 static void 2508 dc_txeof(sc) 2509 struct dc_softc *sc; 2510 { 2511 struct dc_desc *cur_tx = NULL; 2512 struct ifnet *ifp; 2513 int idx; 2514 2515 ifp = &sc->arpcom.ac_if; 2516 2517 /* 2518 * Go through our tx list and free mbufs for those 2519 * frames that have been transmitted. 2520 */ 2521 idx = sc->dc_cdata.dc_tx_cons; 2522 while(idx != sc->dc_cdata.dc_tx_prod) { 2523 u_int32_t txstat; 2524 2525 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2526 txstat = cur_tx->dc_status; 2527 2528 if (txstat & DC_TXSTAT_OWN) 2529 break; 2530 2531 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2532 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2533 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2534 /* 2535 * Yes, the PNIC is so brain damaged 2536 * that it will sometimes generate a TX 2537 * underrun error while DMAing the RX 2538 * filter setup frame. If we detect this, 2539 * we have to send the setup frame again, 2540 * or else the filter won't be programmed 2541 * correctly. 2542 */ 2543 if (DC_IS_PNIC(sc)) { 2544 if (txstat & DC_TXSTAT_ERRSUM) 2545 dc_setfilt(sc); 2546 } 2547 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2548 } 2549 sc->dc_cdata.dc_tx_cnt--; 2550 DC_INC(idx, DC_TX_LIST_CNT); 2551 continue; 2552 } 2553 2554 if (DC_IS_CONEXANT(sc)) { 2555 /* 2556 * For some reason Conexant chips like 2557 * setting the CARRLOST flag even when 2558 * the carrier is there. In CURRENT we 2559 * have the same problem for Xircom 2560 * cards ! 2561 */ 2562 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2563 sc->dc_pmode == DC_PMODE_MII && 2564 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2565 DC_TXSTAT_NOCARRIER))) 2566 txstat &= ~DC_TXSTAT_ERRSUM; 2567 } else { 2568 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2569 sc->dc_pmode == DC_PMODE_MII && 2570 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2571 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2572 txstat &= ~DC_TXSTAT_ERRSUM; 2573 } 2574 2575 if (txstat & DC_TXSTAT_ERRSUM) { 2576 ifp->if_oerrors++; 2577 if (txstat & DC_TXSTAT_EXCESSCOLL) 2578 ifp->if_collisions++; 2579 if (txstat & DC_TXSTAT_LATECOLL) 2580 ifp->if_collisions++; 2581 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2582 dc_init(sc); 2583 return; 2584 } 2585 } 2586 2587 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2588 2589 ifp->if_opackets++; 2590 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2591 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2592 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2593 } 2594 2595 sc->dc_cdata.dc_tx_cnt--; 2596 DC_INC(idx, DC_TX_LIST_CNT); 2597 } 2598 2599 if (idx != sc->dc_cdata.dc_tx_cons) { 2600 /* some buffers have been freed */ 2601 sc->dc_cdata.dc_tx_cons = idx; 2602 ifp->if_flags &= ~IFF_OACTIVE; 2603 } 2604 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2605 2606 return; 2607 } 2608 2609 static void dc_tick(xsc) 2610 void *xsc; 2611 { 2612 struct dc_softc *sc = xsc; 2613 struct ifnet *ifp = &sc->arpcom.ac_if; 2614 struct mii_data *mii; 2615 u_int32_t r; 2616 2617 crit_enter(); 2618 2619 mii = device_get_softc(sc->dc_miibus); 2620 2621 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2622 if (sc->dc_flags & DC_21143_NWAY) { 2623 r = CSR_READ_4(sc, DC_10BTSTAT); 2624 if (IFM_SUBTYPE(mii->mii_media_active) == 2625 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2626 sc->dc_link = 0; 2627 mii_mediachg(mii); 2628 } 2629 if (IFM_SUBTYPE(mii->mii_media_active) == 2630 IFM_10_T && (r & DC_TSTAT_LS10)) { 2631 sc->dc_link = 0; 2632 mii_mediachg(mii); 2633 } 2634 if (sc->dc_link == 0) 2635 mii_tick(mii); 2636 } else { 2637 r = CSR_READ_4(sc, DC_ISR); 2638 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2639 sc->dc_cdata.dc_tx_cnt == 0) 2640 mii_tick(mii); 2641 if (!(mii->mii_media_status & IFM_ACTIVE)) 2642 sc->dc_link = 0; 2643 } 2644 } else 2645 mii_tick(mii); 2646 2647 /* 2648 * When the init routine completes, we expect to be able to send 2649 * packets right away, and in fact the network code will send a 2650 * gratuitous ARP the moment the init routine marks the interface 2651 * as running. However, even though the MAC may have been initialized, 2652 * there may be a delay of a few seconds before the PHY completes 2653 * autonegotiation and the link is brought up. Any transmissions 2654 * made during that delay will be lost. Dealing with this is tricky: 2655 * we can't just pause in the init routine while waiting for the 2656 * PHY to come ready since that would bring the whole system to 2657 * a screeching halt for several seconds. 2658 * 2659 * What we do here is prevent the TX start routine from sending 2660 * any packets until a link has been established. After the 2661 * interface has been initialized, the tick routine will poll 2662 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2663 * that time, packets will stay in the send queue, and once the 2664 * link comes up, they will be flushed out to the wire. 2665 */ 2666 if (!sc->dc_link) { 2667 mii_pollstat(mii); 2668 if (mii->mii_media_status & IFM_ACTIVE && 2669 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2670 sc->dc_link++; 2671 if (!ifq_is_empty(&ifp->if_snd)) 2672 dc_start(ifp); 2673 } 2674 } 2675 2676 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2677 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2678 else 2679 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2680 2681 crit_exit(); 2682 } 2683 2684 /* 2685 * A transmit underrun has occurred. Back off the transmit threshold, 2686 * or switch to store and forward mode if we have to. 2687 */ 2688 static void dc_tx_underrun(sc) 2689 struct dc_softc *sc; 2690 { 2691 u_int32_t isr; 2692 int i; 2693 2694 if (DC_IS_DAVICOM(sc)) 2695 dc_init(sc); 2696 2697 if (DC_IS_INTEL(sc)) { 2698 /* 2699 * The real 21143 requires that the transmitter be idle 2700 * in order to change the transmit threshold or store 2701 * and forward state. 2702 */ 2703 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2704 2705 for (i = 0; i < DC_TIMEOUT; i++) { 2706 isr = CSR_READ_4(sc, DC_ISR); 2707 if (isr & DC_ISR_TX_IDLE) 2708 break; 2709 DELAY(10); 2710 } 2711 if (i == DC_TIMEOUT) { 2712 if_printf(&sc->arpcom.ac_if, 2713 "failed to force tx to idle state\n"); 2714 dc_init(sc); 2715 } 2716 } 2717 2718 if_printf(&sc->arpcom.ac_if, "TX underrun -- "); 2719 sc->dc_txthresh += DC_TXTHRESH_INC; 2720 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2721 printf("using store and forward mode\n"); 2722 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2723 } else { 2724 printf("increasing TX threshold\n"); 2725 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2726 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2727 } 2728 2729 if (DC_IS_INTEL(sc)) 2730 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2731 2732 return; 2733 } 2734 2735 #ifdef DEVICE_POLLING 2736 2737 static void 2738 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2739 { 2740 struct dc_softc *sc = ifp->if_softc; 2741 u_int32_t status; 2742 2743 switch(cmd) { 2744 case POLL_REGISTER: 2745 /* Disable interrupts */ 2746 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2747 break; 2748 case POLL_DEREGISTER: 2749 /* Re-enable interrupts. */ 2750 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2751 break; 2752 case POLL_ONLY: 2753 sc->rxcycles = count; 2754 dc_rxeof(sc); 2755 dc_txeof(sc); 2756 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2757 dc_start(ifp); 2758 break; 2759 case POLL_AND_CHECK_STATUS: 2760 sc->rxcycles = count; 2761 dc_rxeof(sc); 2762 dc_txeof(sc); 2763 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2764 dc_start(ifp); 2765 status = CSR_READ_4(sc, DC_ISR); 2766 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2767 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2768 DC_ISR_BUS_ERR); 2769 if (!status) 2770 break; 2771 /* ack what we have */ 2772 CSR_WRITE_4(sc, DC_ISR, status); 2773 2774 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2775 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2776 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2777 2778 if (dc_rx_resync(sc)) 2779 dc_rxeof(sc); 2780 } 2781 /* restart transmit unit if necessary */ 2782 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2783 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2784 2785 if (status & DC_ISR_TX_UNDERRUN) 2786 dc_tx_underrun(sc); 2787 2788 if (status & DC_ISR_BUS_ERR) { 2789 if_printf(ifp, "dc_poll: bus error\n"); 2790 dc_reset(sc); 2791 dc_init(sc); 2792 } 2793 break; 2794 } 2795 } 2796 #endif /* DEVICE_POLLING */ 2797 2798 static void dc_intr(arg) 2799 void *arg; 2800 { 2801 struct dc_softc *sc; 2802 struct ifnet *ifp; 2803 u_int32_t status; 2804 2805 sc = arg; 2806 2807 if (sc->suspended) { 2808 return; 2809 } 2810 2811 ifp = &sc->arpcom.ac_if; 2812 2813 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2814 return ; 2815 2816 /* Suppress unwanted interrupts */ 2817 if (!(ifp->if_flags & IFF_UP)) { 2818 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2819 dc_stop(sc); 2820 return; 2821 } 2822 2823 /* Disable interrupts. */ 2824 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2825 2826 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2827 2828 CSR_WRITE_4(sc, DC_ISR, status); 2829 2830 if (status & DC_ISR_RX_OK) { 2831 int curpkts; 2832 curpkts = ifp->if_ipackets; 2833 dc_rxeof(sc); 2834 if (curpkts == ifp->if_ipackets) { 2835 while(dc_rx_resync(sc)) 2836 dc_rxeof(sc); 2837 } 2838 } 2839 2840 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2841 dc_txeof(sc); 2842 2843 if (status & DC_ISR_TX_IDLE) { 2844 dc_txeof(sc); 2845 if (sc->dc_cdata.dc_tx_cnt) { 2846 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2847 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2848 } 2849 } 2850 2851 if (status & DC_ISR_TX_UNDERRUN) 2852 dc_tx_underrun(sc); 2853 2854 if ((status & DC_ISR_RX_WATDOGTIMEO) 2855 || (status & DC_ISR_RX_NOBUF)) { 2856 int curpkts; 2857 curpkts = ifp->if_ipackets; 2858 dc_rxeof(sc); 2859 if (curpkts == ifp->if_ipackets) { 2860 while(dc_rx_resync(sc)) 2861 dc_rxeof(sc); 2862 } 2863 } 2864 2865 if (status & DC_ISR_BUS_ERR) { 2866 dc_reset(sc); 2867 dc_init(sc); 2868 } 2869 } 2870 2871 /* Re-enable interrupts. */ 2872 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2873 2874 if (!ifq_is_empty(&ifp->if_snd)) 2875 dc_start(ifp); 2876 2877 return; 2878 } 2879 2880 /* 2881 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2882 * pointers to the fragment pointers. 2883 */ 2884 static int dc_encap(sc, m_head, txidx) 2885 struct dc_softc *sc; 2886 struct mbuf *m_head; 2887 u_int32_t *txidx; 2888 { 2889 struct dc_desc *f = NULL; 2890 struct mbuf *m; 2891 int frag, cur, cnt = 0; 2892 2893 /* 2894 * Start packing the mbufs in this chain into 2895 * the fragment pointers. Stop when we run out 2896 * of fragments or hit the end of the mbuf chain. 2897 */ 2898 m = m_head; 2899 cur = frag = *txidx; 2900 2901 for (m = m_head; m != NULL; m = m->m_next) { 2902 if (m->m_len != 0) { 2903 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2904 if (*txidx != sc->dc_cdata.dc_tx_prod && 2905 frag == (DC_TX_LIST_CNT - 1)) 2906 return(ENOBUFS); 2907 } 2908 if ((DC_TX_LIST_CNT - 2909 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2910 return(ENOBUFS); 2911 2912 f = &sc->dc_ldata->dc_tx_list[frag]; 2913 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2914 if (cnt == 0) { 2915 f->dc_status = 0; 2916 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2917 } else 2918 f->dc_status = DC_TXSTAT_OWN; 2919 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2920 cur = frag; 2921 DC_INC(frag, DC_TX_LIST_CNT); 2922 cnt++; 2923 } 2924 } 2925 2926 if (m != NULL) 2927 return(ENOBUFS); 2928 2929 sc->dc_cdata.dc_tx_cnt += cnt; 2930 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2931 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2932 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2933 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2934 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2935 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2936 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2937 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2938 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2939 *txidx = frag; 2940 2941 return(0); 2942 } 2943 2944 /* 2945 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2946 * to the mbuf data regions directly in the transmit lists. We also save a 2947 * copy of the pointers since the transmit list fragment pointers are 2948 * physical addresses. 2949 */ 2950 2951 static void dc_start(ifp) 2952 struct ifnet *ifp; 2953 { 2954 struct dc_softc *sc; 2955 struct mbuf *m_head = NULL, *m_new; 2956 int did_defrag, idx; 2957 2958 sc = ifp->if_softc; 2959 2960 if (!sc->dc_link) 2961 return; 2962 2963 if (ifp->if_flags & IFF_OACTIVE) 2964 return; 2965 2966 idx = sc->dc_cdata.dc_tx_prod; 2967 2968 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2969 did_defrag = 0; 2970 m_head = ifq_poll(&ifp->if_snd); 2971 if (m_head == NULL) 2972 break; 2973 2974 if (sc->dc_flags & DC_TX_COALESCE && 2975 (m_head->m_next != NULL || 2976 sc->dc_flags & DC_TX_ALIGN)){ 2977 /* 2978 * Check first if coalescing allows us to queue 2979 * the packet. We don't want to loose it if 2980 * the TX queue is full. 2981 */ 2982 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 2983 idx != sc->dc_cdata.dc_tx_prod && 2984 idx == (DC_TX_LIST_CNT - 1)) { 2985 ifp->if_flags |= IFF_OACTIVE; 2986 break; 2987 } 2988 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { 2989 ifp->if_flags |= IFF_OACTIVE; 2990 break; 2991 } 2992 2993 /* only coalesce if have >1 mbufs */ 2994 m_new = m_defrag_nofree(m_head, MB_DONTWAIT); 2995 if (m_new == NULL) { 2996 ifp->if_flags |= IFF_OACTIVE; 2997 break; 2998 } 2999 m_freem(m_head); 3000 m_head = m_new; 3001 did_defrag = 1; 3002 } 3003 3004 if (dc_encap(sc, m_head, &idx)) { 3005 if (did_defrag) { 3006 m_freem(m_head); 3007 m_new = ifq_dequeue(&ifp->if_snd); 3008 m_freem(m_new); 3009 } 3010 ifp->if_flags |= IFF_OACTIVE; 3011 break; 3012 } 3013 3014 m_new = ifq_dequeue(&ifp->if_snd); 3015 if (did_defrag) 3016 m_freem(m_new); 3017 3018 /* 3019 * If there's a BPF listener, bounce a copy of this frame 3020 * to him. 3021 */ 3022 BPF_MTAP(ifp, m_head); 3023 3024 if (sc->dc_flags & DC_TX_ONE) { 3025 ifp->if_flags |= IFF_OACTIVE; 3026 break; 3027 } 3028 } 3029 3030 /* Transmit */ 3031 sc->dc_cdata.dc_tx_prod = idx; 3032 if (!(sc->dc_flags & DC_TX_POLL)) 3033 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3034 3035 /* 3036 * Set a timeout in case the chip goes out to lunch. 3037 */ 3038 ifp->if_timer = 5; 3039 3040 return; 3041 } 3042 3043 static void dc_init(xsc) 3044 void *xsc; 3045 { 3046 struct dc_softc *sc = xsc; 3047 struct ifnet *ifp = &sc->arpcom.ac_if; 3048 struct mii_data *mii; 3049 3050 crit_enter(); 3051 3052 mii = device_get_softc(sc->dc_miibus); 3053 3054 /* 3055 * Cancel pending I/O and free all RX/TX buffers. 3056 */ 3057 dc_stop(sc); 3058 dc_reset(sc); 3059 3060 /* 3061 * Set cache alignment and burst length. 3062 */ 3063 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3064 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3065 else 3066 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3067 /* 3068 * Evenly share the bus between receive and transmit process. 3069 */ 3070 if (DC_IS_INTEL(sc)) 3071 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3072 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3073 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3074 } else { 3075 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3076 } 3077 if (sc->dc_flags & DC_TX_POLL) 3078 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3079 switch(sc->dc_cachesize) { 3080 case 32: 3081 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3082 break; 3083 case 16: 3084 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3085 break; 3086 case 8: 3087 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3088 break; 3089 case 0: 3090 default: 3091 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3092 break; 3093 } 3094 3095 if (sc->dc_flags & DC_TX_STORENFWD) 3096 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3097 else { 3098 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3099 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3100 } else { 3101 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3102 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3103 } 3104 } 3105 3106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3108 3109 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3110 /* 3111 * The app notes for the 98713 and 98715A say that 3112 * in order to have the chips operate properly, a magic 3113 * number must be written to CSR16. Macronix does not 3114 * document the meaning of these bits so there's no way 3115 * to know exactly what they do. The 98713 has a magic 3116 * number all its own; the rest all use a different one. 3117 */ 3118 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3119 if (sc->dc_type == DC_TYPE_98713) 3120 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3121 else 3122 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3123 } 3124 3125 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3126 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3127 3128 /* Init circular RX list. */ 3129 if (dc_list_rx_init(sc) == ENOBUFS) { 3130 if_printf(ifp, "initialization failed: no " 3131 "memory for rx buffers\n"); 3132 dc_stop(sc); 3133 crit_exit(); 3134 return; 3135 } 3136 3137 /* 3138 * Init tx descriptors. 3139 */ 3140 dc_list_tx_init(sc); 3141 3142 /* 3143 * Load the address of the RX list. 3144 */ 3145 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3146 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3147 3148 /* 3149 * Enable interrupts. 3150 */ 3151 #ifdef DEVICE_POLLING 3152 /* 3153 * ... but only if we are not polling, and make sure they are off in 3154 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3155 * after a reset. 3156 */ 3157 if (ifp->if_flags & IFF_POLLING) 3158 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3159 else 3160 #endif 3161 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3162 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3163 3164 /* Enable transmitter. */ 3165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3166 3167 /* 3168 * If this is an Intel 21143 and we're not using the 3169 * MII port, program the LED control pins so we get 3170 * link and activity indications. 3171 */ 3172 if (sc->dc_flags & DC_TULIP_LEDS) { 3173 CSR_WRITE_4(sc, DC_WATCHDOG, 3174 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3175 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3176 } 3177 3178 /* 3179 * Load the RX/multicast filter. We do this sort of late 3180 * because the filter programming scheme on the 21143 and 3181 * some clones requires DMAing a setup frame via the TX 3182 * engine, and we need the transmitter enabled for that. 3183 */ 3184 dc_setfilt(sc); 3185 3186 /* Enable receiver. */ 3187 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3188 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3189 3190 mii_mediachg(mii); 3191 dc_setcfg(sc, sc->dc_if_media); 3192 3193 ifp->if_flags |= IFF_RUNNING; 3194 ifp->if_flags &= ~IFF_OACTIVE; 3195 3196 crit_exit(); 3197 3198 /* Don't start the ticker if this is a homePNA link. */ 3199 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3200 sc->dc_link = 1; 3201 else { 3202 if (sc->dc_flags & DC_21143_NWAY) 3203 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3204 else 3205 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3206 } 3207 3208 return; 3209 } 3210 3211 /* 3212 * Set media options. 3213 */ 3214 static int dc_ifmedia_upd(ifp) 3215 struct ifnet *ifp; 3216 { 3217 struct dc_softc *sc; 3218 struct mii_data *mii; 3219 struct ifmedia *ifm; 3220 3221 sc = ifp->if_softc; 3222 mii = device_get_softc(sc->dc_miibus); 3223 mii_mediachg(mii); 3224 ifm = &mii->mii_media; 3225 3226 if (DC_IS_DAVICOM(sc) && 3227 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3228 dc_setcfg(sc, ifm->ifm_media); 3229 else 3230 sc->dc_link = 0; 3231 3232 return(0); 3233 } 3234 3235 /* 3236 * Report current media status. 3237 */ 3238 static void dc_ifmedia_sts(ifp, ifmr) 3239 struct ifnet *ifp; 3240 struct ifmediareq *ifmr; 3241 { 3242 struct dc_softc *sc; 3243 struct mii_data *mii; 3244 struct ifmedia *ifm; 3245 3246 sc = ifp->if_softc; 3247 mii = device_get_softc(sc->dc_miibus); 3248 mii_pollstat(mii); 3249 ifm = &mii->mii_media; 3250 if (DC_IS_DAVICOM(sc)) { 3251 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3252 ifmr->ifm_active = ifm->ifm_media; 3253 ifmr->ifm_status = 0; 3254 return; 3255 } 3256 } 3257 ifmr->ifm_active = mii->mii_media_active; 3258 ifmr->ifm_status = mii->mii_media_status; 3259 3260 return; 3261 } 3262 3263 static int dc_ioctl(ifp, command, data, cr) 3264 struct ifnet *ifp; 3265 u_long command; 3266 caddr_t data; 3267 struct ucred *cr; 3268 { 3269 struct dc_softc *sc = ifp->if_softc; 3270 struct ifreq *ifr = (struct ifreq *) data; 3271 struct mii_data *mii; 3272 int error = 0; 3273 3274 crit_enter(); 3275 3276 switch(command) { 3277 case SIOCSIFFLAGS: 3278 if (ifp->if_flags & IFF_UP) { 3279 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3280 (IFF_PROMISC | IFF_ALLMULTI); 3281 if (ifp->if_flags & IFF_RUNNING) { 3282 if (need_setfilt) 3283 dc_setfilt(sc); 3284 } else { 3285 sc->dc_txthresh = 0; 3286 dc_init(sc); 3287 } 3288 } else { 3289 if (ifp->if_flags & IFF_RUNNING) 3290 dc_stop(sc); 3291 } 3292 sc->dc_if_flags = ifp->if_flags; 3293 error = 0; 3294 break; 3295 case SIOCADDMULTI: 3296 case SIOCDELMULTI: 3297 dc_setfilt(sc); 3298 error = 0; 3299 break; 3300 case SIOCGIFMEDIA: 3301 case SIOCSIFMEDIA: 3302 mii = device_get_softc(sc->dc_miibus); 3303 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3304 break; 3305 default: 3306 error = ether_ioctl(ifp, command, data); 3307 break; 3308 } 3309 3310 crit_exit(); 3311 3312 return(error); 3313 } 3314 3315 static void dc_watchdog(ifp) 3316 struct ifnet *ifp; 3317 { 3318 struct dc_softc *sc; 3319 3320 sc = ifp->if_softc; 3321 3322 ifp->if_oerrors++; 3323 if_printf(ifp, "watchdog timeout\n"); 3324 3325 dc_stop(sc); 3326 dc_reset(sc); 3327 dc_init(sc); 3328 3329 if (!ifq_is_empty(&ifp->if_snd)) 3330 dc_start(ifp); 3331 3332 return; 3333 } 3334 3335 /* 3336 * Stop the adapter and free any mbufs allocated to the 3337 * RX and TX lists. 3338 */ 3339 static void dc_stop(sc) 3340 struct dc_softc *sc; 3341 { 3342 int i; 3343 struct ifnet *ifp; 3344 3345 ifp = &sc->arpcom.ac_if; 3346 ifp->if_timer = 0; 3347 3348 callout_stop(&sc->dc_stat_timer); 3349 3350 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3351 3352 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3353 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3354 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3355 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3356 sc->dc_link = 0; 3357 3358 /* 3359 * Free data in the RX lists. 3360 */ 3361 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3362 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3363 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3364 sc->dc_cdata.dc_rx_chain[i] = NULL; 3365 } 3366 } 3367 bzero((char *)&sc->dc_ldata->dc_rx_list, 3368 sizeof(sc->dc_ldata->dc_rx_list)); 3369 3370 /* 3371 * Free the TX list buffers. 3372 */ 3373 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3374 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3375 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3376 DC_TXCTL_SETUP) || 3377 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3378 DC_TXCTL_LASTFRAG)) { 3379 sc->dc_cdata.dc_tx_chain[i] = NULL; 3380 continue; 3381 } 3382 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3383 sc->dc_cdata.dc_tx_chain[i] = NULL; 3384 } 3385 } 3386 3387 bzero((char *)&sc->dc_ldata->dc_tx_list, 3388 sizeof(sc->dc_ldata->dc_tx_list)); 3389 3390 return; 3391 } 3392 3393 /* 3394 * Stop all chip I/O so that the kernel's probe routines don't 3395 * get confused by errant DMAs when rebooting. 3396 */ 3397 static void dc_shutdown(dev) 3398 device_t dev; 3399 { 3400 struct dc_softc *sc; 3401 3402 sc = device_get_softc(dev); 3403 3404 dc_stop(sc); 3405 3406 return; 3407 } 3408 3409 /* 3410 * Device suspend routine. Stop the interface and save some PCI 3411 * settings in case the BIOS doesn't restore them properly on 3412 * resume. 3413 */ 3414 static int dc_suspend(dev) 3415 device_t dev; 3416 { 3417 struct dc_softc *sc = device_get_softc(dev); 3418 int i; 3419 3420 crit_enter(); 3421 3422 dc_stop(sc); 3423 3424 for (i = 0; i < 5; i++) 3425 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3426 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3427 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3428 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3429 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3430 3431 sc->suspended = 1; 3432 3433 crit_exit(); 3434 return (0); 3435 } 3436 3437 /* 3438 * Device resume routine. Restore some PCI settings in case the BIOS 3439 * doesn't, re-enable busmastering, and restart the interface if 3440 * appropriate. 3441 */ 3442 static int dc_resume(dev) 3443 device_t dev; 3444 { 3445 struct dc_softc *sc = device_get_softc(dev); 3446 struct ifnet *ifp = &sc->arpcom.ac_if; 3447 int i; 3448 3449 crit_enter(); 3450 3451 dc_acpi(dev); 3452 3453 /* better way to do this? */ 3454 for (i = 0; i < 5; i++) 3455 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3456 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3457 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3458 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3459 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3460 3461 /* reenable busmastering */ 3462 pci_enable_busmaster(dev); 3463 pci_enable_io(dev, DC_RES); 3464 3465 /* reinitialize interface if necessary */ 3466 if (ifp->if_flags & IFF_UP) 3467 dc_init(sc); 3468 3469 sc->suspended = 0; 3470 3471 crit_exit(); 3472 return (0); 3473 } 3474