1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.2 2003/06/17 04:28:56 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 36 */ 37 38 /* 39 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 40 * series chips and several workalikes including the following: 41 * 42 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 43 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 44 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 45 * ASIX Electronics AX88140A (www.asix.com.tw) 46 * ASIX Electronics AX88141 (www.asix.com.tw) 47 * ADMtek AL981 (www.admtek.com.tw) 48 * ADMtek AN985 (www.admtek.com.tw) 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Conexant LANfinity (www.conexant.com) 52 * 53 * Datasheets for the 21143 are available at developer.intel.com. 54 * Datasheets for the clone parts can be found at their respective sites. 55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 56 * The PNIC II is essentially a Macronix 98715A chip; the only difference 57 * worth noting is that its multicast hash table is only 128 bits wide 58 * instead of 512. 59 * 60 * Written by Bill Paul <wpaul@ee.columbia.edu> 61 * Electrical Engineering Department 62 * Columbia University, New York City 63 */ 64 65 /* 66 * The Intel 21143 is the successor to the DEC 21140. It is basically 67 * the same as the 21140 but with a few new features. The 21143 supports 68 * three kinds of media attachments: 69 * 70 * o MII port, for 10Mbps and 100Mbps support and NWAY 71 * autonegotiation provided by an external PHY. 72 * o SYM port, for symbol mode 100Mbps support. 73 * o 10baseT port. 74 * o AUI/BNC port. 75 * 76 * The 100Mbps SYM port and 10baseT port can be used together in 77 * combination with the internal NWAY support to create a 10/100 78 * autosensing configuration. 79 * 80 * Note that not all tulip workalikes are handled in this driver: we only 81 * deal with those which are relatively well behaved. The Winbond is 82 * handled separately due to its different register offsets and the 83 * special handling needed for its various bugs. The PNIC is handled 84 * here, but I'm not thrilled about it. 85 * 86 * All of the workalike chips use some form of MII transceiver support 87 * with the exception of the Macronix chips, which also have a SYM port. 88 * The ASIX AX88140A is also documented to have a SYM port, but all 89 * the cards I've seen use an MII transceiver, probably because the 90 * AX88140A doesn't support internal NWAY. 91 */ 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/sysctl.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/clock.h> /* for DELAY */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <pci/pcireg.h> 126 #include <pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct dc_type dc_devs[] = { 142 { DC_VENDORID_DEC, DC_DEVICEID_21143, 143 "Intel 21143 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 145 "Davicom DM9009 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 147 "Davicom DM9100 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 149 "Davicom DM9102 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 151 "Davicom DM9102A 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 153 "ADMtek AL981 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 155 "ADMtek AN985 10/100BaseTX" }, 156 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 157 "ASIX AX88140A 10/100BaseTX" }, 158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 159 "ASIX AX88141 10/100BaseTX" }, 160 { DC_VENDORID_MX, DC_DEVICEID_98713, 161 "Macronix 98713 10/100BaseTX" }, 162 { DC_VENDORID_MX, DC_DEVICEID_98713, 163 "Macronix 98713A 10/100BaseTX" }, 164 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 165 "Compex RL100-TX 10/100BaseTX" }, 166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 167 "Compex RL100-TX 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98715/98715A 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98715AEC-C 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98725 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_98727, 175 "Macronix 98727/98732 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C115, 177 "LC82C115 PNIC II 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C168, 179 "82c168 PNIC 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C168, 181 "82c169 PNIC 10/100BaseTX" }, 182 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 183 "Accton EN1217 10/100BaseTX" }, 184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 185 "Accton EN2242 MiniPCI 10/100BaseTX" }, 186 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 187 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 188 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 189 "3Com OfficeConnect 10/100B" }, 190 { 0, 0, NULL } 191 }; 192 193 static int dc_probe __P((device_t)); 194 static int dc_attach __P((device_t)); 195 static int dc_detach __P((device_t)); 196 static int dc_suspend __P((device_t)); 197 static int dc_resume __P((device_t)); 198 static void dc_acpi __P((device_t)); 199 static struct dc_type *dc_devtype __P((device_t)); 200 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 201 static int dc_encap __P((struct dc_softc *, struct mbuf *, 202 u_int32_t *)); 203 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 204 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 205 static int dc_rx_resync __P((struct dc_softc *)); 206 static void dc_rxeof __P((struct dc_softc *)); 207 static void dc_txeof __P((struct dc_softc *)); 208 static void dc_tick __P((void *)); 209 static void dc_tx_underrun __P((struct dc_softc *)); 210 static void dc_intr __P((void *)); 211 static void dc_start __P((struct ifnet *)); 212 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 213 static void dc_init __P((void *)); 214 static void dc_stop __P((struct dc_softc *)); 215 static void dc_watchdog __P((struct ifnet *)); 216 static void dc_shutdown __P((device_t)); 217 static int dc_ifmedia_upd __P((struct ifnet *)); 218 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 219 220 static void dc_delay __P((struct dc_softc *)); 221 static void dc_eeprom_idle __P((struct dc_softc *)); 222 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 223 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 224 static void dc_eeprom_getword_pnic 225 __P((struct dc_softc *, int, u_int16_t *)); 226 static void dc_eeprom_width __P((struct dc_softc *)); 227 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 228 int, int)); 229 230 static void dc_mii_writebit __P((struct dc_softc *, int)); 231 static int dc_mii_readbit __P((struct dc_softc *)); 232 static void dc_mii_sync __P((struct dc_softc *)); 233 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 234 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 235 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 236 static int dc_miibus_readreg __P((device_t, int, int)); 237 static int dc_miibus_writereg __P((device_t, int, int, int)); 238 static void dc_miibus_statchg __P((device_t)); 239 static void dc_miibus_mediainit __P((device_t)); 240 241 static void dc_setcfg __P((struct dc_softc *, int)); 242 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 243 static u_int32_t dc_crc_be __P((caddr_t)); 244 static void dc_setfilt_21143 __P((struct dc_softc *)); 245 static void dc_setfilt_asix __P((struct dc_softc *)); 246 static void dc_setfilt_admtek __P((struct dc_softc *)); 247 248 static void dc_setfilt __P((struct dc_softc *)); 249 250 static void dc_reset __P((struct dc_softc *)); 251 static int dc_list_rx_init __P((struct dc_softc *)); 252 static int dc_list_tx_init __P((struct dc_softc *)); 253 254 static void dc_read_srom __P((struct dc_softc *, int)); 255 static void dc_parse_21143_srom __P((struct dc_softc *)); 256 static void dc_decode_leaf_sia __P((struct dc_softc *, 257 struct dc_eblock_sia *)); 258 static void dc_decode_leaf_mii __P((struct dc_softc *, 259 struct dc_eblock_mii *)); 260 static void dc_decode_leaf_sym __P((struct dc_softc *, 261 struct dc_eblock_sym *)); 262 static void dc_apply_fixup __P((struct dc_softc *, int)); 263 264 #ifdef DC_USEIOSPACE 265 #define DC_RES SYS_RES_IOPORT 266 #define DC_RID DC_PCI_CFBIO 267 #else 268 #define DC_RES SYS_RES_MEMORY 269 #define DC_RID DC_PCI_CFBMA 270 #endif 271 272 static device_method_t dc_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, dc_probe), 275 DEVMETHOD(device_attach, dc_attach), 276 DEVMETHOD(device_detach, dc_detach), 277 DEVMETHOD(device_suspend, dc_suspend), 278 DEVMETHOD(device_resume, dc_resume), 279 DEVMETHOD(device_shutdown, dc_shutdown), 280 281 /* bus interface */ 282 DEVMETHOD(bus_print_child, bus_generic_print_child), 283 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 284 285 /* MII interface */ 286 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 287 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 288 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 289 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 290 291 { 0, 0 } 292 }; 293 294 static driver_t dc_driver = { 295 "dc", 296 dc_methods, 297 sizeof(struct dc_softc) 298 }; 299 300 static devclass_t dc_devclass; 301 302 #ifdef __i386__ 303 static int dc_quick=1; 304 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 305 &dc_quick,0,"do not mdevget in dc driver"); 306 #endif 307 308 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 309 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 310 311 #define DC_SETBIT(sc, reg, x) \ 312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 313 314 #define DC_CLRBIT(sc, reg, x) \ 315 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 316 317 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 318 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 319 320 static void dc_delay(sc) 321 struct dc_softc *sc; 322 { 323 int idx; 324 325 for (idx = (300 / 33) + 1; idx > 0; idx--) 326 CSR_READ_4(sc, DC_BUSCTL); 327 } 328 329 static void dc_eeprom_width(sc) 330 struct dc_softc *sc; 331 { 332 int i; 333 334 /* Force EEPROM to idle state. */ 335 dc_eeprom_idle(sc); 336 337 /* Enter EEPROM access mode. */ 338 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 339 dc_delay(sc); 340 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 341 dc_delay(sc); 342 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 343 dc_delay(sc); 344 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 345 dc_delay(sc); 346 347 for (i = 3; i--;) { 348 if (6 & (1 << i)) 349 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 350 else 351 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 352 dc_delay(sc); 353 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 354 dc_delay(sc); 355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 356 dc_delay(sc); 357 } 358 359 for (i = 1; i <= 12; i++) { 360 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 361 dc_delay(sc); 362 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 363 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 364 dc_delay(sc); 365 break; 366 } 367 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 368 dc_delay(sc); 369 } 370 371 /* Turn off EEPROM access mode. */ 372 dc_eeprom_idle(sc); 373 374 if (i < 4 || i > 12) 375 sc->dc_romwidth = 6; 376 else 377 sc->dc_romwidth = i; 378 379 /* Enter EEPROM access mode. */ 380 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 381 dc_delay(sc); 382 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 383 dc_delay(sc); 384 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 385 dc_delay(sc); 386 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 387 dc_delay(sc); 388 389 /* Turn off EEPROM access mode. */ 390 dc_eeprom_idle(sc); 391 } 392 393 static void dc_eeprom_idle(sc) 394 struct dc_softc *sc; 395 { 396 register int i; 397 398 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 399 dc_delay(sc); 400 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 401 dc_delay(sc); 402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 403 dc_delay(sc); 404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 405 dc_delay(sc); 406 407 for (i = 0; i < 25; i++) { 408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 409 dc_delay(sc); 410 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 411 dc_delay(sc); 412 } 413 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 417 dc_delay(sc); 418 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 419 420 return; 421 } 422 423 /* 424 * Send a read command and address to the EEPROM, check for ACK. 425 */ 426 static void dc_eeprom_putbyte(sc, addr) 427 struct dc_softc *sc; 428 int addr; 429 { 430 register int d, i; 431 432 d = DC_EECMD_READ >> 6; 433 for (i = 3; i--; ) { 434 if (d & (1 << i)) 435 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 436 else 437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 438 dc_delay(sc); 439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 440 dc_delay(sc); 441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 } 444 445 /* 446 * Feed in each bit and strobe the clock. 447 */ 448 for (i = sc->dc_romwidth; i--;) { 449 if (addr & (1 << i)) { 450 SIO_SET(DC_SIO_EE_DATAIN); 451 } else { 452 SIO_CLR(DC_SIO_EE_DATAIN); 453 } 454 dc_delay(sc); 455 SIO_SET(DC_SIO_EE_CLK); 456 dc_delay(sc); 457 SIO_CLR(DC_SIO_EE_CLK); 458 dc_delay(sc); 459 } 460 461 return; 462 } 463 464 /* 465 * Read a word of data stored in the EEPROM at address 'addr.' 466 * The PNIC 82c168/82c169 has its own non-standard way to read 467 * the EEPROM. 468 */ 469 static void dc_eeprom_getword_pnic(sc, addr, dest) 470 struct dc_softc *sc; 471 int addr; 472 u_int16_t *dest; 473 { 474 register int i; 475 u_int32_t r; 476 477 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 478 479 for (i = 0; i < DC_TIMEOUT; i++) { 480 DELAY(1); 481 r = CSR_READ_4(sc, DC_SIO); 482 if (!(r & DC_PN_SIOCTL_BUSY)) { 483 *dest = (u_int16_t)(r & 0xFFFF); 484 return; 485 } 486 } 487 488 return; 489 } 490 491 /* 492 * Read a word of data stored in the EEPROM at address 'addr.' 493 */ 494 static void dc_eeprom_getword(sc, addr, dest) 495 struct dc_softc *sc; 496 int addr; 497 u_int16_t *dest; 498 { 499 register int i; 500 u_int16_t word = 0; 501 502 /* Force EEPROM to idle state. */ 503 dc_eeprom_idle(sc); 504 505 /* Enter EEPROM access mode. */ 506 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 507 dc_delay(sc); 508 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 509 dc_delay(sc); 510 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 511 dc_delay(sc); 512 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 513 dc_delay(sc); 514 515 /* 516 * Send address of word we want to read. 517 */ 518 dc_eeprom_putbyte(sc, addr); 519 520 /* 521 * Start reading bits from EEPROM. 522 */ 523 for (i = 0x8000; i; i >>= 1) { 524 SIO_SET(DC_SIO_EE_CLK); 525 dc_delay(sc); 526 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 527 word |= i; 528 dc_delay(sc); 529 SIO_CLR(DC_SIO_EE_CLK); 530 dc_delay(sc); 531 } 532 533 /* Turn off EEPROM access mode. */ 534 dc_eeprom_idle(sc); 535 536 *dest = word; 537 538 return; 539 } 540 541 /* 542 * Read a sequence of words from the EEPROM. 543 */ 544 static void dc_read_eeprom(sc, dest, off, cnt, swap) 545 struct dc_softc *sc; 546 caddr_t dest; 547 int off; 548 int cnt; 549 int swap; 550 { 551 int i; 552 u_int16_t word = 0, *ptr; 553 554 for (i = 0; i < cnt; i++) { 555 if (DC_IS_PNIC(sc)) 556 dc_eeprom_getword_pnic(sc, off + i, &word); 557 else 558 dc_eeprom_getword(sc, off + i, &word); 559 ptr = (u_int16_t *)(dest + (i * 2)); 560 if (swap) 561 *ptr = ntohs(word); 562 else 563 *ptr = word; 564 } 565 566 return; 567 } 568 569 /* 570 * The following two routines are taken from the Macronix 98713 571 * Application Notes pp.19-21. 572 */ 573 /* 574 * Write a bit to the MII bus. 575 */ 576 static void dc_mii_writebit(sc, bit) 577 struct dc_softc *sc; 578 int bit; 579 { 580 if (bit) 581 CSR_WRITE_4(sc, DC_SIO, 582 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 583 else 584 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 585 586 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 587 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 588 589 return; 590 } 591 592 /* 593 * Read a bit from the MII bus. 594 */ 595 static int dc_mii_readbit(sc) 596 struct dc_softc *sc; 597 { 598 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 599 CSR_READ_4(sc, DC_SIO); 600 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 601 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 602 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 603 return(1); 604 605 return(0); 606 } 607 608 /* 609 * Sync the PHYs by setting data bit and strobing the clock 32 times. 610 */ 611 static void dc_mii_sync(sc) 612 struct dc_softc *sc; 613 { 614 register int i; 615 616 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 617 618 for (i = 0; i < 32; i++) 619 dc_mii_writebit(sc, 1); 620 621 return; 622 } 623 624 /* 625 * Clock a series of bits through the MII. 626 */ 627 static void dc_mii_send(sc, bits, cnt) 628 struct dc_softc *sc; 629 u_int32_t bits; 630 int cnt; 631 { 632 int i; 633 634 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 635 dc_mii_writebit(sc, bits & i); 636 } 637 638 /* 639 * Read an PHY register through the MII. 640 */ 641 static int dc_mii_readreg(sc, frame) 642 struct dc_softc *sc; 643 struct dc_mii_frame *frame; 644 645 { 646 int i, ack, s; 647 648 s = splimp(); 649 650 /* 651 * Set up frame for RX. 652 */ 653 frame->mii_stdelim = DC_MII_STARTDELIM; 654 frame->mii_opcode = DC_MII_READOP; 655 frame->mii_turnaround = 0; 656 frame->mii_data = 0; 657 658 /* 659 * Sync the PHYs. 660 */ 661 dc_mii_sync(sc); 662 663 /* 664 * Send command/address info. 665 */ 666 dc_mii_send(sc, frame->mii_stdelim, 2); 667 dc_mii_send(sc, frame->mii_opcode, 2); 668 dc_mii_send(sc, frame->mii_phyaddr, 5); 669 dc_mii_send(sc, frame->mii_regaddr, 5); 670 671 #ifdef notdef 672 /* Idle bit */ 673 dc_mii_writebit(sc, 1); 674 dc_mii_writebit(sc, 0); 675 #endif 676 677 /* Check for ack */ 678 ack = dc_mii_readbit(sc); 679 680 /* 681 * Now try reading data bits. If the ack failed, we still 682 * need to clock through 16 cycles to keep the PHY(s) in sync. 683 */ 684 if (ack) { 685 for(i = 0; i < 16; i++) { 686 dc_mii_readbit(sc); 687 } 688 goto fail; 689 } 690 691 for (i = 0x8000; i; i >>= 1) { 692 if (!ack) { 693 if (dc_mii_readbit(sc)) 694 frame->mii_data |= i; 695 } 696 } 697 698 fail: 699 700 dc_mii_writebit(sc, 0); 701 dc_mii_writebit(sc, 0); 702 703 splx(s); 704 705 if (ack) 706 return(1); 707 return(0); 708 } 709 710 /* 711 * Write to a PHY register through the MII. 712 */ 713 static int dc_mii_writereg(sc, frame) 714 struct dc_softc *sc; 715 struct dc_mii_frame *frame; 716 717 { 718 int s; 719 720 s = splimp(); 721 /* 722 * Set up frame for TX. 723 */ 724 725 frame->mii_stdelim = DC_MII_STARTDELIM; 726 frame->mii_opcode = DC_MII_WRITEOP; 727 frame->mii_turnaround = DC_MII_TURNAROUND; 728 729 /* 730 * Sync the PHYs. 731 */ 732 dc_mii_sync(sc); 733 734 dc_mii_send(sc, frame->mii_stdelim, 2); 735 dc_mii_send(sc, frame->mii_opcode, 2); 736 dc_mii_send(sc, frame->mii_phyaddr, 5); 737 dc_mii_send(sc, frame->mii_regaddr, 5); 738 dc_mii_send(sc, frame->mii_turnaround, 2); 739 dc_mii_send(sc, frame->mii_data, 16); 740 741 /* Idle bit. */ 742 dc_mii_writebit(sc, 0); 743 dc_mii_writebit(sc, 0); 744 745 splx(s); 746 747 return(0); 748 } 749 750 static int dc_miibus_readreg(dev, phy, reg) 751 device_t dev; 752 int phy, reg; 753 { 754 struct dc_mii_frame frame; 755 struct dc_softc *sc; 756 int i, rval, phy_reg = 0; 757 758 sc = device_get_softc(dev); 759 bzero((char *)&frame, sizeof(frame)); 760 761 /* 762 * Note: both the AL981 and AN985 have internal PHYs, 763 * however the AL981 provides direct access to the PHY 764 * registers while the AN985 uses a serial MII interface. 765 * The AN985's MII interface is also buggy in that you 766 * can read from any MII address (0 to 31), but only address 1 767 * behaves normally. To deal with both cases, we pretend 768 * that the PHY is at MII address 1. 769 */ 770 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 771 return(0); 772 773 /* 774 * Note: the ukphy probes of the RS7112 report a PHY at 775 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 776 * so we only respond to correct one. 777 */ 778 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 779 return(0); 780 781 if (sc->dc_pmode != DC_PMODE_MII) { 782 if (phy == (MII_NPHY - 1)) { 783 switch(reg) { 784 case MII_BMSR: 785 /* 786 * Fake something to make the probe 787 * code think there's a PHY here. 788 */ 789 return(BMSR_MEDIAMASK); 790 break; 791 case MII_PHYIDR1: 792 if (DC_IS_PNIC(sc)) 793 return(DC_VENDORID_LO); 794 return(DC_VENDORID_DEC); 795 break; 796 case MII_PHYIDR2: 797 if (DC_IS_PNIC(sc)) 798 return(DC_DEVICEID_82C168); 799 return(DC_DEVICEID_21143); 800 break; 801 default: 802 return(0); 803 break; 804 } 805 } else 806 return(0); 807 } 808 809 if (DC_IS_PNIC(sc)) { 810 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 811 (phy << 23) | (reg << 18)); 812 for (i = 0; i < DC_TIMEOUT; i++) { 813 DELAY(1); 814 rval = CSR_READ_4(sc, DC_PN_MII); 815 if (!(rval & DC_PN_MII_BUSY)) { 816 rval &= 0xFFFF; 817 return(rval == 0xFFFF ? 0 : rval); 818 } 819 } 820 return(0); 821 } 822 823 if (DC_IS_COMET(sc)) { 824 switch(reg) { 825 case MII_BMCR: 826 phy_reg = DC_AL_BMCR; 827 break; 828 case MII_BMSR: 829 phy_reg = DC_AL_BMSR; 830 break; 831 case MII_PHYIDR1: 832 phy_reg = DC_AL_VENID; 833 break; 834 case MII_PHYIDR2: 835 phy_reg = DC_AL_DEVID; 836 break; 837 case MII_ANAR: 838 phy_reg = DC_AL_ANAR; 839 break; 840 case MII_ANLPAR: 841 phy_reg = DC_AL_LPAR; 842 break; 843 case MII_ANER: 844 phy_reg = DC_AL_ANER; 845 break; 846 default: 847 printf("dc%d: phy_read: bad phy register %x\n", 848 sc->dc_unit, reg); 849 return(0); 850 break; 851 } 852 853 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 854 855 if (rval == 0xFFFF) 856 return(0); 857 return(rval); 858 } 859 860 frame.mii_phyaddr = phy; 861 frame.mii_regaddr = reg; 862 if (sc->dc_type == DC_TYPE_98713) { 863 phy_reg = CSR_READ_4(sc, DC_NETCFG); 864 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 865 } 866 dc_mii_readreg(sc, &frame); 867 if (sc->dc_type == DC_TYPE_98713) 868 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 869 870 return(frame.mii_data); 871 } 872 873 static int dc_miibus_writereg(dev, phy, reg, data) 874 device_t dev; 875 int phy, reg, data; 876 { 877 struct dc_softc *sc; 878 struct dc_mii_frame frame; 879 int i, phy_reg = 0; 880 881 sc = device_get_softc(dev); 882 bzero((char *)&frame, sizeof(frame)); 883 884 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 885 return(0); 886 887 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 888 return(0); 889 890 if (DC_IS_PNIC(sc)) { 891 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 892 (phy << 23) | (reg << 10) | data); 893 for (i = 0; i < DC_TIMEOUT; i++) { 894 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 895 break; 896 } 897 return(0); 898 } 899 900 if (DC_IS_COMET(sc)) { 901 switch(reg) { 902 case MII_BMCR: 903 phy_reg = DC_AL_BMCR; 904 break; 905 case MII_BMSR: 906 phy_reg = DC_AL_BMSR; 907 break; 908 case MII_PHYIDR1: 909 phy_reg = DC_AL_VENID; 910 break; 911 case MII_PHYIDR2: 912 phy_reg = DC_AL_DEVID; 913 break; 914 case MII_ANAR: 915 phy_reg = DC_AL_ANAR; 916 break; 917 case MII_ANLPAR: 918 phy_reg = DC_AL_LPAR; 919 break; 920 case MII_ANER: 921 phy_reg = DC_AL_ANER; 922 break; 923 default: 924 printf("dc%d: phy_write: bad phy register %x\n", 925 sc->dc_unit, reg); 926 return(0); 927 break; 928 } 929 930 CSR_WRITE_4(sc, phy_reg, data); 931 return(0); 932 } 933 934 frame.mii_phyaddr = phy; 935 frame.mii_regaddr = reg; 936 frame.mii_data = data; 937 938 if (sc->dc_type == DC_TYPE_98713) { 939 phy_reg = CSR_READ_4(sc, DC_NETCFG); 940 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 941 } 942 dc_mii_writereg(sc, &frame); 943 if (sc->dc_type == DC_TYPE_98713) 944 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 945 946 return(0); 947 } 948 949 static void dc_miibus_statchg(dev) 950 device_t dev; 951 { 952 struct dc_softc *sc; 953 struct mii_data *mii; 954 struct ifmedia *ifm; 955 956 sc = device_get_softc(dev); 957 if (DC_IS_ADMTEK(sc)) 958 return; 959 960 mii = device_get_softc(sc->dc_miibus); 961 ifm = &mii->mii_media; 962 if (DC_IS_DAVICOM(sc) && 963 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 964 dc_setcfg(sc, ifm->ifm_media); 965 sc->dc_if_media = ifm->ifm_media; 966 } else { 967 dc_setcfg(sc, mii->mii_media_active); 968 sc->dc_if_media = mii->mii_media_active; 969 } 970 971 return; 972 } 973 974 /* 975 * Special support for DM9102A cards with HomePNA PHYs. Note: 976 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 977 * to be impossible to talk to the management interface of the DM9801 978 * PHY (its MDIO pin is not connected to anything). Consequently, 979 * the driver has to just 'know' about the additional mode and deal 980 * with it itself. *sigh* 981 */ 982 static void dc_miibus_mediainit(dev) 983 device_t dev; 984 { 985 struct dc_softc *sc; 986 struct mii_data *mii; 987 struct ifmedia *ifm; 988 int rev; 989 990 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 991 992 sc = device_get_softc(dev); 993 mii = device_get_softc(sc->dc_miibus); 994 ifm = &mii->mii_media; 995 996 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 997 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 998 999 return; 1000 } 1001 1002 #define DC_POLY 0xEDB88320 1003 #define DC_BITS_512 9 1004 #define DC_BITS_128 7 1005 #define DC_BITS_64 6 1006 1007 static u_int32_t dc_crc_le(sc, addr) 1008 struct dc_softc *sc; 1009 caddr_t addr; 1010 { 1011 u_int32_t idx, bit, data, crc; 1012 1013 /* Compute CRC for the address value. */ 1014 crc = 0xFFFFFFFF; /* initial value */ 1015 1016 for (idx = 0; idx < 6; idx++) { 1017 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1018 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1019 } 1020 1021 /* 1022 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1023 * chips is only 128 bits wide. 1024 */ 1025 if (sc->dc_flags & DC_128BIT_HASH) 1026 return (crc & ((1 << DC_BITS_128) - 1)); 1027 1028 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1029 if (sc->dc_flags & DC_64BIT_HASH) 1030 return (crc & ((1 << DC_BITS_64) - 1)); 1031 1032 return (crc & ((1 << DC_BITS_512) - 1)); 1033 } 1034 1035 /* 1036 * Calculate CRC of a multicast group address, return the lower 6 bits. 1037 */ 1038 static u_int32_t dc_crc_be(addr) 1039 caddr_t addr; 1040 { 1041 u_int32_t crc, carry; 1042 int i, j; 1043 u_int8_t c; 1044 1045 /* Compute CRC for the address value. */ 1046 crc = 0xFFFFFFFF; /* initial value */ 1047 1048 for (i = 0; i < 6; i++) { 1049 c = *(addr + i); 1050 for (j = 0; j < 8; j++) { 1051 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1052 crc <<= 1; 1053 c >>= 1; 1054 if (carry) 1055 crc = (crc ^ 0x04c11db6) | carry; 1056 } 1057 } 1058 1059 /* return the filter bit position */ 1060 return((crc >> 26) & 0x0000003F); 1061 } 1062 1063 /* 1064 * 21143-style RX filter setup routine. Filter programming is done by 1065 * downloading a special setup frame into the TX engine. 21143, Macronix, 1066 * PNIC, PNIC II and Davicom chips are programmed this way. 1067 * 1068 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1069 * address (our node address) and a 512-bit hash filter for multicast 1070 * frames. We also sneak the broadcast address into the hash filter since 1071 * we need that too. 1072 */ 1073 void dc_setfilt_21143(sc) 1074 struct dc_softc *sc; 1075 { 1076 struct dc_desc *sframe; 1077 u_int32_t h, *sp; 1078 struct ifmultiaddr *ifma; 1079 struct ifnet *ifp; 1080 int i; 1081 1082 ifp = &sc->arpcom.ac_if; 1083 1084 i = sc->dc_cdata.dc_tx_prod; 1085 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1086 sc->dc_cdata.dc_tx_cnt++; 1087 sframe = &sc->dc_ldata->dc_tx_list[i]; 1088 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1089 bzero((char *)sp, DC_SFRAME_LEN); 1090 1091 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1092 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1093 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1094 1095 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1096 1097 /* If we want promiscuous mode, set the allframes bit. */ 1098 if (ifp->if_flags & IFF_PROMISC) 1099 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1100 else 1101 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1102 1103 if (ifp->if_flags & IFF_ALLMULTI) 1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1105 else 1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1107 1108 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1109 ifma = ifma->ifma_link.le_next) { 1110 if (ifma->ifma_addr->sa_family != AF_LINK) 1111 continue; 1112 h = dc_crc_le(sc, 1113 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1114 sp[h >> 4] |= 1 << (h & 0xF); 1115 } 1116 1117 if (ifp->if_flags & IFF_BROADCAST) { 1118 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1119 sp[h >> 4] |= 1 << (h & 0xF); 1120 } 1121 1122 /* Set our MAC address */ 1123 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1124 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1125 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1126 1127 sframe->dc_status = DC_TXSTAT_OWN; 1128 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1129 1130 /* 1131 * The PNIC takes an exceedingly long time to process its 1132 * setup frame; wait 10ms after posting the setup frame 1133 * before proceeding, just so it has time to swallow its 1134 * medicine. 1135 */ 1136 DELAY(10000); 1137 1138 ifp->if_timer = 5; 1139 1140 return; 1141 } 1142 1143 void dc_setfilt_admtek(sc) 1144 struct dc_softc *sc; 1145 { 1146 struct ifnet *ifp; 1147 int h = 0; 1148 u_int32_t hashes[2] = { 0, 0 }; 1149 struct ifmultiaddr *ifma; 1150 1151 ifp = &sc->arpcom.ac_if; 1152 1153 /* Init our MAC address */ 1154 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1155 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1156 1157 /* If we want promiscuous mode, set the allframes bit. */ 1158 if (ifp->if_flags & IFF_PROMISC) 1159 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1160 else 1161 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1162 1163 if (ifp->if_flags & IFF_ALLMULTI) 1164 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1165 else 1166 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1167 1168 /* first, zot all the existing hash bits */ 1169 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1170 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1171 1172 /* 1173 * If we're already in promisc or allmulti mode, we 1174 * don't have to bother programming the multicast filter. 1175 */ 1176 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1177 return; 1178 1179 /* now program new ones */ 1180 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1181 ifma = ifma->ifma_link.le_next) { 1182 if (ifma->ifma_addr->sa_family != AF_LINK) 1183 continue; 1184 if (DC_IS_CENTAUR(sc)) 1185 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1186 else 1187 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1188 if (h < 32) 1189 hashes[0] |= (1 << h); 1190 else 1191 hashes[1] |= (1 << (h - 32)); 1192 } 1193 1194 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1195 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1196 1197 return; 1198 } 1199 1200 void dc_setfilt_asix(sc) 1201 struct dc_softc *sc; 1202 { 1203 struct ifnet *ifp; 1204 int h = 0; 1205 u_int32_t hashes[2] = { 0, 0 }; 1206 struct ifmultiaddr *ifma; 1207 1208 ifp = &sc->arpcom.ac_if; 1209 1210 /* Init our MAC address */ 1211 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1212 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1213 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1214 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1215 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1216 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1217 1218 /* If we want promiscuous mode, set the allframes bit. */ 1219 if (ifp->if_flags & IFF_PROMISC) 1220 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1221 else 1222 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1223 1224 if (ifp->if_flags & IFF_ALLMULTI) 1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1226 else 1227 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1228 1229 /* 1230 * The ASIX chip has a special bit to enable reception 1231 * of broadcast frames. 1232 */ 1233 if (ifp->if_flags & IFF_BROADCAST) 1234 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1235 else 1236 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1237 1238 /* first, zot all the existing hash bits */ 1239 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1240 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1243 1244 /* 1245 * If we're already in promisc or allmulti mode, we 1246 * don't have to bother programming the multicast filter. 1247 */ 1248 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1249 return; 1250 1251 /* now program new ones */ 1252 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1253 ifma = ifma->ifma_link.le_next) { 1254 if (ifma->ifma_addr->sa_family != AF_LINK) 1255 continue; 1256 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1257 if (h < 32) 1258 hashes[0] |= (1 << h); 1259 else 1260 hashes[1] |= (1 << (h - 32)); 1261 } 1262 1263 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1264 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1267 1268 return; 1269 } 1270 1271 static void dc_setfilt(sc) 1272 struct dc_softc *sc; 1273 { 1274 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1275 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1276 dc_setfilt_21143(sc); 1277 1278 if (DC_IS_ASIX(sc)) 1279 dc_setfilt_asix(sc); 1280 1281 if (DC_IS_ADMTEK(sc)) 1282 dc_setfilt_admtek(sc); 1283 1284 return; 1285 } 1286 1287 /* 1288 * In order to fiddle with the 1289 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1290 * first have to put the transmit and/or receive logic in the idle state. 1291 */ 1292 static void dc_setcfg(sc, media) 1293 struct dc_softc *sc; 1294 int media; 1295 { 1296 int i, restart = 0; 1297 u_int32_t isr; 1298 1299 if (IFM_SUBTYPE(media) == IFM_NONE) 1300 return; 1301 1302 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1303 restart = 1; 1304 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1305 1306 for (i = 0; i < DC_TIMEOUT; i++) { 1307 isr = CSR_READ_4(sc, DC_ISR); 1308 if (isr & DC_ISR_TX_IDLE || 1309 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1310 break; 1311 DELAY(10); 1312 } 1313 1314 if (i == DC_TIMEOUT) 1315 printf("dc%d: failed to force tx and " 1316 "rx to idle state\n", sc->dc_unit); 1317 } 1318 1319 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1320 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1321 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1322 if (sc->dc_pmode == DC_PMODE_MII) { 1323 int watchdogreg; 1324 1325 if (DC_IS_INTEL(sc)) { 1326 /* there's a write enable bit here that reads as 1 */ 1327 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1328 watchdogreg &= ~DC_WDOG_CTLWREN; 1329 watchdogreg |= DC_WDOG_JABBERDIS; 1330 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1331 } else { 1332 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1333 } 1334 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1335 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1336 if (sc->dc_type == DC_TYPE_98713) 1337 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1338 DC_NETCFG_SCRAMBLER)); 1339 if (!DC_IS_DAVICOM(sc)) 1340 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1341 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1342 if (DC_IS_INTEL(sc)) 1343 dc_apply_fixup(sc, IFM_AUTO); 1344 } else { 1345 if (DC_IS_PNIC(sc)) { 1346 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1347 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1348 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1349 } 1350 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1351 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1353 if (DC_IS_INTEL(sc)) 1354 dc_apply_fixup(sc, 1355 (media & IFM_GMASK) == IFM_FDX ? 1356 IFM_100_TX|IFM_FDX : IFM_100_TX); 1357 } 1358 } 1359 1360 if (IFM_SUBTYPE(media) == IFM_10_T) { 1361 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1362 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1363 if (sc->dc_pmode == DC_PMODE_MII) { 1364 int watchdogreg; 1365 1366 /* there's a write enable bit here that reads as 1 */ 1367 if (DC_IS_INTEL(sc)) { 1368 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1369 watchdogreg &= ~DC_WDOG_CTLWREN; 1370 watchdogreg |= DC_WDOG_JABBERDIS; 1371 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1372 } else { 1373 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1374 } 1375 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1376 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1377 if (sc->dc_type == DC_TYPE_98713) 1378 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1379 if (!DC_IS_DAVICOM(sc)) 1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1381 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1382 if (DC_IS_INTEL(sc)) 1383 dc_apply_fixup(sc, IFM_AUTO); 1384 } else { 1385 if (DC_IS_PNIC(sc)) { 1386 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1387 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1388 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1389 } 1390 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1391 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1393 if (DC_IS_INTEL(sc)) { 1394 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1395 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1396 if ((media & IFM_GMASK) == IFM_FDX) 1397 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1398 else 1399 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1400 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1401 DC_CLRBIT(sc, DC_10BTCTRL, 1402 DC_TCTL_AUTONEGENBL); 1403 dc_apply_fixup(sc, 1404 (media & IFM_GMASK) == IFM_FDX ? 1405 IFM_10_T|IFM_FDX : IFM_10_T); 1406 DELAY(20000); 1407 } 1408 } 1409 } 1410 1411 /* 1412 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1413 * PHY and we want HomePNA mode, set the portsel bit to turn 1414 * on the external MII port. 1415 */ 1416 if (DC_IS_DAVICOM(sc)) { 1417 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1419 sc->dc_link = 1; 1420 } else { 1421 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1422 } 1423 } 1424 1425 if ((media & IFM_GMASK) == IFM_FDX) { 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1427 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1428 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1429 } else { 1430 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1431 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1432 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1433 } 1434 1435 if (restart) 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1437 1438 return; 1439 } 1440 1441 static void dc_reset(sc) 1442 struct dc_softc *sc; 1443 { 1444 register int i; 1445 1446 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1447 1448 for (i = 0; i < DC_TIMEOUT; i++) { 1449 DELAY(10); 1450 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1451 break; 1452 } 1453 1454 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1455 DELAY(10000); 1456 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1457 i = 0; 1458 } 1459 1460 if (i == DC_TIMEOUT) 1461 printf("dc%d: reset never completed!\n", sc->dc_unit); 1462 1463 /* Wait a little while for the chip to get its brains in order. */ 1464 DELAY(1000); 1465 1466 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1467 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1468 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1469 1470 /* 1471 * Bring the SIA out of reset. In some cases, it looks 1472 * like failing to unreset the SIA soon enough gets it 1473 * into a state where it will never come out of reset 1474 * until we reset the whole chip again. 1475 */ 1476 if (DC_IS_INTEL(sc)) { 1477 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1478 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1479 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1480 } 1481 1482 return; 1483 } 1484 1485 static struct dc_type *dc_devtype(dev) 1486 device_t dev; 1487 { 1488 struct dc_type *t; 1489 u_int32_t rev; 1490 1491 t = dc_devs; 1492 1493 while(t->dc_name != NULL) { 1494 if ((pci_get_vendor(dev) == t->dc_vid) && 1495 (pci_get_device(dev) == t->dc_did)) { 1496 /* Check the PCI revision */ 1497 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1498 if (t->dc_did == DC_DEVICEID_98713 && 1499 rev >= DC_REVISION_98713A) 1500 t++; 1501 if (t->dc_did == DC_DEVICEID_98713_CP && 1502 rev >= DC_REVISION_98713A) 1503 t++; 1504 if (t->dc_did == DC_DEVICEID_987x5 && 1505 rev >= DC_REVISION_98715AEC_C) 1506 t++; 1507 if (t->dc_did == DC_DEVICEID_987x5 && 1508 rev >= DC_REVISION_98725) 1509 t++; 1510 if (t->dc_did == DC_DEVICEID_AX88140A && 1511 rev >= DC_REVISION_88141) 1512 t++; 1513 if (t->dc_did == DC_DEVICEID_82C168 && 1514 rev >= DC_REVISION_82C169) 1515 t++; 1516 if (t->dc_did == DC_DEVICEID_DM9102 && 1517 rev >= DC_REVISION_DM9102A) 1518 t++; 1519 return(t); 1520 } 1521 t++; 1522 } 1523 1524 return(NULL); 1525 } 1526 1527 /* 1528 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1529 * IDs against our list and return a device name if we find a match. 1530 * We do a little bit of extra work to identify the exact type of 1531 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1532 * but different revision IDs. The same is true for 98715/98715A 1533 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1534 * cases, the exact chip revision affects driver behavior. 1535 */ 1536 static int dc_probe(dev) 1537 device_t dev; 1538 { 1539 struct dc_type *t; 1540 1541 t = dc_devtype(dev); 1542 1543 if (t != NULL) { 1544 device_set_desc(dev, t->dc_name); 1545 return(0); 1546 } 1547 1548 return(ENXIO); 1549 } 1550 1551 static void dc_acpi(dev) 1552 device_t dev; 1553 { 1554 u_int32_t r, cptr; 1555 int unit; 1556 1557 unit = device_get_unit(dev); 1558 1559 /* Find the location of the capabilities block */ 1560 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1561 1562 r = pci_read_config(dev, cptr, 4) & 0xFF; 1563 if (r == 0x01) { 1564 1565 r = pci_read_config(dev, cptr + 4, 4); 1566 if (r & DC_PSTATE_D3) { 1567 u_int32_t iobase, membase, irq; 1568 1569 /* Save important PCI config data. */ 1570 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1571 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1572 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1573 1574 /* Reset the power state. */ 1575 printf("dc%d: chip is in D%d power mode " 1576 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1577 r &= 0xFFFFFFFC; 1578 pci_write_config(dev, cptr + 4, r, 4); 1579 1580 /* Restore PCI config data. */ 1581 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1582 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1583 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1584 } 1585 } 1586 return; 1587 } 1588 1589 static void dc_apply_fixup(sc, media) 1590 struct dc_softc *sc; 1591 int media; 1592 { 1593 struct dc_mediainfo *m; 1594 u_int8_t *p; 1595 int i; 1596 u_int32_t reg; 1597 1598 m = sc->dc_mi; 1599 1600 while (m != NULL) { 1601 if (m->dc_media == media) 1602 break; 1603 m = m->dc_next; 1604 } 1605 1606 if (m == NULL) 1607 return; 1608 1609 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1610 reg = (p[0] | (p[1] << 8)) << 16; 1611 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1612 } 1613 1614 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1615 reg = (p[0] | (p[1] << 8)) << 16; 1616 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1617 } 1618 1619 return; 1620 } 1621 1622 static void dc_decode_leaf_sia(sc, l) 1623 struct dc_softc *sc; 1624 struct dc_eblock_sia *l; 1625 { 1626 struct dc_mediainfo *m; 1627 1628 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1629 bzero(m, sizeof(struct dc_mediainfo)); 1630 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1631 m->dc_media = IFM_10_T; 1632 1633 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1634 m->dc_media = IFM_10_T|IFM_FDX; 1635 1636 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1637 m->dc_media = IFM_10_2; 1638 1639 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1640 m->dc_media = IFM_10_5; 1641 1642 m->dc_gp_len = 2; 1643 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1644 1645 m->dc_next = sc->dc_mi; 1646 sc->dc_mi = m; 1647 1648 sc->dc_pmode = DC_PMODE_SIA; 1649 1650 return; 1651 } 1652 1653 static void dc_decode_leaf_sym(sc, l) 1654 struct dc_softc *sc; 1655 struct dc_eblock_sym *l; 1656 { 1657 struct dc_mediainfo *m; 1658 1659 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1660 bzero(m, sizeof(struct dc_mediainfo)); 1661 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1662 m->dc_media = IFM_100_TX; 1663 1664 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1665 m->dc_media = IFM_100_TX|IFM_FDX; 1666 1667 m->dc_gp_len = 2; 1668 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1669 1670 m->dc_next = sc->dc_mi; 1671 sc->dc_mi = m; 1672 1673 sc->dc_pmode = DC_PMODE_SYM; 1674 1675 return; 1676 } 1677 1678 static void dc_decode_leaf_mii(sc, l) 1679 struct dc_softc *sc; 1680 struct dc_eblock_mii *l; 1681 { 1682 u_int8_t *p; 1683 struct dc_mediainfo *m; 1684 1685 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1686 bzero(m, sizeof(struct dc_mediainfo)); 1687 /* We abuse IFM_AUTO to represent MII. */ 1688 m->dc_media = IFM_AUTO; 1689 m->dc_gp_len = l->dc_gpr_len; 1690 1691 p = (u_int8_t *)l; 1692 p += sizeof(struct dc_eblock_mii); 1693 m->dc_gp_ptr = p; 1694 p += 2 * l->dc_gpr_len; 1695 m->dc_reset_len = *p; 1696 p++; 1697 m->dc_reset_ptr = p; 1698 1699 m->dc_next = sc->dc_mi; 1700 sc->dc_mi = m; 1701 1702 return; 1703 } 1704 1705 static void dc_read_srom(sc, bits) 1706 struct dc_softc *sc; 1707 int bits; 1708 { 1709 int size; 1710 1711 size = 2 << bits; 1712 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1713 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1714 } 1715 1716 static void dc_parse_21143_srom(sc) 1717 struct dc_softc *sc; 1718 { 1719 struct dc_leaf_hdr *lhdr; 1720 struct dc_eblock_hdr *hdr; 1721 int i, loff; 1722 char *ptr; 1723 int have_mii; 1724 1725 have_mii = 0; 1726 loff = sc->dc_srom[27]; 1727 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1728 1729 ptr = (char *)lhdr; 1730 ptr += sizeof(struct dc_leaf_hdr) - 1; 1731 /* 1732 * Look if we got a MII media block. 1733 */ 1734 for (i = 0; i < lhdr->dc_mcnt; i++) { 1735 hdr = (struct dc_eblock_hdr *)ptr; 1736 if (hdr->dc_type == DC_EBLOCK_MII) 1737 have_mii++; 1738 1739 ptr += (hdr->dc_len & 0x7F); 1740 ptr++; 1741 } 1742 1743 /* 1744 * Do the same thing again. Only use SIA and SYM media 1745 * blocks if no MII media block is available. 1746 */ 1747 ptr = (char *)lhdr; 1748 ptr += sizeof(struct dc_leaf_hdr) - 1; 1749 for (i = 0; i < lhdr->dc_mcnt; i++) { 1750 hdr = (struct dc_eblock_hdr *)ptr; 1751 switch(hdr->dc_type) { 1752 case DC_EBLOCK_MII: 1753 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1754 break; 1755 case DC_EBLOCK_SIA: 1756 if (! have_mii) 1757 dc_decode_leaf_sia(sc, 1758 (struct dc_eblock_sia *)hdr); 1759 break; 1760 case DC_EBLOCK_SYM: 1761 if (! have_mii) 1762 dc_decode_leaf_sym(sc, 1763 (struct dc_eblock_sym *)hdr); 1764 break; 1765 default: 1766 /* Don't care. Yet. */ 1767 break; 1768 } 1769 ptr += (hdr->dc_len & 0x7F); 1770 ptr++; 1771 } 1772 1773 return; 1774 } 1775 1776 /* 1777 * Attach the interface. Allocate softc structures, do ifmedia 1778 * setup and ethernet/BPF attach. 1779 */ 1780 static int dc_attach(dev) 1781 device_t dev; 1782 { 1783 int s, tmp = 0; 1784 u_char eaddr[ETHER_ADDR_LEN]; 1785 u_int32_t command; 1786 struct dc_softc *sc; 1787 struct ifnet *ifp; 1788 u_int32_t revision; 1789 int unit, error = 0, rid, mac_offset; 1790 1791 s = splimp(); 1792 1793 sc = device_get_softc(dev); 1794 unit = device_get_unit(dev); 1795 bzero(sc, sizeof(struct dc_softc)); 1796 1797 /* 1798 * Handle power management nonsense. 1799 */ 1800 dc_acpi(dev); 1801 1802 /* 1803 * Map control/status registers. 1804 */ 1805 command = pci_read_config(dev, PCIR_COMMAND, 4); 1806 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1807 pci_write_config(dev, PCIR_COMMAND, command, 4); 1808 command = pci_read_config(dev, PCIR_COMMAND, 4); 1809 1810 #ifdef DC_USEIOSPACE 1811 if (!(command & PCIM_CMD_PORTEN)) { 1812 printf("dc%d: failed to enable I/O ports!\n", unit); 1813 error = ENXIO; 1814 goto fail; 1815 } 1816 #else 1817 if (!(command & PCIM_CMD_MEMEN)) { 1818 printf("dc%d: failed to enable memory mapping!\n", unit); 1819 error = ENXIO; 1820 goto fail; 1821 } 1822 #endif 1823 1824 rid = DC_RID; 1825 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1826 0, ~0, 1, RF_ACTIVE); 1827 1828 if (sc->dc_res == NULL) { 1829 printf("dc%d: couldn't map ports/memory\n", unit); 1830 error = ENXIO; 1831 goto fail; 1832 } 1833 1834 sc->dc_btag = rman_get_bustag(sc->dc_res); 1835 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1836 1837 /* Allocate interrupt */ 1838 rid = 0; 1839 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1840 RF_SHAREABLE | RF_ACTIVE); 1841 1842 if (sc->dc_irq == NULL) { 1843 printf("dc%d: couldn't map interrupt\n", unit); 1844 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1845 error = ENXIO; 1846 goto fail; 1847 } 1848 1849 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1850 dc_intr, sc, &sc->dc_intrhand); 1851 1852 if (error) { 1853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1854 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1855 printf("dc%d: couldn't set up irq\n", unit); 1856 goto fail; 1857 } 1858 1859 /* Need this info to decide on a chip type. */ 1860 sc->dc_info = dc_devtype(dev); 1861 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1862 1863 /* Get the eeprom width, but PNIC has diff eeprom */ 1864 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1865 dc_eeprom_width(sc); 1866 1867 switch(sc->dc_info->dc_did) { 1868 case DC_DEVICEID_21143: 1869 sc->dc_type = DC_TYPE_21143; 1870 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1871 sc->dc_flags |= DC_REDUCED_MII_POLL; 1872 /* Save EEPROM contents so we can parse them later. */ 1873 dc_read_srom(sc, sc->dc_romwidth); 1874 break; 1875 case DC_DEVICEID_DM9009: 1876 case DC_DEVICEID_DM9100: 1877 case DC_DEVICEID_DM9102: 1878 sc->dc_type = DC_TYPE_DM9102; 1879 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1880 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1881 sc->dc_pmode = DC_PMODE_MII; 1882 /* Increase the latency timer value. */ 1883 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1884 command &= 0xFFFF00FF; 1885 command |= 0x00008000; 1886 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1887 break; 1888 case DC_DEVICEID_AL981: 1889 sc->dc_type = DC_TYPE_AL981; 1890 sc->dc_flags |= DC_TX_USE_TX_INTR; 1891 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1892 sc->dc_pmode = DC_PMODE_MII; 1893 dc_read_srom(sc, sc->dc_romwidth); 1894 break; 1895 case DC_DEVICEID_AN985: 1896 case DC_DEVICEID_EN2242: 1897 case DC_DEVICEID_3CSOHOB: 1898 sc->dc_type = DC_TYPE_AN985; 1899 sc->dc_flags |= DC_64BIT_HASH; 1900 sc->dc_flags |= DC_TX_USE_TX_INTR; 1901 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1902 sc->dc_pmode = DC_PMODE_MII; 1903 dc_read_srom(sc, sc->dc_romwidth); 1904 break; 1905 case DC_DEVICEID_98713: 1906 case DC_DEVICEID_98713_CP: 1907 if (revision < DC_REVISION_98713A) { 1908 sc->dc_type = DC_TYPE_98713; 1909 } 1910 if (revision >= DC_REVISION_98713A) { 1911 sc->dc_type = DC_TYPE_98713A; 1912 sc->dc_flags |= DC_21143_NWAY; 1913 } 1914 sc->dc_flags |= DC_REDUCED_MII_POLL; 1915 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1916 break; 1917 case DC_DEVICEID_987x5: 1918 case DC_DEVICEID_EN1217: 1919 /* 1920 * Macronix MX98715AEC-C/D/E parts have only a 1921 * 128-bit hash table. We need to deal with these 1922 * in the same manner as the PNIC II so that we 1923 * get the right number of bits out of the 1924 * CRC routine. 1925 */ 1926 if (revision >= DC_REVISION_98715AEC_C && 1927 revision < DC_REVISION_98725) 1928 sc->dc_flags |= DC_128BIT_HASH; 1929 sc->dc_type = DC_TYPE_987x5; 1930 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1931 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1932 break; 1933 case DC_DEVICEID_98727: 1934 sc->dc_type = DC_TYPE_987x5; 1935 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1936 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1937 break; 1938 case DC_DEVICEID_82C115: 1939 sc->dc_type = DC_TYPE_PNICII; 1940 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1941 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1942 break; 1943 case DC_DEVICEID_82C168: 1944 sc->dc_type = DC_TYPE_PNIC; 1945 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1946 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1947 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1948 if (revision < DC_REVISION_82C169) 1949 sc->dc_pmode = DC_PMODE_SYM; 1950 break; 1951 case DC_DEVICEID_AX88140A: 1952 sc->dc_type = DC_TYPE_ASIX; 1953 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL; 1955 sc->dc_pmode = DC_PMODE_MII; 1956 break; 1957 case DC_DEVICEID_RS7112: 1958 sc->dc_type = DC_TYPE_CONEXANT; 1959 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1960 sc->dc_flags |= DC_REDUCED_MII_POLL; 1961 sc->dc_pmode = DC_PMODE_MII; 1962 dc_read_srom(sc, sc->dc_romwidth); 1963 break; 1964 default: 1965 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1966 sc->dc_info->dc_did); 1967 break; 1968 } 1969 1970 /* Save the cache line size. */ 1971 if (DC_IS_DAVICOM(sc)) 1972 sc->dc_cachesize = 0; 1973 else 1974 sc->dc_cachesize = pci_read_config(dev, 1975 DC_PCI_CFLT, 4) & 0xFF; 1976 1977 /* Reset the adapter. */ 1978 dc_reset(sc); 1979 1980 /* Take 21143 out of snooze mode */ 1981 if (DC_IS_INTEL(sc)) { 1982 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1983 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1984 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1985 } 1986 1987 /* 1988 * Try to learn something about the supported media. 1989 * We know that ASIX and ADMtek and Davicom devices 1990 * will *always* be using MII media, so that's a no-brainer. 1991 * The tricky ones are the Macronix/PNIC II and the 1992 * Intel 21143. 1993 */ 1994 if (DC_IS_INTEL(sc)) 1995 dc_parse_21143_srom(sc); 1996 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1997 if (sc->dc_type == DC_TYPE_98713) 1998 sc->dc_pmode = DC_PMODE_MII; 1999 else 2000 sc->dc_pmode = DC_PMODE_SYM; 2001 } else if (!sc->dc_pmode) 2002 sc->dc_pmode = DC_PMODE_MII; 2003 2004 /* 2005 * Get station address from the EEPROM. 2006 */ 2007 switch(sc->dc_type) { 2008 case DC_TYPE_98713: 2009 case DC_TYPE_98713A: 2010 case DC_TYPE_987x5: 2011 case DC_TYPE_PNICII: 2012 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2013 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2014 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2015 break; 2016 case DC_TYPE_PNIC: 2017 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2018 break; 2019 case DC_TYPE_DM9102: 2020 case DC_TYPE_21143: 2021 case DC_TYPE_ASIX: 2022 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2023 break; 2024 case DC_TYPE_AL981: 2025 case DC_TYPE_AN985: 2026 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2027 ETHER_ADDR_LEN); 2028 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2029 break; 2030 case DC_TYPE_CONEXANT: 2031 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2032 break; 2033 default: 2034 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2035 break; 2036 } 2037 2038 /* 2039 * A 21143 or clone chip was detected. Inform the world. 2040 */ 2041 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2042 2043 sc->dc_unit = unit; 2044 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2045 2046 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2047 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2048 2049 if (sc->dc_ldata == NULL) { 2050 printf("dc%d: no memory for list buffers!\n", unit); 2051 if (sc->dc_pnic_rx_buf != NULL) 2052 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2053 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2054 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2055 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2056 error = ENXIO; 2057 goto fail; 2058 } 2059 2060 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2061 2062 ifp = &sc->arpcom.ac_if; 2063 ifp->if_softc = sc; 2064 ifp->if_unit = unit; 2065 ifp->if_name = "dc"; 2066 ifp->if_mtu = ETHERMTU; 2067 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2068 ifp->if_ioctl = dc_ioctl; 2069 ifp->if_output = ether_output; 2070 ifp->if_start = dc_start; 2071 ifp->if_watchdog = dc_watchdog; 2072 ifp->if_init = dc_init; 2073 ifp->if_baudrate = 10000000; 2074 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2075 2076 /* 2077 * Do MII setup. If this is a 21143, check for a PHY on the 2078 * MII bus after applying any necessary fixups to twiddle the 2079 * GPIO bits. If we don't end up finding a PHY, restore the 2080 * old selection (SIA only or SIA/SYM) and attach the dcphy 2081 * driver instead. 2082 */ 2083 if (DC_IS_INTEL(sc)) { 2084 dc_apply_fixup(sc, IFM_AUTO); 2085 tmp = sc->dc_pmode; 2086 sc->dc_pmode = DC_PMODE_MII; 2087 } 2088 2089 error = mii_phy_probe(dev, &sc->dc_miibus, 2090 dc_ifmedia_upd, dc_ifmedia_sts); 2091 2092 if (error && DC_IS_INTEL(sc)) { 2093 sc->dc_pmode = tmp; 2094 if (sc->dc_pmode != DC_PMODE_SIA) 2095 sc->dc_pmode = DC_PMODE_SYM; 2096 sc->dc_flags |= DC_21143_NWAY; 2097 mii_phy_probe(dev, &sc->dc_miibus, 2098 dc_ifmedia_upd, dc_ifmedia_sts); 2099 /* 2100 * For non-MII cards, we need to have the 21143 2101 * drive the LEDs. Except there are some systems 2102 * like the NEC VersaPro NoteBook PC which have no 2103 * LEDs, and twiddling these bits has adverse effects 2104 * on them. (I.e. you suddenly can't get a link.) 2105 */ 2106 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2107 sc->dc_flags |= DC_TULIP_LEDS; 2108 error = 0; 2109 } 2110 2111 if (error) { 2112 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2113 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), 2114 M_DEVBUF); 2115 if (sc->dc_pnic_rx_buf != NULL) 2116 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2117 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2118 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2119 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2120 error = ENXIO; 2121 goto fail; 2122 } 2123 2124 /* 2125 * Call MI attach routine. 2126 */ 2127 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2128 callout_handle_init(&sc->dc_stat_ch); 2129 2130 if (DC_IS_ADMTEK(sc)) { 2131 /* 2132 * Set automatic TX underrun recovery for the ADMtek chips 2133 */ 2134 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2135 } 2136 2137 /* 2138 * Tell the upper layer(s) we support long frames. 2139 */ 2140 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2141 2142 #ifdef SRM_MEDIA 2143 sc->dc_srm_media = 0; 2144 2145 /* Remember the SRM console media setting */ 2146 if (DC_IS_INTEL(sc)) { 2147 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2148 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2149 switch ((command >> 8) & 0xff) { 2150 case 3: 2151 sc->dc_srm_media = IFM_10_T; 2152 break; 2153 case 4: 2154 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2155 break; 2156 case 5: 2157 sc->dc_srm_media = IFM_100_TX; 2158 break; 2159 case 6: 2160 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2161 break; 2162 } 2163 if (sc->dc_srm_media) 2164 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2165 } 2166 #endif 2167 2168 2169 fail: 2170 splx(s); 2171 2172 return(error); 2173 } 2174 2175 static int dc_detach(dev) 2176 device_t dev; 2177 { 2178 struct dc_softc *sc; 2179 struct ifnet *ifp; 2180 int s; 2181 struct dc_mediainfo *m; 2182 2183 s = splimp(); 2184 2185 sc = device_get_softc(dev); 2186 ifp = &sc->arpcom.ac_if; 2187 2188 dc_stop(sc); 2189 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2190 2191 bus_generic_detach(dev); 2192 device_delete_child(dev, sc->dc_miibus); 2193 2194 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2195 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2196 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2197 2198 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2199 if (sc->dc_pnic_rx_buf != NULL) 2200 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2201 2202 while(sc->dc_mi != NULL) { 2203 m = sc->dc_mi->dc_next; 2204 free(sc->dc_mi, M_DEVBUF); 2205 sc->dc_mi = m; 2206 } 2207 free(sc->dc_srom, M_DEVBUF); 2208 2209 splx(s); 2210 2211 return(0); 2212 } 2213 2214 /* 2215 * Initialize the transmit descriptors. 2216 */ 2217 static int dc_list_tx_init(sc) 2218 struct dc_softc *sc; 2219 { 2220 struct dc_chain_data *cd; 2221 struct dc_list_data *ld; 2222 int i; 2223 2224 cd = &sc->dc_cdata; 2225 ld = sc->dc_ldata; 2226 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2227 if (i == (DC_TX_LIST_CNT - 1)) { 2228 ld->dc_tx_list[i].dc_next = 2229 vtophys(&ld->dc_tx_list[0]); 2230 } else { 2231 ld->dc_tx_list[i].dc_next = 2232 vtophys(&ld->dc_tx_list[i + 1]); 2233 } 2234 cd->dc_tx_chain[i] = NULL; 2235 ld->dc_tx_list[i].dc_data = 0; 2236 ld->dc_tx_list[i].dc_ctl = 0; 2237 } 2238 2239 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2240 2241 return(0); 2242 } 2243 2244 2245 /* 2246 * Initialize the RX descriptors and allocate mbufs for them. Note that 2247 * we arrange the descriptors in a closed ring, so that the last descriptor 2248 * points back to the first. 2249 */ 2250 static int dc_list_rx_init(sc) 2251 struct dc_softc *sc; 2252 { 2253 struct dc_chain_data *cd; 2254 struct dc_list_data *ld; 2255 int i; 2256 2257 cd = &sc->dc_cdata; 2258 ld = sc->dc_ldata; 2259 2260 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2261 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2262 return(ENOBUFS); 2263 if (i == (DC_RX_LIST_CNT - 1)) { 2264 ld->dc_rx_list[i].dc_next = 2265 vtophys(&ld->dc_rx_list[0]); 2266 } else { 2267 ld->dc_rx_list[i].dc_next = 2268 vtophys(&ld->dc_rx_list[i + 1]); 2269 } 2270 } 2271 2272 cd->dc_rx_prod = 0; 2273 2274 return(0); 2275 } 2276 2277 /* 2278 * Initialize an RX descriptor and attach an MBUF cluster. 2279 */ 2280 static int dc_newbuf(sc, i, m) 2281 struct dc_softc *sc; 2282 int i; 2283 struct mbuf *m; 2284 { 2285 struct mbuf *m_new = NULL; 2286 struct dc_desc *c; 2287 2288 c = &sc->dc_ldata->dc_rx_list[i]; 2289 2290 if (m == NULL) { 2291 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2292 if (m_new == NULL) 2293 return(ENOBUFS); 2294 2295 MCLGET(m_new, M_DONTWAIT); 2296 if (!(m_new->m_flags & M_EXT)) { 2297 m_freem(m_new); 2298 return(ENOBUFS); 2299 } 2300 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2301 } else { 2302 m_new = m; 2303 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2304 m_new->m_data = m_new->m_ext.ext_buf; 2305 } 2306 2307 m_adj(m_new, sizeof(u_int64_t)); 2308 2309 /* 2310 * If this is a PNIC chip, zero the buffer. This is part 2311 * of the workaround for the receive bug in the 82c168 and 2312 * 82c169 chips. 2313 */ 2314 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2315 bzero((char *)mtod(m_new, char *), m_new->m_len); 2316 2317 sc->dc_cdata.dc_rx_chain[i] = m_new; 2318 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2319 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2320 c->dc_status = DC_RXSTAT_OWN; 2321 2322 return(0); 2323 } 2324 2325 /* 2326 * Grrrrr. 2327 * The PNIC chip has a terrible bug in it that manifests itself during 2328 * periods of heavy activity. The exact mode of failure if difficult to 2329 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2330 * will happen on slow machines. The bug is that sometimes instead of 2331 * uploading one complete frame during reception, it uploads what looks 2332 * like the entire contents of its FIFO memory. The frame we want is at 2333 * the end of the whole mess, but we never know exactly how much data has 2334 * been uploaded, so salvaging the frame is hard. 2335 * 2336 * There is only one way to do it reliably, and it's disgusting. 2337 * Here's what we know: 2338 * 2339 * - We know there will always be somewhere between one and three extra 2340 * descriptors uploaded. 2341 * 2342 * - We know the desired received frame will always be at the end of the 2343 * total data upload. 2344 * 2345 * - We know the size of the desired received frame because it will be 2346 * provided in the length field of the status word in the last descriptor. 2347 * 2348 * Here's what we do: 2349 * 2350 * - When we allocate buffers for the receive ring, we bzero() them. 2351 * This means that we know that the buffer contents should be all 2352 * zeros, except for data uploaded by the chip. 2353 * 2354 * - We also force the PNIC chip to upload frames that include the 2355 * ethernet CRC at the end. 2356 * 2357 * - We gather all of the bogus frame data into a single buffer. 2358 * 2359 * - We then position a pointer at the end of this buffer and scan 2360 * backwards until we encounter the first non-zero byte of data. 2361 * This is the end of the received frame. We know we will encounter 2362 * some data at the end of the frame because the CRC will always be 2363 * there, so even if the sender transmits a packet of all zeros, 2364 * we won't be fooled. 2365 * 2366 * - We know the size of the actual received frame, so we subtract 2367 * that value from the current pointer location. This brings us 2368 * to the start of the actual received packet. 2369 * 2370 * - We copy this into an mbuf and pass it on, along with the actual 2371 * frame length. 2372 * 2373 * The performance hit is tremendous, but it beats dropping frames all 2374 * the time. 2375 */ 2376 2377 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2378 static void dc_pnic_rx_bug_war(sc, idx) 2379 struct dc_softc *sc; 2380 int idx; 2381 { 2382 struct dc_desc *cur_rx; 2383 struct dc_desc *c = NULL; 2384 struct mbuf *m = NULL; 2385 unsigned char *ptr; 2386 int i, total_len; 2387 u_int32_t rxstat = 0; 2388 2389 i = sc->dc_pnic_rx_bug_save; 2390 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2391 ptr = sc->dc_pnic_rx_buf; 2392 bzero(ptr, DC_RXLEN * 5); 2393 2394 /* Copy all the bytes from the bogus buffers. */ 2395 while (1) { 2396 c = &sc->dc_ldata->dc_rx_list[i]; 2397 rxstat = c->dc_status; 2398 m = sc->dc_cdata.dc_rx_chain[i]; 2399 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2400 ptr += DC_RXLEN; 2401 /* If this is the last buffer, break out. */ 2402 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2403 break; 2404 dc_newbuf(sc, i, m); 2405 DC_INC(i, DC_RX_LIST_CNT); 2406 } 2407 2408 /* Find the length of the actual receive frame. */ 2409 total_len = DC_RXBYTES(rxstat); 2410 2411 /* Scan backwards until we hit a non-zero byte. */ 2412 while(*ptr == 0x00) 2413 ptr--; 2414 2415 /* Round off. */ 2416 if ((uintptr_t)(ptr) & 0x3) 2417 ptr -= 1; 2418 2419 /* Now find the start of the frame. */ 2420 ptr -= total_len; 2421 if (ptr < sc->dc_pnic_rx_buf) 2422 ptr = sc->dc_pnic_rx_buf; 2423 2424 /* 2425 * Now copy the salvaged frame to the last mbuf and fake up 2426 * the status word to make it look like a successful 2427 * frame reception. 2428 */ 2429 dc_newbuf(sc, i, m); 2430 bcopy(ptr, mtod(m, char *), total_len); 2431 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2432 2433 return; 2434 } 2435 2436 /* 2437 * This routine searches the RX ring for dirty descriptors in the 2438 * event that the rxeof routine falls out of sync with the chip's 2439 * current descriptor pointer. This may happen sometimes as a result 2440 * of a "no RX buffer available" condition that happens when the chip 2441 * consumes all of the RX buffers before the driver has a chance to 2442 * process the RX ring. This routine may need to be called more than 2443 * once to bring the driver back in sync with the chip, however we 2444 * should still be getting RX DONE interrupts to drive the search 2445 * for new packets in the RX ring, so we should catch up eventually. 2446 */ 2447 static int dc_rx_resync(sc) 2448 struct dc_softc *sc; 2449 { 2450 int i, pos; 2451 struct dc_desc *cur_rx; 2452 2453 pos = sc->dc_cdata.dc_rx_prod; 2454 2455 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2456 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2457 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2458 break; 2459 DC_INC(pos, DC_RX_LIST_CNT); 2460 } 2461 2462 /* If the ring really is empty, then just return. */ 2463 if (i == DC_RX_LIST_CNT) 2464 return(0); 2465 2466 /* We've fallen behing the chip: catch it. */ 2467 sc->dc_cdata.dc_rx_prod = pos; 2468 2469 return(EAGAIN); 2470 } 2471 2472 /* 2473 * A frame has been uploaded: pass the resulting mbuf chain up to 2474 * the higher level protocols. 2475 */ 2476 static void dc_rxeof(sc) 2477 struct dc_softc *sc; 2478 { 2479 struct ether_header *eh; 2480 struct mbuf *m; 2481 struct ifnet *ifp; 2482 struct dc_desc *cur_rx; 2483 int i, total_len = 0; 2484 u_int32_t rxstat; 2485 2486 ifp = &sc->arpcom.ac_if; 2487 i = sc->dc_cdata.dc_rx_prod; 2488 2489 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2490 2491 #ifdef DEVICE_POLLING 2492 if (ifp->if_ipending & IFF_POLLING) { 2493 if (sc->rxcycles <= 0) 2494 break; 2495 sc->rxcycles--; 2496 } 2497 #endif /* DEVICE_POLLING */ 2498 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2499 rxstat = cur_rx->dc_status; 2500 m = sc->dc_cdata.dc_rx_chain[i]; 2501 total_len = DC_RXBYTES(rxstat); 2502 2503 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2504 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2505 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2506 sc->dc_pnic_rx_bug_save = i; 2507 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2508 DC_INC(i, DC_RX_LIST_CNT); 2509 continue; 2510 } 2511 dc_pnic_rx_bug_war(sc, i); 2512 rxstat = cur_rx->dc_status; 2513 total_len = DC_RXBYTES(rxstat); 2514 } 2515 } 2516 2517 sc->dc_cdata.dc_rx_chain[i] = NULL; 2518 2519 /* 2520 * If an error occurs, update stats, clear the 2521 * status word and leave the mbuf cluster in place: 2522 * it should simply get re-used next time this descriptor 2523 * comes up in the ring. However, don't report long 2524 * frames as errors since they could be vlans 2525 */ 2526 if ((rxstat & DC_RXSTAT_RXERR)){ 2527 if (!(rxstat & DC_RXSTAT_GIANT) || 2528 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2529 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2530 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2531 ifp->if_ierrors++; 2532 if (rxstat & DC_RXSTAT_COLLSEEN) 2533 ifp->if_collisions++; 2534 dc_newbuf(sc, i, m); 2535 if (rxstat & DC_RXSTAT_CRCERR) { 2536 DC_INC(i, DC_RX_LIST_CNT); 2537 continue; 2538 } else { 2539 dc_init(sc); 2540 return; 2541 } 2542 } 2543 } 2544 2545 /* No errors; receive the packet. */ 2546 total_len -= ETHER_CRC_LEN; 2547 2548 #ifdef __i386__ 2549 /* 2550 * On the x86 we do not have alignment problems, so try to 2551 * allocate a new buffer for the receive ring, and pass up 2552 * the one where the packet is already, saving the expensive 2553 * copy done in m_devget(). 2554 * If we are on an architecture with alignment problems, or 2555 * if the allocation fails, then use m_devget and leave the 2556 * existing buffer in the receive ring. 2557 */ 2558 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2559 m->m_pkthdr.rcvif = ifp; 2560 m->m_pkthdr.len = m->m_len = total_len; 2561 DC_INC(i, DC_RX_LIST_CNT); 2562 } else 2563 #endif 2564 { 2565 struct mbuf *m0; 2566 2567 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2568 total_len + ETHER_ALIGN, 0, ifp, NULL); 2569 dc_newbuf(sc, i, m); 2570 DC_INC(i, DC_RX_LIST_CNT); 2571 if (m0 == NULL) { 2572 ifp->if_ierrors++; 2573 continue; 2574 } 2575 m_adj(m0, ETHER_ALIGN); 2576 m = m0; 2577 } 2578 2579 ifp->if_ipackets++; 2580 eh = mtod(m, struct ether_header *); 2581 2582 /* Remove header from mbuf and pass it on. */ 2583 m_adj(m, sizeof(struct ether_header)); 2584 ether_input(ifp, eh, m); 2585 } 2586 2587 sc->dc_cdata.dc_rx_prod = i; 2588 } 2589 2590 /* 2591 * A frame was downloaded to the chip. It's safe for us to clean up 2592 * the list buffers. 2593 */ 2594 2595 static void 2596 dc_txeof(sc) 2597 struct dc_softc *sc; 2598 { 2599 struct dc_desc *cur_tx = NULL; 2600 struct ifnet *ifp; 2601 int idx; 2602 2603 ifp = &sc->arpcom.ac_if; 2604 2605 /* 2606 * Go through our tx list and free mbufs for those 2607 * frames that have been transmitted. 2608 */ 2609 idx = sc->dc_cdata.dc_tx_cons; 2610 while(idx != sc->dc_cdata.dc_tx_prod) { 2611 u_int32_t txstat; 2612 2613 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2614 txstat = cur_tx->dc_status; 2615 2616 if (txstat & DC_TXSTAT_OWN) 2617 break; 2618 2619 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2620 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2621 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2622 /* 2623 * Yes, the PNIC is so brain damaged 2624 * that it will sometimes generate a TX 2625 * underrun error while DMAing the RX 2626 * filter setup frame. If we detect this, 2627 * we have to send the setup frame again, 2628 * or else the filter won't be programmed 2629 * correctly. 2630 */ 2631 if (DC_IS_PNIC(sc)) { 2632 if (txstat & DC_TXSTAT_ERRSUM) 2633 dc_setfilt(sc); 2634 } 2635 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2636 } 2637 sc->dc_cdata.dc_tx_cnt--; 2638 DC_INC(idx, DC_TX_LIST_CNT); 2639 continue; 2640 } 2641 2642 if (DC_IS_CONEXANT(sc)) { 2643 /* 2644 * For some reason Conexant chips like 2645 * setting the CARRLOST flag even when 2646 * the carrier is there. In CURRENT we 2647 * have the same problem for Xircom 2648 * cards ! 2649 */ 2650 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2651 sc->dc_pmode == DC_PMODE_MII && 2652 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2653 DC_TXSTAT_NOCARRIER))) 2654 txstat &= ~DC_TXSTAT_ERRSUM; 2655 } else { 2656 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2657 sc->dc_pmode == DC_PMODE_MII && 2658 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2659 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2660 txstat &= ~DC_TXSTAT_ERRSUM; 2661 } 2662 2663 if (txstat & DC_TXSTAT_ERRSUM) { 2664 ifp->if_oerrors++; 2665 if (txstat & DC_TXSTAT_EXCESSCOLL) 2666 ifp->if_collisions++; 2667 if (txstat & DC_TXSTAT_LATECOLL) 2668 ifp->if_collisions++; 2669 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2670 dc_init(sc); 2671 return; 2672 } 2673 } 2674 2675 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2676 2677 ifp->if_opackets++; 2678 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2679 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2680 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2681 } 2682 2683 sc->dc_cdata.dc_tx_cnt--; 2684 DC_INC(idx, DC_TX_LIST_CNT); 2685 } 2686 2687 if (idx != sc->dc_cdata.dc_tx_cons) { 2688 /* some buffers have been freed */ 2689 sc->dc_cdata.dc_tx_cons = idx; 2690 ifp->if_flags &= ~IFF_OACTIVE; 2691 } 2692 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2693 2694 return; 2695 } 2696 2697 static void dc_tick(xsc) 2698 void *xsc; 2699 { 2700 struct dc_softc *sc; 2701 struct mii_data *mii; 2702 struct ifnet *ifp; 2703 int s; 2704 u_int32_t r; 2705 2706 s = splimp(); 2707 2708 sc = xsc; 2709 ifp = &sc->arpcom.ac_if; 2710 mii = device_get_softc(sc->dc_miibus); 2711 2712 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2713 if (sc->dc_flags & DC_21143_NWAY) { 2714 r = CSR_READ_4(sc, DC_10BTSTAT); 2715 if (IFM_SUBTYPE(mii->mii_media_active) == 2716 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2717 sc->dc_link = 0; 2718 mii_mediachg(mii); 2719 } 2720 if (IFM_SUBTYPE(mii->mii_media_active) == 2721 IFM_10_T && (r & DC_TSTAT_LS10)) { 2722 sc->dc_link = 0; 2723 mii_mediachg(mii); 2724 } 2725 if (sc->dc_link == 0) 2726 mii_tick(mii); 2727 } else { 2728 r = CSR_READ_4(sc, DC_ISR); 2729 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2730 sc->dc_cdata.dc_tx_cnt == 0) 2731 mii_tick(mii); 2732 if (!(mii->mii_media_status & IFM_ACTIVE)) 2733 sc->dc_link = 0; 2734 } 2735 } else 2736 mii_tick(mii); 2737 2738 /* 2739 * When the init routine completes, we expect to be able to send 2740 * packets right away, and in fact the network code will send a 2741 * gratuitous ARP the moment the init routine marks the interface 2742 * as running. However, even though the MAC may have been initialized, 2743 * there may be a delay of a few seconds before the PHY completes 2744 * autonegotiation and the link is brought up. Any transmissions 2745 * made during that delay will be lost. Dealing with this is tricky: 2746 * we can't just pause in the init routine while waiting for the 2747 * PHY to come ready since that would bring the whole system to 2748 * a screeching halt for several seconds. 2749 * 2750 * What we do here is prevent the TX start routine from sending 2751 * any packets until a link has been established. After the 2752 * interface has been initialized, the tick routine will poll 2753 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2754 * that time, packets will stay in the send queue, and once the 2755 * link comes up, they will be flushed out to the wire. 2756 */ 2757 if (!sc->dc_link) { 2758 mii_pollstat(mii); 2759 if (mii->mii_media_status & IFM_ACTIVE && 2760 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2761 sc->dc_link++; 2762 if (ifp->if_snd.ifq_head != NULL) 2763 dc_start(ifp); 2764 } 2765 } 2766 2767 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2768 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2769 else 2770 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2771 2772 splx(s); 2773 2774 return; 2775 } 2776 2777 /* 2778 * A transmit underrun has occurred. Back off the transmit threshold, 2779 * or switch to store and forward mode if we have to. 2780 */ 2781 static void dc_tx_underrun(sc) 2782 struct dc_softc *sc; 2783 { 2784 u_int32_t isr; 2785 int i; 2786 2787 if (DC_IS_DAVICOM(sc)) 2788 dc_init(sc); 2789 2790 if (DC_IS_INTEL(sc)) { 2791 /* 2792 * The real 21143 requires that the transmitter be idle 2793 * in order to change the transmit threshold or store 2794 * and forward state. 2795 */ 2796 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2797 2798 for (i = 0; i < DC_TIMEOUT; i++) { 2799 isr = CSR_READ_4(sc, DC_ISR); 2800 if (isr & DC_ISR_TX_IDLE) 2801 break; 2802 DELAY(10); 2803 } 2804 if (i == DC_TIMEOUT) { 2805 printf("dc%d: failed to force tx to idle state\n", 2806 sc->dc_unit); 2807 dc_init(sc); 2808 } 2809 } 2810 2811 printf("dc%d: TX underrun -- ", sc->dc_unit); 2812 sc->dc_txthresh += DC_TXTHRESH_INC; 2813 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2814 printf("using store and forward mode\n"); 2815 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2816 } else { 2817 printf("increasing TX threshold\n"); 2818 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2819 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2820 } 2821 2822 if (DC_IS_INTEL(sc)) 2823 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2824 2825 return; 2826 } 2827 2828 #ifdef DEVICE_POLLING 2829 static poll_handler_t dc_poll; 2830 2831 static void 2832 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2833 { 2834 struct dc_softc *sc = ifp->if_softc; 2835 2836 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2837 /* Re-enable interrupts. */ 2838 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2839 return; 2840 } 2841 sc->rxcycles = count; 2842 dc_rxeof(sc); 2843 dc_txeof(sc); 2844 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2845 dc_start(ifp); 2846 2847 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2848 u_int32_t status; 2849 2850 status = CSR_READ_4(sc, DC_ISR); 2851 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2852 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2853 DC_ISR_BUS_ERR); 2854 if (!status) 2855 return ; 2856 /* ack what we have */ 2857 CSR_WRITE_4(sc, DC_ISR, status); 2858 2859 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2860 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2861 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2862 2863 if (dc_rx_resync(sc)) 2864 dc_rxeof(sc); 2865 } 2866 /* restart transmit unit if necessary */ 2867 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2868 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2869 2870 if (status & DC_ISR_TX_UNDERRUN) 2871 dc_tx_underrun(sc); 2872 2873 if (status & DC_ISR_BUS_ERR) { 2874 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2875 dc_reset(sc); 2876 dc_init(sc); 2877 } 2878 } 2879 } 2880 #endif /* DEVICE_POLLING */ 2881 2882 static void dc_intr(arg) 2883 void *arg; 2884 { 2885 struct dc_softc *sc; 2886 struct ifnet *ifp; 2887 u_int32_t status; 2888 2889 sc = arg; 2890 2891 if (sc->suspended) { 2892 return; 2893 } 2894 2895 ifp = &sc->arpcom.ac_if; 2896 2897 #ifdef DEVICE_POLLING 2898 if (ifp->if_ipending & IFF_POLLING) 2899 return; 2900 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2901 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2902 return; 2903 } 2904 #endif /* DEVICE_POLLING */ 2905 2906 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2907 return ; 2908 2909 /* Suppress unwanted interrupts */ 2910 if (!(ifp->if_flags & IFF_UP)) { 2911 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2912 dc_stop(sc); 2913 return; 2914 } 2915 2916 /* Disable interrupts. */ 2917 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2918 2919 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2920 2921 CSR_WRITE_4(sc, DC_ISR, status); 2922 2923 if (status & DC_ISR_RX_OK) { 2924 int curpkts; 2925 curpkts = ifp->if_ipackets; 2926 dc_rxeof(sc); 2927 if (curpkts == ifp->if_ipackets) { 2928 while(dc_rx_resync(sc)) 2929 dc_rxeof(sc); 2930 } 2931 } 2932 2933 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2934 dc_txeof(sc); 2935 2936 if (status & DC_ISR_TX_IDLE) { 2937 dc_txeof(sc); 2938 if (sc->dc_cdata.dc_tx_cnt) { 2939 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2940 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2941 } 2942 } 2943 2944 if (status & DC_ISR_TX_UNDERRUN) 2945 dc_tx_underrun(sc); 2946 2947 if ((status & DC_ISR_RX_WATDOGTIMEO) 2948 || (status & DC_ISR_RX_NOBUF)) { 2949 int curpkts; 2950 curpkts = ifp->if_ipackets; 2951 dc_rxeof(sc); 2952 if (curpkts == ifp->if_ipackets) { 2953 while(dc_rx_resync(sc)) 2954 dc_rxeof(sc); 2955 } 2956 } 2957 2958 if (status & DC_ISR_BUS_ERR) { 2959 dc_reset(sc); 2960 dc_init(sc); 2961 } 2962 } 2963 2964 /* Re-enable interrupts. */ 2965 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2966 2967 if (ifp->if_snd.ifq_head != NULL) 2968 dc_start(ifp); 2969 2970 return; 2971 } 2972 2973 /* 2974 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2975 * pointers to the fragment pointers. 2976 */ 2977 static int dc_encap(sc, m_head, txidx) 2978 struct dc_softc *sc; 2979 struct mbuf *m_head; 2980 u_int32_t *txidx; 2981 { 2982 struct dc_desc *f = NULL; 2983 struct mbuf *m; 2984 int frag, cur, cnt = 0; 2985 2986 /* 2987 * Start packing the mbufs in this chain into 2988 * the fragment pointers. Stop when we run out 2989 * of fragments or hit the end of the mbuf chain. 2990 */ 2991 m = m_head; 2992 cur = frag = *txidx; 2993 2994 for (m = m_head; m != NULL; m = m->m_next) { 2995 if (m->m_len != 0) { 2996 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2997 if (*txidx != sc->dc_cdata.dc_tx_prod && 2998 frag == (DC_TX_LIST_CNT - 1)) 2999 return(ENOBUFS); 3000 } 3001 if ((DC_TX_LIST_CNT - 3002 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3003 return(ENOBUFS); 3004 3005 f = &sc->dc_ldata->dc_tx_list[frag]; 3006 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3007 if (cnt == 0) { 3008 f->dc_status = 0; 3009 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3010 } else 3011 f->dc_status = DC_TXSTAT_OWN; 3012 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3013 cur = frag; 3014 DC_INC(frag, DC_TX_LIST_CNT); 3015 cnt++; 3016 } 3017 } 3018 3019 if (m != NULL) 3020 return(ENOBUFS); 3021 3022 sc->dc_cdata.dc_tx_cnt += cnt; 3023 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3024 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3025 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3026 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3027 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3028 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3029 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3030 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3031 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3032 *txidx = frag; 3033 3034 return(0); 3035 } 3036 3037 /* 3038 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3039 * Needed for some really badly behaved chips that just can't 3040 * do scatter/gather correctly. 3041 */ 3042 static int dc_coal(sc, m_head) 3043 struct dc_softc *sc; 3044 struct mbuf **m_head; 3045 { 3046 struct mbuf *m_new, *m; 3047 3048 m = *m_head; 3049 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3050 if (m_new == NULL) 3051 return(ENOBUFS); 3052 if (m->m_pkthdr.len > MHLEN) { 3053 MCLGET(m_new, M_DONTWAIT); 3054 if (!(m_new->m_flags & M_EXT)) { 3055 m_freem(m_new); 3056 return(ENOBUFS); 3057 } 3058 } 3059 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3060 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3061 m_freem(m); 3062 *m_head = m_new; 3063 3064 return(0); 3065 } 3066 3067 /* 3068 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3069 * to the mbuf data regions directly in the transmit lists. We also save a 3070 * copy of the pointers since the transmit list fragment pointers are 3071 * physical addresses. 3072 */ 3073 3074 static void dc_start(ifp) 3075 struct ifnet *ifp; 3076 { 3077 struct dc_softc *sc; 3078 struct mbuf *m_head = NULL; 3079 int idx; 3080 3081 sc = ifp->if_softc; 3082 3083 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3084 return; 3085 3086 if (ifp->if_flags & IFF_OACTIVE) 3087 return; 3088 3089 idx = sc->dc_cdata.dc_tx_prod; 3090 3091 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3092 IF_DEQUEUE(&ifp->if_snd, m_head); 3093 if (m_head == NULL) 3094 break; 3095 3096 if (sc->dc_flags & DC_TX_COALESCE && 3097 m_head->m_next != NULL) { 3098 /* only coalesce if have >1 mbufs */ 3099 if (dc_coal(sc, &m_head)) { 3100 IF_PREPEND(&ifp->if_snd, m_head); 3101 ifp->if_flags |= IFF_OACTIVE; 3102 break; 3103 } 3104 } 3105 3106 if (dc_encap(sc, m_head, &idx)) { 3107 IF_PREPEND(&ifp->if_snd, m_head); 3108 ifp->if_flags |= IFF_OACTIVE; 3109 break; 3110 } 3111 3112 /* 3113 * If there's a BPF listener, bounce a copy of this frame 3114 * to him. 3115 */ 3116 if (ifp->if_bpf) 3117 bpf_mtap(ifp, m_head); 3118 3119 if (sc->dc_flags & DC_TX_ONE) { 3120 ifp->if_flags |= IFF_OACTIVE; 3121 break; 3122 } 3123 } 3124 3125 /* Transmit */ 3126 sc->dc_cdata.dc_tx_prod = idx; 3127 if (!(sc->dc_flags & DC_TX_POLL)) 3128 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3129 3130 /* 3131 * Set a timeout in case the chip goes out to lunch. 3132 */ 3133 ifp->if_timer = 5; 3134 3135 return; 3136 } 3137 3138 static void dc_init(xsc) 3139 void *xsc; 3140 { 3141 struct dc_softc *sc = xsc; 3142 struct ifnet *ifp = &sc->arpcom.ac_if; 3143 struct mii_data *mii; 3144 int s; 3145 3146 s = splimp(); 3147 3148 mii = device_get_softc(sc->dc_miibus); 3149 3150 /* 3151 * Cancel pending I/O and free all RX/TX buffers. 3152 */ 3153 dc_stop(sc); 3154 dc_reset(sc); 3155 3156 /* 3157 * Set cache alignment and burst length. 3158 */ 3159 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3160 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3161 else 3162 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3163 /* 3164 * Evenly share the bus between receive and transmit process. 3165 */ 3166 if (DC_IS_INTEL(sc)) 3167 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3168 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3169 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3170 } else { 3171 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3172 } 3173 if (sc->dc_flags & DC_TX_POLL) 3174 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3175 switch(sc->dc_cachesize) { 3176 case 32: 3177 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3178 break; 3179 case 16: 3180 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3181 break; 3182 case 8: 3183 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3184 break; 3185 case 0: 3186 default: 3187 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3188 break; 3189 } 3190 3191 if (sc->dc_flags & DC_TX_STORENFWD) 3192 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3193 else { 3194 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3195 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3196 } else { 3197 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3198 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3199 } 3200 } 3201 3202 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3203 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3204 3205 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3206 /* 3207 * The app notes for the 98713 and 98715A say that 3208 * in order to have the chips operate properly, a magic 3209 * number must be written to CSR16. Macronix does not 3210 * document the meaning of these bits so there's no way 3211 * to know exactly what they do. The 98713 has a magic 3212 * number all its own; the rest all use a different one. 3213 */ 3214 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3215 if (sc->dc_type == DC_TYPE_98713) 3216 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3217 else 3218 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3219 } 3220 3221 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3222 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3223 3224 /* Init circular RX list. */ 3225 if (dc_list_rx_init(sc) == ENOBUFS) { 3226 printf("dc%d: initialization failed: no " 3227 "memory for rx buffers\n", sc->dc_unit); 3228 dc_stop(sc); 3229 (void)splx(s); 3230 return; 3231 } 3232 3233 /* 3234 * Init tx descriptors. 3235 */ 3236 dc_list_tx_init(sc); 3237 3238 /* 3239 * Load the address of the RX list. 3240 */ 3241 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3242 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3243 3244 /* 3245 * Enable interrupts. 3246 */ 3247 #ifdef DEVICE_POLLING 3248 /* 3249 * ... but only if we are not polling, and make sure they are off in 3250 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3251 * after a reset. 3252 */ 3253 if (ifp->if_ipending & IFF_POLLING) 3254 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3255 else 3256 #endif 3257 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3258 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3259 3260 /* Enable transmitter. */ 3261 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3262 3263 /* 3264 * If this is an Intel 21143 and we're not using the 3265 * MII port, program the LED control pins so we get 3266 * link and activity indications. 3267 */ 3268 if (sc->dc_flags & DC_TULIP_LEDS) { 3269 CSR_WRITE_4(sc, DC_WATCHDOG, 3270 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3271 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3272 } 3273 3274 /* 3275 * Load the RX/multicast filter. We do this sort of late 3276 * because the filter programming scheme on the 21143 and 3277 * some clones requires DMAing a setup frame via the TX 3278 * engine, and we need the transmitter enabled for that. 3279 */ 3280 dc_setfilt(sc); 3281 3282 /* Enable receiver. */ 3283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3284 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3285 3286 mii_mediachg(mii); 3287 dc_setcfg(sc, sc->dc_if_media); 3288 3289 ifp->if_flags |= IFF_RUNNING; 3290 ifp->if_flags &= ~IFF_OACTIVE; 3291 3292 (void)splx(s); 3293 3294 /* Don't start the ticker if this is a homePNA link. */ 3295 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3296 sc->dc_link = 1; 3297 else { 3298 if (sc->dc_flags & DC_21143_NWAY) 3299 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 3300 else 3301 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 3302 } 3303 3304 #ifdef SRM_MEDIA 3305 if(sc->dc_srm_media) { 3306 struct ifreq ifr; 3307 3308 ifr.ifr_media = sc->dc_srm_media; 3309 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3310 sc->dc_srm_media = 0; 3311 } 3312 #endif 3313 return; 3314 } 3315 3316 /* 3317 * Set media options. 3318 */ 3319 static int dc_ifmedia_upd(ifp) 3320 struct ifnet *ifp; 3321 { 3322 struct dc_softc *sc; 3323 struct mii_data *mii; 3324 struct ifmedia *ifm; 3325 3326 sc = ifp->if_softc; 3327 mii = device_get_softc(sc->dc_miibus); 3328 mii_mediachg(mii); 3329 ifm = &mii->mii_media; 3330 3331 if (DC_IS_DAVICOM(sc) && 3332 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3333 dc_setcfg(sc, ifm->ifm_media); 3334 else 3335 sc->dc_link = 0; 3336 3337 return(0); 3338 } 3339 3340 /* 3341 * Report current media status. 3342 */ 3343 static void dc_ifmedia_sts(ifp, ifmr) 3344 struct ifnet *ifp; 3345 struct ifmediareq *ifmr; 3346 { 3347 struct dc_softc *sc; 3348 struct mii_data *mii; 3349 struct ifmedia *ifm; 3350 3351 sc = ifp->if_softc; 3352 mii = device_get_softc(sc->dc_miibus); 3353 mii_pollstat(mii); 3354 ifm = &mii->mii_media; 3355 if (DC_IS_DAVICOM(sc)) { 3356 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3357 ifmr->ifm_active = ifm->ifm_media; 3358 ifmr->ifm_status = 0; 3359 return; 3360 } 3361 } 3362 ifmr->ifm_active = mii->mii_media_active; 3363 ifmr->ifm_status = mii->mii_media_status; 3364 3365 return; 3366 } 3367 3368 static int dc_ioctl(ifp, command, data) 3369 struct ifnet *ifp; 3370 u_long command; 3371 caddr_t data; 3372 { 3373 struct dc_softc *sc = ifp->if_softc; 3374 struct ifreq *ifr = (struct ifreq *) data; 3375 struct mii_data *mii; 3376 int s, error = 0; 3377 3378 s = splimp(); 3379 3380 switch(command) { 3381 case SIOCSIFADDR: 3382 case SIOCGIFADDR: 3383 case SIOCSIFMTU: 3384 error = ether_ioctl(ifp, command, data); 3385 break; 3386 case SIOCSIFFLAGS: 3387 if (ifp->if_flags & IFF_UP) { 3388 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3389 (IFF_PROMISC | IFF_ALLMULTI); 3390 if (ifp->if_flags & IFF_RUNNING) { 3391 if (need_setfilt) 3392 dc_setfilt(sc); 3393 } else { 3394 sc->dc_txthresh = 0; 3395 dc_init(sc); 3396 } 3397 } else { 3398 if (ifp->if_flags & IFF_RUNNING) 3399 dc_stop(sc); 3400 } 3401 sc->dc_if_flags = ifp->if_flags; 3402 error = 0; 3403 break; 3404 case SIOCADDMULTI: 3405 case SIOCDELMULTI: 3406 dc_setfilt(sc); 3407 error = 0; 3408 break; 3409 case SIOCGIFMEDIA: 3410 case SIOCSIFMEDIA: 3411 mii = device_get_softc(sc->dc_miibus); 3412 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3413 #ifdef SRM_MEDIA 3414 if (sc->dc_srm_media) 3415 sc->dc_srm_media = 0; 3416 #endif 3417 break; 3418 default: 3419 error = EINVAL; 3420 break; 3421 } 3422 3423 (void)splx(s); 3424 3425 return(error); 3426 } 3427 3428 static void dc_watchdog(ifp) 3429 struct ifnet *ifp; 3430 { 3431 struct dc_softc *sc; 3432 3433 sc = ifp->if_softc; 3434 3435 ifp->if_oerrors++; 3436 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3437 3438 dc_stop(sc); 3439 dc_reset(sc); 3440 dc_init(sc); 3441 3442 if (ifp->if_snd.ifq_head != NULL) 3443 dc_start(ifp); 3444 3445 return; 3446 } 3447 3448 /* 3449 * Stop the adapter and free any mbufs allocated to the 3450 * RX and TX lists. 3451 */ 3452 static void dc_stop(sc) 3453 struct dc_softc *sc; 3454 { 3455 register int i; 3456 struct ifnet *ifp; 3457 3458 ifp = &sc->arpcom.ac_if; 3459 ifp->if_timer = 0; 3460 3461 untimeout(dc_tick, sc, sc->dc_stat_ch); 3462 3463 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3464 #ifdef DEVICE_POLLING 3465 ether_poll_deregister(ifp); 3466 #endif 3467 3468 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3469 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3470 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3471 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3472 sc->dc_link = 0; 3473 3474 /* 3475 * Free data in the RX lists. 3476 */ 3477 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3478 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3479 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3480 sc->dc_cdata.dc_rx_chain[i] = NULL; 3481 } 3482 } 3483 bzero((char *)&sc->dc_ldata->dc_rx_list, 3484 sizeof(sc->dc_ldata->dc_rx_list)); 3485 3486 /* 3487 * Free the TX list buffers. 3488 */ 3489 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3490 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3491 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3492 DC_TXCTL_SETUP) { 3493 sc->dc_cdata.dc_tx_chain[i] = NULL; 3494 continue; 3495 } 3496 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3497 sc->dc_cdata.dc_tx_chain[i] = NULL; 3498 } 3499 } 3500 3501 bzero((char *)&sc->dc_ldata->dc_tx_list, 3502 sizeof(sc->dc_ldata->dc_tx_list)); 3503 3504 return; 3505 } 3506 3507 /* 3508 * Stop all chip I/O so that the kernel's probe routines don't 3509 * get confused by errant DMAs when rebooting. 3510 */ 3511 static void dc_shutdown(dev) 3512 device_t dev; 3513 { 3514 struct dc_softc *sc; 3515 3516 sc = device_get_softc(dev); 3517 3518 dc_stop(sc); 3519 3520 return; 3521 } 3522 3523 /* 3524 * Device suspend routine. Stop the interface and save some PCI 3525 * settings in case the BIOS doesn't restore them properly on 3526 * resume. 3527 */ 3528 static int dc_suspend(dev) 3529 device_t dev; 3530 { 3531 register int i; 3532 int s; 3533 struct dc_softc *sc; 3534 3535 s = splimp(); 3536 3537 sc = device_get_softc(dev); 3538 3539 dc_stop(sc); 3540 3541 for (i = 0; i < 5; i++) 3542 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3543 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3544 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3545 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3546 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3547 3548 sc->suspended = 1; 3549 3550 splx(s); 3551 return (0); 3552 } 3553 3554 /* 3555 * Device resume routine. Restore some PCI settings in case the BIOS 3556 * doesn't, re-enable busmastering, and restart the interface if 3557 * appropriate. 3558 */ 3559 static int dc_resume(dev) 3560 device_t dev; 3561 { 3562 register int i; 3563 int s; 3564 struct dc_softc *sc; 3565 struct ifnet *ifp; 3566 3567 s = splimp(); 3568 3569 sc = device_get_softc(dev); 3570 ifp = &sc->arpcom.ac_if; 3571 3572 dc_acpi(dev); 3573 3574 /* better way to do this? */ 3575 for (i = 0; i < 5; i++) 3576 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3577 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3578 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3579 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3580 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3581 3582 /* reenable busmastering */ 3583 pci_enable_busmaster(dev); 3584 pci_enable_io(dev, DC_RES); 3585 3586 /* reinitialize interface if necessary */ 3587 if (ifp->if_flags & IFF_UP) 3588 dc_init(sc); 3589 3590 sc->suspended = 0; 3591 3592 splx(s); 3593 return (0); 3594 } 3595