1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.18 2005/01/23 20:21:30 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 36 */ 37 38 /* 39 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 40 * series chips and several workalikes including the following: 41 * 42 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 43 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 44 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 45 * ASIX Electronics AX88140A (www.asix.com.tw) 46 * ASIX Electronics AX88141 (www.asix.com.tw) 47 * ADMtek AL981 (www.admtek.com.tw) 48 * ADMtek AN985 (www.admtek.com.tw) 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Conexant LANfinity (www.conexant.com) 52 * 53 * Datasheets for the 21143 are available at developer.intel.com. 54 * Datasheets for the clone parts can be found at their respective sites. 55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 56 * The PNIC II is essentially a Macronix 98715A chip; the only difference 57 * worth noting is that its multicast hash table is only 128 bits wide 58 * instead of 512. 59 * 60 * Written by Bill Paul <wpaul@ee.columbia.edu> 61 * Electrical Engineering Department 62 * Columbia University, New York City 63 */ 64 65 /* 66 * The Intel 21143 is the successor to the DEC 21140. It is basically 67 * the same as the 21140 but with a few new features. The 21143 supports 68 * three kinds of media attachments: 69 * 70 * o MII port, for 10Mbps and 100Mbps support and NWAY 71 * autonegotiation provided by an external PHY. 72 * o SYM port, for symbol mode 100Mbps support. 73 * o 10baseT port. 74 * o AUI/BNC port. 75 * 76 * The 100Mbps SYM port and 10baseT port can be used together in 77 * combination with the internal NWAY support to create a 10/100 78 * autosensing configuration. 79 * 80 * Note that not all tulip workalikes are handled in this driver: we only 81 * deal with those which are relatively well behaved. The Winbond is 82 * handled separately due to its different register offsets and the 83 * special handling needed for its various bugs. The PNIC is handled 84 * here, but I'm not thrilled about it. 85 * 86 * All of the workalike chips use some form of MII transceiver support 87 * with the exception of the Macronix chips, which also have a SYM port. 88 * The ASIX AX88140A is also documented to have a SYM port, but all 89 * the cards I've seen use an MII transceiver, probably because the 90 * AX88140A doesn't support internal NWAY. 91 */ 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/sysctl.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/vlan/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/clock.h> /* for DELAY */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include "../mii_layer/mii.h" 123 #include "../mii_layer/miivar.h" 124 125 #include <bus/pci/pcireg.h> 126 #include <bus/pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include "if_dcreg.h" 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct dc_type dc_devs[] = { 142 { DC_VENDORID_DEC, DC_DEVICEID_21143, 143 "Intel 21143 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 145 "Davicom DM9009 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 147 "Davicom DM9100 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 149 "Davicom DM9102 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 151 "Davicom DM9102A 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 153 "ADMtek AL981 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 155 "ADMtek AN985 10/100BaseTX" }, 156 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 157 "ASIX AX88140A 10/100BaseTX" }, 158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 159 "ASIX AX88141 10/100BaseTX" }, 160 { DC_VENDORID_MX, DC_DEVICEID_98713, 161 "Macronix 98713 10/100BaseTX" }, 162 { DC_VENDORID_MX, DC_DEVICEID_98713, 163 "Macronix 98713A 10/100BaseTX" }, 164 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 165 "Compex RL100-TX 10/100BaseTX" }, 166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 167 "Compex RL100-TX 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98715/98715A 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98715AEC-C 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98725 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_98727, 175 "Macronix 98727/98732 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C115, 177 "LC82C115 PNIC II 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C168, 179 "82c168 PNIC 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C168, 181 "82c169 PNIC 10/100BaseTX" }, 182 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 183 "Accton EN1217 10/100BaseTX" }, 184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 185 "Accton EN2242 MiniPCI 10/100BaseTX" }, 186 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 187 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 188 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 189 "3Com OfficeConnect 10/100B" }, 190 { 0, 0, NULL } 191 }; 192 193 static int dc_probe (device_t); 194 static int dc_attach (device_t); 195 static int dc_detach (device_t); 196 static int dc_suspend (device_t); 197 static int dc_resume (device_t); 198 static void dc_acpi (device_t); 199 static struct dc_type *dc_devtype (device_t); 200 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 201 static int dc_encap (struct dc_softc *, struct mbuf *, 202 u_int32_t *); 203 static int dc_coal (struct dc_softc *, struct mbuf **); 204 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 205 static int dc_rx_resync (struct dc_softc *); 206 static void dc_rxeof (struct dc_softc *); 207 static void dc_txeof (struct dc_softc *); 208 static void dc_tick (void *); 209 static void dc_tx_underrun (struct dc_softc *); 210 static void dc_intr (void *); 211 static void dc_start (struct ifnet *); 212 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 213 struct ucred *); 214 static void dc_init (void *); 215 static void dc_stop (struct dc_softc *); 216 static void dc_watchdog (struct ifnet *); 217 static void dc_shutdown (device_t); 218 static int dc_ifmedia_upd (struct ifnet *); 219 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 220 221 static void dc_delay (struct dc_softc *); 222 static void dc_eeprom_idle (struct dc_softc *); 223 static void dc_eeprom_putbyte (struct dc_softc *, int); 224 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 225 static void dc_eeprom_getword_pnic 226 (struct dc_softc *, int, u_int16_t *); 227 static void dc_eeprom_width (struct dc_softc *); 228 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 229 int, int); 230 231 static void dc_mii_writebit (struct dc_softc *, int); 232 static int dc_mii_readbit (struct dc_softc *); 233 static void dc_mii_sync (struct dc_softc *); 234 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 235 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 236 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 237 static int dc_miibus_readreg (device_t, int, int); 238 static int dc_miibus_writereg (device_t, int, int, int); 239 static void dc_miibus_statchg (device_t); 240 static void dc_miibus_mediainit (device_t); 241 242 static void dc_setcfg (struct dc_softc *, int); 243 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 244 static u_int32_t dc_crc_be (caddr_t); 245 static void dc_setfilt_21143 (struct dc_softc *); 246 static void dc_setfilt_asix (struct dc_softc *); 247 static void dc_setfilt_admtek (struct dc_softc *); 248 249 static void dc_setfilt (struct dc_softc *); 250 251 static void dc_reset (struct dc_softc *); 252 static int dc_list_rx_init (struct dc_softc *); 253 static int dc_list_tx_init (struct dc_softc *); 254 255 static void dc_read_srom (struct dc_softc *, int); 256 static void dc_parse_21143_srom (struct dc_softc *); 257 static void dc_decode_leaf_sia (struct dc_softc *, 258 struct dc_eblock_sia *); 259 static void dc_decode_leaf_mii (struct dc_softc *, 260 struct dc_eblock_mii *); 261 static void dc_decode_leaf_sym (struct dc_softc *, 262 struct dc_eblock_sym *); 263 static void dc_apply_fixup (struct dc_softc *, int); 264 265 #ifdef DC_USEIOSPACE 266 #define DC_RES SYS_RES_IOPORT 267 #define DC_RID DC_PCI_CFBIO 268 #else 269 #define DC_RES SYS_RES_MEMORY 270 #define DC_RID DC_PCI_CFBMA 271 #endif 272 273 static device_method_t dc_methods[] = { 274 /* Device interface */ 275 DEVMETHOD(device_probe, dc_probe), 276 DEVMETHOD(device_attach, dc_attach), 277 DEVMETHOD(device_detach, dc_detach), 278 DEVMETHOD(device_suspend, dc_suspend), 279 DEVMETHOD(device_resume, dc_resume), 280 DEVMETHOD(device_shutdown, dc_shutdown), 281 282 /* bus interface */ 283 DEVMETHOD(bus_print_child, bus_generic_print_child), 284 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 285 286 /* MII interface */ 287 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 288 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 289 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 290 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 291 292 { 0, 0 } 293 }; 294 295 static driver_t dc_driver = { 296 "dc", 297 dc_methods, 298 sizeof(struct dc_softc) 299 }; 300 301 static devclass_t dc_devclass; 302 303 #ifdef __i386__ 304 static int dc_quick=1; 305 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 306 &dc_quick,0,"do not mdevget in dc driver"); 307 #endif 308 309 DECLARE_DUMMY_MODULE(if_dc); 310 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 311 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 312 313 #define DC_SETBIT(sc, reg, x) \ 314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 315 316 #define DC_CLRBIT(sc, reg, x) \ 317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 318 319 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 320 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 321 322 static void dc_delay(sc) 323 struct dc_softc *sc; 324 { 325 int idx; 326 327 for (idx = (300 / 33) + 1; idx > 0; idx--) 328 CSR_READ_4(sc, DC_BUSCTL); 329 } 330 331 static void dc_eeprom_width(sc) 332 struct dc_softc *sc; 333 { 334 int i; 335 336 /* Force EEPROM to idle state. */ 337 dc_eeprom_idle(sc); 338 339 /* Enter EEPROM access mode. */ 340 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 341 dc_delay(sc); 342 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 343 dc_delay(sc); 344 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 345 dc_delay(sc); 346 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 347 dc_delay(sc); 348 349 for (i = 3; i--;) { 350 if (6 & (1 << i)) 351 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 352 else 353 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 354 dc_delay(sc); 355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 356 dc_delay(sc); 357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 358 dc_delay(sc); 359 } 360 361 for (i = 1; i <= 12; i++) { 362 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 363 dc_delay(sc); 364 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 365 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 366 dc_delay(sc); 367 break; 368 } 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 } 372 373 /* Turn off EEPROM access mode. */ 374 dc_eeprom_idle(sc); 375 376 if (i < 4 || i > 12) 377 sc->dc_romwidth = 6; 378 else 379 sc->dc_romwidth = i; 380 381 /* Enter EEPROM access mode. */ 382 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 383 dc_delay(sc); 384 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 385 dc_delay(sc); 386 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 387 dc_delay(sc); 388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 389 dc_delay(sc); 390 391 /* Turn off EEPROM access mode. */ 392 dc_eeprom_idle(sc); 393 } 394 395 static void dc_eeprom_idle(sc) 396 struct dc_softc *sc; 397 { 398 int i; 399 400 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 401 dc_delay(sc); 402 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 403 dc_delay(sc); 404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 405 dc_delay(sc); 406 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 407 dc_delay(sc); 408 409 for (i = 0; i < 25; i++) { 410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 411 dc_delay(sc); 412 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 413 dc_delay(sc); 414 } 415 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 419 dc_delay(sc); 420 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 421 422 return; 423 } 424 425 /* 426 * Send a read command and address to the EEPROM, check for ACK. 427 */ 428 static void dc_eeprom_putbyte(sc, addr) 429 struct dc_softc *sc; 430 int addr; 431 { 432 int d, i; 433 434 d = DC_EECMD_READ >> 6; 435 for (i = 3; i--; ) { 436 if (d & (1 << i)) 437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 438 else 439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 440 dc_delay(sc); 441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 444 dc_delay(sc); 445 } 446 447 /* 448 * Feed in each bit and strobe the clock. 449 */ 450 for (i = sc->dc_romwidth; i--;) { 451 if (addr & (1 << i)) { 452 SIO_SET(DC_SIO_EE_DATAIN); 453 } else { 454 SIO_CLR(DC_SIO_EE_DATAIN); 455 } 456 dc_delay(sc); 457 SIO_SET(DC_SIO_EE_CLK); 458 dc_delay(sc); 459 SIO_CLR(DC_SIO_EE_CLK); 460 dc_delay(sc); 461 } 462 463 return; 464 } 465 466 /* 467 * Read a word of data stored in the EEPROM at address 'addr.' 468 * The PNIC 82c168/82c169 has its own non-standard way to read 469 * the EEPROM. 470 */ 471 static void dc_eeprom_getword_pnic(sc, addr, dest) 472 struct dc_softc *sc; 473 int addr; 474 u_int16_t *dest; 475 { 476 int i; 477 u_int32_t r; 478 479 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 480 481 for (i = 0; i < DC_TIMEOUT; i++) { 482 DELAY(1); 483 r = CSR_READ_4(sc, DC_SIO); 484 if (!(r & DC_PN_SIOCTL_BUSY)) { 485 *dest = (u_int16_t)(r & 0xFFFF); 486 return; 487 } 488 } 489 490 return; 491 } 492 493 /* 494 * Read a word of data stored in the EEPROM at address 'addr.' 495 */ 496 static void dc_eeprom_getword(sc, addr, dest) 497 struct dc_softc *sc; 498 int addr; 499 u_int16_t *dest; 500 { 501 int i; 502 u_int16_t word = 0; 503 504 /* Force EEPROM to idle state. */ 505 dc_eeprom_idle(sc); 506 507 /* Enter EEPROM access mode. */ 508 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 509 dc_delay(sc); 510 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 511 dc_delay(sc); 512 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 513 dc_delay(sc); 514 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 515 dc_delay(sc); 516 517 /* 518 * Send address of word we want to read. 519 */ 520 dc_eeprom_putbyte(sc, addr); 521 522 /* 523 * Start reading bits from EEPROM. 524 */ 525 for (i = 0x8000; i; i >>= 1) { 526 SIO_SET(DC_SIO_EE_CLK); 527 dc_delay(sc); 528 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 529 word |= i; 530 dc_delay(sc); 531 SIO_CLR(DC_SIO_EE_CLK); 532 dc_delay(sc); 533 } 534 535 /* Turn off EEPROM access mode. */ 536 dc_eeprom_idle(sc); 537 538 *dest = word; 539 540 return; 541 } 542 543 /* 544 * Read a sequence of words from the EEPROM. 545 */ 546 static void dc_read_eeprom(sc, dest, off, cnt, swap) 547 struct dc_softc *sc; 548 caddr_t dest; 549 int off; 550 int cnt; 551 int swap; 552 { 553 int i; 554 u_int16_t word = 0, *ptr; 555 556 for (i = 0; i < cnt; i++) { 557 if (DC_IS_PNIC(sc)) 558 dc_eeprom_getword_pnic(sc, off + i, &word); 559 else 560 dc_eeprom_getword(sc, off + i, &word); 561 ptr = (u_int16_t *)(dest + (i * 2)); 562 if (swap) 563 *ptr = ntohs(word); 564 else 565 *ptr = word; 566 } 567 568 return; 569 } 570 571 /* 572 * The following two routines are taken from the Macronix 98713 573 * Application Notes pp.19-21. 574 */ 575 /* 576 * Write a bit to the MII bus. 577 */ 578 static void dc_mii_writebit(sc, bit) 579 struct dc_softc *sc; 580 int bit; 581 { 582 if (bit) 583 CSR_WRITE_4(sc, DC_SIO, 584 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 585 else 586 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 587 588 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 589 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 590 591 return; 592 } 593 594 /* 595 * Read a bit from the MII bus. 596 */ 597 static int dc_mii_readbit(sc) 598 struct dc_softc *sc; 599 { 600 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 601 CSR_READ_4(sc, DC_SIO); 602 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 603 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 604 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 605 return(1); 606 607 return(0); 608 } 609 610 /* 611 * Sync the PHYs by setting data bit and strobing the clock 32 times. 612 */ 613 static void dc_mii_sync(sc) 614 struct dc_softc *sc; 615 { 616 int i; 617 618 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 619 620 for (i = 0; i < 32; i++) 621 dc_mii_writebit(sc, 1); 622 623 return; 624 } 625 626 /* 627 * Clock a series of bits through the MII. 628 */ 629 static void dc_mii_send(sc, bits, cnt) 630 struct dc_softc *sc; 631 u_int32_t bits; 632 int cnt; 633 { 634 int i; 635 636 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 637 dc_mii_writebit(sc, bits & i); 638 } 639 640 /* 641 * Read an PHY register through the MII. 642 */ 643 static int dc_mii_readreg(sc, frame) 644 struct dc_softc *sc; 645 struct dc_mii_frame *frame; 646 647 { 648 int i, ack, s; 649 650 s = splimp(); 651 652 /* 653 * Set up frame for RX. 654 */ 655 frame->mii_stdelim = DC_MII_STARTDELIM; 656 frame->mii_opcode = DC_MII_READOP; 657 frame->mii_turnaround = 0; 658 frame->mii_data = 0; 659 660 /* 661 * Sync the PHYs. 662 */ 663 dc_mii_sync(sc); 664 665 /* 666 * Send command/address info. 667 */ 668 dc_mii_send(sc, frame->mii_stdelim, 2); 669 dc_mii_send(sc, frame->mii_opcode, 2); 670 dc_mii_send(sc, frame->mii_phyaddr, 5); 671 dc_mii_send(sc, frame->mii_regaddr, 5); 672 673 #ifdef notdef 674 /* Idle bit */ 675 dc_mii_writebit(sc, 1); 676 dc_mii_writebit(sc, 0); 677 #endif 678 679 /* Check for ack */ 680 ack = dc_mii_readbit(sc); 681 682 /* 683 * Now try reading data bits. If the ack failed, we still 684 * need to clock through 16 cycles to keep the PHY(s) in sync. 685 */ 686 if (ack) { 687 for(i = 0; i < 16; i++) { 688 dc_mii_readbit(sc); 689 } 690 goto fail; 691 } 692 693 for (i = 0x8000; i; i >>= 1) { 694 if (!ack) { 695 if (dc_mii_readbit(sc)) 696 frame->mii_data |= i; 697 } 698 } 699 700 fail: 701 702 dc_mii_writebit(sc, 0); 703 dc_mii_writebit(sc, 0); 704 705 splx(s); 706 707 if (ack) 708 return(1); 709 return(0); 710 } 711 712 /* 713 * Write to a PHY register through the MII. 714 */ 715 static int dc_mii_writereg(sc, frame) 716 struct dc_softc *sc; 717 struct dc_mii_frame *frame; 718 719 { 720 int s; 721 722 s = splimp(); 723 /* 724 * Set up frame for TX. 725 */ 726 727 frame->mii_stdelim = DC_MII_STARTDELIM; 728 frame->mii_opcode = DC_MII_WRITEOP; 729 frame->mii_turnaround = DC_MII_TURNAROUND; 730 731 /* 732 * Sync the PHYs. 733 */ 734 dc_mii_sync(sc); 735 736 dc_mii_send(sc, frame->mii_stdelim, 2); 737 dc_mii_send(sc, frame->mii_opcode, 2); 738 dc_mii_send(sc, frame->mii_phyaddr, 5); 739 dc_mii_send(sc, frame->mii_regaddr, 5); 740 dc_mii_send(sc, frame->mii_turnaround, 2); 741 dc_mii_send(sc, frame->mii_data, 16); 742 743 /* Idle bit. */ 744 dc_mii_writebit(sc, 0); 745 dc_mii_writebit(sc, 0); 746 747 splx(s); 748 749 return(0); 750 } 751 752 static int dc_miibus_readreg(dev, phy, reg) 753 device_t dev; 754 int phy, reg; 755 { 756 struct dc_mii_frame frame; 757 struct dc_softc *sc; 758 int i, rval, phy_reg = 0; 759 760 sc = device_get_softc(dev); 761 bzero((char *)&frame, sizeof(frame)); 762 763 /* 764 * Note: both the AL981 and AN985 have internal PHYs, 765 * however the AL981 provides direct access to the PHY 766 * registers while the AN985 uses a serial MII interface. 767 * The AN985's MII interface is also buggy in that you 768 * can read from any MII address (0 to 31), but only address 1 769 * behaves normally. To deal with both cases, we pretend 770 * that the PHY is at MII address 1. 771 */ 772 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 773 return(0); 774 775 /* 776 * Note: the ukphy probes of the RS7112 report a PHY at 777 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 778 * so we only respond to correct one. 779 */ 780 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 781 return(0); 782 783 if (sc->dc_pmode != DC_PMODE_MII) { 784 if (phy == (MII_NPHY - 1)) { 785 switch(reg) { 786 case MII_BMSR: 787 /* 788 * Fake something to make the probe 789 * code think there's a PHY here. 790 */ 791 return(BMSR_MEDIAMASK); 792 break; 793 case MII_PHYIDR1: 794 if (DC_IS_PNIC(sc)) 795 return(DC_VENDORID_LO); 796 return(DC_VENDORID_DEC); 797 break; 798 case MII_PHYIDR2: 799 if (DC_IS_PNIC(sc)) 800 return(DC_DEVICEID_82C168); 801 return(DC_DEVICEID_21143); 802 break; 803 default: 804 return(0); 805 break; 806 } 807 } else 808 return(0); 809 } 810 811 if (DC_IS_PNIC(sc)) { 812 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 813 (phy << 23) | (reg << 18)); 814 for (i = 0; i < DC_TIMEOUT; i++) { 815 DELAY(1); 816 rval = CSR_READ_4(sc, DC_PN_MII); 817 if (!(rval & DC_PN_MII_BUSY)) { 818 rval &= 0xFFFF; 819 return(rval == 0xFFFF ? 0 : rval); 820 } 821 } 822 return(0); 823 } 824 825 if (DC_IS_COMET(sc)) { 826 switch(reg) { 827 case MII_BMCR: 828 phy_reg = DC_AL_BMCR; 829 break; 830 case MII_BMSR: 831 phy_reg = DC_AL_BMSR; 832 break; 833 case MII_PHYIDR1: 834 phy_reg = DC_AL_VENID; 835 break; 836 case MII_PHYIDR2: 837 phy_reg = DC_AL_DEVID; 838 break; 839 case MII_ANAR: 840 phy_reg = DC_AL_ANAR; 841 break; 842 case MII_ANLPAR: 843 phy_reg = DC_AL_LPAR; 844 break; 845 case MII_ANER: 846 phy_reg = DC_AL_ANER; 847 break; 848 default: 849 printf("dc%d: phy_read: bad phy register %x\n", 850 sc->dc_unit, reg); 851 return(0); 852 break; 853 } 854 855 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 856 857 if (rval == 0xFFFF) 858 return(0); 859 return(rval); 860 } 861 862 frame.mii_phyaddr = phy; 863 frame.mii_regaddr = reg; 864 if (sc->dc_type == DC_TYPE_98713) { 865 phy_reg = CSR_READ_4(sc, DC_NETCFG); 866 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 867 } 868 dc_mii_readreg(sc, &frame); 869 if (sc->dc_type == DC_TYPE_98713) 870 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 871 872 return(frame.mii_data); 873 } 874 875 static int dc_miibus_writereg(dev, phy, reg, data) 876 device_t dev; 877 int phy, reg, data; 878 { 879 struct dc_softc *sc; 880 struct dc_mii_frame frame; 881 int i, phy_reg = 0; 882 883 sc = device_get_softc(dev); 884 bzero((char *)&frame, sizeof(frame)); 885 886 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 887 return(0); 888 889 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 890 return(0); 891 892 if (DC_IS_PNIC(sc)) { 893 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 894 (phy << 23) | (reg << 10) | data); 895 for (i = 0; i < DC_TIMEOUT; i++) { 896 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 897 break; 898 } 899 return(0); 900 } 901 902 if (DC_IS_COMET(sc)) { 903 switch(reg) { 904 case MII_BMCR: 905 phy_reg = DC_AL_BMCR; 906 break; 907 case MII_BMSR: 908 phy_reg = DC_AL_BMSR; 909 break; 910 case MII_PHYIDR1: 911 phy_reg = DC_AL_VENID; 912 break; 913 case MII_PHYIDR2: 914 phy_reg = DC_AL_DEVID; 915 break; 916 case MII_ANAR: 917 phy_reg = DC_AL_ANAR; 918 break; 919 case MII_ANLPAR: 920 phy_reg = DC_AL_LPAR; 921 break; 922 case MII_ANER: 923 phy_reg = DC_AL_ANER; 924 break; 925 default: 926 printf("dc%d: phy_write: bad phy register %x\n", 927 sc->dc_unit, reg); 928 return(0); 929 break; 930 } 931 932 CSR_WRITE_4(sc, phy_reg, data); 933 return(0); 934 } 935 936 frame.mii_phyaddr = phy; 937 frame.mii_regaddr = reg; 938 frame.mii_data = data; 939 940 if (sc->dc_type == DC_TYPE_98713) { 941 phy_reg = CSR_READ_4(sc, DC_NETCFG); 942 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 943 } 944 dc_mii_writereg(sc, &frame); 945 if (sc->dc_type == DC_TYPE_98713) 946 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 947 948 return(0); 949 } 950 951 static void dc_miibus_statchg(dev) 952 device_t dev; 953 { 954 struct dc_softc *sc; 955 struct mii_data *mii; 956 struct ifmedia *ifm; 957 958 sc = device_get_softc(dev); 959 if (DC_IS_ADMTEK(sc)) 960 return; 961 962 mii = device_get_softc(sc->dc_miibus); 963 ifm = &mii->mii_media; 964 if (DC_IS_DAVICOM(sc) && 965 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 966 dc_setcfg(sc, ifm->ifm_media); 967 sc->dc_if_media = ifm->ifm_media; 968 } else { 969 dc_setcfg(sc, mii->mii_media_active); 970 sc->dc_if_media = mii->mii_media_active; 971 } 972 973 return; 974 } 975 976 /* 977 * Special support for DM9102A cards with HomePNA PHYs. Note: 978 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 979 * to be impossible to talk to the management interface of the DM9801 980 * PHY (its MDIO pin is not connected to anything). Consequently, 981 * the driver has to just 'know' about the additional mode and deal 982 * with it itself. *sigh* 983 */ 984 static void dc_miibus_mediainit(dev) 985 device_t dev; 986 { 987 struct dc_softc *sc; 988 struct mii_data *mii; 989 struct ifmedia *ifm; 990 int rev; 991 992 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 993 994 sc = device_get_softc(dev); 995 mii = device_get_softc(sc->dc_miibus); 996 ifm = &mii->mii_media; 997 998 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 999 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 1000 1001 return; 1002 } 1003 1004 #define DC_POLY 0xEDB88320 1005 #define DC_BITS_512 9 1006 #define DC_BITS_128 7 1007 #define DC_BITS_64 6 1008 1009 static u_int32_t dc_crc_le(sc, addr) 1010 struct dc_softc *sc; 1011 caddr_t addr; 1012 { 1013 u_int32_t idx, bit, data, crc; 1014 1015 /* Compute CRC for the address value. */ 1016 crc = 0xFFFFFFFF; /* initial value */ 1017 1018 for (idx = 0; idx < 6; idx++) { 1019 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1020 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1021 } 1022 1023 /* 1024 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1025 * chips is only 128 bits wide. 1026 */ 1027 if (sc->dc_flags & DC_128BIT_HASH) 1028 return (crc & ((1 << DC_BITS_128) - 1)); 1029 1030 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1031 if (sc->dc_flags & DC_64BIT_HASH) 1032 return (crc & ((1 << DC_BITS_64) - 1)); 1033 1034 return (crc & ((1 << DC_BITS_512) - 1)); 1035 } 1036 1037 /* 1038 * Calculate CRC of a multicast group address, return the lower 6 bits. 1039 */ 1040 static u_int32_t dc_crc_be(addr) 1041 caddr_t addr; 1042 { 1043 u_int32_t crc, carry; 1044 int i, j; 1045 u_int8_t c; 1046 1047 /* Compute CRC for the address value. */ 1048 crc = 0xFFFFFFFF; /* initial value */ 1049 1050 for (i = 0; i < 6; i++) { 1051 c = *(addr + i); 1052 for (j = 0; j < 8; j++) { 1053 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1054 crc <<= 1; 1055 c >>= 1; 1056 if (carry) 1057 crc = (crc ^ 0x04c11db6) | carry; 1058 } 1059 } 1060 1061 /* return the filter bit position */ 1062 return((crc >> 26) & 0x0000003F); 1063 } 1064 1065 /* 1066 * 21143-style RX filter setup routine. Filter programming is done by 1067 * downloading a special setup frame into the TX engine. 21143, Macronix, 1068 * PNIC, PNIC II and Davicom chips are programmed this way. 1069 * 1070 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1071 * address (our node address) and a 512-bit hash filter for multicast 1072 * frames. We also sneak the broadcast address into the hash filter since 1073 * we need that too. 1074 */ 1075 void dc_setfilt_21143(sc) 1076 struct dc_softc *sc; 1077 { 1078 struct dc_desc *sframe; 1079 u_int32_t h, *sp; 1080 struct ifmultiaddr *ifma; 1081 struct ifnet *ifp; 1082 int i; 1083 1084 ifp = &sc->arpcom.ac_if; 1085 1086 i = sc->dc_cdata.dc_tx_prod; 1087 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1088 sc->dc_cdata.dc_tx_cnt++; 1089 sframe = &sc->dc_ldata->dc_tx_list[i]; 1090 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1091 bzero((char *)sp, DC_SFRAME_LEN); 1092 1093 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1094 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1095 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1096 1097 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1098 1099 /* If we want promiscuous mode, set the allframes bit. */ 1100 if (ifp->if_flags & IFF_PROMISC) 1101 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1102 else 1103 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1104 1105 if (ifp->if_flags & IFF_ALLMULTI) 1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1107 else 1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1109 1110 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1111 ifma = ifma->ifma_link.le_next) { 1112 if (ifma->ifma_addr->sa_family != AF_LINK) 1113 continue; 1114 h = dc_crc_le(sc, 1115 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1116 sp[h >> 4] |= 1 << (h & 0xF); 1117 } 1118 1119 if (ifp->if_flags & IFF_BROADCAST) { 1120 h = dc_crc_le(sc, ifp->if_broadcastaddr); 1121 sp[h >> 4] |= 1 << (h & 0xF); 1122 } 1123 1124 /* Set our MAC address */ 1125 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1126 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1127 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1128 1129 sframe->dc_status = DC_TXSTAT_OWN; 1130 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1131 1132 /* 1133 * The PNIC takes an exceedingly long time to process its 1134 * setup frame; wait 10ms after posting the setup frame 1135 * before proceeding, just so it has time to swallow its 1136 * medicine. 1137 */ 1138 DELAY(10000); 1139 1140 ifp->if_timer = 5; 1141 1142 return; 1143 } 1144 1145 void dc_setfilt_admtek(sc) 1146 struct dc_softc *sc; 1147 { 1148 struct ifnet *ifp; 1149 int h = 0; 1150 u_int32_t hashes[2] = { 0, 0 }; 1151 struct ifmultiaddr *ifma; 1152 1153 ifp = &sc->arpcom.ac_if; 1154 1155 /* Init our MAC address */ 1156 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1157 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1158 1159 /* If we want promiscuous mode, set the allframes bit. */ 1160 if (ifp->if_flags & IFF_PROMISC) 1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1162 else 1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1164 1165 if (ifp->if_flags & IFF_ALLMULTI) 1166 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1167 else 1168 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1169 1170 /* first, zot all the existing hash bits */ 1171 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1172 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1173 1174 /* 1175 * If we're already in promisc or allmulti mode, we 1176 * don't have to bother programming the multicast filter. 1177 */ 1178 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1179 return; 1180 1181 /* now program new ones */ 1182 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1183 ifma = ifma->ifma_link.le_next) { 1184 if (ifma->ifma_addr->sa_family != AF_LINK) 1185 continue; 1186 if (DC_IS_CENTAUR(sc)) 1187 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1188 else 1189 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1190 if (h < 32) 1191 hashes[0] |= (1 << h); 1192 else 1193 hashes[1] |= (1 << (h - 32)); 1194 } 1195 1196 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1197 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1198 1199 return; 1200 } 1201 1202 void dc_setfilt_asix(sc) 1203 struct dc_softc *sc; 1204 { 1205 struct ifnet *ifp; 1206 int h = 0; 1207 u_int32_t hashes[2] = { 0, 0 }; 1208 struct ifmultiaddr *ifma; 1209 1210 ifp = &sc->arpcom.ac_if; 1211 1212 /* Init our MAC address */ 1213 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1214 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1215 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1217 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1218 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1219 1220 /* If we want promiscuous mode, set the allframes bit. */ 1221 if (ifp->if_flags & IFF_PROMISC) 1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1223 else 1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1225 1226 if (ifp->if_flags & IFF_ALLMULTI) 1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1228 else 1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1230 1231 /* 1232 * The ASIX chip has a special bit to enable reception 1233 * of broadcast frames. 1234 */ 1235 if (ifp->if_flags & IFF_BROADCAST) 1236 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1237 else 1238 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1239 1240 /* first, zot all the existing hash bits */ 1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1245 1246 /* 1247 * If we're already in promisc or allmulti mode, we 1248 * don't have to bother programming the multicast filter. 1249 */ 1250 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1251 return; 1252 1253 /* now program new ones */ 1254 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1255 ifma = ifma->ifma_link.le_next) { 1256 if (ifma->ifma_addr->sa_family != AF_LINK) 1257 continue; 1258 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1259 if (h < 32) 1260 hashes[0] |= (1 << h); 1261 else 1262 hashes[1] |= (1 << (h - 32)); 1263 } 1264 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1269 1270 return; 1271 } 1272 1273 static void dc_setfilt(sc) 1274 struct dc_softc *sc; 1275 { 1276 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1277 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1278 dc_setfilt_21143(sc); 1279 1280 if (DC_IS_ASIX(sc)) 1281 dc_setfilt_asix(sc); 1282 1283 if (DC_IS_ADMTEK(sc)) 1284 dc_setfilt_admtek(sc); 1285 1286 return; 1287 } 1288 1289 /* 1290 * In order to fiddle with the 1291 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1292 * first have to put the transmit and/or receive logic in the idle state. 1293 */ 1294 static void dc_setcfg(sc, media) 1295 struct dc_softc *sc; 1296 int media; 1297 { 1298 int i, restart = 0; 1299 u_int32_t isr; 1300 1301 if (IFM_SUBTYPE(media) == IFM_NONE) 1302 return; 1303 1304 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1305 restart = 1; 1306 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1307 1308 for (i = 0; i < DC_TIMEOUT; i++) { 1309 isr = CSR_READ_4(sc, DC_ISR); 1310 if (isr & DC_ISR_TX_IDLE || 1311 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1312 break; 1313 DELAY(10); 1314 } 1315 1316 if (i == DC_TIMEOUT) 1317 printf("dc%d: failed to force tx and " 1318 "rx to idle state\n", sc->dc_unit); 1319 } 1320 1321 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1322 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1323 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1324 if (sc->dc_pmode == DC_PMODE_MII) { 1325 int watchdogreg; 1326 1327 if (DC_IS_INTEL(sc)) { 1328 /* there's a write enable bit here that reads as 1 */ 1329 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1330 watchdogreg &= ~DC_WDOG_CTLWREN; 1331 watchdogreg |= DC_WDOG_JABBERDIS; 1332 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1333 } else { 1334 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1335 } 1336 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1337 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1338 if (sc->dc_type == DC_TYPE_98713) 1339 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1340 DC_NETCFG_SCRAMBLER)); 1341 if (!DC_IS_DAVICOM(sc)) 1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1343 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1344 if (DC_IS_INTEL(sc)) 1345 dc_apply_fixup(sc, IFM_AUTO); 1346 } else { 1347 if (DC_IS_PNIC(sc)) { 1348 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1349 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1350 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1351 } 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1353 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1354 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1355 if (DC_IS_INTEL(sc)) 1356 dc_apply_fixup(sc, 1357 (media & IFM_GMASK) == IFM_FDX ? 1358 IFM_100_TX|IFM_FDX : IFM_100_TX); 1359 } 1360 } 1361 1362 if (IFM_SUBTYPE(media) == IFM_10_T) { 1363 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1364 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1365 if (sc->dc_pmode == DC_PMODE_MII) { 1366 int watchdogreg; 1367 1368 /* there's a write enable bit here that reads as 1 */ 1369 if (DC_IS_INTEL(sc)) { 1370 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1371 watchdogreg &= ~DC_WDOG_CTLWREN; 1372 watchdogreg |= DC_WDOG_JABBERDIS; 1373 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1374 } else { 1375 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1376 } 1377 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1378 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1379 if (sc->dc_type == DC_TYPE_98713) 1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1381 if (!DC_IS_DAVICOM(sc)) 1382 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1383 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1384 if (DC_IS_INTEL(sc)) 1385 dc_apply_fixup(sc, IFM_AUTO); 1386 } else { 1387 if (DC_IS_PNIC(sc)) { 1388 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1389 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1390 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1391 } 1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1393 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1394 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1395 if (DC_IS_INTEL(sc)) { 1396 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1397 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1398 if ((media & IFM_GMASK) == IFM_FDX) 1399 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1400 else 1401 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1402 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1403 DC_CLRBIT(sc, DC_10BTCTRL, 1404 DC_TCTL_AUTONEGENBL); 1405 dc_apply_fixup(sc, 1406 (media & IFM_GMASK) == IFM_FDX ? 1407 IFM_10_T|IFM_FDX : IFM_10_T); 1408 DELAY(20000); 1409 } 1410 } 1411 } 1412 1413 /* 1414 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1415 * PHY and we want HomePNA mode, set the portsel bit to turn 1416 * on the external MII port. 1417 */ 1418 if (DC_IS_DAVICOM(sc)) { 1419 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1421 sc->dc_link = 1; 1422 } else { 1423 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1424 } 1425 } 1426 1427 if ((media & IFM_GMASK) == IFM_FDX) { 1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1429 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1430 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1431 } else { 1432 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1433 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1434 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1435 } 1436 1437 if (restart) 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1439 1440 return; 1441 } 1442 1443 static void dc_reset(sc) 1444 struct dc_softc *sc; 1445 { 1446 int i; 1447 1448 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1449 1450 for (i = 0; i < DC_TIMEOUT; i++) { 1451 DELAY(10); 1452 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1453 break; 1454 } 1455 1456 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1457 DELAY(10000); 1458 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1459 i = 0; 1460 } 1461 1462 if (i == DC_TIMEOUT) 1463 printf("dc%d: reset never completed!\n", sc->dc_unit); 1464 1465 /* Wait a little while for the chip to get its brains in order. */ 1466 DELAY(1000); 1467 1468 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1469 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1470 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1471 1472 /* 1473 * Bring the SIA out of reset. In some cases, it looks 1474 * like failing to unreset the SIA soon enough gets it 1475 * into a state where it will never come out of reset 1476 * until we reset the whole chip again. 1477 */ 1478 if (DC_IS_INTEL(sc)) { 1479 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1480 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1481 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1482 } 1483 1484 return; 1485 } 1486 1487 static struct dc_type *dc_devtype(dev) 1488 device_t dev; 1489 { 1490 struct dc_type *t; 1491 u_int32_t rev; 1492 1493 t = dc_devs; 1494 1495 while(t->dc_name != NULL) { 1496 if ((pci_get_vendor(dev) == t->dc_vid) && 1497 (pci_get_device(dev) == t->dc_did)) { 1498 /* Check the PCI revision */ 1499 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1500 if (t->dc_did == DC_DEVICEID_98713 && 1501 rev >= DC_REVISION_98713A) 1502 t++; 1503 if (t->dc_did == DC_DEVICEID_98713_CP && 1504 rev >= DC_REVISION_98713A) 1505 t++; 1506 if (t->dc_did == DC_DEVICEID_987x5 && 1507 rev >= DC_REVISION_98715AEC_C) 1508 t++; 1509 if (t->dc_did == DC_DEVICEID_987x5 && 1510 rev >= DC_REVISION_98725) 1511 t++; 1512 if (t->dc_did == DC_DEVICEID_AX88140A && 1513 rev >= DC_REVISION_88141) 1514 t++; 1515 if (t->dc_did == DC_DEVICEID_82C168 && 1516 rev >= DC_REVISION_82C169) 1517 t++; 1518 if (t->dc_did == DC_DEVICEID_DM9102 && 1519 rev >= DC_REVISION_DM9102A) 1520 t++; 1521 return(t); 1522 } 1523 t++; 1524 } 1525 1526 return(NULL); 1527 } 1528 1529 /* 1530 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1531 * IDs against our list and return a device name if we find a match. 1532 * We do a little bit of extra work to identify the exact type of 1533 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1534 * but different revision IDs. The same is true for 98715/98715A 1535 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1536 * cases, the exact chip revision affects driver behavior. 1537 */ 1538 static int dc_probe(dev) 1539 device_t dev; 1540 { 1541 struct dc_type *t; 1542 1543 t = dc_devtype(dev); 1544 1545 if (t != NULL) { 1546 device_set_desc(dev, t->dc_name); 1547 return(0); 1548 } 1549 1550 return(ENXIO); 1551 } 1552 1553 static void dc_acpi(dev) 1554 device_t dev; 1555 { 1556 u_int32_t r, cptr; 1557 int unit; 1558 1559 unit = device_get_unit(dev); 1560 1561 /* Find the location of the capabilities block */ 1562 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1563 1564 r = pci_read_config(dev, cptr, 4) & 0xFF; 1565 if (r == 0x01) { 1566 1567 r = pci_read_config(dev, cptr + 4, 4); 1568 if (r & DC_PSTATE_D3) { 1569 u_int32_t iobase, membase, irq; 1570 1571 /* Save important PCI config data. */ 1572 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1573 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1574 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1575 1576 /* Reset the power state. */ 1577 printf("dc%d: chip is in D%d power mode " 1578 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1579 r &= 0xFFFFFFFC; 1580 pci_write_config(dev, cptr + 4, r, 4); 1581 1582 /* Restore PCI config data. */ 1583 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1584 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1585 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1586 } 1587 } 1588 return; 1589 } 1590 1591 static void dc_apply_fixup(sc, media) 1592 struct dc_softc *sc; 1593 int media; 1594 { 1595 struct dc_mediainfo *m; 1596 u_int8_t *p; 1597 int i; 1598 u_int32_t reg; 1599 1600 m = sc->dc_mi; 1601 1602 while (m != NULL) { 1603 if (m->dc_media == media) 1604 break; 1605 m = m->dc_next; 1606 } 1607 1608 if (m == NULL) 1609 return; 1610 1611 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1612 reg = (p[0] | (p[1] << 8)) << 16; 1613 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1614 } 1615 1616 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1617 reg = (p[0] | (p[1] << 8)) << 16; 1618 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1619 } 1620 1621 return; 1622 } 1623 1624 static void dc_decode_leaf_sia(sc, l) 1625 struct dc_softc *sc; 1626 struct dc_eblock_sia *l; 1627 { 1628 struct dc_mediainfo *m; 1629 1630 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1631 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1632 m->dc_media = IFM_10_T; 1633 1634 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1635 m->dc_media = IFM_10_T|IFM_FDX; 1636 1637 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1638 m->dc_media = IFM_10_2; 1639 1640 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1641 m->dc_media = IFM_10_5; 1642 1643 m->dc_gp_len = 2; 1644 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1645 1646 m->dc_next = sc->dc_mi; 1647 sc->dc_mi = m; 1648 1649 sc->dc_pmode = DC_PMODE_SIA; 1650 1651 return; 1652 } 1653 1654 static void dc_decode_leaf_sym(sc, l) 1655 struct dc_softc *sc; 1656 struct dc_eblock_sym *l; 1657 { 1658 struct dc_mediainfo *m; 1659 1660 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1661 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1662 m->dc_media = IFM_100_TX; 1663 1664 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1665 m->dc_media = IFM_100_TX|IFM_FDX; 1666 1667 m->dc_gp_len = 2; 1668 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1669 1670 m->dc_next = sc->dc_mi; 1671 sc->dc_mi = m; 1672 1673 sc->dc_pmode = DC_PMODE_SYM; 1674 1675 return; 1676 } 1677 1678 static void dc_decode_leaf_mii(sc, l) 1679 struct dc_softc *sc; 1680 struct dc_eblock_mii *l; 1681 { 1682 u_int8_t *p; 1683 struct dc_mediainfo *m; 1684 1685 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1686 /* We abuse IFM_AUTO to represent MII. */ 1687 m->dc_media = IFM_AUTO; 1688 m->dc_gp_len = l->dc_gpr_len; 1689 1690 p = (u_int8_t *)l; 1691 p += sizeof(struct dc_eblock_mii); 1692 m->dc_gp_ptr = p; 1693 p += 2 * l->dc_gpr_len; 1694 m->dc_reset_len = *p; 1695 p++; 1696 m->dc_reset_ptr = p; 1697 1698 m->dc_next = sc->dc_mi; 1699 sc->dc_mi = m; 1700 1701 return; 1702 } 1703 1704 static void dc_read_srom(sc, bits) 1705 struct dc_softc *sc; 1706 int bits; 1707 { 1708 int size; 1709 1710 size = 2 << bits; 1711 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT); 1712 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1713 } 1714 1715 static void dc_parse_21143_srom(sc) 1716 struct dc_softc *sc; 1717 { 1718 struct dc_leaf_hdr *lhdr; 1719 struct dc_eblock_hdr *hdr; 1720 int i, loff; 1721 char *ptr; 1722 int have_mii; 1723 1724 have_mii = 0; 1725 loff = sc->dc_srom[27]; 1726 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1727 1728 ptr = (char *)lhdr; 1729 ptr += sizeof(struct dc_leaf_hdr) - 1; 1730 /* 1731 * Look if we got a MII media block. 1732 */ 1733 for (i = 0; i < lhdr->dc_mcnt; i++) { 1734 hdr = (struct dc_eblock_hdr *)ptr; 1735 if (hdr->dc_type == DC_EBLOCK_MII) 1736 have_mii++; 1737 1738 ptr += (hdr->dc_len & 0x7F); 1739 ptr++; 1740 } 1741 1742 /* 1743 * Do the same thing again. Only use SIA and SYM media 1744 * blocks if no MII media block is available. 1745 */ 1746 ptr = (char *)lhdr; 1747 ptr += sizeof(struct dc_leaf_hdr) - 1; 1748 for (i = 0; i < lhdr->dc_mcnt; i++) { 1749 hdr = (struct dc_eblock_hdr *)ptr; 1750 switch(hdr->dc_type) { 1751 case DC_EBLOCK_MII: 1752 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1753 break; 1754 case DC_EBLOCK_SIA: 1755 if (! have_mii) 1756 dc_decode_leaf_sia(sc, 1757 (struct dc_eblock_sia *)hdr); 1758 break; 1759 case DC_EBLOCK_SYM: 1760 if (! have_mii) 1761 dc_decode_leaf_sym(sc, 1762 (struct dc_eblock_sym *)hdr); 1763 break; 1764 default: 1765 /* Don't care. Yet. */ 1766 break; 1767 } 1768 ptr += (hdr->dc_len & 0x7F); 1769 ptr++; 1770 } 1771 1772 return; 1773 } 1774 1775 /* 1776 * Attach the interface. Allocate softc structures, do ifmedia 1777 * setup and ethernet/BPF attach. 1778 */ 1779 static int dc_attach(dev) 1780 device_t dev; 1781 { 1782 int s, tmp = 0; 1783 u_char eaddr[ETHER_ADDR_LEN]; 1784 u_int32_t command; 1785 struct dc_softc *sc; 1786 struct ifnet *ifp; 1787 u_int32_t revision; 1788 int unit, error = 0, rid, mac_offset; 1789 1790 s = splimp(); 1791 1792 sc = device_get_softc(dev); 1793 unit = device_get_unit(dev); 1794 bzero(sc, sizeof(struct dc_softc)); 1795 callout_init(&sc->dc_stat_timer); 1796 1797 /* 1798 * Handle power management nonsense. 1799 */ 1800 dc_acpi(dev); 1801 1802 /* 1803 * Map control/status registers. 1804 */ 1805 command = pci_read_config(dev, PCIR_COMMAND, 4); 1806 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1807 pci_write_config(dev, PCIR_COMMAND, command, 4); 1808 command = pci_read_config(dev, PCIR_COMMAND, 4); 1809 1810 #ifdef DC_USEIOSPACE 1811 if (!(command & PCIM_CMD_PORTEN)) { 1812 printf("dc%d: failed to enable I/O ports!\n", unit); 1813 error = ENXIO; 1814 goto fail; 1815 } 1816 #else 1817 if (!(command & PCIM_CMD_MEMEN)) { 1818 printf("dc%d: failed to enable memory mapping!\n", unit); 1819 error = ENXIO; 1820 goto fail; 1821 } 1822 #endif 1823 1824 rid = DC_RID; 1825 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1826 0, ~0, 1, RF_ACTIVE); 1827 1828 if (sc->dc_res == NULL) { 1829 printf("dc%d: couldn't map ports/memory\n", unit); 1830 error = ENXIO; 1831 goto fail; 1832 } 1833 1834 sc->dc_btag = rman_get_bustag(sc->dc_res); 1835 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1836 1837 /* Allocate interrupt */ 1838 rid = 0; 1839 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1840 RF_SHAREABLE | RF_ACTIVE); 1841 1842 if (sc->dc_irq == NULL) { 1843 printf("dc%d: couldn't map interrupt\n", unit); 1844 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1845 error = ENXIO; 1846 goto fail; 1847 } 1848 1849 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1850 dc_intr, sc, &sc->dc_intrhand); 1851 1852 if (error) { 1853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1854 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1855 printf("dc%d: couldn't set up irq\n", unit); 1856 goto fail; 1857 } 1858 1859 /* Need this info to decide on a chip type. */ 1860 sc->dc_info = dc_devtype(dev); 1861 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1862 1863 /* Get the eeprom width, but PNIC has diff eeprom */ 1864 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1865 dc_eeprom_width(sc); 1866 1867 switch(sc->dc_info->dc_did) { 1868 case DC_DEVICEID_21143: 1869 sc->dc_type = DC_TYPE_21143; 1870 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1871 sc->dc_flags |= DC_REDUCED_MII_POLL; 1872 /* Save EEPROM contents so we can parse them later. */ 1873 dc_read_srom(sc, sc->dc_romwidth); 1874 break; 1875 case DC_DEVICEID_DM9009: 1876 case DC_DEVICEID_DM9100: 1877 case DC_DEVICEID_DM9102: 1878 sc->dc_type = DC_TYPE_DM9102; 1879 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1880 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1881 sc->dc_pmode = DC_PMODE_MII; 1882 /* Increase the latency timer value. */ 1883 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1884 command &= 0xFFFF00FF; 1885 command |= 0x00008000; 1886 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1887 break; 1888 case DC_DEVICEID_AL981: 1889 sc->dc_type = DC_TYPE_AL981; 1890 sc->dc_flags |= DC_TX_USE_TX_INTR; 1891 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1892 sc->dc_pmode = DC_PMODE_MII; 1893 dc_read_srom(sc, sc->dc_romwidth); 1894 break; 1895 case DC_DEVICEID_AN985: 1896 case DC_DEVICEID_EN2242: 1897 case DC_DEVICEID_3CSOHOB: 1898 sc->dc_type = DC_TYPE_AN985; 1899 sc->dc_flags |= DC_64BIT_HASH; 1900 sc->dc_flags |= DC_TX_USE_TX_INTR; 1901 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1902 sc->dc_pmode = DC_PMODE_MII; 1903 dc_read_srom(sc, sc->dc_romwidth); 1904 break; 1905 case DC_DEVICEID_98713: 1906 case DC_DEVICEID_98713_CP: 1907 if (revision < DC_REVISION_98713A) { 1908 sc->dc_type = DC_TYPE_98713; 1909 } 1910 if (revision >= DC_REVISION_98713A) { 1911 sc->dc_type = DC_TYPE_98713A; 1912 sc->dc_flags |= DC_21143_NWAY; 1913 } 1914 sc->dc_flags |= DC_REDUCED_MII_POLL; 1915 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1916 break; 1917 case DC_DEVICEID_987x5: 1918 case DC_DEVICEID_EN1217: 1919 /* 1920 * Macronix MX98715AEC-C/D/E parts have only a 1921 * 128-bit hash table. We need to deal with these 1922 * in the same manner as the PNIC II so that we 1923 * get the right number of bits out of the 1924 * CRC routine. 1925 */ 1926 if (revision >= DC_REVISION_98715AEC_C && 1927 revision < DC_REVISION_98725) 1928 sc->dc_flags |= DC_128BIT_HASH; 1929 sc->dc_type = DC_TYPE_987x5; 1930 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1931 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1932 break; 1933 case DC_DEVICEID_98727: 1934 sc->dc_type = DC_TYPE_987x5; 1935 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1936 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1937 break; 1938 case DC_DEVICEID_82C115: 1939 sc->dc_type = DC_TYPE_PNICII; 1940 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1941 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1942 break; 1943 case DC_DEVICEID_82C168: 1944 sc->dc_type = DC_TYPE_PNIC; 1945 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1946 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1947 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1948 if (revision < DC_REVISION_82C169) 1949 sc->dc_pmode = DC_PMODE_SYM; 1950 break; 1951 case DC_DEVICEID_AX88140A: 1952 sc->dc_type = DC_TYPE_ASIX; 1953 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL; 1955 sc->dc_pmode = DC_PMODE_MII; 1956 break; 1957 case DC_DEVICEID_RS7112: 1958 sc->dc_type = DC_TYPE_CONEXANT; 1959 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1960 sc->dc_flags |= DC_REDUCED_MII_POLL; 1961 sc->dc_pmode = DC_PMODE_MII; 1962 dc_read_srom(sc, sc->dc_romwidth); 1963 break; 1964 default: 1965 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1966 sc->dc_info->dc_did); 1967 break; 1968 } 1969 1970 /* Save the cache line size. */ 1971 if (DC_IS_DAVICOM(sc)) 1972 sc->dc_cachesize = 0; 1973 else 1974 sc->dc_cachesize = pci_read_config(dev, 1975 DC_PCI_CFLT, 4) & 0xFF; 1976 1977 /* Reset the adapter. */ 1978 dc_reset(sc); 1979 1980 /* Take 21143 out of snooze mode */ 1981 if (DC_IS_INTEL(sc)) { 1982 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1983 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1984 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1985 } 1986 1987 /* 1988 * Try to learn something about the supported media. 1989 * We know that ASIX and ADMtek and Davicom devices 1990 * will *always* be using MII media, so that's a no-brainer. 1991 * The tricky ones are the Macronix/PNIC II and the 1992 * Intel 21143. 1993 */ 1994 if (DC_IS_INTEL(sc)) 1995 dc_parse_21143_srom(sc); 1996 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1997 if (sc->dc_type == DC_TYPE_98713) 1998 sc->dc_pmode = DC_PMODE_MII; 1999 else 2000 sc->dc_pmode = DC_PMODE_SYM; 2001 } else if (!sc->dc_pmode) 2002 sc->dc_pmode = DC_PMODE_MII; 2003 2004 /* 2005 * Get station address from the EEPROM. 2006 */ 2007 switch(sc->dc_type) { 2008 case DC_TYPE_98713: 2009 case DC_TYPE_98713A: 2010 case DC_TYPE_987x5: 2011 case DC_TYPE_PNICII: 2012 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2013 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2014 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2015 break; 2016 case DC_TYPE_PNIC: 2017 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2018 break; 2019 case DC_TYPE_DM9102: 2020 case DC_TYPE_21143: 2021 case DC_TYPE_ASIX: 2022 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2023 break; 2024 case DC_TYPE_AL981: 2025 case DC_TYPE_AN985: 2026 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2027 ETHER_ADDR_LEN); 2028 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2029 break; 2030 case DC_TYPE_CONEXANT: 2031 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2032 break; 2033 default: 2034 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2035 break; 2036 } 2037 2038 sc->dc_unit = unit; 2039 2040 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2041 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2042 2043 if (sc->dc_ldata == NULL) { 2044 printf("dc%d: no memory for list buffers!\n", unit); 2045 if (sc->dc_pnic_rx_buf != NULL) 2046 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2047 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2049 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2050 error = ENXIO; 2051 goto fail; 2052 } 2053 2054 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2055 2056 ifp = &sc->arpcom.ac_if; 2057 ifp->if_softc = sc; 2058 if_initname(ifp, "dc", unit); 2059 ifp->if_mtu = ETHERMTU; 2060 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2061 ifp->if_ioctl = dc_ioctl; 2062 ifp->if_start = dc_start; 2063 ifp->if_watchdog = dc_watchdog; 2064 ifp->if_init = dc_init; 2065 ifp->if_baudrate = 10000000; 2066 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2067 2068 /* 2069 * Do MII setup. If this is a 21143, check for a PHY on the 2070 * MII bus after applying any necessary fixups to twiddle the 2071 * GPIO bits. If we don't end up finding a PHY, restore the 2072 * old selection (SIA only or SIA/SYM) and attach the dcphy 2073 * driver instead. 2074 */ 2075 if (DC_IS_INTEL(sc)) { 2076 dc_apply_fixup(sc, IFM_AUTO); 2077 tmp = sc->dc_pmode; 2078 sc->dc_pmode = DC_PMODE_MII; 2079 } 2080 2081 error = mii_phy_probe(dev, &sc->dc_miibus, 2082 dc_ifmedia_upd, dc_ifmedia_sts); 2083 2084 if (error && DC_IS_INTEL(sc)) { 2085 sc->dc_pmode = tmp; 2086 if (sc->dc_pmode != DC_PMODE_SIA) 2087 sc->dc_pmode = DC_PMODE_SYM; 2088 sc->dc_flags |= DC_21143_NWAY; 2089 mii_phy_probe(dev, &sc->dc_miibus, 2090 dc_ifmedia_upd, dc_ifmedia_sts); 2091 /* 2092 * For non-MII cards, we need to have the 21143 2093 * drive the LEDs. Except there are some systems 2094 * like the NEC VersaPro NoteBook PC which have no 2095 * LEDs, and twiddling these bits has adverse effects 2096 * on them. (I.e. you suddenly can't get a link.) 2097 */ 2098 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2099 sc->dc_flags |= DC_TULIP_LEDS; 2100 error = 0; 2101 } 2102 2103 if (error) { 2104 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2105 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), 2106 M_DEVBUF); 2107 if (sc->dc_pnic_rx_buf != NULL) 2108 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2109 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2110 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2111 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2112 error = ENXIO; 2113 goto fail; 2114 } 2115 2116 /* 2117 * Call MI attach routine. 2118 */ 2119 ether_ifattach(ifp, eaddr); 2120 2121 if (DC_IS_ADMTEK(sc)) { 2122 /* 2123 * Set automatic TX underrun recovery for the ADMtek chips 2124 */ 2125 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2126 } 2127 2128 /* 2129 * Tell the upper layer(s) we support long frames. 2130 */ 2131 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2132 2133 #ifdef SRM_MEDIA 2134 sc->dc_srm_media = 0; 2135 2136 /* Remember the SRM console media setting */ 2137 if (DC_IS_INTEL(sc)) { 2138 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2139 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2140 switch ((command >> 8) & 0xff) { 2141 case 3: 2142 sc->dc_srm_media = IFM_10_T; 2143 break; 2144 case 4: 2145 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2146 break; 2147 case 5: 2148 sc->dc_srm_media = IFM_100_TX; 2149 break; 2150 case 6: 2151 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2152 break; 2153 } 2154 if (sc->dc_srm_media) 2155 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2156 } 2157 #endif 2158 2159 2160 fail: 2161 splx(s); 2162 2163 return(error); 2164 } 2165 2166 static int dc_detach(dev) 2167 device_t dev; 2168 { 2169 struct dc_softc *sc; 2170 struct ifnet *ifp; 2171 int s; 2172 struct dc_mediainfo *m; 2173 2174 s = splimp(); 2175 2176 sc = device_get_softc(dev); 2177 ifp = &sc->arpcom.ac_if; 2178 2179 dc_stop(sc); 2180 ether_ifdetach(ifp); 2181 2182 bus_generic_detach(dev); 2183 device_delete_child(dev, sc->dc_miibus); 2184 2185 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2186 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2187 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2188 2189 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2190 if (sc->dc_pnic_rx_buf != NULL) 2191 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2192 2193 while(sc->dc_mi != NULL) { 2194 m = sc->dc_mi->dc_next; 2195 free(sc->dc_mi, M_DEVBUF); 2196 sc->dc_mi = m; 2197 } 2198 free(sc->dc_srom, M_DEVBUF); 2199 2200 splx(s); 2201 2202 return(0); 2203 } 2204 2205 /* 2206 * Initialize the transmit descriptors. 2207 */ 2208 static int dc_list_tx_init(sc) 2209 struct dc_softc *sc; 2210 { 2211 struct dc_chain_data *cd; 2212 struct dc_list_data *ld; 2213 int i; 2214 2215 cd = &sc->dc_cdata; 2216 ld = sc->dc_ldata; 2217 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2218 if (i == (DC_TX_LIST_CNT - 1)) { 2219 ld->dc_tx_list[i].dc_next = 2220 vtophys(&ld->dc_tx_list[0]); 2221 } else { 2222 ld->dc_tx_list[i].dc_next = 2223 vtophys(&ld->dc_tx_list[i + 1]); 2224 } 2225 cd->dc_tx_chain[i] = NULL; 2226 ld->dc_tx_list[i].dc_data = 0; 2227 ld->dc_tx_list[i].dc_ctl = 0; 2228 } 2229 2230 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2231 2232 return(0); 2233 } 2234 2235 2236 /* 2237 * Initialize the RX descriptors and allocate mbufs for them. Note that 2238 * we arrange the descriptors in a closed ring, so that the last descriptor 2239 * points back to the first. 2240 */ 2241 static int dc_list_rx_init(sc) 2242 struct dc_softc *sc; 2243 { 2244 struct dc_chain_data *cd; 2245 struct dc_list_data *ld; 2246 int i; 2247 2248 cd = &sc->dc_cdata; 2249 ld = sc->dc_ldata; 2250 2251 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2252 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2253 return(ENOBUFS); 2254 if (i == (DC_RX_LIST_CNT - 1)) { 2255 ld->dc_rx_list[i].dc_next = 2256 vtophys(&ld->dc_rx_list[0]); 2257 } else { 2258 ld->dc_rx_list[i].dc_next = 2259 vtophys(&ld->dc_rx_list[i + 1]); 2260 } 2261 } 2262 2263 cd->dc_rx_prod = 0; 2264 2265 return(0); 2266 } 2267 2268 /* 2269 * Initialize an RX descriptor and attach an MBUF cluster. 2270 */ 2271 static int dc_newbuf(sc, i, m) 2272 struct dc_softc *sc; 2273 int i; 2274 struct mbuf *m; 2275 { 2276 struct mbuf *m_new = NULL; 2277 struct dc_desc *c; 2278 2279 c = &sc->dc_ldata->dc_rx_list[i]; 2280 2281 if (m == NULL) { 2282 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 2283 if (m_new == NULL) 2284 return(ENOBUFS); 2285 2286 MCLGET(m_new, MB_DONTWAIT); 2287 if (!(m_new->m_flags & M_EXT)) { 2288 m_freem(m_new); 2289 return(ENOBUFS); 2290 } 2291 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2292 } else { 2293 m_new = m; 2294 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2295 m_new->m_data = m_new->m_ext.ext_buf; 2296 } 2297 2298 m_adj(m_new, sizeof(u_int64_t)); 2299 2300 /* 2301 * If this is a PNIC chip, zero the buffer. This is part 2302 * of the workaround for the receive bug in the 82c168 and 2303 * 82c169 chips. 2304 */ 2305 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2306 bzero((char *)mtod(m_new, char *), m_new->m_len); 2307 2308 sc->dc_cdata.dc_rx_chain[i] = m_new; 2309 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2310 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2311 c->dc_status = DC_RXSTAT_OWN; 2312 2313 return(0); 2314 } 2315 2316 /* 2317 * Grrrrr. 2318 * The PNIC chip has a terrible bug in it that manifests itself during 2319 * periods of heavy activity. The exact mode of failure if difficult to 2320 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2321 * will happen on slow machines. The bug is that sometimes instead of 2322 * uploading one complete frame during reception, it uploads what looks 2323 * like the entire contents of its FIFO memory. The frame we want is at 2324 * the end of the whole mess, but we never know exactly how much data has 2325 * been uploaded, so salvaging the frame is hard. 2326 * 2327 * There is only one way to do it reliably, and it's disgusting. 2328 * Here's what we know: 2329 * 2330 * - We know there will always be somewhere between one and three extra 2331 * descriptors uploaded. 2332 * 2333 * - We know the desired received frame will always be at the end of the 2334 * total data upload. 2335 * 2336 * - We know the size of the desired received frame because it will be 2337 * provided in the length field of the status word in the last descriptor. 2338 * 2339 * Here's what we do: 2340 * 2341 * - When we allocate buffers for the receive ring, we bzero() them. 2342 * This means that we know that the buffer contents should be all 2343 * zeros, except for data uploaded by the chip. 2344 * 2345 * - We also force the PNIC chip to upload frames that include the 2346 * ethernet CRC at the end. 2347 * 2348 * - We gather all of the bogus frame data into a single buffer. 2349 * 2350 * - We then position a pointer at the end of this buffer and scan 2351 * backwards until we encounter the first non-zero byte of data. 2352 * This is the end of the received frame. We know we will encounter 2353 * some data at the end of the frame because the CRC will always be 2354 * there, so even if the sender transmits a packet of all zeros, 2355 * we won't be fooled. 2356 * 2357 * - We know the size of the actual received frame, so we subtract 2358 * that value from the current pointer location. This brings us 2359 * to the start of the actual received packet. 2360 * 2361 * - We copy this into an mbuf and pass it on, along with the actual 2362 * frame length. 2363 * 2364 * The performance hit is tremendous, but it beats dropping frames all 2365 * the time. 2366 */ 2367 2368 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2369 static void dc_pnic_rx_bug_war(sc, idx) 2370 struct dc_softc *sc; 2371 int idx; 2372 { 2373 struct dc_desc *cur_rx; 2374 struct dc_desc *c = NULL; 2375 struct mbuf *m = NULL; 2376 unsigned char *ptr; 2377 int i, total_len; 2378 u_int32_t rxstat = 0; 2379 2380 i = sc->dc_pnic_rx_bug_save; 2381 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2382 ptr = sc->dc_pnic_rx_buf; 2383 bzero(ptr, DC_RXLEN * 5); 2384 2385 /* Copy all the bytes from the bogus buffers. */ 2386 while (1) { 2387 c = &sc->dc_ldata->dc_rx_list[i]; 2388 rxstat = c->dc_status; 2389 m = sc->dc_cdata.dc_rx_chain[i]; 2390 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2391 ptr += DC_RXLEN; 2392 /* If this is the last buffer, break out. */ 2393 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2394 break; 2395 dc_newbuf(sc, i, m); 2396 DC_INC(i, DC_RX_LIST_CNT); 2397 } 2398 2399 /* Find the length of the actual receive frame. */ 2400 total_len = DC_RXBYTES(rxstat); 2401 2402 /* Scan backwards until we hit a non-zero byte. */ 2403 while(*ptr == 0x00) 2404 ptr--; 2405 2406 /* Round off. */ 2407 if ((uintptr_t)(ptr) & 0x3) 2408 ptr -= 1; 2409 2410 /* Now find the start of the frame. */ 2411 ptr -= total_len; 2412 if (ptr < sc->dc_pnic_rx_buf) 2413 ptr = sc->dc_pnic_rx_buf; 2414 2415 /* 2416 * Now copy the salvaged frame to the last mbuf and fake up 2417 * the status word to make it look like a successful 2418 * frame reception. 2419 */ 2420 dc_newbuf(sc, i, m); 2421 bcopy(ptr, mtod(m, char *), total_len); 2422 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2423 2424 return; 2425 } 2426 2427 /* 2428 * This routine searches the RX ring for dirty descriptors in the 2429 * event that the rxeof routine falls out of sync with the chip's 2430 * current descriptor pointer. This may happen sometimes as a result 2431 * of a "no RX buffer available" condition that happens when the chip 2432 * consumes all of the RX buffers before the driver has a chance to 2433 * process the RX ring. This routine may need to be called more than 2434 * once to bring the driver back in sync with the chip, however we 2435 * should still be getting RX DONE interrupts to drive the search 2436 * for new packets in the RX ring, so we should catch up eventually. 2437 */ 2438 static int dc_rx_resync(sc) 2439 struct dc_softc *sc; 2440 { 2441 int i, pos; 2442 struct dc_desc *cur_rx; 2443 2444 pos = sc->dc_cdata.dc_rx_prod; 2445 2446 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2447 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2448 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2449 break; 2450 DC_INC(pos, DC_RX_LIST_CNT); 2451 } 2452 2453 /* If the ring really is empty, then just return. */ 2454 if (i == DC_RX_LIST_CNT) 2455 return(0); 2456 2457 /* We've fallen behing the chip: catch it. */ 2458 sc->dc_cdata.dc_rx_prod = pos; 2459 2460 return(EAGAIN); 2461 } 2462 2463 /* 2464 * A frame has been uploaded: pass the resulting mbuf chain up to 2465 * the higher level protocols. 2466 */ 2467 static void dc_rxeof(sc) 2468 struct dc_softc *sc; 2469 { 2470 struct mbuf *m; 2471 struct ifnet *ifp; 2472 struct dc_desc *cur_rx; 2473 int i, total_len = 0; 2474 u_int32_t rxstat; 2475 2476 ifp = &sc->arpcom.ac_if; 2477 i = sc->dc_cdata.dc_rx_prod; 2478 2479 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2480 2481 #ifdef DEVICE_POLLING 2482 if (ifp->if_flags & IFF_POLLING) { 2483 if (sc->rxcycles <= 0) 2484 break; 2485 sc->rxcycles--; 2486 } 2487 #endif /* DEVICE_POLLING */ 2488 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2489 rxstat = cur_rx->dc_status; 2490 m = sc->dc_cdata.dc_rx_chain[i]; 2491 total_len = DC_RXBYTES(rxstat); 2492 2493 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2494 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2495 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2496 sc->dc_pnic_rx_bug_save = i; 2497 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2498 DC_INC(i, DC_RX_LIST_CNT); 2499 continue; 2500 } 2501 dc_pnic_rx_bug_war(sc, i); 2502 rxstat = cur_rx->dc_status; 2503 total_len = DC_RXBYTES(rxstat); 2504 } 2505 } 2506 2507 sc->dc_cdata.dc_rx_chain[i] = NULL; 2508 2509 /* 2510 * If an error occurs, update stats, clear the 2511 * status word and leave the mbuf cluster in place: 2512 * it should simply get re-used next time this descriptor 2513 * comes up in the ring. However, don't report long 2514 * frames as errors since they could be vlans 2515 */ 2516 if ((rxstat & DC_RXSTAT_RXERR)){ 2517 if (!(rxstat & DC_RXSTAT_GIANT) || 2518 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2519 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2520 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2521 ifp->if_ierrors++; 2522 if (rxstat & DC_RXSTAT_COLLSEEN) 2523 ifp->if_collisions++; 2524 dc_newbuf(sc, i, m); 2525 if (rxstat & DC_RXSTAT_CRCERR) { 2526 DC_INC(i, DC_RX_LIST_CNT); 2527 continue; 2528 } else { 2529 dc_init(sc); 2530 return; 2531 } 2532 } 2533 } 2534 2535 /* No errors; receive the packet. */ 2536 total_len -= ETHER_CRC_LEN; 2537 2538 #ifdef __i386__ 2539 /* 2540 * On the x86 we do not have alignment problems, so try to 2541 * allocate a new buffer for the receive ring, and pass up 2542 * the one where the packet is already, saving the expensive 2543 * copy done in m_devget(). 2544 * If we are on an architecture with alignment problems, or 2545 * if the allocation fails, then use m_devget and leave the 2546 * existing buffer in the receive ring. 2547 */ 2548 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2549 m->m_pkthdr.rcvif = ifp; 2550 m->m_pkthdr.len = m->m_len = total_len; 2551 DC_INC(i, DC_RX_LIST_CNT); 2552 } else 2553 #endif 2554 { 2555 struct mbuf *m0; 2556 2557 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2558 total_len + ETHER_ALIGN, 0, ifp, NULL); 2559 dc_newbuf(sc, i, m); 2560 DC_INC(i, DC_RX_LIST_CNT); 2561 if (m0 == NULL) { 2562 ifp->if_ierrors++; 2563 continue; 2564 } 2565 m_adj(m0, ETHER_ALIGN); 2566 m = m0; 2567 } 2568 2569 ifp->if_ipackets++; 2570 (*ifp->if_input)(ifp, m); 2571 } 2572 2573 sc->dc_cdata.dc_rx_prod = i; 2574 } 2575 2576 /* 2577 * A frame was downloaded to the chip. It's safe for us to clean up 2578 * the list buffers. 2579 */ 2580 2581 static void 2582 dc_txeof(sc) 2583 struct dc_softc *sc; 2584 { 2585 struct dc_desc *cur_tx = NULL; 2586 struct ifnet *ifp; 2587 int idx; 2588 2589 ifp = &sc->arpcom.ac_if; 2590 2591 /* 2592 * Go through our tx list and free mbufs for those 2593 * frames that have been transmitted. 2594 */ 2595 idx = sc->dc_cdata.dc_tx_cons; 2596 while(idx != sc->dc_cdata.dc_tx_prod) { 2597 u_int32_t txstat; 2598 2599 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2600 txstat = cur_tx->dc_status; 2601 2602 if (txstat & DC_TXSTAT_OWN) 2603 break; 2604 2605 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2606 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2607 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2608 /* 2609 * Yes, the PNIC is so brain damaged 2610 * that it will sometimes generate a TX 2611 * underrun error while DMAing the RX 2612 * filter setup frame. If we detect this, 2613 * we have to send the setup frame again, 2614 * or else the filter won't be programmed 2615 * correctly. 2616 */ 2617 if (DC_IS_PNIC(sc)) { 2618 if (txstat & DC_TXSTAT_ERRSUM) 2619 dc_setfilt(sc); 2620 } 2621 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2622 } 2623 sc->dc_cdata.dc_tx_cnt--; 2624 DC_INC(idx, DC_TX_LIST_CNT); 2625 continue; 2626 } 2627 2628 if (DC_IS_CONEXANT(sc)) { 2629 /* 2630 * For some reason Conexant chips like 2631 * setting the CARRLOST flag even when 2632 * the carrier is there. In CURRENT we 2633 * have the same problem for Xircom 2634 * cards ! 2635 */ 2636 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2637 sc->dc_pmode == DC_PMODE_MII && 2638 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2639 DC_TXSTAT_NOCARRIER))) 2640 txstat &= ~DC_TXSTAT_ERRSUM; 2641 } else { 2642 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2643 sc->dc_pmode == DC_PMODE_MII && 2644 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2645 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2646 txstat &= ~DC_TXSTAT_ERRSUM; 2647 } 2648 2649 if (txstat & DC_TXSTAT_ERRSUM) { 2650 ifp->if_oerrors++; 2651 if (txstat & DC_TXSTAT_EXCESSCOLL) 2652 ifp->if_collisions++; 2653 if (txstat & DC_TXSTAT_LATECOLL) 2654 ifp->if_collisions++; 2655 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2656 dc_init(sc); 2657 return; 2658 } 2659 } 2660 2661 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2662 2663 ifp->if_opackets++; 2664 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2665 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2666 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2667 } 2668 2669 sc->dc_cdata.dc_tx_cnt--; 2670 DC_INC(idx, DC_TX_LIST_CNT); 2671 } 2672 2673 if (idx != sc->dc_cdata.dc_tx_cons) { 2674 /* some buffers have been freed */ 2675 sc->dc_cdata.dc_tx_cons = idx; 2676 ifp->if_flags &= ~IFF_OACTIVE; 2677 } 2678 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2679 2680 return; 2681 } 2682 2683 static void dc_tick(xsc) 2684 void *xsc; 2685 { 2686 struct dc_softc *sc; 2687 struct mii_data *mii; 2688 struct ifnet *ifp; 2689 int s; 2690 u_int32_t r; 2691 2692 s = splimp(); 2693 2694 sc = xsc; 2695 ifp = &sc->arpcom.ac_if; 2696 mii = device_get_softc(sc->dc_miibus); 2697 2698 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2699 if (sc->dc_flags & DC_21143_NWAY) { 2700 r = CSR_READ_4(sc, DC_10BTSTAT); 2701 if (IFM_SUBTYPE(mii->mii_media_active) == 2702 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2703 sc->dc_link = 0; 2704 mii_mediachg(mii); 2705 } 2706 if (IFM_SUBTYPE(mii->mii_media_active) == 2707 IFM_10_T && (r & DC_TSTAT_LS10)) { 2708 sc->dc_link = 0; 2709 mii_mediachg(mii); 2710 } 2711 if (sc->dc_link == 0) 2712 mii_tick(mii); 2713 } else { 2714 r = CSR_READ_4(sc, DC_ISR); 2715 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2716 sc->dc_cdata.dc_tx_cnt == 0) 2717 mii_tick(mii); 2718 if (!(mii->mii_media_status & IFM_ACTIVE)) 2719 sc->dc_link = 0; 2720 } 2721 } else 2722 mii_tick(mii); 2723 2724 /* 2725 * When the init routine completes, we expect to be able to send 2726 * packets right away, and in fact the network code will send a 2727 * gratuitous ARP the moment the init routine marks the interface 2728 * as running. However, even though the MAC may have been initialized, 2729 * there may be a delay of a few seconds before the PHY completes 2730 * autonegotiation and the link is brought up. Any transmissions 2731 * made during that delay will be lost. Dealing with this is tricky: 2732 * we can't just pause in the init routine while waiting for the 2733 * PHY to come ready since that would bring the whole system to 2734 * a screeching halt for several seconds. 2735 * 2736 * What we do here is prevent the TX start routine from sending 2737 * any packets until a link has been established. After the 2738 * interface has been initialized, the tick routine will poll 2739 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2740 * that time, packets will stay in the send queue, and once the 2741 * link comes up, they will be flushed out to the wire. 2742 */ 2743 if (!sc->dc_link) { 2744 mii_pollstat(mii); 2745 if (mii->mii_media_status & IFM_ACTIVE && 2746 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2747 sc->dc_link++; 2748 if (ifp->if_snd.ifq_head != NULL) 2749 dc_start(ifp); 2750 } 2751 } 2752 2753 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2754 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2755 else 2756 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2757 2758 splx(s); 2759 2760 return; 2761 } 2762 2763 /* 2764 * A transmit underrun has occurred. Back off the transmit threshold, 2765 * or switch to store and forward mode if we have to. 2766 */ 2767 static void dc_tx_underrun(sc) 2768 struct dc_softc *sc; 2769 { 2770 u_int32_t isr; 2771 int i; 2772 2773 if (DC_IS_DAVICOM(sc)) 2774 dc_init(sc); 2775 2776 if (DC_IS_INTEL(sc)) { 2777 /* 2778 * The real 21143 requires that the transmitter be idle 2779 * in order to change the transmit threshold or store 2780 * and forward state. 2781 */ 2782 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2783 2784 for (i = 0; i < DC_TIMEOUT; i++) { 2785 isr = CSR_READ_4(sc, DC_ISR); 2786 if (isr & DC_ISR_TX_IDLE) 2787 break; 2788 DELAY(10); 2789 } 2790 if (i == DC_TIMEOUT) { 2791 printf("dc%d: failed to force tx to idle state\n", 2792 sc->dc_unit); 2793 dc_init(sc); 2794 } 2795 } 2796 2797 printf("dc%d: TX underrun -- ", sc->dc_unit); 2798 sc->dc_txthresh += DC_TXTHRESH_INC; 2799 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2800 printf("using store and forward mode\n"); 2801 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2802 } else { 2803 printf("increasing TX threshold\n"); 2804 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2805 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2806 } 2807 2808 if (DC_IS_INTEL(sc)) 2809 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2810 2811 return; 2812 } 2813 2814 #ifdef DEVICE_POLLING 2815 static poll_handler_t dc_poll; 2816 2817 static void 2818 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2819 { 2820 struct dc_softc *sc = ifp->if_softc; 2821 2822 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2823 /* Re-enable interrupts. */ 2824 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2825 return; 2826 } 2827 sc->rxcycles = count; 2828 dc_rxeof(sc); 2829 dc_txeof(sc); 2830 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2831 dc_start(ifp); 2832 2833 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2834 u_int32_t status; 2835 2836 status = CSR_READ_4(sc, DC_ISR); 2837 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2838 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2839 DC_ISR_BUS_ERR); 2840 if (!status) 2841 return ; 2842 /* ack what we have */ 2843 CSR_WRITE_4(sc, DC_ISR, status); 2844 2845 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2846 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2847 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2848 2849 if (dc_rx_resync(sc)) 2850 dc_rxeof(sc); 2851 } 2852 /* restart transmit unit if necessary */ 2853 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2854 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2855 2856 if (status & DC_ISR_TX_UNDERRUN) 2857 dc_tx_underrun(sc); 2858 2859 if (status & DC_ISR_BUS_ERR) { 2860 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2861 dc_reset(sc); 2862 dc_init(sc); 2863 } 2864 } 2865 } 2866 #endif /* DEVICE_POLLING */ 2867 2868 static void dc_intr(arg) 2869 void *arg; 2870 { 2871 struct dc_softc *sc; 2872 struct ifnet *ifp; 2873 u_int32_t status; 2874 2875 sc = arg; 2876 2877 if (sc->suspended) { 2878 return; 2879 } 2880 2881 ifp = &sc->arpcom.ac_if; 2882 2883 #ifdef DEVICE_POLLING 2884 if (ifp->if_flags & IFF_POLLING) 2885 return; 2886 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2887 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2888 return; 2889 } 2890 #endif /* DEVICE_POLLING */ 2891 2892 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2893 return ; 2894 2895 /* Suppress unwanted interrupts */ 2896 if (!(ifp->if_flags & IFF_UP)) { 2897 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2898 dc_stop(sc); 2899 return; 2900 } 2901 2902 /* Disable interrupts. */ 2903 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2904 2905 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2906 2907 CSR_WRITE_4(sc, DC_ISR, status); 2908 2909 if (status & DC_ISR_RX_OK) { 2910 int curpkts; 2911 curpkts = ifp->if_ipackets; 2912 dc_rxeof(sc); 2913 if (curpkts == ifp->if_ipackets) { 2914 while(dc_rx_resync(sc)) 2915 dc_rxeof(sc); 2916 } 2917 } 2918 2919 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2920 dc_txeof(sc); 2921 2922 if (status & DC_ISR_TX_IDLE) { 2923 dc_txeof(sc); 2924 if (sc->dc_cdata.dc_tx_cnt) { 2925 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2926 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2927 } 2928 } 2929 2930 if (status & DC_ISR_TX_UNDERRUN) 2931 dc_tx_underrun(sc); 2932 2933 if ((status & DC_ISR_RX_WATDOGTIMEO) 2934 || (status & DC_ISR_RX_NOBUF)) { 2935 int curpkts; 2936 curpkts = ifp->if_ipackets; 2937 dc_rxeof(sc); 2938 if (curpkts == ifp->if_ipackets) { 2939 while(dc_rx_resync(sc)) 2940 dc_rxeof(sc); 2941 } 2942 } 2943 2944 if (status & DC_ISR_BUS_ERR) { 2945 dc_reset(sc); 2946 dc_init(sc); 2947 } 2948 } 2949 2950 /* Re-enable interrupts. */ 2951 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2952 2953 if (ifp->if_snd.ifq_head != NULL) 2954 dc_start(ifp); 2955 2956 return; 2957 } 2958 2959 /* 2960 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2961 * pointers to the fragment pointers. 2962 */ 2963 static int dc_encap(sc, m_head, txidx) 2964 struct dc_softc *sc; 2965 struct mbuf *m_head; 2966 u_int32_t *txidx; 2967 { 2968 struct dc_desc *f = NULL; 2969 struct mbuf *m; 2970 int frag, cur, cnt = 0; 2971 2972 /* 2973 * Start packing the mbufs in this chain into 2974 * the fragment pointers. Stop when we run out 2975 * of fragments or hit the end of the mbuf chain. 2976 */ 2977 m = m_head; 2978 cur = frag = *txidx; 2979 2980 for (m = m_head; m != NULL; m = m->m_next) { 2981 if (m->m_len != 0) { 2982 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2983 if (*txidx != sc->dc_cdata.dc_tx_prod && 2984 frag == (DC_TX_LIST_CNT - 1)) 2985 return(ENOBUFS); 2986 } 2987 if ((DC_TX_LIST_CNT - 2988 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2989 return(ENOBUFS); 2990 2991 f = &sc->dc_ldata->dc_tx_list[frag]; 2992 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2993 if (cnt == 0) { 2994 f->dc_status = 0; 2995 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2996 } else 2997 f->dc_status = DC_TXSTAT_OWN; 2998 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2999 cur = frag; 3000 DC_INC(frag, DC_TX_LIST_CNT); 3001 cnt++; 3002 } 3003 } 3004 3005 if (m != NULL) 3006 return(ENOBUFS); 3007 3008 sc->dc_cdata.dc_tx_cnt += cnt; 3009 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3010 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3011 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3012 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3013 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3014 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3015 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3016 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3017 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3018 *txidx = frag; 3019 3020 return(0); 3021 } 3022 3023 /* 3024 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3025 * Needed for some really badly behaved chips that just can't 3026 * do scatter/gather correctly. 3027 */ 3028 static int dc_coal(sc, m_head) 3029 struct dc_softc *sc; 3030 struct mbuf **m_head; 3031 { 3032 struct mbuf *m_new, *m; 3033 3034 m = *m_head; 3035 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 3036 if (m_new == NULL) 3037 return(ENOBUFS); 3038 if (m->m_pkthdr.len > MHLEN) { 3039 MCLGET(m_new, MB_DONTWAIT); 3040 if (!(m_new->m_flags & M_EXT)) { 3041 m_freem(m_new); 3042 return(ENOBUFS); 3043 } 3044 } 3045 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3046 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3047 m_freem(m); 3048 *m_head = m_new; 3049 3050 return(0); 3051 } 3052 3053 /* 3054 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3055 * to the mbuf data regions directly in the transmit lists. We also save a 3056 * copy of the pointers since the transmit list fragment pointers are 3057 * physical addresses. 3058 */ 3059 3060 static void dc_start(ifp) 3061 struct ifnet *ifp; 3062 { 3063 struct dc_softc *sc; 3064 struct mbuf *m_head = NULL; 3065 int idx; 3066 3067 sc = ifp->if_softc; 3068 3069 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3070 return; 3071 3072 if (ifp->if_flags & IFF_OACTIVE) 3073 return; 3074 3075 idx = sc->dc_cdata.dc_tx_prod; 3076 3077 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3078 IF_DEQUEUE(&ifp->if_snd, m_head); 3079 if (m_head == NULL) 3080 break; 3081 3082 if (sc->dc_flags & DC_TX_COALESCE && 3083 m_head->m_next != NULL) { 3084 /* only coalesce if have >1 mbufs */ 3085 if (dc_coal(sc, &m_head)) { 3086 IF_PREPEND(&ifp->if_snd, m_head); 3087 ifp->if_flags |= IFF_OACTIVE; 3088 break; 3089 } 3090 } 3091 3092 if (dc_encap(sc, m_head, &idx)) { 3093 IF_PREPEND(&ifp->if_snd, m_head); 3094 ifp->if_flags |= IFF_OACTIVE; 3095 break; 3096 } 3097 3098 /* 3099 * If there's a BPF listener, bounce a copy of this frame 3100 * to him. 3101 */ 3102 BPF_MTAP(ifp, m_head); 3103 3104 if (sc->dc_flags & DC_TX_ONE) { 3105 ifp->if_flags |= IFF_OACTIVE; 3106 break; 3107 } 3108 } 3109 3110 /* Transmit */ 3111 sc->dc_cdata.dc_tx_prod = idx; 3112 if (!(sc->dc_flags & DC_TX_POLL)) 3113 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3114 3115 /* 3116 * Set a timeout in case the chip goes out to lunch. 3117 */ 3118 ifp->if_timer = 5; 3119 3120 return; 3121 } 3122 3123 static void dc_init(xsc) 3124 void *xsc; 3125 { 3126 struct dc_softc *sc = xsc; 3127 struct ifnet *ifp = &sc->arpcom.ac_if; 3128 struct mii_data *mii; 3129 int s; 3130 3131 s = splimp(); 3132 3133 mii = device_get_softc(sc->dc_miibus); 3134 3135 /* 3136 * Cancel pending I/O and free all RX/TX buffers. 3137 */ 3138 dc_stop(sc); 3139 dc_reset(sc); 3140 3141 /* 3142 * Set cache alignment and burst length. 3143 */ 3144 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3145 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3146 else 3147 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3148 /* 3149 * Evenly share the bus between receive and transmit process. 3150 */ 3151 if (DC_IS_INTEL(sc)) 3152 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3153 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3154 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3155 } else { 3156 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3157 } 3158 if (sc->dc_flags & DC_TX_POLL) 3159 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3160 switch(sc->dc_cachesize) { 3161 case 32: 3162 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3163 break; 3164 case 16: 3165 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3166 break; 3167 case 8: 3168 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3169 break; 3170 case 0: 3171 default: 3172 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3173 break; 3174 } 3175 3176 if (sc->dc_flags & DC_TX_STORENFWD) 3177 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3178 else { 3179 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3180 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3181 } else { 3182 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3183 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3184 } 3185 } 3186 3187 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3188 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3189 3190 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3191 /* 3192 * The app notes for the 98713 and 98715A say that 3193 * in order to have the chips operate properly, a magic 3194 * number must be written to CSR16. Macronix does not 3195 * document the meaning of these bits so there's no way 3196 * to know exactly what they do. The 98713 has a magic 3197 * number all its own; the rest all use a different one. 3198 */ 3199 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3200 if (sc->dc_type == DC_TYPE_98713) 3201 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3202 else 3203 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3204 } 3205 3206 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3207 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3208 3209 /* Init circular RX list. */ 3210 if (dc_list_rx_init(sc) == ENOBUFS) { 3211 printf("dc%d: initialization failed: no " 3212 "memory for rx buffers\n", sc->dc_unit); 3213 dc_stop(sc); 3214 (void)splx(s); 3215 return; 3216 } 3217 3218 /* 3219 * Init tx descriptors. 3220 */ 3221 dc_list_tx_init(sc); 3222 3223 /* 3224 * Load the address of the RX list. 3225 */ 3226 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3227 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3228 3229 /* 3230 * Enable interrupts. 3231 */ 3232 #ifdef DEVICE_POLLING 3233 /* 3234 * ... but only if we are not polling, and make sure they are off in 3235 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3236 * after a reset. 3237 */ 3238 if (ifp->if_flags & IFF_POLLING) 3239 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3240 else 3241 #endif 3242 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3243 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3244 3245 /* Enable transmitter. */ 3246 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3247 3248 /* 3249 * If this is an Intel 21143 and we're not using the 3250 * MII port, program the LED control pins so we get 3251 * link and activity indications. 3252 */ 3253 if (sc->dc_flags & DC_TULIP_LEDS) { 3254 CSR_WRITE_4(sc, DC_WATCHDOG, 3255 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3256 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3257 } 3258 3259 /* 3260 * Load the RX/multicast filter. We do this sort of late 3261 * because the filter programming scheme on the 21143 and 3262 * some clones requires DMAing a setup frame via the TX 3263 * engine, and we need the transmitter enabled for that. 3264 */ 3265 dc_setfilt(sc); 3266 3267 /* Enable receiver. */ 3268 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3269 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3270 3271 mii_mediachg(mii); 3272 dc_setcfg(sc, sc->dc_if_media); 3273 3274 ifp->if_flags |= IFF_RUNNING; 3275 ifp->if_flags &= ~IFF_OACTIVE; 3276 3277 (void)splx(s); 3278 3279 /* Don't start the ticker if this is a homePNA link. */ 3280 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3281 sc->dc_link = 1; 3282 else { 3283 if (sc->dc_flags & DC_21143_NWAY) 3284 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3285 else 3286 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3287 } 3288 3289 #ifdef SRM_MEDIA 3290 if(sc->dc_srm_media) { 3291 struct ifreq ifr; 3292 3293 ifr.ifr_media = sc->dc_srm_media; 3294 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3295 sc->dc_srm_media = 0; 3296 } 3297 #endif 3298 return; 3299 } 3300 3301 /* 3302 * Set media options. 3303 */ 3304 static int dc_ifmedia_upd(ifp) 3305 struct ifnet *ifp; 3306 { 3307 struct dc_softc *sc; 3308 struct mii_data *mii; 3309 struct ifmedia *ifm; 3310 3311 sc = ifp->if_softc; 3312 mii = device_get_softc(sc->dc_miibus); 3313 mii_mediachg(mii); 3314 ifm = &mii->mii_media; 3315 3316 if (DC_IS_DAVICOM(sc) && 3317 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3318 dc_setcfg(sc, ifm->ifm_media); 3319 else 3320 sc->dc_link = 0; 3321 3322 return(0); 3323 } 3324 3325 /* 3326 * Report current media status. 3327 */ 3328 static void dc_ifmedia_sts(ifp, ifmr) 3329 struct ifnet *ifp; 3330 struct ifmediareq *ifmr; 3331 { 3332 struct dc_softc *sc; 3333 struct mii_data *mii; 3334 struct ifmedia *ifm; 3335 3336 sc = ifp->if_softc; 3337 mii = device_get_softc(sc->dc_miibus); 3338 mii_pollstat(mii); 3339 ifm = &mii->mii_media; 3340 if (DC_IS_DAVICOM(sc)) { 3341 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3342 ifmr->ifm_active = ifm->ifm_media; 3343 ifmr->ifm_status = 0; 3344 return; 3345 } 3346 } 3347 ifmr->ifm_active = mii->mii_media_active; 3348 ifmr->ifm_status = mii->mii_media_status; 3349 3350 return; 3351 } 3352 3353 static int dc_ioctl(ifp, command, data, cr) 3354 struct ifnet *ifp; 3355 u_long command; 3356 caddr_t data; 3357 struct ucred *cr; 3358 { 3359 struct dc_softc *sc = ifp->if_softc; 3360 struct ifreq *ifr = (struct ifreq *) data; 3361 struct mii_data *mii; 3362 int s, error = 0; 3363 3364 s = splimp(); 3365 3366 switch(command) { 3367 case SIOCSIFADDR: 3368 case SIOCGIFADDR: 3369 case SIOCSIFMTU: 3370 error = ether_ioctl(ifp, command, data); 3371 break; 3372 case SIOCSIFFLAGS: 3373 if (ifp->if_flags & IFF_UP) { 3374 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3375 (IFF_PROMISC | IFF_ALLMULTI); 3376 if (ifp->if_flags & IFF_RUNNING) { 3377 if (need_setfilt) 3378 dc_setfilt(sc); 3379 } else { 3380 sc->dc_txthresh = 0; 3381 dc_init(sc); 3382 } 3383 } else { 3384 if (ifp->if_flags & IFF_RUNNING) 3385 dc_stop(sc); 3386 } 3387 sc->dc_if_flags = ifp->if_flags; 3388 error = 0; 3389 break; 3390 case SIOCADDMULTI: 3391 case SIOCDELMULTI: 3392 dc_setfilt(sc); 3393 error = 0; 3394 break; 3395 case SIOCGIFMEDIA: 3396 case SIOCSIFMEDIA: 3397 mii = device_get_softc(sc->dc_miibus); 3398 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3399 #ifdef SRM_MEDIA 3400 if (sc->dc_srm_media) 3401 sc->dc_srm_media = 0; 3402 #endif 3403 break; 3404 default: 3405 error = EINVAL; 3406 break; 3407 } 3408 3409 (void)splx(s); 3410 3411 return(error); 3412 } 3413 3414 static void dc_watchdog(ifp) 3415 struct ifnet *ifp; 3416 { 3417 struct dc_softc *sc; 3418 3419 sc = ifp->if_softc; 3420 3421 ifp->if_oerrors++; 3422 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3423 3424 dc_stop(sc); 3425 dc_reset(sc); 3426 dc_init(sc); 3427 3428 if (ifp->if_snd.ifq_head != NULL) 3429 dc_start(ifp); 3430 3431 return; 3432 } 3433 3434 /* 3435 * Stop the adapter and free any mbufs allocated to the 3436 * RX and TX lists. 3437 */ 3438 static void dc_stop(sc) 3439 struct dc_softc *sc; 3440 { 3441 int i; 3442 struct ifnet *ifp; 3443 3444 ifp = &sc->arpcom.ac_if; 3445 ifp->if_timer = 0; 3446 3447 callout_stop(&sc->dc_stat_timer); 3448 3449 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3450 #ifdef DEVICE_POLLING 3451 ether_poll_deregister(ifp); 3452 #endif 3453 3454 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3455 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3456 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3457 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3458 sc->dc_link = 0; 3459 3460 /* 3461 * Free data in the RX lists. 3462 */ 3463 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3464 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3465 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3466 sc->dc_cdata.dc_rx_chain[i] = NULL; 3467 } 3468 } 3469 bzero((char *)&sc->dc_ldata->dc_rx_list, 3470 sizeof(sc->dc_ldata->dc_rx_list)); 3471 3472 /* 3473 * Free the TX list buffers. 3474 */ 3475 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3476 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3477 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3478 DC_TXCTL_SETUP) || 3479 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3480 DC_TXCTL_LASTFRAG)) { 3481 sc->dc_cdata.dc_tx_chain[i] = NULL; 3482 continue; 3483 } 3484 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3485 sc->dc_cdata.dc_tx_chain[i] = NULL; 3486 } 3487 } 3488 3489 bzero((char *)&sc->dc_ldata->dc_tx_list, 3490 sizeof(sc->dc_ldata->dc_tx_list)); 3491 3492 return; 3493 } 3494 3495 /* 3496 * Stop all chip I/O so that the kernel's probe routines don't 3497 * get confused by errant DMAs when rebooting. 3498 */ 3499 static void dc_shutdown(dev) 3500 device_t dev; 3501 { 3502 struct dc_softc *sc; 3503 3504 sc = device_get_softc(dev); 3505 3506 dc_stop(sc); 3507 3508 return; 3509 } 3510 3511 /* 3512 * Device suspend routine. Stop the interface and save some PCI 3513 * settings in case the BIOS doesn't restore them properly on 3514 * resume. 3515 */ 3516 static int dc_suspend(dev) 3517 device_t dev; 3518 { 3519 int i; 3520 int s; 3521 struct dc_softc *sc; 3522 3523 s = splimp(); 3524 3525 sc = device_get_softc(dev); 3526 3527 dc_stop(sc); 3528 3529 for (i = 0; i < 5; i++) 3530 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3531 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3532 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3533 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3534 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3535 3536 sc->suspended = 1; 3537 3538 splx(s); 3539 return (0); 3540 } 3541 3542 /* 3543 * Device resume routine. Restore some PCI settings in case the BIOS 3544 * doesn't, re-enable busmastering, and restart the interface if 3545 * appropriate. 3546 */ 3547 static int dc_resume(dev) 3548 device_t dev; 3549 { 3550 int i; 3551 int s; 3552 struct dc_softc *sc; 3553 struct ifnet *ifp; 3554 3555 s = splimp(); 3556 3557 sc = device_get_softc(dev); 3558 ifp = &sc->arpcom.ac_if; 3559 3560 dc_acpi(dev); 3561 3562 /* better way to do this? */ 3563 for (i = 0; i < 5; i++) 3564 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3565 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3566 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3567 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3568 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3569 3570 /* reenable busmastering */ 3571 pci_enable_busmaster(dev); 3572 pci_enable_io(dev, DC_RES); 3573 3574 /* reinitialize interface if necessary */ 3575 if (ifp->if_flags & IFF_UP) 3576 dc_init(sc); 3577 3578 sc->suspended = 0; 3579 3580 splx(s); 3581 return (0); 3582 } 3583