1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.56 2008/05/14 11:59:19 sephe Exp $ 34 */ 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Conexant LANfinity (www.conexant.com) 52 * 53 * Datasheets for the 21143 are available at developer.intel.com. 54 * Datasheets for the clone parts can be found at their respective sites. 55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 56 * The PNIC II is essentially a Macronix 98715A chip; the only difference 57 * worth noting is that its multicast hash table is only 128 bits wide 58 * instead of 512. 59 * 60 * Written by Bill Paul <wpaul@ee.columbia.edu> 61 * Electrical Engineering Department 62 * Columbia University, New York City 63 */ 64 65 /* 66 * The Intel 21143 is the successor to the DEC 21140. It is basically 67 * the same as the 21140 but with a few new features. The 21143 supports 68 * three kinds of media attachments: 69 * 70 * o MII port, for 10Mbps and 100Mbps support and NWAY 71 * autonegotiation provided by an external PHY. 72 * o SYM port, for symbol mode 100Mbps support. 73 * o 10baseT port. 74 * o AUI/BNC port. 75 * 76 * The 100Mbps SYM port and 10baseT port can be used together in 77 * combination with the internal NWAY support to create a 10/100 78 * autosensing configuration. 79 * 80 * Note that not all tulip workalikes are handled in this driver: we only 81 * deal with those which are relatively well behaved. The Winbond is 82 * handled separately due to its different register offsets and the 83 * special handling needed for its various bugs. The PNIC is handled 84 * here, but I'm not thrilled about it. 85 * 86 * All of the workalike chips use some form of MII transceiver support 87 * with the exception of the Macronix chips, which also have a SYM port. 88 * The ASIX AX88140A is also documented to have a SYM port, but all 89 * the cards I've seen use an MII transceiver, probably because the 90 * AX88140A doesn't support internal NWAY. 91 */ 92 93 #include "opt_polling.h" 94 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/interrupt.h> 102 #include <sys/socket.h> 103 #include <sys/sysctl.h> 104 #include <sys/bus.h> 105 #include <sys/rman.h> 106 #include <sys/thread2.h> 107 108 #include <net/if.h> 109 #include <net/ifq_var.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/vlan/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <vm/vm.h> /* for vtophys */ 120 #include <vm/pmap.h> /* for vtophys */ 121 122 #include "../mii_layer/mii.h" 123 #include "../mii_layer/miivar.h" 124 125 #include <bus/pci/pcireg.h> 126 #include <bus/pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 130 #include "if_dcreg.h" 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 /* 136 * Various supported device vendors/types and their names. 137 */ 138 static const struct dc_type dc_devs[] = { 139 { DC_VENDORID_DEC, DC_DEVICEID_21143, 140 "Intel 21143 10/100BaseTX" }, 141 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 142 "Davicom DM9009 10/100BaseTX" }, 143 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 144 "Davicom DM9100 10/100BaseTX" }, 145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 146 "Davicom DM9102 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 148 "Davicom DM9102A 10/100BaseTX" }, 149 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 150 "ADMtek AL981 10/100BaseTX" }, 151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 152 "ADMtek AN985 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 154 "Netgear FA511 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 156 "ADMtek ADM9511 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 158 "ADMtek ADM9513 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 192 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 193 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 194 "3Com OfficeConnect 10/100B" }, 195 { 0, 0, NULL } 196 }; 197 198 static int dc_probe (device_t); 199 static int dc_attach (device_t); 200 static int dc_detach (device_t); 201 static int dc_suspend (device_t); 202 static int dc_resume (device_t); 203 static void dc_acpi (device_t); 204 static const struct dc_type *dc_devtype (device_t); 205 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 206 static int dc_encap (struct dc_softc *, struct mbuf *, 207 u_int32_t *); 208 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 209 static int dc_rx_resync (struct dc_softc *); 210 static void dc_rxeof (struct dc_softc *); 211 static void dc_txeof (struct dc_softc *); 212 static void dc_tick (void *); 213 static void dc_tx_underrun (struct dc_softc *); 214 static void dc_intr (void *); 215 static void dc_start (struct ifnet *); 216 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 217 struct ucred *); 218 #ifdef DEVICE_POLLING 219 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd, 220 int count); 221 #endif 222 static void dc_init (void *); 223 static void dc_stop (struct dc_softc *); 224 static void dc_watchdog (struct ifnet *); 225 static void dc_shutdown (device_t); 226 static int dc_ifmedia_upd (struct ifnet *); 227 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 228 229 static void dc_delay (struct dc_softc *); 230 static void dc_eeprom_idle (struct dc_softc *); 231 static void dc_eeprom_putbyte (struct dc_softc *, int); 232 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 233 static void dc_eeprom_getword_pnic 234 (struct dc_softc *, int, u_int16_t *); 235 static void dc_eeprom_getword_xircom 236 (struct dc_softc *, int, u_int16_t *); 237 static void dc_eeprom_width (struct dc_softc *); 238 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 239 int, int); 240 241 static void dc_mii_writebit (struct dc_softc *, int); 242 static int dc_mii_readbit (struct dc_softc *); 243 static void dc_mii_sync (struct dc_softc *); 244 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 245 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 246 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 247 static int dc_miibus_readreg (device_t, int, int); 248 static int dc_miibus_writereg (device_t, int, int, int); 249 static void dc_miibus_statchg (device_t); 250 static void dc_miibus_mediainit (device_t); 251 252 static u_int32_t dc_crc_mask (struct dc_softc *); 253 static void dc_setcfg (struct dc_softc *, int); 254 static void dc_setfilt_21143 (struct dc_softc *); 255 static void dc_setfilt_asix (struct dc_softc *); 256 static void dc_setfilt_admtek (struct dc_softc *); 257 static void dc_setfilt_xircom (struct dc_softc *); 258 259 static void dc_setfilt (struct dc_softc *); 260 261 static void dc_reset (struct dc_softc *); 262 static int dc_list_rx_init (struct dc_softc *); 263 static int dc_list_tx_init (struct dc_softc *); 264 265 static void dc_read_srom (struct dc_softc *, int); 266 static void dc_parse_21143_srom (struct dc_softc *); 267 static void dc_decode_leaf_sia (struct dc_softc *, 268 struct dc_eblock_sia *); 269 static void dc_decode_leaf_mii (struct dc_softc *, 270 struct dc_eblock_mii *); 271 static void dc_decode_leaf_sym (struct dc_softc *, 272 struct dc_eblock_sym *); 273 static void dc_apply_fixup (struct dc_softc *, int); 274 static uint32_t dc_mchash_xircom(struct dc_softc *, const uint8_t *); 275 276 #ifdef DC_USEIOSPACE 277 #define DC_RES SYS_RES_IOPORT 278 #define DC_RID DC_PCI_CFBIO 279 #else 280 #define DC_RES SYS_RES_MEMORY 281 #define DC_RID DC_PCI_CFBMA 282 #endif 283 284 static device_method_t dc_methods[] = { 285 /* Device interface */ 286 DEVMETHOD(device_probe, dc_probe), 287 DEVMETHOD(device_attach, dc_attach), 288 DEVMETHOD(device_detach, dc_detach), 289 DEVMETHOD(device_suspend, dc_suspend), 290 DEVMETHOD(device_resume, dc_resume), 291 DEVMETHOD(device_shutdown, dc_shutdown), 292 293 /* bus interface */ 294 DEVMETHOD(bus_print_child, bus_generic_print_child), 295 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 296 297 /* MII interface */ 298 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 299 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 300 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 301 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 302 303 { 0, 0 } 304 }; 305 306 static driver_t dc_driver = { 307 "dc", 308 dc_methods, 309 sizeof(struct dc_softc) 310 }; 311 312 static devclass_t dc_devclass; 313 314 #ifdef __i386__ 315 static int dc_quick=1; 316 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 317 &dc_quick,0,"do not mdevget in dc driver"); 318 #endif 319 320 DECLARE_DUMMY_MODULE(if_dc); 321 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 322 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 323 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 324 325 #define DC_SETBIT(sc, reg, x) \ 326 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 327 328 #define DC_CLRBIT(sc, reg, x) \ 329 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 330 331 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 332 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 333 334 static void 335 dc_delay(struct dc_softc *sc) 336 { 337 int idx; 338 339 for (idx = (300 / 33) + 1; idx > 0; idx--) 340 CSR_READ_4(sc, DC_BUSCTL); 341 } 342 343 static void 344 dc_eeprom_width(struct dc_softc *sc) 345 { 346 int i; 347 348 /* Force EEPROM to idle state. */ 349 dc_eeprom_idle(sc); 350 351 /* Enter EEPROM access mode. */ 352 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 353 dc_delay(sc); 354 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 355 dc_delay(sc); 356 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 357 dc_delay(sc); 358 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 359 dc_delay(sc); 360 361 for (i = 3; i--;) { 362 if (6 & (1 << i)) 363 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 364 else 365 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 366 dc_delay(sc); 367 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 368 dc_delay(sc); 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 } 372 373 for (i = 1; i <= 12; i++) { 374 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 375 dc_delay(sc); 376 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 378 dc_delay(sc); 379 break; 380 } 381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 382 dc_delay(sc); 383 } 384 385 /* Turn off EEPROM access mode. */ 386 dc_eeprom_idle(sc); 387 388 if (i < 4 || i > 12) 389 sc->dc_romwidth = 6; 390 else 391 sc->dc_romwidth = i; 392 393 /* Enter EEPROM access mode. */ 394 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 395 dc_delay(sc); 396 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 397 dc_delay(sc); 398 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 399 dc_delay(sc); 400 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 401 dc_delay(sc); 402 403 /* Turn off EEPROM access mode. */ 404 dc_eeprom_idle(sc); 405 } 406 407 static void 408 dc_eeprom_idle(struct dc_softc *sc) 409 { 410 int i; 411 412 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 415 dc_delay(sc); 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 419 dc_delay(sc); 420 421 for (i = 0; i < 25; i++) { 422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 423 dc_delay(sc); 424 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 425 dc_delay(sc); 426 } 427 428 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 429 dc_delay(sc); 430 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 431 dc_delay(sc); 432 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 433 434 return; 435 } 436 437 /* 438 * Send a read command and address to the EEPROM, check for ACK. 439 */ 440 static void 441 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 442 { 443 int d, i; 444 445 d = DC_EECMD_READ >> 6; 446 for (i = 3; i--; ) { 447 if (d & (1 << i)) 448 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 449 else 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 451 dc_delay(sc); 452 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 453 dc_delay(sc); 454 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 455 dc_delay(sc); 456 } 457 458 /* 459 * Feed in each bit and strobe the clock. 460 */ 461 for (i = sc->dc_romwidth; i--;) { 462 if (addr & (1 << i)) { 463 SIO_SET(DC_SIO_EE_DATAIN); 464 } else { 465 SIO_CLR(DC_SIO_EE_DATAIN); 466 } 467 dc_delay(sc); 468 SIO_SET(DC_SIO_EE_CLK); 469 dc_delay(sc); 470 SIO_CLR(DC_SIO_EE_CLK); 471 dc_delay(sc); 472 } 473 474 return; 475 } 476 477 /* 478 * Read a word of data stored in the EEPROM at address 'addr.' 479 * The PNIC 82c168/82c169 has its own non-standard way to read 480 * the EEPROM. 481 */ 482 static void 483 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 484 { 485 int i; 486 u_int32_t r; 487 488 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 489 490 for (i = 0; i < DC_TIMEOUT; i++) { 491 DELAY(1); 492 r = CSR_READ_4(sc, DC_SIO); 493 if (!(r & DC_PN_SIOCTL_BUSY)) { 494 *dest = (u_int16_t)(r & 0xFFFF); 495 return; 496 } 497 } 498 499 return; 500 } 501 502 /* 503 * Read a word of data stored in the EEPROM at address 'addr.' 504 * The Xircom X3201 has its own non-standard way to read 505 * the EEPROM, too. 506 */ 507 static void 508 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 509 { 510 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 511 512 addr *= 2; 513 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 514 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 515 addr += 1; 516 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 517 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 518 519 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 520 } 521 522 /* 523 * Read a word of data stored in the EEPROM at address 'addr.' 524 */ 525 static void 526 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 527 { 528 int i; 529 u_int16_t word = 0; 530 531 /* Force EEPROM to idle state. */ 532 dc_eeprom_idle(sc); 533 534 /* Enter EEPROM access mode. */ 535 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 536 dc_delay(sc); 537 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 538 dc_delay(sc); 539 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 540 dc_delay(sc); 541 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 542 dc_delay(sc); 543 544 /* 545 * Send address of word we want to read. 546 */ 547 dc_eeprom_putbyte(sc, addr); 548 549 /* 550 * Start reading bits from EEPROM. 551 */ 552 for (i = 0x8000; i; i >>= 1) { 553 SIO_SET(DC_SIO_EE_CLK); 554 dc_delay(sc); 555 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 556 word |= i; 557 dc_delay(sc); 558 SIO_CLR(DC_SIO_EE_CLK); 559 dc_delay(sc); 560 } 561 562 /* Turn off EEPROM access mode. */ 563 dc_eeprom_idle(sc); 564 565 *dest = word; 566 567 return; 568 } 569 570 /* 571 * Read a sequence of words from the EEPROM. 572 */ 573 static void 574 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 575 { 576 int i; 577 u_int16_t word = 0, *ptr; 578 579 for (i = 0; i < cnt; i++) { 580 if (DC_IS_PNIC(sc)) 581 dc_eeprom_getword_pnic(sc, off + i, &word); 582 else if (DC_IS_XIRCOM(sc)) 583 dc_eeprom_getword_xircom(sc, off + i, &word); 584 else 585 dc_eeprom_getword(sc, off + i, &word); 586 ptr = (u_int16_t *)(dest + (i * 2)); 587 if (swap) 588 *ptr = ntohs(word); 589 else 590 *ptr = word; 591 } 592 593 return; 594 } 595 596 /* 597 * The following two routines are taken from the Macronix 98713 598 * Application Notes pp.19-21. 599 */ 600 /* 601 * Write a bit to the MII bus. 602 */ 603 static void 604 dc_mii_writebit(struct dc_softc *sc, int bit) 605 { 606 if (bit) 607 CSR_WRITE_4(sc, DC_SIO, 608 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 609 else 610 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 611 612 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 613 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 614 615 return; 616 } 617 618 /* 619 * Read a bit from the MII bus. 620 */ 621 static int 622 dc_mii_readbit(struct dc_softc *sc) 623 { 624 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 625 CSR_READ_4(sc, DC_SIO); 626 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 627 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 628 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 629 return(1); 630 631 return(0); 632 } 633 634 /* 635 * Sync the PHYs by setting data bit and strobing the clock 32 times. 636 */ 637 static void 638 dc_mii_sync(struct dc_softc *sc) 639 { 640 int i; 641 642 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 643 644 for (i = 0; i < 32; i++) 645 dc_mii_writebit(sc, 1); 646 647 return; 648 } 649 650 /* 651 * Clock a series of bits through the MII. 652 */ 653 static void 654 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 655 { 656 int i; 657 658 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 659 dc_mii_writebit(sc, bits & i); 660 } 661 662 /* 663 * Read an PHY register through the MII. 664 */ 665 static int 666 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 667 { 668 int ack, i; 669 670 /* 671 * Set up frame for RX. 672 */ 673 frame->mii_stdelim = DC_MII_STARTDELIM; 674 frame->mii_opcode = DC_MII_READOP; 675 frame->mii_turnaround = 0; 676 frame->mii_data = 0; 677 678 /* 679 * Sync the PHYs. 680 */ 681 dc_mii_sync(sc); 682 683 /* 684 * Send command/address info. 685 */ 686 dc_mii_send(sc, frame->mii_stdelim, 2); 687 dc_mii_send(sc, frame->mii_opcode, 2); 688 dc_mii_send(sc, frame->mii_phyaddr, 5); 689 dc_mii_send(sc, frame->mii_regaddr, 5); 690 691 #ifdef notdef 692 /* Idle bit */ 693 dc_mii_writebit(sc, 1); 694 dc_mii_writebit(sc, 0); 695 #endif 696 697 /* Check for ack */ 698 ack = dc_mii_readbit(sc); 699 700 /* 701 * Now try reading data bits. If the ack failed, we still 702 * need to clock through 16 cycles to keep the PHY(s) in sync. 703 */ 704 if (ack) { 705 for(i = 0; i < 16; i++) { 706 dc_mii_readbit(sc); 707 } 708 goto fail; 709 } 710 711 for (i = 0x8000; i; i >>= 1) { 712 if (!ack) { 713 if (dc_mii_readbit(sc)) 714 frame->mii_data |= i; 715 } 716 } 717 718 fail: 719 720 dc_mii_writebit(sc, 0); 721 dc_mii_writebit(sc, 0); 722 723 if (ack) 724 return(1); 725 return(0); 726 } 727 728 /* 729 * Write to a PHY register through the MII. 730 */ 731 static int 732 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 733 { 734 /* 735 * Set up frame for TX. 736 */ 737 738 frame->mii_stdelim = DC_MII_STARTDELIM; 739 frame->mii_opcode = DC_MII_WRITEOP; 740 frame->mii_turnaround = DC_MII_TURNAROUND; 741 742 /* 743 * Sync the PHYs. 744 */ 745 dc_mii_sync(sc); 746 747 dc_mii_send(sc, frame->mii_stdelim, 2); 748 dc_mii_send(sc, frame->mii_opcode, 2); 749 dc_mii_send(sc, frame->mii_phyaddr, 5); 750 dc_mii_send(sc, frame->mii_regaddr, 5); 751 dc_mii_send(sc, frame->mii_turnaround, 2); 752 dc_mii_send(sc, frame->mii_data, 16); 753 754 /* Idle bit. */ 755 dc_mii_writebit(sc, 0); 756 dc_mii_writebit(sc, 0); 757 758 return(0); 759 } 760 761 static int 762 dc_miibus_readreg(device_t dev, int phy, int reg) 763 { 764 struct dc_mii_frame frame; 765 struct dc_softc *sc; 766 int i, rval, phy_reg = 0; 767 768 sc = device_get_softc(dev); 769 bzero((char *)&frame, sizeof(frame)); 770 771 /* 772 * Note: both the AL981 and AN985 have internal PHYs, 773 * however the AL981 provides direct access to the PHY 774 * registers while the AN985 uses a serial MII interface. 775 * The AN985's MII interface is also buggy in that you 776 * can read from any MII address (0 to 31), but only address 1 777 * behaves normally. To deal with both cases, we pretend 778 * that the PHY is at MII address 1. 779 */ 780 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 781 return(0); 782 783 /* 784 * Note: the ukphy probes of the RS7112 report a PHY at 785 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 786 * so we only respond to correct one. 787 */ 788 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 789 return(0); 790 791 if (sc->dc_pmode != DC_PMODE_MII) { 792 if (phy == (MII_NPHY - 1)) { 793 switch(reg) { 794 case MII_BMSR: 795 /* 796 * Fake something to make the probe 797 * code think there's a PHY here. 798 */ 799 return(BMSR_MEDIAMASK); 800 break; 801 case MII_PHYIDR1: 802 if (DC_IS_PNIC(sc)) 803 return(DC_VENDORID_LO); 804 return(DC_VENDORID_DEC); 805 break; 806 case MII_PHYIDR2: 807 if (DC_IS_PNIC(sc)) 808 return(DC_DEVICEID_82C168); 809 return(DC_DEVICEID_21143); 810 break; 811 default: 812 return(0); 813 break; 814 } 815 } else 816 return(0); 817 } 818 819 if (DC_IS_PNIC(sc)) { 820 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 821 (phy << 23) | (reg << 18)); 822 for (i = 0; i < DC_TIMEOUT; i++) { 823 DELAY(1); 824 rval = CSR_READ_4(sc, DC_PN_MII); 825 if (!(rval & DC_PN_MII_BUSY)) { 826 rval &= 0xFFFF; 827 return(rval == 0xFFFF ? 0 : rval); 828 } 829 } 830 return(0); 831 } 832 833 if (DC_IS_COMET(sc)) { 834 switch(reg) { 835 case MII_BMCR: 836 phy_reg = DC_AL_BMCR; 837 break; 838 case MII_BMSR: 839 phy_reg = DC_AL_BMSR; 840 break; 841 case MII_PHYIDR1: 842 phy_reg = DC_AL_VENID; 843 break; 844 case MII_PHYIDR2: 845 phy_reg = DC_AL_DEVID; 846 break; 847 case MII_ANAR: 848 phy_reg = DC_AL_ANAR; 849 break; 850 case MII_ANLPAR: 851 phy_reg = DC_AL_LPAR; 852 break; 853 case MII_ANER: 854 phy_reg = DC_AL_ANER; 855 break; 856 default: 857 if_printf(&sc->arpcom.ac_if, 858 "phy_read: bad phy register %x\n", reg); 859 return(0); 860 break; 861 } 862 863 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 864 865 if (rval == 0xFFFF) 866 return(0); 867 return(rval); 868 } 869 870 frame.mii_phyaddr = phy; 871 frame.mii_regaddr = reg; 872 if (sc->dc_type == DC_TYPE_98713) { 873 phy_reg = CSR_READ_4(sc, DC_NETCFG); 874 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 875 } 876 dc_mii_readreg(sc, &frame); 877 if (sc->dc_type == DC_TYPE_98713) 878 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 879 880 return(frame.mii_data); 881 } 882 883 static int 884 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 885 { 886 struct dc_softc *sc; 887 struct dc_mii_frame frame; 888 int i, phy_reg = 0; 889 890 sc = device_get_softc(dev); 891 bzero((char *)&frame, sizeof(frame)); 892 893 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 894 return(0); 895 896 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 897 return(0); 898 899 if (DC_IS_PNIC(sc)) { 900 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 901 (phy << 23) | (reg << 10) | data); 902 for (i = 0; i < DC_TIMEOUT; i++) { 903 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 904 break; 905 } 906 return(0); 907 } 908 909 if (DC_IS_COMET(sc)) { 910 switch(reg) { 911 case MII_BMCR: 912 phy_reg = DC_AL_BMCR; 913 break; 914 case MII_BMSR: 915 phy_reg = DC_AL_BMSR; 916 break; 917 case MII_PHYIDR1: 918 phy_reg = DC_AL_VENID; 919 break; 920 case MII_PHYIDR2: 921 phy_reg = DC_AL_DEVID; 922 break; 923 case MII_ANAR: 924 phy_reg = DC_AL_ANAR; 925 break; 926 case MII_ANLPAR: 927 phy_reg = DC_AL_LPAR; 928 break; 929 case MII_ANER: 930 phy_reg = DC_AL_ANER; 931 break; 932 default: 933 if_printf(&sc->arpcom.ac_if, 934 "phy_write: bad phy register %x\n", reg); 935 return(0); 936 break; 937 } 938 939 CSR_WRITE_4(sc, phy_reg, data); 940 return(0); 941 } 942 943 frame.mii_phyaddr = phy; 944 frame.mii_regaddr = reg; 945 frame.mii_data = data; 946 947 if (sc->dc_type == DC_TYPE_98713) { 948 phy_reg = CSR_READ_4(sc, DC_NETCFG); 949 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 950 } 951 dc_mii_writereg(sc, &frame); 952 if (sc->dc_type == DC_TYPE_98713) 953 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 954 955 return(0); 956 } 957 958 static void 959 dc_miibus_statchg(device_t dev) 960 { 961 struct dc_softc *sc; 962 struct mii_data *mii; 963 struct ifmedia *ifm; 964 965 sc = device_get_softc(dev); 966 if (DC_IS_ADMTEK(sc)) 967 return; 968 969 mii = device_get_softc(sc->dc_miibus); 970 ifm = &mii->mii_media; 971 if (DC_IS_DAVICOM(sc) && 972 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 973 dc_setcfg(sc, ifm->ifm_media); 974 sc->dc_if_media = ifm->ifm_media; 975 } else { 976 dc_setcfg(sc, mii->mii_media_active); 977 sc->dc_if_media = mii->mii_media_active; 978 } 979 980 return; 981 } 982 983 /* 984 * Special support for DM9102A cards with HomePNA PHYs. Note: 985 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 986 * to be impossible to talk to the management interface of the DM9801 987 * PHY (its MDIO pin is not connected to anything). Consequently, 988 * the driver has to just 'know' about the additional mode and deal 989 * with it itself. *sigh* 990 */ 991 static void 992 dc_miibus_mediainit(device_t dev) 993 { 994 struct dc_softc *sc; 995 struct mii_data *mii; 996 struct ifmedia *ifm; 997 int rev; 998 999 rev = pci_get_revid(dev); 1000 1001 sc = device_get_softc(dev); 1002 mii = device_get_softc(sc->dc_miibus); 1003 ifm = &mii->mii_media; 1004 1005 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1006 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1007 1008 return; 1009 } 1010 1011 #define DC_BITS_512 9 1012 #define DC_BITS_128 7 1013 #define DC_BITS_64 6 1014 1015 static u_int32_t 1016 dc_crc_mask(struct dc_softc *sc) 1017 { 1018 /* 1019 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1020 * chips is only 128 bits wide. 1021 */ 1022 if (sc->dc_flags & DC_128BIT_HASH) 1023 return ((1 << DC_BITS_128) - 1); 1024 1025 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1026 if (sc->dc_flags & DC_64BIT_HASH) 1027 return ((1 << DC_BITS_64) - 1); 1028 1029 return ((1 << DC_BITS_512) - 1); 1030 } 1031 1032 /* 1033 * 21143-style RX filter setup routine. Filter programming is done by 1034 * downloading a special setup frame into the TX engine. 21143, Macronix, 1035 * PNIC, PNIC II and Davicom chips are programmed this way. 1036 * 1037 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1038 * address (our node address) and a 512-bit hash filter for multicast 1039 * frames. We also sneak the broadcast address into the hash filter since 1040 * we need that too. 1041 */ 1042 void 1043 dc_setfilt_21143(struct dc_softc *sc) 1044 { 1045 struct dc_desc *sframe; 1046 u_int32_t h, crc_mask, *sp; 1047 struct ifmultiaddr *ifma; 1048 struct ifnet *ifp; 1049 int i; 1050 1051 ifp = &sc->arpcom.ac_if; 1052 1053 i = sc->dc_cdata.dc_tx_prod; 1054 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1055 sc->dc_cdata.dc_tx_cnt++; 1056 sframe = &sc->dc_ldata->dc_tx_list[i]; 1057 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1058 bzero((char *)sp, DC_SFRAME_LEN); 1059 1060 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1061 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1062 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1063 1064 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1065 1066 /* If we want promiscuous mode, set the allframes bit. */ 1067 if (ifp->if_flags & IFF_PROMISC) 1068 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1069 else 1070 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1071 1072 if (ifp->if_flags & IFF_ALLMULTI) 1073 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1074 else 1075 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1076 1077 crc_mask = dc_crc_mask(sc); 1078 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1079 if (ifma->ifma_addr->sa_family != AF_LINK) 1080 continue; 1081 h = ether_crc32_le( 1082 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1083 ETHER_ADDR_LEN) & crc_mask; 1084 sp[h >> 4] |= 1 << (h & 0xF); 1085 } 1086 1087 if (ifp->if_flags & IFF_BROADCAST) { 1088 h = ether_crc32_le(ifp->if_broadcastaddr, 1089 ETHER_ADDR_LEN) & crc_mask; 1090 sp[h >> 4] |= 1 << (h & 0xF); 1091 } 1092 1093 /* Set our MAC address */ 1094 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1095 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1096 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1097 1098 sframe->dc_status = DC_TXSTAT_OWN; 1099 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1100 1101 /* 1102 * The PNIC takes an exceedingly long time to process its 1103 * setup frame; wait 10ms after posting the setup frame 1104 * before proceeding, just so it has time to swallow its 1105 * medicine. 1106 */ 1107 DELAY(10000); 1108 1109 ifp->if_timer = 5; 1110 1111 return; 1112 } 1113 1114 void 1115 dc_setfilt_admtek(struct dc_softc *sc) 1116 { 1117 struct ifnet *ifp; 1118 int h = 0; 1119 u_int32_t crc_mask; 1120 u_int32_t hashes[2] = { 0, 0 }; 1121 struct ifmultiaddr *ifma; 1122 1123 ifp = &sc->arpcom.ac_if; 1124 1125 /* Init our MAC address */ 1126 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1127 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1128 1129 /* If we want promiscuous mode, set the allframes bit. */ 1130 if (ifp->if_flags & IFF_PROMISC) 1131 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1132 else 1133 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1134 1135 if (ifp->if_flags & IFF_ALLMULTI) 1136 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1137 else 1138 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1139 1140 /* first, zot all the existing hash bits */ 1141 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1142 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1143 1144 /* 1145 * If we're already in promisc or allmulti mode, we 1146 * don't have to bother programming the multicast filter. 1147 */ 1148 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1149 return; 1150 1151 /* now program new ones */ 1152 if (DC_IS_CENTAUR(sc)) 1153 crc_mask = dc_crc_mask(sc); 1154 else 1155 crc_mask = 0x3f; 1156 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1157 if (ifma->ifma_addr->sa_family != AF_LINK) 1158 continue; 1159 if (DC_IS_CENTAUR(sc)) { 1160 h = ether_crc32_le( 1161 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1162 ETHER_ADDR_LEN) & crc_mask; 1163 } else { 1164 h = ether_crc32_be( 1165 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1166 ETHER_ADDR_LEN); 1167 h = (h >> 26) & crc_mask; 1168 } 1169 if (h < 32) 1170 hashes[0] |= (1 << h); 1171 else 1172 hashes[1] |= (1 << (h - 32)); 1173 } 1174 1175 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1176 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1177 1178 return; 1179 } 1180 1181 void 1182 dc_setfilt_asix(struct dc_softc *sc) 1183 { 1184 struct ifnet *ifp; 1185 int h = 0; 1186 u_int32_t hashes[2] = { 0, 0 }; 1187 struct ifmultiaddr *ifma; 1188 1189 ifp = &sc->arpcom.ac_if; 1190 1191 /* Init our MAC address */ 1192 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1193 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1194 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1195 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1196 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1197 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1198 1199 /* If we want promiscuous mode, set the allframes bit. */ 1200 if (ifp->if_flags & IFF_PROMISC) 1201 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1202 else 1203 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1204 1205 if (ifp->if_flags & IFF_ALLMULTI) 1206 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1207 else 1208 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1209 1210 /* 1211 * The ASIX chip has a special bit to enable reception 1212 * of broadcast frames. 1213 */ 1214 if (ifp->if_flags & IFF_BROADCAST) 1215 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1216 else 1217 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1218 1219 /* first, zot all the existing hash bits */ 1220 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1221 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1224 1225 /* 1226 * If we're already in promisc or allmulti mode, we 1227 * don't have to bother programming the multicast filter. 1228 */ 1229 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1230 return; 1231 1232 /* now program new ones */ 1233 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1234 if (ifma->ifma_addr->sa_family != AF_LINK) 1235 continue; 1236 h = ether_crc32_be( 1237 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1238 ETHER_ADDR_LEN); 1239 h = (h >> 26) & 0x3f; 1240 if (h < 32) 1241 hashes[0] |= (1 << h); 1242 else 1243 hashes[1] |= (1 << (h - 32)); 1244 } 1245 1246 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1247 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1250 1251 return; 1252 } 1253 1254 void 1255 dc_setfilt_xircom(struct dc_softc *sc) 1256 { 1257 struct dc_desc *sframe; 1258 u_int32_t h, *sp; 1259 struct ifmultiaddr *ifma; 1260 struct ifnet *ifp; 1261 int i; 1262 1263 ifp = &sc->arpcom.ac_if; 1264 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1265 1266 i = sc->dc_cdata.dc_tx_prod; 1267 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1268 sc->dc_cdata.dc_tx_cnt++; 1269 sframe = &sc->dc_ldata->dc_tx_list[i]; 1270 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1271 bzero(sp, DC_SFRAME_LEN); 1272 1273 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1274 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1275 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1276 1277 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1278 1279 /* If we want promiscuous mode, set the allframes bit. */ 1280 if (ifp->if_flags & IFF_PROMISC) 1281 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1282 else 1283 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1284 1285 if (ifp->if_flags & IFF_ALLMULTI) 1286 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1287 else 1288 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1289 1290 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1291 if (ifma->ifma_addr->sa_family != AF_LINK) 1292 continue; 1293 h = dc_mchash_xircom(sc, 1294 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1295 sp[h >> 4] |= 1 << (h & 0xF); 1296 } 1297 1298 if (ifp->if_flags & IFF_BROADCAST) { 1299 h = dc_mchash_xircom(sc, (caddr_t)ðerbroadcastaddr); 1300 sp[h >> 4] |= 1 << (h & 0xF); 1301 } 1302 1303 /* Set our MAC address */ 1304 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1305 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1306 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1307 1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1309 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1310 ifp->if_flags |= IFF_RUNNING; 1311 sframe->dc_status = DC_TXSTAT_OWN; 1312 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1313 1314 /* 1315 * wait some time... 1316 */ 1317 DELAY(1000); 1318 1319 ifp->if_timer = 5; 1320 } 1321 1322 static void 1323 dc_setfilt(struct dc_softc *sc) 1324 { 1325 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1326 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1327 dc_setfilt_21143(sc); 1328 1329 if (DC_IS_ASIX(sc)) 1330 dc_setfilt_asix(sc); 1331 1332 if (DC_IS_ADMTEK(sc)) 1333 dc_setfilt_admtek(sc); 1334 1335 if (DC_IS_XIRCOM(sc)) 1336 dc_setfilt_xircom(sc); 1337 } 1338 1339 /* 1340 * In order to fiddle with the 1341 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1342 * first have to put the transmit and/or receive logic in the idle state. 1343 */ 1344 static void 1345 dc_setcfg(struct dc_softc *sc, int media) 1346 { 1347 int i, restart = 0; 1348 u_int32_t isr; 1349 1350 if (IFM_SUBTYPE(media) == IFM_NONE) 1351 return; 1352 1353 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1354 restart = 1; 1355 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1356 1357 for (i = 0; i < DC_TIMEOUT; i++) { 1358 isr = CSR_READ_4(sc, DC_ISR); 1359 if ((isr & DC_ISR_TX_IDLE) && 1360 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1361 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1362 break; 1363 DELAY(10); 1364 } 1365 1366 if (i == DC_TIMEOUT) { 1367 if_printf(&sc->arpcom.ac_if, 1368 "failed to force tx and rx to idle state\n"); 1369 } 1370 } 1371 1372 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1373 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1374 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1375 if (sc->dc_pmode == DC_PMODE_MII) { 1376 int watchdogreg; 1377 1378 if (DC_IS_INTEL(sc)) { 1379 /* there's a write enable bit here that reads as 1 */ 1380 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1381 watchdogreg &= ~DC_WDOG_CTLWREN; 1382 watchdogreg |= DC_WDOG_JABBERDIS; 1383 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1384 } else { 1385 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1386 } 1387 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1388 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1389 if (sc->dc_type == DC_TYPE_98713) 1390 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1391 DC_NETCFG_SCRAMBLER)); 1392 if (!DC_IS_DAVICOM(sc)) 1393 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1394 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1395 if (DC_IS_INTEL(sc)) 1396 dc_apply_fixup(sc, IFM_AUTO); 1397 } else { 1398 if (DC_IS_PNIC(sc)) { 1399 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1400 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1401 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1402 } 1403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1405 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1406 if (DC_IS_INTEL(sc)) 1407 dc_apply_fixup(sc, 1408 (media & IFM_GMASK) == IFM_FDX ? 1409 IFM_100_TX|IFM_FDX : IFM_100_TX); 1410 } 1411 } 1412 1413 if (IFM_SUBTYPE(media) == IFM_10_T) { 1414 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1415 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1416 if (sc->dc_pmode == DC_PMODE_MII) { 1417 int watchdogreg; 1418 1419 /* there's a write enable bit here that reads as 1 */ 1420 if (DC_IS_INTEL(sc)) { 1421 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1422 watchdogreg &= ~DC_WDOG_CTLWREN; 1423 watchdogreg |= DC_WDOG_JABBERDIS; 1424 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1425 } else { 1426 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1427 } 1428 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1429 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1430 if (sc->dc_type == DC_TYPE_98713) 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1432 if (!DC_IS_DAVICOM(sc)) 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1434 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1435 if (DC_IS_INTEL(sc)) 1436 dc_apply_fixup(sc, IFM_AUTO); 1437 } else { 1438 if (DC_IS_PNIC(sc)) { 1439 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1440 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1441 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1442 } 1443 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1445 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1446 if (DC_IS_INTEL(sc)) { 1447 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1448 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1449 if ((media & IFM_GMASK) == IFM_FDX) 1450 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1451 else 1452 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1453 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1454 DC_CLRBIT(sc, DC_10BTCTRL, 1455 DC_TCTL_AUTONEGENBL); 1456 dc_apply_fixup(sc, 1457 (media & IFM_GMASK) == IFM_FDX ? 1458 IFM_10_T|IFM_FDX : IFM_10_T); 1459 DELAY(20000); 1460 } 1461 } 1462 } 1463 1464 /* 1465 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1466 * PHY and we want HomePNA mode, set the portsel bit to turn 1467 * on the external MII port. 1468 */ 1469 if (DC_IS_DAVICOM(sc)) { 1470 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1471 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1472 sc->dc_link = 1; 1473 } else { 1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1475 } 1476 } 1477 1478 if ((media & IFM_GMASK) == IFM_FDX) { 1479 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1480 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1481 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1482 } else { 1483 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1484 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1485 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1486 } 1487 1488 if (restart) 1489 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1490 1491 return; 1492 } 1493 1494 static void 1495 dc_reset(struct dc_softc *sc) 1496 { 1497 int i; 1498 1499 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1500 1501 for (i = 0; i < DC_TIMEOUT; i++) { 1502 DELAY(10); 1503 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1504 break; 1505 } 1506 1507 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) || 1508 DC_IS_CONEXANT(sc)) { 1509 DELAY(10000); 1510 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1511 i = 0; 1512 } 1513 1514 if (i == DC_TIMEOUT) 1515 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 1516 1517 /* Wait a little while for the chip to get its brains in order. */ 1518 DELAY(1000); 1519 1520 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1521 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1522 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1523 1524 /* 1525 * Bring the SIA out of reset. In some cases, it looks 1526 * like failing to unreset the SIA soon enough gets it 1527 * into a state where it will never come out of reset 1528 * until we reset the whole chip again. 1529 */ 1530 if (DC_IS_INTEL(sc)) { 1531 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1532 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1533 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1534 } 1535 1536 return; 1537 } 1538 1539 static const struct dc_type * 1540 dc_devtype(device_t dev) 1541 { 1542 const struct dc_type *t; 1543 u_int32_t rev; 1544 1545 t = dc_devs; 1546 1547 while(t->dc_name != NULL) { 1548 if ((pci_get_vendor(dev) == t->dc_vid) && 1549 (pci_get_device(dev) == t->dc_did)) { 1550 /* Check the PCI revision */ 1551 rev = pci_get_revid(dev); 1552 if (t->dc_did == DC_DEVICEID_98713 && 1553 rev >= DC_REVISION_98713A) 1554 t++; 1555 if (t->dc_did == DC_DEVICEID_98713_CP && 1556 rev >= DC_REVISION_98713A) 1557 t++; 1558 if (t->dc_did == DC_DEVICEID_987x5 && 1559 rev >= DC_REVISION_98715AEC_C) 1560 t++; 1561 if (t->dc_did == DC_DEVICEID_987x5 && 1562 rev >= DC_REVISION_98725) 1563 t++; 1564 if (t->dc_did == DC_DEVICEID_AX88140A && 1565 rev >= DC_REVISION_88141) 1566 t++; 1567 if (t->dc_did == DC_DEVICEID_82C168 && 1568 rev >= DC_REVISION_82C169) 1569 t++; 1570 if (t->dc_did == DC_DEVICEID_DM9102 && 1571 rev >= DC_REVISION_DM9102A) 1572 t++; 1573 return(t); 1574 } 1575 t++; 1576 } 1577 1578 return(NULL); 1579 } 1580 1581 /* 1582 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1583 * IDs against our list and return a device name if we find a match. 1584 * We do a little bit of extra work to identify the exact type of 1585 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1586 * but different revision IDs. The same is true for 98715/98715A 1587 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1588 * cases, the exact chip revision affects driver behavior. 1589 */ 1590 static int 1591 dc_probe(device_t dev) 1592 { 1593 const struct dc_type *t; 1594 1595 t = dc_devtype(dev); 1596 if (t != NULL) { 1597 struct dc_softc *sc = device_get_softc(dev); 1598 1599 /* Need this info to decide on a chip type. */ 1600 sc->dc_info = t; 1601 device_set_desc(dev, t->dc_name); 1602 return(0); 1603 } 1604 1605 return(ENXIO); 1606 } 1607 1608 static void 1609 dc_acpi(device_t dev) 1610 { 1611 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1612 uint32_t iobase, membase, irq; 1613 struct dc_softc *sc; 1614 1615 /* Save important PCI config data. */ 1616 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1617 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1618 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1619 1620 sc = device_get_softc(dev); 1621 /* Reset the power state. */ 1622 if_printf(&sc->arpcom.ac_if, 1623 "chip is in D%d power mode " 1624 "-- setting to D0\n", pci_get_powerstate(dev)); 1625 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1626 1627 /* Restore PCI config data. */ 1628 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1629 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1630 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1631 } 1632 } 1633 1634 static void 1635 dc_apply_fixup(struct dc_softc *sc, int media) 1636 { 1637 struct dc_mediainfo *m; 1638 u_int8_t *p; 1639 int i; 1640 u_int32_t reg; 1641 1642 m = sc->dc_mi; 1643 1644 while (m != NULL) { 1645 if (m->dc_media == media) 1646 break; 1647 m = m->dc_next; 1648 } 1649 1650 if (m == NULL) 1651 return; 1652 1653 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1654 reg = (p[0] | (p[1] << 8)) << 16; 1655 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1656 } 1657 1658 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1659 reg = (p[0] | (p[1] << 8)) << 16; 1660 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1661 } 1662 1663 return; 1664 } 1665 1666 static void 1667 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1668 { 1669 struct dc_mediainfo *m; 1670 1671 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1672 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){ 1673 case DC_SIA_CODE_10BT: 1674 m->dc_media = IFM_10_T; 1675 break; 1676 1677 case DC_SIA_CODE_10BT_FDX: 1678 m->dc_media = IFM_10_T|IFM_FDX; 1679 break; 1680 1681 case DC_SIA_CODE_10B2: 1682 m->dc_media = IFM_10_2; 1683 break; 1684 1685 case DC_SIA_CODE_10B5: 1686 m->dc_media = IFM_10_5; 1687 break; 1688 } 1689 if (l->dc_sia_code & DC_SIA_CODE_EXT){ 1690 m->dc_gp_len = 2; 1691 m->dc_gp_ptr = 1692 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1693 } else { 1694 m->dc_gp_len = 2; 1695 m->dc_gp_ptr = 1696 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1697 } 1698 1699 m->dc_next = sc->dc_mi; 1700 sc->dc_mi = m; 1701 1702 sc->dc_pmode = DC_PMODE_SIA; 1703 1704 return; 1705 } 1706 1707 static void 1708 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1709 { 1710 struct dc_mediainfo *m; 1711 1712 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1713 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1714 m->dc_media = IFM_100_TX; 1715 1716 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1717 m->dc_media = IFM_100_TX|IFM_FDX; 1718 1719 m->dc_gp_len = 2; 1720 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1721 1722 m->dc_next = sc->dc_mi; 1723 sc->dc_mi = m; 1724 1725 sc->dc_pmode = DC_PMODE_SYM; 1726 1727 return; 1728 } 1729 1730 static void 1731 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1732 { 1733 u_int8_t *p; 1734 struct dc_mediainfo *m; 1735 1736 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1737 /* We abuse IFM_AUTO to represent MII. */ 1738 m->dc_media = IFM_AUTO; 1739 m->dc_gp_len = l->dc_gpr_len; 1740 1741 p = (u_int8_t *)l; 1742 p += sizeof(struct dc_eblock_mii); 1743 m->dc_gp_ptr = p; 1744 p += 2 * l->dc_gpr_len; 1745 m->dc_reset_len = *p; 1746 p++; 1747 m->dc_reset_ptr = p; 1748 1749 m->dc_next = sc->dc_mi; 1750 sc->dc_mi = m; 1751 1752 return; 1753 } 1754 1755 static void 1756 dc_read_srom(struct dc_softc *sc, int bits) 1757 { 1758 int size; 1759 1760 size = 2 << bits; 1761 sc->dc_srom = kmalloc(size, M_DEVBUF, M_INTWAIT); 1762 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1763 } 1764 1765 static void 1766 dc_parse_21143_srom(struct dc_softc *sc) 1767 { 1768 struct dc_leaf_hdr *lhdr; 1769 struct dc_eblock_hdr *hdr; 1770 int i, loff; 1771 char *ptr; 1772 int have_mii; 1773 1774 have_mii = 0; 1775 loff = sc->dc_srom[27]; 1776 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1777 1778 ptr = (char *)lhdr; 1779 ptr += sizeof(struct dc_leaf_hdr) - 1; 1780 /* 1781 * Look if we got a MII media block. 1782 */ 1783 for (i = 0; i < lhdr->dc_mcnt; i++) { 1784 hdr = (struct dc_eblock_hdr *)ptr; 1785 if (hdr->dc_type == DC_EBLOCK_MII) 1786 have_mii++; 1787 1788 ptr += (hdr->dc_len & 0x7F); 1789 ptr++; 1790 } 1791 1792 /* 1793 * Do the same thing again. Only use SIA and SYM media 1794 * blocks if no MII media block is available. 1795 */ 1796 ptr = (char *)lhdr; 1797 ptr += sizeof(struct dc_leaf_hdr) - 1; 1798 for (i = 0; i < lhdr->dc_mcnt; i++) { 1799 hdr = (struct dc_eblock_hdr *)ptr; 1800 switch(hdr->dc_type) { 1801 case DC_EBLOCK_MII: 1802 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1803 break; 1804 case DC_EBLOCK_SIA: 1805 if (! have_mii) 1806 dc_decode_leaf_sia(sc, 1807 (struct dc_eblock_sia *)hdr); 1808 break; 1809 case DC_EBLOCK_SYM: 1810 if (! have_mii) 1811 dc_decode_leaf_sym(sc, 1812 (struct dc_eblock_sym *)hdr); 1813 break; 1814 default: 1815 /* Don't care. Yet. */ 1816 break; 1817 } 1818 ptr += (hdr->dc_len & 0x7F); 1819 ptr++; 1820 } 1821 1822 return; 1823 } 1824 1825 /* 1826 * Attach the interface. Allocate softc structures, do ifmedia 1827 * setup and ethernet/BPF attach. 1828 */ 1829 static int 1830 dc_attach(device_t dev) 1831 { 1832 int tmp = 0; 1833 u_char eaddr[ETHER_ADDR_LEN]; 1834 u_int32_t command; 1835 struct dc_softc *sc; 1836 struct ifnet *ifp; 1837 u_int32_t revision; 1838 int error = 0, rid, mac_offset; 1839 uint8_t *mac; 1840 1841 sc = device_get_softc(dev); 1842 callout_init(&sc->dc_stat_timer); 1843 1844 ifp = &sc->arpcom.ac_if; 1845 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1846 1847 /* 1848 * Handle power management nonsense. 1849 */ 1850 dc_acpi(dev); 1851 1852 /* 1853 * Map control/status registers. 1854 */ 1855 pci_enable_busmaster(dev); 1856 1857 rid = DC_RID; 1858 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1859 1860 if (sc->dc_res == NULL) { 1861 device_printf(dev, "couldn't map ports/memory\n"); 1862 error = ENXIO; 1863 goto fail; 1864 } 1865 1866 sc->dc_btag = rman_get_bustag(sc->dc_res); 1867 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1868 1869 /* Allocate interrupt */ 1870 rid = 0; 1871 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1872 RF_SHAREABLE | RF_ACTIVE); 1873 1874 if (sc->dc_irq == NULL) { 1875 device_printf(dev, "couldn't map interrupt\n"); 1876 error = ENXIO; 1877 goto fail; 1878 } 1879 1880 revision = pci_get_revid(dev); 1881 1882 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1883 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1884 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1885 dc_eeprom_width(sc); 1886 1887 switch(sc->dc_info->dc_did) { 1888 case DC_DEVICEID_21143: 1889 sc->dc_type = DC_TYPE_21143; 1890 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1891 sc->dc_flags |= DC_REDUCED_MII_POLL; 1892 /* Save EEPROM contents so we can parse them later. */ 1893 dc_read_srom(sc, sc->dc_romwidth); 1894 break; 1895 case DC_DEVICEID_DM9009: 1896 case DC_DEVICEID_DM9100: 1897 case DC_DEVICEID_DM9102: 1898 sc->dc_type = DC_TYPE_DM9102; 1899 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1900 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1901 sc->dc_flags |= DC_TX_ALIGN; 1902 sc->dc_pmode = DC_PMODE_MII; 1903 /* Increase the latency timer value. */ 1904 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1905 command &= 0xFFFF00FF; 1906 command |= 0x00008000; 1907 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1908 break; 1909 case DC_DEVICEID_AL981: 1910 sc->dc_type = DC_TYPE_AL981; 1911 sc->dc_flags |= DC_TX_USE_TX_INTR; 1912 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1913 sc->dc_pmode = DC_PMODE_MII; 1914 dc_read_srom(sc, sc->dc_romwidth); 1915 break; 1916 case DC_DEVICEID_AN985: 1917 case DC_DEVICEID_ADM9511: 1918 case DC_DEVICEID_ADM9513: 1919 case DC_DEVICEID_FA511: 1920 case DC_DEVICEID_EN2242: 1921 case DC_DEVICEID_3CSOHOB: 1922 sc->dc_type = DC_TYPE_AN985; 1923 sc->dc_flags |= DC_64BIT_HASH; 1924 sc->dc_flags |= DC_TX_USE_TX_INTR; 1925 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1926 sc->dc_pmode = DC_PMODE_MII; 1927 break; 1928 case DC_DEVICEID_98713: 1929 case DC_DEVICEID_98713_CP: 1930 if (revision < DC_REVISION_98713A) { 1931 sc->dc_type = DC_TYPE_98713; 1932 } 1933 if (revision >= DC_REVISION_98713A) { 1934 sc->dc_type = DC_TYPE_98713A; 1935 sc->dc_flags |= DC_21143_NWAY; 1936 } 1937 sc->dc_flags |= DC_REDUCED_MII_POLL; 1938 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1939 break; 1940 case DC_DEVICEID_987x5: 1941 case DC_DEVICEID_EN1217: 1942 /* 1943 * Macronix MX98715AEC-C/D/E parts have only a 1944 * 128-bit hash table. We need to deal with these 1945 * in the same manner as the PNIC II so that we 1946 * get the right number of bits out of the 1947 * CRC routine. 1948 */ 1949 if (revision >= DC_REVISION_98715AEC_C && 1950 revision < DC_REVISION_98725) 1951 sc->dc_flags |= DC_128BIT_HASH; 1952 sc->dc_type = DC_TYPE_987x5; 1953 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1955 break; 1956 case DC_DEVICEID_98727: 1957 sc->dc_type = DC_TYPE_987x5; 1958 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1959 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1960 break; 1961 case DC_DEVICEID_82C115: 1962 sc->dc_type = DC_TYPE_PNICII; 1963 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1964 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1965 break; 1966 case DC_DEVICEID_82C168: 1967 sc->dc_type = DC_TYPE_PNIC; 1968 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1969 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1970 sc->dc_pnic_rx_buf = kmalloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1971 if (revision < DC_REVISION_82C169) 1972 sc->dc_pmode = DC_PMODE_SYM; 1973 break; 1974 case DC_DEVICEID_AX88140A: 1975 sc->dc_type = DC_TYPE_ASIX; 1976 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1977 sc->dc_flags |= DC_REDUCED_MII_POLL; 1978 sc->dc_pmode = DC_PMODE_MII; 1979 break; 1980 case DC_DEVICEID_RS7112: 1981 sc->dc_type = DC_TYPE_CONEXANT; 1982 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1983 sc->dc_flags |= DC_REDUCED_MII_POLL; 1984 sc->dc_pmode = DC_PMODE_MII; 1985 dc_read_srom(sc, sc->dc_romwidth); 1986 break; 1987 case DC_DEVICEID_X3201: 1988 sc->dc_type = DC_TYPE_XIRCOM; 1989 sc->dc_flags |= (DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1990 DC_TX_ALIGN); 1991 /* 1992 * We don't actually need to coalesce, but we're doing 1993 * it to obtain a double word aligned buffer. 1994 * The DC_TX_COALESCE flag is required. 1995 */ 1996 sc->dc_pmode = DC_PMODE_MII; 1997 break; 1998 default: 1999 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2000 break; 2001 } 2002 2003 /* Save the cache line size. */ 2004 if (DC_IS_DAVICOM(sc)) 2005 sc->dc_cachesize = 0; 2006 else 2007 sc->dc_cachesize = pci_read_config(dev, 2008 DC_PCI_CFLT, 4) & 0xFF; 2009 2010 /* Reset the adapter. */ 2011 dc_reset(sc); 2012 2013 /* Take 21143 out of snooze mode */ 2014 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2015 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2016 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2017 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2018 } 2019 2020 /* 2021 * Try to learn something about the supported media. 2022 * We know that ASIX and ADMtek and Davicom devices 2023 * will *always* be using MII media, so that's a no-brainer. 2024 * The tricky ones are the Macronix/PNIC II and the 2025 * Intel 21143. 2026 */ 2027 if (DC_IS_INTEL(sc)) 2028 dc_parse_21143_srom(sc); 2029 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2030 if (sc->dc_type == DC_TYPE_98713) 2031 sc->dc_pmode = DC_PMODE_MII; 2032 else 2033 sc->dc_pmode = DC_PMODE_SYM; 2034 } else if (!sc->dc_pmode) 2035 sc->dc_pmode = DC_PMODE_MII; 2036 2037 /* 2038 * Get station address from the EEPROM. 2039 */ 2040 switch(sc->dc_type) { 2041 case DC_TYPE_98713: 2042 case DC_TYPE_98713A: 2043 case DC_TYPE_987x5: 2044 case DC_TYPE_PNICII: 2045 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2046 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2047 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2048 break; 2049 case DC_TYPE_PNIC: 2050 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2051 break; 2052 case DC_TYPE_DM9102: 2053 case DC_TYPE_21143: 2054 case DC_TYPE_ASIX: 2055 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2056 break; 2057 case DC_TYPE_AL981: 2058 case DC_TYPE_AN985: 2059 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0); 2060 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1); 2061 break; 2062 case DC_TYPE_CONEXANT: 2063 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2064 break; 2065 case DC_TYPE_XIRCOM: 2066 /* The MAC comes from the CIS */ 2067 mac = pci_get_ether(dev); 2068 if (!mac) { 2069 device_printf(dev, "No station address in CIS!\n"); 2070 error = ENXIO; 2071 goto fail; 2072 } 2073 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2074 break; 2075 default: 2076 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2077 break; 2078 } 2079 2080 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2081 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 2082 2083 if (sc->dc_ldata == NULL) { 2084 device_printf(dev, "no memory for list buffers!\n"); 2085 error = ENXIO; 2086 goto fail; 2087 } 2088 2089 ifp->if_softc = sc; 2090 ifp->if_mtu = ETHERMTU; 2091 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2092 ifp->if_ioctl = dc_ioctl; 2093 ifp->if_start = dc_start; 2094 #ifdef DEVICE_POLLING 2095 ifp->if_poll = dc_poll; 2096 #endif 2097 ifp->if_watchdog = dc_watchdog; 2098 ifp->if_init = dc_init; 2099 ifp->if_baudrate = 10000000; 2100 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2101 ifq_set_ready(&ifp->if_snd); 2102 2103 /* 2104 * Do MII setup. If this is a 21143, check for a PHY on the 2105 * MII bus after applying any necessary fixups to twiddle the 2106 * GPIO bits. If we don't end up finding a PHY, restore the 2107 * old selection (SIA only or SIA/SYM) and attach the dcphy 2108 * driver instead. 2109 */ 2110 if (DC_IS_INTEL(sc)) { 2111 dc_apply_fixup(sc, IFM_AUTO); 2112 tmp = sc->dc_pmode; 2113 sc->dc_pmode = DC_PMODE_MII; 2114 } 2115 2116 /* 2117 * Setup General Purpose port mode and data so the tulip can talk 2118 * to the MII. This needs to be done before mii_phy_probe so that 2119 * we can actually see them. 2120 */ 2121 if (DC_IS_XIRCOM(sc)) { 2122 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2123 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2124 DELAY(10); 2125 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2126 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2127 DELAY(10); 2128 } 2129 2130 error = mii_phy_probe(dev, &sc->dc_miibus, 2131 dc_ifmedia_upd, dc_ifmedia_sts); 2132 2133 if (error && DC_IS_INTEL(sc)) { 2134 sc->dc_pmode = tmp; 2135 if (sc->dc_pmode != DC_PMODE_SIA) 2136 sc->dc_pmode = DC_PMODE_SYM; 2137 sc->dc_flags |= DC_21143_NWAY; 2138 mii_phy_probe(dev, &sc->dc_miibus, 2139 dc_ifmedia_upd, dc_ifmedia_sts); 2140 /* 2141 * For non-MII cards, we need to have the 21143 2142 * drive the LEDs. Except there are some systems 2143 * like the NEC VersaPro NoteBook PC which have no 2144 * LEDs, and twiddling these bits has adverse effects 2145 * on them. (I.e. you suddenly can't get a link.) 2146 */ 2147 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2148 sc->dc_flags |= DC_TULIP_LEDS; 2149 error = 0; 2150 } 2151 2152 if (error) { 2153 device_printf(dev, "MII without any PHY!\n"); 2154 error = ENXIO; 2155 goto fail; 2156 } 2157 2158 /* 2159 * Call MI attach routine. 2160 */ 2161 ether_ifattach(ifp, eaddr, NULL); 2162 2163 if (DC_IS_ADMTEK(sc)) { 2164 /* 2165 * Set automatic TX underrun recovery for the ADMtek chips 2166 */ 2167 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2168 } 2169 2170 /* 2171 * Tell the upper layer(s) we support long frames. 2172 */ 2173 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2174 2175 error = bus_setup_intr(dev, sc->dc_irq, INTR_NETSAFE, 2176 dc_intr, sc, &sc->dc_intrhand, 2177 ifp->if_serializer); 2178 if (error) { 2179 ether_ifdetach(ifp); 2180 device_printf(dev, "couldn't set up irq\n"); 2181 goto fail; 2182 } 2183 2184 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->dc_irq)); 2185 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 2186 2187 return(0); 2188 2189 fail: 2190 dc_detach(dev); 2191 return(error); 2192 } 2193 2194 static int 2195 dc_detach(device_t dev) 2196 { 2197 struct dc_softc *sc = device_get_softc(dev); 2198 struct ifnet *ifp = &sc->arpcom.ac_if; 2199 struct dc_mediainfo *m; 2200 2201 if (device_is_attached(dev)) { 2202 lwkt_serialize_enter(ifp->if_serializer); 2203 dc_stop(sc); 2204 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2205 lwkt_serialize_exit(ifp->if_serializer); 2206 2207 ether_ifdetach(ifp); 2208 } 2209 2210 if (sc->dc_miibus) 2211 device_delete_child(dev, sc->dc_miibus); 2212 bus_generic_detach(dev); 2213 2214 if (sc->dc_irq) 2215 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2216 if (sc->dc_res) 2217 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2218 2219 if (sc->dc_ldata) 2220 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2221 if (sc->dc_pnic_rx_buf != NULL) 2222 kfree(sc->dc_pnic_rx_buf, M_DEVBUF); 2223 2224 while (sc->dc_mi != NULL) { 2225 m = sc->dc_mi->dc_next; 2226 kfree(sc->dc_mi, M_DEVBUF); 2227 sc->dc_mi = m; 2228 } 2229 2230 if (sc->dc_srom) 2231 kfree(sc->dc_srom, M_DEVBUF); 2232 2233 return(0); 2234 } 2235 2236 /* 2237 * Initialize the transmit descriptors. 2238 */ 2239 static int 2240 dc_list_tx_init(struct dc_softc *sc) 2241 { 2242 struct dc_chain_data *cd; 2243 struct dc_list_data *ld; 2244 int i; 2245 2246 cd = &sc->dc_cdata; 2247 ld = sc->dc_ldata; 2248 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2249 if (i == (DC_TX_LIST_CNT - 1)) { 2250 ld->dc_tx_list[i].dc_next = 2251 vtophys(&ld->dc_tx_list[0]); 2252 } else { 2253 ld->dc_tx_list[i].dc_next = 2254 vtophys(&ld->dc_tx_list[i + 1]); 2255 } 2256 cd->dc_tx_chain[i] = NULL; 2257 ld->dc_tx_list[i].dc_data = 0; 2258 ld->dc_tx_list[i].dc_ctl = 0; 2259 } 2260 2261 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2262 2263 return(0); 2264 } 2265 2266 2267 /* 2268 * Initialize the RX descriptors and allocate mbufs for them. Note that 2269 * we arrange the descriptors in a closed ring, so that the last descriptor 2270 * points back to the first. 2271 */ 2272 static int 2273 dc_list_rx_init(struct dc_softc *sc) 2274 { 2275 struct dc_chain_data *cd; 2276 struct dc_list_data *ld; 2277 int i; 2278 2279 cd = &sc->dc_cdata; 2280 ld = sc->dc_ldata; 2281 2282 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2283 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2284 return(ENOBUFS); 2285 if (i == (DC_RX_LIST_CNT - 1)) { 2286 ld->dc_rx_list[i].dc_next = 2287 vtophys(&ld->dc_rx_list[0]); 2288 } else { 2289 ld->dc_rx_list[i].dc_next = 2290 vtophys(&ld->dc_rx_list[i + 1]); 2291 } 2292 } 2293 2294 cd->dc_rx_prod = 0; 2295 2296 return(0); 2297 } 2298 2299 /* 2300 * Initialize an RX descriptor and attach an MBUF cluster. 2301 */ 2302 static int 2303 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) 2304 { 2305 struct mbuf *m_new = NULL; 2306 struct dc_desc *c; 2307 2308 c = &sc->dc_ldata->dc_rx_list[i]; 2309 2310 if (m == NULL) { 2311 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2312 if (m_new == NULL) 2313 return (ENOBUFS); 2314 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2315 } else { 2316 m_new = m; 2317 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2318 m_new->m_data = m_new->m_ext.ext_buf; 2319 } 2320 2321 m_adj(m_new, sizeof(u_int64_t)); 2322 2323 /* 2324 * If this is a PNIC chip, zero the buffer. This is part 2325 * of the workaround for the receive bug in the 82c168 and 2326 * 82c169 chips. 2327 */ 2328 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2329 bzero((char *)mtod(m_new, char *), m_new->m_len); 2330 2331 sc->dc_cdata.dc_rx_chain[i] = m_new; 2332 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2333 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2334 c->dc_status = DC_RXSTAT_OWN; 2335 2336 return(0); 2337 } 2338 2339 /* 2340 * Grrrrr. 2341 * The PNIC chip has a terrible bug in it that manifests itself during 2342 * periods of heavy activity. The exact mode of failure if difficult to 2343 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2344 * will happen on slow machines. The bug is that sometimes instead of 2345 * uploading one complete frame during reception, it uploads what looks 2346 * like the entire contents of its FIFO memory. The frame we want is at 2347 * the end of the whole mess, but we never know exactly how much data has 2348 * been uploaded, so salvaging the frame is hard. 2349 * 2350 * There is only one way to do it reliably, and it's disgusting. 2351 * Here's what we know: 2352 * 2353 * - We know there will always be somewhere between one and three extra 2354 * descriptors uploaded. 2355 * 2356 * - We know the desired received frame will always be at the end of the 2357 * total data upload. 2358 * 2359 * - We know the size of the desired received frame because it will be 2360 * provided in the length field of the status word in the last descriptor. 2361 * 2362 * Here's what we do: 2363 * 2364 * - When we allocate buffers for the receive ring, we bzero() them. 2365 * This means that we know that the buffer contents should be all 2366 * zeros, except for data uploaded by the chip. 2367 * 2368 * - We also force the PNIC chip to upload frames that include the 2369 * ethernet CRC at the end. 2370 * 2371 * - We gather all of the bogus frame data into a single buffer. 2372 * 2373 * - We then position a pointer at the end of this buffer and scan 2374 * backwards until we encounter the first non-zero byte of data. 2375 * This is the end of the received frame. We know we will encounter 2376 * some data at the end of the frame because the CRC will always be 2377 * there, so even if the sender transmits a packet of all zeros, 2378 * we won't be fooled. 2379 * 2380 * - We know the size of the actual received frame, so we subtract 2381 * that value from the current pointer location. This brings us 2382 * to the start of the actual received packet. 2383 * 2384 * - We copy this into an mbuf and pass it on, along with the actual 2385 * frame length. 2386 * 2387 * The performance hit is tremendous, but it beats dropping frames all 2388 * the time. 2389 */ 2390 2391 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2392 static void 2393 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2394 { 2395 struct dc_desc *cur_rx; 2396 struct dc_desc *c = NULL; 2397 struct mbuf *m = NULL; 2398 unsigned char *ptr; 2399 int i, total_len; 2400 u_int32_t rxstat = 0; 2401 2402 i = sc->dc_pnic_rx_bug_save; 2403 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2404 ptr = sc->dc_pnic_rx_buf; 2405 bzero(ptr, DC_RXLEN * 5); 2406 2407 /* Copy all the bytes from the bogus buffers. */ 2408 while (1) { 2409 c = &sc->dc_ldata->dc_rx_list[i]; 2410 rxstat = c->dc_status; 2411 m = sc->dc_cdata.dc_rx_chain[i]; 2412 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2413 ptr += DC_RXLEN; 2414 /* If this is the last buffer, break out. */ 2415 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2416 break; 2417 dc_newbuf(sc, i, m); 2418 DC_INC(i, DC_RX_LIST_CNT); 2419 } 2420 2421 /* Find the length of the actual receive frame. */ 2422 total_len = DC_RXBYTES(rxstat); 2423 2424 /* Scan backwards until we hit a non-zero byte. */ 2425 while(*ptr == 0x00) 2426 ptr--; 2427 2428 /* Round off. */ 2429 if ((uintptr_t)(ptr) & 0x3) 2430 ptr -= 1; 2431 2432 /* Now find the start of the frame. */ 2433 ptr -= total_len; 2434 if (ptr < sc->dc_pnic_rx_buf) 2435 ptr = sc->dc_pnic_rx_buf; 2436 2437 /* 2438 * Now copy the salvaged frame to the last mbuf and fake up 2439 * the status word to make it look like a successful 2440 * frame reception. 2441 */ 2442 dc_newbuf(sc, i, m); 2443 bcopy(ptr, mtod(m, char *), total_len); 2444 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2445 2446 return; 2447 } 2448 2449 /* 2450 * This routine searches the RX ring for dirty descriptors in the 2451 * event that the rxeof routine falls out of sync with the chip's 2452 * current descriptor pointer. This may happen sometimes as a result 2453 * of a "no RX buffer available" condition that happens when the chip 2454 * consumes all of the RX buffers before the driver has a chance to 2455 * process the RX ring. This routine may need to be called more than 2456 * once to bring the driver back in sync with the chip, however we 2457 * should still be getting RX DONE interrupts to drive the search 2458 * for new packets in the RX ring, so we should catch up eventually. 2459 */ 2460 static int 2461 dc_rx_resync(struct dc_softc *sc) 2462 { 2463 int i, pos; 2464 struct dc_desc *cur_rx; 2465 2466 pos = sc->dc_cdata.dc_rx_prod; 2467 2468 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2469 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2470 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2471 break; 2472 DC_INC(pos, DC_RX_LIST_CNT); 2473 } 2474 2475 /* If the ring really is empty, then just return. */ 2476 if (i == DC_RX_LIST_CNT) 2477 return(0); 2478 2479 /* We've fallen behing the chip: catch it. */ 2480 sc->dc_cdata.dc_rx_prod = pos; 2481 2482 return(EAGAIN); 2483 } 2484 2485 /* 2486 * A frame has been uploaded: pass the resulting mbuf chain up to 2487 * the higher level protocols. 2488 */ 2489 static void 2490 dc_rxeof(struct dc_softc *sc) 2491 { 2492 struct mbuf *m; 2493 struct ifnet *ifp; 2494 struct dc_desc *cur_rx; 2495 int i, total_len = 0; 2496 u_int32_t rxstat; 2497 2498 ifp = &sc->arpcom.ac_if; 2499 i = sc->dc_cdata.dc_rx_prod; 2500 2501 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2502 2503 #ifdef DEVICE_POLLING 2504 if (ifp->if_flags & IFF_POLLING) { 2505 if (sc->rxcycles <= 0) 2506 break; 2507 sc->rxcycles--; 2508 } 2509 #endif /* DEVICE_POLLING */ 2510 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2511 rxstat = cur_rx->dc_status; 2512 m = sc->dc_cdata.dc_rx_chain[i]; 2513 total_len = DC_RXBYTES(rxstat); 2514 2515 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2516 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2517 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2518 sc->dc_pnic_rx_bug_save = i; 2519 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2520 DC_INC(i, DC_RX_LIST_CNT); 2521 continue; 2522 } 2523 dc_pnic_rx_bug_war(sc, i); 2524 rxstat = cur_rx->dc_status; 2525 total_len = DC_RXBYTES(rxstat); 2526 } 2527 } 2528 2529 sc->dc_cdata.dc_rx_chain[i] = NULL; 2530 2531 /* 2532 * If an error occurs, update stats, clear the 2533 * status word and leave the mbuf cluster in place: 2534 * it should simply get re-used next time this descriptor 2535 * comes up in the ring. However, don't report long 2536 * frames as errors since they could be vlans 2537 */ 2538 if ((rxstat & DC_RXSTAT_RXERR)){ 2539 if (!(rxstat & DC_RXSTAT_GIANT) || 2540 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2541 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2542 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2543 ifp->if_ierrors++; 2544 if (rxstat & DC_RXSTAT_COLLSEEN) 2545 ifp->if_collisions++; 2546 dc_newbuf(sc, i, m); 2547 if (rxstat & DC_RXSTAT_CRCERR) { 2548 DC_INC(i, DC_RX_LIST_CNT); 2549 continue; 2550 } else { 2551 dc_init(sc); 2552 return; 2553 } 2554 } 2555 } 2556 2557 /* No errors; receive the packet. */ 2558 total_len -= ETHER_CRC_LEN; 2559 2560 #ifdef __i386__ 2561 /* 2562 * On the x86 we do not have alignment problems, so try to 2563 * allocate a new buffer for the receive ring, and pass up 2564 * the one where the packet is already, saving the expensive 2565 * copy done in m_devget(). 2566 * If we are on an architecture with alignment problems, or 2567 * if the allocation fails, then use m_devget and leave the 2568 * existing buffer in the receive ring. 2569 */ 2570 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2571 m->m_pkthdr.rcvif = ifp; 2572 m->m_pkthdr.len = m->m_len = total_len; 2573 DC_INC(i, DC_RX_LIST_CNT); 2574 } else 2575 #endif 2576 { 2577 struct mbuf *m0; 2578 2579 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2580 total_len + ETHER_ALIGN, 0, ifp, NULL); 2581 dc_newbuf(sc, i, m); 2582 DC_INC(i, DC_RX_LIST_CNT); 2583 if (m0 == NULL) { 2584 ifp->if_ierrors++; 2585 continue; 2586 } 2587 m_adj(m0, ETHER_ALIGN); 2588 m = m0; 2589 } 2590 2591 ifp->if_ipackets++; 2592 ifp->if_input(ifp, m); 2593 } 2594 2595 sc->dc_cdata.dc_rx_prod = i; 2596 } 2597 2598 /* 2599 * A frame was downloaded to the chip. It's safe for us to clean up 2600 * the list buffers. 2601 */ 2602 2603 static void 2604 dc_txeof(struct dc_softc *sc) 2605 { 2606 struct dc_desc *cur_tx = NULL; 2607 struct ifnet *ifp; 2608 int idx; 2609 2610 ifp = &sc->arpcom.ac_if; 2611 2612 /* 2613 * Go through our tx list and free mbufs for those 2614 * frames that have been transmitted. 2615 */ 2616 idx = sc->dc_cdata.dc_tx_cons; 2617 while(idx != sc->dc_cdata.dc_tx_prod) { 2618 u_int32_t txstat; 2619 2620 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2621 txstat = cur_tx->dc_status; 2622 2623 if (txstat & DC_TXSTAT_OWN) 2624 break; 2625 2626 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2627 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2628 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2629 /* 2630 * Yes, the PNIC is so brain damaged 2631 * that it will sometimes generate a TX 2632 * underrun error while DMAing the RX 2633 * filter setup frame. If we detect this, 2634 * we have to send the setup frame again, 2635 * or else the filter won't be programmed 2636 * correctly. 2637 */ 2638 if (DC_IS_PNIC(sc)) { 2639 if (txstat & DC_TXSTAT_ERRSUM) 2640 dc_setfilt(sc); 2641 } 2642 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2643 } 2644 sc->dc_cdata.dc_tx_cnt--; 2645 DC_INC(idx, DC_TX_LIST_CNT); 2646 continue; 2647 } 2648 2649 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2650 /* 2651 * XXX: Why does my Xircom taunt me so? 2652 * For some reason Conexant chips like 2653 * setting the CARRLOST flag even when 2654 * the carrier is there. In CURRENT we 2655 * have the same problem for Xircom 2656 * cards ! 2657 */ 2658 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2659 sc->dc_pmode == DC_PMODE_MII && 2660 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2661 DC_TXSTAT_NOCARRIER))) 2662 txstat &= ~DC_TXSTAT_ERRSUM; 2663 } else { 2664 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2665 sc->dc_pmode == DC_PMODE_MII && 2666 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2667 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2668 txstat &= ~DC_TXSTAT_ERRSUM; 2669 } 2670 2671 if (txstat & DC_TXSTAT_ERRSUM) { 2672 ifp->if_oerrors++; 2673 if (txstat & DC_TXSTAT_EXCESSCOLL) 2674 ifp->if_collisions++; 2675 if (txstat & DC_TXSTAT_LATECOLL) 2676 ifp->if_collisions++; 2677 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2678 dc_init(sc); 2679 return; 2680 } 2681 } 2682 2683 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2684 2685 ifp->if_opackets++; 2686 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2687 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2688 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2689 } 2690 2691 sc->dc_cdata.dc_tx_cnt--; 2692 DC_INC(idx, DC_TX_LIST_CNT); 2693 } 2694 2695 if (idx != sc->dc_cdata.dc_tx_cons) { 2696 /* some buffers have been freed */ 2697 sc->dc_cdata.dc_tx_cons = idx; 2698 ifp->if_flags &= ~IFF_OACTIVE; 2699 } 2700 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2701 2702 return; 2703 } 2704 2705 static void 2706 dc_tick(void *xsc) 2707 { 2708 struct dc_softc *sc = xsc; 2709 struct ifnet *ifp = &sc->arpcom.ac_if; 2710 struct mii_data *mii; 2711 u_int32_t r; 2712 2713 lwkt_serialize_enter(ifp->if_serializer); 2714 2715 mii = device_get_softc(sc->dc_miibus); 2716 2717 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2718 if (sc->dc_flags & DC_21143_NWAY) { 2719 r = CSR_READ_4(sc, DC_10BTSTAT); 2720 if (IFM_SUBTYPE(mii->mii_media_active) == 2721 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2722 sc->dc_link = 0; 2723 mii_mediachg(mii); 2724 } 2725 if (IFM_SUBTYPE(mii->mii_media_active) == 2726 IFM_10_T && (r & DC_TSTAT_LS10)) { 2727 sc->dc_link = 0; 2728 mii_mediachg(mii); 2729 } 2730 if (sc->dc_link == 0) 2731 mii_tick(mii); 2732 } else { 2733 r = CSR_READ_4(sc, DC_ISR); 2734 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2735 sc->dc_cdata.dc_tx_cnt == 0) { 2736 mii_tick(mii); 2737 if (!(mii->mii_media_status & IFM_ACTIVE)) 2738 sc->dc_link = 0; 2739 } 2740 } 2741 } else { 2742 mii_tick(mii); 2743 } 2744 2745 /* 2746 * When the init routine completes, we expect to be able to send 2747 * packets right away, and in fact the network code will send a 2748 * gratuitous ARP the moment the init routine marks the interface 2749 * as running. However, even though the MAC may have been initialized, 2750 * there may be a delay of a few seconds before the PHY completes 2751 * autonegotiation and the link is brought up. Any transmissions 2752 * made during that delay will be lost. Dealing with this is tricky: 2753 * we can't just pause in the init routine while waiting for the 2754 * PHY to come ready since that would bring the whole system to 2755 * a screeching halt for several seconds. 2756 * 2757 * What we do here is prevent the TX start routine from sending 2758 * any packets until a link has been established. After the 2759 * interface has been initialized, the tick routine will poll 2760 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2761 * that time, packets will stay in the send queue, and once the 2762 * link comes up, they will be flushed out to the wire. 2763 */ 2764 if (!sc->dc_link) { 2765 mii_pollstat(mii); 2766 if (mii->mii_media_status & IFM_ACTIVE && 2767 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2768 sc->dc_link++; 2769 if (!ifq_is_empty(&ifp->if_snd)) 2770 if_devstart(ifp); 2771 } 2772 } 2773 2774 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2775 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2776 else 2777 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2778 2779 lwkt_serialize_exit(ifp->if_serializer); 2780 } 2781 2782 /* 2783 * A transmit underrun has occurred. Back off the transmit threshold, 2784 * or switch to store and forward mode if we have to. 2785 */ 2786 static void 2787 dc_tx_underrun(struct dc_softc *sc) 2788 { 2789 u_int32_t isr; 2790 int i; 2791 2792 if (DC_IS_DAVICOM(sc)) 2793 dc_init(sc); 2794 2795 if (DC_IS_INTEL(sc)) { 2796 /* 2797 * The real 21143 requires that the transmitter be idle 2798 * in order to change the transmit threshold or store 2799 * and forward state. 2800 */ 2801 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2802 2803 for (i = 0; i < DC_TIMEOUT; i++) { 2804 isr = CSR_READ_4(sc, DC_ISR); 2805 if (isr & DC_ISR_TX_IDLE) 2806 break; 2807 DELAY(10); 2808 } 2809 if (i == DC_TIMEOUT) { 2810 if_printf(&sc->arpcom.ac_if, 2811 "failed to force tx to idle state\n"); 2812 dc_init(sc); 2813 } 2814 } 2815 2816 if_printf(&sc->arpcom.ac_if, "TX underrun -- "); 2817 sc->dc_txthresh += DC_TXTHRESH_INC; 2818 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2819 kprintf("using store and forward mode\n"); 2820 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2821 } else { 2822 kprintf("increasing TX threshold\n"); 2823 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2824 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2825 } 2826 2827 if (DC_IS_INTEL(sc)) 2828 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2829 2830 return; 2831 } 2832 2833 #ifdef DEVICE_POLLING 2834 2835 static void 2836 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2837 { 2838 struct dc_softc *sc = ifp->if_softc; 2839 u_int32_t status; 2840 2841 switch(cmd) { 2842 case POLL_REGISTER: 2843 /* Disable interrupts */ 2844 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2845 break; 2846 case POLL_DEREGISTER: 2847 /* Re-enable interrupts. */ 2848 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2849 break; 2850 case POLL_ONLY: 2851 sc->rxcycles = count; 2852 dc_rxeof(sc); 2853 dc_txeof(sc); 2854 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2855 if_devstart(ifp); 2856 break; 2857 case POLL_AND_CHECK_STATUS: 2858 sc->rxcycles = count; 2859 dc_rxeof(sc); 2860 dc_txeof(sc); 2861 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2862 if_devstart(ifp); 2863 status = CSR_READ_4(sc, DC_ISR); 2864 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2865 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2866 DC_ISR_BUS_ERR); 2867 if (!status) 2868 break; 2869 /* ack what we have */ 2870 CSR_WRITE_4(sc, DC_ISR, status); 2871 2872 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2873 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2874 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2875 2876 if (dc_rx_resync(sc)) 2877 dc_rxeof(sc); 2878 } 2879 /* restart transmit unit if necessary */ 2880 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2881 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2882 2883 if (status & DC_ISR_TX_UNDERRUN) 2884 dc_tx_underrun(sc); 2885 2886 if (status & DC_ISR_BUS_ERR) { 2887 if_printf(ifp, "dc_poll: bus error\n"); 2888 dc_reset(sc); 2889 dc_init(sc); 2890 } 2891 break; 2892 } 2893 } 2894 #endif /* DEVICE_POLLING */ 2895 2896 static void 2897 dc_intr(void *arg) 2898 { 2899 struct dc_softc *sc; 2900 struct ifnet *ifp; 2901 u_int32_t status; 2902 2903 sc = arg; 2904 2905 if (sc->suspended) { 2906 return; 2907 } 2908 2909 ifp = &sc->arpcom.ac_if; 2910 2911 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2912 return ; 2913 2914 /* Suppress unwanted interrupts */ 2915 if (!(ifp->if_flags & IFF_UP)) { 2916 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2917 dc_stop(sc); 2918 return; 2919 } 2920 2921 /* Disable interrupts. */ 2922 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2923 2924 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 2925 status != 0xFFFFFFFF) { 2926 2927 CSR_WRITE_4(sc, DC_ISR, status); 2928 2929 if (status & DC_ISR_RX_OK) { 2930 int curpkts; 2931 curpkts = ifp->if_ipackets; 2932 dc_rxeof(sc); 2933 if (curpkts == ifp->if_ipackets) { 2934 while(dc_rx_resync(sc)) 2935 dc_rxeof(sc); 2936 } 2937 } 2938 2939 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2940 dc_txeof(sc); 2941 2942 if (status & DC_ISR_TX_IDLE) { 2943 dc_txeof(sc); 2944 if (sc->dc_cdata.dc_tx_cnt) { 2945 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2946 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2947 } 2948 } 2949 2950 if (status & DC_ISR_TX_UNDERRUN) 2951 dc_tx_underrun(sc); 2952 2953 if ((status & DC_ISR_RX_WATDOGTIMEO) 2954 || (status & DC_ISR_RX_NOBUF)) { 2955 int curpkts; 2956 curpkts = ifp->if_ipackets; 2957 dc_rxeof(sc); 2958 if (curpkts == ifp->if_ipackets) { 2959 while(dc_rx_resync(sc)) 2960 dc_rxeof(sc); 2961 } 2962 } 2963 2964 if (status & DC_ISR_BUS_ERR) { 2965 dc_reset(sc); 2966 dc_init(sc); 2967 } 2968 } 2969 2970 /* Re-enable interrupts. */ 2971 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2972 2973 if (!ifq_is_empty(&ifp->if_snd)) 2974 if_devstart(ifp); 2975 } 2976 2977 /* 2978 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2979 * pointers to the fragment pointers. 2980 */ 2981 static int 2982 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2983 { 2984 struct dc_desc *f = NULL; 2985 struct mbuf *m; 2986 int frag, cur, cnt = 0; 2987 2988 /* 2989 * Start packing the mbufs in this chain into 2990 * the fragment pointers. Stop when we run out 2991 * of fragments or hit the end of the mbuf chain. 2992 */ 2993 m = m_head; 2994 cur = frag = *txidx; 2995 2996 for (m = m_head; m != NULL; m = m->m_next) { 2997 if (m->m_len != 0) { 2998 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2999 if (*txidx != sc->dc_cdata.dc_tx_prod && 3000 frag == (DC_TX_LIST_CNT - 1)) 3001 return(ENOBUFS); 3002 } 3003 if ((DC_TX_LIST_CNT - 3004 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3005 return(ENOBUFS); 3006 3007 f = &sc->dc_ldata->dc_tx_list[frag]; 3008 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3009 if (cnt == 0) { 3010 f->dc_status = 0; 3011 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3012 } else 3013 f->dc_status = DC_TXSTAT_OWN; 3014 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3015 cur = frag; 3016 DC_INC(frag, DC_TX_LIST_CNT); 3017 cnt++; 3018 } 3019 } 3020 3021 if (m != NULL) 3022 return(ENOBUFS); 3023 3024 sc->dc_cdata.dc_tx_cnt += cnt; 3025 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3026 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3027 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3028 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3029 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3030 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3031 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3032 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3033 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3034 *txidx = frag; 3035 3036 return(0); 3037 } 3038 3039 /* 3040 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3041 * to the mbuf data regions directly in the transmit lists. We also save a 3042 * copy of the pointers since the transmit list fragment pointers are 3043 * physical addresses. 3044 */ 3045 3046 static void 3047 dc_start(struct ifnet *ifp) 3048 { 3049 struct dc_softc *sc; 3050 struct mbuf *m_head, *m_defragged; 3051 int idx, need_trans; 3052 3053 sc = ifp->if_softc; 3054 3055 if (!sc->dc_link) { 3056 ifq_purge(&ifp->if_snd); 3057 return; 3058 } 3059 3060 if (ifp->if_flags & IFF_OACTIVE) 3061 return; 3062 3063 idx = sc->dc_cdata.dc_tx_prod; 3064 3065 need_trans = 0; 3066 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3067 m_defragged = NULL; 3068 m_head = ifq_dequeue(&ifp->if_snd, NULL); 3069 if (m_head == NULL) 3070 break; 3071 3072 if ((sc->dc_flags & DC_TX_COALESCE) && 3073 (m_head->m_next != NULL || (sc->dc_flags & DC_TX_ALIGN))) { 3074 /* 3075 * Check first if coalescing allows us to queue 3076 * the packet. We don't want to loose it if 3077 * the TX queue is full. 3078 */ 3079 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3080 idx != sc->dc_cdata.dc_tx_prod && 3081 idx == (DC_TX_LIST_CNT - 1)) { 3082 ifp->if_flags |= IFF_OACTIVE; 3083 ifq_prepend(&ifp->if_snd, m_head); 3084 break; 3085 } 3086 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { 3087 ifp->if_flags |= IFF_OACTIVE; 3088 ifq_prepend(&ifp->if_snd, m_head); 3089 break; 3090 } 3091 3092 /* only coalesce if have >1 mbufs */ 3093 m_defragged = m_defrag(m_head, MB_DONTWAIT); 3094 if (m_defragged == NULL) { 3095 ifp->if_flags |= IFF_OACTIVE; 3096 ifq_prepend(&ifp->if_snd, m_head); 3097 break; 3098 } 3099 m_head = m_defragged; 3100 } 3101 3102 if (dc_encap(sc, m_head, &idx)) { 3103 if (m_defragged) { 3104 /* 3105 * Throw away the original packet if the 3106 * defragged packet could not be encapsulated, 3107 * as well as the defragged packet. 3108 */ 3109 m_freem(m_head); 3110 } else { 3111 ifq_prepend(&ifp->if_snd, m_head); 3112 } 3113 ifp->if_flags |= IFF_OACTIVE; 3114 break; 3115 } 3116 3117 need_trans = 1; 3118 3119 /* 3120 * If there's a BPF listener, bounce a copy of this frame 3121 * to him. 3122 */ 3123 BPF_MTAP(ifp, m_head); 3124 3125 if (sc->dc_flags & DC_TX_ONE) { 3126 ifp->if_flags |= IFF_OACTIVE; 3127 break; 3128 } 3129 } 3130 3131 if (!need_trans) 3132 return; 3133 3134 /* Transmit */ 3135 sc->dc_cdata.dc_tx_prod = idx; 3136 if (!(sc->dc_flags & DC_TX_POLL)) 3137 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3138 3139 /* 3140 * Set a timeout in case the chip goes out to lunch. 3141 */ 3142 ifp->if_timer = 5; 3143 } 3144 3145 static void 3146 dc_init(void *xsc) 3147 { 3148 struct dc_softc *sc = xsc; 3149 struct ifnet *ifp = &sc->arpcom.ac_if; 3150 struct mii_data *mii; 3151 3152 mii = device_get_softc(sc->dc_miibus); 3153 3154 /* 3155 * Cancel pending I/O and free all RX/TX buffers. 3156 */ 3157 dc_stop(sc); 3158 dc_reset(sc); 3159 3160 /* 3161 * Set cache alignment and burst length. 3162 */ 3163 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3164 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3165 else 3166 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3167 /* 3168 * Evenly share the bus between receive and transmit process. 3169 */ 3170 if (DC_IS_INTEL(sc)) 3171 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3172 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3173 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3174 } else { 3175 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3176 } 3177 if (sc->dc_flags & DC_TX_POLL) 3178 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3179 switch(sc->dc_cachesize) { 3180 case 32: 3181 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3182 break; 3183 case 16: 3184 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3185 break; 3186 case 8: 3187 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3188 break; 3189 case 0: 3190 default: 3191 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3192 break; 3193 } 3194 3195 if (sc->dc_flags & DC_TX_STORENFWD) 3196 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3197 else { 3198 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3199 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3200 } else { 3201 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3202 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3203 } 3204 } 3205 3206 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3207 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3208 3209 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3210 /* 3211 * The app notes for the 98713 and 98715A say that 3212 * in order to have the chips operate properly, a magic 3213 * number must be written to CSR16. Macronix does not 3214 * document the meaning of these bits so there's no way 3215 * to know exactly what they do. The 98713 has a magic 3216 * number all its own; the rest all use a different one. 3217 */ 3218 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3219 if (sc->dc_type == DC_TYPE_98713) 3220 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3221 else 3222 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3223 } 3224 3225 if (DC_IS_XIRCOM(sc)) { 3226 /* 3227 * Setup General Purpose Port mode and data so the tulip 3228 * can talk to the MII. 3229 */ 3230 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3231 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3232 DELAY(10); 3233 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3234 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3235 DELAY(10); 3236 } 3237 3238 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3239 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3240 3241 /* Init circular RX list. */ 3242 if (dc_list_rx_init(sc) == ENOBUFS) { 3243 if_printf(ifp, "initialization failed: no " 3244 "memory for rx buffers\n"); 3245 dc_stop(sc); 3246 return; 3247 } 3248 3249 /* 3250 * Init tx descriptors. 3251 */ 3252 dc_list_tx_init(sc); 3253 3254 /* 3255 * Load the address of the RX list. 3256 */ 3257 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3258 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3259 3260 /* 3261 * Enable interrupts. 3262 */ 3263 #ifdef DEVICE_POLLING 3264 /* 3265 * ... but only if we are not polling, and make sure they are off in 3266 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3267 * after a reset. 3268 */ 3269 if (ifp->if_flags & IFF_POLLING) 3270 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3271 else 3272 #endif 3273 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3274 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3275 3276 /* Enable transmitter. */ 3277 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3278 3279 /* 3280 * If this is an Intel 21143 and we're not using the 3281 * MII port, program the LED control pins so we get 3282 * link and activity indications. 3283 */ 3284 if (sc->dc_flags & DC_TULIP_LEDS) { 3285 CSR_WRITE_4(sc, DC_WATCHDOG, 3286 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3287 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3288 } 3289 3290 /* 3291 * Load the RX/multicast filter. We do this sort of late 3292 * because the filter programming scheme on the 21143 and 3293 * some clones requires DMAing a setup frame via the TX 3294 * engine, and we need the transmitter enabled for that. 3295 */ 3296 dc_setfilt(sc); 3297 3298 /* Enable receiver. */ 3299 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3300 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3301 3302 mii_mediachg(mii); 3303 dc_setcfg(sc, sc->dc_if_media); 3304 3305 ifp->if_flags |= IFF_RUNNING; 3306 ifp->if_flags &= ~IFF_OACTIVE; 3307 3308 /* Don't start the ticker if this is a homePNA link. */ 3309 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3310 sc->dc_link = 1; 3311 else { 3312 if (sc->dc_flags & DC_21143_NWAY) 3313 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3314 else 3315 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3316 } 3317 3318 return; 3319 } 3320 3321 /* 3322 * Set media options. 3323 */ 3324 static int 3325 dc_ifmedia_upd(struct ifnet *ifp) 3326 { 3327 struct dc_softc *sc; 3328 struct mii_data *mii; 3329 struct ifmedia *ifm; 3330 3331 sc = ifp->if_softc; 3332 mii = device_get_softc(sc->dc_miibus); 3333 mii_mediachg(mii); 3334 ifm = &mii->mii_media; 3335 3336 if (DC_IS_DAVICOM(sc) && 3337 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3338 dc_setcfg(sc, ifm->ifm_media); 3339 else 3340 sc->dc_link = 0; 3341 3342 return(0); 3343 } 3344 3345 /* 3346 * Report current media status. 3347 */ 3348 static void 3349 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3350 { 3351 struct dc_softc *sc; 3352 struct mii_data *mii; 3353 struct ifmedia *ifm; 3354 3355 sc = ifp->if_softc; 3356 mii = device_get_softc(sc->dc_miibus); 3357 mii_pollstat(mii); 3358 ifm = &mii->mii_media; 3359 if (DC_IS_DAVICOM(sc)) { 3360 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3361 ifmr->ifm_active = ifm->ifm_media; 3362 ifmr->ifm_status = 0; 3363 return; 3364 } 3365 } 3366 ifmr->ifm_active = mii->mii_media_active; 3367 ifmr->ifm_status = mii->mii_media_status; 3368 3369 return; 3370 } 3371 3372 static int 3373 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3374 { 3375 struct dc_softc *sc = ifp->if_softc; 3376 struct ifreq *ifr = (struct ifreq *) data; 3377 struct mii_data *mii; 3378 int error = 0; 3379 3380 switch(command) { 3381 case SIOCSIFFLAGS: 3382 if (ifp->if_flags & IFF_UP) { 3383 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3384 (IFF_PROMISC | IFF_ALLMULTI); 3385 if (ifp->if_flags & IFF_RUNNING) { 3386 if (need_setfilt) 3387 dc_setfilt(sc); 3388 } else { 3389 sc->dc_txthresh = 0; 3390 dc_init(sc); 3391 } 3392 } else { 3393 if (ifp->if_flags & IFF_RUNNING) 3394 dc_stop(sc); 3395 } 3396 sc->dc_if_flags = ifp->if_flags; 3397 error = 0; 3398 break; 3399 case SIOCADDMULTI: 3400 case SIOCDELMULTI: 3401 dc_setfilt(sc); 3402 error = 0; 3403 break; 3404 case SIOCGIFMEDIA: 3405 case SIOCSIFMEDIA: 3406 mii = device_get_softc(sc->dc_miibus); 3407 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3408 break; 3409 default: 3410 error = ether_ioctl(ifp, command, data); 3411 break; 3412 } 3413 3414 return(error); 3415 } 3416 3417 static void 3418 dc_watchdog(struct ifnet *ifp) 3419 { 3420 struct dc_softc *sc; 3421 3422 sc = ifp->if_softc; 3423 3424 ifp->if_oerrors++; 3425 if_printf(ifp, "watchdog timeout\n"); 3426 3427 dc_stop(sc); 3428 dc_reset(sc); 3429 dc_init(sc); 3430 3431 if (!ifq_is_empty(&ifp->if_snd)) 3432 if_devstart(ifp); 3433 } 3434 3435 /* 3436 * Stop the adapter and free any mbufs allocated to the 3437 * RX and TX lists. 3438 */ 3439 static void 3440 dc_stop(struct dc_softc *sc) 3441 { 3442 int i; 3443 struct ifnet *ifp; 3444 3445 ifp = &sc->arpcom.ac_if; 3446 ifp->if_timer = 0; 3447 3448 callout_stop(&sc->dc_stat_timer); 3449 3450 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3451 3452 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3453 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3454 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3455 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3456 sc->dc_link = 0; 3457 3458 /* 3459 * Free data in the RX lists. 3460 */ 3461 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3462 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3463 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3464 sc->dc_cdata.dc_rx_chain[i] = NULL; 3465 } 3466 } 3467 bzero((char *)&sc->dc_ldata->dc_rx_list, 3468 sizeof(sc->dc_ldata->dc_rx_list)); 3469 3470 /* 3471 * Free the TX list buffers. 3472 */ 3473 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3474 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3475 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3476 DC_TXCTL_SETUP) || 3477 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3478 DC_TXCTL_LASTFRAG)) { 3479 sc->dc_cdata.dc_tx_chain[i] = NULL; 3480 continue; 3481 } 3482 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3483 sc->dc_cdata.dc_tx_chain[i] = NULL; 3484 } 3485 } 3486 bzero((char *)&sc->dc_ldata->dc_tx_list, 3487 sizeof(sc->dc_ldata->dc_tx_list)); 3488 } 3489 3490 /* 3491 * Stop all chip I/O so that the kernel's probe routines don't 3492 * get confused by errant DMAs when rebooting. 3493 */ 3494 static void 3495 dc_shutdown(device_t dev) 3496 { 3497 struct dc_softc *sc; 3498 struct ifnet *ifp; 3499 3500 sc = device_get_softc(dev); 3501 ifp = &sc->arpcom.ac_if; 3502 lwkt_serialize_enter(ifp->if_serializer); 3503 3504 dc_stop(sc); 3505 3506 lwkt_serialize_exit(ifp->if_serializer); 3507 } 3508 3509 /* 3510 * Device suspend routine. Stop the interface and save some PCI 3511 * settings in case the BIOS doesn't restore them properly on 3512 * resume. 3513 */ 3514 static int 3515 dc_suspend(device_t dev) 3516 { 3517 struct dc_softc *sc = device_get_softc(dev); 3518 struct ifnet *ifp = &sc->arpcom.ac_if; 3519 int i; 3520 lwkt_serialize_enter(ifp->if_serializer); 3521 3522 dc_stop(sc); 3523 for (i = 0; i < 5; i++) 3524 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3525 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3526 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3527 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3528 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3529 3530 sc->suspended = 1; 3531 3532 lwkt_serialize_exit(ifp->if_serializer); 3533 return (0); 3534 } 3535 3536 /* 3537 * Device resume routine. Restore some PCI settings in case the BIOS 3538 * doesn't, re-enable busmastering, and restart the interface if 3539 * appropriate. 3540 */ 3541 static int 3542 dc_resume(device_t dev) 3543 { 3544 struct dc_softc *sc = device_get_softc(dev); 3545 struct ifnet *ifp = &sc->arpcom.ac_if; 3546 int i; 3547 3548 lwkt_serialize_enter(ifp->if_serializer); 3549 dc_acpi(dev); 3550 3551 /* better way to do this? */ 3552 for (i = 0; i < 5; i++) 3553 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3554 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3555 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3556 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3557 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3558 3559 /* reenable busmastering */ 3560 pci_enable_busmaster(dev); 3561 pci_enable_io(dev, DC_RES); 3562 3563 /* reinitialize interface if necessary */ 3564 if (ifp->if_flags & IFF_UP) 3565 dc_init(sc); 3566 3567 sc->suspended = 0; 3568 lwkt_serialize_exit(ifp->if_serializer); 3569 3570 return (0); 3571 } 3572 3573 static uint32_t 3574 dc_mchash_xircom(struct dc_softc *sc, const uint8_t *addr) 3575 { 3576 uint32_t crc; 3577 3578 /* Compute CRC for the address value. */ 3579 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 3580 3581 if ((crc & 0x180) == 0x180) 3582 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 3583 else 3584 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + (12 << 4)); 3585 } 3586