1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.54 2006/12/22 23:26:19 swildner Exp $ 34 */ 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Conexant LANfinity (www.conexant.com) 52 * 53 * Datasheets for the 21143 are available at developer.intel.com. 54 * Datasheets for the clone parts can be found at their respective sites. 55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 56 * The PNIC II is essentially a Macronix 98715A chip; the only difference 57 * worth noting is that its multicast hash table is only 128 bits wide 58 * instead of 512. 59 * 60 * Written by Bill Paul <wpaul@ee.columbia.edu> 61 * Electrical Engineering Department 62 * Columbia University, New York City 63 */ 64 65 /* 66 * The Intel 21143 is the successor to the DEC 21140. It is basically 67 * the same as the 21140 but with a few new features. The 21143 supports 68 * three kinds of media attachments: 69 * 70 * o MII port, for 10Mbps and 100Mbps support and NWAY 71 * autonegotiation provided by an external PHY. 72 * o SYM port, for symbol mode 100Mbps support. 73 * o 10baseT port. 74 * o AUI/BNC port. 75 * 76 * The 100Mbps SYM port and 10baseT port can be used together in 77 * combination with the internal NWAY support to create a 10/100 78 * autosensing configuration. 79 * 80 * Note that not all tulip workalikes are handled in this driver: we only 81 * deal with those which are relatively well behaved. The Winbond is 82 * handled separately due to its different register offsets and the 83 * special handling needed for its various bugs. The PNIC is handled 84 * here, but I'm not thrilled about it. 85 * 86 * All of the workalike chips use some form of MII transceiver support 87 * with the exception of the Macronix chips, which also have a SYM port. 88 * The ASIX AX88140A is also documented to have a SYM port, but all 89 * the cards I've seen use an MII transceiver, probably because the 90 * AX88140A doesn't support internal NWAY. 91 */ 92 93 #include "opt_polling.h" 94 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 #include <sys/sysctl.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 #include <sys/thread2.h> 106 107 #include <net/if.h> 108 #include <net/ifq_var.h> 109 #include <net/if_arp.h> 110 #include <net/ethernet.h> 111 #include <net/if_dl.h> 112 #include <net/if_media.h> 113 #include <net/if_types.h> 114 #include <net/vlan/if_vlan_var.h> 115 116 #include <net/bpf.h> 117 118 #include <vm/vm.h> /* for vtophys */ 119 #include <vm/pmap.h> /* for vtophys */ 120 121 #include "../mii_layer/mii.h" 122 #include "../mii_layer/miivar.h" 123 124 #include <bus/pci/pcireg.h> 125 #include <bus/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 129 #include "if_dcreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 static const struct dc_type dc_devs[] = { 138 { DC_VENDORID_DEC, DC_DEVICEID_21143, 139 "Intel 21143 10/100BaseTX" }, 140 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 141 "Davicom DM9009 10/100BaseTX" }, 142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 143 "Davicom DM9100 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 145 "Davicom DM9102 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 147 "Davicom DM9102A 10/100BaseTX" }, 148 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 149 "ADMtek AL981 10/100BaseTX" }, 150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 151 "ADMtek AN985 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 153 "Netgear FA511 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 155 "ADMtek ADM9511 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 157 "ADMtek ADM9513 10/100BaseTX" }, 158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 159 "ASIX AX88140A 10/100BaseTX" }, 160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 161 "ASIX AX88141 10/100BaseTX" }, 162 { DC_VENDORID_MX, DC_DEVICEID_98713, 163 "Macronix 98713 10/100BaseTX" }, 164 { DC_VENDORID_MX, DC_DEVICEID_98713, 165 "Macronix 98713A 10/100BaseTX" }, 166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 167 "Compex RL100-TX 10/100BaseTX" }, 168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 169 "Compex RL100-TX 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98715/98715A 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98715AEC-C 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_987x5, 175 "Macronix 98725 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_98727, 177 "Macronix 98727/98732 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C115, 179 "LC82C115 PNIC II 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C168, 181 "82c168 PNIC 10/100BaseTX" }, 182 { DC_VENDORID_LO, DC_DEVICEID_82C168, 183 "82c169 PNIC 10/100BaseTX" }, 184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 185 "Accton EN1217 10/100BaseTX" }, 186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 187 "Accton EN2242 MiniPCI 10/100BaseTX" }, 188 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 189 "Xircom X3201 10/100BaseTX" }, 190 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 191 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 192 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 193 "3Com OfficeConnect 10/100B" }, 194 { 0, 0, NULL } 195 }; 196 197 static int dc_probe (device_t); 198 static int dc_attach (device_t); 199 static int dc_detach (device_t); 200 static int dc_suspend (device_t); 201 static int dc_resume (device_t); 202 static void dc_acpi (device_t); 203 static const struct dc_type *dc_devtype (device_t); 204 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 205 static int dc_encap (struct dc_softc *, struct mbuf *, 206 u_int32_t *); 207 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 208 static int dc_rx_resync (struct dc_softc *); 209 static void dc_rxeof (struct dc_softc *); 210 static void dc_txeof (struct dc_softc *); 211 static void dc_tick (void *); 212 static void dc_tx_underrun (struct dc_softc *); 213 static void dc_intr (void *); 214 static void dc_start (struct ifnet *); 215 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 216 struct ucred *); 217 #ifdef DEVICE_POLLING 218 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd, 219 int count); 220 #endif 221 static void dc_init (void *); 222 static void dc_stop (struct dc_softc *); 223 static void dc_watchdog (struct ifnet *); 224 static void dc_shutdown (device_t); 225 static int dc_ifmedia_upd (struct ifnet *); 226 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 227 228 static void dc_delay (struct dc_softc *); 229 static void dc_eeprom_idle (struct dc_softc *); 230 static void dc_eeprom_putbyte (struct dc_softc *, int); 231 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 232 static void dc_eeprom_getword_pnic 233 (struct dc_softc *, int, u_int16_t *); 234 static void dc_eeprom_getword_xircom 235 (struct dc_softc *, int, u_int16_t *); 236 static void dc_eeprom_width (struct dc_softc *); 237 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 238 int, int); 239 240 static void dc_mii_writebit (struct dc_softc *, int); 241 static int dc_mii_readbit (struct dc_softc *); 242 static void dc_mii_sync (struct dc_softc *); 243 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 244 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 245 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 246 static int dc_miibus_readreg (device_t, int, int); 247 static int dc_miibus_writereg (device_t, int, int, int); 248 static void dc_miibus_statchg (device_t); 249 static void dc_miibus_mediainit (device_t); 250 251 static u_int32_t dc_crc_mask (struct dc_softc *); 252 static void dc_setcfg (struct dc_softc *, int); 253 static void dc_setfilt_21143 (struct dc_softc *); 254 static void dc_setfilt_asix (struct dc_softc *); 255 static void dc_setfilt_admtek (struct dc_softc *); 256 static void dc_setfilt_xircom (struct dc_softc *); 257 258 static void dc_setfilt (struct dc_softc *); 259 260 static void dc_reset (struct dc_softc *); 261 static int dc_list_rx_init (struct dc_softc *); 262 static int dc_list_tx_init (struct dc_softc *); 263 264 static void dc_read_srom (struct dc_softc *, int); 265 static void dc_parse_21143_srom (struct dc_softc *); 266 static void dc_decode_leaf_sia (struct dc_softc *, 267 struct dc_eblock_sia *); 268 static void dc_decode_leaf_mii (struct dc_softc *, 269 struct dc_eblock_mii *); 270 static void dc_decode_leaf_sym (struct dc_softc *, 271 struct dc_eblock_sym *); 272 static void dc_apply_fixup (struct dc_softc *, int); 273 static uint32_t dc_mchash_xircom(struct dc_softc *, const uint8_t *); 274 275 #ifdef DC_USEIOSPACE 276 #define DC_RES SYS_RES_IOPORT 277 #define DC_RID DC_PCI_CFBIO 278 #else 279 #define DC_RES SYS_RES_MEMORY 280 #define DC_RID DC_PCI_CFBMA 281 #endif 282 283 static device_method_t dc_methods[] = { 284 /* Device interface */ 285 DEVMETHOD(device_probe, dc_probe), 286 DEVMETHOD(device_attach, dc_attach), 287 DEVMETHOD(device_detach, dc_detach), 288 DEVMETHOD(device_suspend, dc_suspend), 289 DEVMETHOD(device_resume, dc_resume), 290 DEVMETHOD(device_shutdown, dc_shutdown), 291 292 /* bus interface */ 293 DEVMETHOD(bus_print_child, bus_generic_print_child), 294 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 295 296 /* MII interface */ 297 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 298 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 299 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 300 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 301 302 { 0, 0 } 303 }; 304 305 static driver_t dc_driver = { 306 "dc", 307 dc_methods, 308 sizeof(struct dc_softc) 309 }; 310 311 static devclass_t dc_devclass; 312 313 #ifdef __i386__ 314 static int dc_quick=1; 315 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 316 &dc_quick,0,"do not mdevget in dc driver"); 317 #endif 318 319 DECLARE_DUMMY_MODULE(if_dc); 320 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 321 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 322 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 323 324 #define DC_SETBIT(sc, reg, x) \ 325 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 326 327 #define DC_CLRBIT(sc, reg, x) \ 328 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 329 330 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 331 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 332 333 static void 334 dc_delay(struct dc_softc *sc) 335 { 336 int idx; 337 338 for (idx = (300 / 33) + 1; idx > 0; idx--) 339 CSR_READ_4(sc, DC_BUSCTL); 340 } 341 342 static void 343 dc_eeprom_width(struct dc_softc *sc) 344 { 345 int i; 346 347 /* Force EEPROM to idle state. */ 348 dc_eeprom_idle(sc); 349 350 /* Enter EEPROM access mode. */ 351 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 352 dc_delay(sc); 353 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 354 dc_delay(sc); 355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 356 dc_delay(sc); 357 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 358 dc_delay(sc); 359 360 for (i = 3; i--;) { 361 if (6 & (1 << i)) 362 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 363 else 364 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 365 dc_delay(sc); 366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 367 dc_delay(sc); 368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 369 dc_delay(sc); 370 } 371 372 for (i = 1; i <= 12; i++) { 373 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 376 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 377 dc_delay(sc); 378 break; 379 } 380 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 } 383 384 /* Turn off EEPROM access mode. */ 385 dc_eeprom_idle(sc); 386 387 if (i < 4 || i > 12) 388 sc->dc_romwidth = 6; 389 else 390 sc->dc_romwidth = i; 391 392 /* Enter EEPROM access mode. */ 393 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 394 dc_delay(sc); 395 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 396 dc_delay(sc); 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 400 dc_delay(sc); 401 402 /* Turn off EEPROM access mode. */ 403 dc_eeprom_idle(sc); 404 } 405 406 static void 407 dc_eeprom_idle(struct dc_softc *sc) 408 { 409 int i; 410 411 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 412 dc_delay(sc); 413 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 414 dc_delay(sc); 415 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 416 dc_delay(sc); 417 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 418 dc_delay(sc); 419 420 for (i = 0; i < 25; i++) { 421 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 424 dc_delay(sc); 425 } 426 427 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 428 dc_delay(sc); 429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 430 dc_delay(sc); 431 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 432 433 return; 434 } 435 436 /* 437 * Send a read command and address to the EEPROM, check for ACK. 438 */ 439 static void 440 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 441 { 442 int d, i; 443 444 d = DC_EECMD_READ >> 6; 445 for (i = 3; i--; ) { 446 if (d & (1 << i)) 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 448 else 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 450 dc_delay(sc); 451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 } 456 457 /* 458 * Feed in each bit and strobe the clock. 459 */ 460 for (i = sc->dc_romwidth; i--;) { 461 if (addr & (1 << i)) { 462 SIO_SET(DC_SIO_EE_DATAIN); 463 } else { 464 SIO_CLR(DC_SIO_EE_DATAIN); 465 } 466 dc_delay(sc); 467 SIO_SET(DC_SIO_EE_CLK); 468 dc_delay(sc); 469 SIO_CLR(DC_SIO_EE_CLK); 470 dc_delay(sc); 471 } 472 473 return; 474 } 475 476 /* 477 * Read a word of data stored in the EEPROM at address 'addr.' 478 * The PNIC 82c168/82c169 has its own non-standard way to read 479 * the EEPROM. 480 */ 481 static void 482 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 483 { 484 int i; 485 u_int32_t r; 486 487 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 488 489 for (i = 0; i < DC_TIMEOUT; i++) { 490 DELAY(1); 491 r = CSR_READ_4(sc, DC_SIO); 492 if (!(r & DC_PN_SIOCTL_BUSY)) { 493 *dest = (u_int16_t)(r & 0xFFFF); 494 return; 495 } 496 } 497 498 return; 499 } 500 501 /* 502 * Read a word of data stored in the EEPROM at address 'addr.' 503 * The Xircom X3201 has its own non-standard way to read 504 * the EEPROM, too. 505 */ 506 static void 507 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 508 { 509 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 510 511 addr *= 2; 512 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 513 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 514 addr += 1; 515 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 516 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 517 518 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 519 } 520 521 /* 522 * Read a word of data stored in the EEPROM at address 'addr.' 523 */ 524 static void 525 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 526 { 527 int i; 528 u_int16_t word = 0; 529 530 /* Force EEPROM to idle state. */ 531 dc_eeprom_idle(sc); 532 533 /* Enter EEPROM access mode. */ 534 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 535 dc_delay(sc); 536 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 537 dc_delay(sc); 538 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 539 dc_delay(sc); 540 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 541 dc_delay(sc); 542 543 /* 544 * Send address of word we want to read. 545 */ 546 dc_eeprom_putbyte(sc, addr); 547 548 /* 549 * Start reading bits from EEPROM. 550 */ 551 for (i = 0x8000; i; i >>= 1) { 552 SIO_SET(DC_SIO_EE_CLK); 553 dc_delay(sc); 554 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 555 word |= i; 556 dc_delay(sc); 557 SIO_CLR(DC_SIO_EE_CLK); 558 dc_delay(sc); 559 } 560 561 /* Turn off EEPROM access mode. */ 562 dc_eeprom_idle(sc); 563 564 *dest = word; 565 566 return; 567 } 568 569 /* 570 * Read a sequence of words from the EEPROM. 571 */ 572 static void 573 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 574 { 575 int i; 576 u_int16_t word = 0, *ptr; 577 578 for (i = 0; i < cnt; i++) { 579 if (DC_IS_PNIC(sc)) 580 dc_eeprom_getword_pnic(sc, off + i, &word); 581 else if (DC_IS_XIRCOM(sc)) 582 dc_eeprom_getword_xircom(sc, off + i, &word); 583 else 584 dc_eeprom_getword(sc, off + i, &word); 585 ptr = (u_int16_t *)(dest + (i * 2)); 586 if (swap) 587 *ptr = ntohs(word); 588 else 589 *ptr = word; 590 } 591 592 return; 593 } 594 595 /* 596 * The following two routines are taken from the Macronix 98713 597 * Application Notes pp.19-21. 598 */ 599 /* 600 * Write a bit to the MII bus. 601 */ 602 static void 603 dc_mii_writebit(struct dc_softc *sc, int bit) 604 { 605 if (bit) 606 CSR_WRITE_4(sc, DC_SIO, 607 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 608 else 609 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 610 611 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 612 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 613 614 return; 615 } 616 617 /* 618 * Read a bit from the MII bus. 619 */ 620 static int 621 dc_mii_readbit(struct dc_softc *sc) 622 { 623 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 624 CSR_READ_4(sc, DC_SIO); 625 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 626 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 627 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 628 return(1); 629 630 return(0); 631 } 632 633 /* 634 * Sync the PHYs by setting data bit and strobing the clock 32 times. 635 */ 636 static void 637 dc_mii_sync(struct dc_softc *sc) 638 { 639 int i; 640 641 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 642 643 for (i = 0; i < 32; i++) 644 dc_mii_writebit(sc, 1); 645 646 return; 647 } 648 649 /* 650 * Clock a series of bits through the MII. 651 */ 652 static void 653 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 654 { 655 int i; 656 657 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 658 dc_mii_writebit(sc, bits & i); 659 } 660 661 /* 662 * Read an PHY register through the MII. 663 */ 664 static int 665 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 666 { 667 int ack, i; 668 669 /* 670 * Set up frame for RX. 671 */ 672 frame->mii_stdelim = DC_MII_STARTDELIM; 673 frame->mii_opcode = DC_MII_READOP; 674 frame->mii_turnaround = 0; 675 frame->mii_data = 0; 676 677 /* 678 * Sync the PHYs. 679 */ 680 dc_mii_sync(sc); 681 682 /* 683 * Send command/address info. 684 */ 685 dc_mii_send(sc, frame->mii_stdelim, 2); 686 dc_mii_send(sc, frame->mii_opcode, 2); 687 dc_mii_send(sc, frame->mii_phyaddr, 5); 688 dc_mii_send(sc, frame->mii_regaddr, 5); 689 690 #ifdef notdef 691 /* Idle bit */ 692 dc_mii_writebit(sc, 1); 693 dc_mii_writebit(sc, 0); 694 #endif 695 696 /* Check for ack */ 697 ack = dc_mii_readbit(sc); 698 699 /* 700 * Now try reading data bits. If the ack failed, we still 701 * need to clock through 16 cycles to keep the PHY(s) in sync. 702 */ 703 if (ack) { 704 for(i = 0; i < 16; i++) { 705 dc_mii_readbit(sc); 706 } 707 goto fail; 708 } 709 710 for (i = 0x8000; i; i >>= 1) { 711 if (!ack) { 712 if (dc_mii_readbit(sc)) 713 frame->mii_data |= i; 714 } 715 } 716 717 fail: 718 719 dc_mii_writebit(sc, 0); 720 dc_mii_writebit(sc, 0); 721 722 if (ack) 723 return(1); 724 return(0); 725 } 726 727 /* 728 * Write to a PHY register through the MII. 729 */ 730 static int 731 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 732 { 733 /* 734 * Set up frame for TX. 735 */ 736 737 frame->mii_stdelim = DC_MII_STARTDELIM; 738 frame->mii_opcode = DC_MII_WRITEOP; 739 frame->mii_turnaround = DC_MII_TURNAROUND; 740 741 /* 742 * Sync the PHYs. 743 */ 744 dc_mii_sync(sc); 745 746 dc_mii_send(sc, frame->mii_stdelim, 2); 747 dc_mii_send(sc, frame->mii_opcode, 2); 748 dc_mii_send(sc, frame->mii_phyaddr, 5); 749 dc_mii_send(sc, frame->mii_regaddr, 5); 750 dc_mii_send(sc, frame->mii_turnaround, 2); 751 dc_mii_send(sc, frame->mii_data, 16); 752 753 /* Idle bit. */ 754 dc_mii_writebit(sc, 0); 755 dc_mii_writebit(sc, 0); 756 757 return(0); 758 } 759 760 static int 761 dc_miibus_readreg(device_t dev, int phy, int reg) 762 { 763 struct dc_mii_frame frame; 764 struct dc_softc *sc; 765 int i, rval, phy_reg = 0; 766 767 sc = device_get_softc(dev); 768 bzero((char *)&frame, sizeof(frame)); 769 770 /* 771 * Note: both the AL981 and AN985 have internal PHYs, 772 * however the AL981 provides direct access to the PHY 773 * registers while the AN985 uses a serial MII interface. 774 * The AN985's MII interface is also buggy in that you 775 * can read from any MII address (0 to 31), but only address 1 776 * behaves normally. To deal with both cases, we pretend 777 * that the PHY is at MII address 1. 778 */ 779 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 780 return(0); 781 782 /* 783 * Note: the ukphy probes of the RS7112 report a PHY at 784 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 785 * so we only respond to correct one. 786 */ 787 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 788 return(0); 789 790 if (sc->dc_pmode != DC_PMODE_MII) { 791 if (phy == (MII_NPHY - 1)) { 792 switch(reg) { 793 case MII_BMSR: 794 /* 795 * Fake something to make the probe 796 * code think there's a PHY here. 797 */ 798 return(BMSR_MEDIAMASK); 799 break; 800 case MII_PHYIDR1: 801 if (DC_IS_PNIC(sc)) 802 return(DC_VENDORID_LO); 803 return(DC_VENDORID_DEC); 804 break; 805 case MII_PHYIDR2: 806 if (DC_IS_PNIC(sc)) 807 return(DC_DEVICEID_82C168); 808 return(DC_DEVICEID_21143); 809 break; 810 default: 811 return(0); 812 break; 813 } 814 } else 815 return(0); 816 } 817 818 if (DC_IS_PNIC(sc)) { 819 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 820 (phy << 23) | (reg << 18)); 821 for (i = 0; i < DC_TIMEOUT; i++) { 822 DELAY(1); 823 rval = CSR_READ_4(sc, DC_PN_MII); 824 if (!(rval & DC_PN_MII_BUSY)) { 825 rval &= 0xFFFF; 826 return(rval == 0xFFFF ? 0 : rval); 827 } 828 } 829 return(0); 830 } 831 832 if (DC_IS_COMET(sc)) { 833 switch(reg) { 834 case MII_BMCR: 835 phy_reg = DC_AL_BMCR; 836 break; 837 case MII_BMSR: 838 phy_reg = DC_AL_BMSR; 839 break; 840 case MII_PHYIDR1: 841 phy_reg = DC_AL_VENID; 842 break; 843 case MII_PHYIDR2: 844 phy_reg = DC_AL_DEVID; 845 break; 846 case MII_ANAR: 847 phy_reg = DC_AL_ANAR; 848 break; 849 case MII_ANLPAR: 850 phy_reg = DC_AL_LPAR; 851 break; 852 case MII_ANER: 853 phy_reg = DC_AL_ANER; 854 break; 855 default: 856 if_printf(&sc->arpcom.ac_if, 857 "phy_read: bad phy register %x\n", reg); 858 return(0); 859 break; 860 } 861 862 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 863 864 if (rval == 0xFFFF) 865 return(0); 866 return(rval); 867 } 868 869 frame.mii_phyaddr = phy; 870 frame.mii_regaddr = reg; 871 if (sc->dc_type == DC_TYPE_98713) { 872 phy_reg = CSR_READ_4(sc, DC_NETCFG); 873 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 874 } 875 dc_mii_readreg(sc, &frame); 876 if (sc->dc_type == DC_TYPE_98713) 877 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 878 879 return(frame.mii_data); 880 } 881 882 static int 883 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 884 { 885 struct dc_softc *sc; 886 struct dc_mii_frame frame; 887 int i, phy_reg = 0; 888 889 sc = device_get_softc(dev); 890 bzero((char *)&frame, sizeof(frame)); 891 892 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 893 return(0); 894 895 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 896 return(0); 897 898 if (DC_IS_PNIC(sc)) { 899 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 900 (phy << 23) | (reg << 10) | data); 901 for (i = 0; i < DC_TIMEOUT; i++) { 902 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 903 break; 904 } 905 return(0); 906 } 907 908 if (DC_IS_COMET(sc)) { 909 switch(reg) { 910 case MII_BMCR: 911 phy_reg = DC_AL_BMCR; 912 break; 913 case MII_BMSR: 914 phy_reg = DC_AL_BMSR; 915 break; 916 case MII_PHYIDR1: 917 phy_reg = DC_AL_VENID; 918 break; 919 case MII_PHYIDR2: 920 phy_reg = DC_AL_DEVID; 921 break; 922 case MII_ANAR: 923 phy_reg = DC_AL_ANAR; 924 break; 925 case MII_ANLPAR: 926 phy_reg = DC_AL_LPAR; 927 break; 928 case MII_ANER: 929 phy_reg = DC_AL_ANER; 930 break; 931 default: 932 if_printf(&sc->arpcom.ac_if, 933 "phy_write: bad phy register %x\n", reg); 934 return(0); 935 break; 936 } 937 938 CSR_WRITE_4(sc, phy_reg, data); 939 return(0); 940 } 941 942 frame.mii_phyaddr = phy; 943 frame.mii_regaddr = reg; 944 frame.mii_data = data; 945 946 if (sc->dc_type == DC_TYPE_98713) { 947 phy_reg = CSR_READ_4(sc, DC_NETCFG); 948 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 949 } 950 dc_mii_writereg(sc, &frame); 951 if (sc->dc_type == DC_TYPE_98713) 952 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 953 954 return(0); 955 } 956 957 static void 958 dc_miibus_statchg(device_t dev) 959 { 960 struct dc_softc *sc; 961 struct mii_data *mii; 962 struct ifmedia *ifm; 963 964 sc = device_get_softc(dev); 965 if (DC_IS_ADMTEK(sc)) 966 return; 967 968 mii = device_get_softc(sc->dc_miibus); 969 ifm = &mii->mii_media; 970 if (DC_IS_DAVICOM(sc) && 971 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 972 dc_setcfg(sc, ifm->ifm_media); 973 sc->dc_if_media = ifm->ifm_media; 974 } else { 975 dc_setcfg(sc, mii->mii_media_active); 976 sc->dc_if_media = mii->mii_media_active; 977 } 978 979 return; 980 } 981 982 /* 983 * Special support for DM9102A cards with HomePNA PHYs. Note: 984 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 985 * to be impossible to talk to the management interface of the DM9801 986 * PHY (its MDIO pin is not connected to anything). Consequently, 987 * the driver has to just 'know' about the additional mode and deal 988 * with it itself. *sigh* 989 */ 990 static void 991 dc_miibus_mediainit(device_t dev) 992 { 993 struct dc_softc *sc; 994 struct mii_data *mii; 995 struct ifmedia *ifm; 996 int rev; 997 998 rev = pci_get_revid(dev); 999 1000 sc = device_get_softc(dev); 1001 mii = device_get_softc(sc->dc_miibus); 1002 ifm = &mii->mii_media; 1003 1004 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1005 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1006 1007 return; 1008 } 1009 1010 #define DC_BITS_512 9 1011 #define DC_BITS_128 7 1012 #define DC_BITS_64 6 1013 1014 static u_int32_t 1015 dc_crc_mask(struct dc_softc *sc) 1016 { 1017 /* 1018 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1019 * chips is only 128 bits wide. 1020 */ 1021 if (sc->dc_flags & DC_128BIT_HASH) 1022 return ((1 << DC_BITS_128) - 1); 1023 1024 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1025 if (sc->dc_flags & DC_64BIT_HASH) 1026 return ((1 << DC_BITS_64) - 1); 1027 1028 return ((1 << DC_BITS_512) - 1); 1029 } 1030 1031 /* 1032 * 21143-style RX filter setup routine. Filter programming is done by 1033 * downloading a special setup frame into the TX engine. 21143, Macronix, 1034 * PNIC, PNIC II and Davicom chips are programmed this way. 1035 * 1036 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1037 * address (our node address) and a 512-bit hash filter for multicast 1038 * frames. We also sneak the broadcast address into the hash filter since 1039 * we need that too. 1040 */ 1041 void 1042 dc_setfilt_21143(struct dc_softc *sc) 1043 { 1044 struct dc_desc *sframe; 1045 u_int32_t h, crc_mask, *sp; 1046 struct ifmultiaddr *ifma; 1047 struct ifnet *ifp; 1048 int i; 1049 1050 ifp = &sc->arpcom.ac_if; 1051 1052 i = sc->dc_cdata.dc_tx_prod; 1053 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1054 sc->dc_cdata.dc_tx_cnt++; 1055 sframe = &sc->dc_ldata->dc_tx_list[i]; 1056 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1057 bzero((char *)sp, DC_SFRAME_LEN); 1058 1059 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1060 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1061 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1062 1063 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1064 1065 /* If we want promiscuous mode, set the allframes bit. */ 1066 if (ifp->if_flags & IFF_PROMISC) 1067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1068 else 1069 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1070 1071 if (ifp->if_flags & IFF_ALLMULTI) 1072 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1073 else 1074 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1075 1076 crc_mask = dc_crc_mask(sc); 1077 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1078 if (ifma->ifma_addr->sa_family != AF_LINK) 1079 continue; 1080 h = ether_crc32_le( 1081 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1082 ETHER_ADDR_LEN) & crc_mask; 1083 sp[h >> 4] |= 1 << (h & 0xF); 1084 } 1085 1086 if (ifp->if_flags & IFF_BROADCAST) { 1087 h = ether_crc32_le(ifp->if_broadcastaddr, 1088 ETHER_ADDR_LEN) & crc_mask; 1089 sp[h >> 4] |= 1 << (h & 0xF); 1090 } 1091 1092 /* Set our MAC address */ 1093 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1094 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1095 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1096 1097 sframe->dc_status = DC_TXSTAT_OWN; 1098 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1099 1100 /* 1101 * The PNIC takes an exceedingly long time to process its 1102 * setup frame; wait 10ms after posting the setup frame 1103 * before proceeding, just so it has time to swallow its 1104 * medicine. 1105 */ 1106 DELAY(10000); 1107 1108 ifp->if_timer = 5; 1109 1110 return; 1111 } 1112 1113 void 1114 dc_setfilt_admtek(struct dc_softc *sc) 1115 { 1116 struct ifnet *ifp; 1117 int h = 0; 1118 u_int32_t crc_mask; 1119 u_int32_t hashes[2] = { 0, 0 }; 1120 struct ifmultiaddr *ifma; 1121 1122 ifp = &sc->arpcom.ac_if; 1123 1124 /* Init our MAC address */ 1125 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1126 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1127 1128 /* If we want promiscuous mode, set the allframes bit. */ 1129 if (ifp->if_flags & IFF_PROMISC) 1130 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1131 else 1132 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1133 1134 if (ifp->if_flags & IFF_ALLMULTI) 1135 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1136 else 1137 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1138 1139 /* first, zot all the existing hash bits */ 1140 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1141 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1142 1143 /* 1144 * If we're already in promisc or allmulti mode, we 1145 * don't have to bother programming the multicast filter. 1146 */ 1147 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1148 return; 1149 1150 /* now program new ones */ 1151 if (DC_IS_CENTAUR(sc)) 1152 crc_mask = dc_crc_mask(sc); 1153 else 1154 crc_mask = 0x3f; 1155 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1156 if (ifma->ifma_addr->sa_family != AF_LINK) 1157 continue; 1158 if (DC_IS_CENTAUR(sc)) { 1159 h = ether_crc32_le( 1160 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1161 ETHER_ADDR_LEN) & crc_mask; 1162 } else { 1163 h = ether_crc32_be( 1164 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1165 ETHER_ADDR_LEN); 1166 h = (h >> 26) & crc_mask; 1167 } 1168 if (h < 32) 1169 hashes[0] |= (1 << h); 1170 else 1171 hashes[1] |= (1 << (h - 32)); 1172 } 1173 1174 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1175 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1176 1177 return; 1178 } 1179 1180 void 1181 dc_setfilt_asix(struct dc_softc *sc) 1182 { 1183 struct ifnet *ifp; 1184 int h = 0; 1185 u_int32_t hashes[2] = { 0, 0 }; 1186 struct ifmultiaddr *ifma; 1187 1188 ifp = &sc->arpcom.ac_if; 1189 1190 /* Init our MAC address */ 1191 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1192 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1193 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1194 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1195 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1196 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1197 1198 /* If we want promiscuous mode, set the allframes bit. */ 1199 if (ifp->if_flags & IFF_PROMISC) 1200 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1201 else 1202 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1203 1204 if (ifp->if_flags & IFF_ALLMULTI) 1205 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1206 else 1207 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1208 1209 /* 1210 * The ASIX chip has a special bit to enable reception 1211 * of broadcast frames. 1212 */ 1213 if (ifp->if_flags & IFF_BROADCAST) 1214 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1215 else 1216 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1217 1218 /* first, zot all the existing hash bits */ 1219 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1220 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1223 1224 /* 1225 * If we're already in promisc or allmulti mode, we 1226 * don't have to bother programming the multicast filter. 1227 */ 1228 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1229 return; 1230 1231 /* now program new ones */ 1232 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1233 if (ifma->ifma_addr->sa_family != AF_LINK) 1234 continue; 1235 h = ether_crc32_be( 1236 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1237 ETHER_ADDR_LEN); 1238 h = (h >> 26) & 0x3f; 1239 if (h < 32) 1240 hashes[0] |= (1 << h); 1241 else 1242 hashes[1] |= (1 << (h - 32)); 1243 } 1244 1245 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1246 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1247 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1248 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1249 1250 return; 1251 } 1252 1253 void 1254 dc_setfilt_xircom(struct dc_softc *sc) 1255 { 1256 struct dc_desc *sframe; 1257 u_int32_t h, *sp; 1258 struct ifmultiaddr *ifma; 1259 struct ifnet *ifp; 1260 int i; 1261 1262 ifp = &sc->arpcom.ac_if; 1263 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1264 1265 i = sc->dc_cdata.dc_tx_prod; 1266 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1267 sc->dc_cdata.dc_tx_cnt++; 1268 sframe = &sc->dc_ldata->dc_tx_list[i]; 1269 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1270 bzero(sp, DC_SFRAME_LEN); 1271 1272 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1273 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1274 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1275 1276 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1277 1278 /* If we want promiscuous mode, set the allframes bit. */ 1279 if (ifp->if_flags & IFF_PROMISC) 1280 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1281 else 1282 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1283 1284 if (ifp->if_flags & IFF_ALLMULTI) 1285 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1286 else 1287 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1288 1289 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1290 if (ifma->ifma_addr->sa_family != AF_LINK) 1291 continue; 1292 h = dc_mchash_xircom(sc, 1293 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1294 sp[h >> 4] |= 1 << (h & 0xF); 1295 } 1296 1297 if (ifp->if_flags & IFF_BROADCAST) { 1298 h = dc_mchash_xircom(sc, (caddr_t)ðerbroadcastaddr); 1299 sp[h >> 4] |= 1 << (h & 0xF); 1300 } 1301 1302 /* Set our MAC address */ 1303 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1304 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1305 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1306 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1309 ifp->if_flags |= IFF_RUNNING; 1310 sframe->dc_status = DC_TXSTAT_OWN; 1311 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1312 1313 /* 1314 * wait some time... 1315 */ 1316 DELAY(1000); 1317 1318 ifp->if_timer = 5; 1319 } 1320 1321 static void 1322 dc_setfilt(struct dc_softc *sc) 1323 { 1324 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1325 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1326 dc_setfilt_21143(sc); 1327 1328 if (DC_IS_ASIX(sc)) 1329 dc_setfilt_asix(sc); 1330 1331 if (DC_IS_ADMTEK(sc)) 1332 dc_setfilt_admtek(sc); 1333 1334 if (DC_IS_XIRCOM(sc)) 1335 dc_setfilt_xircom(sc); 1336 } 1337 1338 /* 1339 * In order to fiddle with the 1340 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1341 * first have to put the transmit and/or receive logic in the idle state. 1342 */ 1343 static void 1344 dc_setcfg(struct dc_softc *sc, int media) 1345 { 1346 int i, restart = 0; 1347 u_int32_t isr; 1348 1349 if (IFM_SUBTYPE(media) == IFM_NONE) 1350 return; 1351 1352 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1353 restart = 1; 1354 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1355 1356 for (i = 0; i < DC_TIMEOUT; i++) { 1357 isr = CSR_READ_4(sc, DC_ISR); 1358 if ((isr & DC_ISR_TX_IDLE) && 1359 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1360 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1361 break; 1362 DELAY(10); 1363 } 1364 1365 if (i == DC_TIMEOUT) { 1366 if_printf(&sc->arpcom.ac_if, 1367 "failed to force tx and rx to idle state\n"); 1368 } 1369 } 1370 1371 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1372 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1373 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1374 if (sc->dc_pmode == DC_PMODE_MII) { 1375 int watchdogreg; 1376 1377 if (DC_IS_INTEL(sc)) { 1378 /* there's a write enable bit here that reads as 1 */ 1379 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1380 watchdogreg &= ~DC_WDOG_CTLWREN; 1381 watchdogreg |= DC_WDOG_JABBERDIS; 1382 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1383 } else { 1384 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1385 } 1386 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1387 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1388 if (sc->dc_type == DC_TYPE_98713) 1389 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1390 DC_NETCFG_SCRAMBLER)); 1391 if (!DC_IS_DAVICOM(sc)) 1392 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1393 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1394 if (DC_IS_INTEL(sc)) 1395 dc_apply_fixup(sc, IFM_AUTO); 1396 } else { 1397 if (DC_IS_PNIC(sc)) { 1398 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1399 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1400 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1401 } 1402 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1405 if (DC_IS_INTEL(sc)) 1406 dc_apply_fixup(sc, 1407 (media & IFM_GMASK) == IFM_FDX ? 1408 IFM_100_TX|IFM_FDX : IFM_100_TX); 1409 } 1410 } 1411 1412 if (IFM_SUBTYPE(media) == IFM_10_T) { 1413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1414 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1415 if (sc->dc_pmode == DC_PMODE_MII) { 1416 int watchdogreg; 1417 1418 /* there's a write enable bit here that reads as 1 */ 1419 if (DC_IS_INTEL(sc)) { 1420 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1421 watchdogreg &= ~DC_WDOG_CTLWREN; 1422 watchdogreg |= DC_WDOG_JABBERDIS; 1423 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1424 } else { 1425 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1426 } 1427 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1428 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1429 if (sc->dc_type == DC_TYPE_98713) 1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1431 if (!DC_IS_DAVICOM(sc)) 1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1433 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1434 if (DC_IS_INTEL(sc)) 1435 dc_apply_fixup(sc, IFM_AUTO); 1436 } else { 1437 if (DC_IS_PNIC(sc)) { 1438 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1439 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1440 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1441 } 1442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1443 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1445 if (DC_IS_INTEL(sc)) { 1446 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1447 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1448 if ((media & IFM_GMASK) == IFM_FDX) 1449 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1450 else 1451 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1452 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1453 DC_CLRBIT(sc, DC_10BTCTRL, 1454 DC_TCTL_AUTONEGENBL); 1455 dc_apply_fixup(sc, 1456 (media & IFM_GMASK) == IFM_FDX ? 1457 IFM_10_T|IFM_FDX : IFM_10_T); 1458 DELAY(20000); 1459 } 1460 } 1461 } 1462 1463 /* 1464 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1465 * PHY and we want HomePNA mode, set the portsel bit to turn 1466 * on the external MII port. 1467 */ 1468 if (DC_IS_DAVICOM(sc)) { 1469 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1471 sc->dc_link = 1; 1472 } else { 1473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1474 } 1475 } 1476 1477 if ((media & IFM_GMASK) == IFM_FDX) { 1478 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1479 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1480 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1481 } else { 1482 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1483 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1484 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1485 } 1486 1487 if (restart) 1488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1489 1490 return; 1491 } 1492 1493 static void 1494 dc_reset(struct dc_softc *sc) 1495 { 1496 int i; 1497 1498 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1499 1500 for (i = 0; i < DC_TIMEOUT; i++) { 1501 DELAY(10); 1502 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1503 break; 1504 } 1505 1506 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) || 1507 DC_IS_CONEXANT(sc)) { 1508 DELAY(10000); 1509 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1510 i = 0; 1511 } 1512 1513 if (i == DC_TIMEOUT) 1514 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 1515 1516 /* Wait a little while for the chip to get its brains in order. */ 1517 DELAY(1000); 1518 1519 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1520 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1521 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1522 1523 /* 1524 * Bring the SIA out of reset. In some cases, it looks 1525 * like failing to unreset the SIA soon enough gets it 1526 * into a state where it will never come out of reset 1527 * until we reset the whole chip again. 1528 */ 1529 if (DC_IS_INTEL(sc)) { 1530 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1531 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1532 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1533 } 1534 1535 return; 1536 } 1537 1538 static const struct dc_type * 1539 dc_devtype(device_t dev) 1540 { 1541 const struct dc_type *t; 1542 u_int32_t rev; 1543 1544 t = dc_devs; 1545 1546 while(t->dc_name != NULL) { 1547 if ((pci_get_vendor(dev) == t->dc_vid) && 1548 (pci_get_device(dev) == t->dc_did)) { 1549 /* Check the PCI revision */ 1550 rev = pci_get_revid(dev); 1551 if (t->dc_did == DC_DEVICEID_98713 && 1552 rev >= DC_REVISION_98713A) 1553 t++; 1554 if (t->dc_did == DC_DEVICEID_98713_CP && 1555 rev >= DC_REVISION_98713A) 1556 t++; 1557 if (t->dc_did == DC_DEVICEID_987x5 && 1558 rev >= DC_REVISION_98715AEC_C) 1559 t++; 1560 if (t->dc_did == DC_DEVICEID_987x5 && 1561 rev >= DC_REVISION_98725) 1562 t++; 1563 if (t->dc_did == DC_DEVICEID_AX88140A && 1564 rev >= DC_REVISION_88141) 1565 t++; 1566 if (t->dc_did == DC_DEVICEID_82C168 && 1567 rev >= DC_REVISION_82C169) 1568 t++; 1569 if (t->dc_did == DC_DEVICEID_DM9102 && 1570 rev >= DC_REVISION_DM9102A) 1571 t++; 1572 return(t); 1573 } 1574 t++; 1575 } 1576 1577 return(NULL); 1578 } 1579 1580 /* 1581 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1582 * IDs against our list and return a device name if we find a match. 1583 * We do a little bit of extra work to identify the exact type of 1584 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1585 * but different revision IDs. The same is true for 98715/98715A 1586 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1587 * cases, the exact chip revision affects driver behavior. 1588 */ 1589 static int 1590 dc_probe(device_t dev) 1591 { 1592 const struct dc_type *t; 1593 1594 t = dc_devtype(dev); 1595 if (t != NULL) { 1596 struct dc_softc *sc = device_get_softc(dev); 1597 1598 /* Need this info to decide on a chip type. */ 1599 sc->dc_info = t; 1600 device_set_desc(dev, t->dc_name); 1601 return(0); 1602 } 1603 1604 return(ENXIO); 1605 } 1606 1607 static void 1608 dc_acpi(device_t dev) 1609 { 1610 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1611 uint32_t iobase, membase, irq; 1612 struct dc_softc *sc; 1613 1614 /* Save important PCI config data. */ 1615 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1616 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1617 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1618 1619 sc = device_get_softc(dev); 1620 /* Reset the power state. */ 1621 if_printf(&sc->arpcom.ac_if, 1622 "chip is in D%d power mode " 1623 "-- setting to D0\n", pci_get_powerstate(dev)); 1624 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1625 1626 /* Restore PCI config data. */ 1627 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1628 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1629 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1630 } 1631 } 1632 1633 static void 1634 dc_apply_fixup(struct dc_softc *sc, int media) 1635 { 1636 struct dc_mediainfo *m; 1637 u_int8_t *p; 1638 int i; 1639 u_int32_t reg; 1640 1641 m = sc->dc_mi; 1642 1643 while (m != NULL) { 1644 if (m->dc_media == media) 1645 break; 1646 m = m->dc_next; 1647 } 1648 1649 if (m == NULL) 1650 return; 1651 1652 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1653 reg = (p[0] | (p[1] << 8)) << 16; 1654 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1655 } 1656 1657 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1658 reg = (p[0] | (p[1] << 8)) << 16; 1659 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1660 } 1661 1662 return; 1663 } 1664 1665 static void 1666 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1667 { 1668 struct dc_mediainfo *m; 1669 1670 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1671 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){ 1672 case DC_SIA_CODE_10BT: 1673 m->dc_media = IFM_10_T; 1674 break; 1675 1676 case DC_SIA_CODE_10BT_FDX: 1677 m->dc_media = IFM_10_T|IFM_FDX; 1678 break; 1679 1680 case DC_SIA_CODE_10B2: 1681 m->dc_media = IFM_10_2; 1682 break; 1683 1684 case DC_SIA_CODE_10B5: 1685 m->dc_media = IFM_10_5; 1686 break; 1687 } 1688 if (l->dc_sia_code & DC_SIA_CODE_EXT){ 1689 m->dc_gp_len = 2; 1690 m->dc_gp_ptr = 1691 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1692 } else { 1693 m->dc_gp_len = 2; 1694 m->dc_gp_ptr = 1695 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1696 } 1697 1698 m->dc_next = sc->dc_mi; 1699 sc->dc_mi = m; 1700 1701 sc->dc_pmode = DC_PMODE_SIA; 1702 1703 return; 1704 } 1705 1706 static void 1707 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1708 { 1709 struct dc_mediainfo *m; 1710 1711 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1712 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1713 m->dc_media = IFM_100_TX; 1714 1715 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1716 m->dc_media = IFM_100_TX|IFM_FDX; 1717 1718 m->dc_gp_len = 2; 1719 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1720 1721 m->dc_next = sc->dc_mi; 1722 sc->dc_mi = m; 1723 1724 sc->dc_pmode = DC_PMODE_SYM; 1725 1726 return; 1727 } 1728 1729 static void 1730 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1731 { 1732 u_int8_t *p; 1733 struct dc_mediainfo *m; 1734 1735 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1736 /* We abuse IFM_AUTO to represent MII. */ 1737 m->dc_media = IFM_AUTO; 1738 m->dc_gp_len = l->dc_gpr_len; 1739 1740 p = (u_int8_t *)l; 1741 p += sizeof(struct dc_eblock_mii); 1742 m->dc_gp_ptr = p; 1743 p += 2 * l->dc_gpr_len; 1744 m->dc_reset_len = *p; 1745 p++; 1746 m->dc_reset_ptr = p; 1747 1748 m->dc_next = sc->dc_mi; 1749 sc->dc_mi = m; 1750 1751 return; 1752 } 1753 1754 static void 1755 dc_read_srom(struct dc_softc *sc, int bits) 1756 { 1757 int size; 1758 1759 size = 2 << bits; 1760 sc->dc_srom = kmalloc(size, M_DEVBUF, M_INTWAIT); 1761 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1762 } 1763 1764 static void 1765 dc_parse_21143_srom(struct dc_softc *sc) 1766 { 1767 struct dc_leaf_hdr *lhdr; 1768 struct dc_eblock_hdr *hdr; 1769 int i, loff; 1770 char *ptr; 1771 int have_mii; 1772 1773 have_mii = 0; 1774 loff = sc->dc_srom[27]; 1775 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1776 1777 ptr = (char *)lhdr; 1778 ptr += sizeof(struct dc_leaf_hdr) - 1; 1779 /* 1780 * Look if we got a MII media block. 1781 */ 1782 for (i = 0; i < lhdr->dc_mcnt; i++) { 1783 hdr = (struct dc_eblock_hdr *)ptr; 1784 if (hdr->dc_type == DC_EBLOCK_MII) 1785 have_mii++; 1786 1787 ptr += (hdr->dc_len & 0x7F); 1788 ptr++; 1789 } 1790 1791 /* 1792 * Do the same thing again. Only use SIA and SYM media 1793 * blocks if no MII media block is available. 1794 */ 1795 ptr = (char *)lhdr; 1796 ptr += sizeof(struct dc_leaf_hdr) - 1; 1797 for (i = 0; i < lhdr->dc_mcnt; i++) { 1798 hdr = (struct dc_eblock_hdr *)ptr; 1799 switch(hdr->dc_type) { 1800 case DC_EBLOCK_MII: 1801 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1802 break; 1803 case DC_EBLOCK_SIA: 1804 if (! have_mii) 1805 dc_decode_leaf_sia(sc, 1806 (struct dc_eblock_sia *)hdr); 1807 break; 1808 case DC_EBLOCK_SYM: 1809 if (! have_mii) 1810 dc_decode_leaf_sym(sc, 1811 (struct dc_eblock_sym *)hdr); 1812 break; 1813 default: 1814 /* Don't care. Yet. */ 1815 break; 1816 } 1817 ptr += (hdr->dc_len & 0x7F); 1818 ptr++; 1819 } 1820 1821 return; 1822 } 1823 1824 /* 1825 * Attach the interface. Allocate softc structures, do ifmedia 1826 * setup and ethernet/BPF attach. 1827 */ 1828 static int 1829 dc_attach(device_t dev) 1830 { 1831 int tmp = 0; 1832 u_char eaddr[ETHER_ADDR_LEN]; 1833 u_int32_t command; 1834 struct dc_softc *sc; 1835 struct ifnet *ifp; 1836 u_int32_t revision; 1837 int error = 0, rid, mac_offset; 1838 uint8_t *mac; 1839 1840 sc = device_get_softc(dev); 1841 callout_init(&sc->dc_stat_timer); 1842 1843 ifp = &sc->arpcom.ac_if; 1844 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1845 1846 /* 1847 * Handle power management nonsense. 1848 */ 1849 dc_acpi(dev); 1850 1851 /* 1852 * Map control/status registers. 1853 */ 1854 pci_enable_busmaster(dev); 1855 1856 rid = DC_RID; 1857 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1858 1859 if (sc->dc_res == NULL) { 1860 device_printf(dev, "couldn't map ports/memory\n"); 1861 error = ENXIO; 1862 goto fail; 1863 } 1864 1865 sc->dc_btag = rman_get_bustag(sc->dc_res); 1866 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1867 1868 /* Allocate interrupt */ 1869 rid = 0; 1870 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1871 RF_SHAREABLE | RF_ACTIVE); 1872 1873 if (sc->dc_irq == NULL) { 1874 device_printf(dev, "couldn't map interrupt\n"); 1875 error = ENXIO; 1876 goto fail; 1877 } 1878 1879 revision = pci_get_revid(dev); 1880 1881 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1882 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1883 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1884 dc_eeprom_width(sc); 1885 1886 switch(sc->dc_info->dc_did) { 1887 case DC_DEVICEID_21143: 1888 sc->dc_type = DC_TYPE_21143; 1889 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1890 sc->dc_flags |= DC_REDUCED_MII_POLL; 1891 /* Save EEPROM contents so we can parse them later. */ 1892 dc_read_srom(sc, sc->dc_romwidth); 1893 break; 1894 case DC_DEVICEID_DM9009: 1895 case DC_DEVICEID_DM9100: 1896 case DC_DEVICEID_DM9102: 1897 sc->dc_type = DC_TYPE_DM9102; 1898 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1899 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1900 sc->dc_flags |= DC_TX_ALIGN; 1901 sc->dc_pmode = DC_PMODE_MII; 1902 /* Increase the latency timer value. */ 1903 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1904 command &= 0xFFFF00FF; 1905 command |= 0x00008000; 1906 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1907 break; 1908 case DC_DEVICEID_AL981: 1909 sc->dc_type = DC_TYPE_AL981; 1910 sc->dc_flags |= DC_TX_USE_TX_INTR; 1911 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1912 sc->dc_pmode = DC_PMODE_MII; 1913 dc_read_srom(sc, sc->dc_romwidth); 1914 break; 1915 case DC_DEVICEID_AN985: 1916 case DC_DEVICEID_ADM9511: 1917 case DC_DEVICEID_ADM9513: 1918 case DC_DEVICEID_FA511: 1919 case DC_DEVICEID_EN2242: 1920 case DC_DEVICEID_3CSOHOB: 1921 sc->dc_type = DC_TYPE_AN985; 1922 sc->dc_flags |= DC_64BIT_HASH; 1923 sc->dc_flags |= DC_TX_USE_TX_INTR; 1924 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1925 sc->dc_pmode = DC_PMODE_MII; 1926 break; 1927 case DC_DEVICEID_98713: 1928 case DC_DEVICEID_98713_CP: 1929 if (revision < DC_REVISION_98713A) { 1930 sc->dc_type = DC_TYPE_98713; 1931 } 1932 if (revision >= DC_REVISION_98713A) { 1933 sc->dc_type = DC_TYPE_98713A; 1934 sc->dc_flags |= DC_21143_NWAY; 1935 } 1936 sc->dc_flags |= DC_REDUCED_MII_POLL; 1937 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1938 break; 1939 case DC_DEVICEID_987x5: 1940 case DC_DEVICEID_EN1217: 1941 /* 1942 * Macronix MX98715AEC-C/D/E parts have only a 1943 * 128-bit hash table. We need to deal with these 1944 * in the same manner as the PNIC II so that we 1945 * get the right number of bits out of the 1946 * CRC routine. 1947 */ 1948 if (revision >= DC_REVISION_98715AEC_C && 1949 revision < DC_REVISION_98725) 1950 sc->dc_flags |= DC_128BIT_HASH; 1951 sc->dc_type = DC_TYPE_987x5; 1952 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1953 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1954 break; 1955 case DC_DEVICEID_98727: 1956 sc->dc_type = DC_TYPE_987x5; 1957 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1958 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1959 break; 1960 case DC_DEVICEID_82C115: 1961 sc->dc_type = DC_TYPE_PNICII; 1962 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1963 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1964 break; 1965 case DC_DEVICEID_82C168: 1966 sc->dc_type = DC_TYPE_PNIC; 1967 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1968 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1969 sc->dc_pnic_rx_buf = kmalloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1970 if (revision < DC_REVISION_82C169) 1971 sc->dc_pmode = DC_PMODE_SYM; 1972 break; 1973 case DC_DEVICEID_AX88140A: 1974 sc->dc_type = DC_TYPE_ASIX; 1975 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1976 sc->dc_flags |= DC_REDUCED_MII_POLL; 1977 sc->dc_pmode = DC_PMODE_MII; 1978 break; 1979 case DC_DEVICEID_RS7112: 1980 sc->dc_type = DC_TYPE_CONEXANT; 1981 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1982 sc->dc_flags |= DC_REDUCED_MII_POLL; 1983 sc->dc_pmode = DC_PMODE_MII; 1984 dc_read_srom(sc, sc->dc_romwidth); 1985 break; 1986 case DC_DEVICEID_X3201: 1987 sc->dc_type = DC_TYPE_XIRCOM; 1988 sc->dc_flags |= (DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1989 DC_TX_ALIGN); 1990 /* 1991 * We don't actually need to coalesce, but we're doing 1992 * it to obtain a double word aligned buffer. 1993 * The DC_TX_COALESCE flag is required. 1994 */ 1995 sc->dc_pmode = DC_PMODE_MII; 1996 break; 1997 default: 1998 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 1999 break; 2000 } 2001 2002 /* Save the cache line size. */ 2003 if (DC_IS_DAVICOM(sc)) 2004 sc->dc_cachesize = 0; 2005 else 2006 sc->dc_cachesize = pci_read_config(dev, 2007 DC_PCI_CFLT, 4) & 0xFF; 2008 2009 /* Reset the adapter. */ 2010 dc_reset(sc); 2011 2012 /* Take 21143 out of snooze mode */ 2013 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2014 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2015 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2016 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2017 } 2018 2019 /* 2020 * Try to learn something about the supported media. 2021 * We know that ASIX and ADMtek and Davicom devices 2022 * will *always* be using MII media, so that's a no-brainer. 2023 * The tricky ones are the Macronix/PNIC II and the 2024 * Intel 21143. 2025 */ 2026 if (DC_IS_INTEL(sc)) 2027 dc_parse_21143_srom(sc); 2028 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2029 if (sc->dc_type == DC_TYPE_98713) 2030 sc->dc_pmode = DC_PMODE_MII; 2031 else 2032 sc->dc_pmode = DC_PMODE_SYM; 2033 } else if (!sc->dc_pmode) 2034 sc->dc_pmode = DC_PMODE_MII; 2035 2036 /* 2037 * Get station address from the EEPROM. 2038 */ 2039 switch(sc->dc_type) { 2040 case DC_TYPE_98713: 2041 case DC_TYPE_98713A: 2042 case DC_TYPE_987x5: 2043 case DC_TYPE_PNICII: 2044 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2045 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2046 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2047 break; 2048 case DC_TYPE_PNIC: 2049 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2050 break; 2051 case DC_TYPE_DM9102: 2052 case DC_TYPE_21143: 2053 case DC_TYPE_ASIX: 2054 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2055 break; 2056 case DC_TYPE_AL981: 2057 case DC_TYPE_AN985: 2058 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0); 2059 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1); 2060 break; 2061 case DC_TYPE_CONEXANT: 2062 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2063 break; 2064 case DC_TYPE_XIRCOM: 2065 /* The MAC comes from the CIS */ 2066 mac = pci_get_ether(dev); 2067 if (!mac) { 2068 device_printf(dev, "No station address in CIS!\n"); 2069 error = ENXIO; 2070 goto fail; 2071 } 2072 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2073 break; 2074 default: 2075 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2076 break; 2077 } 2078 2079 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2080 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 2081 2082 if (sc->dc_ldata == NULL) { 2083 device_printf(dev, "no memory for list buffers!\n"); 2084 error = ENXIO; 2085 goto fail; 2086 } 2087 2088 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2089 2090 ifp->if_softc = sc; 2091 ifp->if_mtu = ETHERMTU; 2092 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2093 ifp->if_ioctl = dc_ioctl; 2094 ifp->if_start = dc_start; 2095 #ifdef DEVICE_POLLING 2096 ifp->if_poll = dc_poll; 2097 #endif 2098 ifp->if_watchdog = dc_watchdog; 2099 ifp->if_init = dc_init; 2100 ifp->if_baudrate = 10000000; 2101 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2102 ifq_set_ready(&ifp->if_snd); 2103 2104 /* 2105 * Do MII setup. If this is a 21143, check for a PHY on the 2106 * MII bus after applying any necessary fixups to twiddle the 2107 * GPIO bits. If we don't end up finding a PHY, restore the 2108 * old selection (SIA only or SIA/SYM) and attach the dcphy 2109 * driver instead. 2110 */ 2111 if (DC_IS_INTEL(sc)) { 2112 dc_apply_fixup(sc, IFM_AUTO); 2113 tmp = sc->dc_pmode; 2114 sc->dc_pmode = DC_PMODE_MII; 2115 } 2116 2117 /* 2118 * Setup General Purpose port mode and data so the tulip can talk 2119 * to the MII. This needs to be done before mii_phy_probe so that 2120 * we can actually see them. 2121 */ 2122 if (DC_IS_XIRCOM(sc)) { 2123 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2124 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2125 DELAY(10); 2126 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2127 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2128 DELAY(10); 2129 } 2130 2131 error = mii_phy_probe(dev, &sc->dc_miibus, 2132 dc_ifmedia_upd, dc_ifmedia_sts); 2133 2134 if (error && DC_IS_INTEL(sc)) { 2135 sc->dc_pmode = tmp; 2136 if (sc->dc_pmode != DC_PMODE_SIA) 2137 sc->dc_pmode = DC_PMODE_SYM; 2138 sc->dc_flags |= DC_21143_NWAY; 2139 mii_phy_probe(dev, &sc->dc_miibus, 2140 dc_ifmedia_upd, dc_ifmedia_sts); 2141 /* 2142 * For non-MII cards, we need to have the 21143 2143 * drive the LEDs. Except there are some systems 2144 * like the NEC VersaPro NoteBook PC which have no 2145 * LEDs, and twiddling these bits has adverse effects 2146 * on them. (I.e. you suddenly can't get a link.) 2147 */ 2148 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2149 sc->dc_flags |= DC_TULIP_LEDS; 2150 error = 0; 2151 } 2152 2153 if (error) { 2154 device_printf(dev, "MII without any PHY!\n"); 2155 error = ENXIO; 2156 goto fail; 2157 } 2158 2159 /* 2160 * Call MI attach routine. 2161 */ 2162 ether_ifattach(ifp, eaddr, NULL); 2163 2164 if (DC_IS_ADMTEK(sc)) { 2165 /* 2166 * Set automatic TX underrun recovery for the ADMtek chips 2167 */ 2168 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2169 } 2170 2171 /* 2172 * Tell the upper layer(s) we support long frames. 2173 */ 2174 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2175 2176 error = bus_setup_intr(dev, sc->dc_irq, INTR_NETSAFE, 2177 dc_intr, sc, &sc->dc_intrhand, 2178 ifp->if_serializer); 2179 if (error) { 2180 ether_ifdetach(ifp); 2181 device_printf(dev, "couldn't set up irq\n"); 2182 goto fail; 2183 } 2184 2185 return(0); 2186 2187 fail: 2188 dc_detach(dev); 2189 return(error); 2190 } 2191 2192 static int 2193 dc_detach(device_t dev) 2194 { 2195 struct dc_softc *sc = device_get_softc(dev); 2196 struct ifnet *ifp = &sc->arpcom.ac_if; 2197 struct dc_mediainfo *m; 2198 2199 if (device_is_attached(dev)) { 2200 lwkt_serialize_enter(ifp->if_serializer); 2201 dc_stop(sc); 2202 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2203 lwkt_serialize_exit(ifp->if_serializer); 2204 2205 ether_ifdetach(ifp); 2206 } 2207 2208 if (sc->dc_miibus) 2209 device_delete_child(dev, sc->dc_miibus); 2210 bus_generic_detach(dev); 2211 2212 if (sc->dc_irq) 2213 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2214 if (sc->dc_res) 2215 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2216 2217 if (sc->dc_ldata) 2218 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2219 if (sc->dc_pnic_rx_buf != NULL) 2220 kfree(sc->dc_pnic_rx_buf, M_DEVBUF); 2221 2222 while (sc->dc_mi != NULL) { 2223 m = sc->dc_mi->dc_next; 2224 kfree(sc->dc_mi, M_DEVBUF); 2225 sc->dc_mi = m; 2226 } 2227 2228 if (sc->dc_srom) 2229 kfree(sc->dc_srom, M_DEVBUF); 2230 2231 return(0); 2232 } 2233 2234 /* 2235 * Initialize the transmit descriptors. 2236 */ 2237 static int 2238 dc_list_tx_init(struct dc_softc *sc) 2239 { 2240 struct dc_chain_data *cd; 2241 struct dc_list_data *ld; 2242 int i; 2243 2244 cd = &sc->dc_cdata; 2245 ld = sc->dc_ldata; 2246 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2247 if (i == (DC_TX_LIST_CNT - 1)) { 2248 ld->dc_tx_list[i].dc_next = 2249 vtophys(&ld->dc_tx_list[0]); 2250 } else { 2251 ld->dc_tx_list[i].dc_next = 2252 vtophys(&ld->dc_tx_list[i + 1]); 2253 } 2254 cd->dc_tx_chain[i] = NULL; 2255 ld->dc_tx_list[i].dc_data = 0; 2256 ld->dc_tx_list[i].dc_ctl = 0; 2257 } 2258 2259 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2260 2261 return(0); 2262 } 2263 2264 2265 /* 2266 * Initialize the RX descriptors and allocate mbufs for them. Note that 2267 * we arrange the descriptors in a closed ring, so that the last descriptor 2268 * points back to the first. 2269 */ 2270 static int 2271 dc_list_rx_init(struct dc_softc *sc) 2272 { 2273 struct dc_chain_data *cd; 2274 struct dc_list_data *ld; 2275 int i; 2276 2277 cd = &sc->dc_cdata; 2278 ld = sc->dc_ldata; 2279 2280 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2281 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2282 return(ENOBUFS); 2283 if (i == (DC_RX_LIST_CNT - 1)) { 2284 ld->dc_rx_list[i].dc_next = 2285 vtophys(&ld->dc_rx_list[0]); 2286 } else { 2287 ld->dc_rx_list[i].dc_next = 2288 vtophys(&ld->dc_rx_list[i + 1]); 2289 } 2290 } 2291 2292 cd->dc_rx_prod = 0; 2293 2294 return(0); 2295 } 2296 2297 /* 2298 * Initialize an RX descriptor and attach an MBUF cluster. 2299 */ 2300 static int 2301 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) 2302 { 2303 struct mbuf *m_new = NULL; 2304 struct dc_desc *c; 2305 2306 c = &sc->dc_ldata->dc_rx_list[i]; 2307 2308 if (m == NULL) { 2309 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2310 if (m_new == NULL) 2311 return (ENOBUFS); 2312 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2313 } else { 2314 m_new = m; 2315 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2316 m_new->m_data = m_new->m_ext.ext_buf; 2317 } 2318 2319 m_adj(m_new, sizeof(u_int64_t)); 2320 2321 /* 2322 * If this is a PNIC chip, zero the buffer. This is part 2323 * of the workaround for the receive bug in the 82c168 and 2324 * 82c169 chips. 2325 */ 2326 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2327 bzero((char *)mtod(m_new, char *), m_new->m_len); 2328 2329 sc->dc_cdata.dc_rx_chain[i] = m_new; 2330 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2331 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2332 c->dc_status = DC_RXSTAT_OWN; 2333 2334 return(0); 2335 } 2336 2337 /* 2338 * Grrrrr. 2339 * The PNIC chip has a terrible bug in it that manifests itself during 2340 * periods of heavy activity. The exact mode of failure if difficult to 2341 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2342 * will happen on slow machines. The bug is that sometimes instead of 2343 * uploading one complete frame during reception, it uploads what looks 2344 * like the entire contents of its FIFO memory. The frame we want is at 2345 * the end of the whole mess, but we never know exactly how much data has 2346 * been uploaded, so salvaging the frame is hard. 2347 * 2348 * There is only one way to do it reliably, and it's disgusting. 2349 * Here's what we know: 2350 * 2351 * - We know there will always be somewhere between one and three extra 2352 * descriptors uploaded. 2353 * 2354 * - We know the desired received frame will always be at the end of the 2355 * total data upload. 2356 * 2357 * - We know the size of the desired received frame because it will be 2358 * provided in the length field of the status word in the last descriptor. 2359 * 2360 * Here's what we do: 2361 * 2362 * - When we allocate buffers for the receive ring, we bzero() them. 2363 * This means that we know that the buffer contents should be all 2364 * zeros, except for data uploaded by the chip. 2365 * 2366 * - We also force the PNIC chip to upload frames that include the 2367 * ethernet CRC at the end. 2368 * 2369 * - We gather all of the bogus frame data into a single buffer. 2370 * 2371 * - We then position a pointer at the end of this buffer and scan 2372 * backwards until we encounter the first non-zero byte of data. 2373 * This is the end of the received frame. We know we will encounter 2374 * some data at the end of the frame because the CRC will always be 2375 * there, so even if the sender transmits a packet of all zeros, 2376 * we won't be fooled. 2377 * 2378 * - We know the size of the actual received frame, so we subtract 2379 * that value from the current pointer location. This brings us 2380 * to the start of the actual received packet. 2381 * 2382 * - We copy this into an mbuf and pass it on, along with the actual 2383 * frame length. 2384 * 2385 * The performance hit is tremendous, but it beats dropping frames all 2386 * the time. 2387 */ 2388 2389 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2390 static void 2391 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2392 { 2393 struct dc_desc *cur_rx; 2394 struct dc_desc *c = NULL; 2395 struct mbuf *m = NULL; 2396 unsigned char *ptr; 2397 int i, total_len; 2398 u_int32_t rxstat = 0; 2399 2400 i = sc->dc_pnic_rx_bug_save; 2401 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2402 ptr = sc->dc_pnic_rx_buf; 2403 bzero(ptr, DC_RXLEN * 5); 2404 2405 /* Copy all the bytes from the bogus buffers. */ 2406 while (1) { 2407 c = &sc->dc_ldata->dc_rx_list[i]; 2408 rxstat = c->dc_status; 2409 m = sc->dc_cdata.dc_rx_chain[i]; 2410 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2411 ptr += DC_RXLEN; 2412 /* If this is the last buffer, break out. */ 2413 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2414 break; 2415 dc_newbuf(sc, i, m); 2416 DC_INC(i, DC_RX_LIST_CNT); 2417 } 2418 2419 /* Find the length of the actual receive frame. */ 2420 total_len = DC_RXBYTES(rxstat); 2421 2422 /* Scan backwards until we hit a non-zero byte. */ 2423 while(*ptr == 0x00) 2424 ptr--; 2425 2426 /* Round off. */ 2427 if ((uintptr_t)(ptr) & 0x3) 2428 ptr -= 1; 2429 2430 /* Now find the start of the frame. */ 2431 ptr -= total_len; 2432 if (ptr < sc->dc_pnic_rx_buf) 2433 ptr = sc->dc_pnic_rx_buf; 2434 2435 /* 2436 * Now copy the salvaged frame to the last mbuf and fake up 2437 * the status word to make it look like a successful 2438 * frame reception. 2439 */ 2440 dc_newbuf(sc, i, m); 2441 bcopy(ptr, mtod(m, char *), total_len); 2442 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2443 2444 return; 2445 } 2446 2447 /* 2448 * This routine searches the RX ring for dirty descriptors in the 2449 * event that the rxeof routine falls out of sync with the chip's 2450 * current descriptor pointer. This may happen sometimes as a result 2451 * of a "no RX buffer available" condition that happens when the chip 2452 * consumes all of the RX buffers before the driver has a chance to 2453 * process the RX ring. This routine may need to be called more than 2454 * once to bring the driver back in sync with the chip, however we 2455 * should still be getting RX DONE interrupts to drive the search 2456 * for new packets in the RX ring, so we should catch up eventually. 2457 */ 2458 static int 2459 dc_rx_resync(struct dc_softc *sc) 2460 { 2461 int i, pos; 2462 struct dc_desc *cur_rx; 2463 2464 pos = sc->dc_cdata.dc_rx_prod; 2465 2466 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2467 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2468 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2469 break; 2470 DC_INC(pos, DC_RX_LIST_CNT); 2471 } 2472 2473 /* If the ring really is empty, then just return. */ 2474 if (i == DC_RX_LIST_CNT) 2475 return(0); 2476 2477 /* We've fallen behing the chip: catch it. */ 2478 sc->dc_cdata.dc_rx_prod = pos; 2479 2480 return(EAGAIN); 2481 } 2482 2483 /* 2484 * A frame has been uploaded: pass the resulting mbuf chain up to 2485 * the higher level protocols. 2486 */ 2487 static void 2488 dc_rxeof(struct dc_softc *sc) 2489 { 2490 struct mbuf *m; 2491 struct ifnet *ifp; 2492 struct dc_desc *cur_rx; 2493 int i, total_len = 0; 2494 u_int32_t rxstat; 2495 2496 ifp = &sc->arpcom.ac_if; 2497 i = sc->dc_cdata.dc_rx_prod; 2498 2499 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2500 2501 #ifdef DEVICE_POLLING 2502 if (ifp->if_flags & IFF_POLLING) { 2503 if (sc->rxcycles <= 0) 2504 break; 2505 sc->rxcycles--; 2506 } 2507 #endif /* DEVICE_POLLING */ 2508 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2509 rxstat = cur_rx->dc_status; 2510 m = sc->dc_cdata.dc_rx_chain[i]; 2511 total_len = DC_RXBYTES(rxstat); 2512 2513 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2514 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2515 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2516 sc->dc_pnic_rx_bug_save = i; 2517 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2518 DC_INC(i, DC_RX_LIST_CNT); 2519 continue; 2520 } 2521 dc_pnic_rx_bug_war(sc, i); 2522 rxstat = cur_rx->dc_status; 2523 total_len = DC_RXBYTES(rxstat); 2524 } 2525 } 2526 2527 sc->dc_cdata.dc_rx_chain[i] = NULL; 2528 2529 /* 2530 * If an error occurs, update stats, clear the 2531 * status word and leave the mbuf cluster in place: 2532 * it should simply get re-used next time this descriptor 2533 * comes up in the ring. However, don't report long 2534 * frames as errors since they could be vlans 2535 */ 2536 if ((rxstat & DC_RXSTAT_RXERR)){ 2537 if (!(rxstat & DC_RXSTAT_GIANT) || 2538 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2539 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2540 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2541 ifp->if_ierrors++; 2542 if (rxstat & DC_RXSTAT_COLLSEEN) 2543 ifp->if_collisions++; 2544 dc_newbuf(sc, i, m); 2545 if (rxstat & DC_RXSTAT_CRCERR) { 2546 DC_INC(i, DC_RX_LIST_CNT); 2547 continue; 2548 } else { 2549 dc_init(sc); 2550 return; 2551 } 2552 } 2553 } 2554 2555 /* No errors; receive the packet. */ 2556 total_len -= ETHER_CRC_LEN; 2557 2558 #ifdef __i386__ 2559 /* 2560 * On the x86 we do not have alignment problems, so try to 2561 * allocate a new buffer for the receive ring, and pass up 2562 * the one where the packet is already, saving the expensive 2563 * copy done in m_devget(). 2564 * If we are on an architecture with alignment problems, or 2565 * if the allocation fails, then use m_devget and leave the 2566 * existing buffer in the receive ring. 2567 */ 2568 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2569 m->m_pkthdr.rcvif = ifp; 2570 m->m_pkthdr.len = m->m_len = total_len; 2571 DC_INC(i, DC_RX_LIST_CNT); 2572 } else 2573 #endif 2574 { 2575 struct mbuf *m0; 2576 2577 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2578 total_len + ETHER_ALIGN, 0, ifp, NULL); 2579 dc_newbuf(sc, i, m); 2580 DC_INC(i, DC_RX_LIST_CNT); 2581 if (m0 == NULL) { 2582 ifp->if_ierrors++; 2583 continue; 2584 } 2585 m_adj(m0, ETHER_ALIGN); 2586 m = m0; 2587 } 2588 2589 ifp->if_ipackets++; 2590 ifp->if_input(ifp, m); 2591 } 2592 2593 sc->dc_cdata.dc_rx_prod = i; 2594 } 2595 2596 /* 2597 * A frame was downloaded to the chip. It's safe for us to clean up 2598 * the list buffers. 2599 */ 2600 2601 static void 2602 dc_txeof(struct dc_softc *sc) 2603 { 2604 struct dc_desc *cur_tx = NULL; 2605 struct ifnet *ifp; 2606 int idx; 2607 2608 ifp = &sc->arpcom.ac_if; 2609 2610 /* 2611 * Go through our tx list and free mbufs for those 2612 * frames that have been transmitted. 2613 */ 2614 idx = sc->dc_cdata.dc_tx_cons; 2615 while(idx != sc->dc_cdata.dc_tx_prod) { 2616 u_int32_t txstat; 2617 2618 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2619 txstat = cur_tx->dc_status; 2620 2621 if (txstat & DC_TXSTAT_OWN) 2622 break; 2623 2624 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2625 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2626 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2627 /* 2628 * Yes, the PNIC is so brain damaged 2629 * that it will sometimes generate a TX 2630 * underrun error while DMAing the RX 2631 * filter setup frame. If we detect this, 2632 * we have to send the setup frame again, 2633 * or else the filter won't be programmed 2634 * correctly. 2635 */ 2636 if (DC_IS_PNIC(sc)) { 2637 if (txstat & DC_TXSTAT_ERRSUM) 2638 dc_setfilt(sc); 2639 } 2640 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2641 } 2642 sc->dc_cdata.dc_tx_cnt--; 2643 DC_INC(idx, DC_TX_LIST_CNT); 2644 continue; 2645 } 2646 2647 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2648 /* 2649 * XXX: Why does my Xircom taunt me so? 2650 * For some reason Conexant chips like 2651 * setting the CARRLOST flag even when 2652 * the carrier is there. In CURRENT we 2653 * have the same problem for Xircom 2654 * cards ! 2655 */ 2656 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2657 sc->dc_pmode == DC_PMODE_MII && 2658 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2659 DC_TXSTAT_NOCARRIER))) 2660 txstat &= ~DC_TXSTAT_ERRSUM; 2661 } else { 2662 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2663 sc->dc_pmode == DC_PMODE_MII && 2664 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2665 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2666 txstat &= ~DC_TXSTAT_ERRSUM; 2667 } 2668 2669 if (txstat & DC_TXSTAT_ERRSUM) { 2670 ifp->if_oerrors++; 2671 if (txstat & DC_TXSTAT_EXCESSCOLL) 2672 ifp->if_collisions++; 2673 if (txstat & DC_TXSTAT_LATECOLL) 2674 ifp->if_collisions++; 2675 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2676 dc_init(sc); 2677 return; 2678 } 2679 } 2680 2681 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2682 2683 ifp->if_opackets++; 2684 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2685 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2686 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2687 } 2688 2689 sc->dc_cdata.dc_tx_cnt--; 2690 DC_INC(idx, DC_TX_LIST_CNT); 2691 } 2692 2693 if (idx != sc->dc_cdata.dc_tx_cons) { 2694 /* some buffers have been freed */ 2695 sc->dc_cdata.dc_tx_cons = idx; 2696 ifp->if_flags &= ~IFF_OACTIVE; 2697 } 2698 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2699 2700 return; 2701 } 2702 2703 static void 2704 dc_tick(void *xsc) 2705 { 2706 struct dc_softc *sc = xsc; 2707 struct ifnet *ifp = &sc->arpcom.ac_if; 2708 struct mii_data *mii; 2709 u_int32_t r; 2710 2711 lwkt_serialize_enter(ifp->if_serializer); 2712 2713 mii = device_get_softc(sc->dc_miibus); 2714 2715 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2716 if (sc->dc_flags & DC_21143_NWAY) { 2717 r = CSR_READ_4(sc, DC_10BTSTAT); 2718 if (IFM_SUBTYPE(mii->mii_media_active) == 2719 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2720 sc->dc_link = 0; 2721 mii_mediachg(mii); 2722 } 2723 if (IFM_SUBTYPE(mii->mii_media_active) == 2724 IFM_10_T && (r & DC_TSTAT_LS10)) { 2725 sc->dc_link = 0; 2726 mii_mediachg(mii); 2727 } 2728 if (sc->dc_link == 0) 2729 mii_tick(mii); 2730 } else { 2731 r = CSR_READ_4(sc, DC_ISR); 2732 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2733 sc->dc_cdata.dc_tx_cnt == 0) { 2734 mii_tick(mii); 2735 if (!(mii->mii_media_status & IFM_ACTIVE)) 2736 sc->dc_link = 0; 2737 } 2738 } 2739 } else { 2740 mii_tick(mii); 2741 } 2742 2743 /* 2744 * When the init routine completes, we expect to be able to send 2745 * packets right away, and in fact the network code will send a 2746 * gratuitous ARP the moment the init routine marks the interface 2747 * as running. However, even though the MAC may have been initialized, 2748 * there may be a delay of a few seconds before the PHY completes 2749 * autonegotiation and the link is brought up. Any transmissions 2750 * made during that delay will be lost. Dealing with this is tricky: 2751 * we can't just pause in the init routine while waiting for the 2752 * PHY to come ready since that would bring the whole system to 2753 * a screeching halt for several seconds. 2754 * 2755 * What we do here is prevent the TX start routine from sending 2756 * any packets until a link has been established. After the 2757 * interface has been initialized, the tick routine will poll 2758 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2759 * that time, packets will stay in the send queue, and once the 2760 * link comes up, they will be flushed out to the wire. 2761 */ 2762 if (!sc->dc_link) { 2763 mii_pollstat(mii); 2764 if (mii->mii_media_status & IFM_ACTIVE && 2765 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2766 sc->dc_link++; 2767 if (!ifq_is_empty(&ifp->if_snd)) 2768 dc_start(ifp); 2769 } 2770 } 2771 2772 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2773 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2774 else 2775 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2776 2777 lwkt_serialize_exit(ifp->if_serializer); 2778 } 2779 2780 /* 2781 * A transmit underrun has occurred. Back off the transmit threshold, 2782 * or switch to store and forward mode if we have to. 2783 */ 2784 static void 2785 dc_tx_underrun(struct dc_softc *sc) 2786 { 2787 u_int32_t isr; 2788 int i; 2789 2790 if (DC_IS_DAVICOM(sc)) 2791 dc_init(sc); 2792 2793 if (DC_IS_INTEL(sc)) { 2794 /* 2795 * The real 21143 requires that the transmitter be idle 2796 * in order to change the transmit threshold or store 2797 * and forward state. 2798 */ 2799 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2800 2801 for (i = 0; i < DC_TIMEOUT; i++) { 2802 isr = CSR_READ_4(sc, DC_ISR); 2803 if (isr & DC_ISR_TX_IDLE) 2804 break; 2805 DELAY(10); 2806 } 2807 if (i == DC_TIMEOUT) { 2808 if_printf(&sc->arpcom.ac_if, 2809 "failed to force tx to idle state\n"); 2810 dc_init(sc); 2811 } 2812 } 2813 2814 if_printf(&sc->arpcom.ac_if, "TX underrun -- "); 2815 sc->dc_txthresh += DC_TXTHRESH_INC; 2816 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2817 kprintf("using store and forward mode\n"); 2818 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2819 } else { 2820 kprintf("increasing TX threshold\n"); 2821 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2822 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2823 } 2824 2825 if (DC_IS_INTEL(sc)) 2826 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2827 2828 return; 2829 } 2830 2831 #ifdef DEVICE_POLLING 2832 2833 static void 2834 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2835 { 2836 struct dc_softc *sc = ifp->if_softc; 2837 u_int32_t status; 2838 2839 switch(cmd) { 2840 case POLL_REGISTER: 2841 /* Disable interrupts */ 2842 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2843 break; 2844 case POLL_DEREGISTER: 2845 /* Re-enable interrupts. */ 2846 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2847 break; 2848 case POLL_ONLY: 2849 sc->rxcycles = count; 2850 dc_rxeof(sc); 2851 dc_txeof(sc); 2852 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2853 dc_start(ifp); 2854 break; 2855 case POLL_AND_CHECK_STATUS: 2856 sc->rxcycles = count; 2857 dc_rxeof(sc); 2858 dc_txeof(sc); 2859 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2860 dc_start(ifp); 2861 status = CSR_READ_4(sc, DC_ISR); 2862 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2863 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2864 DC_ISR_BUS_ERR); 2865 if (!status) 2866 break; 2867 /* ack what we have */ 2868 CSR_WRITE_4(sc, DC_ISR, status); 2869 2870 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2871 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2872 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2873 2874 if (dc_rx_resync(sc)) 2875 dc_rxeof(sc); 2876 } 2877 /* restart transmit unit if necessary */ 2878 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2879 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2880 2881 if (status & DC_ISR_TX_UNDERRUN) 2882 dc_tx_underrun(sc); 2883 2884 if (status & DC_ISR_BUS_ERR) { 2885 if_printf(ifp, "dc_poll: bus error\n"); 2886 dc_reset(sc); 2887 dc_init(sc); 2888 } 2889 break; 2890 } 2891 } 2892 #endif /* DEVICE_POLLING */ 2893 2894 static void 2895 dc_intr(void *arg) 2896 { 2897 struct dc_softc *sc; 2898 struct ifnet *ifp; 2899 u_int32_t status; 2900 2901 sc = arg; 2902 2903 if (sc->suspended) { 2904 return; 2905 } 2906 2907 ifp = &sc->arpcom.ac_if; 2908 2909 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2910 return ; 2911 2912 /* Suppress unwanted interrupts */ 2913 if (!(ifp->if_flags & IFF_UP)) { 2914 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2915 dc_stop(sc); 2916 return; 2917 } 2918 2919 /* Disable interrupts. */ 2920 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2921 2922 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 2923 status != 0xFFFFFFFF) { 2924 2925 CSR_WRITE_4(sc, DC_ISR, status); 2926 2927 if (status & DC_ISR_RX_OK) { 2928 int curpkts; 2929 curpkts = ifp->if_ipackets; 2930 dc_rxeof(sc); 2931 if (curpkts == ifp->if_ipackets) { 2932 while(dc_rx_resync(sc)) 2933 dc_rxeof(sc); 2934 } 2935 } 2936 2937 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2938 dc_txeof(sc); 2939 2940 if (status & DC_ISR_TX_IDLE) { 2941 dc_txeof(sc); 2942 if (sc->dc_cdata.dc_tx_cnt) { 2943 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2944 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2945 } 2946 } 2947 2948 if (status & DC_ISR_TX_UNDERRUN) 2949 dc_tx_underrun(sc); 2950 2951 if ((status & DC_ISR_RX_WATDOGTIMEO) 2952 || (status & DC_ISR_RX_NOBUF)) { 2953 int curpkts; 2954 curpkts = ifp->if_ipackets; 2955 dc_rxeof(sc); 2956 if (curpkts == ifp->if_ipackets) { 2957 while(dc_rx_resync(sc)) 2958 dc_rxeof(sc); 2959 } 2960 } 2961 2962 if (status & DC_ISR_BUS_ERR) { 2963 dc_reset(sc); 2964 dc_init(sc); 2965 } 2966 } 2967 2968 /* Re-enable interrupts. */ 2969 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2970 2971 if (!ifq_is_empty(&ifp->if_snd)) 2972 dc_start(ifp); 2973 2974 return; 2975 } 2976 2977 /* 2978 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2979 * pointers to the fragment pointers. 2980 */ 2981 static int 2982 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2983 { 2984 struct dc_desc *f = NULL; 2985 struct mbuf *m; 2986 int frag, cur, cnt = 0; 2987 2988 /* 2989 * Start packing the mbufs in this chain into 2990 * the fragment pointers. Stop when we run out 2991 * of fragments or hit the end of the mbuf chain. 2992 */ 2993 m = m_head; 2994 cur = frag = *txidx; 2995 2996 for (m = m_head; m != NULL; m = m->m_next) { 2997 if (m->m_len != 0) { 2998 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2999 if (*txidx != sc->dc_cdata.dc_tx_prod && 3000 frag == (DC_TX_LIST_CNT - 1)) 3001 return(ENOBUFS); 3002 } 3003 if ((DC_TX_LIST_CNT - 3004 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3005 return(ENOBUFS); 3006 3007 f = &sc->dc_ldata->dc_tx_list[frag]; 3008 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3009 if (cnt == 0) { 3010 f->dc_status = 0; 3011 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3012 } else 3013 f->dc_status = DC_TXSTAT_OWN; 3014 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3015 cur = frag; 3016 DC_INC(frag, DC_TX_LIST_CNT); 3017 cnt++; 3018 } 3019 } 3020 3021 if (m != NULL) 3022 return(ENOBUFS); 3023 3024 sc->dc_cdata.dc_tx_cnt += cnt; 3025 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3026 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3027 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3028 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3029 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3030 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3031 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3032 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3033 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3034 *txidx = frag; 3035 3036 return(0); 3037 } 3038 3039 /* 3040 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3041 * to the mbuf data regions directly in the transmit lists. We also save a 3042 * copy of the pointers since the transmit list fragment pointers are 3043 * physical addresses. 3044 */ 3045 3046 static void 3047 dc_start(struct ifnet *ifp) 3048 { 3049 struct dc_softc *sc; 3050 struct mbuf *m_head; 3051 struct mbuf *m_defragged; 3052 int idx, need_trans; 3053 3054 sc = ifp->if_softc; 3055 3056 if (!sc->dc_link) 3057 return; 3058 3059 if (ifp->if_flags & IFF_OACTIVE) 3060 return; 3061 3062 idx = sc->dc_cdata.dc_tx_prod; 3063 3064 need_trans = 0; 3065 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3066 m_defragged = NULL; 3067 m_head = ifq_poll(&ifp->if_snd); 3068 if (m_head == NULL) 3069 break; 3070 3071 if (sc->dc_flags & DC_TX_COALESCE && 3072 (m_head->m_next != NULL || 3073 sc->dc_flags & DC_TX_ALIGN)){ 3074 /* 3075 * Check first if coalescing allows us to queue 3076 * the packet. We don't want to loose it if 3077 * the TX queue is full. 3078 */ 3079 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3080 idx != sc->dc_cdata.dc_tx_prod && 3081 idx == (DC_TX_LIST_CNT - 1)) { 3082 ifp->if_flags |= IFF_OACTIVE; 3083 break; 3084 } 3085 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { 3086 ifp->if_flags |= IFF_OACTIVE; 3087 break; 3088 } 3089 3090 /* only coalesce if have >1 mbufs */ 3091 m_defragged = m_defrag_nofree(m_head, MB_DONTWAIT); 3092 if (m_defragged == NULL) { 3093 ifp->if_flags |= IFF_OACTIVE; 3094 break; 3095 } 3096 } 3097 3098 if (dc_encap(sc, (m_defragged ? m_defragged : m_head), &idx)) { 3099 if (m_defragged) { 3100 /* 3101 * Throw away the original packet if the 3102 * defragged packet could not be encapsulated, 3103 * as well as the defragged packet. 3104 */ 3105 ifq_dequeue(&ifp->if_snd, m_head); 3106 m_freem(m_head); 3107 m_freem(m_defragged); 3108 } 3109 ifp->if_flags |= IFF_OACTIVE; 3110 break; 3111 } 3112 3113 ifq_dequeue(&ifp->if_snd, m_head); 3114 3115 need_trans = 1; 3116 3117 /* 3118 * If there's a BPF listener, bounce a copy of this frame 3119 * to him. 3120 */ 3121 BPF_MTAP(ifp, (m_defragged ? m_defragged : m_head)); 3122 3123 /* 3124 * If we defragged the packet, m_head is not the one we 3125 * encapsulated so we can throw it away. 3126 */ 3127 if (m_defragged) 3128 m_freem(m_head); 3129 3130 if (sc->dc_flags & DC_TX_ONE) { 3131 ifp->if_flags |= IFF_OACTIVE; 3132 break; 3133 } 3134 } 3135 3136 if (!need_trans) 3137 return; 3138 3139 /* Transmit */ 3140 sc->dc_cdata.dc_tx_prod = idx; 3141 if (!(sc->dc_flags & DC_TX_POLL)) 3142 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3143 3144 /* 3145 * Set a timeout in case the chip goes out to lunch. 3146 */ 3147 ifp->if_timer = 5; 3148 } 3149 3150 static void 3151 dc_init(void *xsc) 3152 { 3153 struct dc_softc *sc = xsc; 3154 struct ifnet *ifp = &sc->arpcom.ac_if; 3155 struct mii_data *mii; 3156 3157 mii = device_get_softc(sc->dc_miibus); 3158 3159 /* 3160 * Cancel pending I/O and free all RX/TX buffers. 3161 */ 3162 dc_stop(sc); 3163 dc_reset(sc); 3164 3165 /* 3166 * Set cache alignment and burst length. 3167 */ 3168 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3169 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3170 else 3171 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3172 /* 3173 * Evenly share the bus between receive and transmit process. 3174 */ 3175 if (DC_IS_INTEL(sc)) 3176 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3177 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3178 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3179 } else { 3180 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3181 } 3182 if (sc->dc_flags & DC_TX_POLL) 3183 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3184 switch(sc->dc_cachesize) { 3185 case 32: 3186 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3187 break; 3188 case 16: 3189 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3190 break; 3191 case 8: 3192 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3193 break; 3194 case 0: 3195 default: 3196 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3197 break; 3198 } 3199 3200 if (sc->dc_flags & DC_TX_STORENFWD) 3201 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3202 else { 3203 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3204 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3205 } else { 3206 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3207 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3208 } 3209 } 3210 3211 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3212 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3213 3214 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3215 /* 3216 * The app notes for the 98713 and 98715A say that 3217 * in order to have the chips operate properly, a magic 3218 * number must be written to CSR16. Macronix does not 3219 * document the meaning of these bits so there's no way 3220 * to know exactly what they do. The 98713 has a magic 3221 * number all its own; the rest all use a different one. 3222 */ 3223 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3224 if (sc->dc_type == DC_TYPE_98713) 3225 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3226 else 3227 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3228 } 3229 3230 if (DC_IS_XIRCOM(sc)) { 3231 /* 3232 * Setup General Purpose Port mode and data so the tulip 3233 * can talk to the MII. 3234 */ 3235 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3236 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3237 DELAY(10); 3238 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3239 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3240 DELAY(10); 3241 } 3242 3243 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3244 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3245 3246 /* Init circular RX list. */ 3247 if (dc_list_rx_init(sc) == ENOBUFS) { 3248 if_printf(ifp, "initialization failed: no " 3249 "memory for rx buffers\n"); 3250 dc_stop(sc); 3251 return; 3252 } 3253 3254 /* 3255 * Init tx descriptors. 3256 */ 3257 dc_list_tx_init(sc); 3258 3259 /* 3260 * Load the address of the RX list. 3261 */ 3262 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3263 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3264 3265 /* 3266 * Enable interrupts. 3267 */ 3268 #ifdef DEVICE_POLLING 3269 /* 3270 * ... but only if we are not polling, and make sure they are off in 3271 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3272 * after a reset. 3273 */ 3274 if (ifp->if_flags & IFF_POLLING) 3275 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3276 else 3277 #endif 3278 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3279 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3280 3281 /* Enable transmitter. */ 3282 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3283 3284 /* 3285 * If this is an Intel 21143 and we're not using the 3286 * MII port, program the LED control pins so we get 3287 * link and activity indications. 3288 */ 3289 if (sc->dc_flags & DC_TULIP_LEDS) { 3290 CSR_WRITE_4(sc, DC_WATCHDOG, 3291 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3292 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3293 } 3294 3295 /* 3296 * Load the RX/multicast filter. We do this sort of late 3297 * because the filter programming scheme on the 21143 and 3298 * some clones requires DMAing a setup frame via the TX 3299 * engine, and we need the transmitter enabled for that. 3300 */ 3301 dc_setfilt(sc); 3302 3303 /* Enable receiver. */ 3304 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3305 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3306 3307 mii_mediachg(mii); 3308 dc_setcfg(sc, sc->dc_if_media); 3309 3310 ifp->if_flags |= IFF_RUNNING; 3311 ifp->if_flags &= ~IFF_OACTIVE; 3312 3313 /* Don't start the ticker if this is a homePNA link. */ 3314 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3315 sc->dc_link = 1; 3316 else { 3317 if (sc->dc_flags & DC_21143_NWAY) 3318 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3319 else 3320 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3321 } 3322 3323 return; 3324 } 3325 3326 /* 3327 * Set media options. 3328 */ 3329 static int 3330 dc_ifmedia_upd(struct ifnet *ifp) 3331 { 3332 struct dc_softc *sc; 3333 struct mii_data *mii; 3334 struct ifmedia *ifm; 3335 3336 sc = ifp->if_softc; 3337 mii = device_get_softc(sc->dc_miibus); 3338 mii_mediachg(mii); 3339 ifm = &mii->mii_media; 3340 3341 if (DC_IS_DAVICOM(sc) && 3342 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3343 dc_setcfg(sc, ifm->ifm_media); 3344 else 3345 sc->dc_link = 0; 3346 3347 return(0); 3348 } 3349 3350 /* 3351 * Report current media status. 3352 */ 3353 static void 3354 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3355 { 3356 struct dc_softc *sc; 3357 struct mii_data *mii; 3358 struct ifmedia *ifm; 3359 3360 sc = ifp->if_softc; 3361 mii = device_get_softc(sc->dc_miibus); 3362 mii_pollstat(mii); 3363 ifm = &mii->mii_media; 3364 if (DC_IS_DAVICOM(sc)) { 3365 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3366 ifmr->ifm_active = ifm->ifm_media; 3367 ifmr->ifm_status = 0; 3368 return; 3369 } 3370 } 3371 ifmr->ifm_active = mii->mii_media_active; 3372 ifmr->ifm_status = mii->mii_media_status; 3373 3374 return; 3375 } 3376 3377 static int 3378 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3379 { 3380 struct dc_softc *sc = ifp->if_softc; 3381 struct ifreq *ifr = (struct ifreq *) data; 3382 struct mii_data *mii; 3383 int error = 0; 3384 3385 switch(command) { 3386 case SIOCSIFFLAGS: 3387 if (ifp->if_flags & IFF_UP) { 3388 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3389 (IFF_PROMISC | IFF_ALLMULTI); 3390 if (ifp->if_flags & IFF_RUNNING) { 3391 if (need_setfilt) 3392 dc_setfilt(sc); 3393 } else { 3394 sc->dc_txthresh = 0; 3395 dc_init(sc); 3396 } 3397 } else { 3398 if (ifp->if_flags & IFF_RUNNING) 3399 dc_stop(sc); 3400 } 3401 sc->dc_if_flags = ifp->if_flags; 3402 error = 0; 3403 break; 3404 case SIOCADDMULTI: 3405 case SIOCDELMULTI: 3406 dc_setfilt(sc); 3407 error = 0; 3408 break; 3409 case SIOCGIFMEDIA: 3410 case SIOCSIFMEDIA: 3411 mii = device_get_softc(sc->dc_miibus); 3412 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3413 break; 3414 default: 3415 error = ether_ioctl(ifp, command, data); 3416 break; 3417 } 3418 3419 return(error); 3420 } 3421 3422 static void 3423 dc_watchdog(struct ifnet *ifp) 3424 { 3425 struct dc_softc *sc; 3426 3427 sc = ifp->if_softc; 3428 3429 ifp->if_oerrors++; 3430 if_printf(ifp, "watchdog timeout\n"); 3431 3432 dc_stop(sc); 3433 dc_reset(sc); 3434 dc_init(sc); 3435 3436 if (!ifq_is_empty(&ifp->if_snd)) 3437 dc_start(ifp); 3438 3439 return; 3440 } 3441 3442 /* 3443 * Stop the adapter and free any mbufs allocated to the 3444 * RX and TX lists. 3445 */ 3446 static void 3447 dc_stop(struct dc_softc *sc) 3448 { 3449 int i; 3450 struct ifnet *ifp; 3451 3452 ifp = &sc->arpcom.ac_if; 3453 ifp->if_timer = 0; 3454 3455 callout_stop(&sc->dc_stat_timer); 3456 3457 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3458 3459 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3460 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3461 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3462 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3463 sc->dc_link = 0; 3464 3465 /* 3466 * Free data in the RX lists. 3467 */ 3468 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3469 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3470 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3471 sc->dc_cdata.dc_rx_chain[i] = NULL; 3472 } 3473 } 3474 bzero((char *)&sc->dc_ldata->dc_rx_list, 3475 sizeof(sc->dc_ldata->dc_rx_list)); 3476 3477 /* 3478 * Free the TX list buffers. 3479 */ 3480 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3481 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3482 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3483 DC_TXCTL_SETUP) || 3484 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3485 DC_TXCTL_LASTFRAG)) { 3486 sc->dc_cdata.dc_tx_chain[i] = NULL; 3487 continue; 3488 } 3489 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3490 sc->dc_cdata.dc_tx_chain[i] = NULL; 3491 } 3492 } 3493 3494 bzero((char *)&sc->dc_ldata->dc_tx_list, 3495 sizeof(sc->dc_ldata->dc_tx_list)); 3496 3497 return; 3498 } 3499 3500 /* 3501 * Stop all chip I/O so that the kernel's probe routines don't 3502 * get confused by errant DMAs when rebooting. 3503 */ 3504 static void 3505 dc_shutdown(device_t dev) 3506 { 3507 struct dc_softc *sc; 3508 struct ifnet *ifp; 3509 3510 sc = device_get_softc(dev); 3511 ifp = &sc->arpcom.ac_if; 3512 lwkt_serialize_enter(ifp->if_serializer); 3513 3514 dc_stop(sc); 3515 3516 lwkt_serialize_exit(ifp->if_serializer); 3517 } 3518 3519 /* 3520 * Device suspend routine. Stop the interface and save some PCI 3521 * settings in case the BIOS doesn't restore them properly on 3522 * resume. 3523 */ 3524 static int 3525 dc_suspend(device_t dev) 3526 { 3527 struct dc_softc *sc = device_get_softc(dev); 3528 struct ifnet *ifp = &sc->arpcom.ac_if; 3529 int i; 3530 lwkt_serialize_enter(ifp->if_serializer); 3531 3532 dc_stop(sc); 3533 for (i = 0; i < 5; i++) 3534 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3535 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3536 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3537 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3538 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3539 3540 sc->suspended = 1; 3541 3542 lwkt_serialize_exit(ifp->if_serializer); 3543 return (0); 3544 } 3545 3546 /* 3547 * Device resume routine. Restore some PCI settings in case the BIOS 3548 * doesn't, re-enable busmastering, and restart the interface if 3549 * appropriate. 3550 */ 3551 static int 3552 dc_resume(device_t dev) 3553 { 3554 struct dc_softc *sc = device_get_softc(dev); 3555 struct ifnet *ifp = &sc->arpcom.ac_if; 3556 int i; 3557 3558 lwkt_serialize_enter(ifp->if_serializer); 3559 dc_acpi(dev); 3560 3561 /* better way to do this? */ 3562 for (i = 0; i < 5; i++) 3563 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3564 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3565 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3566 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3567 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3568 3569 /* reenable busmastering */ 3570 pci_enable_busmaster(dev); 3571 pci_enable_io(dev, DC_RES); 3572 3573 /* reinitialize interface if necessary */ 3574 if (ifp->if_flags & IFF_UP) 3575 dc_init(sc); 3576 3577 sc->suspended = 0; 3578 lwkt_serialize_exit(ifp->if_serializer); 3579 3580 return (0); 3581 } 3582 3583 static uint32_t 3584 dc_mchash_xircom(struct dc_softc *sc, const uint8_t *addr) 3585 { 3586 uint32_t crc; 3587 3588 /* Compute CRC for the address value. */ 3589 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 3590 3591 if ((crc & 0x180) == 0x180) 3592 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 3593 else 3594 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + (12 << 4)); 3595 } 3596