1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dcreg.h,v 1.4.2.22 2003/06/07 16:55:35 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dcreg.h,v 1.3 2004/09/14 22:44:46 joerg Exp $ 34 */ 35 36 /* 37 * 21143 and clone common register definitions. 38 */ 39 40 #define DC_BUSCTL 0x00 /* bus control */ 41 #define DC_TXSTART 0x08 /* tx start demand */ 42 #define DC_RXSTART 0x10 /* rx start demand */ 43 #define DC_RXADDR 0x18 /* rx descriptor list start addr */ 44 #define DC_TXADDR 0x20 /* tx descriptor list start addr */ 45 #define DC_ISR 0x28 /* interrupt status register */ 46 #define DC_NETCFG 0x30 /* network config register */ 47 #define DC_IMR 0x38 /* interrupt mask */ 48 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 49 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 50 #define DC_ROM 0x50 /* ROM programming address */ 51 #define DC_TIMER 0x58 /* general timer */ 52 #define DC_10BTSTAT 0x60 /* SIA status */ 53 #define DC_SIARESET 0x68 /* SIA connectivity */ 54 #define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 55 #define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 56 57 /* 58 * There are two general 'types' of MX chips that we need to be 59 * concerned with. One is the original 98713, which has its internal 60 * NWAY support controlled via the MDIO bits in the serial I/O 61 * register. The other is everything else (from the 98713A on up), 62 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 63 * just like the 21143. This type setting also governs which of the 64 * 'magic' numbers we write to CSR16. The PNIC II falls into the 65 * 98713A/98715/98715A/98725 category. 66 */ 67 #define DC_TYPE_98713 0x1 68 #define DC_TYPE_98713A 0x2 69 #define DC_TYPE_987x5 0x3 70 71 /* Other type of supported chips. */ 72 #define DC_TYPE_21143 0x4 /* Intel 21143 */ 73 #define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 74 #define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 75 #define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ 76 #define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 77 #define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 78 #define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 79 #define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ 80 81 #define DC_IS_MACRONIX(x) \ 82 (x->dc_type == DC_TYPE_98713 || \ 83 x->dc_type == DC_TYPE_98713A || \ 84 x->dc_type == DC_TYPE_987x5) 85 86 #define DC_IS_ADMTEK(x) \ 87 (x->dc_type == DC_TYPE_AL981 || \ 88 x->dc_type == DC_TYPE_AN985) 89 90 #define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 91 #define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 92 #define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 93 #define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) 94 #define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 95 #define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 96 #define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 97 #define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) 98 99 /* MII/symbol mode port types */ 100 #define DC_PMODE_MII 0x1 101 #define DC_PMODE_SYM 0x2 102 #define DC_PMODE_SIA 0x3 103 104 /* 105 * Bus control bits. 106 */ 107 #define DC_BUSCTL_RESET 0x00000001 108 #define DC_BUSCTL_ARBITRATION 0x00000002 109 #define DC_BUSCTL_SKIPLEN 0x0000007C 110 #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 111 #define DC_BUSCTL_BURSTLEN 0x00003F00 112 #define DC_BUSCTL_CACHEALIGN 0x0000C000 113 #define DC_BUSCTL_TXPOLL 0x000E0000 114 #define DC_BUSCTL_DBO 0x00100000 115 #define DC_BUSCTL_MRME 0x00200000 116 #define DC_BUSCTL_MRLE 0x00800000 117 #define DC_BUSCTL_MWIE 0x01000000 118 #define DC_BUSCTL_ONNOW_ENB 0x04000000 119 120 #define DC_SKIPLEN_1LONG 0x00000004 121 #define DC_SKIPLEN_2LONG 0x00000008 122 #define DC_SKIPLEN_3LONG 0x00000010 123 #define DC_SKIPLEN_4LONG 0x00000020 124 #define DC_SKIPLEN_5LONG 0x00000040 125 126 #define DC_CACHEALIGN_NONE 0x00000000 127 #define DC_CACHEALIGN_8LONG 0x00004000 128 #define DC_CACHEALIGN_16LONG 0x00008000 129 #define DC_CACHEALIGN_32LONG 0x0000C000 130 131 #define DC_BURSTLEN_USECA 0x00000000 132 #define DC_BURSTLEN_1LONG 0x00000100 133 #define DC_BURSTLEN_2LONG 0x00000200 134 #define DC_BURSTLEN_4LONG 0x00000400 135 #define DC_BURSTLEN_8LONG 0x00000800 136 #define DC_BURSTLEN_16LONG 0x00001000 137 #define DC_BURSTLEN_32LONG 0x00002000 138 139 #define DC_TXPOLL_OFF 0x00000000 140 #define DC_TXPOLL_1 0x00020000 141 #define DC_TXPOLL_2 0x00040000 142 #define DC_TXPOLL_3 0x00060000 143 #define DC_TXPOLL_4 0x00080000 144 #define DC_TXPOLL_5 0x000A0000 145 #define DC_TXPOLL_6 0x000C0000 146 #define DC_TXPOLL_7 0x000E0000 147 148 /* 149 * Interrupt status bits. 150 */ 151 #define DC_ISR_TX_OK 0x00000001 152 #define DC_ISR_TX_IDLE 0x00000002 153 #define DC_ISR_TX_NOBUF 0x00000004 154 #define DC_ISR_TX_JABBERTIMEO 0x00000008 155 #define DC_ISR_LINKGOOD 0x00000010 156 #define DC_ISR_TX_UNDERRUN 0x00000020 157 #define DC_ISR_RX_OK 0x00000040 158 #define DC_ISR_RX_NOBUF 0x00000080 159 #define DC_ISR_RX_READ 0x00000100 160 #define DC_ISR_RX_WATDOGTIMEO 0x00000200 161 #define DC_ISR_TX_EARLY 0x00000400 162 #define DC_ISR_TIMER_EXPIRED 0x00000800 163 #define DC_ISR_LINKFAIL 0x00001000 164 #define DC_ISR_BUS_ERR 0x00002000 165 #define DC_ISR_RX_EARLY 0x00004000 166 #define DC_ISR_ABNORMAL 0x00008000 167 #define DC_ISR_NORMAL 0x00010000 168 #define DC_ISR_RX_STATE 0x000E0000 169 #define DC_ISR_TX_STATE 0x00700000 170 #define DC_ISR_BUSERRTYPE 0x03800000 171 #define DC_ISR_100MBPSLINK 0x08000000 172 #define DC_ISR_MAGICKPACK 0x10000000 173 174 #define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 175 #define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 176 #define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 177 #define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 178 #define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 179 #define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 180 #define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 181 #define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 182 183 #define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 184 #define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 185 #define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 186 #define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 187 #define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 188 #define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 189 #define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 190 #define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 191 192 /* 193 * Network config bits. 194 */ 195 #define DC_NETCFG_RX_HASHPERF 0x00000001 196 #define DC_NETCFG_RX_ON 0x00000002 197 #define DC_NETCFG_RX_HASHONLY 0x00000004 198 #define DC_NETCFG_RX_BADFRAMES 0x00000008 199 #define DC_NETCFG_RX_INVFILT 0x00000010 200 #define DC_NETCFG_BACKOFFCNT 0x00000020 201 #define DC_NETCFG_RX_PROMISC 0x00000040 202 #define DC_NETCFG_RX_ALLMULTI 0x00000080 203 #define DC_NETCFG_FULLDUPLEX 0x00000200 204 #define DC_NETCFG_LOOPBACK 0x00000C00 205 #define DC_NETCFG_FORCECOLL 0x00001000 206 #define DC_NETCFG_TX_ON 0x00002000 207 #define DC_NETCFG_TX_THRESH 0x0000C000 208 #define DC_NETCFG_TX_BACKOFF 0x00020000 209 #define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 210 #define DC_NETCFG_HEARTBEAT 0x00080000 211 #define DC_NETCFG_STORENFWD 0x00200000 212 #define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 213 #define DC_NETCFG_PCS 0x00800000 214 #define DC_NETCFG_SCRAMBLER 0x01000000 215 #define DC_NETCFG_NO_RXCRC 0x02000000 216 #define DC_NETCFG_RX_ALL 0x40000000 217 #define DC_NETCFG_CAPEFFECT 0x80000000 218 219 #define DC_OPMODE_NORM 0x00000000 220 #define DC_OPMODE_INTLOOP 0x00000400 221 #define DC_OPMODE_EXTLOOP 0x00000800 222 223 #if 0 224 #define DC_TXTHRESH_72BYTES 0x00000000 225 #define DC_TXTHRESH_96BYTES 0x00004000 226 #define DC_TXTHRESH_128BYTES 0x00008000 227 #define DC_TXTHRESH_160BYTES 0x0000C000 228 #endif 229 230 #define DC_TXTHRESH_MIN 0x00000000 231 #define DC_TXTHRESH_INC 0x00004000 232 #define DC_TXTHRESH_MAX 0x0000C000 233 234 235 /* 236 * Interrupt mask bits. 237 */ 238 #define DC_IMR_TX_OK 0x00000001 239 #define DC_IMR_TX_IDLE 0x00000002 240 #define DC_IMR_TX_NOBUF 0x00000004 241 #define DC_IMR_TX_JABBERTIMEO 0x00000008 242 #define DC_IMR_LINKGOOD 0x00000010 243 #define DC_IMR_TX_UNDERRUN 0x00000020 244 #define DC_IMR_RX_OK 0x00000040 245 #define DC_IMR_RX_NOBUF 0x00000080 246 #define DC_IMR_RX_READ 0x00000100 247 #define DC_IMR_RX_WATDOGTIMEO 0x00000200 248 #define DC_IMR_TX_EARLY 0x00000400 249 #define DC_IMR_TIMER_EXPIRED 0x00000800 250 #define DC_IMR_LINKFAIL 0x00001000 251 #define DC_IMR_BUS_ERR 0x00002000 252 #define DC_IMR_RX_EARLY 0x00004000 253 #define DC_IMR_ABNORMAL 0x00008000 254 #define DC_IMR_NORMAL 0x00010000 255 #define DC_IMR_100MBPSLINK 0x08000000 256 #define DC_IMR_MAGICKPACK 0x10000000 257 258 #define DC_INTRS \ 259 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 260 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 261 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 262 /* 263 * Serial I/O (EEPROM/ROM) bits. 264 */ 265 #define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 266 #define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 267 #define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 268 #define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 269 #define DC_SIO_ROMDATA4 0x00000010 270 #define DC_SIO_ROMDATA5 0x00000020 271 #define DC_SIO_ROMDATA6 0x00000040 272 #define DC_SIO_ROMDATA7 0x00000080 273 #define DC_SIO_EESEL 0x00000800 274 #define DC_SIO_ROMSEL 0x00001000 275 #define DC_SIO_ROMCTL_WRITE 0x00002000 276 #define DC_SIO_ROMCTL_READ 0x00004000 277 #define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 278 #define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 279 #define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 280 #define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 281 282 #define DC_EECMD_WRITE 0x140 283 #define DC_EECMD_READ 0x180 284 #define DC_EECMD_ERASE 0x1c0 285 286 #define DC_EE_NODEADDR_OFFSET 0x70 287 #define DC_EE_NODEADDR 10 288 289 /* 290 * General purpose timer register 291 */ 292 #define DC_TIMER_VALUE 0x0000FFFF 293 #define DC_TIMER_CONTINUOUS 0x00010000 294 295 /* 296 * 10baseT status register 297 */ 298 #define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 299 #define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 300 #define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 301 #define DC_TSTAT_AUTOPOLARITY 0x00000008 302 #define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 303 #define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 304 #define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 305 #define DC_TSTAT_REMFAULT 0x00000800 306 #define DC_TSTAT_ANEGSTAT 0x00007000 307 #define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 308 #define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 309 310 #define DC_ASTAT_DISABLE 0x00000000 311 #define DC_ASTAT_TXDISABLE 0x00001000 312 #define DC_ASTAT_ABDETECT 0x00002000 313 #define DC_ASTAT_ACKDETECT 0x00003000 314 #define DC_ASTAT_CMPACKDETECT 0x00004000 315 #define DC_ASTAT_AUTONEGCMP 0x00005000 316 #define DC_ASTAT_LINKCHECK 0x00006000 317 318 /* 319 * PHY reset register 320 */ 321 #define DC_SIA_RESET 0x00000001 322 #define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 323 324 /* 325 * 10baseT control register 326 */ 327 #define DC_TCTL_ENCODER_ENB 0x00000001 328 #define DC_TCTL_LOOPBACK 0x00000002 329 #define DC_TCTL_DRIVER_ENB 0x00000004 330 #define DC_TCTL_LNKPULSE_ENB 0x00000008 331 #define DC_TCTL_HALFDUPLEX 0x00000040 332 #define DC_TCTL_AUTONEGENBL 0x00000080 333 #define DC_TCTL_RX_SQUELCH 0x00000100 334 #define DC_TCTL_COLL_SQUELCH 0x00000200 335 #define DC_TCTL_COLL_DETECT 0x00000400 336 #define DC_TCTL_SQE_ENB 0x00000800 337 #define DC_TCTL_LINKTEST 0x00001000 338 #define DC_TCTL_AUTOPOLARITY 0x00002000 339 #define DC_TCTL_SET_POL_PLUS 0x00004000 340 #define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 341 #define DC_TCTL_100BTXHALF 0x00010000 342 #define DC_TCTL_100BTXFULL 0x00020000 343 #define DC_TCTL_100BT4 0x00040000 344 345 /* 346 * Watchdog timer register 347 */ 348 #define DC_WDOG_JABBERDIS 0x00000001 349 #define DC_WDOG_HOSTUNJAB 0x00000002 350 #define DC_WDOG_JABBERCLK 0x00000004 351 #define DC_WDOG_RXWDOGDIS 0x00000010 352 #define DC_WDOG_RXWDOGCLK 0x00000020 353 #define DC_WDOG_MUSTBEZERO 0x00000100 354 #define DC_WDOG_AUIBNC 0x00100000 355 #define DC_WDOG_ACTIVITY 0x00200000 356 #define DC_WDOG_RX_MATCH 0x00400000 357 #define DC_WDOG_LINK 0x00800000 358 #define DC_WDOG_CTLWREN 0x08000000 359 360 /* 361 * Size of a setup frame. 362 */ 363 #define DC_SFRAME_LEN 192 364 365 /* 366 * 21x4x TX/RX list structure. 367 */ 368 369 struct dc_desc { 370 u_int32_t dc_status; 371 u_int32_t dc_ctl; 372 u_int32_t dc_ptr1; 373 u_int32_t dc_ptr2; 374 }; 375 376 #define dc_data dc_ptr1 377 #define dc_next dc_ptr2 378 379 #define DC_RXSTAT_FIFOOFLOW 0x00000001 380 #define DC_RXSTAT_CRCERR 0x00000002 381 #define DC_RXSTAT_DRIBBLE 0x00000004 382 #define DC_RXSTAT_MIIERE 0x00000008 383 #define DC_RXSTAT_WATCHDOG 0x00000010 384 #define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 385 #define DC_RXSTAT_COLLSEEN 0x00000040 386 #define DC_RXSTAT_GIANT 0x00000080 387 #define DC_RXSTAT_LASTFRAG 0x00000100 388 #define DC_RXSTAT_FIRSTFRAG 0x00000200 389 #define DC_RXSTAT_MULTICAST 0x00000400 390 #define DC_RXSTAT_RUNT 0x00000800 391 #define DC_RXSTAT_RXTYPE 0x00003000 392 #define DC_RXSTAT_DE 0x00004000 393 #define DC_RXSTAT_RXERR 0x00008000 394 #define DC_RXSTAT_RXLEN 0x3FFF0000 395 #define DC_RXSTAT_OWN 0x80000000 396 397 #define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 398 #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 399 400 #define DC_RXCTL_BUFLEN1 0x00000FFF 401 #define DC_RXCTL_BUFLEN2 0x00FFF000 402 #define DC_RXCTL_RLINK 0x01000000 403 #define DC_RXCTL_RLAST 0x02000000 404 405 #define DC_TXSTAT_DEFER 0x00000001 406 #define DC_TXSTAT_UNDERRUN 0x00000002 407 #define DC_TXSTAT_LINKFAIL 0x00000003 408 #define DC_TXSTAT_COLLCNT 0x00000078 409 #define DC_TXSTAT_SQE 0x00000080 410 #define DC_TXSTAT_EXCESSCOLL 0x00000100 411 #define DC_TXSTAT_LATECOLL 0x00000200 412 #define DC_TXSTAT_NOCARRIER 0x00000400 413 #define DC_TXSTAT_CARRLOST 0x00000800 414 #define DC_TXSTAT_JABTIMEO 0x00004000 415 #define DC_TXSTAT_ERRSUM 0x00008000 416 #define DC_TXSTAT_OWN 0x80000000 417 418 #define DC_TXCTL_BUFLEN1 0x000007FF 419 #define DC_TXCTL_BUFLEN2 0x003FF800 420 #define DC_TXCTL_FILTTYPE0 0x00400000 421 #define DC_TXCTL_PAD 0x00800000 422 #define DC_TXCTL_TLINK 0x01000000 423 #define DC_TXCTL_TLAST 0x02000000 424 #define DC_TXCTL_NOCRC 0x04000000 425 #define DC_TXCTL_SETUP 0x08000000 426 #define DC_TXCTL_FILTTYPE1 0x10000000 427 #define DC_TXCTL_FIRSTFRAG 0x20000000 428 #define DC_TXCTL_LASTFRAG 0x40000000 429 #define DC_TXCTL_FINT 0x80000000 430 431 #define DC_FILTER_PERFECT 0x00000000 432 #define DC_FILTER_HASHPERF 0x00400000 433 #define DC_FILTER_INVERSE 0x10000000 434 #define DC_FILTER_HASHONLY 0x10400000 435 436 #define DC_MAXFRAGS 16 437 #ifdef DEVICE_POLLING 438 #define DC_RX_LIST_CNT 192 439 #else 440 #define DC_RX_LIST_CNT 64 441 #endif 442 #define DC_TX_LIST_CNT 256 443 #define DC_MIN_FRAMELEN 60 444 #define DC_RXLEN 1536 445 446 #define DC_INC(x, y) (x) = (x + 1) % y 447 448 struct dc_list_data { 449 struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 450 struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 451 }; 452 453 struct dc_chain_data { 454 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 455 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 456 u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 457 u_int8_t dc_pad[DC_MIN_FRAMELEN]; 458 int dc_tx_prod; 459 int dc_tx_cons; 460 int dc_tx_cnt; 461 int dc_rx_prod; 462 }; 463 464 struct dc_mediainfo { 465 int dc_media; 466 u_int8_t *dc_gp_ptr; 467 u_int8_t dc_gp_len; 468 u_int8_t *dc_reset_ptr; 469 u_int8_t dc_reset_len; 470 struct dc_mediainfo *dc_next; 471 }; 472 473 474 struct dc_type { 475 u_int16_t dc_vid; 476 u_int16_t dc_did; 477 char *dc_name; 478 }; 479 480 struct dc_mii_frame { 481 u_int8_t mii_stdelim; 482 u_int8_t mii_opcode; 483 u_int8_t mii_phyaddr; 484 u_int8_t mii_regaddr; 485 u_int8_t mii_turnaround; 486 u_int16_t mii_data; 487 }; 488 489 /* 490 * MII constants 491 */ 492 #define DC_MII_STARTDELIM 0x01 493 #define DC_MII_READOP 0x02 494 #define DC_MII_WRITEOP 0x01 495 #define DC_MII_TURNAROUND 0x02 496 497 498 /* 499 * Registers specific to clone devices. 500 * This mainly relates to RX filter programming: not all 21x4x clones 501 * use the standard DEC filter programming mechanism. 502 */ 503 504 /* 505 * ADMtek specific registers and constants for the AL981 and AN985. 506 * The AN985 doesn't use the magic PHY registers. 507 */ 508 #define DC_AL_CR 0x88 /* command register */ 509 #define DC_AL_PAR0 0xA4 /* station address */ 510 #define DC_AL_PAR1 0xA8 /* station address */ 511 #define DC_AL_MAR0 0xAC /* multicast hash filter */ 512 #define DC_AL_MAR1 0xB0 /* multicast hash filter */ 513 #define DC_AL_BMCR 0xB4 /* built in PHY control */ 514 #define DC_AL_BMSR 0xB8 /* built in PHY status */ 515 #define DC_AL_VENID 0xBC /* built in PHY ID0 */ 516 #define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 517 #define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 518 #define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 519 #define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 520 521 #define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ 522 #define DC_ADMTEK_PHYADDR 0x1 523 #define DC_AL_EE_NODEADDR 4 524 /* End of ADMtek specific registers */ 525 526 /* 527 * ASIX specific registers. 528 */ 529 #define DC_AX_FILTIDX 0x68 /* RX filter index */ 530 #define DC_AX_FILTDATA 0x70 /* RX filter data */ 531 532 /* 533 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 534 */ 535 #define DC_AX_NETCFG_RX_BROAD 0x00000100 536 537 /* 538 * RX Filter Index Register values 539 */ 540 #define DC_AX_FILTIDX_PAR0 0x00000000 541 #define DC_AX_FILTIDX_PAR1 0x00000001 542 #define DC_AX_FILTIDX_MAR0 0x00000002 543 #define DC_AX_FILTIDX_MAR1 0x00000003 544 /* End of ASIX specific registers */ 545 546 /* 547 * Macronix specific registers. The Macronix chips have a special 548 * register for reading the NWAY status, which we don't use, plus 549 * a magic packet register, which we need to tweak a bit per the 550 * Macronix application notes. 551 */ 552 #define DC_MX_MAGICPACKET 0x80 553 #define DC_MX_NWAYSTAT 0xA0 554 555 /* 556 * Magic packet register 557 */ 558 #define DC_MX_MPACK_DISABLE 0x00400000 559 560 /* 561 * NWAY status register. 562 */ 563 #define DC_MX_NWAY_10BTHALF 0x08000000 564 #define DC_MX_NWAY_10BTFULL 0x10000000 565 #define DC_MX_NWAY_100BTHALF 0x20000000 566 #define DC_MX_NWAY_100BTFULL 0x40000000 567 #define DC_MX_NWAY_100BT4 0x80000000 568 569 /* 570 * These are magic values that must be written into CSR16 571 * (DC_MX_MAGICPACKET) in order to put the chip into proper 572 * operating mode. The magic numbers are documented in the 573 * Macronix 98715 application notes. 574 */ 575 #define DC_MX_MAGIC_98713 0x0F370000 576 #define DC_MX_MAGIC_98713A 0x0B3C0000 577 #define DC_MX_MAGIC_98715 0x0B3C0000 578 #define DC_MX_MAGIC_98725 0x0B3C0000 579 /* End of Macronix specific registers */ 580 581 /* 582 * PNIC 82c168/82c169 specific registers. 583 * The PNIC has its own special NWAY support, which doesn't work, 584 * and shortcut ways of reading the EEPROM and MII bus. 585 */ 586 #define DC_PN_GPIO 0x60 /* general purpose pins control */ 587 #define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 588 #define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 589 #define DC_PN_MII 0xA0 /* MII access register */ 590 #define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 591 592 /* Serial I/O EEPROM register */ 593 #define DC_PN_SIOCTL_DATA 0x0000003F 594 #define DC_PN_SIOCTL_OPCODE 0x00000300 595 #define DC_PN_SIOCTL_BUSY 0x80000000 596 597 #define DC_PN_EEOPCODE_ERASE 0x00000300 598 #define DC_PN_EEOPCODE_READ 0x00000600 599 #define DC_PN_EEOPCODE_WRITE 0x00000100 600 601 /* 602 * The first two general purpose pins control speed selection and 603 * 100Mbps loopback on the 82c168 chip. The control bits should always 604 * be set (to make the data pins outputs) and the speed selction and 605 * loopback bits set accordingly when changing media. Physically, this 606 * will set the state of a relay mounted on the card. 607 */ 608 #define DC_PN_GPIO_DATA0 0x000000001 609 #define DC_PN_GPIO_DATA1 0x000000002 610 #define DC_PN_GPIO_DATA2 0x000000004 611 #define DC_PN_GPIO_DATA3 0x000000008 612 #define DC_PN_GPIO_CTL0 0x000000010 613 #define DC_PN_GPIO_CTL1 0x000000020 614 #define DC_PN_GPIO_CTL2 0x000000040 615 #define DC_PN_GPIO_CTL3 0x000000080 616 #define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 617 #define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 618 #define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 619 #define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 620 #define DC_PN_GPIO_SETBIT(sc, r) \ 621 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 622 #define DC_PN_GPIO_CLRBIT(sc, r) \ 623 { \ 624 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 625 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 626 } 627 628 /* shortcut MII access register */ 629 #define DC_PN_MII_DATA 0x0000FFFF 630 #define DC_PN_MII_RESERVER 0x00020000 631 #define DC_PN_MII_REGADDR 0x007C0000 632 #define DC_PN_MII_PHYADDR 0x0F800000 633 #define DC_PN_MII_OPCODE 0x30000000 634 #define DC_PN_MII_BUSY 0x80000000 635 636 #define DC_PN_MIIOPCODE_READ 0x60020000 637 #define DC_PN_MIIOPCODE_WRITE 0x50020000 638 639 /* Internal NWAY bits */ 640 #define DC_PN_NWAY_RESET 0x00000001 /* reset */ 641 #define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 642 #define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 643 #define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 644 #define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 645 #define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 646 #define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 647 #define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 648 #define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 649 #define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 650 #define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 651 #define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 652 #define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 653 #define DC_PN_NWAY_CAP10HDX 0x00002000 654 #define DC_PN_NWAY_CAP10FDX 0x00004000 655 #define DC_PN_NWAY_CAP100FDX 0x00008000 656 #define DC_PN_NWAY_CAP100HDX 0x00010000 657 #define DC_PN_NWAY_CAP100T4 0x00020000 658 #define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 659 #define DC_PN_NWAY_REMFAULT 0x04000000 660 #define DC_PN_NWAY_LPAR10HDX 0x08000000 661 #define DC_PN_NWAY_LPAR10FDX 0x10000000 662 #define DC_PN_NWAY_LPAR100FDX 0x20000000 663 #define DC_PN_NWAY_LPAR100HDX 0x40000000 664 #define DC_PN_NWAY_LPAR100T4 0x80000000 665 666 /* End of PNIC specific registers */ 667 668 /* 669 * CONEXANT specific registers. 670 */ 671 672 #define DC_CONEXANT_PHYADDR 0x1 673 #define DC_CONEXANT_EE_NODEADDR 0x19A 674 675 /* End of CONEXANT specific registers */ 676 677 678 struct dc_softc { 679 struct arpcom arpcom; /* interface info */ 680 bus_space_handle_t dc_bhandle; /* bus space handle */ 681 bus_space_tag_t dc_btag; /* bus space tag */ 682 void *dc_intrhand; 683 struct resource *dc_irq; 684 struct resource *dc_res; 685 struct dc_type *dc_info; /* adapter info */ 686 device_t dc_miibus; 687 u_int8_t dc_unit; /* interface number */ 688 u_int8_t dc_type; 689 u_int8_t dc_pmode; 690 u_int8_t dc_link; 691 u_int8_t dc_cachesize; 692 int dc_romwidth; 693 int dc_pnic_rx_bug_save; 694 unsigned char *dc_pnic_rx_buf; 695 int dc_if_flags; 696 int dc_if_media; 697 u_int32_t dc_flags; 698 u_int32_t dc_txthresh; 699 u_int8_t *dc_srom; 700 struct dc_mediainfo *dc_mi; 701 struct dc_list_data *dc_ldata; 702 struct dc_chain_data dc_cdata; 703 struct callout dc_stat_timer; 704 #ifdef __alpha__ 705 int dc_srm_media; 706 #endif 707 #ifdef DEVICE_POLLING 708 int rxcycles; /* ... when polling */ 709 #endif 710 int suspended; /* 0 = normal 1 = suspended */ 711 712 u_int32_t saved_maps[5]; /* pci data */ 713 u_int32_t saved_biosaddr; 714 u_int8_t saved_intline; 715 u_int8_t saved_cachelnsz; 716 u_int8_t saved_lattimer; 717 }; 718 719 #define DC_TX_POLL 0x00000001 720 #define DC_TX_COALESCE 0x00000002 721 #define DC_TX_ADMTEK_WAR 0x00000004 722 #define DC_TX_USE_TX_INTR 0x00000008 723 #define DC_RX_FILTER_TULIP 0x00000010 724 #define DC_TX_INTR_FIRSTFRAG 0x00000020 725 #define DC_PNIC_RX_BUG_WAR 0x00000040 726 #define DC_TX_FIXED_RING 0x00000080 727 #define DC_TX_STORENFWD 0x00000100 728 #define DC_REDUCED_MII_POLL 0x00000200 729 #define DC_TX_INTR_ALWAYS 0x00000400 730 #define DC_21143_NWAY 0x00000800 731 #define DC_128BIT_HASH 0x00001000 732 #define DC_64BIT_HASH 0x00002000 733 #define DC_TULIP_LEDS 0x00004000 734 #define DC_TX_ONE 0x00008000 735 736 /* 737 * register space access macros 738 */ 739 #define CSR_WRITE_4(sc, reg, val) \ 740 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 741 742 #define CSR_READ_4(sc, reg) \ 743 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 744 745 #define DC_TIMEOUT 1000 746 #define ETHER_ALIGN 2 747 748 /* 749 * General constants that are fun to know. 750 */ 751 752 /* 753 * DEC PCI vendor ID 754 */ 755 #define DC_VENDORID_DEC 0x1011 756 757 /* 758 * DEC/Intel 21143 PCI device ID 759 */ 760 #define DC_DEVICEID_21143 0x0019 761 762 /* 763 * Macronix PCI vendor ID 764 */ 765 #define DC_VENDORID_MX 0x10D9 766 767 /* 768 * Macronix PMAC device IDs. 769 */ 770 #define DC_DEVICEID_98713 0x0512 771 #define DC_DEVICEID_987x5 0x0531 772 #define DC_DEVICEID_98727 0x0532 773 #define DC_DEVICEID_98732 0x0532 774 775 /* Macronix PCI revision codes. */ 776 #define DC_REVISION_98713 0x00 777 #define DC_REVISION_98713A 0x10 778 #define DC_REVISION_98715 0x20 779 #define DC_REVISION_98715AEC_C 0x25 780 #define DC_REVISION_98725 0x30 781 782 /* 783 * Compex PCI vendor ID. 784 */ 785 #define DC_VENDORID_CP 0x11F6 786 787 /* 788 * Compex PMAC PCI device IDs. 789 */ 790 #define DC_DEVICEID_98713_CP 0x9881 791 792 /* 793 * Lite-On PNIC PCI vendor ID 794 */ 795 #define DC_VENDORID_LO 0x11AD 796 797 /* 798 * 82c168/82c169 PNIC device IDs. Both chips have the same device 799 * ID but different revisions. Revision 0x10 is the 82c168, and 800 * 0x20 is the 82c169. 801 */ 802 #define DC_DEVICEID_82C168 0x0002 803 804 #define DC_REVISION_82C168 0x10 805 #define DC_REVISION_82C169 0x20 806 807 /* 808 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 809 * with wake on lan/magic packet support. 810 */ 811 #define DC_DEVICEID_82C115 0xc115 812 813 /* 814 * Davicom vendor ID. 815 */ 816 #define DC_VENDORID_DAVICOM 0x1282 817 818 /* 819 * Davicom device IDs. 820 */ 821 #define DC_DEVICEID_DM9009 0x9009 822 #define DC_DEVICEID_DM9100 0x9100 823 #define DC_DEVICEID_DM9102 0x9102 824 825 /* 826 * The DM9102A has the same PCI device ID as the DM9102, 827 * but a higher revision code. 828 */ 829 #define DC_REVISION_DM9102 0x10 830 #define DC_REVISION_DM9102A 0x30 831 832 /* 833 * ADMtek vendor ID. 834 */ 835 #define DC_VENDORID_ADMTEK 0x1317 836 837 /* 838 * ADMtek device IDs. 839 */ 840 #define DC_DEVICEID_AL981 0x0981 841 #define DC_DEVICEID_AN985 0x0985 842 843 844 /* 845 * 3COM PCI vendor ID 846 */ 847 #define DC_VENDORID_3COM 0x10b7 848 849 /* 850 * 3COM OfficeConnect 10/100B (3CSOHO100B-TX) 851 */ 852 #define DC_DEVICEID_3CSOHOB 0x9300 853 854 /* 855 * ASIX vendor ID. 856 */ 857 #define DC_VENDORID_ASIX 0x125B 858 859 /* 860 * ASIX device IDs. 861 */ 862 #define DC_DEVICEID_AX88140A 0x1400 863 864 /* 865 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 866 * device IDs but different revision values. 867 */ 868 #define DC_REVISION_88140 0x00 869 #define DC_REVISION_88141 0x10 870 871 /* 872 * Accton vendor ID. 873 */ 874 #define DC_VENDORID_ACCTON 0x1113 875 876 /* 877 * Accton device IDs. 878 */ 879 #define DC_DEVICEID_EN1217 0x1217 880 #define DC_DEVICEID_EN2242 0x1216 881 882 /* 883 * Conexant vendor ID. 884 */ 885 #define DC_VENDORID_CONEXANT 0x14f1 886 887 /* 888 * Conexant device IDs. 889 */ 890 #define DC_DEVICEID_RS7112 0x1803 891 892 /* 893 * PCI low memory base and low I/O base register, and 894 * other PCI registers. 895 */ 896 897 #define DC_PCI_CFID 0x00 /* Id */ 898 #define DC_PCI_CFCS 0x04 /* Command and status */ 899 #define DC_PCI_CFRV 0x08 /* Revision */ 900 #define DC_PCI_CFLT 0x0C /* Latency timer */ 901 #define DC_PCI_CFBIO 0x10 /* Base I/O address */ 902 #define DC_PCI_CFBMA 0x14 /* Base memory address */ 903 #define DC_PCI_CCIS 0x28 /* Card info struct */ 904 #define DC_PCI_CSID 0x2C /* Subsystem ID */ 905 #define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 906 #define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 907 #define DC_PCI_CFIT 0x3C /* Interrupt */ 908 #define DC_PCI_CFDD 0x40 /* Device and driver area */ 909 #define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 910 #define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 911 #define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 912 #define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 913 #define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 914 #define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 915 #define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 916 917 /* PCI ID register */ 918 #define DC_CFID_VENDOR 0x0000FFFF 919 #define DC_CFID_DEVICE 0xFFFF0000 920 921 /* PCI command/status register */ 922 #define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 923 #define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 924 #define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 925 #define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */ 926 #define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */ 927 #define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */ 928 #define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 929 #define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 930 #define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 931 #define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 932 #define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 933 #define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 934 #define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 935 #define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 936 937 /* PCI revision register */ 938 #define DC_CFRV_STEPPING 0x0000000F 939 #define DC_CFRV_REVISION 0x000000F0 940 #define DC_CFRV_SUBCLASS 0x00FF0000 941 #define DC_CFRV_BASECLASS 0xFF000000 942 943 #define DC_21143_PB_REV 0x00000030 944 #define DC_21143_TB_REV 0x00000030 945 #define DC_21143_PC_REV 0x00000030 946 #define DC_21143_TC_REV 0x00000030 947 #define DC_21143_PD_REV 0x00000041 948 #define DC_21143_TD_REV 0x00000041 949 950 /* PCI latency timer register */ 951 #define DC_CFLT_CACHELINESIZE 0x000000FF 952 #define DC_CFLT_LATENCYTIMER 0x0000FF00 953 954 /* PCI subsystem ID register */ 955 #define DC_CSID_VENDOR 0x0000FFFF 956 #define DC_CSID_DEVICE 0xFFFF0000 957 958 /* PCI cababilities pointer */ 959 #define DC_CCAP_OFFSET 0x000000FF 960 961 /* PCI interrupt config register */ 962 #define DC_CFIT_INTLINE 0x000000FF 963 #define DC_CFIT_INTPIN 0x0000FF00 964 #define DC_CFIT_MIN_GNT 0x00FF0000 965 #define DC_CFIT_MAX_LAT 0xFF000000 966 967 /* PCI capability register */ 968 #define DC_CCID_CAPID 0x000000FF 969 #define DC_CCID_NEXTPTR 0x0000FF00 970 #define DC_CCID_PM_VERS 0x00070000 971 #define DC_CCID_PME_CLK 0x00080000 972 #define DC_CCID_DVSPEC_INT 0x00200000 973 #define DC_CCID_STATE_D1 0x02000000 974 #define DC_CCID_STATE_D2 0x04000000 975 #define DC_CCID_PME_D0 0x08000000 976 #define DC_CCID_PME_D1 0x10000000 977 #define DC_CCID_PME_D2 0x20000000 978 #define DC_CCID_PME_D3HOT 0x40000000 979 #define DC_CCID_PME_D3COLD 0x80000000 980 981 /* PCI power management control/status register */ 982 #define DC_CPMC_STATE 0x00000003 983 #define DC_CPMC_PME_ENB 0x00000100 984 #define DC_CPMC_PME_STS 0x00008000 985 986 #define DC_PSTATE_D0 0x0 987 #define DC_PSTATE_D1 0x1 988 #define DC_PSTATE_D2 0x2 989 #define DC_PSTATE_D3 0x3 990 991 /* Device specific region */ 992 /* Configuration and driver area */ 993 #define DC_CFDD_DRVUSE 0x0000FFFF 994 #define DC_CFDD_SNOOZE_MODE 0x40000000 995 #define DC_CFDD_SLEEP_MODE 0x80000000 996 997 /* Configuration wake-up command register */ 998 #define DC_CWUC_MUST_BE_ZERO 0x00000001 999 #define DC_CWUC_SECUREON_ENB 0x00000002 1000 #define DC_CWUC_FORCE_WUL 0x00000004 1001 #define DC_CWUC_BNC_ABILITY 0x00000008 1002 #define DC_CWUC_AUI_ABILITY 0x00000010 1003 #define DC_CWUC_TP10_ABILITY 0x00000020 1004 #define DC_CWUC_MII_ABILITY 0x00000040 1005 #define DC_CWUC_SYM_ABILITY 0x00000080 1006 #define DC_CWUC_LOCK 0x00000100 1007 1008 /* 1009 * SROM nonsense. 1010 */ 1011 1012 #define DC_IB_CTLRCNT 0x13 1013 #define DC_IB_LEAF0_CNUM 0x1A 1014 #define DC_IB_LEAF0_OFFSET 0x1B 1015 1016 struct dc_info_leaf { 1017 u_int16_t dc_conntype; 1018 u_int8_t dc_blkcnt; 1019 u_int8_t dc_rsvd; 1020 u_int16_t dc_infoblk; 1021 }; 1022 1023 #define DC_CTYPE_10BT 0x0000 1024 #define DC_CTYPE_10BT_NWAY 0x0100 1025 #define DC_CTYPE_10BT_FDX 0x0204 1026 #define DC_CTYPE_10B2 0x0001 1027 #define DC_CTYPE_10B5 0x0002 1028 #define DC_CTYPE_100BT 0x0003 1029 #define DC_CTYPE_100BT_FDX 0x0205 1030 #define DC_CTYPE_100T4 0x0006 1031 #define DC_CTYPE_100FX 0x0007 1032 #define DC_CTYPE_100FX_FDX 0x0208 1033 #define DC_CTYPE_MII_10BT 0x0009 1034 #define DC_CTYPE_MII_10BT_FDX 0x020A 1035 #define DC_CTYPE_MII_100BT 0x000D 1036 #define DC_CTYPE_MII_100BT_FDX 0x020E 1037 #define DC_CTYPE_MII_100T4 0x000F 1038 #define DC_CTYPE_MII_100FX 0x0010 1039 #define DC_CTYPE_MII_100FX_FDX 0x0211 1040 #define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 1041 #define DC_CTYPE_PUP_AUTOSENSE 0x8800 1042 #define DC_CTYPE_NOMEDIA 0xFFFF 1043 1044 #define DC_EBLOCK_SIA 0x0002 1045 #define DC_EBLOCK_MII 0x0003 1046 #define DC_EBLOCK_SYM 0x0004 1047 #define DC_EBLOCK_RESET 0x0005 1048 #define DC_EBLOCK_PHY_SHUTDOWN 0x0006 1049 1050 struct dc_leaf_hdr { 1051 u_int16_t dc_mtype; 1052 u_int8_t dc_mcnt; 1053 u_int8_t dc_rsvd; 1054 }; 1055 1056 struct dc_eblock_hdr { 1057 u_int8_t dc_len; 1058 u_int8_t dc_type; 1059 }; 1060 1061 struct dc_eblock_sia { 1062 struct dc_eblock_hdr dc_sia_hdr; 1063 u_int8_t dc_sia_code; 1064 u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 1065 u_int8_t dc_sia_gpio_ctl[2]; 1066 u_int8_t dc_sia_gpio_dat[2]; 1067 }; 1068 1069 #define DC_SIA_CODE_10BT 0x00 1070 #define DC_SIA_CODE_10B2 0x01 1071 #define DC_SIA_CODE_10B5 0x02 1072 #define DC_SIA_CODE_10BT_FDX 0x04 1073 #define DC_SIA_CODE_EXT 0x40 1074 1075 /* 1076 * Note that the first word in the gpr and reset 1077 * sequences is always a control word. 1078 */ 1079 struct dc_eblock_mii { 1080 struct dc_eblock_hdr dc_mii_hdr; 1081 u_int8_t dc_mii_phynum; 1082 u_int8_t dc_gpr_len; 1083 /* u_int16_t dc_gpr_dat[n]; */ 1084 /* u_int8_t dc_reset_len; */ 1085 /* u_int16_t dc_reset_dat[n]; */ 1086 /* There are other fields after these, but we don't 1087 * care about them since they can be determined by looking 1088 * at the PHY. 1089 */ 1090 }; 1091 1092 struct dc_eblock_sym { 1093 struct dc_eblock_hdr dc_sym_hdr; 1094 u_int8_t dc_sym_code; 1095 u_int8_t dc_sym_gpio_ctl[2]; 1096 u_int8_t dc_sym_gpio_dat[2]; 1097 u_int8_t dc_sym_cmd[2]; 1098 }; 1099 1100 #define DC_SYM_CODE_100BT 0x03 1101 #define DC_SYM_CODE_100BT_FDX 0x05 1102 #define DC_SYM_CODE_100T4 0x06 1103 #define DC_SYM_CODE_100FX 0x07 1104 #define DC_SYM_CODE_100FX_FDX 0x08 1105 1106 struct dc_eblock_reset { 1107 struct dc_eblock_hdr dc_reset_hdr; 1108 u_int8_t dc_reset_len; 1109 /* u_int16_t dc_reset_dat[n]; */ 1110 }; 1111 1112 #ifdef __alpha__ 1113 #undef vtophys 1114 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1115 #endif 1116