1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dcreg.h,v 1.4.2.22 2003/06/07 16:55:35 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dcreg.h,v 1.9 2005/12/30 13:39:21 sephe Exp $ 34 */ 35 36 /* 37 * 21143 and clone common register definitions. 38 */ 39 40 #define DC_BUSCTL 0x00 /* bus control */ 41 #define DC_TXSTART 0x08 /* tx start demand */ 42 #define DC_RXSTART 0x10 /* rx start demand */ 43 #define DC_RXADDR 0x18 /* rx descriptor list start addr */ 44 #define DC_TXADDR 0x20 /* tx descriptor list start addr */ 45 #define DC_ISR 0x28 /* interrupt status register */ 46 #define DC_NETCFG 0x30 /* network config register */ 47 #define DC_IMR 0x38 /* interrupt mask */ 48 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 49 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 50 #define DC_ROM 0x50 /* ROM programming address */ 51 #define DC_TIMER 0x58 /* general timer */ 52 #define DC_10BTSTAT 0x60 /* SIA status */ 53 #define DC_SIARESET 0x68 /* SIA connectivity */ 54 #define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 55 #define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 56 #define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ 57 58 /* 59 * There are two general 'types' of MX chips that we need to be 60 * concerned with. One is the original 98713, which has its internal 61 * NWAY support controlled via the MDIO bits in the serial I/O 62 * register. The other is everything else (from the 98713A on up), 63 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 64 * just like the 21143. This type setting also governs which of the 65 * 'magic' numbers we write to CSR16. The PNIC II falls into the 66 * 98713A/98715/98715A/98725 category. 67 */ 68 #define DC_TYPE_98713 0x1 69 #define DC_TYPE_98713A 0x2 70 #define DC_TYPE_987x5 0x3 71 72 /* Other type of supported chips. */ 73 #define DC_TYPE_21143 0x4 /* Intel 21143 */ 74 #define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 75 #define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 76 #define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ 77 #define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 78 #define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 79 #define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 80 #define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ 81 #define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ 82 83 #define DC_IS_MACRONIX(x) \ 84 (x->dc_type == DC_TYPE_98713 || \ 85 x->dc_type == DC_TYPE_98713A || \ 86 x->dc_type == DC_TYPE_987x5) 87 88 #define DC_IS_ADMTEK(x) \ 89 (x->dc_type == DC_TYPE_AL981 || \ 90 x->dc_type == DC_TYPE_AN985) 91 92 #define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 93 #define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 94 #define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 95 #define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) 96 #define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 97 #define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 98 #define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 99 #define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) 100 #define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) 101 102 /* MII/symbol mode port types */ 103 #define DC_PMODE_MII 0x1 104 #define DC_PMODE_SYM 0x2 105 #define DC_PMODE_SIA 0x3 106 107 /* 108 * Bus control bits. 109 */ 110 #define DC_BUSCTL_RESET 0x00000001 111 #define DC_BUSCTL_ARBITRATION 0x00000002 112 #define DC_BUSCTL_SKIPLEN 0x0000007C 113 #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 114 #define DC_BUSCTL_BURSTLEN 0x00003F00 115 #define DC_BUSCTL_CACHEALIGN 0x0000C000 116 #define DC_BUSCTL_TXPOLL 0x000E0000 117 #define DC_BUSCTL_DBO 0x00100000 118 #define DC_BUSCTL_MRME 0x00200000 119 #define DC_BUSCTL_MRLE 0x00800000 120 #define DC_BUSCTL_MWIE 0x01000000 121 #define DC_BUSCTL_ONNOW_ENB 0x04000000 122 123 #define DC_SKIPLEN_1LONG 0x00000004 124 #define DC_SKIPLEN_2LONG 0x00000008 125 #define DC_SKIPLEN_3LONG 0x00000010 126 #define DC_SKIPLEN_4LONG 0x00000020 127 #define DC_SKIPLEN_5LONG 0x00000040 128 129 #define DC_CACHEALIGN_NONE 0x00000000 130 #define DC_CACHEALIGN_8LONG 0x00004000 131 #define DC_CACHEALIGN_16LONG 0x00008000 132 #define DC_CACHEALIGN_32LONG 0x0000C000 133 134 #define DC_BURSTLEN_USECA 0x00000000 135 #define DC_BURSTLEN_1LONG 0x00000100 136 #define DC_BURSTLEN_2LONG 0x00000200 137 #define DC_BURSTLEN_4LONG 0x00000400 138 #define DC_BURSTLEN_8LONG 0x00000800 139 #define DC_BURSTLEN_16LONG 0x00001000 140 #define DC_BURSTLEN_32LONG 0x00002000 141 142 #define DC_TXPOLL_OFF 0x00000000 143 #define DC_TXPOLL_1 0x00020000 144 #define DC_TXPOLL_2 0x00040000 145 #define DC_TXPOLL_3 0x00060000 146 #define DC_TXPOLL_4 0x00080000 147 #define DC_TXPOLL_5 0x000A0000 148 #define DC_TXPOLL_6 0x000C0000 149 #define DC_TXPOLL_7 0x000E0000 150 151 /* 152 * Interrupt status bits. 153 */ 154 #define DC_ISR_TX_OK 0x00000001 155 #define DC_ISR_TX_IDLE 0x00000002 156 #define DC_ISR_TX_NOBUF 0x00000004 157 #define DC_ISR_TX_JABBERTIMEO 0x00000008 158 #define DC_ISR_LINKGOOD 0x00000010 159 #define DC_ISR_TX_UNDERRUN 0x00000020 160 #define DC_ISR_RX_OK 0x00000040 161 #define DC_ISR_RX_NOBUF 0x00000080 162 #define DC_ISR_RX_READ 0x00000100 163 #define DC_ISR_RX_WATDOGTIMEO 0x00000200 164 #define DC_ISR_TX_EARLY 0x00000400 165 #define DC_ISR_TIMER_EXPIRED 0x00000800 166 #define DC_ISR_LINKFAIL 0x00001000 167 #define DC_ISR_BUS_ERR 0x00002000 168 #define DC_ISR_RX_EARLY 0x00004000 169 #define DC_ISR_ABNORMAL 0x00008000 170 #define DC_ISR_NORMAL 0x00010000 171 #define DC_ISR_RX_STATE 0x000E0000 172 #define DC_ISR_TX_STATE 0x00700000 173 #define DC_ISR_BUSERRTYPE 0x03800000 174 #define DC_ISR_100MBPSLINK 0x08000000 175 #define DC_ISR_MAGICKPACK 0x10000000 176 177 #define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 178 #define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 179 #define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 180 #define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 181 #define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 182 #define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 183 #define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 184 #define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 185 186 #define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 187 #define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 188 #define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 189 #define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 190 #define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 191 #define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 192 #define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 193 #define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 194 195 /* 196 * Network config bits. 197 */ 198 #define DC_NETCFG_RX_HASHPERF 0x00000001 199 #define DC_NETCFG_RX_ON 0x00000002 200 #define DC_NETCFG_RX_HASHONLY 0x00000004 201 #define DC_NETCFG_RX_BADFRAMES 0x00000008 202 #define DC_NETCFG_RX_INVFILT 0x00000010 203 #define DC_NETCFG_BACKOFFCNT 0x00000020 204 #define DC_NETCFG_RX_PROMISC 0x00000040 205 #define DC_NETCFG_RX_ALLMULTI 0x00000080 206 #define DC_NETCFG_FULLDUPLEX 0x00000200 207 #define DC_NETCFG_LOOPBACK 0x00000C00 208 #define DC_NETCFG_FORCECOLL 0x00001000 209 #define DC_NETCFG_TX_ON 0x00002000 210 #define DC_NETCFG_TX_THRESH 0x0000C000 211 #define DC_NETCFG_TX_BACKOFF 0x00020000 212 #define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 213 #define DC_NETCFG_HEARTBEAT 0x00080000 214 #define DC_NETCFG_STORENFWD 0x00200000 215 #define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 216 #define DC_NETCFG_PCS 0x00800000 217 #define DC_NETCFG_SCRAMBLER 0x01000000 218 #define DC_NETCFG_NO_RXCRC 0x02000000 219 #define DC_NETCFG_RX_ALL 0x40000000 220 #define DC_NETCFG_CAPEFFECT 0x80000000 221 222 #define DC_OPMODE_NORM 0x00000000 223 #define DC_OPMODE_INTLOOP 0x00000400 224 #define DC_OPMODE_EXTLOOP 0x00000800 225 226 #if 0 227 #define DC_TXTHRESH_72BYTES 0x00000000 228 #define DC_TXTHRESH_96BYTES 0x00004000 229 #define DC_TXTHRESH_128BYTES 0x00008000 230 #define DC_TXTHRESH_160BYTES 0x0000C000 231 #endif 232 233 #define DC_TXTHRESH_MIN 0x00000000 234 #define DC_TXTHRESH_INC 0x00004000 235 #define DC_TXTHRESH_MAX 0x0000C000 236 237 238 /* 239 * Interrupt mask bits. 240 */ 241 #define DC_IMR_TX_OK 0x00000001 242 #define DC_IMR_TX_IDLE 0x00000002 243 #define DC_IMR_TX_NOBUF 0x00000004 244 #define DC_IMR_TX_JABBERTIMEO 0x00000008 245 #define DC_IMR_LINKGOOD 0x00000010 246 #define DC_IMR_TX_UNDERRUN 0x00000020 247 #define DC_IMR_RX_OK 0x00000040 248 #define DC_IMR_RX_NOBUF 0x00000080 249 #define DC_IMR_RX_READ 0x00000100 250 #define DC_IMR_RX_WATDOGTIMEO 0x00000200 251 #define DC_IMR_TX_EARLY 0x00000400 252 #define DC_IMR_TIMER_EXPIRED 0x00000800 253 #define DC_IMR_LINKFAIL 0x00001000 254 #define DC_IMR_BUS_ERR 0x00002000 255 #define DC_IMR_RX_EARLY 0x00004000 256 #define DC_IMR_ABNORMAL 0x00008000 257 #define DC_IMR_NORMAL 0x00010000 258 #define DC_IMR_100MBPSLINK 0x08000000 259 #define DC_IMR_MAGICKPACK 0x10000000 260 261 #define DC_INTRS \ 262 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 263 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 264 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 265 /* 266 * Serial I/O (EEPROM/ROM) bits. 267 */ 268 #define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 269 #define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 270 #define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 271 #define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 272 #define DC_SIO_ROMDATA4 0x00000010 273 #define DC_SIO_ROMDATA5 0x00000020 274 #define DC_SIO_ROMDATA6 0x00000040 275 #define DC_SIO_ROMDATA7 0x00000080 276 #define DC_SIO_EESEL 0x00000800 277 #define DC_SIO_ROMSEL 0x00001000 278 #define DC_SIO_ROMCTL_WRITE 0x00002000 279 #define DC_SIO_ROMCTL_READ 0x00004000 280 #define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 281 #define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 282 #define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 283 #define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 284 285 #define DC_EECMD_WRITE 0x140 286 #define DC_EECMD_READ 0x180 287 #define DC_EECMD_ERASE 0x1c0 288 289 #define DC_EE_NODEADDR_OFFSET 0x70 290 #define DC_EE_NODEADDR 10 291 292 /* 293 * General purpose timer register 294 */ 295 #define DC_TIMER_VALUE 0x0000FFFF 296 #define DC_TIMER_CONTINUOUS 0x00010000 297 298 /* 299 * 10baseT status register 300 */ 301 #define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 302 #define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 303 #define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 304 #define DC_TSTAT_AUTOPOLARITY 0x00000008 305 #define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 306 #define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 307 #define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 308 #define DC_TSTAT_REMFAULT 0x00000800 309 #define DC_TSTAT_ANEGSTAT 0x00007000 310 #define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 311 #define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 312 313 #define DC_ASTAT_DISABLE 0x00000000 314 #define DC_ASTAT_TXDISABLE 0x00001000 315 #define DC_ASTAT_ABDETECT 0x00002000 316 #define DC_ASTAT_ACKDETECT 0x00003000 317 #define DC_ASTAT_CMPACKDETECT 0x00004000 318 #define DC_ASTAT_AUTONEGCMP 0x00005000 319 #define DC_ASTAT_LINKCHECK 0x00006000 320 321 /* 322 * PHY reset register 323 */ 324 #define DC_SIA_RESET 0x00000001 325 #define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 326 327 /* 328 * 10baseT control register 329 */ 330 #define DC_TCTL_ENCODER_ENB 0x00000001 331 #define DC_TCTL_LOOPBACK 0x00000002 332 #define DC_TCTL_DRIVER_ENB 0x00000004 333 #define DC_TCTL_LNKPULSE_ENB 0x00000008 334 #define DC_TCTL_HALFDUPLEX 0x00000040 335 #define DC_TCTL_AUTONEGENBL 0x00000080 336 #define DC_TCTL_RX_SQUELCH 0x00000100 337 #define DC_TCTL_COLL_SQUELCH 0x00000200 338 #define DC_TCTL_COLL_DETECT 0x00000400 339 #define DC_TCTL_SQE_ENB 0x00000800 340 #define DC_TCTL_LINKTEST 0x00001000 341 #define DC_TCTL_AUTOPOLARITY 0x00002000 342 #define DC_TCTL_SET_POL_PLUS 0x00004000 343 #define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 344 #define DC_TCTL_100BTXHALF 0x00010000 345 #define DC_TCTL_100BTXFULL 0x00020000 346 #define DC_TCTL_100BT4 0x00040000 347 348 /* 349 * Watchdog timer register 350 */ 351 #define DC_WDOG_JABBERDIS 0x00000001 352 #define DC_WDOG_HOSTUNJAB 0x00000002 353 #define DC_WDOG_JABBERCLK 0x00000004 354 #define DC_WDOG_RXWDOGDIS 0x00000010 355 #define DC_WDOG_RXWDOGCLK 0x00000020 356 #define DC_WDOG_MUSTBEZERO 0x00000100 357 #define DC_WDOG_AUIBNC 0x00100000 358 #define DC_WDOG_ACTIVITY 0x00200000 359 #define DC_WDOG_RX_MATCH 0x00400000 360 #define DC_WDOG_LINK 0x00800000 361 #define DC_WDOG_CTLWREN 0x08000000 362 363 /* 364 * SIA and General Purpose Port register (X3201) 365 */ 366 #define DC_SIAGP_RXMATCH 0x40000000 367 #define DC_SIAGP_INT1 0x20000000 368 #define DC_SIAGP_INT0 0x10000000 369 #define DC_SIAGP_WRITE_EN 0x08000000 370 #define DC_SIAGP_RXMATCH_EN 0x04000000 371 #define DC_SIAGP_INT1_EN 0x02000000 372 #define DC_SIAGP_INT0_EN 0x01000000 373 #define DC_SIAGP_LED3 0x00800000 374 #define DC_SIAGP_LED2 0x00400000 375 #define DC_SIAGP_LED1 0x00200000 376 #define DC_SIAGP_LED0 0x00100000 377 #define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 378 #define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 379 #define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 380 #define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 381 382 /* 383 * Size of a setup frame. 384 */ 385 #define DC_SFRAME_LEN 192 386 387 /* 388 * 21x4x TX/RX list structure. 389 */ 390 391 struct dc_desc { 392 u_int32_t dc_status; 393 u_int32_t dc_ctl; 394 u_int32_t dc_ptr1; 395 u_int32_t dc_ptr2; 396 }; 397 398 #define dc_data dc_ptr1 399 #define dc_next dc_ptr2 400 401 #define DC_RXSTAT_FIFOOFLOW 0x00000001 402 #define DC_RXSTAT_CRCERR 0x00000002 403 #define DC_RXSTAT_DRIBBLE 0x00000004 404 #define DC_RXSTAT_MIIERE 0x00000008 405 #define DC_RXSTAT_WATCHDOG 0x00000010 406 #define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 407 #define DC_RXSTAT_COLLSEEN 0x00000040 408 #define DC_RXSTAT_GIANT 0x00000080 409 #define DC_RXSTAT_LASTFRAG 0x00000100 410 #define DC_RXSTAT_FIRSTFRAG 0x00000200 411 #define DC_RXSTAT_MULTICAST 0x00000400 412 #define DC_RXSTAT_RUNT 0x00000800 413 #define DC_RXSTAT_RXTYPE 0x00003000 414 #define DC_RXSTAT_DE 0x00004000 415 #define DC_RXSTAT_RXERR 0x00008000 416 #define DC_RXSTAT_RXLEN 0x3FFF0000 417 #define DC_RXSTAT_OWN 0x80000000 418 419 #define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 420 #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 421 422 #define DC_RXCTL_BUFLEN1 0x00000FFF 423 #define DC_RXCTL_BUFLEN2 0x00FFF000 424 #define DC_RXCTL_RLINK 0x01000000 425 #define DC_RXCTL_RLAST 0x02000000 426 427 #define DC_TXSTAT_DEFER 0x00000001 428 #define DC_TXSTAT_UNDERRUN 0x00000002 429 #define DC_TXSTAT_LINKFAIL 0x00000003 430 #define DC_TXSTAT_COLLCNT 0x00000078 431 #define DC_TXSTAT_SQE 0x00000080 432 #define DC_TXSTAT_EXCESSCOLL 0x00000100 433 #define DC_TXSTAT_LATECOLL 0x00000200 434 #define DC_TXSTAT_NOCARRIER 0x00000400 435 #define DC_TXSTAT_CARRLOST 0x00000800 436 #define DC_TXSTAT_JABTIMEO 0x00004000 437 #define DC_TXSTAT_ERRSUM 0x00008000 438 #define DC_TXSTAT_OWN 0x80000000 439 440 #define DC_TXCTL_BUFLEN1 0x000007FF 441 #define DC_TXCTL_BUFLEN2 0x003FF800 442 #define DC_TXCTL_FILTTYPE0 0x00400000 443 #define DC_TXCTL_PAD 0x00800000 444 #define DC_TXCTL_TLINK 0x01000000 445 #define DC_TXCTL_TLAST 0x02000000 446 #define DC_TXCTL_NOCRC 0x04000000 447 #define DC_TXCTL_SETUP 0x08000000 448 #define DC_TXCTL_FILTTYPE1 0x10000000 449 #define DC_TXCTL_FIRSTFRAG 0x20000000 450 #define DC_TXCTL_LASTFRAG 0x40000000 451 #define DC_TXCTL_FINT 0x80000000 452 453 #define DC_FILTER_PERFECT 0x00000000 454 #define DC_FILTER_HASHPERF 0x00400000 455 #define DC_FILTER_INVERSE 0x10000000 456 #define DC_FILTER_HASHONLY 0x10400000 457 458 #define DC_MAXFRAGS 16 459 #ifdef DEVICE_POLLING 460 #define DC_RX_LIST_CNT 192 461 #else 462 #define DC_RX_LIST_CNT 64 463 #endif 464 #define DC_TX_LIST_CNT 256 465 #define DC_MIN_FRAMELEN 60 466 #define DC_RXLEN 1536 467 468 #define DC_INC(x, y) (x) = (x + 1) % y 469 470 struct dc_list_data { 471 struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 472 struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 473 }; 474 475 struct dc_chain_data { 476 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 477 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 478 u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 479 u_int8_t dc_pad[DC_MIN_FRAMELEN]; 480 int dc_tx_prod; 481 int dc_tx_cons; 482 int dc_tx_cnt; 483 int dc_rx_prod; 484 }; 485 486 struct dc_mediainfo { 487 int dc_media; 488 u_int8_t *dc_gp_ptr; 489 u_int8_t dc_gp_len; 490 u_int8_t *dc_reset_ptr; 491 u_int8_t dc_reset_len; 492 struct dc_mediainfo *dc_next; 493 }; 494 495 496 struct dc_type { 497 uint16_t dc_vid; 498 uint16_t dc_did; 499 const char *dc_name; 500 }; 501 502 struct dc_mii_frame { 503 u_int8_t mii_stdelim; 504 u_int8_t mii_opcode; 505 u_int8_t mii_phyaddr; 506 u_int8_t mii_regaddr; 507 u_int8_t mii_turnaround; 508 u_int16_t mii_data; 509 }; 510 511 /* 512 * MII constants 513 */ 514 #define DC_MII_STARTDELIM 0x01 515 #define DC_MII_READOP 0x02 516 #define DC_MII_WRITEOP 0x01 517 #define DC_MII_TURNAROUND 0x02 518 519 520 /* 521 * Registers specific to clone devices. 522 * This mainly relates to RX filter programming: not all 21x4x clones 523 * use the standard DEC filter programming mechanism. 524 */ 525 526 /* 527 * ADMtek specific registers and constants for the AL981 and AN985. 528 * The AN985 doesn't use the magic PHY registers. 529 */ 530 #define DC_AL_CR 0x88 /* command register */ 531 #define DC_AL_PAR0 0xA4 /* station address */ 532 #define DC_AL_PAR1 0xA8 /* station address */ 533 #define DC_AL_MAR0 0xAC /* multicast hash filter */ 534 #define DC_AL_MAR1 0xB0 /* multicast hash filter */ 535 #define DC_AL_BMCR 0xB4 /* built in PHY control */ 536 #define DC_AL_BMSR 0xB8 /* built in PHY status */ 537 #define DC_AL_VENID 0xBC /* built in PHY ID0 */ 538 #define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 539 #define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 540 #define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 541 #define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 542 543 #define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ 544 #define DC_ADMTEK_PHYADDR 0x1 545 #define DC_AL_EE_NODEADDR 4 546 /* End of ADMtek specific registers */ 547 548 /* 549 * ASIX specific registers. 550 */ 551 #define DC_AX_FILTIDX 0x68 /* RX filter index */ 552 #define DC_AX_FILTDATA 0x70 /* RX filter data */ 553 554 /* 555 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 556 */ 557 #define DC_AX_NETCFG_RX_BROAD 0x00000100 558 559 /* 560 * RX Filter Index Register values 561 */ 562 #define DC_AX_FILTIDX_PAR0 0x00000000 563 #define DC_AX_FILTIDX_PAR1 0x00000001 564 #define DC_AX_FILTIDX_MAR0 0x00000002 565 #define DC_AX_FILTIDX_MAR1 0x00000003 566 /* End of ASIX specific registers */ 567 568 /* 569 * Macronix specific registers. The Macronix chips have a special 570 * register for reading the NWAY status, which we don't use, plus 571 * a magic packet register, which we need to tweak a bit per the 572 * Macronix application notes. 573 */ 574 #define DC_MX_MAGICPACKET 0x80 575 #define DC_MX_NWAYSTAT 0xA0 576 577 /* 578 * Magic packet register 579 */ 580 #define DC_MX_MPACK_DISABLE 0x00400000 581 582 /* 583 * NWAY status register. 584 */ 585 #define DC_MX_NWAY_10BTHALF 0x08000000 586 #define DC_MX_NWAY_10BTFULL 0x10000000 587 #define DC_MX_NWAY_100BTHALF 0x20000000 588 #define DC_MX_NWAY_100BTFULL 0x40000000 589 #define DC_MX_NWAY_100BT4 0x80000000 590 591 /* 592 * These are magic values that must be written into CSR16 593 * (DC_MX_MAGICPACKET) in order to put the chip into proper 594 * operating mode. The magic numbers are documented in the 595 * Macronix 98715 application notes. 596 */ 597 #define DC_MX_MAGIC_98713 0x0F370000 598 #define DC_MX_MAGIC_98713A 0x0B3C0000 599 #define DC_MX_MAGIC_98715 0x0B3C0000 600 #define DC_MX_MAGIC_98725 0x0B3C0000 601 /* End of Macronix specific registers */ 602 603 /* 604 * PNIC 82c168/82c169 specific registers. 605 * The PNIC has its own special NWAY support, which doesn't work, 606 * and shortcut ways of reading the EEPROM and MII bus. 607 */ 608 #define DC_PN_GPIO 0x60 /* general purpose pins control */ 609 #define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 610 #define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 611 #define DC_PN_MII 0xA0 /* MII access register */ 612 #define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 613 614 /* Serial I/O EEPROM register */ 615 #define DC_PN_SIOCTL_DATA 0x0000003F 616 #define DC_PN_SIOCTL_OPCODE 0x00000300 617 #define DC_PN_SIOCTL_BUSY 0x80000000 618 619 #define DC_PN_EEOPCODE_ERASE 0x00000300 620 #define DC_PN_EEOPCODE_READ 0x00000600 621 #define DC_PN_EEOPCODE_WRITE 0x00000100 622 623 /* 624 * The first two general purpose pins control speed selection and 625 * 100Mbps loopback on the 82c168 chip. The control bits should always 626 * be set (to make the data pins outputs) and the speed selction and 627 * loopback bits set accordingly when changing media. Physically, this 628 * will set the state of a relay mounted on the card. 629 */ 630 #define DC_PN_GPIO_DATA0 0x000000001 631 #define DC_PN_GPIO_DATA1 0x000000002 632 #define DC_PN_GPIO_DATA2 0x000000004 633 #define DC_PN_GPIO_DATA3 0x000000008 634 #define DC_PN_GPIO_CTL0 0x000000010 635 #define DC_PN_GPIO_CTL1 0x000000020 636 #define DC_PN_GPIO_CTL2 0x000000040 637 #define DC_PN_GPIO_CTL3 0x000000080 638 #define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 639 #define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 640 #define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 641 #define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 642 #define DC_PN_GPIO_SETBIT(sc, r) \ 643 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 644 #define DC_PN_GPIO_CLRBIT(sc, r) \ 645 { \ 646 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 647 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 648 } 649 650 /* shortcut MII access register */ 651 #define DC_PN_MII_DATA 0x0000FFFF 652 #define DC_PN_MII_RESERVER 0x00020000 653 #define DC_PN_MII_REGADDR 0x007C0000 654 #define DC_PN_MII_PHYADDR 0x0F800000 655 #define DC_PN_MII_OPCODE 0x30000000 656 #define DC_PN_MII_BUSY 0x80000000 657 658 #define DC_PN_MIIOPCODE_READ 0x60020000 659 #define DC_PN_MIIOPCODE_WRITE 0x50020000 660 661 /* Internal NWAY bits */ 662 #define DC_PN_NWAY_RESET 0x00000001 /* reset */ 663 #define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 664 #define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 665 #define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 666 #define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 667 #define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 668 #define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 669 #define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 670 #define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 671 #define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 672 #define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 673 #define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 674 #define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 675 #define DC_PN_NWAY_CAP10HDX 0x00002000 676 #define DC_PN_NWAY_CAP10FDX 0x00004000 677 #define DC_PN_NWAY_CAP100FDX 0x00008000 678 #define DC_PN_NWAY_CAP100HDX 0x00010000 679 #define DC_PN_NWAY_CAP100T4 0x00020000 680 #define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 681 #define DC_PN_NWAY_REMFAULT 0x04000000 682 #define DC_PN_NWAY_LPAR10HDX 0x08000000 683 #define DC_PN_NWAY_LPAR10FDX 0x10000000 684 #define DC_PN_NWAY_LPAR100FDX 0x20000000 685 #define DC_PN_NWAY_LPAR100HDX 0x40000000 686 #define DC_PN_NWAY_LPAR100T4 0x80000000 687 688 /* End of PNIC specific registers */ 689 690 /* 691 * CONEXANT specific registers. 692 */ 693 694 #define DC_CONEXANT_PHYADDR 0x1 695 #define DC_CONEXANT_EE_NODEADDR 0x19A 696 697 /* End of CONEXANT specific registers */ 698 699 700 struct dc_softc { 701 struct arpcom arpcom; /* interface info */ 702 bus_space_handle_t dc_bhandle; /* bus space handle */ 703 bus_space_tag_t dc_btag; /* bus space tag */ 704 void *dc_intrhand; 705 struct resource *dc_irq; 706 struct resource *dc_res; 707 const struct dc_type *dc_info; /* adapter info */ 708 device_t dc_miibus; 709 u_int8_t dc_type; 710 u_int8_t dc_pmode; 711 u_int8_t dc_link; 712 u_int8_t dc_cachesize; 713 int dc_romwidth; 714 int dc_pnic_rx_bug_save; 715 unsigned char *dc_pnic_rx_buf; 716 int dc_if_flags; 717 int dc_if_media; 718 u_int32_t dc_flags; 719 u_int32_t dc_txthresh; 720 u_int8_t *dc_srom; 721 struct dc_mediainfo *dc_mi; 722 struct dc_list_data *dc_ldata; 723 struct dc_chain_data dc_cdata; 724 struct callout dc_stat_timer; 725 #ifdef DEVICE_POLLING 726 int rxcycles; /* ... when polling */ 727 #endif 728 int suspended; /* 0 = normal 1 = suspended */ 729 730 u_int32_t saved_maps[5]; /* pci data */ 731 u_int32_t saved_biosaddr; 732 u_int8_t saved_intline; 733 u_int8_t saved_cachelnsz; 734 u_int8_t saved_lattimer; 735 }; 736 737 #define DC_TX_POLL 0x00000001 738 #define DC_TX_COALESCE 0x00000002 739 #define DC_TX_ADMTEK_WAR 0x00000004 740 #define DC_TX_USE_TX_INTR 0x00000008 741 #define DC_RX_FILTER_TULIP 0x00000010 742 #define DC_TX_INTR_FIRSTFRAG 0x00000020 743 #define DC_PNIC_RX_BUG_WAR 0x00000040 744 #define DC_TX_FIXED_RING 0x00000080 745 #define DC_TX_STORENFWD 0x00000100 746 #define DC_REDUCED_MII_POLL 0x00000200 747 #define DC_TX_INTR_ALWAYS 0x00000400 748 #define DC_21143_NWAY 0x00000800 749 #define DC_128BIT_HASH 0x00001000 750 #define DC_64BIT_HASH 0x00002000 751 #define DC_TULIP_LEDS 0x00004000 752 #define DC_TX_ONE 0x00008000 753 #define DC_TX_ALIGN 0x00010000 754 755 /* 756 * register space access macros 757 */ 758 #define CSR_WRITE_4(sc, reg, val) \ 759 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 760 761 #define CSR_READ_4(sc, reg) \ 762 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 763 764 #define DC_TIMEOUT 1000 765 #define ETHER_ALIGN 2 766 767 /* 768 * General constants that are fun to know. 769 */ 770 771 /* 772 * DEC PCI vendor ID 773 */ 774 #define DC_VENDORID_DEC 0x1011 775 776 /* 777 * DEC/Intel 21143 PCI device ID 778 */ 779 #define DC_DEVICEID_21143 0x0019 780 781 /* 782 * Macronix PCI vendor ID 783 */ 784 #define DC_VENDORID_MX 0x10D9 785 786 /* 787 * Macronix PMAC device IDs. 788 */ 789 #define DC_DEVICEID_98713 0x0512 790 #define DC_DEVICEID_987x5 0x0531 791 #define DC_DEVICEID_98727 0x0532 792 #define DC_DEVICEID_98732 0x0532 793 794 /* Macronix PCI revision codes. */ 795 #define DC_REVISION_98713 0x00 796 #define DC_REVISION_98713A 0x10 797 #define DC_REVISION_98715 0x20 798 #define DC_REVISION_98715AEC_C 0x25 799 #define DC_REVISION_98725 0x30 800 801 /* 802 * Compex PCI vendor ID. 803 */ 804 #define DC_VENDORID_CP 0x11F6 805 806 /* 807 * Compex PMAC PCI device IDs. 808 */ 809 #define DC_DEVICEID_98713_CP 0x9881 810 811 /* 812 * Lite-On PNIC PCI vendor ID 813 */ 814 #define DC_VENDORID_LO 0x11AD 815 816 /* 817 * 82c168/82c169 PNIC device IDs. Both chips have the same device 818 * ID but different revisions. Revision 0x10 is the 82c168, and 819 * 0x20 is the 82c169. 820 */ 821 #define DC_DEVICEID_82C168 0x0002 822 823 #define DC_REVISION_82C168 0x10 824 #define DC_REVISION_82C169 0x20 825 826 /* 827 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 828 * with wake on lan/magic packet support. 829 */ 830 #define DC_DEVICEID_82C115 0xc115 831 832 /* 833 * Davicom vendor ID. 834 */ 835 #define DC_VENDORID_DAVICOM 0x1282 836 837 /* 838 * Davicom device IDs. 839 */ 840 #define DC_DEVICEID_DM9009 0x9009 841 #define DC_DEVICEID_DM9100 0x9100 842 #define DC_DEVICEID_DM9102 0x9102 843 844 /* 845 * The DM9102A has the same PCI device ID as the DM9102, 846 * but a higher revision code. 847 */ 848 #define DC_REVISION_DM9102 0x10 849 #define DC_REVISION_DM9102A 0x30 850 851 /* 852 * ADMtek vendor ID. 853 */ 854 #define DC_VENDORID_ADMTEK 0x1317 855 856 /* 857 * ADMtek device IDs. 858 */ 859 #define DC_DEVICEID_AL981 0x0981 860 #define DC_DEVICEID_AN985 0x0985 861 #define DC_DEVICEID_ADM9511 0x9511 862 #define DC_DEVICEID_ADM9513 0x9513 863 864 865 /* 866 * 3COM PCI vendor ID 867 */ 868 #define DC_VENDORID_3COM 0x10b7 869 870 /* 871 * 3COM OfficeConnect 10/100B (3CSOHO100B-TX) 872 */ 873 #define DC_DEVICEID_3CSOHOB 0x9300 874 875 /* 876 * ASIX vendor ID. 877 */ 878 #define DC_VENDORID_ASIX 0x125B 879 880 /* 881 * ASIX device IDs. 882 */ 883 #define DC_DEVICEID_AX88140A 0x1400 884 885 /* 886 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 887 * device IDs but different revision values. 888 */ 889 #define DC_REVISION_88140 0x00 890 #define DC_REVISION_88141 0x10 891 892 /* 893 * Accton vendor ID. 894 */ 895 #define DC_VENDORID_ACCTON 0x1113 896 897 /* 898 * Accton device IDs. 899 */ 900 #define DC_DEVICEID_EN1217 0x1217 901 #define DC_DEVICEID_EN2242 0x1216 902 903 /* 904 * Xircom vendor ID 905 */ 906 #define DC_VENDORID_XIRCOM 0x115d 907 908 /* 909 * Xircom device IDs. 910 */ 911 #define DC_DEVICEID_X3201 0x0003 912 913 /* 914 * Conexant vendor ID. 915 */ 916 #define DC_VENDORID_CONEXANT 0x14f1 917 918 /* 919 * Conexant device IDs. 920 */ 921 #define DC_DEVICEID_RS7112 0x1803 922 923 /* 924 * PCI low memory base and low I/O base register, and 925 * other PCI registers. 926 */ 927 928 #define DC_PCI_CFID 0x00 /* Id */ 929 #define DC_PCI_CFCS 0x04 /* Command and status */ 930 #define DC_PCI_CFRV 0x08 /* Revision */ 931 #define DC_PCI_CFLT 0x0C /* Latency timer */ 932 #define DC_PCI_CFBIO 0x10 /* Base I/O address */ 933 #define DC_PCI_CFBMA 0x14 /* Base memory address */ 934 #define DC_PCI_CCIS 0x28 /* Card info struct */ 935 #define DC_PCI_CSID 0x2C /* Subsystem ID */ 936 #define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 937 #define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 938 #define DC_PCI_CFIT 0x3C /* Interrupt */ 939 #define DC_PCI_CFDD 0x40 /* Device and driver area */ 940 #define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 941 #define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 942 #define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 943 #define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 944 #define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 945 #define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 946 #define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 947 948 /* PCI ID register */ 949 #define DC_CFID_VENDOR 0x0000FFFF 950 #define DC_CFID_DEVICE 0xFFFF0000 951 952 /* PCI command/status register */ 953 #define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 954 #define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 955 #define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 956 #define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */ 957 #define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */ 958 #define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */ 959 #define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 960 #define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 961 #define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 962 #define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 963 #define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 964 #define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 965 #define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 966 #define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 967 968 /* PCI revision register */ 969 #define DC_CFRV_STEPPING 0x0000000F 970 #define DC_CFRV_REVISION 0x000000F0 971 #define DC_CFRV_SUBCLASS 0x00FF0000 972 #define DC_CFRV_BASECLASS 0xFF000000 973 974 #define DC_21143_PB_REV 0x00000030 975 #define DC_21143_TB_REV 0x00000030 976 #define DC_21143_PC_REV 0x00000030 977 #define DC_21143_TC_REV 0x00000030 978 #define DC_21143_PD_REV 0x00000041 979 #define DC_21143_TD_REV 0x00000041 980 981 /* PCI latency timer register */ 982 #define DC_CFLT_CACHELINESIZE 0x000000FF 983 #define DC_CFLT_LATENCYTIMER 0x0000FF00 984 985 /* PCI subsystem ID register */ 986 #define DC_CSID_VENDOR 0x0000FFFF 987 #define DC_CSID_DEVICE 0xFFFF0000 988 989 /* PCI cababilities pointer */ 990 #define DC_CCAP_OFFSET 0x000000FF 991 992 /* PCI interrupt config register */ 993 #define DC_CFIT_INTLINE 0x000000FF 994 #define DC_CFIT_INTPIN 0x0000FF00 995 #define DC_CFIT_MIN_GNT 0x00FF0000 996 #define DC_CFIT_MAX_LAT 0xFF000000 997 998 /* PCI capability register */ 999 #define DC_CCID_CAPID 0x000000FF 1000 #define DC_CCID_NEXTPTR 0x0000FF00 1001 #define DC_CCID_PM_VERS 0x00070000 1002 #define DC_CCID_PME_CLK 0x00080000 1003 #define DC_CCID_DVSPEC_INT 0x00200000 1004 #define DC_CCID_STATE_D1 0x02000000 1005 #define DC_CCID_STATE_D2 0x04000000 1006 #define DC_CCID_PME_D0 0x08000000 1007 #define DC_CCID_PME_D1 0x10000000 1008 #define DC_CCID_PME_D2 0x20000000 1009 #define DC_CCID_PME_D3HOT 0x40000000 1010 #define DC_CCID_PME_D3COLD 0x80000000 1011 1012 /* PCI power management control/status register */ 1013 #define DC_CPMC_STATE 0x00000003 1014 #define DC_CPMC_PME_ENB 0x00000100 1015 #define DC_CPMC_PME_STS 0x00008000 1016 1017 /* Device specific region */ 1018 /* Configuration and driver area */ 1019 #define DC_CFDD_DRVUSE 0x0000FFFF 1020 #define DC_CFDD_SNOOZE_MODE 0x40000000 1021 #define DC_CFDD_SLEEP_MODE 0x80000000 1022 1023 /* Configuration wake-up command register */ 1024 #define DC_CWUC_MUST_BE_ZERO 0x00000001 1025 #define DC_CWUC_SECUREON_ENB 0x00000002 1026 #define DC_CWUC_FORCE_WUL 0x00000004 1027 #define DC_CWUC_BNC_ABILITY 0x00000008 1028 #define DC_CWUC_AUI_ABILITY 0x00000010 1029 #define DC_CWUC_TP10_ABILITY 0x00000020 1030 #define DC_CWUC_MII_ABILITY 0x00000040 1031 #define DC_CWUC_SYM_ABILITY 0x00000080 1032 #define DC_CWUC_LOCK 0x00000100 1033 1034 /* 1035 * SROM nonsense. 1036 */ 1037 1038 #define DC_IB_CTLRCNT 0x13 1039 #define DC_IB_LEAF0_CNUM 0x1A 1040 #define DC_IB_LEAF0_OFFSET 0x1B 1041 1042 struct dc_info_leaf { 1043 u_int16_t dc_conntype; 1044 u_int8_t dc_blkcnt; 1045 u_int8_t dc_rsvd; 1046 u_int16_t dc_infoblk; 1047 }; 1048 1049 #define DC_CTYPE_10BT 0x0000 1050 #define DC_CTYPE_10BT_NWAY 0x0100 1051 #define DC_CTYPE_10BT_FDX 0x0204 1052 #define DC_CTYPE_10B2 0x0001 1053 #define DC_CTYPE_10B5 0x0002 1054 #define DC_CTYPE_100BT 0x0003 1055 #define DC_CTYPE_100BT_FDX 0x0205 1056 #define DC_CTYPE_100T4 0x0006 1057 #define DC_CTYPE_100FX 0x0007 1058 #define DC_CTYPE_100FX_FDX 0x0208 1059 #define DC_CTYPE_MII_10BT 0x0009 1060 #define DC_CTYPE_MII_10BT_FDX 0x020A 1061 #define DC_CTYPE_MII_100BT 0x000D 1062 #define DC_CTYPE_MII_100BT_FDX 0x020E 1063 #define DC_CTYPE_MII_100T4 0x000F 1064 #define DC_CTYPE_MII_100FX 0x0010 1065 #define DC_CTYPE_MII_100FX_FDX 0x0211 1066 #define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 1067 #define DC_CTYPE_PUP_AUTOSENSE 0x8800 1068 #define DC_CTYPE_NOMEDIA 0xFFFF 1069 1070 #define DC_EBLOCK_SIA 0x0002 1071 #define DC_EBLOCK_MII 0x0003 1072 #define DC_EBLOCK_SYM 0x0004 1073 #define DC_EBLOCK_RESET 0x0005 1074 #define DC_EBLOCK_PHY_SHUTDOWN 0x0006 1075 1076 struct dc_leaf_hdr { 1077 u_int16_t dc_mtype; 1078 u_int8_t dc_mcnt; 1079 u_int8_t dc_rsvd; 1080 }; 1081 1082 struct dc_eblock_hdr { 1083 u_int8_t dc_len; 1084 u_int8_t dc_type; 1085 }; 1086 1087 struct dc_eblock_sia { 1088 struct dc_eblock_hdr dc_sia_hdr; 1089 u_int8_t dc_sia_code; 1090 union { 1091 struct dc_sia_ext { 1092 u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 1093 u_int8_t dc_sia_gpio_ctl[2]; 1094 u_int8_t dc_sia_gpio_dat[2]; 1095 } dc_sia_ext; 1096 struct dc_sia_noext { 1097 u_int8_t dc_sia_gpio_ctl[2]; 1098 u_int8_t dc_sia_gpio_dat[2]; 1099 } dc_sia_noext; 1100 } dc_un; 1101 }; 1102 1103 #define DC_SIA_CODE_10BT 0x00 1104 #define DC_SIA_CODE_10B2 0x01 1105 #define DC_SIA_CODE_10B5 0x02 1106 #define DC_SIA_CODE_10BT_FDX 0x04 1107 #define DC_SIA_CODE_EXT 0x40 1108 1109 /* 1110 * Note that the first word in the gpr and reset 1111 * sequences is always a control word. 1112 */ 1113 struct dc_eblock_mii { 1114 struct dc_eblock_hdr dc_mii_hdr; 1115 u_int8_t dc_mii_phynum; 1116 u_int8_t dc_gpr_len; 1117 /* u_int16_t dc_gpr_dat[n]; */ 1118 /* u_int8_t dc_reset_len; */ 1119 /* u_int16_t dc_reset_dat[n]; */ 1120 /* There are other fields after these, but we don't 1121 * care about them since they can be determined by looking 1122 * at the PHY. 1123 */ 1124 }; 1125 1126 struct dc_eblock_sym { 1127 struct dc_eblock_hdr dc_sym_hdr; 1128 u_int8_t dc_sym_code; 1129 u_int8_t dc_sym_gpio_ctl[2]; 1130 u_int8_t dc_sym_gpio_dat[2]; 1131 u_int8_t dc_sym_cmd[2]; 1132 }; 1133 1134 #define DC_SYM_CODE_100BT 0x03 1135 #define DC_SYM_CODE_100BT_FDX 0x05 1136 #define DC_SYM_CODE_100T4 0x06 1137 #define DC_SYM_CODE_100FX 0x07 1138 #define DC_SYM_CODE_100FX_FDX 0x08 1139 1140 struct dc_eblock_reset { 1141 struct dc_eblock_hdr dc_reset_hdr; 1142 u_int8_t dc_reset_len; 1143 /* u_int16_t dc_reset_dat[n]; */ 1144 }; 1145