1 /* $NetBSD: dc21040reg.h,v 1.15 1998/05/22 18:50:59 matt Exp $ */ 2 3 /* $FreeBSD: head/sys/dev/de/dc21040reg.h 97748 2002-06-02 20:05:59Z schweikh $ */ 4 5 /*- 6 * Copyright (c) 1994, 1995, 1996 Matt Thomas <matt@3am-software.com> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Id: dc21040reg.h,v 1.24 1997/05/16 19:47:09 thomas Exp 29 */ 30 31 #if !defined(_DC21040_H) 32 #define _DC21040_H 33 34 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 35 #define TULIP_BITFIELD2(a, b) b, a 36 #define TULIP_BITFIELD3(a, b, c) c, b, a 37 #define TULIP_BITFIELD4(a, b, c, d) d, c, b, a 38 #else 39 #define TULIP_BITFIELD2(a, b) a, b 40 #define TULIP_BITFIELD3(a, b, c) a, b, c 41 #define TULIP_BITFIELD4(a, b, c, d) a, b, c, d 42 #endif 43 44 typedef struct { 45 u_int32_t d_status; 46 u_int32_t TULIP_BITFIELD3(d_length1 : 11, 47 d_length2 : 11, 48 d_flag : 10); 49 u_int32_t d_addr1; 50 u_int32_t d_addr2; 51 } tulip_desc_t; 52 53 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = 21040) */ 54 #define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */ 55 /* 56 * Transmit Status 57 */ 58 #define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */ 59 #define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */ 60 #define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */ 61 #define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */ 62 #define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */ 63 #define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */ 64 #define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */ 65 #define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */ 66 #define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */ 67 #define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */ 68 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */ 69 /* 70 * Receive Status 71 */ 72 #define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */ 73 #define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */ 74 #define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */ 75 #define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */ 76 #define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */ 77 #define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */ 78 #define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */ 79 #define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */ 80 #define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */ 81 #define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */ 82 #define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */ 83 #define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */ 84 #define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */ 85 86 87 #define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */ 88 #define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */ 89 90 #define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */ 91 #define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */ 92 #define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */ 93 #define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */ 94 #define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */ 95 #define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */ 96 #define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */ 97 #define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */ 98 99 /* 100 * The 21040 Registers (IO Space Addresses) 101 */ 102 #define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */ 103 #define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */ 104 #define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */ 105 #define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */ 106 #define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */ 107 #define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */ 108 #define TULIP_REG_CMD 0x30 /* CSR6 -- Command */ 109 #define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */ 110 #define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */ 111 #define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */ 112 #define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */ 113 #define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */ 114 #define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */ 115 #define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */ 116 #define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */ 117 #define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */ 118 119 /* 120 * CSR5 -- Status Register 121 * CSR7 -- Interrupt Control 122 */ 123 #define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */ 124 #define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */ 125 #define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */ 126 #define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */ 127 #define TULIP_STS_ERR_SHIFT 23 128 #define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */ 129 #define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */ 130 #define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */ 131 #define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */ 132 #define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */ 133 #define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */ 134 #define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */ 135 #define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an 136 unavailable transmit descriptor */ 137 #define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */ 138 #define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/ 139 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */ 140 #define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */ 141 #define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive 142 packet before prefetch of next descriptor */ 143 #define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */ 144 #define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of 145 unavailable receive buffers */ 146 #define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */ 147 #define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame 148 from the receive FIFO as a result of 149 an unavailable receive buffer */ 150 #define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame 151 from the receive FIFO into the receive 152 buffer. */ 153 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */ 154 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */ 155 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */ 156 #define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (21040) */ 157 #define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (21040) */ 158 #define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (21140) */ 159 #define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (21040) */ 160 #define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchbog Timeout */ 161 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */ 162 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */ 163 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */ 164 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */ 165 #define TULIP_STS_LINKPASS 0x00000010L /* (RW) LinkPass (21041) */ 166 #define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */ 167 #define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */ 168 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */ 169 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */ 170 171 /* 172 * CSR6 -- Command (Operation Mode) Register 173 */ 174 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (21140) */ 175 #define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (21140) */ 176 #define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (21140) */ 177 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (21140) */ 178 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Foward (21140) */ 179 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (21140) */ 180 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (21140) */ 181 #define TULIP_CMD_ENHCAPTEFFCT 0x00040000L /* (RW) Enhanced Capture Effecty (21041) */ 182 #define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */ 183 #define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (21040) */ 184 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */ 185 #define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */ 186 #define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */ 187 #define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */ 188 #define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */ 189 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */ 190 #define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */ 191 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */ 192 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */ 193 #define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */ 194 #define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */ 195 #define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */ 196 #define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */ 197 #define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */ 198 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */ 199 #define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */ 200 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */ 201 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */ 202 203 #define TULIP_SIASTS_OTHERRXACTIVITY 0x00000200L 204 #define TULIP_SIASTS_RXACTIVITY 0x00000100L 205 #define TULIP_SIASTS_LINKFAIL 0x00000004L 206 #define TULIP_SIASTS_LINK100FAIL 0x00000002L 207 #define TULIP_SIACONN_RESET 0x00000000L 208 209 /* 210 * 21040 SIA definitions 211 */ 212 #define TULIP_21040_PROBE_10BASET_TIMEOUT 2500 213 #define TULIP_21040_PROBE_AUIBNC_TIMEOUT 300 214 #define TULIP_21040_PROBE_EXTSIA_TIMEOUT 300 215 216 #define TULIP_21040_SIACONN_10BASET 0x0000EF01L 217 #define TULIP_21040_SIATXRX_10BASET 0x0000FFFFL 218 #define TULIP_21040_SIAGEN_10BASET 0x00000000L 219 220 #define TULIP_21040_SIACONN_10BASET_FD 0x0000EF01L 221 #define TULIP_21040_SIATXRX_10BASET_FD 0x0000FFFDL 222 #define TULIP_21040_SIAGEN_10BASET_FD 0x00000000L 223 224 #define TULIP_21040_SIACONN_AUIBNC 0x0000EF09L 225 #define TULIP_21040_SIATXRX_AUIBNC 0x00000705L 226 #define TULIP_21040_SIAGEN_AUIBNC 0x00000006L 227 228 #define TULIP_21040_SIACONN_EXTSIA 0x00003041L 229 #define TULIP_21040_SIATXRX_EXTSIA 0x00000000L 230 #define TULIP_21040_SIAGEN_EXTSIA 0x00000006L 231 232 /* 233 * 21041 SIA definitions 234 */ 235 236 #define TULIP_21041_PROBE_10BASET_TIMEOUT 2500 237 #define TULIP_21041_PROBE_AUIBNC_TIMEOUT 300 238 239 #define TULIP_21041_SIACONN_10BASET 0x0000EF01L 240 #define TULIP_21041_SIATXRX_10BASET 0x0000FF3FL 241 #define TULIP_21041_SIAGEN_10BASET 0x00000000L 242 243 #define TULIP_21041P2_SIACONN_10BASET 0x0000EF01L 244 #define TULIP_21041P2_SIATXRX_10BASET 0x0000FFFFL 245 #define TULIP_21041P2_SIAGEN_10BASET 0x00000000L 246 247 #define TULIP_21041_SIACONN_10BASET_FD 0x0000EF01L 248 #define TULIP_21041_SIATXRX_10BASET_FD 0x0000FF3DL 249 #define TULIP_21041_SIAGEN_10BASET_FD 0x00000000L 250 251 #define TULIP_21041P2_SIACONN_10BASET_FD 0x0000EF01L 252 #define TULIP_21041P2_SIATXRX_10BASET_FD 0x0000FFFFL 253 #define TULIP_21041P2_SIAGEN_10BASET_FD 0x00000000L 254 255 #define TULIP_21041_SIACONN_AUI 0x0000EF09L 256 #define TULIP_21041_SIATXRX_AUI 0x0000F73DL 257 #define TULIP_21041_SIAGEN_AUI 0x0000000EL 258 259 #define TULIP_21041P2_SIACONN_AUI 0x0000EF09L 260 #define TULIP_21041P2_SIATXRX_AUI 0x0000F7FDL 261 #define TULIP_21041P2_SIAGEN_AUI 0x0000000EL 262 263 #define TULIP_21041_SIACONN_BNC 0x0000EF09L 264 #define TULIP_21041_SIATXRX_BNC 0x0000F73DL 265 #define TULIP_21041_SIAGEN_BNC 0x00000006L 266 267 #define TULIP_21041P2_SIACONN_BNC 0x0000EF09L 268 #define TULIP_21041P2_SIATXRX_BNC 0x0000F7FDL 269 #define TULIP_21041P2_SIAGEN_BNC 0x00000006L 270 271 /* 272 * 21142 SIA definitions 273 */ 274 275 #define TULIP_21142_PROBE_10BASET_TIMEOUT 2500 276 #define TULIP_21142_PROBE_AUIBNC_TIMEOUT 300 277 278 #define TULIP_21142_SIACONN_10BASET 0x00000001L 279 #define TULIP_21142_SIATXRX_10BASET 0x00007F3FL 280 #define TULIP_21142_SIAGEN_10BASET 0x00000008L 281 282 #define TULIP_21142_SIACONN_10BASET_FD 0x00000001L 283 #define TULIP_21142_SIATXRX_10BASET_FD 0x00007F3DL 284 #define TULIP_21142_SIAGEN_10BASET_FD 0x00000008L 285 286 #define TULIP_21142_SIACONN_AUI 0x00000009L 287 #define TULIP_21142_SIATXRX_AUI 0x00000705L 288 #define TULIP_21142_SIAGEN_AUI 0x0000000EL 289 290 #define TULIP_21142_SIACONN_BNC 0x00000009L 291 #define TULIP_21142_SIATXRX_BNC 0x00000705L 292 #define TULIP_21142_SIAGEN_BNC 0x00000006L 293 294 295 296 297 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L 298 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L 299 300 #define TULIP_BUSMODE_SWRESET 0x00000001L 301 #define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL 302 #define TULIP_BUSMODE_BIGENDIAN 0x00000080L 303 #define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L 304 #define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L 305 #define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L 306 #define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L 307 #define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L 308 #define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L 309 #define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L 310 #define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L 311 #define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L 312 #define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L 313 #define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L 314 #define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L 315 #define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L 316 #define TULIP_BUSMODE_TXPOLL_200000ns 0x00020000L 317 #define TULIP_BUSMODE_TXPOLL_800000ns 0x00040000L 318 #define TULIP_BUSMODE_TXPOLL_1600000ns 0x00060000L 319 #define TULIP_BUSMODE_TXPOLL_12800ns 0x00080000L /* 21041 only */ 320 #define TULIP_BUSMODE_TXPOLL_25600ns 0x000A0000L /* 21041 only */ 321 #define TULIP_BUSMODE_TXPOLL_51200ns 0x000C0000L /* 21041 only */ 322 #define TULIP_BUSMODE_TXPOLL_102400ns 0x000E0000L /* 21041 only */ 323 #define TULIP_BUSMODE_DESC_BIGENDIAN 0x00100000L /* 21041 only */ 324 #define TULIP_BUSMODE_READMULTIPLE 0x00200000L /* */ 325 326 #define TULIP_REG_CFDA 0x40 327 #define TULIP_CFDA_SLEEP 0x80000000L 328 #define TULIP_CFDA_SNOOZE 0x40000000L 329 330 #define TULIP_GP_PINSET 0x00000100L 331 /* 332 * These are the defintitions used for the DEC 21140 333 * evaluation board. 334 */ 335 #define TULIP_GP_EB_PINS 0x0000001F /* General Purpose Pin directions */ 336 #define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 337 #define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 338 #define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */ 339 340 /* 341 * These are the defintitions used for the SMC9332 (21140) board. 342 */ 343 #define TULIP_GP_SMC_9332_PINS 0x0000003F /* General Purpose Pin directions */ 344 #define TULIP_GP_SMC_9332_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 345 #define TULIP_GP_SMC_9332_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 346 #define TULIP_GP_SMC_9332_INIT 0x00000009 /* No loopback --- point-to-point */ 347 348 /* 349 * There are the definitions used for the DEC DE500 350 * 10/100 family of boards 351 */ 352 #define TULIP_GP_DE500_PINS 0x0000001FL 353 #define TULIP_GP_DE500_LINK_PASS 0x00000080L 354 #define TULIP_GP_DE500_SYM_LINK 0x00000040L 355 #define TULIP_GP_DE500_SIGNAL_DETECT 0x00000020L 356 #define TULIP_GP_DE500_PHY_RESET 0x00000010L 357 #define TULIP_GP_DE500_HALFDUPLEX 0x00000008L 358 #define TULIP_GP_DE500_PHY_LOOPBACK 0x00000004L 359 #define TULIP_GP_DE500_FORCE_LED 0x00000002L 360 #define TULIP_GP_DE500_FORCE_100 0x00000001L 361 362 /* 363 * These are the defintitions used for the Cogent EM100 364 * 21140 board. 365 */ 366 #define TULIP_GP_EM100_PINS 0x0000003F /* General Purpose Pin directions */ 367 #define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */ 368 #define TULIP_COGENT_EM100TX_ID 0x12 369 #define TULIP_COGENT_EM100FX_ID 0x15 370 371 372 /* 373 * These are the defintitions used for the Znyx ZX342 374 * 10/100 board 375 */ 376 #define TULIP_ZNYX_ID_ZX312 0x0602 377 #define TULIP_ZNYX_ID_ZX312T 0x0622 378 #define TULIP_ZNYX_ID_ZX314_INTA 0x0701 379 #define TULIP_ZNYX_ID_ZX314 0x0711 380 #define TULIP_ZNYX_ID_ZX315_INTA 0x0801 381 #define TULIP_ZNYX_ID_ZX315 0x0811 382 #define TULIP_ZNYX_ID_ZX342 0x0901 383 #define TULIP_ZNYX_ID_ZX342B 0x0921 384 #define TULIP_ZNYX_ID_ZX342_X3 0x0902 385 #define TULIP_ZNYX_ID_ZX342_X4 0x0903 386 #define TULIP_ZNYX_ID_ZX344 0x0A01 387 #define TULIP_ZNYX_ID_ZX351 0x0B01 388 #define TULIP_ZNYX_ID_ZX345 0x0C01 389 #define TULIP_ZNYX_ID_ZX311 0x0D01 390 #define TULIP_ZNYX_ID_ZX346 0x0E01 391 392 #define TULIP_GP_ZX34X_PINS 0x0000001F /* General Purpose Pin directions */ 393 #define TULIP_GP_ZX344_PINS 0x0000000B /* General Purpose Pin directions */ 394 #define TULIP_GP_ZX345_PINS 0x00000003 /* General Purpose Pin directions */ 395 #define TULIP_GP_ZX346_PINS 0x00000043 /* General Purpose Pin directions */ 396 #define TULIP_GP_ZX34X_LNKFAIL 0x00000080 /* 10Mb/s Link Failure */ 397 #define TULIP_GP_ZX34X_SYMDET 0x00000040 /* 100Mb/s Symbol Detect */ 398 #define TULIP_GP_ZX345_PHYACT 0x00000040 /* PHY Activity */ 399 #define TULIP_GP_ZX34X_SIGDET 0x00000020 /* 100Mb/s Signal Detect */ 400 #define TULIP_GP_ZX346_AUTONEG_ENABLED 0x00000020 /* 802.3u autoneg enabled */ 401 #define TULIP_GP_ZX342_COLENA 0x00000008 /* 10t Ext LB */ 402 #define TULIP_GP_ZX344_ROTINT 0x00000008 /* PPB IRQ rotation */ 403 #define TULIP_GP_ZX345_SPEED10 0x00000008 /* 10Mb speed detect */ 404 #define TULIP_GP_ZX346_SPEED100 0x00000008 /* 100Mb speed detect */ 405 #define TULIP_GP_ZX34X_NCOLENA 0x00000004 /* 10t Int LB */ 406 #define TULIP_GP_ZX34X_RXMATCH 0x00000004 /* RX Match */ 407 #define TULIP_GP_ZX346_FULLDUPLEX 0x00000004 /* Full Duplex Sensed */ 408 #define TULIP_GP_ZX34X_LB102 0x00000002 /* 100tx twister LB */ 409 #define TULIP_GP_ZX34X_NLB101 0x00000001 /* PDT/PDR LB */ 410 #define TULIP_GP_ZX34X_INIT 0x00000009 411 412 /* 413 * Asante's stuff... 414 */ 415 #define TULIP_GP_ASANTE_PINS 0x000000bf /* GP pin config */ 416 #define TULIP_GP_ASANTE_PHYRESET 0x00000008 /* Reset PHY */ 417 418 /* 419 * ACCTON EN1207 specialties 420 */ 421 422 #define TULIP_CSR8_EN1207 0x08 423 #define TULIP_CSR9_EN1207 0x00 424 #define TULIP_CSR10_EN1207 0x03 425 #define TULIP_CSR11_EN1207 0x1F 426 427 #define TULIP_GP_EN1207_BNC_INIT 0x0000011B 428 #define TULIP_GP_EN1207_UTP_INIT 0x9E00000B 429 #define TULIP_GP_EN1207_100_INIT 0x6D00031B 430 431 /* 432 * SROM definitions for the 21140 and 21041. 433 */ 434 #define SROMXREG 0x0400 435 #define SROMSEL 0x0800 436 #define SROMRD 0x4000 437 #define SROMWR 0x2000 438 #define SROMDIN 0x0008 439 #define SROMDOUT 0x0004 440 #define SROMDOUTON 0x0004 441 #define SROMDOUTOFF 0x0004 442 #define SROMCLKON 0x0002 443 #define SROMCLKOFF 0x0002 444 #define SROMCSON 0x0001 445 #define SROMCSOFF 0x0001 446 #define SROMCS 0x0001 447 448 #define SROMCMD_MODE 4 449 #define SROMCMD_WR 5 450 #define SROMCMD_RD 6 451 452 #define SROM_BITWIDTH 6 453 454 /* 455 * MII Definitions for the 21041 and 21140/21140A/21142 456 */ 457 #define MII_PREAMBLE (~0) 458 #define MII_TEST 0xAAAAAAAA 459 #define MII_RDCMD 0xF6 /* 1111.0110 */ 460 #define MII_WRCMD 0xF5 /* 1111.0101 */ 461 #define MII_DIN 0x00080000 462 #define MII_RD 0x00040000 463 #define MII_WR 0x00000000 464 #define MII_DOUT 0x00020000 465 #define MII_CLK 0x00010000 466 #define MII_CLKON MII_CLK 467 #define MII_CLKOFF MII_CLK 468 469 #define PHYREG_CONTROL 0 470 #define PHYREG_STATUS 1 471 #define PHYREG_IDLOW 2 472 #define PHYREG_IDHIGH 3 473 #define PHYREG_AUTONEG_ADVERTISEMENT 4 474 #define PHYREG_AUTONEG_ABILITIES 5 475 #define PHYREG_AUTONEG_EXPANSION 6 476 #define PHYREG_AUTONEG_NEXTPAGE 7 477 478 #define PHYSTS_100BASET4 0x8000 479 #define PHYSTS_100BASETX_FD 0x4000 480 #define PHYSTS_100BASETX 0x2000 481 #define PHYSTS_10BASET_FD 0x1000 482 #define PHYSTS_10BASET 0x0800 483 #define PHYSTS_AUTONEG_DONE 0x0020 484 #define PHYSTS_REMOTE_FAULT 0x0010 485 #define PHYSTS_CAN_AUTONEG 0x0008 486 #define PHYSTS_LINK_UP 0x0004 487 #define PHYSTS_JABBER_DETECT 0x0002 488 #define PHYSTS_EXTENDED_REGS 0x0001 489 490 #define PHYCTL_RESET 0x8000 491 #define PHYCTL_SELECT_100MB 0x2000 492 #define PHYCTL_AUTONEG_ENABLE 0x1000 493 #define PHYCTL_ISOLATE 0x0400 494 #define PHYCTL_AUTONEG_RESTART 0x0200 495 #define PHYCTL_FULL_DUPLEX 0x0100 496 497 /* 498 * Definitions for the DE425. 499 */ 500 #define DE425_CFID 0x08 /* Configuration Id */ 501 #define DE425_CFCS 0x0C /* Configuration Command-Status */ 502 #define DE425_CFRV 0x18 /* Configuration Revision */ 503 #define DE425_CFLT 0x1C /* Configuration Latency Timer */ 504 #define DE425_CBIO 0x28 /* Configuration Base IO Address */ 505 #define DE425_CFDA 0x2C /* Configuration Driver Area */ 506 #define DE425_ENETROM_OFFSET 0xC90 /* Offset in I/O space for ENETROM */ 507 #define DE425_CFG0 0xC88 /* IRQ register */ 508 #define DE425_EISAID 0x10a34250 /* EISA device id */ 509 #define DE425_EISA_IOSIZE 0x100 510 511 #define DEC_VENDORID 0x1011 512 #define CHIPID_21040 0x0002 513 #define CHIPID_21140 0x0009 514 #define CHIPID_21041 0x0014 515 #define CHIPID_21142 0x0019 516 #define PCI_VENDORID(x) ((x) & 0xFFFF) 517 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF) 518 519 /* 520 * Generic SROM Format 521 * 522 * 523 */ 524 525 typedef struct { 526 u_int8_t sh_idbuf[18]; 527 u_int8_t sh_version; 528 u_int8_t sh_adapter_count; 529 u_int8_t sh_ieee802_address[6]; 530 } tulip_srom_header_t; 531 532 typedef struct { 533 u_int8_t sai_device; 534 u_int8_t sai_leaf_offset_lowbyte; 535 u_int8_t sai_leaf_offset_highbyte; 536 } tulip_srom_adapter_info_t; 537 538 typedef enum { 539 TULIP_SROM_CONNTYPE_10BASET =0x0000, 540 TULIP_SROM_CONNTYPE_BNC =0x0001, 541 TULIP_SROM_CONNTYPE_AUI =0x0002, 542 TULIP_SROM_CONNTYPE_100BASETX =0x0003, 543 TULIP_SROM_CONNTYPE_100BASET4 =0x0006, 544 TULIP_SROM_CONNTYPE_100BASEFX =0x0007, 545 TULIP_SROM_CONNTYPE_MII_10BASET =0x0009, 546 TULIP_SROM_CONNTYPE_MII_100BASETX =0x000D, 547 TULIP_SROM_CONNTYPE_MII_100BASET4 =0x000F, 548 TULIP_SROM_CONNTYPE_MII_100BASEFX =0x0010, 549 TULIP_SROM_CONNTYPE_10BASET_NWAY =0x0100, 550 TULIP_SROM_CONNTYPE_10BASET_FD =0x0204, 551 TULIP_SROM_CONNTYPE_MII_10BASET_FD =0x020A, 552 TULIP_SROM_CONNTYPE_100BASETX_FD =0x020E, 553 TULIP_SROM_CONNTYPE_MII_100BASETX_FD =0x0211, 554 TULIP_SROM_CONNTYPE_10BASET_NOLINKPASS =0x0400, 555 TULIP_SROM_CONNTYPE_AUTOSENSE =0x0800, 556 TULIP_SROM_CONNTYPE_AUTOSENSE_POWERUP =0x8800, 557 TULIP_SROM_CONNTYPE_AUTOSENSE_NWAY =0x9000, 558 TULIP_SROM_CONNTYPE_NOT_USED =0xFFFF 559 } tulip_srom_connection_t; 560 561 typedef enum { 562 TULIP_SROM_MEDIA_10BASET =0x0000, 563 TULIP_SROM_MEDIA_BNC =0x0001, 564 TULIP_SROM_MEDIA_AUI =0x0002, 565 TULIP_SROM_MEDIA_100BASETX =0x0003, 566 TULIP_SROM_MEDIA_10BASET_FD =0x0004, 567 TULIP_SROM_MEDIA_100BASETX_FD =0x0005, 568 TULIP_SROM_MEDIA_100BASET4 =0x0006, 569 TULIP_SROM_MEDIA_100BASEFX =0x0007, 570 TULIP_SROM_MEDIA_100BASEFX_FD =0x0008 571 } tulip_srom_media_t; 572 573 #define TULIP_SROM_21041_EXTENDED 0x40 574 575 #define TULIP_SROM_2114X_NOINDICATOR 0x8000 576 #define TULIP_SROM_2114X_DEFAULT 0x4000 577 #define TULIP_SROM_2114X_POLARITY 0x0080 578 #define TULIP_SROM_2114X_CMDBITS(n) (((n) & 0x0071) << 18) 579 #define TULIP_SROM_2114X_BITPOS(b) (1 << (((b) & 0x0E) >> 1)) 580 581 582 583 #endif /* !defined(_DC21040_H) */ 584