1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.80 2008/09/17 08:51:29 sephe Exp $ 67 */ 68 /* 69 * SERIALIZATION API RULES: 70 * 71 * - If the driver uses the same serializer for the interrupt as for the 72 * ifnet, most of the serialization will be done automatically for the 73 * driver. 74 * 75 * - ifmedia entry points will be serialized by the ifmedia code using the 76 * ifnet serializer. 77 * 78 * - if_* entry points except for if_input will be serialized by the IF 79 * and protocol layers. 80 * 81 * - The device driver must be sure to serialize access from timeout code 82 * installed by the device driver. 83 * 84 * - The device driver typically holds the serializer at the time it wishes 85 * to call if_input. 86 * 87 * - We must call lwkt_serialize_handler_enable() prior to enabling the 88 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 89 * the hardware interrupt in order to avoid handler execution races from 90 * scheduled interrupt threads. 91 * 92 * NOTE! Since callers into the device driver hold the ifnet serializer, 93 * the device driver may be holding a serializer at the time it calls 94 * if_input even if it is not serializer-aware. 95 */ 96 97 #include "opt_polling.h" 98 99 #include <sys/param.h> 100 #include <sys/bus.h> 101 #include <sys/endian.h> 102 #include <sys/interrupt.h> 103 #include <sys/kernel.h> 104 #include <sys/ktr.h> 105 #include <sys/malloc.h> 106 #include <sys/mbuf.h> 107 #include <sys/proc.h> 108 #include <sys/rman.h> 109 #include <sys/serialize.h> 110 #include <sys/socket.h> 111 #include <sys/sockio.h> 112 #include <sys/sysctl.h> 113 #include <sys/systm.h> 114 115 #include <net/bpf.h> 116 #include <net/ethernet.h> 117 #include <net/if.h> 118 #include <net/if_arp.h> 119 #include <net/if_dl.h> 120 #include <net/if_media.h> 121 #include <net/ifq_var.h> 122 #include <net/vlan/if_vlan_var.h> 123 #include <net/vlan/if_vlan_ether.h> 124 125 #include <netinet/in_systm.h> 126 #include <netinet/in.h> 127 #include <netinet/ip.h> 128 #include <netinet/tcp.h> 129 #include <netinet/udp.h> 130 131 #include <bus/pci/pcivar.h> 132 #include <bus/pci/pcireg.h> 133 134 #include <dev/netif/ig_hal/e1000_api.h> 135 #include <dev/netif/ig_hal/e1000_82571.h> 136 #include <dev/netif/em/if_em.h> 137 138 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 139 #define EM_VER " 6.9.6" 140 141 #define _EM_DEVICE(id, ret) \ 142 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 143 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 144 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 145 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 146 147 static const struct em_vendor_info em_vendor_info_array[] = { 148 EM_DEVICE(82540EM), 149 EM_DEVICE(82540EM_LOM), 150 EM_DEVICE(82540EP), 151 EM_DEVICE(82540EP_LOM), 152 EM_DEVICE(82540EP_LP), 153 154 EM_DEVICE(82541EI), 155 EM_DEVICE(82541ER), 156 EM_DEVICE(82541ER_LOM), 157 EM_DEVICE(82541EI_MOBILE), 158 EM_DEVICE(82541GI), 159 EM_DEVICE(82541GI_LF), 160 EM_DEVICE(82541GI_MOBILE), 161 162 EM_DEVICE(82542), 163 164 EM_DEVICE(82543GC_FIBER), 165 EM_DEVICE(82543GC_COPPER), 166 167 EM_DEVICE(82544EI_COPPER), 168 EM_DEVICE(82544EI_FIBER), 169 EM_DEVICE(82544GC_COPPER), 170 EM_DEVICE(82544GC_LOM), 171 172 EM_DEVICE(82545EM_COPPER), 173 EM_DEVICE(82545EM_FIBER), 174 EM_DEVICE(82545GM_COPPER), 175 EM_DEVICE(82545GM_FIBER), 176 EM_DEVICE(82545GM_SERDES), 177 178 EM_DEVICE(82546EB_COPPER), 179 EM_DEVICE(82546EB_FIBER), 180 EM_DEVICE(82546EB_QUAD_COPPER), 181 EM_DEVICE(82546GB_COPPER), 182 EM_DEVICE(82546GB_FIBER), 183 EM_DEVICE(82546GB_SERDES), 184 EM_DEVICE(82546GB_PCIE), 185 EM_DEVICE(82546GB_QUAD_COPPER), 186 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 187 188 EM_DEVICE(82547EI), 189 EM_DEVICE(82547EI_MOBILE), 190 EM_DEVICE(82547GI), 191 192 EM_EMX_DEVICE(82571EB_COPPER), 193 EM_EMX_DEVICE(82571EB_FIBER), 194 EM_EMX_DEVICE(82571EB_SERDES), 195 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 196 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 197 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 198 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 199 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 200 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 201 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 202 203 EM_EMX_DEVICE(82572EI_COPPER), 204 EM_EMX_DEVICE(82572EI_FIBER), 205 EM_EMX_DEVICE(82572EI_SERDES), 206 EM_EMX_DEVICE(82572EI), 207 208 EM_EMX_DEVICE(82573E), 209 EM_EMX_DEVICE(82573E_IAMT), 210 EM_EMX_DEVICE(82573L), 211 212 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 213 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 214 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 215 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 216 217 EM_DEVICE(ICH8_IGP_M_AMT), 218 EM_DEVICE(ICH8_IGP_AMT), 219 EM_DEVICE(ICH8_IGP_C), 220 EM_DEVICE(ICH8_IFE), 221 EM_DEVICE(ICH8_IFE_GT), 222 EM_DEVICE(ICH8_IFE_G), 223 EM_DEVICE(ICH8_IGP_M), 224 225 EM_DEVICE(ICH9_IGP_M_AMT), 226 EM_DEVICE(ICH9_IGP_AMT), 227 EM_DEVICE(ICH9_IGP_C), 228 EM_DEVICE(ICH9_IGP_M), 229 EM_DEVICE(ICH9_IGP_M_V), 230 EM_DEVICE(ICH9_IFE), 231 EM_DEVICE(ICH9_IFE_GT), 232 EM_DEVICE(ICH9_IFE_G), 233 EM_DEVICE(ICH9_BM), 234 235 EM_EMX_DEVICE(82574L), 236 237 EM_DEVICE(ICH10_R_BM_LM), 238 EM_DEVICE(ICH10_R_BM_LF), 239 EM_DEVICE(ICH10_R_BM_V), 240 EM_DEVICE(ICH10_D_BM_LM), 241 EM_DEVICE(ICH10_D_BM_LF), 242 243 /* required last entry */ 244 EM_DEVICE_NULL 245 }; 246 247 static int em_probe(device_t); 248 static int em_attach(device_t); 249 static int em_detach(device_t); 250 static int em_shutdown(device_t); 251 static int em_suspend(device_t); 252 static int em_resume(device_t); 253 254 static void em_init(void *); 255 static void em_stop(struct adapter *); 256 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 257 static void em_start(struct ifnet *); 258 #ifdef DEVICE_POLLING 259 static void em_poll(struct ifnet *, enum poll_cmd, int); 260 #endif 261 static void em_watchdog(struct ifnet *); 262 static void em_media_status(struct ifnet *, struct ifmediareq *); 263 static int em_media_change(struct ifnet *); 264 static void em_timer(void *); 265 266 static void em_intr(void *); 267 static void em_rxeof(struct adapter *, int); 268 static void em_txeof(struct adapter *); 269 static void em_tx_collect(struct adapter *); 270 static void em_tx_purge(struct adapter *); 271 static void em_enable_intr(struct adapter *); 272 static void em_disable_intr(struct adapter *); 273 274 static int em_dma_malloc(struct adapter *, bus_size_t, 275 struct em_dma_alloc *); 276 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 277 static void em_init_tx_ring(struct adapter *); 278 static int em_init_rx_ring(struct adapter *); 279 static int em_create_tx_ring(struct adapter *); 280 static int em_create_rx_ring(struct adapter *); 281 static void em_destroy_tx_ring(struct adapter *, int); 282 static void em_destroy_rx_ring(struct adapter *, int); 283 static int em_newbuf(struct adapter *, int, int); 284 static int em_encap(struct adapter *, struct mbuf **); 285 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 286 struct mbuf *); 287 static int em_txcsum_pullup(struct adapter *, struct mbuf **); 288 static int em_txcsum(struct adapter *, struct mbuf *, 289 uint32_t *, uint32_t *); 290 291 static int em_get_hw_info(struct adapter *); 292 static int em_is_valid_eaddr(const uint8_t *); 293 static int em_alloc_pci_res(struct adapter *); 294 static void em_free_pci_res(struct adapter *); 295 static int em_hw_init(struct adapter *); 296 static void em_setup_ifp(struct adapter *); 297 static void em_init_tx_unit(struct adapter *); 298 static void em_init_rx_unit(struct adapter *); 299 static void em_update_stats(struct adapter *); 300 static void em_set_promisc(struct adapter *); 301 static void em_disable_promisc(struct adapter *); 302 static void em_set_multi(struct adapter *); 303 static void em_update_link_status(struct adapter *); 304 static void em_smartspeed(struct adapter *); 305 306 /* Hardware workarounds */ 307 static int em_82547_fifo_workaround(struct adapter *, int); 308 static void em_82547_update_fifo_head(struct adapter *, int); 309 static int em_82547_tx_fifo_reset(struct adapter *); 310 static void em_82547_move_tail(void *); 311 static void em_82547_move_tail_serialized(struct adapter *); 312 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 313 314 static void em_print_debug_info(struct adapter *); 315 static void em_print_nvm_info(struct adapter *); 316 static void em_print_hw_stats(struct adapter *); 317 318 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 319 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 320 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 321 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 322 static void em_add_sysctl(struct adapter *adapter); 323 324 /* Management and WOL Support */ 325 static void em_get_mgmt(struct adapter *); 326 static void em_rel_mgmt(struct adapter *); 327 static void em_get_hw_control(struct adapter *); 328 static void em_rel_hw_control(struct adapter *); 329 static void em_enable_wol(device_t); 330 331 static device_method_t em_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, em_probe), 334 DEVMETHOD(device_attach, em_attach), 335 DEVMETHOD(device_detach, em_detach), 336 DEVMETHOD(device_shutdown, em_shutdown), 337 DEVMETHOD(device_suspend, em_suspend), 338 DEVMETHOD(device_resume, em_resume), 339 { 0, 0 } 340 }; 341 342 static driver_t em_driver = { 343 "em", 344 em_methods, 345 sizeof(struct adapter), 346 }; 347 348 static devclass_t em_devclass; 349 350 DECLARE_DUMMY_MODULE(if_em); 351 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 352 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, 0, 0); 353 354 /* 355 * Tunables 356 */ 357 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 358 static int em_rxd = EM_DEFAULT_RXD; 359 static int em_txd = EM_DEFAULT_TXD; 360 static int em_smart_pwr_down = FALSE; 361 362 /* Controls whether promiscuous also shows bad packets */ 363 static int em_debug_sbp = FALSE; 364 365 static int em_82573_workaround = TRUE; 366 367 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 368 TUNABLE_INT("hw.em.rxd", &em_rxd); 369 TUNABLE_INT("hw.em.txd", &em_txd); 370 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 371 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 372 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 373 374 /* Global used in WOL setup with multiport cards */ 375 static int em_global_quad_port_a = 0; 376 377 /* Set this to one to display debug statistics */ 378 static int em_display_debug_stats = 0; 379 380 #if !defined(KTR_IF_EM) 381 #define KTR_IF_EM KTR_ALL 382 #endif 383 KTR_INFO_MASTER(if_em); 384 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0); 385 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0); 386 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0); 387 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0); 388 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0); 389 #define logif(name) KTR_LOG(if_em_ ## name) 390 391 static int 392 em_probe(device_t dev) 393 { 394 const struct em_vendor_info *ent; 395 uint16_t vid, did; 396 397 vid = pci_get_vendor(dev); 398 did = pci_get_device(dev); 399 400 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 401 if (vid == ent->vendor_id && did == ent->device_id) { 402 device_set_desc(dev, ent->desc); 403 device_set_async_attach(dev, TRUE); 404 return (ent->ret); 405 } 406 } 407 return (ENXIO); 408 } 409 410 static int 411 em_attach(device_t dev) 412 { 413 struct adapter *adapter = device_get_softc(dev); 414 struct ifnet *ifp = &adapter->arpcom.ac_if; 415 int tsize, rsize; 416 int error = 0; 417 uint16_t eeprom_data, device_id; 418 419 adapter->dev = adapter->osdep.dev = dev; 420 421 callout_init(&adapter->timer); 422 callout_init(&adapter->tx_fifo_timer); 423 424 /* Determine hardware and mac info */ 425 error = em_get_hw_info(adapter); 426 if (error) { 427 device_printf(dev, "Identify hardware failed\n"); 428 goto fail; 429 } 430 431 /* Setup PCI resources */ 432 error = em_alloc_pci_res(adapter); 433 if (error) { 434 device_printf(dev, "Allocation of PCI resources failed\n"); 435 goto fail; 436 } 437 438 /* 439 * For ICH8 and family we need to map the flash memory, 440 * and this must happen after the MAC is identified. 441 */ 442 if (adapter->hw.mac.type == e1000_ich8lan || 443 adapter->hw.mac.type == e1000_ich10lan || 444 adapter->hw.mac.type == e1000_ich9lan) { 445 adapter->flash_rid = EM_BAR_FLASH; 446 447 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 448 &adapter->flash_rid, RF_ACTIVE); 449 if (adapter->flash == NULL) { 450 device_printf(dev, "Mapping of Flash failed\n"); 451 error = ENXIO; 452 goto fail; 453 } 454 adapter->osdep.flash_bus_space_tag = 455 rman_get_bustag(adapter->flash); 456 adapter->osdep.flash_bus_space_handle = 457 rman_get_bushandle(adapter->flash); 458 459 /* 460 * This is used in the shared code 461 * XXX this goof is actually not used. 462 */ 463 adapter->hw.flash_address = (uint8_t *)adapter->flash; 464 } 465 466 /* Do Shared Code initialization */ 467 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 468 device_printf(dev, "Setup of Shared code failed\n"); 469 error = ENXIO; 470 goto fail; 471 } 472 473 e1000_get_bus_info(&adapter->hw); 474 475 /* 476 * Validate number of transmit and receive descriptors. It 477 * must not exceed hardware maximum, and must be multiple 478 * of E1000_DBA_ALIGN. 479 */ 480 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 481 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 482 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 483 em_txd < EM_MIN_TXD) { 484 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 485 EM_DEFAULT_TXD, em_txd); 486 adapter->num_tx_desc = EM_DEFAULT_TXD; 487 } else { 488 adapter->num_tx_desc = em_txd; 489 } 490 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 491 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 492 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 493 em_rxd < EM_MIN_RXD) { 494 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 495 EM_DEFAULT_RXD, em_rxd); 496 adapter->num_rx_desc = EM_DEFAULT_RXD; 497 } else { 498 adapter->num_rx_desc = em_rxd; 499 } 500 501 adapter->hw.mac.autoneg = DO_AUTO_NEG; 502 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 503 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 504 adapter->rx_buffer_len = MCLBYTES; 505 506 /* 507 * Interrupt throttle rate 508 */ 509 if (em_int_throttle_ceil == 0) { 510 adapter->int_throttle_ceil = 0; 511 } else { 512 int throttle = em_int_throttle_ceil; 513 514 if (throttle < 0) 515 throttle = EM_DEFAULT_ITR; 516 517 /* Recalculate the tunable value to get the exact frequency. */ 518 throttle = 1000000000 / 256 / throttle; 519 520 /* Upper 16bits of ITR is reserved and should be zero */ 521 if (throttle & 0xffff0000) 522 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 523 524 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 525 } 526 527 e1000_init_script_state_82541(&adapter->hw, TRUE); 528 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 529 530 /* Copper options */ 531 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 532 adapter->hw.phy.mdix = AUTO_ALL_MODES; 533 adapter->hw.phy.disable_polarity_correction = FALSE; 534 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 535 } 536 537 /* Set the frame limits assuming standard ethernet sized frames. */ 538 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 539 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 540 541 /* This controls when hardware reports transmit completion status. */ 542 adapter->hw.mac.report_tx_early = 1; 543 544 /* 545 * Create top level busdma tag 546 */ 547 error = bus_dma_tag_create(NULL, 1, 0, 548 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 549 NULL, NULL, 550 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 551 0, &adapter->parent_dtag); 552 if (error) { 553 device_printf(dev, "could not create top level DMA tag\n"); 554 goto fail; 555 } 556 557 /* 558 * Allocate Transmit Descriptor ring 559 */ 560 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 561 EM_DBA_ALIGN); 562 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 563 if (error) { 564 device_printf(dev, "Unable to allocate tx_desc memory\n"); 565 goto fail; 566 } 567 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 568 569 /* 570 * Allocate Receive Descriptor ring 571 */ 572 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 573 EM_DBA_ALIGN); 574 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 575 if (error) { 576 device_printf(dev, "Unable to allocate rx_desc memory\n"); 577 goto fail; 578 } 579 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 580 581 /* Make sure we have a good EEPROM before we read from it */ 582 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 583 /* 584 * Some PCI-E parts fail the first check due to 585 * the link being in sleep state, call it again, 586 * if it fails a second time its a real issue. 587 */ 588 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 589 device_printf(dev, 590 "The EEPROM Checksum Is Not Valid\n"); 591 error = EIO; 592 goto fail; 593 } 594 } 595 596 /* Initialize the hardware */ 597 error = em_hw_init(adapter); 598 if (error) { 599 device_printf(dev, "Unable to initialize the hardware\n"); 600 goto fail; 601 } 602 603 /* Copy the permanent MAC address out of the EEPROM */ 604 if (e1000_read_mac_addr(&adapter->hw) < 0) { 605 device_printf(dev, "EEPROM read error while reading MAC" 606 " address\n"); 607 error = EIO; 608 goto fail; 609 } 610 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 611 device_printf(dev, "Invalid MAC address\n"); 612 error = EIO; 613 goto fail; 614 } 615 616 /* Allocate transmit descriptors and buffers */ 617 error = em_create_tx_ring(adapter); 618 if (error) { 619 device_printf(dev, "Could not setup transmit structures\n"); 620 goto fail; 621 } 622 623 /* Allocate receive descriptors and buffers */ 624 error = em_create_rx_ring(adapter); 625 if (error) { 626 device_printf(dev, "Could not setup receive structures\n"); 627 goto fail; 628 } 629 630 /* Manually turn off all interrupts */ 631 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 632 633 /* Setup OS specific network interface */ 634 em_setup_ifp(adapter); 635 636 /* Add sysctl tree, must after em_setup_ifp() */ 637 em_add_sysctl(adapter); 638 639 /* Initialize statistics */ 640 em_update_stats(adapter); 641 642 adapter->hw.mac.get_link_status = 1; 643 em_update_link_status(adapter); 644 645 /* Indicate SOL/IDER usage */ 646 if (e1000_check_reset_block(&adapter->hw)) { 647 device_printf(dev, 648 "PHY reset is blocked due to SOL/IDER session.\n"); 649 } 650 651 /* Determine if we have to control management hardware */ 652 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 653 654 /* 655 * Setup Wake-on-Lan 656 */ 657 switch (adapter->hw.mac.type) { 658 case e1000_82542: 659 case e1000_82543: 660 break; 661 662 case e1000_82546: 663 case e1000_82546_rev_3: 664 case e1000_82571: 665 case e1000_80003es2lan: 666 if (adapter->hw.bus.func == 1) { 667 e1000_read_nvm(&adapter->hw, 668 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 669 } else { 670 e1000_read_nvm(&adapter->hw, 671 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 672 } 673 eeprom_data &= EM_EEPROM_APME; 674 break; 675 676 default: 677 /* APME bit in EEPROM is mapped to WUC.APME */ 678 eeprom_data = 679 E1000_READ_REG(&adapter->hw, E1000_WUC) & E1000_WUC_APME; 680 break; 681 } 682 if (eeprom_data) 683 adapter->wol = E1000_WUFC_MAG; 684 /* 685 * We have the eeprom settings, now apply the special cases 686 * where the eeprom may be wrong or the board won't support 687 * wake on lan on a particular port 688 */ 689 device_id = pci_get_device(dev); 690 switch (device_id) { 691 case E1000_DEV_ID_82546GB_PCIE: 692 adapter->wol = 0; 693 break; 694 695 case E1000_DEV_ID_82546EB_FIBER: 696 case E1000_DEV_ID_82546GB_FIBER: 697 case E1000_DEV_ID_82571EB_FIBER: 698 /* 699 * Wake events only supported on port A for dual fiber 700 * regardless of eeprom setting 701 */ 702 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 703 E1000_STATUS_FUNC_1) 704 adapter->wol = 0; 705 break; 706 707 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 708 case E1000_DEV_ID_82571EB_QUAD_COPPER: 709 case E1000_DEV_ID_82571EB_QUAD_FIBER: 710 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 711 /* if quad port adapter, disable WoL on all but port A */ 712 if (em_global_quad_port_a != 0) 713 adapter->wol = 0; 714 /* Reset for multiple quad port adapters */ 715 if (++em_global_quad_port_a == 4) 716 em_global_quad_port_a = 0; 717 break; 718 } 719 720 /* XXX disable wol */ 721 adapter->wol = 0; 722 723 /* Do we need workaround for 82544 PCI-X adapter? */ 724 if (adapter->hw.bus.type == e1000_bus_type_pcix && 725 adapter->hw.mac.type == e1000_82544) 726 adapter->pcix_82544 = TRUE; 727 else 728 adapter->pcix_82544 = FALSE; 729 730 if (adapter->pcix_82544) { 731 /* 732 * 82544 on PCI-X may split one TX segment 733 * into two TX descs, so we double its number 734 * of spare TX desc here. 735 */ 736 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 737 } else { 738 adapter->spare_tx_desc = EM_TX_SPARE; 739 } 740 741 /* 742 * Keep following relationship between spare_tx_desc, oact_tx_desc 743 * and tx_int_nsegs: 744 * (spare_tx_desc + EM_TX_RESERVED) <= 745 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 746 */ 747 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 748 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 749 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 750 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 751 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 752 753 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 754 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 755 adapter->tx_int_nsegs = adapter->oact_tx_desc; 756 757 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 758 em_intr, adapter, &adapter->intr_tag, 759 ifp->if_serializer); 760 if (error) { 761 device_printf(dev, "Failed to register interrupt handler"); 762 ether_ifdetach(&adapter->arpcom.ac_if); 763 goto fail; 764 } 765 766 ifp->if_cpuid = ithread_cpuid(rman_get_start(adapter->intr_res)); 767 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 768 return (0); 769 fail: 770 em_detach(dev); 771 return (error); 772 } 773 774 static int 775 em_detach(device_t dev) 776 { 777 struct adapter *adapter = device_get_softc(dev); 778 779 if (device_is_attached(dev)) { 780 struct ifnet *ifp = &adapter->arpcom.ac_if; 781 782 lwkt_serialize_enter(ifp->if_serializer); 783 784 em_stop(adapter); 785 786 e1000_phy_hw_reset(&adapter->hw); 787 788 em_rel_mgmt(adapter); 789 790 if ((adapter->hw.mac.type == e1000_82573 || 791 adapter->hw.mac.type == e1000_ich8lan || 792 adapter->hw.mac.type == e1000_ich10lan || 793 adapter->hw.mac.type == e1000_ich9lan) && 794 e1000_check_mng_mode(&adapter->hw)) 795 em_rel_hw_control(adapter); 796 797 if (adapter->wol) { 798 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 799 E1000_WUC_PME_EN); 800 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 801 em_enable_wol(dev); 802 } 803 804 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 805 806 lwkt_serialize_exit(ifp->if_serializer); 807 808 ether_ifdetach(ifp); 809 } 810 bus_generic_detach(dev); 811 812 em_free_pci_res(adapter); 813 814 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 815 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 816 817 /* Free Transmit Descriptor ring */ 818 if (adapter->tx_desc_base) 819 em_dma_free(adapter, &adapter->txdma); 820 821 /* Free Receive Descriptor ring */ 822 if (adapter->rx_desc_base) 823 em_dma_free(adapter, &adapter->rxdma); 824 825 /* Free top level busdma tag */ 826 if (adapter->parent_dtag != NULL) 827 bus_dma_tag_destroy(adapter->parent_dtag); 828 829 /* Free sysctl tree */ 830 if (adapter->sysctl_tree != NULL) 831 sysctl_ctx_free(&adapter->sysctl_ctx); 832 833 return (0); 834 } 835 836 static int 837 em_shutdown(device_t dev) 838 { 839 return em_suspend(dev); 840 } 841 842 static int 843 em_suspend(device_t dev) 844 { 845 struct adapter *adapter = device_get_softc(dev); 846 struct ifnet *ifp = &adapter->arpcom.ac_if; 847 848 lwkt_serialize_enter(ifp->if_serializer); 849 850 em_stop(adapter); 851 852 em_rel_mgmt(adapter); 853 854 if ((adapter->hw.mac.type == e1000_82573 || 855 adapter->hw.mac.type == e1000_ich8lan || 856 adapter->hw.mac.type == e1000_ich10lan || 857 adapter->hw.mac.type == e1000_ich9lan) && 858 e1000_check_mng_mode(&adapter->hw)) 859 em_rel_hw_control(adapter); 860 861 if (adapter->wol) { 862 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 863 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 864 em_enable_wol(dev); 865 } 866 867 lwkt_serialize_exit(ifp->if_serializer); 868 869 return bus_generic_suspend(dev); 870 } 871 872 static int 873 em_resume(device_t dev) 874 { 875 struct adapter *adapter = device_get_softc(dev); 876 struct ifnet *ifp = &adapter->arpcom.ac_if; 877 878 lwkt_serialize_enter(ifp->if_serializer); 879 880 em_init(adapter); 881 em_get_mgmt(adapter); 882 if_devstart(ifp); 883 884 lwkt_serialize_exit(ifp->if_serializer); 885 886 return bus_generic_resume(dev); 887 } 888 889 static void 890 em_start(struct ifnet *ifp) 891 { 892 struct adapter *adapter = ifp->if_softc; 893 struct mbuf *m_head; 894 895 ASSERT_SERIALIZED(ifp->if_serializer); 896 897 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 898 return; 899 900 if (!adapter->link_active) { 901 ifq_purge(&ifp->if_snd); 902 return; 903 } 904 905 while (!ifq_is_empty(&ifp->if_snd)) { 906 /* Now do we at least have a minimal? */ 907 if (EM_IS_OACTIVE(adapter)) { 908 em_tx_collect(adapter); 909 if (EM_IS_OACTIVE(adapter)) { 910 ifp->if_flags |= IFF_OACTIVE; 911 adapter->no_tx_desc_avail1++; 912 break; 913 } 914 } 915 916 logif(pkt_txqueue); 917 m_head = ifq_dequeue(&ifp->if_snd, NULL); 918 if (m_head == NULL) 919 break; 920 921 if (em_encap(adapter, &m_head)) { 922 ifp->if_oerrors++; 923 em_tx_collect(adapter); 924 continue; 925 } 926 927 /* Send a copy of the frame to the BPF listener */ 928 ETHER_BPF_MTAP(ifp, m_head); 929 930 /* Set timeout in case hardware has problems transmitting. */ 931 ifp->if_timer = EM_TX_TIMEOUT; 932 } 933 } 934 935 static int 936 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 937 { 938 struct adapter *adapter = ifp->if_softc; 939 struct ifreq *ifr = (struct ifreq *)data; 940 uint16_t eeprom_data = 0; 941 int max_frame_size, mask, reinit; 942 int error = 0; 943 944 ASSERT_SERIALIZED(ifp->if_serializer); 945 946 switch (command) { 947 case SIOCSIFMTU: 948 switch (adapter->hw.mac.type) { 949 case e1000_82573: 950 /* 951 * 82573 only supports jumbo frames 952 * if ASPM is disabled. 953 */ 954 e1000_read_nvm(&adapter->hw, 955 NVM_INIT_3GIO_3, 1, &eeprom_data); 956 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 957 max_frame_size = ETHER_MAX_LEN; 958 break; 959 } 960 /* FALL THROUGH */ 961 962 /* Limit Jumbo Frame size */ 963 case e1000_82571: 964 case e1000_82572: 965 case e1000_ich9lan: 966 case e1000_ich10lan: 967 case e1000_82574: 968 case e1000_80003es2lan: 969 max_frame_size = 9234; 970 break; 971 972 /* Adapters that do not support jumbo frames */ 973 case e1000_82542: 974 case e1000_ich8lan: 975 max_frame_size = ETHER_MAX_LEN; 976 break; 977 978 default: 979 max_frame_size = MAX_JUMBO_FRAME_SIZE; 980 break; 981 } 982 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 983 ETHER_CRC_LEN) { 984 error = EINVAL; 985 break; 986 } 987 988 ifp->if_mtu = ifr->ifr_mtu; 989 adapter->max_frame_size = 990 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 991 992 if (ifp->if_flags & IFF_RUNNING) 993 em_init(adapter); 994 break; 995 996 case SIOCSIFFLAGS: 997 if (ifp->if_flags & IFF_UP) { 998 if ((ifp->if_flags & IFF_RUNNING)) { 999 if ((ifp->if_flags ^ adapter->if_flags) & 1000 (IFF_PROMISC | IFF_ALLMULTI)) { 1001 em_disable_promisc(adapter); 1002 em_set_promisc(adapter); 1003 } 1004 } else { 1005 em_init(adapter); 1006 } 1007 } else if (ifp->if_flags & IFF_RUNNING) { 1008 em_stop(adapter); 1009 } 1010 adapter->if_flags = ifp->if_flags; 1011 break; 1012 1013 case SIOCADDMULTI: 1014 case SIOCDELMULTI: 1015 if (ifp->if_flags & IFF_RUNNING) { 1016 em_disable_intr(adapter); 1017 em_set_multi(adapter); 1018 if (adapter->hw.mac.type == e1000_82542 && 1019 adapter->hw.revision_id == E1000_REVISION_2) 1020 em_init_rx_unit(adapter); 1021 #ifdef DEVICE_POLLING 1022 if (!(ifp->if_flags & IFF_POLLING)) 1023 #endif 1024 em_enable_intr(adapter); 1025 } 1026 break; 1027 1028 case SIOCSIFMEDIA: 1029 /* Check SOL/IDER usage */ 1030 if (e1000_check_reset_block(&adapter->hw)) { 1031 device_printf(adapter->dev, "Media change is" 1032 " blocked due to SOL/IDER session.\n"); 1033 break; 1034 } 1035 /* FALL THROUGH */ 1036 1037 case SIOCGIFMEDIA: 1038 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1039 break; 1040 1041 case SIOCSIFCAP: 1042 reinit = 0; 1043 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1044 if (mask & IFCAP_HWCSUM) { 1045 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 1046 reinit = 1; 1047 } 1048 if (mask & IFCAP_VLAN_HWTAGGING) { 1049 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1050 reinit = 1; 1051 } 1052 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1053 em_init(adapter); 1054 break; 1055 1056 default: 1057 error = ether_ioctl(ifp, command, data); 1058 break; 1059 } 1060 return (error); 1061 } 1062 1063 static void 1064 em_watchdog(struct ifnet *ifp) 1065 { 1066 struct adapter *adapter = ifp->if_softc; 1067 1068 ASSERT_SERIALIZED(ifp->if_serializer); 1069 1070 /* 1071 * The timer is set to 5 every time start queues a packet. 1072 * Then txeof keeps resetting it as long as it cleans at 1073 * least one descriptor. 1074 * Finally, anytime all descriptors are clean the timer is 1075 * set to 0. 1076 */ 1077 1078 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1079 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1080 /* 1081 * If we reach here, all TX jobs are completed and 1082 * the TX engine should have been idled for some time. 1083 * We don't need to call if_devstart() here. 1084 */ 1085 ifp->if_flags &= ~IFF_OACTIVE; 1086 ifp->if_timer = 0; 1087 return; 1088 } 1089 1090 /* 1091 * If we are in this routine because of pause frames, then 1092 * don't reset the hardware. 1093 */ 1094 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1095 E1000_STATUS_TXOFF) { 1096 ifp->if_timer = EM_TX_TIMEOUT; 1097 return; 1098 } 1099 1100 if (e1000_check_for_link(&adapter->hw) == 0) 1101 if_printf(ifp, "watchdog timeout -- resetting\n"); 1102 1103 ifp->if_oerrors++; 1104 adapter->watchdog_events++; 1105 1106 em_init(adapter); 1107 1108 if (!ifq_is_empty(&ifp->if_snd)) 1109 if_devstart(ifp); 1110 } 1111 1112 static void 1113 em_init(void *xsc) 1114 { 1115 struct adapter *adapter = xsc; 1116 struct ifnet *ifp = &adapter->arpcom.ac_if; 1117 device_t dev = adapter->dev; 1118 uint32_t pba; 1119 1120 ASSERT_SERIALIZED(ifp->if_serializer); 1121 1122 em_stop(adapter); 1123 1124 /* 1125 * Packet Buffer Allocation (PBA) 1126 * Writing PBA sets the receive portion of the buffer 1127 * the remainder is used for the transmit buffer. 1128 * 1129 * Devices before the 82547 had a Packet Buffer of 64K. 1130 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1131 * After the 82547 the buffer was reduced to 40K. 1132 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1133 * Note: default does not leave enough room for Jumbo Frame >10k. 1134 */ 1135 switch (adapter->hw.mac.type) { 1136 case e1000_82547: 1137 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1138 if (adapter->max_frame_size > 8192) 1139 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1140 else 1141 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1142 adapter->tx_fifo_head = 0; 1143 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1144 adapter->tx_fifo_size = 1145 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1146 break; 1147 1148 /* Total Packet Buffer on these is 48K */ 1149 case e1000_82571: 1150 case e1000_82572: 1151 case e1000_80003es2lan: 1152 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1153 break; 1154 1155 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1156 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1157 break; 1158 1159 case e1000_82574: 1160 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1161 break; 1162 1163 case e1000_ich9lan: 1164 case e1000_ich10lan: 1165 #define E1000_PBA_10K 0x000A 1166 pba = E1000_PBA_10K; 1167 break; 1168 1169 case e1000_ich8lan: 1170 pba = E1000_PBA_8K; 1171 break; 1172 1173 default: 1174 /* Devices before 82547 had a Packet Buffer of 64K. */ 1175 if (adapter->max_frame_size > 8192) 1176 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1177 else 1178 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1179 } 1180 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1181 1182 /* Get the latest mac address, User can use a LAA */ 1183 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1184 1185 /* Put the address into the Receive Address Array */ 1186 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1187 1188 /* 1189 * With the 82571 adapter, RAR[0] may be overwritten 1190 * when the other port is reset, we make a duplicate 1191 * in RAR[14] for that eventuality, this assures 1192 * the interface continues to function. 1193 */ 1194 if (adapter->hw.mac.type == e1000_82571) { 1195 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1196 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1197 E1000_RAR_ENTRIES - 1); 1198 } 1199 1200 /* Initialize the hardware */ 1201 if (em_hw_init(adapter)) { 1202 device_printf(dev, "Unable to initialize the hardware\n"); 1203 /* XXX em_stop()? */ 1204 return; 1205 } 1206 em_update_link_status(adapter); 1207 1208 /* Setup VLAN support, basic and offload if available */ 1209 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1210 1211 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1212 uint32_t ctrl; 1213 1214 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1215 ctrl |= E1000_CTRL_VME; 1216 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1217 } 1218 1219 /* Set hardware offload abilities */ 1220 if (ifp->if_capenable & IFCAP_TXCSUM) 1221 ifp->if_hwassist = EM_CSUM_FEATURES; 1222 else 1223 ifp->if_hwassist = 0; 1224 1225 /* Configure for OS presence */ 1226 em_get_mgmt(adapter); 1227 1228 /* Prepare transmit descriptors and buffers */ 1229 em_init_tx_ring(adapter); 1230 em_init_tx_unit(adapter); 1231 1232 /* Setup Multicast table */ 1233 em_set_multi(adapter); 1234 1235 /* Prepare receive descriptors and buffers */ 1236 if (em_init_rx_ring(adapter)) { 1237 device_printf(dev, "Could not setup receive structures\n"); 1238 em_stop(adapter); 1239 return; 1240 } 1241 em_init_rx_unit(adapter); 1242 1243 /* Don't lose promiscuous settings */ 1244 em_set_promisc(adapter); 1245 1246 ifp->if_flags |= IFF_RUNNING; 1247 ifp->if_flags &= ~IFF_OACTIVE; 1248 1249 callout_reset(&adapter->timer, hz, em_timer, adapter); 1250 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1251 1252 /* MSI/X configuration for 82574 */ 1253 if (adapter->hw.mac.type == e1000_82574) { 1254 int tmp; 1255 1256 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1257 tmp |= E1000_CTRL_EXT_PBA_CLR; 1258 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1259 /* 1260 * Set the IVAR - interrupt vector routing. 1261 * Each nibble represents a vector, high bit 1262 * is enable, other 3 bits are the MSIX table 1263 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1264 * Link (other) to 2, hence the magic number. 1265 */ 1266 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1267 } 1268 1269 #ifdef DEVICE_POLLING 1270 /* 1271 * Only enable interrupts if we are not polling, make sure 1272 * they are off otherwise. 1273 */ 1274 if (ifp->if_flags & IFF_POLLING) 1275 em_disable_intr(adapter); 1276 else 1277 #endif /* DEVICE_POLLING */ 1278 em_enable_intr(adapter); 1279 1280 /* Don't reset the phy next time init gets called */ 1281 adapter->hw.phy.reset_disable = TRUE; 1282 } 1283 1284 #ifdef DEVICE_POLLING 1285 1286 static void 1287 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1288 { 1289 struct adapter *adapter = ifp->if_softc; 1290 uint32_t reg_icr; 1291 1292 ASSERT_SERIALIZED(ifp->if_serializer); 1293 1294 switch (cmd) { 1295 case POLL_REGISTER: 1296 em_disable_intr(adapter); 1297 break; 1298 1299 case POLL_DEREGISTER: 1300 em_enable_intr(adapter); 1301 break; 1302 1303 case POLL_AND_CHECK_STATUS: 1304 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1305 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1306 callout_stop(&adapter->timer); 1307 adapter->hw.mac.get_link_status = 1; 1308 em_update_link_status(adapter); 1309 callout_reset(&adapter->timer, hz, em_timer, adapter); 1310 } 1311 /* FALL THROUGH */ 1312 case POLL_ONLY: 1313 if (ifp->if_flags & IFF_RUNNING) { 1314 em_rxeof(adapter, count); 1315 em_txeof(adapter); 1316 1317 if (!ifq_is_empty(&ifp->if_snd)) 1318 if_devstart(ifp); 1319 } 1320 break; 1321 } 1322 } 1323 1324 #endif /* DEVICE_POLLING */ 1325 1326 static void 1327 em_intr(void *xsc) 1328 { 1329 struct adapter *adapter = xsc; 1330 struct ifnet *ifp = &adapter->arpcom.ac_if; 1331 uint32_t reg_icr; 1332 1333 logif(intr_beg); 1334 ASSERT_SERIALIZED(ifp->if_serializer); 1335 1336 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1337 1338 if ((adapter->hw.mac.type >= e1000_82571 && 1339 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1340 reg_icr == 0) { 1341 logif(intr_end); 1342 return; 1343 } 1344 1345 /* 1346 * XXX: some laptops trigger several spurious interrupts 1347 * on em(4) when in the resume cycle. The ICR register 1348 * reports all-ones value in this case. Processing such 1349 * interrupts would lead to a freeze. I don't know why. 1350 */ 1351 if (reg_icr == 0xffffffff) { 1352 logif(intr_end); 1353 return; 1354 } 1355 1356 if (ifp->if_flags & IFF_RUNNING) { 1357 if (reg_icr & 1358 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1359 em_rxeof(adapter, -1); 1360 if (reg_icr & E1000_ICR_TXDW) { 1361 em_txeof(adapter); 1362 if (!ifq_is_empty(&ifp->if_snd)) 1363 if_devstart(ifp); 1364 } 1365 } 1366 1367 /* Link status change */ 1368 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1369 callout_stop(&adapter->timer); 1370 adapter->hw.mac.get_link_status = 1; 1371 em_update_link_status(adapter); 1372 1373 /* Deal with TX cruft when link lost */ 1374 em_tx_purge(adapter); 1375 1376 callout_reset(&adapter->timer, hz, em_timer, adapter); 1377 } 1378 1379 if (reg_icr & E1000_ICR_RXO) 1380 adapter->rx_overruns++; 1381 1382 logif(intr_end); 1383 } 1384 1385 static void 1386 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1387 { 1388 struct adapter *adapter = ifp->if_softc; 1389 u_char fiber_type = IFM_1000_SX; 1390 1391 ASSERT_SERIALIZED(ifp->if_serializer); 1392 1393 em_update_link_status(adapter); 1394 1395 ifmr->ifm_status = IFM_AVALID; 1396 ifmr->ifm_active = IFM_ETHER; 1397 1398 if (!adapter->link_active) 1399 return; 1400 1401 ifmr->ifm_status |= IFM_ACTIVE; 1402 1403 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1404 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1405 if (adapter->hw.mac.type == e1000_82545) 1406 fiber_type = IFM_1000_LX; 1407 ifmr->ifm_active |= fiber_type | IFM_FDX; 1408 } else { 1409 switch (adapter->link_speed) { 1410 case 10: 1411 ifmr->ifm_active |= IFM_10_T; 1412 break; 1413 case 100: 1414 ifmr->ifm_active |= IFM_100_TX; 1415 break; 1416 1417 case 1000: 1418 ifmr->ifm_active |= IFM_1000_T; 1419 break; 1420 } 1421 if (adapter->link_duplex == FULL_DUPLEX) 1422 ifmr->ifm_active |= IFM_FDX; 1423 else 1424 ifmr->ifm_active |= IFM_HDX; 1425 } 1426 } 1427 1428 static int 1429 em_media_change(struct ifnet *ifp) 1430 { 1431 struct adapter *adapter = ifp->if_softc; 1432 struct ifmedia *ifm = &adapter->media; 1433 1434 ASSERT_SERIALIZED(ifp->if_serializer); 1435 1436 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1437 return (EINVAL); 1438 1439 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1440 case IFM_AUTO: 1441 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1442 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1443 break; 1444 1445 case IFM_1000_LX: 1446 case IFM_1000_SX: 1447 case IFM_1000_T: 1448 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1449 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1450 break; 1451 1452 case IFM_100_TX: 1453 adapter->hw.mac.autoneg = FALSE; 1454 adapter->hw.phy.autoneg_advertised = 0; 1455 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1456 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1457 else 1458 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1459 break; 1460 1461 case IFM_10_T: 1462 adapter->hw.mac.autoneg = FALSE; 1463 adapter->hw.phy.autoneg_advertised = 0; 1464 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1465 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1466 else 1467 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1468 break; 1469 1470 default: 1471 if_printf(ifp, "Unsupported media type\n"); 1472 break; 1473 } 1474 1475 /* 1476 * As the speed/duplex settings my have changed we need to 1477 * reset the PHY. 1478 */ 1479 adapter->hw.phy.reset_disable = FALSE; 1480 1481 em_init(adapter); 1482 1483 return (0); 1484 } 1485 1486 static int 1487 em_encap(struct adapter *adapter, struct mbuf **m_headp) 1488 { 1489 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1490 bus_dmamap_t map; 1491 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1492 struct e1000_tx_desc *ctxd = NULL; 1493 struct mbuf *m_head = *m_headp; 1494 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1495 int maxsegs, nsegs, i, j, first, last = 0, error; 1496 1497 if (m_head->m_len < EM_TXCSUM_MINHL && 1498 (m_head->m_flags & EM_CSUM_FEATURES)) { 1499 /* 1500 * Make sure that ethernet header and ip.ip_hl are in 1501 * contiguous memory, since if TXCSUM is enabled, later 1502 * TX context descriptor's setup need to access ip.ip_hl. 1503 */ 1504 error = em_txcsum_pullup(adapter, m_headp); 1505 if (error) { 1506 KKASSERT(*m_headp == NULL); 1507 return error; 1508 } 1509 m_head = *m_headp; 1510 } 1511 1512 txd_upper = txd_lower = 0; 1513 txd_used = 0; 1514 1515 /* 1516 * Capture the first descriptor index, this descriptor 1517 * will have the index of the EOP which is the only one 1518 * that now gets a DONE bit writeback. 1519 */ 1520 first = adapter->next_avail_tx_desc; 1521 tx_buffer = &adapter->tx_buffer_area[first]; 1522 tx_buffer_mapped = tx_buffer; 1523 map = tx_buffer->map; 1524 1525 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1526 KASSERT(maxsegs >= adapter->spare_tx_desc, 1527 ("not enough spare TX desc\n")); 1528 if (adapter->pcix_82544) { 1529 /* Half it; see the comment in em_attach() */ 1530 maxsegs >>= 1; 1531 } 1532 if (maxsegs > EM_MAX_SCATTER) 1533 maxsegs = EM_MAX_SCATTER; 1534 1535 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1536 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1537 if (error) { 1538 if (error == ENOBUFS) 1539 adapter->mbuf_alloc_failed++; 1540 else 1541 adapter->no_tx_dma_setup++; 1542 1543 m_freem(*m_headp); 1544 *m_headp = NULL; 1545 return error; 1546 } 1547 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1548 1549 m_head = *m_headp; 1550 adapter->tx_nsegs += nsegs; 1551 1552 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1553 /* TX csum offloading will consume one TX desc */ 1554 adapter->tx_nsegs += em_txcsum(adapter, m_head, 1555 &txd_upper, &txd_lower); 1556 } 1557 i = adapter->next_avail_tx_desc; 1558 1559 /* Set up our transmit descriptors */ 1560 for (j = 0; j < nsegs; j++) { 1561 /* If adapter is 82544 and on PCIX bus */ 1562 if(adapter->pcix_82544) { 1563 DESC_ARRAY desc_array; 1564 uint32_t array_elements, counter; 1565 1566 /* 1567 * Check the Address and Length combination and 1568 * split the data accordingly 1569 */ 1570 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1571 segs[j].ds_len, &desc_array); 1572 for (counter = 0; counter < array_elements; counter++) { 1573 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1574 1575 tx_buffer = &adapter->tx_buffer_area[i]; 1576 ctxd = &adapter->tx_desc_base[i]; 1577 1578 ctxd->buffer_addr = htole64( 1579 desc_array.descriptor[counter].address); 1580 ctxd->lower.data = htole32( 1581 E1000_TXD_CMD_IFCS | txd_lower | 1582 desc_array.descriptor[counter].length); 1583 ctxd->upper.data = htole32(txd_upper); 1584 1585 last = i; 1586 if (++i == adapter->num_tx_desc) 1587 i = 0; 1588 1589 txd_used++; 1590 } 1591 } else { 1592 tx_buffer = &adapter->tx_buffer_area[i]; 1593 ctxd = &adapter->tx_desc_base[i]; 1594 1595 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1596 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1597 txd_lower | segs[j].ds_len); 1598 ctxd->upper.data = htole32(txd_upper); 1599 1600 last = i; 1601 if (++i == adapter->num_tx_desc) 1602 i = 0; 1603 } 1604 } 1605 1606 adapter->next_avail_tx_desc = i; 1607 if (adapter->pcix_82544) { 1608 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1609 adapter->num_tx_desc_avail -= txd_used; 1610 } else { 1611 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1612 adapter->num_tx_desc_avail -= nsegs; 1613 } 1614 1615 /* Handle VLAN tag */ 1616 if (m_head->m_flags & M_VLANTAG) { 1617 /* Set the vlan id. */ 1618 ctxd->upper.fields.special = 1619 htole16(m_head->m_pkthdr.ether_vlantag); 1620 1621 /* Tell hardware to add tag */ 1622 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1623 } 1624 1625 tx_buffer->m_head = m_head; 1626 tx_buffer_mapped->map = tx_buffer->map; 1627 tx_buffer->map = map; 1628 1629 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1630 adapter->tx_nsegs = 0; 1631 1632 /* 1633 * Report Status (RS) is turned on 1634 * every tx_int_nsegs descriptors. 1635 */ 1636 cmd = E1000_TXD_CMD_RS; 1637 1638 /* 1639 * Keep track of the descriptor, which will 1640 * be written back by hardware. 1641 */ 1642 adapter->tx_dd[adapter->tx_dd_tail] = last; 1643 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1644 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1645 } 1646 1647 /* 1648 * Last Descriptor of Packet needs End Of Packet (EOP) 1649 */ 1650 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1651 1652 /* 1653 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 1654 * that this frame is available to transmit. 1655 */ 1656 if (adapter->hw.mac.type == e1000_82547 && 1657 adapter->link_duplex == HALF_DUPLEX) { 1658 em_82547_move_tail_serialized(adapter); 1659 } else { 1660 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1661 if (adapter->hw.mac.type == e1000_82547) { 1662 em_82547_update_fifo_head(adapter, 1663 m_head->m_pkthdr.len); 1664 } 1665 } 1666 return (0); 1667 } 1668 1669 /* 1670 * 82547 workaround to avoid controller hang in half-duplex environment. 1671 * The workaround is to avoid queuing a large packet that would span 1672 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1673 * in this case. We do that only when FIFO is quiescent. 1674 */ 1675 static void 1676 em_82547_move_tail_serialized(struct adapter *adapter) 1677 { 1678 struct e1000_tx_desc *tx_desc; 1679 uint16_t hw_tdt, sw_tdt, length = 0; 1680 bool eop = 0; 1681 1682 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1683 1684 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1685 sw_tdt = adapter->next_avail_tx_desc; 1686 1687 while (hw_tdt != sw_tdt) { 1688 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1689 length += tx_desc->lower.flags.length; 1690 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1691 if (++hw_tdt == adapter->num_tx_desc) 1692 hw_tdt = 0; 1693 1694 if (eop) { 1695 if (em_82547_fifo_workaround(adapter, length)) { 1696 adapter->tx_fifo_wrk_cnt++; 1697 callout_reset(&adapter->tx_fifo_timer, 1, 1698 em_82547_move_tail, adapter); 1699 break; 1700 } 1701 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1702 em_82547_update_fifo_head(adapter, length); 1703 length = 0; 1704 } 1705 } 1706 } 1707 1708 static void 1709 em_82547_move_tail(void *xsc) 1710 { 1711 struct adapter *adapter = xsc; 1712 struct ifnet *ifp = &adapter->arpcom.ac_if; 1713 1714 lwkt_serialize_enter(ifp->if_serializer); 1715 em_82547_move_tail_serialized(adapter); 1716 lwkt_serialize_exit(ifp->if_serializer); 1717 } 1718 1719 static int 1720 em_82547_fifo_workaround(struct adapter *adapter, int len) 1721 { 1722 int fifo_space, fifo_pkt_len; 1723 1724 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1725 1726 if (adapter->link_duplex == HALF_DUPLEX) { 1727 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1728 1729 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1730 if (em_82547_tx_fifo_reset(adapter)) 1731 return (0); 1732 else 1733 return (1); 1734 } 1735 } 1736 return (0); 1737 } 1738 1739 static void 1740 em_82547_update_fifo_head(struct adapter *adapter, int len) 1741 { 1742 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1743 1744 /* tx_fifo_head is always 16 byte aligned */ 1745 adapter->tx_fifo_head += fifo_pkt_len; 1746 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1747 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1748 } 1749 1750 static int 1751 em_82547_tx_fifo_reset(struct adapter *adapter) 1752 { 1753 uint32_t tctl; 1754 1755 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1756 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1757 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1758 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1759 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1760 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1761 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1762 /* Disable TX unit */ 1763 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1764 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1765 tctl & ~E1000_TCTL_EN); 1766 1767 /* Reset FIFO pointers */ 1768 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1769 adapter->tx_head_addr); 1770 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1771 adapter->tx_head_addr); 1772 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1773 adapter->tx_head_addr); 1774 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1775 adapter->tx_head_addr); 1776 1777 /* Re-enable TX unit */ 1778 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1779 E1000_WRITE_FLUSH(&adapter->hw); 1780 1781 adapter->tx_fifo_head = 0; 1782 adapter->tx_fifo_reset_cnt++; 1783 1784 return (TRUE); 1785 } else { 1786 return (FALSE); 1787 } 1788 } 1789 1790 static void 1791 em_set_promisc(struct adapter *adapter) 1792 { 1793 struct ifnet *ifp = &adapter->arpcom.ac_if; 1794 uint32_t reg_rctl; 1795 1796 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1797 1798 if (ifp->if_flags & IFF_PROMISC) { 1799 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1800 /* Turn this on if you want to see bad packets */ 1801 if (em_debug_sbp) 1802 reg_rctl |= E1000_RCTL_SBP; 1803 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1804 } else if (ifp->if_flags & IFF_ALLMULTI) { 1805 reg_rctl |= E1000_RCTL_MPE; 1806 reg_rctl &= ~E1000_RCTL_UPE; 1807 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1808 } 1809 } 1810 1811 static void 1812 em_disable_promisc(struct adapter *adapter) 1813 { 1814 uint32_t reg_rctl; 1815 1816 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1817 1818 reg_rctl &= ~E1000_RCTL_UPE; 1819 reg_rctl &= ~E1000_RCTL_MPE; 1820 reg_rctl &= ~E1000_RCTL_SBP; 1821 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1822 } 1823 1824 static void 1825 em_set_multi(struct adapter *adapter) 1826 { 1827 struct ifnet *ifp = &adapter->arpcom.ac_if; 1828 struct ifmultiaddr *ifma; 1829 uint32_t reg_rctl = 0; 1830 uint8_t mta[512]; /* Largest MTS is 4096 bits */ 1831 int mcnt = 0; 1832 1833 if (adapter->hw.mac.type == e1000_82542 && 1834 adapter->hw.revision_id == E1000_REVISION_2) { 1835 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1836 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1837 e1000_pci_clear_mwi(&adapter->hw); 1838 reg_rctl |= E1000_RCTL_RST; 1839 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1840 msec_delay(5); 1841 } 1842 1843 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1844 if (ifma->ifma_addr->sa_family != AF_LINK) 1845 continue; 1846 1847 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1848 break; 1849 1850 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1851 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1852 mcnt++; 1853 } 1854 1855 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1856 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1857 reg_rctl |= E1000_RCTL_MPE; 1858 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1859 } else { 1860 e1000_update_mc_addr_list(&adapter->hw, mta, 1861 mcnt, 1, adapter->hw.mac.rar_entry_count); 1862 } 1863 1864 if (adapter->hw.mac.type == e1000_82542 && 1865 adapter->hw.revision_id == E1000_REVISION_2) { 1866 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1867 reg_rctl &= ~E1000_RCTL_RST; 1868 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1869 msec_delay(5); 1870 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1871 e1000_pci_set_mwi(&adapter->hw); 1872 } 1873 } 1874 1875 /* 1876 * This routine checks for link status and updates statistics. 1877 */ 1878 static void 1879 em_timer(void *xsc) 1880 { 1881 struct adapter *adapter = xsc; 1882 struct ifnet *ifp = &adapter->arpcom.ac_if; 1883 1884 lwkt_serialize_enter(ifp->if_serializer); 1885 1886 em_update_link_status(adapter); 1887 em_update_stats(adapter); 1888 1889 /* Reset LAA into RAR[0] on 82571 */ 1890 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 1891 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1892 1893 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1894 em_print_hw_stats(adapter); 1895 1896 em_smartspeed(adapter); 1897 1898 callout_reset(&adapter->timer, hz, em_timer, adapter); 1899 1900 lwkt_serialize_exit(ifp->if_serializer); 1901 } 1902 1903 static void 1904 em_update_link_status(struct adapter *adapter) 1905 { 1906 struct e1000_hw *hw = &adapter->hw; 1907 struct ifnet *ifp = &adapter->arpcom.ac_if; 1908 device_t dev = adapter->dev; 1909 uint32_t link_check = 0; 1910 1911 /* Get the cached link value or read phy for real */ 1912 switch (hw->phy.media_type) { 1913 case e1000_media_type_copper: 1914 if (hw->mac.get_link_status) { 1915 /* Do the work to read phy */ 1916 e1000_check_for_link(hw); 1917 link_check = !hw->mac.get_link_status; 1918 if (link_check) /* ESB2 fix */ 1919 e1000_cfg_on_link_up(hw); 1920 } else { 1921 link_check = TRUE; 1922 } 1923 break; 1924 1925 case e1000_media_type_fiber: 1926 e1000_check_for_link(hw); 1927 link_check = 1928 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1929 break; 1930 1931 case e1000_media_type_internal_serdes: 1932 e1000_check_for_link(hw); 1933 link_check = adapter->hw.mac.serdes_has_link; 1934 break; 1935 1936 case e1000_media_type_unknown: 1937 default: 1938 break; 1939 } 1940 1941 /* Now check for a transition */ 1942 if (link_check && adapter->link_active == 0) { 1943 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1944 &adapter->link_duplex); 1945 1946 /* 1947 * Check if we should enable/disable SPEED_MODE bit on 1948 * 82571/82572 1949 */ 1950 if (hw->mac.type == e1000_82571 || 1951 hw->mac.type == e1000_82572) { 1952 int tarc0; 1953 1954 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1955 if (adapter->link_speed != SPEED_1000) 1956 tarc0 &= ~SPEED_MODE_BIT; 1957 else 1958 tarc0 |= SPEED_MODE_BIT; 1959 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1960 } 1961 if (bootverbose) { 1962 device_printf(dev, "Link is up %d Mbps %s\n", 1963 adapter->link_speed, 1964 ((adapter->link_duplex == FULL_DUPLEX) ? 1965 "Full Duplex" : "Half Duplex")); 1966 } 1967 adapter->link_active = 1; 1968 adapter->smartspeed = 0; 1969 ifp->if_baudrate = adapter->link_speed * 1000000; 1970 ifp->if_link_state = LINK_STATE_UP; 1971 if_link_state_change(ifp); 1972 } else if (!link_check && adapter->link_active == 1) { 1973 ifp->if_baudrate = adapter->link_speed = 0; 1974 adapter->link_duplex = 0; 1975 if (bootverbose) 1976 device_printf(dev, "Link is Down\n"); 1977 adapter->link_active = 0; 1978 #if 0 1979 /* Link down, disable watchdog */ 1980 if->if_timer = 0; 1981 #endif 1982 ifp->if_link_state = LINK_STATE_DOWN; 1983 if_link_state_change(ifp); 1984 } 1985 } 1986 1987 static void 1988 em_stop(struct adapter *adapter) 1989 { 1990 struct ifnet *ifp = &adapter->arpcom.ac_if; 1991 int i; 1992 1993 ASSERT_SERIALIZED(ifp->if_serializer); 1994 1995 em_disable_intr(adapter); 1996 1997 callout_stop(&adapter->timer); 1998 callout_stop(&adapter->tx_fifo_timer); 1999 2000 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2001 ifp->if_timer = 0; 2002 2003 e1000_reset_hw(&adapter->hw); 2004 if (adapter->hw.mac.type >= e1000_82544) 2005 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2006 2007 for (i = 0; i < adapter->num_tx_desc; i++) { 2008 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2009 2010 if (tx_buffer->m_head != NULL) { 2011 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2012 m_freem(tx_buffer->m_head); 2013 tx_buffer->m_head = NULL; 2014 } 2015 } 2016 2017 for (i = 0; i < adapter->num_rx_desc; i++) { 2018 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2019 2020 if (rx_buffer->m_head != NULL) { 2021 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2022 m_freem(rx_buffer->m_head); 2023 rx_buffer->m_head = NULL; 2024 } 2025 } 2026 2027 if (adapter->fmp != NULL) 2028 m_freem(adapter->fmp); 2029 adapter->fmp = NULL; 2030 adapter->lmp = NULL; 2031 2032 adapter->csum_flags = 0; 2033 adapter->csum_ehlen = 0; 2034 adapter->csum_iphlen = 0; 2035 2036 adapter->tx_dd_head = 0; 2037 adapter->tx_dd_tail = 0; 2038 adapter->tx_nsegs = 0; 2039 } 2040 2041 static int 2042 em_get_hw_info(struct adapter *adapter) 2043 { 2044 device_t dev = adapter->dev; 2045 2046 /* Save off the information about this board */ 2047 adapter->hw.vendor_id = pci_get_vendor(dev); 2048 adapter->hw.device_id = pci_get_device(dev); 2049 adapter->hw.revision_id = pci_get_revid(dev); 2050 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2051 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2052 2053 /* Do Shared Code Init and Setup */ 2054 if (e1000_set_mac_type(&adapter->hw)) 2055 return ENXIO; 2056 return 0; 2057 } 2058 2059 static int 2060 em_alloc_pci_res(struct adapter *adapter) 2061 { 2062 device_t dev = adapter->dev; 2063 int val, rid; 2064 2065 /* Enable bus mastering */ 2066 pci_enable_busmaster(dev); 2067 2068 adapter->memory_rid = EM_BAR_MEM; 2069 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2070 &adapter->memory_rid, RF_ACTIVE); 2071 if (adapter->memory == NULL) { 2072 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2073 return (ENXIO); 2074 } 2075 adapter->osdep.mem_bus_space_tag = 2076 rman_get_bustag(adapter->memory); 2077 adapter->osdep.mem_bus_space_handle = 2078 rman_get_bushandle(adapter->memory); 2079 2080 /* XXX This is quite goofy, it is not actually used */ 2081 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2082 2083 /* Only older adapters use IO mapping */ 2084 if (adapter->hw.mac.type > e1000_82543 && 2085 adapter->hw.mac.type < e1000_82571) { 2086 /* Figure our where our IO BAR is ? */ 2087 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2088 val = pci_read_config(dev, rid, 4); 2089 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2090 adapter->io_rid = rid; 2091 break; 2092 } 2093 rid += 4; 2094 /* check for 64bit BAR */ 2095 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2096 rid += 4; 2097 } 2098 if (rid >= PCIR_CARDBUSCIS) { 2099 device_printf(dev, "Unable to locate IO BAR\n"); 2100 return (ENXIO); 2101 } 2102 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2103 &adapter->io_rid, RF_ACTIVE); 2104 if (adapter->ioport == NULL) { 2105 device_printf(dev, "Unable to allocate bus resource: " 2106 "ioport\n"); 2107 return (ENXIO); 2108 } 2109 adapter->hw.io_base = 0; 2110 adapter->osdep.io_bus_space_tag = 2111 rman_get_bustag(adapter->ioport); 2112 adapter->osdep.io_bus_space_handle = 2113 rman_get_bushandle(adapter->ioport); 2114 } 2115 2116 adapter->intr_rid = 0; 2117 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2118 &adapter->intr_rid, 2119 RF_SHAREABLE | RF_ACTIVE); 2120 if (adapter->intr_res == NULL) { 2121 device_printf(dev, "Unable to allocate bus resource: " 2122 "interrupt\n"); 2123 return (ENXIO); 2124 } 2125 2126 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2127 adapter->hw.back = &adapter->osdep; 2128 return (0); 2129 } 2130 2131 static void 2132 em_free_pci_res(struct adapter *adapter) 2133 { 2134 device_t dev = adapter->dev; 2135 2136 if (adapter->intr_res != NULL) { 2137 bus_release_resource(dev, SYS_RES_IRQ, 2138 adapter->intr_rid, adapter->intr_res); 2139 } 2140 2141 if (adapter->memory != NULL) { 2142 bus_release_resource(dev, SYS_RES_MEMORY, 2143 adapter->memory_rid, adapter->memory); 2144 } 2145 2146 if (adapter->flash != NULL) { 2147 bus_release_resource(dev, SYS_RES_MEMORY, 2148 adapter->flash_rid, adapter->flash); 2149 } 2150 2151 if (adapter->ioport != NULL) { 2152 bus_release_resource(dev, SYS_RES_IOPORT, 2153 adapter->io_rid, adapter->ioport); 2154 } 2155 } 2156 2157 static int 2158 em_hw_init(struct adapter *adapter) 2159 { 2160 device_t dev = adapter->dev; 2161 uint16_t rx_buffer_size; 2162 2163 /* Issue a global reset */ 2164 e1000_reset_hw(&adapter->hw); 2165 2166 /* Get control from any management/hw control */ 2167 if ((adapter->hw.mac.type == e1000_82573 || 2168 adapter->hw.mac.type == e1000_ich8lan || 2169 adapter->hw.mac.type == e1000_ich10lan || 2170 adapter->hw.mac.type == e1000_ich9lan) && 2171 e1000_check_mng_mode(&adapter->hw)) 2172 em_get_hw_control(adapter); 2173 2174 /* When hardware is reset, fifo_head is also reset */ 2175 adapter->tx_fifo_head = 0; 2176 2177 /* Set up smart power down as default off on newer adapters. */ 2178 if (!em_smart_pwr_down && 2179 (adapter->hw.mac.type == e1000_82571 || 2180 adapter->hw.mac.type == e1000_82572)) { 2181 uint16_t phy_tmp = 0; 2182 2183 /* Speed up time to link by disabling smart power down. */ 2184 e1000_read_phy_reg(&adapter->hw, 2185 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2186 phy_tmp &= ~IGP02E1000_PM_SPD; 2187 e1000_write_phy_reg(&adapter->hw, 2188 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2189 } 2190 2191 /* 2192 * These parameters control the automatic generation (Tx) and 2193 * response (Rx) to Ethernet PAUSE frames. 2194 * - High water mark should allow for at least two frames to be 2195 * received after sending an XOFF. 2196 * - Low water mark works best when it is very near the high water mark. 2197 * This allows the receiver to restart by sending XON when it has 2198 * drained a bit. Here we use an arbitary value of 1500 which will 2199 * restart after one full frame is pulled from the buffer. There 2200 * could be several smaller frames in the buffer and if so they will 2201 * not trigger the XON until their total number reduces the buffer 2202 * by 1500. 2203 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2204 */ 2205 rx_buffer_size = 2206 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2207 2208 adapter->hw.fc.high_water = rx_buffer_size - 2209 roundup2(adapter->max_frame_size, 1024); 2210 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2211 2212 if (adapter->hw.mac.type == e1000_80003es2lan) 2213 adapter->hw.fc.pause_time = 0xFFFF; 2214 else 2215 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2216 adapter->hw.fc.send_xon = TRUE; 2217 adapter->hw.fc.requested_mode = e1000_fc_full; 2218 2219 if (e1000_init_hw(&adapter->hw) < 0) { 2220 device_printf(dev, "Hardware Initialization Failed\n"); 2221 return (EIO); 2222 } 2223 2224 e1000_check_for_link(&adapter->hw); 2225 2226 return (0); 2227 } 2228 2229 static void 2230 em_setup_ifp(struct adapter *adapter) 2231 { 2232 struct ifnet *ifp = &adapter->arpcom.ac_if; 2233 2234 if_initname(ifp, device_get_name(adapter->dev), 2235 device_get_unit(adapter->dev)); 2236 ifp->if_softc = adapter; 2237 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2238 ifp->if_init = em_init; 2239 ifp->if_ioctl = em_ioctl; 2240 ifp->if_start = em_start; 2241 #ifdef DEVICE_POLLING 2242 ifp->if_poll = em_poll; 2243 #endif 2244 ifp->if_watchdog = em_watchdog; 2245 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2246 ifq_set_ready(&ifp->if_snd); 2247 2248 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2249 2250 if (adapter->hw.mac.type >= e1000_82543) 2251 ifp->if_capabilities = IFCAP_HWCSUM; 2252 2253 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2254 ifp->if_capenable = ifp->if_capabilities; 2255 2256 if (ifp->if_capenable & IFCAP_TXCSUM) 2257 ifp->if_hwassist = EM_CSUM_FEATURES; 2258 2259 /* 2260 * Tell the upper layer(s) we support long frames. 2261 */ 2262 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2263 2264 /* 2265 * Specify the media types supported by this adapter and register 2266 * callbacks to update media and link information 2267 */ 2268 ifmedia_init(&adapter->media, IFM_IMASK, 2269 em_media_change, em_media_status); 2270 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2271 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2272 u_char fiber_type = IFM_1000_SX; /* default type */ 2273 2274 if (adapter->hw.mac.type == e1000_82545) 2275 fiber_type = IFM_1000_LX; 2276 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2277 0, NULL); 2278 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2279 } else { 2280 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2281 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2282 0, NULL); 2283 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2284 0, NULL); 2285 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2286 0, NULL); 2287 if (adapter->hw.phy.type != e1000_phy_ife) { 2288 ifmedia_add(&adapter->media, 2289 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2290 ifmedia_add(&adapter->media, 2291 IFM_ETHER | IFM_1000_T, 0, NULL); 2292 } 2293 } 2294 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2295 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2296 } 2297 2298 2299 /* 2300 * Workaround for SmartSpeed on 82541 and 82547 controllers 2301 */ 2302 static void 2303 em_smartspeed(struct adapter *adapter) 2304 { 2305 uint16_t phy_tmp; 2306 2307 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2308 adapter->hw.mac.autoneg == 0 || 2309 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2310 return; 2311 2312 if (adapter->smartspeed == 0) { 2313 /* 2314 * If Master/Slave config fault is asserted twice, 2315 * we assume back-to-back 2316 */ 2317 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2318 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2319 return; 2320 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2321 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2322 e1000_read_phy_reg(&adapter->hw, 2323 PHY_1000T_CTRL, &phy_tmp); 2324 if (phy_tmp & CR_1000T_MS_ENABLE) { 2325 phy_tmp &= ~CR_1000T_MS_ENABLE; 2326 e1000_write_phy_reg(&adapter->hw, 2327 PHY_1000T_CTRL, phy_tmp); 2328 adapter->smartspeed++; 2329 if (adapter->hw.mac.autoneg && 2330 !e1000_phy_setup_autoneg(&adapter->hw) && 2331 !e1000_read_phy_reg(&adapter->hw, 2332 PHY_CONTROL, &phy_tmp)) { 2333 phy_tmp |= MII_CR_AUTO_NEG_EN | 2334 MII_CR_RESTART_AUTO_NEG; 2335 e1000_write_phy_reg(&adapter->hw, 2336 PHY_CONTROL, phy_tmp); 2337 } 2338 } 2339 } 2340 return; 2341 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2342 /* If still no link, perhaps using 2/3 pair cable */ 2343 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2344 phy_tmp |= CR_1000T_MS_ENABLE; 2345 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2346 if (adapter->hw.mac.autoneg && 2347 !e1000_phy_setup_autoneg(&adapter->hw) && 2348 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2349 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2350 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2351 } 2352 } 2353 2354 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2355 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2356 adapter->smartspeed = 0; 2357 } 2358 2359 static int 2360 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2361 struct em_dma_alloc *dma) 2362 { 2363 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2364 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2365 &dma->dma_tag, &dma->dma_map, 2366 &dma->dma_paddr); 2367 if (dma->dma_vaddr == NULL) 2368 return ENOMEM; 2369 else 2370 return 0; 2371 } 2372 2373 static void 2374 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2375 { 2376 if (dma->dma_tag == NULL) 2377 return; 2378 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2379 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2380 bus_dma_tag_destroy(dma->dma_tag); 2381 } 2382 2383 static int 2384 em_create_tx_ring(struct adapter *adapter) 2385 { 2386 device_t dev = adapter->dev; 2387 struct em_buffer *tx_buffer; 2388 int error, i; 2389 2390 adapter->tx_buffer_area = 2391 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2392 M_DEVBUF, M_WAITOK | M_ZERO); 2393 2394 /* 2395 * Create DMA tags for tx buffers 2396 */ 2397 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2398 1, 0, /* alignment, bounds */ 2399 BUS_SPACE_MAXADDR, /* lowaddr */ 2400 BUS_SPACE_MAXADDR, /* highaddr */ 2401 NULL, NULL, /* filter, filterarg */ 2402 EM_TSO_SIZE, /* maxsize */ 2403 EM_MAX_SCATTER, /* nsegments */ 2404 EM_MAX_SEGSIZE, /* maxsegsize */ 2405 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2406 BUS_DMA_ONEBPAGE, /* flags */ 2407 &adapter->txtag); 2408 if (error) { 2409 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2410 kfree(adapter->tx_buffer_area, M_DEVBUF); 2411 adapter->tx_buffer_area = NULL; 2412 return error; 2413 } 2414 2415 /* 2416 * Create DMA maps for tx buffers 2417 */ 2418 for (i = 0; i < adapter->num_tx_desc; i++) { 2419 tx_buffer = &adapter->tx_buffer_area[i]; 2420 2421 error = bus_dmamap_create(adapter->txtag, 2422 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2423 &tx_buffer->map); 2424 if (error) { 2425 device_printf(dev, "Unable to create TX DMA map\n"); 2426 em_destroy_tx_ring(adapter, i); 2427 return error; 2428 } 2429 } 2430 return (0); 2431 } 2432 2433 static void 2434 em_init_tx_ring(struct adapter *adapter) 2435 { 2436 /* Clear the old ring contents */ 2437 bzero(adapter->tx_desc_base, 2438 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2439 2440 /* Reset state */ 2441 adapter->next_avail_tx_desc = 0; 2442 adapter->next_tx_to_clean = 0; 2443 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2444 } 2445 2446 static void 2447 em_init_tx_unit(struct adapter *adapter) 2448 { 2449 uint32_t tctl, tarc, tipg = 0; 2450 uint64_t bus_addr; 2451 2452 /* Setup the Base and Length of the Tx Descriptor Ring */ 2453 bus_addr = adapter->txdma.dma_paddr; 2454 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2455 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2456 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2457 (uint32_t)(bus_addr >> 32)); 2458 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2459 (uint32_t)bus_addr); 2460 /* Setup the HW Tx Head and Tail descriptor pointers */ 2461 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2462 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2463 2464 /* Set the default values for the Tx Inter Packet Gap timer */ 2465 switch (adapter->hw.mac.type) { 2466 case e1000_82542: 2467 tipg = DEFAULT_82542_TIPG_IPGT; 2468 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2469 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2470 break; 2471 2472 case e1000_80003es2lan: 2473 tipg = DEFAULT_82543_TIPG_IPGR1; 2474 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2475 E1000_TIPG_IPGR2_SHIFT; 2476 break; 2477 2478 default: 2479 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2480 adapter->hw.phy.media_type == 2481 e1000_media_type_internal_serdes) 2482 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2483 else 2484 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2485 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2486 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2487 break; 2488 } 2489 2490 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2491 2492 /* NOTE: 0 is not allowed for TIDV */ 2493 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2494 if(adapter->hw.mac.type >= e1000_82540) 2495 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2496 2497 if (adapter->hw.mac.type == e1000_82571 || 2498 adapter->hw.mac.type == e1000_82572) { 2499 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2500 tarc |= SPEED_MODE_BIT; 2501 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2502 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2503 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2504 tarc |= 1; 2505 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2506 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2507 tarc |= 1; 2508 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2509 } 2510 2511 /* Program the Transmit Control Register */ 2512 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2513 tctl &= ~E1000_TCTL_CT; 2514 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2515 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2516 2517 if (adapter->hw.mac.type >= e1000_82571) 2518 tctl |= E1000_TCTL_MULR; 2519 2520 /* This write will effectively turn on the transmit unit. */ 2521 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2522 } 2523 2524 static void 2525 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2526 { 2527 struct em_buffer *tx_buffer; 2528 int i; 2529 2530 if (adapter->tx_buffer_area == NULL) 2531 return; 2532 2533 for (i = 0; i < ndesc; i++) { 2534 tx_buffer = &adapter->tx_buffer_area[i]; 2535 2536 KKASSERT(tx_buffer->m_head == NULL); 2537 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2538 } 2539 bus_dma_tag_destroy(adapter->txtag); 2540 2541 kfree(adapter->tx_buffer_area, M_DEVBUF); 2542 adapter->tx_buffer_area = NULL; 2543 } 2544 2545 /* 2546 * The offload context needs to be set when we transfer the first 2547 * packet of a particular protocol (TCP/UDP). This routine has been 2548 * enhanced to deal with inserted VLAN headers. 2549 * 2550 * If the new packet's ether header length, ip header length and 2551 * csum offloading type are same as the previous packet, we should 2552 * avoid allocating a new csum context descriptor; mainly to take 2553 * advantage of the pipeline effect of the TX data read request. 2554 * 2555 * This function returns number of TX descrptors allocated for 2556 * csum context. 2557 */ 2558 static int 2559 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2560 uint32_t *txd_upper, uint32_t *txd_lower) 2561 { 2562 struct e1000_context_desc *TXD; 2563 struct em_buffer *tx_buffer; 2564 struct ether_vlan_header *eh; 2565 struct ip *ip; 2566 int curr_txd, ehdrlen, csum_flags; 2567 uint32_t cmd, hdr_len, ip_hlen; 2568 uint16_t etype; 2569 2570 /* 2571 * Determine where frame payload starts. 2572 * Jump over vlan headers if already present, 2573 * helpful for QinQ too. 2574 */ 2575 KASSERT(mp->m_len >= ETHER_HDR_LEN, 2576 ("em_txcsum_pullup is not called (eh)?\n")); 2577 eh = mtod(mp, struct ether_vlan_header *); 2578 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2579 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN, 2580 ("em_txcsum_pullup is not called (evh)?\n")); 2581 etype = ntohs(eh->evl_proto); 2582 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN; 2583 } else { 2584 etype = ntohs(eh->evl_encap_proto); 2585 ehdrlen = ETHER_HDR_LEN; 2586 } 2587 2588 /* 2589 * We only support TCP/UDP for IPv4 for the moment. 2590 * TODO: Support SCTP too when it hits the tree. 2591 */ 2592 if (etype != ETHERTYPE_IP) 2593 return 0; 2594 2595 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE, 2596 ("em_txcsum_pullup is not called (eh+ip_vhl)?\n")); 2597 2598 /* NOTE: We could only safely access ip.ip_vhl part */ 2599 ip = (struct ip *)(mp->m_data + ehdrlen); 2600 ip_hlen = ip->ip_hl << 2; 2601 2602 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2603 2604 if (adapter->csum_ehlen == ehdrlen && 2605 adapter->csum_iphlen == ip_hlen && 2606 adapter->csum_flags == csum_flags) { 2607 /* 2608 * Same csum offload context as the previous packets; 2609 * just return. 2610 */ 2611 *txd_upper = adapter->csum_txd_upper; 2612 *txd_lower = adapter->csum_txd_lower; 2613 return 0; 2614 } 2615 2616 /* 2617 * Setup a new csum offload context. 2618 */ 2619 2620 curr_txd = adapter->next_avail_tx_desc; 2621 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 2622 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2623 2624 cmd = 0; 2625 2626 /* Setup of IP header checksum. */ 2627 if (csum_flags & CSUM_IP) { 2628 /* 2629 * Start offset for header checksum calculation. 2630 * End offset for header checksum calculation. 2631 * Offset of place to put the checksum. 2632 */ 2633 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2634 TXD->lower_setup.ip_fields.ipcse = 2635 htole16(ehdrlen + ip_hlen - 1); 2636 TXD->lower_setup.ip_fields.ipcso = 2637 ehdrlen + offsetof(struct ip, ip_sum); 2638 cmd |= E1000_TXD_CMD_IP; 2639 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2640 } 2641 hdr_len = ehdrlen + ip_hlen; 2642 2643 if (csum_flags & CSUM_TCP) { 2644 /* 2645 * Start offset for payload checksum calculation. 2646 * End offset for payload checksum calculation. 2647 * Offset of place to put the checksum. 2648 */ 2649 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2650 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2651 TXD->upper_setup.tcp_fields.tucso = 2652 hdr_len + offsetof(struct tcphdr, th_sum); 2653 cmd |= E1000_TXD_CMD_TCP; 2654 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2655 } else if (csum_flags & CSUM_UDP) { 2656 /* 2657 * Start offset for header checksum calculation. 2658 * End offset for header checksum calculation. 2659 * Offset of place to put the checksum. 2660 */ 2661 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2662 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2663 TXD->upper_setup.tcp_fields.tucso = 2664 hdr_len + offsetof(struct udphdr, uh_sum); 2665 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2666 } 2667 2668 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2669 E1000_TXD_DTYP_D; /* Data descr */ 2670 2671 /* Save the information for this csum offloading context */ 2672 adapter->csum_ehlen = ehdrlen; 2673 adapter->csum_iphlen = ip_hlen; 2674 adapter->csum_flags = csum_flags; 2675 adapter->csum_txd_upper = *txd_upper; 2676 adapter->csum_txd_lower = *txd_lower; 2677 2678 TXD->tcp_seg_setup.data = htole32(0); 2679 TXD->cmd_and_length = 2680 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2681 2682 if (++curr_txd == adapter->num_tx_desc) 2683 curr_txd = 0; 2684 2685 KKASSERT(adapter->num_tx_desc_avail > 0); 2686 adapter->num_tx_desc_avail--; 2687 2688 adapter->next_avail_tx_desc = curr_txd; 2689 return 1; 2690 } 2691 2692 static int 2693 em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0) 2694 { 2695 struct mbuf *m = *m0; 2696 struct ether_header *eh; 2697 int len; 2698 2699 adapter->tx_csum_try_pullup++; 2700 2701 len = ETHER_HDR_LEN + EM_IPVHL_SIZE; 2702 2703 if (__predict_false(!M_WRITABLE(m))) { 2704 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2705 adapter->tx_csum_drop1++; 2706 m_freem(m); 2707 *m0 = NULL; 2708 return ENOBUFS; 2709 } 2710 eh = mtod(m, struct ether_header *); 2711 2712 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2713 len += EVL_ENCAPLEN; 2714 2715 if (m->m_len < len) { 2716 adapter->tx_csum_drop2++; 2717 m_freem(m); 2718 *m0 = NULL; 2719 return ENOBUFS; 2720 } 2721 return 0; 2722 } 2723 2724 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2725 adapter->tx_csum_pullup1++; 2726 m = m_pullup(m, ETHER_HDR_LEN); 2727 if (m == NULL) { 2728 adapter->tx_csum_pullup1_failed++; 2729 *m0 = NULL; 2730 return ENOBUFS; 2731 } 2732 *m0 = m; 2733 } 2734 eh = mtod(m, struct ether_header *); 2735 2736 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2737 len += EVL_ENCAPLEN; 2738 2739 if (m->m_len < len) { 2740 adapter->tx_csum_pullup2++; 2741 m = m_pullup(m, len); 2742 if (m == NULL) { 2743 adapter->tx_csum_pullup2_failed++; 2744 *m0 = NULL; 2745 return ENOBUFS; 2746 } 2747 *m0 = m; 2748 } 2749 return 0; 2750 } 2751 2752 static void 2753 em_txeof(struct adapter *adapter) 2754 { 2755 struct ifnet *ifp = &adapter->arpcom.ac_if; 2756 struct em_buffer *tx_buffer; 2757 int first, num_avail; 2758 2759 if (adapter->tx_dd_head == adapter->tx_dd_tail) 2760 return; 2761 2762 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2763 return; 2764 2765 num_avail = adapter->num_tx_desc_avail; 2766 first = adapter->next_tx_to_clean; 2767 2768 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 2769 struct e1000_tx_desc *tx_desc; 2770 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2771 2772 tx_desc = &adapter->tx_desc_base[dd_idx]; 2773 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2774 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2775 2776 if (++dd_idx == adapter->num_tx_desc) 2777 dd_idx = 0; 2778 2779 while (first != dd_idx) { 2780 logif(pkt_txclean); 2781 2782 num_avail++; 2783 2784 tx_buffer = &adapter->tx_buffer_area[first]; 2785 if (tx_buffer->m_head) { 2786 ifp->if_opackets++; 2787 bus_dmamap_unload(adapter->txtag, 2788 tx_buffer->map); 2789 m_freem(tx_buffer->m_head); 2790 tx_buffer->m_head = NULL; 2791 } 2792 2793 if (++first == adapter->num_tx_desc) 2794 first = 0; 2795 } 2796 } else { 2797 break; 2798 } 2799 } 2800 adapter->next_tx_to_clean = first; 2801 adapter->num_tx_desc_avail = num_avail; 2802 2803 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2804 adapter->tx_dd_head = 0; 2805 adapter->tx_dd_tail = 0; 2806 } 2807 2808 if (!EM_IS_OACTIVE(adapter)) { 2809 ifp->if_flags &= ~IFF_OACTIVE; 2810 2811 /* All clean, turn off the timer */ 2812 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2813 ifp->if_timer = 0; 2814 } 2815 } 2816 2817 static void 2818 em_tx_collect(struct adapter *adapter) 2819 { 2820 struct ifnet *ifp = &adapter->arpcom.ac_if; 2821 struct em_buffer *tx_buffer; 2822 int tdh, first, num_avail, dd_idx = -1; 2823 2824 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2825 return; 2826 2827 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 2828 if (tdh == adapter->next_tx_to_clean) 2829 return; 2830 2831 if (adapter->tx_dd_head != adapter->tx_dd_tail) 2832 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2833 2834 num_avail = adapter->num_tx_desc_avail; 2835 first = adapter->next_tx_to_clean; 2836 2837 while (first != tdh) { 2838 logif(pkt_txclean); 2839 2840 num_avail++; 2841 2842 tx_buffer = &adapter->tx_buffer_area[first]; 2843 if (tx_buffer->m_head) { 2844 ifp->if_opackets++; 2845 bus_dmamap_unload(adapter->txtag, 2846 tx_buffer->map); 2847 m_freem(tx_buffer->m_head); 2848 tx_buffer->m_head = NULL; 2849 } 2850 2851 if (first == dd_idx) { 2852 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2853 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2854 adapter->tx_dd_head = 0; 2855 adapter->tx_dd_tail = 0; 2856 dd_idx = -1; 2857 } else { 2858 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2859 } 2860 } 2861 2862 if (++first == adapter->num_tx_desc) 2863 first = 0; 2864 } 2865 adapter->next_tx_to_clean = first; 2866 adapter->num_tx_desc_avail = num_avail; 2867 2868 if (!EM_IS_OACTIVE(adapter)) { 2869 ifp->if_flags &= ~IFF_OACTIVE; 2870 2871 /* All clean, turn off the timer */ 2872 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2873 ifp->if_timer = 0; 2874 } 2875 } 2876 2877 /* 2878 * When Link is lost sometimes there is work still in the TX ring 2879 * which will result in a watchdog, rather than allow that do an 2880 * attempted cleanup and then reinit here. Note that this has been 2881 * seens mostly with fiber adapters. 2882 */ 2883 static void 2884 em_tx_purge(struct adapter *adapter) 2885 { 2886 struct ifnet *ifp = &adapter->arpcom.ac_if; 2887 2888 if (!adapter->link_active && ifp->if_timer) { 2889 em_tx_collect(adapter); 2890 if (ifp->if_timer) { 2891 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2892 ifp->if_timer = 0; 2893 em_init(adapter); 2894 } 2895 } 2896 } 2897 2898 static int 2899 em_newbuf(struct adapter *adapter, int i, int init) 2900 { 2901 struct mbuf *m; 2902 bus_dma_segment_t seg; 2903 bus_dmamap_t map; 2904 struct em_buffer *rx_buffer; 2905 int error, nseg; 2906 2907 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2908 if (m == NULL) { 2909 adapter->mbuf_cluster_failed++; 2910 if (init) { 2911 if_printf(&adapter->arpcom.ac_if, 2912 "Unable to allocate RX mbuf\n"); 2913 } 2914 return (ENOBUFS); 2915 } 2916 m->m_len = m->m_pkthdr.len = MCLBYTES; 2917 2918 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2919 m_adj(m, ETHER_ALIGN); 2920 2921 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 2922 adapter->rx_sparemap, m, 2923 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2924 if (error) { 2925 m_freem(m); 2926 if (init) { 2927 if_printf(&adapter->arpcom.ac_if, 2928 "Unable to load RX mbuf\n"); 2929 } 2930 return (error); 2931 } 2932 2933 rx_buffer = &adapter->rx_buffer_area[i]; 2934 if (rx_buffer->m_head != NULL) 2935 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2936 2937 map = rx_buffer->map; 2938 rx_buffer->map = adapter->rx_sparemap; 2939 adapter->rx_sparemap = map; 2940 2941 rx_buffer->m_head = m; 2942 2943 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 2944 return (0); 2945 } 2946 2947 static int 2948 em_create_rx_ring(struct adapter *adapter) 2949 { 2950 device_t dev = adapter->dev; 2951 struct em_buffer *rx_buffer; 2952 int i, error; 2953 2954 adapter->rx_buffer_area = 2955 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 2956 M_DEVBUF, M_WAITOK | M_ZERO); 2957 2958 /* 2959 * Create DMA tag for rx buffers 2960 */ 2961 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2962 1, 0, /* alignment, bounds */ 2963 BUS_SPACE_MAXADDR, /* lowaddr */ 2964 BUS_SPACE_MAXADDR, /* highaddr */ 2965 NULL, NULL, /* filter, filterarg */ 2966 MCLBYTES, /* maxsize */ 2967 1, /* nsegments */ 2968 MCLBYTES, /* maxsegsize */ 2969 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2970 &adapter->rxtag); 2971 if (error) { 2972 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2973 kfree(adapter->rx_buffer_area, M_DEVBUF); 2974 adapter->rx_buffer_area = NULL; 2975 return error; 2976 } 2977 2978 /* 2979 * Create spare DMA map for rx buffers 2980 */ 2981 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 2982 &adapter->rx_sparemap); 2983 if (error) { 2984 device_printf(dev, "Unable to create spare RX DMA map\n"); 2985 bus_dma_tag_destroy(adapter->rxtag); 2986 kfree(adapter->rx_buffer_area, M_DEVBUF); 2987 adapter->rx_buffer_area = NULL; 2988 return error; 2989 } 2990 2991 /* 2992 * Create DMA maps for rx buffers 2993 */ 2994 for (i = 0; i < adapter->num_rx_desc; i++) { 2995 rx_buffer = &adapter->rx_buffer_area[i]; 2996 2997 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 2998 &rx_buffer->map); 2999 if (error) { 3000 device_printf(dev, "Unable to create RX DMA map\n"); 3001 em_destroy_rx_ring(adapter, i); 3002 return error; 3003 } 3004 } 3005 return (0); 3006 } 3007 3008 static int 3009 em_init_rx_ring(struct adapter *adapter) 3010 { 3011 int i, error; 3012 3013 /* Reset descriptor ring */ 3014 bzero(adapter->rx_desc_base, 3015 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3016 3017 /* Allocate new ones. */ 3018 for (i = 0; i < adapter->num_rx_desc; i++) { 3019 error = em_newbuf(adapter, i, 1); 3020 if (error) 3021 return (error); 3022 } 3023 3024 /* Setup our descriptor pointers */ 3025 adapter->next_rx_desc_to_check = 0; 3026 3027 return (0); 3028 } 3029 3030 static void 3031 em_init_rx_unit(struct adapter *adapter) 3032 { 3033 struct ifnet *ifp = &adapter->arpcom.ac_if; 3034 uint64_t bus_addr; 3035 uint32_t rctl, rxcsum; 3036 3037 /* 3038 * Make sure receives are disabled while setting 3039 * up the descriptor ring 3040 */ 3041 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3042 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3043 3044 if (adapter->hw.mac.type >= e1000_82540) { 3045 /* 3046 * Set the interrupt throttling rate. Value is calculated 3047 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3048 */ 3049 if (adapter->int_throttle_ceil) { 3050 E1000_WRITE_REG(&adapter->hw, E1000_ITR, 3051 1000000000 / 256 / adapter->int_throttle_ceil); 3052 } else { 3053 E1000_WRITE_REG(&adapter->hw, E1000_ITR, 0); 3054 } 3055 } 3056 3057 /* Disable accelerated ackknowledge */ 3058 if (adapter->hw.mac.type == e1000_82574) { 3059 E1000_WRITE_REG(&adapter->hw, 3060 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3061 } 3062 3063 /* Setup the Base and Length of the Rx Descriptor Ring */ 3064 bus_addr = adapter->rxdma.dma_paddr; 3065 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3066 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3067 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3068 (uint32_t)(bus_addr >> 32)); 3069 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3070 (uint32_t)bus_addr); 3071 3072 /* Setup the Receive Control Register */ 3073 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3074 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3075 E1000_RCTL_RDMTS_HALF | 3076 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3077 3078 /* Make sure VLAN Filters are off */ 3079 rctl &= ~E1000_RCTL_VFE; 3080 3081 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3082 rctl |= E1000_RCTL_SBP; 3083 else 3084 rctl &= ~E1000_RCTL_SBP; 3085 3086 switch (adapter->rx_buffer_len) { 3087 default: 3088 case 2048: 3089 rctl |= E1000_RCTL_SZ_2048; 3090 break; 3091 3092 case 4096: 3093 rctl |= E1000_RCTL_SZ_4096 | 3094 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3095 break; 3096 3097 case 8192: 3098 rctl |= E1000_RCTL_SZ_8192 | 3099 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3100 break; 3101 3102 case 16384: 3103 rctl |= E1000_RCTL_SZ_16384 | 3104 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3105 break; 3106 } 3107 3108 if (ifp->if_mtu > ETHERMTU) 3109 rctl |= E1000_RCTL_LPE; 3110 else 3111 rctl &= ~E1000_RCTL_LPE; 3112 3113 /* Receive Checksum Offload for TCP and UDP */ 3114 if (ifp->if_capenable & IFCAP_RXCSUM) { 3115 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3116 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3117 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3118 } 3119 3120 /* 3121 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3122 * long latencies are observed, like Lenovo X60. This 3123 * change eliminates the problem, but since having positive 3124 * values in RDTR is a known source of problems on other 3125 * platforms another solution is being sought. 3126 */ 3127 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3128 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3129 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3130 } 3131 3132 /* 3133 * Setup the HW Rx Head and Tail Descriptor Pointers 3134 */ 3135 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3136 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3137 3138 /* Enable Receives */ 3139 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3140 } 3141 3142 static void 3143 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3144 { 3145 struct em_buffer *rx_buffer; 3146 int i; 3147 3148 if (adapter->rx_buffer_area == NULL) 3149 return; 3150 3151 for (i = 0; i < ndesc; i++) { 3152 rx_buffer = &adapter->rx_buffer_area[i]; 3153 3154 KKASSERT(rx_buffer->m_head == NULL); 3155 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3156 } 3157 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3158 bus_dma_tag_destroy(adapter->rxtag); 3159 3160 kfree(adapter->rx_buffer_area, M_DEVBUF); 3161 adapter->rx_buffer_area = NULL; 3162 } 3163 3164 static void 3165 em_rxeof(struct adapter *adapter, int count) 3166 { 3167 struct ifnet *ifp = &adapter->arpcom.ac_if; 3168 uint8_t status, accept_frame = 0, eop = 0; 3169 uint16_t len, desc_len, prev_len_adj; 3170 struct e1000_rx_desc *current_desc; 3171 struct mbuf *mp; 3172 int i; 3173 struct mbuf_chain chain[MAXCPU]; 3174 3175 i = adapter->next_rx_desc_to_check; 3176 current_desc = &adapter->rx_desc_base[i]; 3177 3178 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3179 return; 3180 3181 ether_input_chain_init(chain); 3182 3183 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3184 struct mbuf *m = NULL; 3185 3186 logif(pkt_receive); 3187 3188 mp = adapter->rx_buffer_area[i].m_head; 3189 3190 /* 3191 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3192 * needs to access the last received byte in the mbuf. 3193 */ 3194 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3195 BUS_DMASYNC_POSTREAD); 3196 3197 accept_frame = 1; 3198 prev_len_adj = 0; 3199 desc_len = le16toh(current_desc->length); 3200 status = current_desc->status; 3201 if (status & E1000_RXD_STAT_EOP) { 3202 count--; 3203 eop = 1; 3204 if (desc_len < ETHER_CRC_LEN) { 3205 len = 0; 3206 prev_len_adj = ETHER_CRC_LEN - desc_len; 3207 } else { 3208 len = desc_len - ETHER_CRC_LEN; 3209 } 3210 } else { 3211 eop = 0; 3212 len = desc_len; 3213 } 3214 3215 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3216 uint8_t last_byte; 3217 uint32_t pkt_len = desc_len; 3218 3219 if (adapter->fmp != NULL) 3220 pkt_len += adapter->fmp->m_pkthdr.len; 3221 3222 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3223 if (TBI_ACCEPT(&adapter->hw, status, 3224 current_desc->errors, pkt_len, last_byte, 3225 adapter->min_frame_size, adapter->max_frame_size)) { 3226 e1000_tbi_adjust_stats_82543(&adapter->hw, 3227 &adapter->stats, pkt_len, 3228 adapter->hw.mac.addr, 3229 adapter->max_frame_size); 3230 if (len > 0) 3231 len--; 3232 } else { 3233 accept_frame = 0; 3234 } 3235 } 3236 3237 if (accept_frame) { 3238 if (em_newbuf(adapter, i, 0) != 0) { 3239 ifp->if_iqdrops++; 3240 goto discard; 3241 } 3242 3243 /* Assign correct length to the current fragment */ 3244 mp->m_len = len; 3245 3246 if (adapter->fmp == NULL) { 3247 mp->m_pkthdr.len = len; 3248 adapter->fmp = mp; /* Store the first mbuf */ 3249 adapter->lmp = mp; 3250 } else { 3251 /* 3252 * Chain mbuf's together 3253 */ 3254 3255 /* 3256 * Adjust length of previous mbuf in chain if 3257 * we received less than 4 bytes in the last 3258 * descriptor. 3259 */ 3260 if (prev_len_adj > 0) { 3261 adapter->lmp->m_len -= prev_len_adj; 3262 adapter->fmp->m_pkthdr.len -= 3263 prev_len_adj; 3264 } 3265 adapter->lmp->m_next = mp; 3266 adapter->lmp = adapter->lmp->m_next; 3267 adapter->fmp->m_pkthdr.len += len; 3268 } 3269 3270 if (eop) { 3271 adapter->fmp->m_pkthdr.rcvif = ifp; 3272 ifp->if_ipackets++; 3273 3274 if (ifp->if_capenable & IFCAP_RXCSUM) { 3275 em_rxcsum(adapter, current_desc, 3276 adapter->fmp); 3277 } 3278 3279 if (status & E1000_RXD_STAT_VP) { 3280 adapter->fmp->m_pkthdr.ether_vlantag = 3281 (le16toh(current_desc->special) & 3282 E1000_RXD_SPC_VLAN_MASK); 3283 adapter->fmp->m_flags |= M_VLANTAG; 3284 } 3285 m = adapter->fmp; 3286 adapter->fmp = NULL; 3287 adapter->lmp = NULL; 3288 } 3289 } else { 3290 ifp->if_ierrors++; 3291 discard: 3292 #ifdef foo 3293 /* Reuse loaded DMA map and just update mbuf chain */ 3294 mp = adapter->rx_buffer_area[i].m_head; 3295 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3296 mp->m_data = mp->m_ext.ext_buf; 3297 mp->m_next = NULL; 3298 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 3299 m_adj(mp, ETHER_ALIGN); 3300 #endif 3301 if (adapter->fmp != NULL) { 3302 m_freem(adapter->fmp); 3303 adapter->fmp = NULL; 3304 adapter->lmp = NULL; 3305 } 3306 m = NULL; 3307 } 3308 3309 /* Zero out the receive descriptors status. */ 3310 current_desc->status = 0; 3311 3312 if (m != NULL) 3313 ether_input_chain(ifp, m, NULL, chain); 3314 3315 /* Advance our pointers to the next descriptor. */ 3316 if (++i == adapter->num_rx_desc) 3317 i = 0; 3318 current_desc = &adapter->rx_desc_base[i]; 3319 } 3320 adapter->next_rx_desc_to_check = i; 3321 3322 ether_input_dispatch(chain); 3323 3324 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3325 if (--i < 0) 3326 i = adapter->num_rx_desc - 1; 3327 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3328 } 3329 3330 static void 3331 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3332 struct mbuf *mp) 3333 { 3334 /* 82543 or newer only */ 3335 if (adapter->hw.mac.type < e1000_82543 || 3336 /* Ignore Checksum bit is set */ 3337 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3338 return; 3339 3340 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3341 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3342 /* IP Checksum Good */ 3343 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3344 } 3345 3346 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3347 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3348 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3349 CSUM_PSEUDO_HDR | 3350 CSUM_FRAG_NOT_CHECKED; 3351 mp->m_pkthdr.csum_data = htons(0xffff); 3352 } 3353 } 3354 3355 static void 3356 em_enable_intr(struct adapter *adapter) 3357 { 3358 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3359 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); 3360 } 3361 3362 static void 3363 em_disable_intr(struct adapter *adapter) 3364 { 3365 uint32_t clear = 0xffffffff; 3366 3367 /* 3368 * The first version of 82542 had an errata where when link was forced 3369 * it would stay up even up even if the cable was disconnected. 3370 * Sequence errors were used to detect the disconnect and then the 3371 * driver would unforce the link. This code in the in the ISR. For 3372 * this to work correctly the Sequence error interrupt had to be 3373 * enabled all the time. 3374 */ 3375 if (adapter->hw.mac.type == e1000_82542 && 3376 adapter->hw.revision_id == E1000_REVISION_2) 3377 clear &= ~E1000_IMC_RXSEQ; 3378 3379 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3380 3381 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3382 } 3383 3384 /* 3385 * Bit of a misnomer, what this really means is 3386 * to enable OS management of the system... aka 3387 * to disable special hardware management features 3388 */ 3389 static void 3390 em_get_mgmt(struct adapter *adapter) 3391 { 3392 /* A shared code workaround */ 3393 #define E1000_82542_MANC2H E1000_MANC2H 3394 if (adapter->has_manage) { 3395 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3396 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3397 3398 /* disable hardware interception of ARP */ 3399 manc &= ~(E1000_MANC_ARP_EN); 3400 3401 /* enable receiving management packets to the host */ 3402 if (adapter->hw.mac.type >= e1000_82571) { 3403 manc |= E1000_MANC_EN_MNG2HOST; 3404 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3405 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3406 manc2h |= E1000_MNG2HOST_PORT_623; 3407 manc2h |= E1000_MNG2HOST_PORT_664; 3408 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3409 } 3410 3411 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3412 } 3413 } 3414 3415 /* 3416 * Give control back to hardware management 3417 * controller if there is one. 3418 */ 3419 static void 3420 em_rel_mgmt(struct adapter *adapter) 3421 { 3422 if (adapter->has_manage) { 3423 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3424 3425 /* re-enable hardware interception of ARP */ 3426 manc |= E1000_MANC_ARP_EN; 3427 3428 if (adapter->hw.mac.type >= e1000_82571) 3429 manc &= ~E1000_MANC_EN_MNG2HOST; 3430 3431 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3432 } 3433 } 3434 3435 /* 3436 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3437 * For ASF and Pass Through versions of f/w this means that 3438 * the driver is loaded. For AMT version (only with 82573) 3439 * of the f/w this means that the network i/f is open. 3440 */ 3441 static void 3442 em_get_hw_control(struct adapter *adapter) 3443 { 3444 uint32_t ctrl_ext, swsm; 3445 3446 /* Let firmware know the driver has taken over */ 3447 switch (adapter->hw.mac.type) { 3448 case e1000_82573: 3449 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3450 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3451 swsm | E1000_SWSM_DRV_LOAD); 3452 break; 3453 case e1000_82571: 3454 case e1000_82572: 3455 case e1000_80003es2lan: 3456 case e1000_ich8lan: 3457 case e1000_ich9lan: 3458 case e1000_ich10lan: 3459 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3460 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3461 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3462 break; 3463 default: 3464 break; 3465 } 3466 } 3467 3468 /* 3469 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3470 * For ASF and Pass Through versions of f/w this means that the 3471 * driver is no longer loaded. For AMT version (only with 82573) 3472 * of the f/w this means that the network i/f is closed. 3473 */ 3474 static void 3475 em_rel_hw_control(struct adapter *adapter) 3476 { 3477 uint32_t ctrl_ext, swsm; 3478 3479 /* Let firmware taken over control of h/w */ 3480 switch (adapter->hw.mac.type) { 3481 case e1000_82573: 3482 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3483 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3484 swsm & ~E1000_SWSM_DRV_LOAD); 3485 break; 3486 3487 case e1000_82571: 3488 case e1000_82572: 3489 case e1000_80003es2lan: 3490 case e1000_ich8lan: 3491 case e1000_ich9lan: 3492 case e1000_ich10lan: 3493 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3494 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3495 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3496 break; 3497 3498 default: 3499 break; 3500 } 3501 } 3502 3503 static int 3504 em_is_valid_eaddr(const uint8_t *addr) 3505 { 3506 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3507 3508 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3509 return (FALSE); 3510 3511 return (TRUE); 3512 } 3513 3514 /* 3515 * Enable PCI Wake On Lan capability 3516 */ 3517 void 3518 em_enable_wol(device_t dev) 3519 { 3520 uint16_t cap, status; 3521 uint8_t id; 3522 3523 /* First find the capabilities pointer*/ 3524 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3525 3526 /* Read the PM Capabilities */ 3527 id = pci_read_config(dev, cap, 1); 3528 if (id != PCIY_PMG) /* Something wrong */ 3529 return; 3530 3531 /* 3532 * OK, we have the power capabilities, 3533 * so now get the status register 3534 */ 3535 cap += PCIR_POWER_STATUS; 3536 status = pci_read_config(dev, cap, 2); 3537 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3538 pci_write_config(dev, cap, status, 2); 3539 } 3540 3541 3542 /* 3543 * 82544 Coexistence issue workaround. 3544 * There are 2 issues. 3545 * 1. Transmit Hang issue. 3546 * To detect this issue, following equation can be used... 3547 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3548 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3549 * 3550 * 2. DAC issue. 3551 * To detect this issue, following equation can be used... 3552 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3553 * If SUM[3:0] is in between 9 to c, we will have this issue. 3554 * 3555 * WORKAROUND: 3556 * Make sure we do not have ending address 3557 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3558 */ 3559 static uint32_t 3560 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3561 { 3562 uint32_t safe_terminator; 3563 3564 /* 3565 * Since issue is sensitive to length and address. 3566 * Let us first check the address... 3567 */ 3568 if (length <= 4) { 3569 desc_array->descriptor[0].address = address; 3570 desc_array->descriptor[0].length = length; 3571 desc_array->elements = 1; 3572 return (desc_array->elements); 3573 } 3574 3575 safe_terminator = 3576 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3577 3578 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3579 if (safe_terminator == 0 || 3580 (safe_terminator > 4 && safe_terminator < 9) || 3581 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3582 desc_array->descriptor[0].address = address; 3583 desc_array->descriptor[0].length = length; 3584 desc_array->elements = 1; 3585 return (desc_array->elements); 3586 } 3587 3588 desc_array->descriptor[0].address = address; 3589 desc_array->descriptor[0].length = length - 4; 3590 desc_array->descriptor[1].address = address + (length - 4); 3591 desc_array->descriptor[1].length = 4; 3592 desc_array->elements = 2; 3593 return (desc_array->elements); 3594 } 3595 3596 static void 3597 em_update_stats(struct adapter *adapter) 3598 { 3599 struct ifnet *ifp = &adapter->arpcom.ac_if; 3600 3601 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3602 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3603 adapter->stats.symerrs += 3604 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3605 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3606 } 3607 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3608 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3609 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3610 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3611 3612 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3613 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3614 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3615 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3616 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3617 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3618 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3619 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3620 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3621 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3622 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3623 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3624 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3625 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3626 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3627 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3628 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3629 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3630 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3631 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3632 3633 /* For the 64-bit byte counters the low dword must be read first. */ 3634 /* Both registers clear on the read of the high dword */ 3635 3636 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3637 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3638 3639 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3640 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3641 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3642 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3643 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3644 3645 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3646 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3647 3648 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3649 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3650 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3651 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3652 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3653 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3654 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3655 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3656 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3657 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3658 3659 if (adapter->hw.mac.type >= e1000_82543) { 3660 adapter->stats.algnerrc += 3661 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3662 adapter->stats.rxerrc += 3663 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3664 adapter->stats.tncrs += 3665 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3666 adapter->stats.cexterr += 3667 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3668 adapter->stats.tsctc += 3669 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3670 adapter->stats.tsctfc += 3671 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3672 } 3673 3674 ifp->if_collisions = adapter->stats.colc; 3675 3676 /* Rx Errors */ 3677 ifp->if_ierrors = 3678 adapter->dropped_pkts + adapter->stats.rxerrc + 3679 adapter->stats.crcerrs + adapter->stats.algnerrc + 3680 adapter->stats.ruc + adapter->stats.roc + 3681 adapter->stats.mpc + adapter->stats.cexterr; 3682 3683 /* Tx Errors */ 3684 ifp->if_oerrors = 3685 adapter->stats.ecol + adapter->stats.latecol + 3686 adapter->watchdog_events; 3687 } 3688 3689 static void 3690 em_print_debug_info(struct adapter *adapter) 3691 { 3692 device_t dev = adapter->dev; 3693 uint8_t *hw_addr = adapter->hw.hw_addr; 3694 3695 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3696 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3697 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3698 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3699 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3700 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3701 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3702 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3703 adapter->hw.fc.high_water, 3704 adapter->hw.fc.low_water); 3705 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3706 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3707 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3708 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3709 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3710 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3711 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3712 (long long)adapter->tx_fifo_wrk_cnt, 3713 (long long)adapter->tx_fifo_reset_cnt); 3714 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3715 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3716 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3717 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3718 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3719 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3720 device_printf(dev, "Num Tx descriptors avail = %d\n", 3721 adapter->num_tx_desc_avail); 3722 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3723 adapter->no_tx_desc_avail1); 3724 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3725 adapter->no_tx_desc_avail2); 3726 device_printf(dev, "Std mbuf failed = %ld\n", 3727 adapter->mbuf_alloc_failed); 3728 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3729 adapter->mbuf_cluster_failed); 3730 device_printf(dev, "Driver dropped packets = %ld\n", 3731 adapter->dropped_pkts); 3732 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3733 adapter->no_tx_dma_setup); 3734 3735 device_printf(dev, "TXCSUM try pullup = %lu\n", 3736 adapter->tx_csum_try_pullup); 3737 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n", 3738 adapter->tx_csum_pullup1); 3739 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n", 3740 adapter->tx_csum_pullup1_failed); 3741 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n", 3742 adapter->tx_csum_pullup2); 3743 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n", 3744 adapter->tx_csum_pullup2_failed); 3745 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n", 3746 adapter->tx_csum_drop1); 3747 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n", 3748 adapter->tx_csum_drop2); 3749 } 3750 3751 static void 3752 em_print_hw_stats(struct adapter *adapter) 3753 { 3754 device_t dev = adapter->dev; 3755 3756 device_printf(dev, "Excessive collisions = %lld\n", 3757 (long long)adapter->stats.ecol); 3758 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3759 device_printf(dev, "Symbol errors = %lld\n", 3760 (long long)adapter->stats.symerrs); 3761 #endif 3762 device_printf(dev, "Sequence errors = %lld\n", 3763 (long long)adapter->stats.sec); 3764 device_printf(dev, "Defer count = %lld\n", 3765 (long long)adapter->stats.dc); 3766 device_printf(dev, "Missed Packets = %lld\n", 3767 (long long)adapter->stats.mpc); 3768 device_printf(dev, "Receive No Buffers = %lld\n", 3769 (long long)adapter->stats.rnbc); 3770 /* RLEC is inaccurate on some hardware, calculate our own. */ 3771 device_printf(dev, "Receive Length Errors = %lld\n", 3772 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 3773 device_printf(dev, "Receive errors = %lld\n", 3774 (long long)adapter->stats.rxerrc); 3775 device_printf(dev, "Crc errors = %lld\n", 3776 (long long)adapter->stats.crcerrs); 3777 device_printf(dev, "Alignment errors = %lld\n", 3778 (long long)adapter->stats.algnerrc); 3779 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3780 (long long)adapter->stats.cexterr); 3781 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 3782 device_printf(dev, "watchdog timeouts = %ld\n", 3783 adapter->watchdog_events); 3784 device_printf(dev, "XON Rcvd = %lld\n", 3785 (long long)adapter->stats.xonrxc); 3786 device_printf(dev, "XON Xmtd = %lld\n", 3787 (long long)adapter->stats.xontxc); 3788 device_printf(dev, "XOFF Rcvd = %lld\n", 3789 (long long)adapter->stats.xoffrxc); 3790 device_printf(dev, "XOFF Xmtd = %lld\n", 3791 (long long)adapter->stats.xofftxc); 3792 device_printf(dev, "Good Packets Rcvd = %lld\n", 3793 (long long)adapter->stats.gprc); 3794 device_printf(dev, "Good Packets Xmtd = %lld\n", 3795 (long long)adapter->stats.gptc); 3796 } 3797 3798 static void 3799 em_print_nvm_info(struct adapter *adapter) 3800 { 3801 uint16_t eeprom_data; 3802 int i, j, row = 0; 3803 3804 /* Its a bit crude, but it gets the job done */ 3805 kprintf("\nInterface EEPROM Dump:\n"); 3806 kprintf("Offset\n0x0000 "); 3807 for (i = 0, j = 0; i < 32; i++, j++) { 3808 if (j == 8) { /* Make the offset block */ 3809 j = 0; ++row; 3810 kprintf("\n0x00%x0 ",row); 3811 } 3812 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 3813 kprintf("%04x ", eeprom_data); 3814 } 3815 kprintf("\n"); 3816 } 3817 3818 static int 3819 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3820 { 3821 struct adapter *adapter; 3822 struct ifnet *ifp; 3823 int error, result; 3824 3825 result = -1; 3826 error = sysctl_handle_int(oidp, &result, 0, req); 3827 if (error || !req->newptr) 3828 return (error); 3829 3830 adapter = (struct adapter *)arg1; 3831 ifp = &adapter->arpcom.ac_if; 3832 3833 lwkt_serialize_enter(ifp->if_serializer); 3834 3835 if (result == 1) 3836 em_print_debug_info(adapter); 3837 3838 /* 3839 * This value will cause a hex dump of the 3840 * first 32 16-bit words of the EEPROM to 3841 * the screen. 3842 */ 3843 if (result == 2) 3844 em_print_nvm_info(adapter); 3845 3846 lwkt_serialize_exit(ifp->if_serializer); 3847 3848 return (error); 3849 } 3850 3851 static int 3852 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3853 { 3854 int error, result; 3855 3856 result = -1; 3857 error = sysctl_handle_int(oidp, &result, 0, req); 3858 if (error || !req->newptr) 3859 return (error); 3860 3861 if (result == 1) { 3862 struct adapter *adapter = (struct adapter *)arg1; 3863 struct ifnet *ifp = &adapter->arpcom.ac_if; 3864 3865 lwkt_serialize_enter(ifp->if_serializer); 3866 em_print_hw_stats(adapter); 3867 lwkt_serialize_exit(ifp->if_serializer); 3868 } 3869 return (error); 3870 } 3871 3872 static void 3873 em_add_sysctl(struct adapter *adapter) 3874 { 3875 sysctl_ctx_init(&adapter->sysctl_ctx); 3876 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 3877 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3878 device_get_nameunit(adapter->dev), 3879 CTLFLAG_RD, 0, ""); 3880 if (adapter->sysctl_tree == NULL) { 3881 device_printf(adapter->dev, "can't add sysctl node\n"); 3882 } else { 3883 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 3884 SYSCTL_CHILDREN(adapter->sysctl_tree), 3885 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 3886 em_sysctl_debug_info, "I", "Debug Information"); 3887 3888 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 3889 SYSCTL_CHILDREN(adapter->sysctl_tree), 3890 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 3891 em_sysctl_stats, "I", "Statistics"); 3892 3893 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 3894 SYSCTL_CHILDREN(adapter->sysctl_tree), 3895 OID_AUTO, "rxd", CTLFLAG_RD, 3896 &adapter->num_rx_desc, 0, NULL); 3897 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 3898 SYSCTL_CHILDREN(adapter->sysctl_tree), 3899 OID_AUTO, "txd", CTLFLAG_RD, 3900 &adapter->num_tx_desc, 0, NULL); 3901 3902 if (adapter->hw.mac.type >= e1000_82540) { 3903 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 3904 SYSCTL_CHILDREN(adapter->sysctl_tree), 3905 OID_AUTO, "int_throttle_ceil", 3906 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 3907 em_sysctl_int_throttle, "I", 3908 "interrupt throttling rate"); 3909 } 3910 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 3911 SYSCTL_CHILDREN(adapter->sysctl_tree), 3912 OID_AUTO, "int_tx_nsegs", 3913 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 3914 em_sysctl_int_tx_nsegs, "I", 3915 "# segments per TX interrupt"); 3916 } 3917 } 3918 3919 static int 3920 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3921 { 3922 struct adapter *adapter = (void *)arg1; 3923 struct ifnet *ifp = &adapter->arpcom.ac_if; 3924 int error, throttle; 3925 3926 throttle = adapter->int_throttle_ceil; 3927 error = sysctl_handle_int(oidp, &throttle, 0, req); 3928 if (error || req->newptr == NULL) 3929 return error; 3930 if (throttle < 0 || throttle > 1000000000 / 256) 3931 return EINVAL; 3932 3933 if (throttle) { 3934 /* 3935 * Set the interrupt throttling rate in 256ns increments, 3936 * recalculate sysctl value assignment to get exact frequency. 3937 */ 3938 throttle = 1000000000 / 256 / throttle; 3939 3940 /* Upper 16bits of ITR is reserved and should be zero */ 3941 if (throttle & 0xffff0000) 3942 return EINVAL; 3943 } 3944 3945 lwkt_serialize_enter(ifp->if_serializer); 3946 3947 if (throttle) 3948 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 3949 else 3950 adapter->int_throttle_ceil = 0; 3951 3952 if (ifp->if_flags & IFF_RUNNING) 3953 E1000_WRITE_REG(&adapter->hw, E1000_ITR, throttle); 3954 3955 lwkt_serialize_exit(ifp->if_serializer); 3956 3957 if (bootverbose) { 3958 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3959 adapter->int_throttle_ceil); 3960 } 3961 return 0; 3962 } 3963 3964 static int 3965 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 3966 { 3967 struct adapter *adapter = (void *)arg1; 3968 struct ifnet *ifp = &adapter->arpcom.ac_if; 3969 int error, segs; 3970 3971 segs = adapter->tx_int_nsegs; 3972 error = sysctl_handle_int(oidp, &segs, 0, req); 3973 if (error || req->newptr == NULL) 3974 return error; 3975 if (segs <= 0) 3976 return EINVAL; 3977 3978 lwkt_serialize_enter(ifp->if_serializer); 3979 3980 /* 3981 * Don't allow int_tx_nsegs to become: 3982 * o Less the oact_tx_desc 3983 * o Too large that no TX desc will cause TX interrupt to 3984 * be generated (OACTIVE will never recover) 3985 * o Too small that will cause tx_dd[] overflow 3986 */ 3987 if (segs < adapter->oact_tx_desc || 3988 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 3989 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 3990 error = EINVAL; 3991 } else { 3992 error = 0; 3993 adapter->tx_int_nsegs = segs; 3994 } 3995 3996 lwkt_serialize_exit(ifp->if_serializer); 3997 3998 return error; 3999 } 4000