1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2014, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - We must call lwkt_serialize_handler_enable() prior to enabling the 71 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 72 * the hardware interrupt in order to avoid handler execution races from 73 * scheduled interrupt threads. 74 */ 75 76 #include "opt_ifpoll.h" 77 78 #include <sys/param.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/interrupt.h> 82 #include <sys/kernel.h> 83 #include <sys/ktr.h> 84 #include <sys/malloc.h> 85 #include <sys/mbuf.h> 86 #include <sys/proc.h> 87 #include <sys/rman.h> 88 #include <sys/serialize.h> 89 #include <sys/socket.h> 90 #include <sys/sockio.h> 91 #include <sys/sysctl.h> 92 #include <sys/systm.h> 93 94 #include <net/bpf.h> 95 #include <net/ethernet.h> 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_poll.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <netinet/ip.h> 106 #include <netinet/tcp.h> 107 #include <netinet/udp.h> 108 109 #include <bus/pci/pcivar.h> 110 #include <bus/pci/pcireg.h> 111 112 #include <dev/netif/ig_hal/e1000_api.h> 113 #include <dev/netif/ig_hal/e1000_82571.h> 114 #include <dev/netif/ig_hal/e1000_dragonfly.h> 115 #include <dev/netif/em/if_em.h> 116 117 #define DEBUG_HW 0 118 119 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 120 #define EM_VER " 7.4.2" 121 122 #define _EM_DEVICE(id, ret) \ 123 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 124 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 125 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 126 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 127 128 static const struct em_vendor_info em_vendor_info_array[] = { 129 EM_DEVICE(82540EM), 130 EM_DEVICE(82540EM_LOM), 131 EM_DEVICE(82540EP), 132 EM_DEVICE(82540EP_LOM), 133 EM_DEVICE(82540EP_LP), 134 135 EM_DEVICE(82541EI), 136 EM_DEVICE(82541ER), 137 EM_DEVICE(82541ER_LOM), 138 EM_DEVICE(82541EI_MOBILE), 139 EM_DEVICE(82541GI), 140 EM_DEVICE(82541GI_LF), 141 EM_DEVICE(82541GI_MOBILE), 142 143 EM_DEVICE(82542), 144 145 EM_DEVICE(82543GC_FIBER), 146 EM_DEVICE(82543GC_COPPER), 147 148 EM_DEVICE(82544EI_COPPER), 149 EM_DEVICE(82544EI_FIBER), 150 EM_DEVICE(82544GC_COPPER), 151 EM_DEVICE(82544GC_LOM), 152 153 EM_DEVICE(82545EM_COPPER), 154 EM_DEVICE(82545EM_FIBER), 155 EM_DEVICE(82545GM_COPPER), 156 EM_DEVICE(82545GM_FIBER), 157 EM_DEVICE(82545GM_SERDES), 158 159 EM_DEVICE(82546EB_COPPER), 160 EM_DEVICE(82546EB_FIBER), 161 EM_DEVICE(82546EB_QUAD_COPPER), 162 EM_DEVICE(82546GB_COPPER), 163 EM_DEVICE(82546GB_FIBER), 164 EM_DEVICE(82546GB_SERDES), 165 EM_DEVICE(82546GB_PCIE), 166 EM_DEVICE(82546GB_QUAD_COPPER), 167 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 168 169 EM_DEVICE(82547EI), 170 EM_DEVICE(82547EI_MOBILE), 171 EM_DEVICE(82547GI), 172 173 EM_EMX_DEVICE(82571EB_COPPER), 174 EM_EMX_DEVICE(82571EB_FIBER), 175 EM_EMX_DEVICE(82571EB_SERDES), 176 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 177 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 178 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 179 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 180 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 181 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 182 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 183 184 EM_EMX_DEVICE(82572EI_COPPER), 185 EM_EMX_DEVICE(82572EI_FIBER), 186 EM_EMX_DEVICE(82572EI_SERDES), 187 EM_EMX_DEVICE(82572EI), 188 189 EM_EMX_DEVICE(82573E), 190 EM_EMX_DEVICE(82573E_IAMT), 191 EM_EMX_DEVICE(82573L), 192 193 EM_DEVICE(82583V), 194 195 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 196 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 197 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 198 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 199 200 EM_DEVICE(ICH8_IGP_M_AMT), 201 EM_DEVICE(ICH8_IGP_AMT), 202 EM_DEVICE(ICH8_IGP_C), 203 EM_DEVICE(ICH8_IFE), 204 EM_DEVICE(ICH8_IFE_GT), 205 EM_DEVICE(ICH8_IFE_G), 206 EM_DEVICE(ICH8_IGP_M), 207 EM_DEVICE(ICH8_82567V_3), 208 209 EM_DEVICE(ICH9_IGP_M_AMT), 210 EM_DEVICE(ICH9_IGP_AMT), 211 EM_DEVICE(ICH9_IGP_C), 212 EM_DEVICE(ICH9_IGP_M), 213 EM_DEVICE(ICH9_IGP_M_V), 214 EM_DEVICE(ICH9_IFE), 215 EM_DEVICE(ICH9_IFE_GT), 216 EM_DEVICE(ICH9_IFE_G), 217 EM_DEVICE(ICH9_BM), 218 219 EM_EMX_DEVICE(82574L), 220 EM_EMX_DEVICE(82574LA), 221 222 EM_DEVICE(ICH10_R_BM_LM), 223 EM_DEVICE(ICH10_R_BM_LF), 224 EM_DEVICE(ICH10_R_BM_V), 225 EM_DEVICE(ICH10_D_BM_LM), 226 EM_DEVICE(ICH10_D_BM_LF), 227 EM_DEVICE(ICH10_D_BM_V), 228 229 EM_DEVICE(PCH_M_HV_LM), 230 EM_DEVICE(PCH_M_HV_LC), 231 EM_DEVICE(PCH_D_HV_DM), 232 EM_DEVICE(PCH_D_HV_DC), 233 234 EM_DEVICE(PCH2_LV_LM), 235 EM_DEVICE(PCH2_LV_V), 236 237 EM_EMX_DEVICE(PCH_LPT_I217_LM), 238 EM_EMX_DEVICE(PCH_LPT_I217_V), 239 EM_EMX_DEVICE(PCH_LPTLP_I218_LM), 240 EM_EMX_DEVICE(PCH_LPTLP_I218_V), 241 EM_EMX_DEVICE(PCH_I218_LM2), 242 EM_EMX_DEVICE(PCH_I218_V2), 243 EM_EMX_DEVICE(PCH_I218_LM3), 244 EM_EMX_DEVICE(PCH_I218_V3), 245 246 /* required last entry */ 247 EM_DEVICE_NULL 248 }; 249 250 static int em_probe(device_t); 251 static int em_attach(device_t); 252 static int em_detach(device_t); 253 static int em_shutdown(device_t); 254 static int em_suspend(device_t); 255 static int em_resume(device_t); 256 257 static void em_init(void *); 258 static void em_stop(struct adapter *); 259 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 260 static void em_start(struct ifnet *, struct ifaltq_subque *); 261 #ifdef IFPOLL_ENABLE 262 static void em_npoll(struct ifnet *, struct ifpoll_info *); 263 static void em_npoll_compat(struct ifnet *, void *, int); 264 #endif 265 static void em_watchdog(struct ifnet *); 266 static void em_media_status(struct ifnet *, struct ifmediareq *); 267 static int em_media_change(struct ifnet *); 268 static void em_timer(void *); 269 270 static void em_intr(void *); 271 static void em_intr_mask(void *); 272 static void em_intr_body(struct adapter *, boolean_t); 273 static void em_rxeof(struct adapter *, int); 274 static void em_txeof(struct adapter *); 275 static void em_tx_collect(struct adapter *); 276 static void em_tx_purge(struct adapter *); 277 static void em_enable_intr(struct adapter *); 278 static void em_disable_intr(struct adapter *); 279 280 static int em_dma_malloc(struct adapter *, bus_size_t, 281 struct em_dma_alloc *); 282 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 283 static void em_init_tx_ring(struct adapter *); 284 static int em_init_rx_ring(struct adapter *); 285 static int em_create_tx_ring(struct adapter *); 286 static int em_create_rx_ring(struct adapter *); 287 static void em_destroy_tx_ring(struct adapter *, int); 288 static void em_destroy_rx_ring(struct adapter *, int); 289 static int em_newbuf(struct adapter *, int, int); 290 static int em_encap(struct adapter *, struct mbuf **, int *, int *); 291 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 292 struct mbuf *); 293 static int em_txcsum(struct adapter *, struct mbuf *, 294 uint32_t *, uint32_t *); 295 static int em_tso_pullup(struct adapter *, struct mbuf **); 296 static int em_tso_setup(struct adapter *, struct mbuf *, 297 uint32_t *, uint32_t *); 298 299 static int em_get_hw_info(struct adapter *); 300 static int em_is_valid_eaddr(const uint8_t *); 301 static int em_alloc_pci_res(struct adapter *); 302 static void em_free_pci_res(struct adapter *); 303 static int em_reset(struct adapter *); 304 static void em_setup_ifp(struct adapter *); 305 static void em_init_tx_unit(struct adapter *); 306 static void em_init_rx_unit(struct adapter *); 307 static void em_update_stats(struct adapter *); 308 static void em_set_promisc(struct adapter *); 309 static void em_disable_promisc(struct adapter *); 310 static void em_set_multi(struct adapter *); 311 static void em_update_link_status(struct adapter *); 312 static void em_smartspeed(struct adapter *); 313 static void em_set_itr(struct adapter *, uint32_t); 314 static void em_disable_aspm(struct adapter *); 315 316 /* Hardware workarounds */ 317 static int em_82547_fifo_workaround(struct adapter *, int); 318 static void em_82547_update_fifo_head(struct adapter *, int); 319 static int em_82547_tx_fifo_reset(struct adapter *); 320 static void em_82547_move_tail(void *); 321 static void em_82547_move_tail_serialized(struct adapter *); 322 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 323 324 static void em_print_debug_info(struct adapter *); 325 static void em_print_nvm_info(struct adapter *); 326 static void em_print_hw_stats(struct adapter *); 327 328 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 331 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 332 static void em_add_sysctl(struct adapter *adapter); 333 334 /* Management and WOL Support */ 335 static void em_get_mgmt(struct adapter *); 336 static void em_rel_mgmt(struct adapter *); 337 static void em_get_hw_control(struct adapter *); 338 static void em_rel_hw_control(struct adapter *); 339 static void em_enable_wol(device_t); 340 341 static device_method_t em_methods[] = { 342 /* Device interface */ 343 DEVMETHOD(device_probe, em_probe), 344 DEVMETHOD(device_attach, em_attach), 345 DEVMETHOD(device_detach, em_detach), 346 DEVMETHOD(device_shutdown, em_shutdown), 347 DEVMETHOD(device_suspend, em_suspend), 348 DEVMETHOD(device_resume, em_resume), 349 DEVMETHOD_END 350 }; 351 352 static driver_t em_driver = { 353 "em", 354 em_methods, 355 sizeof(struct adapter), 356 }; 357 358 static devclass_t em_devclass; 359 360 DECLARE_DUMMY_MODULE(if_em); 361 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 362 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 363 364 /* 365 * Tunables 366 */ 367 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 368 static int em_rxd = EM_DEFAULT_RXD; 369 static int em_txd = EM_DEFAULT_TXD; 370 static int em_smart_pwr_down = 0; 371 372 /* Controls whether promiscuous also shows bad packets */ 373 static int em_debug_sbp = FALSE; 374 375 static int em_82573_workaround = 1; 376 static int em_msi_enable = 1; 377 378 static char em_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_RXPAUSE; 379 380 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 381 TUNABLE_INT("hw.em.rxd", &em_rxd); 382 TUNABLE_INT("hw.em.txd", &em_txd); 383 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 384 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 385 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 386 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 387 TUNABLE_STR("hw.em.flow_ctrl", em_flowctrl, sizeof(em_flowctrl)); 388 389 /* Global used in WOL setup with multiport cards */ 390 static int em_global_quad_port_a = 0; 391 392 /* Set this to one to display debug statistics */ 393 static int em_display_debug_stats = 0; 394 395 #if !defined(KTR_IF_EM) 396 #define KTR_IF_EM KTR_ALL 397 #endif 398 KTR_INFO_MASTER(if_em); 399 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 400 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 401 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 402 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 403 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 404 #define logif(name) KTR_LOG(if_em_ ## name) 405 406 static int 407 em_probe(device_t dev) 408 { 409 const struct em_vendor_info *ent; 410 uint16_t vid, did; 411 412 vid = pci_get_vendor(dev); 413 did = pci_get_device(dev); 414 415 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 416 if (vid == ent->vendor_id && did == ent->device_id) { 417 device_set_desc(dev, ent->desc); 418 device_set_async_attach(dev, TRUE); 419 return (ent->ret); 420 } 421 } 422 return (ENXIO); 423 } 424 425 static int 426 em_attach(device_t dev) 427 { 428 struct adapter *adapter = device_get_softc(dev); 429 struct ifnet *ifp = &adapter->arpcom.ac_if; 430 int tsize, rsize; 431 int error = 0; 432 uint16_t eeprom_data, device_id, apme_mask; 433 driver_intr_t *intr_func; 434 char flowctrl[IFM_ETH_FC_STRLEN]; 435 436 adapter->dev = adapter->osdep.dev = dev; 437 438 callout_init_mp(&adapter->timer); 439 callout_init_mp(&adapter->tx_fifo_timer); 440 441 ifmedia_init(&adapter->media, IFM_IMASK | IFM_ETH_FCMASK, 442 em_media_change, em_media_status); 443 444 /* Determine hardware and mac info */ 445 error = em_get_hw_info(adapter); 446 if (error) { 447 device_printf(dev, "Identify hardware failed\n"); 448 goto fail; 449 } 450 451 /* Setup PCI resources */ 452 error = em_alloc_pci_res(adapter); 453 if (error) { 454 device_printf(dev, "Allocation of PCI resources failed\n"); 455 goto fail; 456 } 457 458 /* 459 * For ICH8 and family we need to map the flash memory, 460 * and this must happen after the MAC is identified. 461 */ 462 if (adapter->hw.mac.type == e1000_ich8lan || 463 adapter->hw.mac.type == e1000_ich9lan || 464 adapter->hw.mac.type == e1000_ich10lan || 465 adapter->hw.mac.type == e1000_pchlan || 466 adapter->hw.mac.type == e1000_pch2lan || 467 adapter->hw.mac.type == e1000_pch_lpt) { 468 adapter->flash_rid = EM_BAR_FLASH; 469 470 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 471 &adapter->flash_rid, RF_ACTIVE); 472 if (adapter->flash == NULL) { 473 device_printf(dev, "Mapping of Flash failed\n"); 474 error = ENXIO; 475 goto fail; 476 } 477 adapter->osdep.flash_bus_space_tag = 478 rman_get_bustag(adapter->flash); 479 adapter->osdep.flash_bus_space_handle = 480 rman_get_bushandle(adapter->flash); 481 482 /* 483 * This is used in the shared code 484 * XXX this goof is actually not used. 485 */ 486 adapter->hw.flash_address = (uint8_t *)adapter->flash; 487 } 488 489 switch (adapter->hw.mac.type) { 490 case e1000_82571: 491 case e1000_82572: 492 case e1000_pch_lpt: 493 /* 494 * Pullup extra 4bytes into the first data segment for 495 * TSO, see: 496 * 82571/82572 specification update errata #7 497 * 498 * Same applies to I217 (and maybe I218). 499 * 500 * NOTE: 501 * 4bytes instead of 2bytes, which are mentioned in the 502 * errata, are pulled; mainly to keep rest of the data 503 * properly aligned. 504 */ 505 adapter->flags |= EM_FLAG_TSO_PULLEX; 506 /* FALL THROUGH */ 507 508 default: 509 if (pci_is_pcie(dev)) 510 adapter->flags |= EM_FLAG_TSO; 511 break; 512 } 513 514 /* Do Shared Code initialization */ 515 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 516 device_printf(dev, "Setup of Shared code failed\n"); 517 error = ENXIO; 518 goto fail; 519 } 520 521 e1000_get_bus_info(&adapter->hw); 522 523 /* 524 * Validate number of transmit and receive descriptors. It 525 * must not exceed hardware maximum, and must be multiple 526 * of E1000_DBA_ALIGN. 527 */ 528 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 529 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 530 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 531 em_txd < EM_MIN_TXD) { 532 if (adapter->hw.mac.type < e1000_82544) 533 adapter->num_tx_desc = EM_MAX_TXD_82543; 534 else 535 adapter->num_tx_desc = EM_DEFAULT_TXD; 536 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 537 adapter->num_tx_desc, em_txd); 538 } else { 539 adapter->num_tx_desc = em_txd; 540 } 541 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 542 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 543 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 544 em_rxd < EM_MIN_RXD) { 545 if (adapter->hw.mac.type < e1000_82544) 546 adapter->num_rx_desc = EM_MAX_RXD_82543; 547 else 548 adapter->num_rx_desc = EM_DEFAULT_RXD; 549 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 550 adapter->num_rx_desc, em_rxd); 551 } else { 552 adapter->num_rx_desc = em_rxd; 553 } 554 555 adapter->hw.mac.autoneg = DO_AUTO_NEG; 556 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 557 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 558 adapter->rx_buffer_len = MCLBYTES; 559 560 /* 561 * Interrupt throttle rate 562 */ 563 if (em_int_throttle_ceil == 0) { 564 adapter->int_throttle_ceil = 0; 565 } else { 566 int throttle = em_int_throttle_ceil; 567 568 if (throttle < 0) 569 throttle = EM_DEFAULT_ITR; 570 571 /* Recalculate the tunable value to get the exact frequency. */ 572 throttle = 1000000000 / 256 / throttle; 573 574 /* Upper 16bits of ITR is reserved and should be zero */ 575 if (throttle & 0xffff0000) 576 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 577 578 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 579 } 580 581 e1000_init_script_state_82541(&adapter->hw, TRUE); 582 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 583 584 /* Copper options */ 585 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 586 adapter->hw.phy.mdix = AUTO_ALL_MODES; 587 adapter->hw.phy.disable_polarity_correction = FALSE; 588 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 589 } 590 591 /* Set the frame limits assuming standard ethernet sized frames. */ 592 adapter->hw.mac.max_frame_size = 593 ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 594 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 595 596 /* This controls when hardware reports transmit completion status. */ 597 adapter->hw.mac.report_tx_early = 1; 598 599 /* 600 * Create top level busdma tag 601 */ 602 error = bus_dma_tag_create(NULL, 1, 0, 603 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 604 NULL, NULL, 605 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 606 0, &adapter->parent_dtag); 607 if (error) { 608 device_printf(dev, "could not create top level DMA tag\n"); 609 goto fail; 610 } 611 612 /* 613 * Allocate Transmit Descriptor ring 614 */ 615 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 616 EM_DBA_ALIGN); 617 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 618 if (error) { 619 device_printf(dev, "Unable to allocate tx_desc memory\n"); 620 goto fail; 621 } 622 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 623 624 /* 625 * Allocate Receive Descriptor ring 626 */ 627 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 628 EM_DBA_ALIGN); 629 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 630 if (error) { 631 device_printf(dev, "Unable to allocate rx_desc memory\n"); 632 goto fail; 633 } 634 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 635 636 /* Allocate multicast array memory. */ 637 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 638 M_DEVBUF, M_WAITOK); 639 640 /* Indicate SOL/IDER usage */ 641 if (e1000_check_reset_block(&adapter->hw)) { 642 device_printf(dev, 643 "PHY reset is blocked due to SOL/IDER session.\n"); 644 } 645 646 /* Disable EEE */ 647 adapter->hw.dev_spec.ich8lan.eee_disable = 1; 648 649 /* 650 * Start from a known state, this is important in reading the 651 * nvm and mac from that. 652 */ 653 e1000_reset_hw(&adapter->hw); 654 655 /* Make sure we have a good EEPROM before we read from it */ 656 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 657 /* 658 * Some PCI-E parts fail the first check due to 659 * the link being in sleep state, call it again, 660 * if it fails a second time its a real issue. 661 */ 662 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 663 device_printf(dev, 664 "The EEPROM Checksum Is Not Valid\n"); 665 error = EIO; 666 goto fail; 667 } 668 } 669 670 /* Copy the permanent MAC address out of the EEPROM */ 671 if (e1000_read_mac_addr(&adapter->hw) < 0) { 672 device_printf(dev, "EEPROM read error while reading MAC" 673 " address\n"); 674 error = EIO; 675 goto fail; 676 } 677 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 678 device_printf(dev, "Invalid MAC address\n"); 679 error = EIO; 680 goto fail; 681 } 682 683 /* Disable ULP support */ 684 e1000_disable_ulp_lpt_lp(&adapter->hw, TRUE); 685 686 /* Allocate transmit descriptors and buffers */ 687 error = em_create_tx_ring(adapter); 688 if (error) { 689 device_printf(dev, "Could not setup transmit structures\n"); 690 goto fail; 691 } 692 693 /* Allocate receive descriptors and buffers */ 694 error = em_create_rx_ring(adapter); 695 if (error) { 696 device_printf(dev, "Could not setup receive structures\n"); 697 goto fail; 698 } 699 700 /* Manually turn off all interrupts */ 701 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 702 703 /* Determine if we have to control management hardware */ 704 if (e1000_enable_mng_pass_thru(&adapter->hw)) 705 adapter->flags |= EM_FLAG_HAS_MGMT; 706 707 /* 708 * Setup Wake-on-Lan 709 */ 710 apme_mask = EM_EEPROM_APME; 711 eeprom_data = 0; 712 switch (adapter->hw.mac.type) { 713 case e1000_82542: 714 case e1000_82543: 715 break; 716 717 case e1000_82573: 718 case e1000_82583: 719 adapter->flags |= EM_FLAG_HAS_AMT; 720 /* FALL THROUGH */ 721 722 case e1000_82546: 723 case e1000_82546_rev_3: 724 case e1000_82571: 725 case e1000_82572: 726 case e1000_80003es2lan: 727 if (adapter->hw.bus.func == 1) { 728 e1000_read_nvm(&adapter->hw, 729 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 730 } else { 731 e1000_read_nvm(&adapter->hw, 732 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 733 } 734 break; 735 736 case e1000_ich8lan: 737 case e1000_ich9lan: 738 case e1000_ich10lan: 739 case e1000_pchlan: 740 case e1000_pch2lan: 741 apme_mask = E1000_WUC_APME; 742 adapter->flags |= EM_FLAG_HAS_AMT; 743 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 744 break; 745 746 default: 747 e1000_read_nvm(&adapter->hw, 748 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 749 break; 750 } 751 if (eeprom_data & apme_mask) 752 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 753 754 /* 755 * We have the eeprom settings, now apply the special cases 756 * where the eeprom may be wrong or the board won't support 757 * wake on lan on a particular port 758 */ 759 device_id = pci_get_device(dev); 760 switch (device_id) { 761 case E1000_DEV_ID_82546GB_PCIE: 762 adapter->wol = 0; 763 break; 764 765 case E1000_DEV_ID_82546EB_FIBER: 766 case E1000_DEV_ID_82546GB_FIBER: 767 case E1000_DEV_ID_82571EB_FIBER: 768 /* 769 * Wake events only supported on port A for dual fiber 770 * regardless of eeprom setting 771 */ 772 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 773 E1000_STATUS_FUNC_1) 774 adapter->wol = 0; 775 break; 776 777 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 778 case E1000_DEV_ID_82571EB_QUAD_COPPER: 779 case E1000_DEV_ID_82571EB_QUAD_FIBER: 780 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 781 /* if quad port adapter, disable WoL on all but port A */ 782 if (em_global_quad_port_a != 0) 783 adapter->wol = 0; 784 /* Reset for multiple quad port adapters */ 785 if (++em_global_quad_port_a == 4) 786 em_global_quad_port_a = 0; 787 break; 788 } 789 790 /* XXX disable wol */ 791 adapter->wol = 0; 792 793 /* Setup flow control. */ 794 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl), 795 em_flowctrl); 796 adapter->ifm_flowctrl = ifmedia_str2ethfc(flowctrl); 797 if (adapter->hw.mac.type == e1000_pchlan) { 798 /* Only PAUSE reception is supported on PCH */ 799 adapter->ifm_flowctrl &= ~IFM_ETH_TXPAUSE; 800 } 801 802 /* Setup OS specific network interface */ 803 em_setup_ifp(adapter); 804 805 /* Add sysctl tree, must after em_setup_ifp() */ 806 em_add_sysctl(adapter); 807 808 #ifdef IFPOLL_ENABLE 809 /* Polling setup */ 810 ifpoll_compat_setup(&adapter->npoll, 811 device_get_sysctl_ctx(dev), device_get_sysctl_tree(dev), 812 device_get_unit(dev), ifp->if_serializer); 813 #endif 814 815 /* Reset the hardware */ 816 error = em_reset(adapter); 817 if (error) { 818 /* 819 * Some 82573 parts fail the first reset, call it again, 820 * if it fails a second time its a real issue. 821 */ 822 error = em_reset(adapter); 823 if (error) { 824 device_printf(dev, "Unable to reset the hardware\n"); 825 ether_ifdetach(ifp); 826 goto fail; 827 } 828 } 829 830 /* Initialize statistics */ 831 em_update_stats(adapter); 832 833 adapter->hw.mac.get_link_status = 1; 834 em_update_link_status(adapter); 835 836 /* Do we need workaround for 82544 PCI-X adapter? */ 837 if (adapter->hw.bus.type == e1000_bus_type_pcix && 838 adapter->hw.mac.type == e1000_82544) 839 adapter->pcix_82544 = TRUE; 840 else 841 adapter->pcix_82544 = FALSE; 842 843 if (adapter->pcix_82544) { 844 /* 845 * 82544 on PCI-X may split one TX segment 846 * into two TX descs, so we double its number 847 * of spare TX desc here. 848 */ 849 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 850 } else { 851 adapter->spare_tx_desc = EM_TX_SPARE; 852 } 853 if (adapter->flags & EM_FLAG_TSO) 854 adapter->spare_tx_desc = EM_TX_SPARE_TSO; 855 adapter->tx_wreg_nsegs = EM_DEFAULT_TXWREG; 856 857 /* 858 * Keep following relationship between spare_tx_desc, oact_tx_desc 859 * and tx_int_nsegs: 860 * (spare_tx_desc + EM_TX_RESERVED) <= 861 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 862 */ 863 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 864 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 865 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 866 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 867 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 868 869 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 870 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 871 adapter->tx_int_nsegs = adapter->oact_tx_desc; 872 873 /* Non-AMT based hardware can now take control from firmware */ 874 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 875 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571) 876 em_get_hw_control(adapter); 877 878 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 879 880 /* 881 * Missing Interrupt Following ICR read: 882 * 883 * 82571/82572 specification update errata #76 884 * 82573 specification update errata #31 885 * 82574 specification update errata #12 886 * 82583 specification update errata #4 887 */ 888 intr_func = em_intr; 889 if ((adapter->flags & EM_FLAG_SHARED_INTR) && 890 (adapter->hw.mac.type == e1000_82571 || 891 adapter->hw.mac.type == e1000_82572 || 892 adapter->hw.mac.type == e1000_82573 || 893 adapter->hw.mac.type == e1000_82574 || 894 adapter->hw.mac.type == e1000_82583)) 895 intr_func = em_intr_mask; 896 897 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 898 intr_func, adapter, &adapter->intr_tag, 899 ifp->if_serializer); 900 if (error) { 901 device_printf(dev, "Failed to register interrupt handler"); 902 ether_ifdetach(ifp); 903 goto fail; 904 } 905 return (0); 906 fail: 907 em_detach(dev); 908 return (error); 909 } 910 911 static int 912 em_detach(device_t dev) 913 { 914 struct adapter *adapter = device_get_softc(dev); 915 916 if (device_is_attached(dev)) { 917 struct ifnet *ifp = &adapter->arpcom.ac_if; 918 919 lwkt_serialize_enter(ifp->if_serializer); 920 921 em_stop(adapter); 922 923 e1000_phy_hw_reset(&adapter->hw); 924 925 em_rel_mgmt(adapter); 926 em_rel_hw_control(adapter); 927 928 if (adapter->wol) { 929 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 930 E1000_WUC_PME_EN); 931 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 932 em_enable_wol(dev); 933 } 934 935 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 936 937 lwkt_serialize_exit(ifp->if_serializer); 938 939 ether_ifdetach(ifp); 940 } else if (adapter->memory != NULL) { 941 em_rel_hw_control(adapter); 942 } 943 944 ifmedia_removeall(&adapter->media); 945 bus_generic_detach(dev); 946 947 em_free_pci_res(adapter); 948 949 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 950 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 951 952 /* Free Transmit Descriptor ring */ 953 if (adapter->tx_desc_base) 954 em_dma_free(adapter, &adapter->txdma); 955 956 /* Free Receive Descriptor ring */ 957 if (adapter->rx_desc_base) 958 em_dma_free(adapter, &adapter->rxdma); 959 960 /* Free top level busdma tag */ 961 if (adapter->parent_dtag != NULL) 962 bus_dma_tag_destroy(adapter->parent_dtag); 963 964 if (adapter->mta != NULL) 965 kfree(adapter->mta, M_DEVBUF); 966 967 return (0); 968 } 969 970 static int 971 em_shutdown(device_t dev) 972 { 973 return em_suspend(dev); 974 } 975 976 static int 977 em_suspend(device_t dev) 978 { 979 struct adapter *adapter = device_get_softc(dev); 980 struct ifnet *ifp = &adapter->arpcom.ac_if; 981 982 lwkt_serialize_enter(ifp->if_serializer); 983 984 em_stop(adapter); 985 986 em_rel_mgmt(adapter); 987 em_rel_hw_control(adapter); 988 989 if (adapter->wol) { 990 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 991 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 992 em_enable_wol(dev); 993 } 994 995 lwkt_serialize_exit(ifp->if_serializer); 996 997 return bus_generic_suspend(dev); 998 } 999 1000 static int 1001 em_resume(device_t dev) 1002 { 1003 struct adapter *adapter = device_get_softc(dev); 1004 struct ifnet *ifp = &adapter->arpcom.ac_if; 1005 1006 lwkt_serialize_enter(ifp->if_serializer); 1007 1008 if (adapter->hw.mac.type == e1000_pch2lan) 1009 e1000_resume_workarounds_pchlan(&adapter->hw); 1010 1011 em_init(adapter); 1012 em_get_mgmt(adapter); 1013 if_devstart(ifp); 1014 1015 lwkt_serialize_exit(ifp->if_serializer); 1016 1017 return bus_generic_resume(dev); 1018 } 1019 1020 static void 1021 em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1022 { 1023 struct adapter *adapter = ifp->if_softc; 1024 struct mbuf *m_head; 1025 int idx = -1, nsegs = 0; 1026 1027 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1028 ASSERT_SERIALIZED(ifp->if_serializer); 1029 1030 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1031 return; 1032 1033 if (!adapter->link_active) { 1034 ifq_purge(&ifp->if_snd); 1035 return; 1036 } 1037 1038 while (!ifq_is_empty(&ifp->if_snd)) { 1039 /* Now do we at least have a minimal? */ 1040 if (EM_IS_OACTIVE(adapter)) { 1041 em_tx_collect(adapter); 1042 if (EM_IS_OACTIVE(adapter)) { 1043 ifq_set_oactive(&ifp->if_snd); 1044 adapter->no_tx_desc_avail1++; 1045 break; 1046 } 1047 } 1048 1049 logif(pkt_txqueue); 1050 m_head = ifq_dequeue(&ifp->if_snd); 1051 if (m_head == NULL) 1052 break; 1053 1054 if (em_encap(adapter, &m_head, &nsegs, &idx)) { 1055 IFNET_STAT_INC(ifp, oerrors, 1); 1056 em_tx_collect(adapter); 1057 continue; 1058 } 1059 1060 /* 1061 * TX interrupt are aggressively aggregated, so increasing 1062 * opackets at TX interrupt time will make the opackets 1063 * statistics vastly inaccurate; we do the opackets increment 1064 * now. 1065 */ 1066 IFNET_STAT_INC(ifp, opackets, 1); 1067 1068 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) { 1069 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1070 nsegs = 0; 1071 idx = -1; 1072 } 1073 1074 /* Send a copy of the frame to the BPF listener */ 1075 ETHER_BPF_MTAP(ifp, m_head); 1076 1077 /* Set timeout in case hardware has problems transmitting. */ 1078 ifp->if_timer = EM_TX_TIMEOUT; 1079 } 1080 if (idx >= 0) 1081 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1082 } 1083 1084 static int 1085 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1086 { 1087 struct adapter *adapter = ifp->if_softc; 1088 struct ifreq *ifr = (struct ifreq *)data; 1089 uint16_t eeprom_data = 0; 1090 int max_frame_size, mask, reinit; 1091 int error = 0; 1092 1093 ASSERT_SERIALIZED(ifp->if_serializer); 1094 1095 switch (command) { 1096 case SIOCSIFMTU: 1097 switch (adapter->hw.mac.type) { 1098 case e1000_82573: 1099 /* 1100 * 82573 only supports jumbo frames 1101 * if ASPM is disabled. 1102 */ 1103 e1000_read_nvm(&adapter->hw, 1104 NVM_INIT_3GIO_3, 1, &eeprom_data); 1105 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1106 max_frame_size = ETHER_MAX_LEN; 1107 break; 1108 } 1109 /* FALL THROUGH */ 1110 1111 /* Limit Jumbo Frame size */ 1112 case e1000_82571: 1113 case e1000_82572: 1114 case e1000_ich9lan: 1115 case e1000_ich10lan: 1116 case e1000_pch2lan: 1117 case e1000_pch_lpt: 1118 case e1000_82574: 1119 case e1000_82583: 1120 case e1000_80003es2lan: 1121 max_frame_size = 9234; 1122 break; 1123 1124 case e1000_pchlan: 1125 max_frame_size = 4096; 1126 break; 1127 1128 /* Adapters that do not support jumbo frames */ 1129 case e1000_82542: 1130 case e1000_ich8lan: 1131 max_frame_size = ETHER_MAX_LEN; 1132 break; 1133 1134 default: 1135 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1136 break; 1137 } 1138 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1139 ETHER_CRC_LEN) { 1140 error = EINVAL; 1141 break; 1142 } 1143 1144 ifp->if_mtu = ifr->ifr_mtu; 1145 adapter->hw.mac.max_frame_size = 1146 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1147 1148 if (ifp->if_flags & IFF_RUNNING) 1149 em_init(adapter); 1150 break; 1151 1152 case SIOCSIFFLAGS: 1153 if (ifp->if_flags & IFF_UP) { 1154 if ((ifp->if_flags & IFF_RUNNING)) { 1155 if ((ifp->if_flags ^ adapter->if_flags) & 1156 (IFF_PROMISC | IFF_ALLMULTI)) { 1157 em_disable_promisc(adapter); 1158 em_set_promisc(adapter); 1159 } 1160 } else { 1161 em_init(adapter); 1162 } 1163 } else if (ifp->if_flags & IFF_RUNNING) { 1164 em_stop(adapter); 1165 } 1166 adapter->if_flags = ifp->if_flags; 1167 break; 1168 1169 case SIOCADDMULTI: 1170 case SIOCDELMULTI: 1171 if (ifp->if_flags & IFF_RUNNING) { 1172 em_disable_intr(adapter); 1173 em_set_multi(adapter); 1174 if (adapter->hw.mac.type == e1000_82542 && 1175 adapter->hw.revision_id == E1000_REVISION_2) 1176 em_init_rx_unit(adapter); 1177 #ifdef IFPOLL_ENABLE 1178 if (!(ifp->if_flags & IFF_NPOLLING)) 1179 #endif 1180 em_enable_intr(adapter); 1181 } 1182 break; 1183 1184 case SIOCSIFMEDIA: 1185 /* Check SOL/IDER usage */ 1186 if (e1000_check_reset_block(&adapter->hw)) { 1187 device_printf(adapter->dev, "Media change is" 1188 " blocked due to SOL/IDER session.\n"); 1189 break; 1190 } 1191 /* FALL THROUGH */ 1192 1193 case SIOCGIFMEDIA: 1194 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1195 break; 1196 1197 case SIOCSIFCAP: 1198 reinit = 0; 1199 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1200 if (mask & IFCAP_RXCSUM) { 1201 ifp->if_capenable ^= IFCAP_RXCSUM; 1202 reinit = 1; 1203 } 1204 if (mask & IFCAP_TXCSUM) { 1205 ifp->if_capenable ^= IFCAP_TXCSUM; 1206 if (ifp->if_capenable & IFCAP_TXCSUM) 1207 ifp->if_hwassist |= EM_CSUM_FEATURES; 1208 else 1209 ifp->if_hwassist &= ~EM_CSUM_FEATURES; 1210 } 1211 if (mask & IFCAP_TSO) { 1212 ifp->if_capenable ^= IFCAP_TSO; 1213 if (ifp->if_capenable & IFCAP_TSO) 1214 ifp->if_hwassist |= CSUM_TSO; 1215 else 1216 ifp->if_hwassist &= ~CSUM_TSO; 1217 } 1218 if (mask & IFCAP_VLAN_HWTAGGING) { 1219 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1220 reinit = 1; 1221 } 1222 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1223 em_init(adapter); 1224 break; 1225 1226 default: 1227 error = ether_ioctl(ifp, command, data); 1228 break; 1229 } 1230 return (error); 1231 } 1232 1233 static void 1234 em_watchdog(struct ifnet *ifp) 1235 { 1236 struct adapter *adapter = ifp->if_softc; 1237 1238 ASSERT_SERIALIZED(ifp->if_serializer); 1239 1240 /* 1241 * The timer is set to 5 every time start queues a packet. 1242 * Then txeof keeps resetting it as long as it cleans at 1243 * least one descriptor. 1244 * Finally, anytime all descriptors are clean the timer is 1245 * set to 0. 1246 */ 1247 1248 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1249 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1250 /* 1251 * If we reach here, all TX jobs are completed and 1252 * the TX engine should have been idled for some time. 1253 * We don't need to call if_devstart() here. 1254 */ 1255 ifq_clr_oactive(&ifp->if_snd); 1256 ifp->if_timer = 0; 1257 return; 1258 } 1259 1260 /* 1261 * If we are in this routine because of pause frames, then 1262 * don't reset the hardware. 1263 */ 1264 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1265 E1000_STATUS_TXOFF) { 1266 ifp->if_timer = EM_TX_TIMEOUT; 1267 return; 1268 } 1269 1270 if (e1000_check_for_link(&adapter->hw) == 0) 1271 if_printf(ifp, "watchdog timeout -- resetting\n"); 1272 1273 IFNET_STAT_INC(ifp, oerrors, 1); 1274 adapter->watchdog_events++; 1275 1276 em_init(adapter); 1277 1278 if (!ifq_is_empty(&ifp->if_snd)) 1279 if_devstart(ifp); 1280 } 1281 1282 static void 1283 em_init(void *xsc) 1284 { 1285 struct adapter *adapter = xsc; 1286 struct ifnet *ifp = &adapter->arpcom.ac_if; 1287 device_t dev = adapter->dev; 1288 1289 ASSERT_SERIALIZED(ifp->if_serializer); 1290 1291 em_stop(adapter); 1292 1293 /* Get the latest mac address, User can use a LAA */ 1294 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1295 1296 /* Put the address into the Receive Address Array */ 1297 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1298 1299 /* 1300 * With the 82571 adapter, RAR[0] may be overwritten 1301 * when the other port is reset, we make a duplicate 1302 * in RAR[14] for that eventuality, this assures 1303 * the interface continues to function. 1304 */ 1305 if (adapter->hw.mac.type == e1000_82571) { 1306 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1307 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1308 E1000_RAR_ENTRIES - 1); 1309 } 1310 1311 /* Reset the hardware */ 1312 if (em_reset(adapter)) { 1313 device_printf(dev, "Unable to reset the hardware\n"); 1314 /* XXX em_stop()? */ 1315 return; 1316 } 1317 em_update_link_status(adapter); 1318 1319 /* Setup VLAN support, basic and offload if available */ 1320 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1321 1322 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1323 uint32_t ctrl; 1324 1325 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1326 ctrl |= E1000_CTRL_VME; 1327 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1328 } 1329 1330 /* Configure for OS presence */ 1331 em_get_mgmt(adapter); 1332 1333 /* Prepare transmit descriptors and buffers */ 1334 em_init_tx_ring(adapter); 1335 em_init_tx_unit(adapter); 1336 1337 /* Setup Multicast table */ 1338 em_set_multi(adapter); 1339 1340 /* Prepare receive descriptors and buffers */ 1341 if (em_init_rx_ring(adapter)) { 1342 device_printf(dev, "Could not setup receive structures\n"); 1343 em_stop(adapter); 1344 return; 1345 } 1346 em_init_rx_unit(adapter); 1347 1348 /* Don't lose promiscuous settings */ 1349 em_set_promisc(adapter); 1350 1351 ifp->if_flags |= IFF_RUNNING; 1352 ifq_clr_oactive(&ifp->if_snd); 1353 1354 callout_reset(&adapter->timer, hz, em_timer, adapter); 1355 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1356 1357 /* MSI/X configuration for 82574 */ 1358 if (adapter->hw.mac.type == e1000_82574) { 1359 int tmp; 1360 1361 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1362 tmp |= E1000_CTRL_EXT_PBA_CLR; 1363 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1364 /* 1365 * XXX MSIX 1366 * Set the IVAR - interrupt vector routing. 1367 * Each nibble represents a vector, high bit 1368 * is enable, other 3 bits are the MSIX table 1369 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1370 * Link (other) to 2, hence the magic number. 1371 */ 1372 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1373 } 1374 1375 #ifdef IFPOLL_ENABLE 1376 /* 1377 * Only enable interrupts if we are not polling, make sure 1378 * they are off otherwise. 1379 */ 1380 if (ifp->if_flags & IFF_NPOLLING) 1381 em_disable_intr(adapter); 1382 else 1383 #endif /* IFPOLL_ENABLE */ 1384 em_enable_intr(adapter); 1385 1386 /* AMT based hardware can now take control from firmware */ 1387 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 1388 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) && 1389 adapter->hw.mac.type >= e1000_82571) 1390 em_get_hw_control(adapter); 1391 } 1392 1393 #ifdef IFPOLL_ENABLE 1394 1395 static void 1396 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1397 { 1398 struct adapter *adapter = ifp->if_softc; 1399 1400 ASSERT_SERIALIZED(ifp->if_serializer); 1401 1402 if (adapter->npoll.ifpc_stcount-- == 0) { 1403 uint32_t reg_icr; 1404 1405 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac; 1406 1407 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1408 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1409 callout_stop(&adapter->timer); 1410 adapter->hw.mac.get_link_status = 1; 1411 em_update_link_status(adapter); 1412 callout_reset(&adapter->timer, hz, em_timer, adapter); 1413 } 1414 } 1415 1416 em_rxeof(adapter, count); 1417 em_txeof(adapter); 1418 1419 if (!ifq_is_empty(&ifp->if_snd)) 1420 if_devstart(ifp); 1421 } 1422 1423 static void 1424 em_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1425 { 1426 struct adapter *adapter = ifp->if_softc; 1427 1428 ASSERT_SERIALIZED(ifp->if_serializer); 1429 1430 if (info != NULL) { 1431 int cpuid = adapter->npoll.ifpc_cpuid; 1432 1433 info->ifpi_rx[cpuid].poll_func = em_npoll_compat; 1434 info->ifpi_rx[cpuid].arg = NULL; 1435 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1436 1437 if (ifp->if_flags & IFF_RUNNING) 1438 em_disable_intr(adapter); 1439 ifq_set_cpuid(&ifp->if_snd, cpuid); 1440 } else { 1441 if (ifp->if_flags & IFF_RUNNING) 1442 em_enable_intr(adapter); 1443 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 1444 } 1445 } 1446 1447 #endif /* IFPOLL_ENABLE */ 1448 1449 static void 1450 em_intr(void *xsc) 1451 { 1452 em_intr_body(xsc, TRUE); 1453 } 1454 1455 static void 1456 em_intr_body(struct adapter *adapter, boolean_t chk_asserted) 1457 { 1458 struct ifnet *ifp = &adapter->arpcom.ac_if; 1459 uint32_t reg_icr; 1460 1461 logif(intr_beg); 1462 ASSERT_SERIALIZED(ifp->if_serializer); 1463 1464 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1465 1466 if (chk_asserted && 1467 ((adapter->hw.mac.type >= e1000_82571 && 1468 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1469 reg_icr == 0)) { 1470 logif(intr_end); 1471 return; 1472 } 1473 1474 /* 1475 * XXX: some laptops trigger several spurious interrupts 1476 * on em(4) when in the resume cycle. The ICR register 1477 * reports all-ones value in this case. Processing such 1478 * interrupts would lead to a freeze. I don't know why. 1479 */ 1480 if (reg_icr == 0xffffffff) { 1481 logif(intr_end); 1482 return; 1483 } 1484 1485 if (ifp->if_flags & IFF_RUNNING) { 1486 if (reg_icr & 1487 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1488 em_rxeof(adapter, -1); 1489 if (reg_icr & E1000_ICR_TXDW) { 1490 em_txeof(adapter); 1491 if (!ifq_is_empty(&ifp->if_snd)) 1492 if_devstart(ifp); 1493 } 1494 } 1495 1496 /* Link status change */ 1497 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1498 callout_stop(&adapter->timer); 1499 adapter->hw.mac.get_link_status = 1; 1500 em_update_link_status(adapter); 1501 1502 /* Deal with TX cruft when link lost */ 1503 em_tx_purge(adapter); 1504 1505 callout_reset(&adapter->timer, hz, em_timer, adapter); 1506 } 1507 1508 if (reg_icr & E1000_ICR_RXO) 1509 adapter->rx_overruns++; 1510 1511 logif(intr_end); 1512 } 1513 1514 static void 1515 em_intr_mask(void *xsc) 1516 { 1517 struct adapter *adapter = xsc; 1518 1519 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 1520 /* 1521 * NOTE: 1522 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1523 * so don't check it. 1524 */ 1525 em_intr_body(adapter, FALSE); 1526 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); 1527 } 1528 1529 static void 1530 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1531 { 1532 struct adapter *adapter = ifp->if_softc; 1533 u_char fiber_type = IFM_1000_SX; 1534 1535 ASSERT_SERIALIZED(ifp->if_serializer); 1536 1537 em_update_link_status(adapter); 1538 1539 ifmr->ifm_status = IFM_AVALID; 1540 ifmr->ifm_active = IFM_ETHER; 1541 1542 if (!adapter->link_active) { 1543 ifmr->ifm_active |= IFM_NONE; 1544 return; 1545 } 1546 1547 ifmr->ifm_status |= IFM_ACTIVE; 1548 if (adapter->ifm_flowctrl & IFM_ETH_FORCEPAUSE) 1549 ifmr->ifm_active |= IFM_ETH_FORCEPAUSE; 1550 1551 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1552 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1553 if (adapter->hw.mac.type == e1000_82545) 1554 fiber_type = IFM_1000_LX; 1555 ifmr->ifm_active |= fiber_type | IFM_FDX; 1556 } else { 1557 switch (adapter->link_speed) { 1558 case 10: 1559 ifmr->ifm_active |= IFM_10_T; 1560 break; 1561 case 100: 1562 ifmr->ifm_active |= IFM_100_TX; 1563 break; 1564 1565 case 1000: 1566 ifmr->ifm_active |= IFM_1000_T; 1567 break; 1568 } 1569 if (adapter->link_duplex == FULL_DUPLEX) 1570 ifmr->ifm_active |= IFM_FDX; 1571 else 1572 ifmr->ifm_active |= IFM_HDX; 1573 } 1574 if (ifmr->ifm_active & IFM_FDX) { 1575 ifmr->ifm_active |= 1576 e1000_fc2ifmedia(adapter->hw.fc.current_mode); 1577 } 1578 } 1579 1580 static int 1581 em_media_change(struct ifnet *ifp) 1582 { 1583 struct adapter *adapter = ifp->if_softc; 1584 struct ifmedia *ifm = &adapter->media; 1585 1586 ASSERT_SERIALIZED(ifp->if_serializer); 1587 1588 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1589 return (EINVAL); 1590 1591 if (adapter->hw.mac.type == e1000_pchlan && 1592 (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)) { 1593 if (bootverbose) 1594 if_printf(ifp, "TX PAUSE is not supported on PCH\n"); 1595 return EINVAL; 1596 } 1597 1598 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1599 case IFM_AUTO: 1600 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1601 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1602 break; 1603 1604 case IFM_1000_LX: 1605 case IFM_1000_SX: 1606 case IFM_1000_T: 1607 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1608 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1609 break; 1610 1611 case IFM_100_TX: 1612 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) { 1613 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1614 } else { 1615 if (IFM_OPTIONS(ifm->ifm_media) & 1616 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 1617 if (bootverbose) { 1618 if_printf(ifp, "Flow control is not " 1619 "allowed for half-duplex\n"); 1620 } 1621 return EINVAL; 1622 } 1623 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1624 } 1625 adapter->hw.mac.autoneg = FALSE; 1626 adapter->hw.phy.autoneg_advertised = 0; 1627 break; 1628 1629 case IFM_10_T: 1630 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) { 1631 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1632 } else { 1633 if (IFM_OPTIONS(ifm->ifm_media) & 1634 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 1635 if (bootverbose) { 1636 if_printf(ifp, "Flow control is not " 1637 "allowed for half-duplex\n"); 1638 } 1639 return EINVAL; 1640 } 1641 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1642 } 1643 adapter->hw.mac.autoneg = FALSE; 1644 adapter->hw.phy.autoneg_advertised = 0; 1645 break; 1646 1647 default: 1648 if (bootverbose) { 1649 if_printf(ifp, "Unsupported media type %d\n", 1650 IFM_SUBTYPE(ifm->ifm_media)); 1651 } 1652 return EINVAL; 1653 } 1654 adapter->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK; 1655 1656 if (ifp->if_flags & IFF_RUNNING) 1657 em_init(adapter); 1658 1659 return (0); 1660 } 1661 1662 static int 1663 em_encap(struct adapter *adapter, struct mbuf **m_headp, 1664 int *segs_used, int *idx) 1665 { 1666 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1667 bus_dmamap_t map; 1668 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1669 struct e1000_tx_desc *ctxd = NULL; 1670 struct mbuf *m_head = *m_headp; 1671 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1672 int maxsegs, nsegs, i, j, first, last = 0, error; 1673 1674 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1675 error = em_tso_pullup(adapter, m_headp); 1676 if (error) 1677 return error; 1678 m_head = *m_headp; 1679 } 1680 1681 txd_upper = txd_lower = 0; 1682 txd_used = 0; 1683 1684 /* 1685 * Capture the first descriptor index, this descriptor 1686 * will have the index of the EOP which is the only one 1687 * that now gets a DONE bit writeback. 1688 */ 1689 first = adapter->next_avail_tx_desc; 1690 tx_buffer = &adapter->tx_buffer_area[first]; 1691 tx_buffer_mapped = tx_buffer; 1692 map = tx_buffer->map; 1693 1694 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1695 KASSERT(maxsegs >= adapter->spare_tx_desc, 1696 ("not enough spare TX desc")); 1697 if (adapter->pcix_82544) { 1698 /* Half it; see the comment in em_attach() */ 1699 maxsegs >>= 1; 1700 } 1701 if (maxsegs > EM_MAX_SCATTER) 1702 maxsegs = EM_MAX_SCATTER; 1703 1704 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1705 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1706 if (error) { 1707 if (error == ENOBUFS) 1708 adapter->mbuf_alloc_failed++; 1709 else 1710 adapter->no_tx_dma_setup++; 1711 1712 m_freem(*m_headp); 1713 *m_headp = NULL; 1714 return error; 1715 } 1716 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1717 1718 m_head = *m_headp; 1719 adapter->tx_nsegs += nsegs; 1720 *segs_used += nsegs; 1721 1722 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1723 /* TSO will consume one TX desc */ 1724 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 1725 adapter->tx_nsegs += i; 1726 *segs_used += i; 1727 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1728 /* TX csum offloading will consume one TX desc */ 1729 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower); 1730 adapter->tx_nsegs += i; 1731 *segs_used += i; 1732 } 1733 1734 /* Handle VLAN tag */ 1735 if (m_head->m_flags & M_VLANTAG) { 1736 /* Set the vlan id. */ 1737 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16); 1738 /* Tell hardware to add tag */ 1739 txd_lower |= htole32(E1000_TXD_CMD_VLE); 1740 } 1741 1742 i = adapter->next_avail_tx_desc; 1743 1744 /* Set up our transmit descriptors */ 1745 for (j = 0; j < nsegs; j++) { 1746 /* If adapter is 82544 and on PCIX bus */ 1747 if(adapter->pcix_82544) { 1748 DESC_ARRAY desc_array; 1749 uint32_t array_elements, counter; 1750 1751 /* 1752 * Check the Address and Length combination and 1753 * split the data accordingly 1754 */ 1755 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1756 segs[j].ds_len, &desc_array); 1757 for (counter = 0; counter < array_elements; counter++) { 1758 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1759 1760 tx_buffer = &adapter->tx_buffer_area[i]; 1761 ctxd = &adapter->tx_desc_base[i]; 1762 1763 ctxd->buffer_addr = htole64( 1764 desc_array.descriptor[counter].address); 1765 ctxd->lower.data = htole32( 1766 E1000_TXD_CMD_IFCS | txd_lower | 1767 desc_array.descriptor[counter].length); 1768 ctxd->upper.data = htole32(txd_upper); 1769 1770 last = i; 1771 if (++i == adapter->num_tx_desc) 1772 i = 0; 1773 1774 txd_used++; 1775 } 1776 } else { 1777 tx_buffer = &adapter->tx_buffer_area[i]; 1778 ctxd = &adapter->tx_desc_base[i]; 1779 1780 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1781 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1782 txd_lower | segs[j].ds_len); 1783 ctxd->upper.data = htole32(txd_upper); 1784 1785 last = i; 1786 if (++i == adapter->num_tx_desc) 1787 i = 0; 1788 } 1789 } 1790 1791 adapter->next_avail_tx_desc = i; 1792 if (adapter->pcix_82544) { 1793 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1794 adapter->num_tx_desc_avail -= txd_used; 1795 } else { 1796 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1797 adapter->num_tx_desc_avail -= nsegs; 1798 } 1799 1800 tx_buffer->m_head = m_head; 1801 tx_buffer_mapped->map = tx_buffer->map; 1802 tx_buffer->map = map; 1803 1804 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1805 adapter->tx_nsegs = 0; 1806 1807 /* 1808 * Report Status (RS) is turned on 1809 * every tx_int_nsegs descriptors. 1810 */ 1811 cmd = E1000_TXD_CMD_RS; 1812 1813 /* 1814 * Keep track of the descriptor, which will 1815 * be written back by hardware. 1816 */ 1817 adapter->tx_dd[adapter->tx_dd_tail] = last; 1818 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1819 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1820 } 1821 1822 /* 1823 * Last Descriptor of Packet needs End Of Packet (EOP) 1824 */ 1825 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1826 1827 if (adapter->hw.mac.type == e1000_82547) { 1828 /* 1829 * Advance the Transmit Descriptor Tail (TDT), this tells the 1830 * E1000 that this frame is available to transmit. 1831 */ 1832 if (adapter->link_duplex == HALF_DUPLEX) { 1833 em_82547_move_tail_serialized(adapter); 1834 } else { 1835 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1836 em_82547_update_fifo_head(adapter, 1837 m_head->m_pkthdr.len); 1838 } 1839 } else { 1840 /* 1841 * Defer TDT updating, until enough descriptors are setup 1842 */ 1843 *idx = i; 1844 } 1845 return (0); 1846 } 1847 1848 /* 1849 * 82547 workaround to avoid controller hang in half-duplex environment. 1850 * The workaround is to avoid queuing a large packet that would span 1851 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1852 * in this case. We do that only when FIFO is quiescent. 1853 */ 1854 static void 1855 em_82547_move_tail_serialized(struct adapter *adapter) 1856 { 1857 struct e1000_tx_desc *tx_desc; 1858 uint16_t hw_tdt, sw_tdt, length = 0; 1859 bool eop = 0; 1860 1861 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1862 1863 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1864 sw_tdt = adapter->next_avail_tx_desc; 1865 1866 while (hw_tdt != sw_tdt) { 1867 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1868 length += tx_desc->lower.flags.length; 1869 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1870 if (++hw_tdt == adapter->num_tx_desc) 1871 hw_tdt = 0; 1872 1873 if (eop) { 1874 if (em_82547_fifo_workaround(adapter, length)) { 1875 adapter->tx_fifo_wrk_cnt++; 1876 callout_reset(&adapter->tx_fifo_timer, 1, 1877 em_82547_move_tail, adapter); 1878 break; 1879 } 1880 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1881 em_82547_update_fifo_head(adapter, length); 1882 length = 0; 1883 } 1884 } 1885 } 1886 1887 static void 1888 em_82547_move_tail(void *xsc) 1889 { 1890 struct adapter *adapter = xsc; 1891 struct ifnet *ifp = &adapter->arpcom.ac_if; 1892 1893 lwkt_serialize_enter(ifp->if_serializer); 1894 em_82547_move_tail_serialized(adapter); 1895 lwkt_serialize_exit(ifp->if_serializer); 1896 } 1897 1898 static int 1899 em_82547_fifo_workaround(struct adapter *adapter, int len) 1900 { 1901 int fifo_space, fifo_pkt_len; 1902 1903 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1904 1905 if (adapter->link_duplex == HALF_DUPLEX) { 1906 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1907 1908 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1909 if (em_82547_tx_fifo_reset(adapter)) 1910 return (0); 1911 else 1912 return (1); 1913 } 1914 } 1915 return (0); 1916 } 1917 1918 static void 1919 em_82547_update_fifo_head(struct adapter *adapter, int len) 1920 { 1921 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1922 1923 /* tx_fifo_head is always 16 byte aligned */ 1924 adapter->tx_fifo_head += fifo_pkt_len; 1925 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1926 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1927 } 1928 1929 static int 1930 em_82547_tx_fifo_reset(struct adapter *adapter) 1931 { 1932 uint32_t tctl; 1933 1934 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1935 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1936 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1937 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1938 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1939 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1940 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1941 /* Disable TX unit */ 1942 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1943 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1944 tctl & ~E1000_TCTL_EN); 1945 1946 /* Reset FIFO pointers */ 1947 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1948 adapter->tx_head_addr); 1949 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1950 adapter->tx_head_addr); 1951 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1952 adapter->tx_head_addr); 1953 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1954 adapter->tx_head_addr); 1955 1956 /* Re-enable TX unit */ 1957 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1958 E1000_WRITE_FLUSH(&adapter->hw); 1959 1960 adapter->tx_fifo_head = 0; 1961 adapter->tx_fifo_reset_cnt++; 1962 1963 return (TRUE); 1964 } else { 1965 return (FALSE); 1966 } 1967 } 1968 1969 static void 1970 em_set_promisc(struct adapter *adapter) 1971 { 1972 struct ifnet *ifp = &adapter->arpcom.ac_if; 1973 uint32_t reg_rctl; 1974 1975 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1976 1977 if (ifp->if_flags & IFF_PROMISC) { 1978 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1979 /* Turn this on if you want to see bad packets */ 1980 if (em_debug_sbp) 1981 reg_rctl |= E1000_RCTL_SBP; 1982 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1983 } else if (ifp->if_flags & IFF_ALLMULTI) { 1984 reg_rctl |= E1000_RCTL_MPE; 1985 reg_rctl &= ~E1000_RCTL_UPE; 1986 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1987 } 1988 } 1989 1990 static void 1991 em_disable_promisc(struct adapter *adapter) 1992 { 1993 uint32_t reg_rctl; 1994 1995 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1996 1997 reg_rctl &= ~E1000_RCTL_UPE; 1998 reg_rctl &= ~E1000_RCTL_MPE; 1999 reg_rctl &= ~E1000_RCTL_SBP; 2000 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2001 } 2002 2003 static void 2004 em_set_multi(struct adapter *adapter) 2005 { 2006 struct ifnet *ifp = &adapter->arpcom.ac_if; 2007 struct ifmultiaddr *ifma; 2008 uint32_t reg_rctl = 0; 2009 uint8_t *mta; 2010 int mcnt = 0; 2011 2012 mta = adapter->mta; 2013 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2014 2015 if (adapter->hw.mac.type == e1000_82542 && 2016 adapter->hw.revision_id == E1000_REVISION_2) { 2017 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2018 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2019 e1000_pci_clear_mwi(&adapter->hw); 2020 reg_rctl |= E1000_RCTL_RST; 2021 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2022 msec_delay(5); 2023 } 2024 2025 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2026 if (ifma->ifma_addr->sa_family != AF_LINK) 2027 continue; 2028 2029 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2030 break; 2031 2032 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2033 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2034 mcnt++; 2035 } 2036 2037 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 2038 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2039 reg_rctl |= E1000_RCTL_MPE; 2040 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2041 } else { 2042 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 2043 } 2044 2045 if (adapter->hw.mac.type == e1000_82542 && 2046 adapter->hw.revision_id == E1000_REVISION_2) { 2047 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2048 reg_rctl &= ~E1000_RCTL_RST; 2049 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2050 msec_delay(5); 2051 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2052 e1000_pci_set_mwi(&adapter->hw); 2053 } 2054 } 2055 2056 /* 2057 * This routine checks for link status and updates statistics. 2058 */ 2059 static void 2060 em_timer(void *xsc) 2061 { 2062 struct adapter *adapter = xsc; 2063 struct ifnet *ifp = &adapter->arpcom.ac_if; 2064 2065 lwkt_serialize_enter(ifp->if_serializer); 2066 2067 em_update_link_status(adapter); 2068 em_update_stats(adapter); 2069 2070 /* Reset LAA into RAR[0] on 82571 */ 2071 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 2072 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2073 2074 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 2075 em_print_hw_stats(adapter); 2076 2077 em_smartspeed(adapter); 2078 2079 callout_reset(&adapter->timer, hz, em_timer, adapter); 2080 2081 lwkt_serialize_exit(ifp->if_serializer); 2082 } 2083 2084 static void 2085 em_update_link_status(struct adapter *adapter) 2086 { 2087 struct e1000_hw *hw = &adapter->hw; 2088 struct ifnet *ifp = &adapter->arpcom.ac_if; 2089 device_t dev = adapter->dev; 2090 uint32_t link_check = 0; 2091 2092 /* Get the cached link value or read phy for real */ 2093 switch (hw->phy.media_type) { 2094 case e1000_media_type_copper: 2095 if (hw->mac.get_link_status) { 2096 /* Do the work to read phy */ 2097 e1000_check_for_link(hw); 2098 link_check = !hw->mac.get_link_status; 2099 if (link_check) /* ESB2 fix */ 2100 e1000_cfg_on_link_up(hw); 2101 } else { 2102 link_check = TRUE; 2103 } 2104 break; 2105 2106 case e1000_media_type_fiber: 2107 e1000_check_for_link(hw); 2108 link_check = 2109 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 2110 break; 2111 2112 case e1000_media_type_internal_serdes: 2113 e1000_check_for_link(hw); 2114 link_check = adapter->hw.mac.serdes_has_link; 2115 break; 2116 2117 case e1000_media_type_unknown: 2118 default: 2119 break; 2120 } 2121 2122 /* Now check for a transition */ 2123 if (link_check && adapter->link_active == 0) { 2124 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2125 &adapter->link_duplex); 2126 2127 /* 2128 * Check if we should enable/disable SPEED_MODE bit on 2129 * 82571/82572 2130 */ 2131 if (adapter->link_speed != SPEED_1000 && 2132 (hw->mac.type == e1000_82571 || 2133 hw->mac.type == e1000_82572)) { 2134 int tarc0; 2135 2136 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2137 tarc0 &= ~SPEED_MODE_BIT; 2138 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2139 } 2140 if (bootverbose) { 2141 char flowctrl[IFM_ETH_FC_STRLEN]; 2142 2143 e1000_fc2str(hw->fc.current_mode, flowctrl, 2144 sizeof(flowctrl)); 2145 device_printf(dev, "Link is up %d Mbps %s, " 2146 "Flow control: %s\n", 2147 adapter->link_speed, 2148 (adapter->link_duplex == FULL_DUPLEX) ? 2149 "Full Duplex" : "Half Duplex", 2150 flowctrl); 2151 } 2152 if (adapter->ifm_flowctrl & IFM_ETH_FORCEPAUSE) 2153 e1000_force_flowctrl(hw, adapter->ifm_flowctrl); 2154 adapter->link_active = 1; 2155 adapter->smartspeed = 0; 2156 ifp->if_baudrate = adapter->link_speed * 1000000; 2157 ifp->if_link_state = LINK_STATE_UP; 2158 if_link_state_change(ifp); 2159 } else if (!link_check && adapter->link_active == 1) { 2160 ifp->if_baudrate = adapter->link_speed = 0; 2161 adapter->link_duplex = 0; 2162 if (bootverbose) 2163 device_printf(dev, "Link is Down\n"); 2164 adapter->link_active = 0; 2165 #if 0 2166 /* Link down, disable watchdog */ 2167 if->if_timer = 0; 2168 #endif 2169 ifp->if_link_state = LINK_STATE_DOWN; 2170 if_link_state_change(ifp); 2171 } 2172 } 2173 2174 static void 2175 em_stop(struct adapter *adapter) 2176 { 2177 struct ifnet *ifp = &adapter->arpcom.ac_if; 2178 int i; 2179 2180 ASSERT_SERIALIZED(ifp->if_serializer); 2181 2182 em_disable_intr(adapter); 2183 2184 callout_stop(&adapter->timer); 2185 callout_stop(&adapter->tx_fifo_timer); 2186 2187 ifp->if_flags &= ~IFF_RUNNING; 2188 ifq_clr_oactive(&ifp->if_snd); 2189 ifp->if_timer = 0; 2190 2191 e1000_reset_hw(&adapter->hw); 2192 if (adapter->hw.mac.type >= e1000_82544) 2193 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2194 2195 for (i = 0; i < adapter->num_tx_desc; i++) { 2196 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2197 2198 if (tx_buffer->m_head != NULL) { 2199 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2200 m_freem(tx_buffer->m_head); 2201 tx_buffer->m_head = NULL; 2202 } 2203 } 2204 2205 for (i = 0; i < adapter->num_rx_desc; i++) { 2206 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2207 2208 if (rx_buffer->m_head != NULL) { 2209 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2210 m_freem(rx_buffer->m_head); 2211 rx_buffer->m_head = NULL; 2212 } 2213 } 2214 2215 if (adapter->fmp != NULL) 2216 m_freem(adapter->fmp); 2217 adapter->fmp = NULL; 2218 adapter->lmp = NULL; 2219 2220 adapter->csum_flags = 0; 2221 adapter->csum_lhlen = 0; 2222 adapter->csum_iphlen = 0; 2223 adapter->csum_thlen = 0; 2224 adapter->csum_mss = 0; 2225 adapter->csum_pktlen = 0; 2226 2227 adapter->tx_dd_head = 0; 2228 adapter->tx_dd_tail = 0; 2229 adapter->tx_nsegs = 0; 2230 } 2231 2232 static int 2233 em_get_hw_info(struct adapter *adapter) 2234 { 2235 device_t dev = adapter->dev; 2236 2237 /* Save off the information about this board */ 2238 adapter->hw.vendor_id = pci_get_vendor(dev); 2239 adapter->hw.device_id = pci_get_device(dev); 2240 adapter->hw.revision_id = pci_get_revid(dev); 2241 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2242 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2243 2244 /* Do Shared Code Init and Setup */ 2245 if (e1000_set_mac_type(&adapter->hw)) 2246 return ENXIO; 2247 return 0; 2248 } 2249 2250 static int 2251 em_alloc_pci_res(struct adapter *adapter) 2252 { 2253 device_t dev = adapter->dev; 2254 u_int intr_flags; 2255 int val, rid, msi_enable; 2256 2257 /* Enable bus mastering */ 2258 pci_enable_busmaster(dev); 2259 2260 adapter->memory_rid = EM_BAR_MEM; 2261 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2262 &adapter->memory_rid, RF_ACTIVE); 2263 if (adapter->memory == NULL) { 2264 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2265 return (ENXIO); 2266 } 2267 adapter->osdep.mem_bus_space_tag = 2268 rman_get_bustag(adapter->memory); 2269 adapter->osdep.mem_bus_space_handle = 2270 rman_get_bushandle(adapter->memory); 2271 2272 /* XXX This is quite goofy, it is not actually used */ 2273 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2274 2275 /* Only older adapters use IO mapping */ 2276 if (adapter->hw.mac.type > e1000_82543 && 2277 adapter->hw.mac.type < e1000_82571) { 2278 /* Figure our where our IO BAR is ? */ 2279 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2280 val = pci_read_config(dev, rid, 4); 2281 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2282 adapter->io_rid = rid; 2283 break; 2284 } 2285 rid += 4; 2286 /* check for 64bit BAR */ 2287 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2288 rid += 4; 2289 } 2290 if (rid >= PCIR_CARDBUSCIS) { 2291 device_printf(dev, "Unable to locate IO BAR\n"); 2292 return (ENXIO); 2293 } 2294 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2295 &adapter->io_rid, RF_ACTIVE); 2296 if (adapter->ioport == NULL) { 2297 device_printf(dev, "Unable to allocate bus resource: " 2298 "ioport\n"); 2299 return (ENXIO); 2300 } 2301 adapter->hw.io_base = 0; 2302 adapter->osdep.io_bus_space_tag = 2303 rman_get_bustag(adapter->ioport); 2304 adapter->osdep.io_bus_space_handle = 2305 rman_get_bushandle(adapter->ioport); 2306 } 2307 2308 /* 2309 * Don't enable MSI-X on 82574, see: 2310 * 82574 specification update errata #15 2311 * 2312 * Don't enable MSI on PCI/PCI-X chips, see: 2313 * 82540 specification update errata #6 2314 * 82545 specification update errata #4 2315 * 2316 * Don't enable MSI on 82571/82572, see: 2317 * 82571/82572 specification update errata #63 2318 */ 2319 msi_enable = em_msi_enable; 2320 if (msi_enable && 2321 (!pci_is_pcie(dev) || 2322 adapter->hw.mac.type == e1000_82571 || 2323 adapter->hw.mac.type == e1000_82572)) 2324 msi_enable = 0; 2325 2326 adapter->intr_type = pci_alloc_1intr(dev, msi_enable, 2327 &adapter->intr_rid, &intr_flags); 2328 2329 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) { 2330 int unshared; 2331 2332 unshared = device_getenv_int(dev, "irq.unshared", 0); 2333 if (!unshared) { 2334 adapter->flags |= EM_FLAG_SHARED_INTR; 2335 if (bootverbose) 2336 device_printf(dev, "IRQ shared\n"); 2337 } else { 2338 intr_flags &= ~RF_SHAREABLE; 2339 if (bootverbose) 2340 device_printf(dev, "IRQ unshared\n"); 2341 } 2342 } 2343 2344 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2345 &adapter->intr_rid, intr_flags); 2346 if (adapter->intr_res == NULL) { 2347 device_printf(dev, "Unable to allocate bus resource: " 2348 "interrupt\n"); 2349 return (ENXIO); 2350 } 2351 2352 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2353 adapter->hw.back = &adapter->osdep; 2354 return (0); 2355 } 2356 2357 static void 2358 em_free_pci_res(struct adapter *adapter) 2359 { 2360 device_t dev = adapter->dev; 2361 2362 if (adapter->intr_res != NULL) { 2363 bus_release_resource(dev, SYS_RES_IRQ, 2364 adapter->intr_rid, adapter->intr_res); 2365 } 2366 2367 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2368 pci_release_msi(dev); 2369 2370 if (adapter->memory != NULL) { 2371 bus_release_resource(dev, SYS_RES_MEMORY, 2372 adapter->memory_rid, adapter->memory); 2373 } 2374 2375 if (adapter->flash != NULL) { 2376 bus_release_resource(dev, SYS_RES_MEMORY, 2377 adapter->flash_rid, adapter->flash); 2378 } 2379 2380 if (adapter->ioport != NULL) { 2381 bus_release_resource(dev, SYS_RES_IOPORT, 2382 adapter->io_rid, adapter->ioport); 2383 } 2384 } 2385 2386 static int 2387 em_reset(struct adapter *adapter) 2388 { 2389 device_t dev = adapter->dev; 2390 uint16_t rx_buffer_size; 2391 uint32_t pba; 2392 2393 /* When hardware is reset, fifo_head is also reset */ 2394 adapter->tx_fifo_head = 0; 2395 2396 /* Set up smart power down as default off on newer adapters. */ 2397 if (!em_smart_pwr_down && 2398 (adapter->hw.mac.type == e1000_82571 || 2399 adapter->hw.mac.type == e1000_82572)) { 2400 uint16_t phy_tmp = 0; 2401 2402 /* Speed up time to link by disabling smart power down. */ 2403 e1000_read_phy_reg(&adapter->hw, 2404 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2405 phy_tmp &= ~IGP02E1000_PM_SPD; 2406 e1000_write_phy_reg(&adapter->hw, 2407 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2408 } 2409 2410 /* 2411 * Packet Buffer Allocation (PBA) 2412 * Writing PBA sets the receive portion of the buffer 2413 * the remainder is used for the transmit buffer. 2414 * 2415 * Devices before the 82547 had a Packet Buffer of 64K. 2416 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 2417 * After the 82547 the buffer was reduced to 40K. 2418 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 2419 * Note: default does not leave enough room for Jumbo Frame >10k. 2420 */ 2421 switch (adapter->hw.mac.type) { 2422 case e1000_82547: 2423 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 2424 if (adapter->hw.mac.max_frame_size > 8192) 2425 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2426 else 2427 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2428 adapter->tx_fifo_head = 0; 2429 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 2430 adapter->tx_fifo_size = 2431 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 2432 break; 2433 2434 /* Total Packet Buffer on these is 48K */ 2435 case e1000_82571: 2436 case e1000_82572: 2437 case e1000_80003es2lan: 2438 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2439 break; 2440 2441 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2442 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2443 break; 2444 2445 case e1000_82574: 2446 case e1000_82583: 2447 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2448 break; 2449 2450 case e1000_ich8lan: 2451 pba = E1000_PBA_8K; 2452 break; 2453 2454 case e1000_ich9lan: 2455 case e1000_ich10lan: 2456 #define E1000_PBA_10K 0x000A 2457 pba = E1000_PBA_10K; 2458 break; 2459 2460 case e1000_pchlan: 2461 case e1000_pch2lan: 2462 case e1000_pch_lpt: 2463 pba = E1000_PBA_26K; 2464 break; 2465 2466 default: 2467 /* Devices before 82547 had a Packet Buffer of 64K. */ 2468 if (adapter->hw.mac.max_frame_size > 8192) 2469 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2470 else 2471 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2472 } 2473 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2474 2475 /* 2476 * These parameters control the automatic generation (Tx) and 2477 * response (Rx) to Ethernet PAUSE frames. 2478 * - High water mark should allow for at least two frames to be 2479 * received after sending an XOFF. 2480 * - Low water mark works best when it is very near the high water mark. 2481 * This allows the receiver to restart by sending XON when it has 2482 * drained a bit. Here we use an arbitary value of 1500 which will 2483 * restart after one full frame is pulled from the buffer. There 2484 * could be several smaller frames in the buffer and if so they will 2485 * not trigger the XON until their total number reduces the buffer 2486 * by 1500. 2487 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2488 */ 2489 rx_buffer_size = 2490 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2491 2492 adapter->hw.fc.high_water = rx_buffer_size - 2493 roundup2(adapter->hw.mac.max_frame_size, 1024); 2494 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2495 2496 if (adapter->hw.mac.type == e1000_80003es2lan) 2497 adapter->hw.fc.pause_time = 0xFFFF; 2498 else 2499 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2500 2501 adapter->hw.fc.send_xon = TRUE; 2502 2503 adapter->hw.fc.requested_mode = e1000_ifmedia2fc(adapter->ifm_flowctrl); 2504 2505 /* 2506 * Device specific overrides/settings 2507 */ 2508 switch (adapter->hw.mac.type) { 2509 case e1000_pchlan: 2510 KASSERT(adapter->hw.fc.requested_mode == e1000_fc_rx_pause || 2511 adapter->hw.fc.requested_mode == e1000_fc_none, 2512 ("unsupported flow control on PCH %d", 2513 adapter->hw.fc.requested_mode)); 2514 adapter->hw.fc.pause_time = 0xFFFF; /* override */ 2515 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2516 adapter->hw.fc.high_water = 0x3500; 2517 adapter->hw.fc.low_water = 0x1500; 2518 } else { 2519 adapter->hw.fc.high_water = 0x5000; 2520 adapter->hw.fc.low_water = 0x3000; 2521 } 2522 adapter->hw.fc.refresh_time = 0x1000; 2523 break; 2524 2525 case e1000_pch2lan: 2526 case e1000_pch_lpt: 2527 adapter->hw.fc.high_water = 0x5C20; 2528 adapter->hw.fc.low_water = 0x5048; 2529 adapter->hw.fc.pause_time = 0x0650; 2530 adapter->hw.fc.refresh_time = 0x0400; 2531 /* Jumbos need adjusted PBA */ 2532 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2533 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2534 else 2535 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2536 break; 2537 2538 case e1000_ich9lan: 2539 case e1000_ich10lan: 2540 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2541 adapter->hw.fc.high_water = 0x2800; 2542 adapter->hw.fc.low_water = 2543 adapter->hw.fc.high_water - 8; 2544 break; 2545 } 2546 /* FALL THROUGH */ 2547 default: 2548 if (adapter->hw.mac.type == e1000_80003es2lan) 2549 adapter->hw.fc.pause_time = 0xFFFF; 2550 break; 2551 } 2552 2553 /* Issue a global reset */ 2554 e1000_reset_hw(&adapter->hw); 2555 if (adapter->hw.mac.type >= e1000_82544) 2556 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2557 em_disable_aspm(adapter); 2558 2559 if (e1000_init_hw(&adapter->hw) < 0) { 2560 device_printf(dev, "Hardware Initialization Failed\n"); 2561 return (EIO); 2562 } 2563 2564 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2565 e1000_get_phy_info(&adapter->hw); 2566 e1000_check_for_link(&adapter->hw); 2567 2568 return (0); 2569 } 2570 2571 static void 2572 em_setup_ifp(struct adapter *adapter) 2573 { 2574 struct ifnet *ifp = &adapter->arpcom.ac_if; 2575 2576 if_initname(ifp, device_get_name(adapter->dev), 2577 device_get_unit(adapter->dev)); 2578 ifp->if_softc = adapter; 2579 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2580 ifp->if_init = em_init; 2581 ifp->if_ioctl = em_ioctl; 2582 ifp->if_start = em_start; 2583 #ifdef IFPOLL_ENABLE 2584 ifp->if_npoll = em_npoll; 2585 #endif 2586 ifp->if_watchdog = em_watchdog; 2587 ifp->if_nmbclusters = adapter->num_rx_desc; 2588 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2589 ifq_set_ready(&ifp->if_snd); 2590 2591 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2592 2593 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2594 if (adapter->hw.mac.type >= e1000_82543) 2595 ifp->if_capabilities |= IFCAP_HWCSUM; 2596 if (adapter->flags & EM_FLAG_TSO) 2597 ifp->if_capabilities |= IFCAP_TSO; 2598 ifp->if_capenable = ifp->if_capabilities; 2599 2600 if (ifp->if_capenable & IFCAP_TXCSUM) 2601 ifp->if_hwassist |= EM_CSUM_FEATURES; 2602 if (ifp->if_capenable & IFCAP_TSO) 2603 ifp->if_hwassist |= CSUM_TSO; 2604 2605 /* 2606 * Tell the upper layer(s) we support long frames. 2607 */ 2608 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2609 2610 /* 2611 * Specify the media types supported by this adapter and register 2612 * callbacks to update media and link information 2613 */ 2614 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2615 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2616 u_char fiber_type = IFM_1000_SX; /* default type */ 2617 2618 if (adapter->hw.mac.type == e1000_82545) 2619 fiber_type = IFM_1000_LX; 2620 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2621 0, NULL); 2622 } else { 2623 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2624 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2625 0, NULL); 2626 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2627 0, NULL); 2628 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2629 0, NULL); 2630 if (adapter->hw.phy.type != e1000_phy_ife) { 2631 ifmedia_add(&adapter->media, 2632 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2633 } 2634 } 2635 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2636 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO | 2637 adapter->ifm_flowctrl); 2638 } 2639 2640 2641 /* 2642 * Workaround for SmartSpeed on 82541 and 82547 controllers 2643 */ 2644 static void 2645 em_smartspeed(struct adapter *adapter) 2646 { 2647 uint16_t phy_tmp; 2648 2649 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2650 adapter->hw.mac.autoneg == 0 || 2651 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2652 return; 2653 2654 if (adapter->smartspeed == 0) { 2655 /* 2656 * If Master/Slave config fault is asserted twice, 2657 * we assume back-to-back 2658 */ 2659 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2660 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2661 return; 2662 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2663 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2664 e1000_read_phy_reg(&adapter->hw, 2665 PHY_1000T_CTRL, &phy_tmp); 2666 if (phy_tmp & CR_1000T_MS_ENABLE) { 2667 phy_tmp &= ~CR_1000T_MS_ENABLE; 2668 e1000_write_phy_reg(&adapter->hw, 2669 PHY_1000T_CTRL, phy_tmp); 2670 adapter->smartspeed++; 2671 if (adapter->hw.mac.autoneg && 2672 !e1000_phy_setup_autoneg(&adapter->hw) && 2673 !e1000_read_phy_reg(&adapter->hw, 2674 PHY_CONTROL, &phy_tmp)) { 2675 phy_tmp |= MII_CR_AUTO_NEG_EN | 2676 MII_CR_RESTART_AUTO_NEG; 2677 e1000_write_phy_reg(&adapter->hw, 2678 PHY_CONTROL, phy_tmp); 2679 } 2680 } 2681 } 2682 return; 2683 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2684 /* If still no link, perhaps using 2/3 pair cable */ 2685 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2686 phy_tmp |= CR_1000T_MS_ENABLE; 2687 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2688 if (adapter->hw.mac.autoneg && 2689 !e1000_phy_setup_autoneg(&adapter->hw) && 2690 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2691 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2692 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2693 } 2694 } 2695 2696 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2697 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2698 adapter->smartspeed = 0; 2699 } 2700 2701 static int 2702 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2703 struct em_dma_alloc *dma) 2704 { 2705 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2706 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2707 &dma->dma_tag, &dma->dma_map, 2708 &dma->dma_paddr); 2709 if (dma->dma_vaddr == NULL) 2710 return ENOMEM; 2711 else 2712 return 0; 2713 } 2714 2715 static void 2716 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2717 { 2718 if (dma->dma_tag == NULL) 2719 return; 2720 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2721 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2722 bus_dma_tag_destroy(dma->dma_tag); 2723 } 2724 2725 static int 2726 em_create_tx_ring(struct adapter *adapter) 2727 { 2728 device_t dev = adapter->dev; 2729 struct em_buffer *tx_buffer; 2730 int error, i; 2731 2732 adapter->tx_buffer_area = 2733 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2734 M_DEVBUF, M_WAITOK | M_ZERO); 2735 2736 /* 2737 * Create DMA tags for tx buffers 2738 */ 2739 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2740 1, 0, /* alignment, bounds */ 2741 BUS_SPACE_MAXADDR, /* lowaddr */ 2742 BUS_SPACE_MAXADDR, /* highaddr */ 2743 NULL, NULL, /* filter, filterarg */ 2744 EM_TSO_SIZE, /* maxsize */ 2745 EM_MAX_SCATTER, /* nsegments */ 2746 PAGE_SIZE, /* maxsegsize */ 2747 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2748 BUS_DMA_ONEBPAGE, /* flags */ 2749 &adapter->txtag); 2750 if (error) { 2751 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2752 kfree(adapter->tx_buffer_area, M_DEVBUF); 2753 adapter->tx_buffer_area = NULL; 2754 return error; 2755 } 2756 2757 /* 2758 * Create DMA maps for tx buffers 2759 */ 2760 for (i = 0; i < adapter->num_tx_desc; i++) { 2761 tx_buffer = &adapter->tx_buffer_area[i]; 2762 2763 error = bus_dmamap_create(adapter->txtag, 2764 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2765 &tx_buffer->map); 2766 if (error) { 2767 device_printf(dev, "Unable to create TX DMA map\n"); 2768 em_destroy_tx_ring(adapter, i); 2769 return error; 2770 } 2771 } 2772 return (0); 2773 } 2774 2775 static void 2776 em_init_tx_ring(struct adapter *adapter) 2777 { 2778 /* Clear the old ring contents */ 2779 bzero(adapter->tx_desc_base, 2780 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2781 2782 /* Reset state */ 2783 adapter->next_avail_tx_desc = 0; 2784 adapter->next_tx_to_clean = 0; 2785 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2786 } 2787 2788 static void 2789 em_init_tx_unit(struct adapter *adapter) 2790 { 2791 uint32_t tctl, tarc, tipg = 0; 2792 uint64_t bus_addr; 2793 2794 /* Setup the Base and Length of the Tx Descriptor Ring */ 2795 bus_addr = adapter->txdma.dma_paddr; 2796 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2797 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2798 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2799 (uint32_t)(bus_addr >> 32)); 2800 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2801 (uint32_t)bus_addr); 2802 /* Setup the HW Tx Head and Tail descriptor pointers */ 2803 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2804 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2805 2806 /* Set the default values for the Tx Inter Packet Gap timer */ 2807 switch (adapter->hw.mac.type) { 2808 case e1000_82542: 2809 tipg = DEFAULT_82542_TIPG_IPGT; 2810 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2811 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2812 break; 2813 2814 case e1000_80003es2lan: 2815 tipg = DEFAULT_82543_TIPG_IPGR1; 2816 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2817 E1000_TIPG_IPGR2_SHIFT; 2818 break; 2819 2820 default: 2821 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2822 adapter->hw.phy.media_type == 2823 e1000_media_type_internal_serdes) 2824 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2825 else 2826 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2827 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2828 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2829 break; 2830 } 2831 2832 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2833 2834 /* NOTE: 0 is not allowed for TIDV */ 2835 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2836 if(adapter->hw.mac.type >= e1000_82540) 2837 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2838 2839 if (adapter->hw.mac.type == e1000_82571 || 2840 adapter->hw.mac.type == e1000_82572) { 2841 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2842 tarc |= SPEED_MODE_BIT; 2843 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2844 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2845 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2846 tarc |= 1; 2847 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2848 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2849 tarc |= 1; 2850 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2851 } 2852 2853 /* Program the Transmit Control Register */ 2854 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2855 tctl &= ~E1000_TCTL_CT; 2856 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2857 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2858 2859 if (adapter->hw.mac.type >= e1000_82571) 2860 tctl |= E1000_TCTL_MULR; 2861 2862 /* This write will effectively turn on the transmit unit. */ 2863 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2864 2865 if (adapter->hw.mac.type == e1000_82571 || 2866 adapter->hw.mac.type == e1000_82572 || 2867 adapter->hw.mac.type == e1000_80003es2lan) { 2868 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 2869 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2870 tarc &= ~(1 << 28); 2871 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2872 } 2873 } 2874 2875 static void 2876 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2877 { 2878 struct em_buffer *tx_buffer; 2879 int i; 2880 2881 if (adapter->tx_buffer_area == NULL) 2882 return; 2883 2884 for (i = 0; i < ndesc; i++) { 2885 tx_buffer = &adapter->tx_buffer_area[i]; 2886 2887 KKASSERT(tx_buffer->m_head == NULL); 2888 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2889 } 2890 bus_dma_tag_destroy(adapter->txtag); 2891 2892 kfree(adapter->tx_buffer_area, M_DEVBUF); 2893 adapter->tx_buffer_area = NULL; 2894 } 2895 2896 /* 2897 * The offload context needs to be set when we transfer the first 2898 * packet of a particular protocol (TCP/UDP). This routine has been 2899 * enhanced to deal with inserted VLAN headers. 2900 * 2901 * If the new packet's ether header length, ip header length and 2902 * csum offloading type are same as the previous packet, we should 2903 * avoid allocating a new csum context descriptor; mainly to take 2904 * advantage of the pipeline effect of the TX data read request. 2905 * 2906 * This function returns number of TX descrptors allocated for 2907 * csum context. 2908 */ 2909 static int 2910 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2911 uint32_t *txd_upper, uint32_t *txd_lower) 2912 { 2913 struct e1000_context_desc *TXD; 2914 int curr_txd, ehdrlen, csum_flags; 2915 uint32_t cmd, hdr_len, ip_hlen; 2916 2917 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2918 ip_hlen = mp->m_pkthdr.csum_iphlen; 2919 ehdrlen = mp->m_pkthdr.csum_lhlen; 2920 2921 if (adapter->csum_lhlen == ehdrlen && 2922 adapter->csum_iphlen == ip_hlen && 2923 adapter->csum_flags == csum_flags) { 2924 /* 2925 * Same csum offload context as the previous packets; 2926 * just return. 2927 */ 2928 *txd_upper = adapter->csum_txd_upper; 2929 *txd_lower = adapter->csum_txd_lower; 2930 return 0; 2931 } 2932 2933 /* 2934 * Setup a new csum offload context. 2935 */ 2936 2937 curr_txd = adapter->next_avail_tx_desc; 2938 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2939 2940 cmd = 0; 2941 2942 /* Setup of IP header checksum. */ 2943 if (csum_flags & CSUM_IP) { 2944 /* 2945 * Start offset for header checksum calculation. 2946 * End offset for header checksum calculation. 2947 * Offset of place to put the checksum. 2948 */ 2949 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2950 TXD->lower_setup.ip_fields.ipcse = 2951 htole16(ehdrlen + ip_hlen - 1); 2952 TXD->lower_setup.ip_fields.ipcso = 2953 ehdrlen + offsetof(struct ip, ip_sum); 2954 cmd |= E1000_TXD_CMD_IP; 2955 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2956 } 2957 hdr_len = ehdrlen + ip_hlen; 2958 2959 if (csum_flags & CSUM_TCP) { 2960 /* 2961 * Start offset for payload checksum calculation. 2962 * End offset for payload checksum calculation. 2963 * Offset of place to put the checksum. 2964 */ 2965 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2966 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2967 TXD->upper_setup.tcp_fields.tucso = 2968 hdr_len + offsetof(struct tcphdr, th_sum); 2969 cmd |= E1000_TXD_CMD_TCP; 2970 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2971 } else if (csum_flags & CSUM_UDP) { 2972 /* 2973 * Start offset for header checksum calculation. 2974 * End offset for header checksum calculation. 2975 * Offset of place to put the checksum. 2976 */ 2977 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2978 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2979 TXD->upper_setup.tcp_fields.tucso = 2980 hdr_len + offsetof(struct udphdr, uh_sum); 2981 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2982 } 2983 2984 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2985 E1000_TXD_DTYP_D; /* Data descr */ 2986 2987 /* Save the information for this csum offloading context */ 2988 adapter->csum_lhlen = ehdrlen; 2989 adapter->csum_iphlen = ip_hlen; 2990 adapter->csum_flags = csum_flags; 2991 adapter->csum_txd_upper = *txd_upper; 2992 adapter->csum_txd_lower = *txd_lower; 2993 2994 TXD->tcp_seg_setup.data = htole32(0); 2995 TXD->cmd_and_length = 2996 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2997 2998 if (++curr_txd == adapter->num_tx_desc) 2999 curr_txd = 0; 3000 3001 KKASSERT(adapter->num_tx_desc_avail > 0); 3002 adapter->num_tx_desc_avail--; 3003 3004 adapter->next_avail_tx_desc = curr_txd; 3005 return 1; 3006 } 3007 3008 static void 3009 em_txeof(struct adapter *adapter) 3010 { 3011 struct ifnet *ifp = &adapter->arpcom.ac_if; 3012 struct em_buffer *tx_buffer; 3013 int first, num_avail; 3014 3015 if (adapter->tx_dd_head == adapter->tx_dd_tail) 3016 return; 3017 3018 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3019 return; 3020 3021 num_avail = adapter->num_tx_desc_avail; 3022 first = adapter->next_tx_to_clean; 3023 3024 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 3025 struct e1000_tx_desc *tx_desc; 3026 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3027 3028 tx_desc = &adapter->tx_desc_base[dd_idx]; 3029 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 3030 EM_INC_TXDD_IDX(adapter->tx_dd_head); 3031 3032 if (++dd_idx == adapter->num_tx_desc) 3033 dd_idx = 0; 3034 3035 while (first != dd_idx) { 3036 logif(pkt_txclean); 3037 3038 num_avail++; 3039 3040 tx_buffer = &adapter->tx_buffer_area[first]; 3041 if (tx_buffer->m_head) { 3042 bus_dmamap_unload(adapter->txtag, 3043 tx_buffer->map); 3044 m_freem(tx_buffer->m_head); 3045 tx_buffer->m_head = NULL; 3046 } 3047 3048 if (++first == adapter->num_tx_desc) 3049 first = 0; 3050 } 3051 } else { 3052 break; 3053 } 3054 } 3055 adapter->next_tx_to_clean = first; 3056 adapter->num_tx_desc_avail = num_avail; 3057 3058 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 3059 adapter->tx_dd_head = 0; 3060 adapter->tx_dd_tail = 0; 3061 } 3062 3063 if (!EM_IS_OACTIVE(adapter)) { 3064 ifq_clr_oactive(&ifp->if_snd); 3065 3066 /* All clean, turn off the timer */ 3067 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3068 ifp->if_timer = 0; 3069 } 3070 } 3071 3072 static void 3073 em_tx_collect(struct adapter *adapter) 3074 { 3075 struct ifnet *ifp = &adapter->arpcom.ac_if; 3076 struct em_buffer *tx_buffer; 3077 int tdh, first, num_avail, dd_idx = -1; 3078 3079 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3080 return; 3081 3082 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 3083 if (tdh == adapter->next_tx_to_clean) 3084 return; 3085 3086 if (adapter->tx_dd_head != adapter->tx_dd_tail) 3087 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3088 3089 num_avail = adapter->num_tx_desc_avail; 3090 first = adapter->next_tx_to_clean; 3091 3092 while (first != tdh) { 3093 logif(pkt_txclean); 3094 3095 num_avail++; 3096 3097 tx_buffer = &adapter->tx_buffer_area[first]; 3098 if (tx_buffer->m_head) { 3099 bus_dmamap_unload(adapter->txtag, 3100 tx_buffer->map); 3101 m_freem(tx_buffer->m_head); 3102 tx_buffer->m_head = NULL; 3103 } 3104 3105 if (first == dd_idx) { 3106 EM_INC_TXDD_IDX(adapter->tx_dd_head); 3107 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 3108 adapter->tx_dd_head = 0; 3109 adapter->tx_dd_tail = 0; 3110 dd_idx = -1; 3111 } else { 3112 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3113 } 3114 } 3115 3116 if (++first == adapter->num_tx_desc) 3117 first = 0; 3118 } 3119 adapter->next_tx_to_clean = first; 3120 adapter->num_tx_desc_avail = num_avail; 3121 3122 if (!EM_IS_OACTIVE(adapter)) { 3123 ifq_clr_oactive(&ifp->if_snd); 3124 3125 /* All clean, turn off the timer */ 3126 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3127 ifp->if_timer = 0; 3128 } 3129 } 3130 3131 /* 3132 * When Link is lost sometimes there is work still in the TX ring 3133 * which will result in a watchdog, rather than allow that do an 3134 * attempted cleanup and then reinit here. Note that this has been 3135 * seens mostly with fiber adapters. 3136 */ 3137 static void 3138 em_tx_purge(struct adapter *adapter) 3139 { 3140 struct ifnet *ifp = &adapter->arpcom.ac_if; 3141 3142 if (!adapter->link_active && ifp->if_timer) { 3143 em_tx_collect(adapter); 3144 if (ifp->if_timer) { 3145 if_printf(ifp, "Link lost, TX pending, reinit\n"); 3146 ifp->if_timer = 0; 3147 em_init(adapter); 3148 } 3149 } 3150 } 3151 3152 static int 3153 em_newbuf(struct adapter *adapter, int i, int init) 3154 { 3155 struct mbuf *m; 3156 bus_dma_segment_t seg; 3157 bus_dmamap_t map; 3158 struct em_buffer *rx_buffer; 3159 int error, nseg; 3160 3161 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 3162 if (m == NULL) { 3163 adapter->mbuf_cluster_failed++; 3164 if (init) { 3165 if_printf(&adapter->arpcom.ac_if, 3166 "Unable to allocate RX mbuf\n"); 3167 } 3168 return (ENOBUFS); 3169 } 3170 m->m_len = m->m_pkthdr.len = MCLBYTES; 3171 3172 if (adapter->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN) 3173 m_adj(m, ETHER_ALIGN); 3174 3175 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3176 adapter->rx_sparemap, m, 3177 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3178 if (error) { 3179 m_freem(m); 3180 if (init) { 3181 if_printf(&adapter->arpcom.ac_if, 3182 "Unable to load RX mbuf\n"); 3183 } 3184 return (error); 3185 } 3186 3187 rx_buffer = &adapter->rx_buffer_area[i]; 3188 if (rx_buffer->m_head != NULL) 3189 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3190 3191 map = rx_buffer->map; 3192 rx_buffer->map = adapter->rx_sparemap; 3193 adapter->rx_sparemap = map; 3194 3195 rx_buffer->m_head = m; 3196 3197 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3198 return (0); 3199 } 3200 3201 static int 3202 em_create_rx_ring(struct adapter *adapter) 3203 { 3204 device_t dev = adapter->dev; 3205 struct em_buffer *rx_buffer; 3206 int i, error; 3207 3208 adapter->rx_buffer_area = 3209 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3210 M_DEVBUF, M_WAITOK | M_ZERO); 3211 3212 /* 3213 * Create DMA tag for rx buffers 3214 */ 3215 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3216 1, 0, /* alignment, bounds */ 3217 BUS_SPACE_MAXADDR, /* lowaddr */ 3218 BUS_SPACE_MAXADDR, /* highaddr */ 3219 NULL, NULL, /* filter, filterarg */ 3220 MCLBYTES, /* maxsize */ 3221 1, /* nsegments */ 3222 MCLBYTES, /* maxsegsize */ 3223 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3224 &adapter->rxtag); 3225 if (error) { 3226 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3227 kfree(adapter->rx_buffer_area, M_DEVBUF); 3228 adapter->rx_buffer_area = NULL; 3229 return error; 3230 } 3231 3232 /* 3233 * Create spare DMA map for rx buffers 3234 */ 3235 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3236 &adapter->rx_sparemap); 3237 if (error) { 3238 device_printf(dev, "Unable to create spare RX DMA map\n"); 3239 bus_dma_tag_destroy(adapter->rxtag); 3240 kfree(adapter->rx_buffer_area, M_DEVBUF); 3241 adapter->rx_buffer_area = NULL; 3242 return error; 3243 } 3244 3245 /* 3246 * Create DMA maps for rx buffers 3247 */ 3248 for (i = 0; i < adapter->num_rx_desc; i++) { 3249 rx_buffer = &adapter->rx_buffer_area[i]; 3250 3251 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3252 &rx_buffer->map); 3253 if (error) { 3254 device_printf(dev, "Unable to create RX DMA map\n"); 3255 em_destroy_rx_ring(adapter, i); 3256 return error; 3257 } 3258 } 3259 return (0); 3260 } 3261 3262 static int 3263 em_init_rx_ring(struct adapter *adapter) 3264 { 3265 int i, error; 3266 3267 /* Reset descriptor ring */ 3268 bzero(adapter->rx_desc_base, 3269 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3270 3271 /* Allocate new ones. */ 3272 for (i = 0; i < adapter->num_rx_desc; i++) { 3273 error = em_newbuf(adapter, i, 1); 3274 if (error) 3275 return (error); 3276 } 3277 3278 /* Setup our descriptor pointers */ 3279 adapter->next_rx_desc_to_check = 0; 3280 3281 return (0); 3282 } 3283 3284 static void 3285 em_init_rx_unit(struct adapter *adapter) 3286 { 3287 struct ifnet *ifp = &adapter->arpcom.ac_if; 3288 uint64_t bus_addr; 3289 uint32_t rctl; 3290 3291 /* 3292 * Make sure receives are disabled while setting 3293 * up the descriptor ring 3294 */ 3295 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3296 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3297 3298 if (adapter->hw.mac.type >= e1000_82540) { 3299 uint32_t itr; 3300 3301 /* 3302 * Set the interrupt throttling rate. Value is calculated 3303 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3304 */ 3305 if (adapter->int_throttle_ceil) 3306 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3307 else 3308 itr = 0; 3309 em_set_itr(adapter, itr); 3310 } 3311 3312 /* Disable accelerated ackknowledge */ 3313 if (adapter->hw.mac.type == e1000_82574) { 3314 E1000_WRITE_REG(&adapter->hw, 3315 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3316 } 3317 3318 /* Receive Checksum Offload for TCP and UDP */ 3319 if (ifp->if_capenable & IFCAP_RXCSUM) { 3320 uint32_t rxcsum; 3321 3322 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3323 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3324 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3325 } 3326 3327 /* 3328 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3329 * long latencies are observed, like Lenovo X60. This 3330 * change eliminates the problem, but since having positive 3331 * values in RDTR is a known source of problems on other 3332 * platforms another solution is being sought. 3333 */ 3334 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3335 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3336 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3337 } 3338 3339 /* 3340 * Setup the Base and Length of the Rx Descriptor Ring 3341 */ 3342 bus_addr = adapter->rxdma.dma_paddr; 3343 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3344 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3345 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3346 (uint32_t)(bus_addr >> 32)); 3347 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3348 (uint32_t)bus_addr); 3349 3350 /* 3351 * Setup the HW Rx Head and Tail Descriptor Pointers 3352 */ 3353 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3354 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3355 3356 /* Set PTHRESH for improved jumbo performance */ 3357 if (((adapter->hw.mac.type == e1000_ich9lan) || 3358 (adapter->hw.mac.type == e1000_pch2lan) || 3359 (adapter->hw.mac.type == e1000_ich10lan)) && 3360 (ifp->if_mtu > ETHERMTU)) { 3361 uint32_t rxdctl; 3362 3363 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3364 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3); 3365 } 3366 3367 if (adapter->hw.mac.type >= e1000_pch2lan) { 3368 if (ifp->if_mtu > ETHERMTU) 3369 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3370 else 3371 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3372 } 3373 3374 /* Setup the Receive Control Register */ 3375 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3376 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3377 E1000_RCTL_RDMTS_HALF | 3378 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3379 3380 /* Make sure VLAN Filters are off */ 3381 rctl &= ~E1000_RCTL_VFE; 3382 3383 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3384 rctl |= E1000_RCTL_SBP; 3385 else 3386 rctl &= ~E1000_RCTL_SBP; 3387 3388 switch (adapter->rx_buffer_len) { 3389 default: 3390 case 2048: 3391 rctl |= E1000_RCTL_SZ_2048; 3392 break; 3393 3394 case 4096: 3395 rctl |= E1000_RCTL_SZ_4096 | 3396 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3397 break; 3398 3399 case 8192: 3400 rctl |= E1000_RCTL_SZ_8192 | 3401 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3402 break; 3403 3404 case 16384: 3405 rctl |= E1000_RCTL_SZ_16384 | 3406 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3407 break; 3408 } 3409 3410 if (ifp->if_mtu > ETHERMTU) 3411 rctl |= E1000_RCTL_LPE; 3412 else 3413 rctl &= ~E1000_RCTL_LPE; 3414 3415 /* Enable Receives */ 3416 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3417 } 3418 3419 static void 3420 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3421 { 3422 struct em_buffer *rx_buffer; 3423 int i; 3424 3425 if (adapter->rx_buffer_area == NULL) 3426 return; 3427 3428 for (i = 0; i < ndesc; i++) { 3429 rx_buffer = &adapter->rx_buffer_area[i]; 3430 3431 KKASSERT(rx_buffer->m_head == NULL); 3432 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3433 } 3434 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3435 bus_dma_tag_destroy(adapter->rxtag); 3436 3437 kfree(adapter->rx_buffer_area, M_DEVBUF); 3438 adapter->rx_buffer_area = NULL; 3439 } 3440 3441 static void 3442 em_rxeof(struct adapter *adapter, int count) 3443 { 3444 struct ifnet *ifp = &adapter->arpcom.ac_if; 3445 uint8_t status, accept_frame = 0, eop = 0; 3446 uint16_t len, desc_len, prev_len_adj; 3447 struct e1000_rx_desc *current_desc; 3448 struct mbuf *mp; 3449 int i; 3450 3451 i = adapter->next_rx_desc_to_check; 3452 current_desc = &adapter->rx_desc_base[i]; 3453 3454 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3455 return; 3456 3457 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3458 struct mbuf *m = NULL; 3459 3460 logif(pkt_receive); 3461 3462 mp = adapter->rx_buffer_area[i].m_head; 3463 3464 /* 3465 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3466 * needs to access the last received byte in the mbuf. 3467 */ 3468 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3469 BUS_DMASYNC_POSTREAD); 3470 3471 accept_frame = 1; 3472 prev_len_adj = 0; 3473 desc_len = le16toh(current_desc->length); 3474 status = current_desc->status; 3475 if (status & E1000_RXD_STAT_EOP) { 3476 count--; 3477 eop = 1; 3478 if (desc_len < ETHER_CRC_LEN) { 3479 len = 0; 3480 prev_len_adj = ETHER_CRC_LEN - desc_len; 3481 } else { 3482 len = desc_len - ETHER_CRC_LEN; 3483 } 3484 } else { 3485 eop = 0; 3486 len = desc_len; 3487 } 3488 3489 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3490 uint8_t last_byte; 3491 uint32_t pkt_len = desc_len; 3492 3493 if (adapter->fmp != NULL) 3494 pkt_len += adapter->fmp->m_pkthdr.len; 3495 3496 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3497 if (TBI_ACCEPT(&adapter->hw, status, 3498 current_desc->errors, pkt_len, last_byte, 3499 adapter->min_frame_size, 3500 adapter->hw.mac.max_frame_size)) { 3501 e1000_tbi_adjust_stats_82543(&adapter->hw, 3502 &adapter->stats, pkt_len, 3503 adapter->hw.mac.addr, 3504 adapter->hw.mac.max_frame_size); 3505 if (len > 0) 3506 len--; 3507 } else { 3508 accept_frame = 0; 3509 } 3510 } 3511 3512 if (accept_frame) { 3513 if (em_newbuf(adapter, i, 0) != 0) { 3514 IFNET_STAT_INC(ifp, iqdrops, 1); 3515 goto discard; 3516 } 3517 3518 /* Assign correct length to the current fragment */ 3519 mp->m_len = len; 3520 3521 if (adapter->fmp == NULL) { 3522 mp->m_pkthdr.len = len; 3523 adapter->fmp = mp; /* Store the first mbuf */ 3524 adapter->lmp = mp; 3525 } else { 3526 /* 3527 * Chain mbuf's together 3528 */ 3529 3530 /* 3531 * Adjust length of previous mbuf in chain if 3532 * we received less than 4 bytes in the last 3533 * descriptor. 3534 */ 3535 if (prev_len_adj > 0) { 3536 adapter->lmp->m_len -= prev_len_adj; 3537 adapter->fmp->m_pkthdr.len -= 3538 prev_len_adj; 3539 } 3540 adapter->lmp->m_next = mp; 3541 adapter->lmp = adapter->lmp->m_next; 3542 adapter->fmp->m_pkthdr.len += len; 3543 } 3544 3545 if (eop) { 3546 adapter->fmp->m_pkthdr.rcvif = ifp; 3547 IFNET_STAT_INC(ifp, ipackets, 1); 3548 3549 if (ifp->if_capenable & IFCAP_RXCSUM) { 3550 em_rxcsum(adapter, current_desc, 3551 adapter->fmp); 3552 } 3553 3554 if (status & E1000_RXD_STAT_VP) { 3555 adapter->fmp->m_pkthdr.ether_vlantag = 3556 (le16toh(current_desc->special) & 3557 E1000_RXD_SPC_VLAN_MASK); 3558 adapter->fmp->m_flags |= M_VLANTAG; 3559 } 3560 m = adapter->fmp; 3561 adapter->fmp = NULL; 3562 adapter->lmp = NULL; 3563 } 3564 } else { 3565 IFNET_STAT_INC(ifp, ierrors, 1); 3566 discard: 3567 #ifdef foo 3568 /* Reuse loaded DMA map and just update mbuf chain */ 3569 mp = adapter->rx_buffer_area[i].m_head; 3570 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3571 mp->m_data = mp->m_ext.ext_buf; 3572 mp->m_next = NULL; 3573 if (adapter->hw.mac.max_frame_size <= 3574 (MCLBYTES - ETHER_ALIGN)) 3575 m_adj(mp, ETHER_ALIGN); 3576 #endif 3577 if (adapter->fmp != NULL) { 3578 m_freem(adapter->fmp); 3579 adapter->fmp = NULL; 3580 adapter->lmp = NULL; 3581 } 3582 m = NULL; 3583 } 3584 3585 /* Zero out the receive descriptors status. */ 3586 current_desc->status = 0; 3587 3588 if (m != NULL) 3589 ifp->if_input(ifp, m, NULL, -1); 3590 3591 /* Advance our pointers to the next descriptor. */ 3592 if (++i == adapter->num_rx_desc) 3593 i = 0; 3594 current_desc = &adapter->rx_desc_base[i]; 3595 } 3596 adapter->next_rx_desc_to_check = i; 3597 3598 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3599 if (--i < 0) 3600 i = adapter->num_rx_desc - 1; 3601 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3602 } 3603 3604 static void 3605 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3606 struct mbuf *mp) 3607 { 3608 /* 82543 or newer only */ 3609 if (adapter->hw.mac.type < e1000_82543 || 3610 /* Ignore Checksum bit is set */ 3611 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3612 return; 3613 3614 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3615 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3616 /* IP Checksum Good */ 3617 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3618 } 3619 3620 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3621 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3622 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3623 CSUM_PSEUDO_HDR | 3624 CSUM_FRAG_NOT_CHECKED; 3625 mp->m_pkthdr.csum_data = htons(0xffff); 3626 } 3627 } 3628 3629 static void 3630 em_enable_intr(struct adapter *adapter) 3631 { 3632 uint32_t ims_mask = IMS_ENABLE_MASK; 3633 3634 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3635 3636 #if 0 3637 /* XXX MSIX */ 3638 if (adapter->hw.mac.type == e1000_82574) { 3639 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3640 ims_mask |= EM_MSIX_MASK; 3641 } 3642 #endif 3643 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3644 } 3645 3646 static void 3647 em_disable_intr(struct adapter *adapter) 3648 { 3649 uint32_t clear = 0xffffffff; 3650 3651 /* 3652 * The first version of 82542 had an errata where when link was forced 3653 * it would stay up even up even if the cable was disconnected. 3654 * Sequence errors were used to detect the disconnect and then the 3655 * driver would unforce the link. This code in the in the ISR. For 3656 * this to work correctly the Sequence error interrupt had to be 3657 * enabled all the time. 3658 */ 3659 if (adapter->hw.mac.type == e1000_82542 && 3660 adapter->hw.revision_id == E1000_REVISION_2) 3661 clear &= ~E1000_ICR_RXSEQ; 3662 else if (adapter->hw.mac.type == e1000_82574) 3663 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3664 3665 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3666 3667 adapter->npoll.ifpc_stcount = 0; 3668 3669 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3670 } 3671 3672 /* 3673 * Bit of a misnomer, what this really means is 3674 * to enable OS management of the system... aka 3675 * to disable special hardware management features 3676 */ 3677 static void 3678 em_get_mgmt(struct adapter *adapter) 3679 { 3680 /* A shared code workaround */ 3681 #define E1000_82542_MANC2H E1000_MANC2H 3682 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3683 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3684 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3685 3686 /* disable hardware interception of ARP */ 3687 manc &= ~(E1000_MANC_ARP_EN); 3688 3689 /* enable receiving management packets to the host */ 3690 if (adapter->hw.mac.type >= e1000_82571) { 3691 manc |= E1000_MANC_EN_MNG2HOST; 3692 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3693 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3694 manc2h |= E1000_MNG2HOST_PORT_623; 3695 manc2h |= E1000_MNG2HOST_PORT_664; 3696 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3697 } 3698 3699 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3700 } 3701 } 3702 3703 /* 3704 * Give control back to hardware management 3705 * controller if there is one. 3706 */ 3707 static void 3708 em_rel_mgmt(struct adapter *adapter) 3709 { 3710 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3711 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3712 3713 /* re-enable hardware interception of ARP */ 3714 manc |= E1000_MANC_ARP_EN; 3715 3716 if (adapter->hw.mac.type >= e1000_82571) 3717 manc &= ~E1000_MANC_EN_MNG2HOST; 3718 3719 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3720 } 3721 } 3722 3723 /* 3724 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3725 * For ASF and Pass Through versions of f/w this means that 3726 * the driver is loaded. For AMT version (only with 82573) 3727 * of the f/w this means that the network i/f is open. 3728 */ 3729 static void 3730 em_get_hw_control(struct adapter *adapter) 3731 { 3732 /* Let firmware know the driver has taken over */ 3733 if (adapter->hw.mac.type == e1000_82573) { 3734 uint32_t swsm; 3735 3736 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3737 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3738 swsm | E1000_SWSM_DRV_LOAD); 3739 } else { 3740 uint32_t ctrl_ext; 3741 3742 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3743 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3744 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3745 } 3746 adapter->flags |= EM_FLAG_HW_CTRL; 3747 } 3748 3749 /* 3750 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3751 * For ASF and Pass Through versions of f/w this means that the 3752 * driver is no longer loaded. For AMT version (only with 82573) 3753 * of the f/w this means that the network i/f is closed. 3754 */ 3755 static void 3756 em_rel_hw_control(struct adapter *adapter) 3757 { 3758 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0) 3759 return; 3760 adapter->flags &= ~EM_FLAG_HW_CTRL; 3761 3762 /* Let firmware taken over control of h/w */ 3763 if (adapter->hw.mac.type == e1000_82573) { 3764 uint32_t swsm; 3765 3766 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3767 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3768 swsm & ~E1000_SWSM_DRV_LOAD); 3769 } else { 3770 uint32_t ctrl_ext; 3771 3772 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3773 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3774 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3775 } 3776 } 3777 3778 static int 3779 em_is_valid_eaddr(const uint8_t *addr) 3780 { 3781 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3782 3783 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3784 return (FALSE); 3785 3786 return (TRUE); 3787 } 3788 3789 /* 3790 * Enable PCI Wake On Lan capability 3791 */ 3792 void 3793 em_enable_wol(device_t dev) 3794 { 3795 uint16_t cap, status; 3796 uint8_t id; 3797 3798 /* First find the capabilities pointer*/ 3799 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3800 3801 /* Read the PM Capabilities */ 3802 id = pci_read_config(dev, cap, 1); 3803 if (id != PCIY_PMG) /* Something wrong */ 3804 return; 3805 3806 /* 3807 * OK, we have the power capabilities, 3808 * so now get the status register 3809 */ 3810 cap += PCIR_POWER_STATUS; 3811 status = pci_read_config(dev, cap, 2); 3812 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3813 pci_write_config(dev, cap, status, 2); 3814 } 3815 3816 3817 /* 3818 * 82544 Coexistence issue workaround. 3819 * There are 2 issues. 3820 * 1. Transmit Hang issue. 3821 * To detect this issue, following equation can be used... 3822 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3823 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3824 * 3825 * 2. DAC issue. 3826 * To detect this issue, following equation can be used... 3827 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3828 * If SUM[3:0] is in between 9 to c, we will have this issue. 3829 * 3830 * WORKAROUND: 3831 * Make sure we do not have ending address 3832 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3833 */ 3834 static uint32_t 3835 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3836 { 3837 uint32_t safe_terminator; 3838 3839 /* 3840 * Since issue is sensitive to length and address. 3841 * Let us first check the address... 3842 */ 3843 if (length <= 4) { 3844 desc_array->descriptor[0].address = address; 3845 desc_array->descriptor[0].length = length; 3846 desc_array->elements = 1; 3847 return (desc_array->elements); 3848 } 3849 3850 safe_terminator = 3851 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3852 3853 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3854 if (safe_terminator == 0 || 3855 (safe_terminator > 4 && safe_terminator < 9) || 3856 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3857 desc_array->descriptor[0].address = address; 3858 desc_array->descriptor[0].length = length; 3859 desc_array->elements = 1; 3860 return (desc_array->elements); 3861 } 3862 3863 desc_array->descriptor[0].address = address; 3864 desc_array->descriptor[0].length = length - 4; 3865 desc_array->descriptor[1].address = address + (length - 4); 3866 desc_array->descriptor[1].length = 4; 3867 desc_array->elements = 2; 3868 return (desc_array->elements); 3869 } 3870 3871 static void 3872 em_update_stats(struct adapter *adapter) 3873 { 3874 struct ifnet *ifp = &adapter->arpcom.ac_if; 3875 3876 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3877 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3878 adapter->stats.symerrs += 3879 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3880 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3881 } 3882 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3883 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3884 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3885 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3886 3887 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3888 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3889 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3890 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3891 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3892 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3893 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3894 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3895 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3896 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3897 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3898 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3899 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3900 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3901 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3902 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3903 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3904 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3905 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3906 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3907 3908 /* For the 64-bit byte counters the low dword must be read first. */ 3909 /* Both registers clear on the read of the high dword */ 3910 3911 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3912 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3913 3914 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3915 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3916 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3917 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3918 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3919 3920 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3921 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3922 3923 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3924 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3925 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3926 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3927 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3928 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3929 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3930 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3931 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3932 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3933 3934 if (adapter->hw.mac.type >= e1000_82543) { 3935 adapter->stats.algnerrc += 3936 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3937 adapter->stats.rxerrc += 3938 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3939 adapter->stats.tncrs += 3940 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3941 adapter->stats.cexterr += 3942 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3943 adapter->stats.tsctc += 3944 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3945 adapter->stats.tsctfc += 3946 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3947 } 3948 3949 IFNET_STAT_SET(ifp, collisions, adapter->stats.colc); 3950 3951 /* Rx Errors */ 3952 IFNET_STAT_SET(ifp, ierrors, 3953 adapter->dropped_pkts + adapter->stats.rxerrc + 3954 adapter->stats.crcerrs + adapter->stats.algnerrc + 3955 adapter->stats.ruc + adapter->stats.roc + 3956 adapter->stats.mpc + adapter->stats.cexterr); 3957 3958 /* Tx Errors */ 3959 IFNET_STAT_SET(ifp, oerrors, 3960 adapter->stats.ecol + adapter->stats.latecol + 3961 adapter->watchdog_events); 3962 } 3963 3964 static void 3965 em_print_debug_info(struct adapter *adapter) 3966 { 3967 device_t dev = adapter->dev; 3968 uint8_t *hw_addr = adapter->hw.hw_addr; 3969 3970 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3971 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3972 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3973 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3974 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3975 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3976 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3977 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3978 adapter->hw.fc.high_water, 3979 adapter->hw.fc.low_water); 3980 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3981 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3982 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3983 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3984 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3985 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3986 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3987 (long long)adapter->tx_fifo_wrk_cnt, 3988 (long long)adapter->tx_fifo_reset_cnt); 3989 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3990 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3991 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3992 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3993 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3994 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3995 device_printf(dev, "Num Tx descriptors avail = %d\n", 3996 adapter->num_tx_desc_avail); 3997 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3998 adapter->no_tx_desc_avail1); 3999 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 4000 adapter->no_tx_desc_avail2); 4001 device_printf(dev, "Std mbuf failed = %ld\n", 4002 adapter->mbuf_alloc_failed); 4003 device_printf(dev, "Std mbuf cluster failed = %ld\n", 4004 adapter->mbuf_cluster_failed); 4005 device_printf(dev, "Driver dropped packets = %ld\n", 4006 adapter->dropped_pkts); 4007 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 4008 adapter->no_tx_dma_setup); 4009 } 4010 4011 static void 4012 em_print_hw_stats(struct adapter *adapter) 4013 { 4014 device_t dev = adapter->dev; 4015 4016 device_printf(dev, "Excessive collisions = %lld\n", 4017 (long long)adapter->stats.ecol); 4018 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 4019 device_printf(dev, "Symbol errors = %lld\n", 4020 (long long)adapter->stats.symerrs); 4021 #endif 4022 device_printf(dev, "Sequence errors = %lld\n", 4023 (long long)adapter->stats.sec); 4024 device_printf(dev, "Defer count = %lld\n", 4025 (long long)adapter->stats.dc); 4026 device_printf(dev, "Missed Packets = %lld\n", 4027 (long long)adapter->stats.mpc); 4028 device_printf(dev, "Receive No Buffers = %lld\n", 4029 (long long)adapter->stats.rnbc); 4030 /* RLEC is inaccurate on some hardware, calculate our own. */ 4031 device_printf(dev, "Receive Length Errors = %lld\n", 4032 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 4033 device_printf(dev, "Receive errors = %lld\n", 4034 (long long)adapter->stats.rxerrc); 4035 device_printf(dev, "Crc errors = %lld\n", 4036 (long long)adapter->stats.crcerrs); 4037 device_printf(dev, "Alignment errors = %lld\n", 4038 (long long)adapter->stats.algnerrc); 4039 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 4040 (long long)adapter->stats.cexterr); 4041 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 4042 device_printf(dev, "watchdog timeouts = %ld\n", 4043 adapter->watchdog_events); 4044 device_printf(dev, "XON Rcvd = %lld\n", 4045 (long long)adapter->stats.xonrxc); 4046 device_printf(dev, "XON Xmtd = %lld\n", 4047 (long long)adapter->stats.xontxc); 4048 device_printf(dev, "XOFF Rcvd = %lld\n", 4049 (long long)adapter->stats.xoffrxc); 4050 device_printf(dev, "XOFF Xmtd = %lld\n", 4051 (long long)adapter->stats.xofftxc); 4052 device_printf(dev, "Good Packets Rcvd = %lld\n", 4053 (long long)adapter->stats.gprc); 4054 device_printf(dev, "Good Packets Xmtd = %lld\n", 4055 (long long)adapter->stats.gptc); 4056 } 4057 4058 static void 4059 em_print_nvm_info(struct adapter *adapter) 4060 { 4061 uint16_t eeprom_data; 4062 int i, j, row = 0; 4063 4064 /* Its a bit crude, but it gets the job done */ 4065 kprintf("\nInterface EEPROM Dump:\n"); 4066 kprintf("Offset\n0x0000 "); 4067 for (i = 0, j = 0; i < 32; i++, j++) { 4068 if (j == 8) { /* Make the offset block */ 4069 j = 0; ++row; 4070 kprintf("\n0x00%x0 ",row); 4071 } 4072 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4073 kprintf("%04x ", eeprom_data); 4074 } 4075 kprintf("\n"); 4076 } 4077 4078 static int 4079 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4080 { 4081 struct adapter *adapter; 4082 struct ifnet *ifp; 4083 int error, result; 4084 4085 result = -1; 4086 error = sysctl_handle_int(oidp, &result, 0, req); 4087 if (error || !req->newptr) 4088 return (error); 4089 4090 adapter = (struct adapter *)arg1; 4091 ifp = &adapter->arpcom.ac_if; 4092 4093 lwkt_serialize_enter(ifp->if_serializer); 4094 4095 if (result == 1) 4096 em_print_debug_info(adapter); 4097 4098 /* 4099 * This value will cause a hex dump of the 4100 * first 32 16-bit words of the EEPROM to 4101 * the screen. 4102 */ 4103 if (result == 2) 4104 em_print_nvm_info(adapter); 4105 4106 lwkt_serialize_exit(ifp->if_serializer); 4107 4108 return (error); 4109 } 4110 4111 static int 4112 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4113 { 4114 int error, result; 4115 4116 result = -1; 4117 error = sysctl_handle_int(oidp, &result, 0, req); 4118 if (error || !req->newptr) 4119 return (error); 4120 4121 if (result == 1) { 4122 struct adapter *adapter = (struct adapter *)arg1; 4123 struct ifnet *ifp = &adapter->arpcom.ac_if; 4124 4125 lwkt_serialize_enter(ifp->if_serializer); 4126 em_print_hw_stats(adapter); 4127 lwkt_serialize_exit(ifp->if_serializer); 4128 } 4129 return (error); 4130 } 4131 4132 static void 4133 em_add_sysctl(struct adapter *adapter) 4134 { 4135 struct sysctl_ctx_list *ctx; 4136 struct sysctl_oid *tree; 4137 4138 ctx = device_get_sysctl_ctx(adapter->dev); 4139 tree = device_get_sysctl_tree(adapter->dev); 4140 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4141 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4142 em_sysctl_debug_info, "I", "Debug Information"); 4143 4144 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4145 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4146 em_sysctl_stats, "I", "Statistics"); 4147 4148 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4149 OID_AUTO, "rxd", CTLFLAG_RD, 4150 &adapter->num_rx_desc, 0, NULL); 4151 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4152 OID_AUTO, "txd", CTLFLAG_RD, 4153 &adapter->num_tx_desc, 0, NULL); 4154 4155 if (adapter->hw.mac.type >= e1000_82540) { 4156 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4157 OID_AUTO, "int_throttle_ceil", 4158 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4159 em_sysctl_int_throttle, "I", 4160 "interrupt throttling rate"); 4161 } 4162 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4163 OID_AUTO, "int_tx_nsegs", 4164 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4165 em_sysctl_int_tx_nsegs, "I", 4166 "# segments per TX interrupt"); 4167 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4168 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW, 4169 &adapter->tx_wreg_nsegs, 0, 4170 "# segments before write to hardware register"); 4171 } 4172 4173 static int 4174 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4175 { 4176 struct adapter *adapter = (void *)arg1; 4177 struct ifnet *ifp = &adapter->arpcom.ac_if; 4178 int error, throttle; 4179 4180 throttle = adapter->int_throttle_ceil; 4181 error = sysctl_handle_int(oidp, &throttle, 0, req); 4182 if (error || req->newptr == NULL) 4183 return error; 4184 if (throttle < 0 || throttle > 1000000000 / 256) 4185 return EINVAL; 4186 4187 if (throttle) { 4188 /* 4189 * Set the interrupt throttling rate in 256ns increments, 4190 * recalculate sysctl value assignment to get exact frequency. 4191 */ 4192 throttle = 1000000000 / 256 / throttle; 4193 4194 /* Upper 16bits of ITR is reserved and should be zero */ 4195 if (throttle & 0xffff0000) 4196 return EINVAL; 4197 } 4198 4199 lwkt_serialize_enter(ifp->if_serializer); 4200 4201 if (throttle) 4202 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4203 else 4204 adapter->int_throttle_ceil = 0; 4205 4206 if (ifp->if_flags & IFF_RUNNING) 4207 em_set_itr(adapter, throttle); 4208 4209 lwkt_serialize_exit(ifp->if_serializer); 4210 4211 if (bootverbose) { 4212 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4213 adapter->int_throttle_ceil); 4214 } 4215 return 0; 4216 } 4217 4218 static int 4219 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4220 { 4221 struct adapter *adapter = (void *)arg1; 4222 struct ifnet *ifp = &adapter->arpcom.ac_if; 4223 int error, segs; 4224 4225 segs = adapter->tx_int_nsegs; 4226 error = sysctl_handle_int(oidp, &segs, 0, req); 4227 if (error || req->newptr == NULL) 4228 return error; 4229 if (segs <= 0) 4230 return EINVAL; 4231 4232 lwkt_serialize_enter(ifp->if_serializer); 4233 4234 /* 4235 * Don't allow int_tx_nsegs to become: 4236 * o Less the oact_tx_desc 4237 * o Too large that no TX desc will cause TX interrupt to 4238 * be generated (OACTIVE will never recover) 4239 * o Too small that will cause tx_dd[] overflow 4240 */ 4241 if (segs < adapter->oact_tx_desc || 4242 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4243 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4244 error = EINVAL; 4245 } else { 4246 error = 0; 4247 adapter->tx_int_nsegs = segs; 4248 } 4249 4250 lwkt_serialize_exit(ifp->if_serializer); 4251 4252 return error; 4253 } 4254 4255 static void 4256 em_set_itr(struct adapter *adapter, uint32_t itr) 4257 { 4258 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4259 if (adapter->hw.mac.type == e1000_82574) { 4260 int i; 4261 4262 /* 4263 * When using MSIX interrupts we need to 4264 * throttle using the EITR register 4265 */ 4266 for (i = 0; i < 4; ++i) { 4267 E1000_WRITE_REG(&adapter->hw, 4268 E1000_EITR_82574(i), itr); 4269 } 4270 } 4271 } 4272 4273 static void 4274 em_disable_aspm(struct adapter *adapter) 4275 { 4276 uint16_t link_cap, link_ctrl, disable; 4277 uint8_t pcie_ptr, reg; 4278 device_t dev = adapter->dev; 4279 4280 switch (adapter->hw.mac.type) { 4281 case e1000_82571: 4282 case e1000_82572: 4283 case e1000_82573: 4284 /* 4285 * 82573 specification update 4286 * errata #8 disable L0s 4287 * errata #41 disable L1 4288 * 4289 * 82571/82572 specification update 4290 # errata #13 disable L1 4291 * errata #68 disable L0s 4292 */ 4293 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4294 break; 4295 4296 case e1000_82574: 4297 case e1000_82583: 4298 /* 4299 * 82574 specification update errata #20 4300 * 82583 specification update errata #9 4301 * 4302 * There is no need to disable L1 4303 */ 4304 disable = PCIEM_LNKCTL_ASPM_L0S; 4305 break; 4306 4307 default: 4308 return; 4309 } 4310 4311 pcie_ptr = pci_get_pciecap_ptr(dev); 4312 if (pcie_ptr == 0) 4313 return; 4314 4315 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4316 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4317 return; 4318 4319 if (bootverbose) { 4320 if_printf(&adapter->arpcom.ac_if, 4321 "disable ASPM %#02x\n", disable); 4322 } 4323 4324 reg = pcie_ptr + PCIER_LINKCTRL; 4325 link_ctrl = pci_read_config(dev, reg, 2); 4326 link_ctrl &= ~disable; 4327 pci_write_config(dev, reg, link_ctrl, 2); 4328 } 4329 4330 static int 4331 em_tso_pullup(struct adapter *adapter, struct mbuf **mp) 4332 { 4333 int iphlen, hoff, thoff, ex = 0; 4334 struct mbuf *m; 4335 struct ip *ip; 4336 4337 m = *mp; 4338 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4339 4340 iphlen = m->m_pkthdr.csum_iphlen; 4341 thoff = m->m_pkthdr.csum_thlen; 4342 hoff = m->m_pkthdr.csum_lhlen; 4343 4344 KASSERT(iphlen > 0, ("invalid ip hlen")); 4345 KASSERT(thoff > 0, ("invalid tcp hlen")); 4346 KASSERT(hoff > 0, ("invalid ether hlen")); 4347 4348 if (adapter->flags & EM_FLAG_TSO_PULLEX) 4349 ex = 4; 4350 4351 if (m->m_len < hoff + iphlen + thoff + ex) { 4352 m = m_pullup(m, hoff + iphlen + thoff + ex); 4353 if (m == NULL) { 4354 *mp = NULL; 4355 return ENOBUFS; 4356 } 4357 *mp = m; 4358 } 4359 ip = mtodoff(m, struct ip *, hoff); 4360 ip->ip_len = 0; 4361 4362 return 0; 4363 } 4364 4365 static int 4366 em_tso_setup(struct adapter *adapter, struct mbuf *mp, 4367 uint32_t *txd_upper, uint32_t *txd_lower) 4368 { 4369 struct e1000_context_desc *TXD; 4370 int hoff, iphlen, thoff, hlen; 4371 int mss, pktlen, curr_txd; 4372 4373 iphlen = mp->m_pkthdr.csum_iphlen; 4374 thoff = mp->m_pkthdr.csum_thlen; 4375 hoff = mp->m_pkthdr.csum_lhlen; 4376 mss = mp->m_pkthdr.tso_segsz; 4377 pktlen = mp->m_pkthdr.len; 4378 4379 if (adapter->csum_flags == CSUM_TSO && 4380 adapter->csum_iphlen == iphlen && 4381 adapter->csum_lhlen == hoff && 4382 adapter->csum_thlen == thoff && 4383 adapter->csum_mss == mss && 4384 adapter->csum_pktlen == pktlen) { 4385 *txd_upper = adapter->csum_txd_upper; 4386 *txd_lower = adapter->csum_txd_lower; 4387 return 0; 4388 } 4389 hlen = hoff + iphlen + thoff; 4390 4391 /* 4392 * Setup a new TSO context. 4393 */ 4394 4395 curr_txd = adapter->next_avail_tx_desc; 4396 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 4397 4398 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4399 E1000_TXD_DTYP_D | /* Data descr type */ 4400 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4401 4402 /* IP and/or TCP header checksum calculation and insertion. */ 4403 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4404 4405 /* 4406 * Start offset for header checksum calculation. 4407 * End offset for header checksum calculation. 4408 * Offset of place put the checksum. 4409 */ 4410 TXD->lower_setup.ip_fields.ipcss = hoff; 4411 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4412 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4413 4414 /* 4415 * Start offset for payload checksum calculation. 4416 * End offset for payload checksum calculation. 4417 * Offset of place to put the checksum. 4418 */ 4419 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4420 TXD->upper_setup.tcp_fields.tucse = 0; 4421 TXD->upper_setup.tcp_fields.tucso = 4422 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4423 4424 /* 4425 * Payload size per packet w/o any headers. 4426 * Length of all headers up to payload. 4427 */ 4428 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4429 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4430 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4431 E1000_TXD_CMD_DEXT | /* Extended descr */ 4432 E1000_TXD_CMD_TSE | /* TSE context */ 4433 E1000_TXD_CMD_IP | /* Do IP csum */ 4434 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4435 (pktlen - hlen)); /* Total len */ 4436 4437 /* Save the information for this TSO context */ 4438 adapter->csum_flags = CSUM_TSO; 4439 adapter->csum_lhlen = hoff; 4440 adapter->csum_iphlen = iphlen; 4441 adapter->csum_thlen = thoff; 4442 adapter->csum_mss = mss; 4443 adapter->csum_pktlen = pktlen; 4444 adapter->csum_txd_upper = *txd_upper; 4445 adapter->csum_txd_lower = *txd_lower; 4446 4447 if (++curr_txd == adapter->num_tx_desc) 4448 curr_txd = 0; 4449 4450 KKASSERT(adapter->num_tx_desc_avail > 0); 4451 adapter->num_tx_desc_avail--; 4452 4453 adapter->next_avail_tx_desc = curr_txd; 4454 return 1; 4455 } 4456