1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - If the driver uses the same serializer for the interrupt as for the 71 * ifnet, most of the serialization will be done automatically for the 72 * driver. 73 * 74 * - ifmedia entry points will be serialized by the ifmedia code using the 75 * ifnet serializer. 76 * 77 * - if_* entry points except for if_input will be serialized by the IF 78 * and protocol layers. 79 * 80 * - The device driver must be sure to serialize access from timeout code 81 * installed by the device driver. 82 * 83 * - The device driver typically holds the serializer at the time it wishes 84 * to call if_input. 85 * 86 * - We must call lwkt_serialize_handler_enable() prior to enabling the 87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 88 * the hardware interrupt in order to avoid handler execution races from 89 * scheduled interrupt threads. 90 * 91 * NOTE! Since callers into the device driver hold the ifnet serializer, 92 * the device driver may be holding a serializer at the time it calls 93 * if_input even if it is not serializer-aware. 94 */ 95 96 /* 97 * NOTE: 98 * 99 * MSI-X MUST NOT be enabled on 82574: 100 * <<82574 specification update>> errata #15 101 */ 102 103 #include "opt_polling.h" 104 105 #include <sys/param.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/interrupt.h> 109 #include <sys/kernel.h> 110 #include <sys/ktr.h> 111 #include <sys/malloc.h> 112 #include <sys/mbuf.h> 113 #include <sys/proc.h> 114 #include <sys/rman.h> 115 #include <sys/serialize.h> 116 #include <sys/socket.h> 117 #include <sys/sockio.h> 118 #include <sys/sysctl.h> 119 #include <sys/systm.h> 120 121 #include <net/bpf.h> 122 #include <net/ethernet.h> 123 #include <net/if.h> 124 #include <net/if_arp.h> 125 #include <net/if_dl.h> 126 #include <net/if_media.h> 127 #include <net/ifq_var.h> 128 #include <net/vlan/if_vlan_var.h> 129 #include <net/vlan/if_vlan_ether.h> 130 131 #include <netinet/in_systm.h> 132 #include <netinet/in.h> 133 #include <netinet/ip.h> 134 #include <netinet/tcp.h> 135 #include <netinet/udp.h> 136 137 #include <bus/pci/pcivar.h> 138 #include <bus/pci/pcireg.h> 139 140 #include <dev/netif/ig_hal/e1000_api.h> 141 #include <dev/netif/ig_hal/e1000_82571.h> 142 #include <dev/netif/em/if_em.h> 143 144 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 145 #define EM_VER " 7.2.4" 146 147 #define _EM_DEVICE(id, ret) \ 148 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 149 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 150 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 151 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 152 153 static const struct em_vendor_info em_vendor_info_array[] = { 154 EM_DEVICE(82540EM), 155 EM_DEVICE(82540EM_LOM), 156 EM_DEVICE(82540EP), 157 EM_DEVICE(82540EP_LOM), 158 EM_DEVICE(82540EP_LP), 159 160 EM_DEVICE(82541EI), 161 EM_DEVICE(82541ER), 162 EM_DEVICE(82541ER_LOM), 163 EM_DEVICE(82541EI_MOBILE), 164 EM_DEVICE(82541GI), 165 EM_DEVICE(82541GI_LF), 166 EM_DEVICE(82541GI_MOBILE), 167 168 EM_DEVICE(82542), 169 170 EM_DEVICE(82543GC_FIBER), 171 EM_DEVICE(82543GC_COPPER), 172 173 EM_DEVICE(82544EI_COPPER), 174 EM_DEVICE(82544EI_FIBER), 175 EM_DEVICE(82544GC_COPPER), 176 EM_DEVICE(82544GC_LOM), 177 178 EM_DEVICE(82545EM_COPPER), 179 EM_DEVICE(82545EM_FIBER), 180 EM_DEVICE(82545GM_COPPER), 181 EM_DEVICE(82545GM_FIBER), 182 EM_DEVICE(82545GM_SERDES), 183 184 EM_DEVICE(82546EB_COPPER), 185 EM_DEVICE(82546EB_FIBER), 186 EM_DEVICE(82546EB_QUAD_COPPER), 187 EM_DEVICE(82546GB_COPPER), 188 EM_DEVICE(82546GB_FIBER), 189 EM_DEVICE(82546GB_SERDES), 190 EM_DEVICE(82546GB_PCIE), 191 EM_DEVICE(82546GB_QUAD_COPPER), 192 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 193 194 EM_DEVICE(82547EI), 195 EM_DEVICE(82547EI_MOBILE), 196 EM_DEVICE(82547GI), 197 198 EM_EMX_DEVICE(82571EB_COPPER), 199 EM_EMX_DEVICE(82571EB_FIBER), 200 EM_EMX_DEVICE(82571EB_SERDES), 201 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 202 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 203 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 204 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 205 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 206 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 207 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 208 209 EM_EMX_DEVICE(82572EI_COPPER), 210 EM_EMX_DEVICE(82572EI_FIBER), 211 EM_EMX_DEVICE(82572EI_SERDES), 212 EM_EMX_DEVICE(82572EI), 213 214 EM_EMX_DEVICE(82573E), 215 EM_EMX_DEVICE(82573E_IAMT), 216 EM_EMX_DEVICE(82573L), 217 218 EM_DEVICE(82583V), 219 220 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 221 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 222 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 223 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 224 225 EM_DEVICE(ICH8_IGP_M_AMT), 226 EM_DEVICE(ICH8_IGP_AMT), 227 EM_DEVICE(ICH8_IGP_C), 228 EM_DEVICE(ICH8_IFE), 229 EM_DEVICE(ICH8_IFE_GT), 230 EM_DEVICE(ICH8_IFE_G), 231 EM_DEVICE(ICH8_IGP_M), 232 EM_DEVICE(ICH8_82567V_3), 233 234 EM_DEVICE(ICH9_IGP_M_AMT), 235 EM_DEVICE(ICH9_IGP_AMT), 236 EM_DEVICE(ICH9_IGP_C), 237 EM_DEVICE(ICH9_IGP_M), 238 EM_DEVICE(ICH9_IGP_M_V), 239 EM_DEVICE(ICH9_IFE), 240 EM_DEVICE(ICH9_IFE_GT), 241 EM_DEVICE(ICH9_IFE_G), 242 EM_DEVICE(ICH9_BM), 243 244 EM_EMX_DEVICE(82574L), 245 EM_EMX_DEVICE(82574LA), 246 247 EM_DEVICE(ICH10_R_BM_LM), 248 EM_DEVICE(ICH10_R_BM_LF), 249 EM_DEVICE(ICH10_R_BM_V), 250 EM_DEVICE(ICH10_D_BM_LM), 251 EM_DEVICE(ICH10_D_BM_LF), 252 EM_DEVICE(ICH10_D_BM_V), 253 254 EM_DEVICE(PCH_M_HV_LM), 255 EM_DEVICE(PCH_M_HV_LC), 256 EM_DEVICE(PCH_D_HV_DM), 257 EM_DEVICE(PCH_D_HV_DC), 258 259 EM_DEVICE(PCH2_LV_LM), 260 EM_DEVICE(PCH2_LV_V), 261 262 /* required last entry */ 263 EM_DEVICE_NULL 264 }; 265 266 static int em_probe(device_t); 267 static int em_attach(device_t); 268 static int em_detach(device_t); 269 static int em_shutdown(device_t); 270 static int em_suspend(device_t); 271 static int em_resume(device_t); 272 273 static void em_init(void *); 274 static void em_stop(struct adapter *); 275 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 276 static void em_start(struct ifnet *); 277 #ifdef DEVICE_POLLING 278 static void em_poll(struct ifnet *, enum poll_cmd, int); 279 #endif 280 static void em_watchdog(struct ifnet *); 281 static void em_media_status(struct ifnet *, struct ifmediareq *); 282 static int em_media_change(struct ifnet *); 283 static void em_timer(void *); 284 285 static void em_intr(void *); 286 static void em_rxeof(struct adapter *, int); 287 static void em_txeof(struct adapter *); 288 static void em_tx_collect(struct adapter *); 289 static void em_tx_purge(struct adapter *); 290 static void em_enable_intr(struct adapter *); 291 static void em_disable_intr(struct adapter *); 292 293 static int em_dma_malloc(struct adapter *, bus_size_t, 294 struct em_dma_alloc *); 295 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 296 static void em_init_tx_ring(struct adapter *); 297 static int em_init_rx_ring(struct adapter *); 298 static int em_create_tx_ring(struct adapter *); 299 static int em_create_rx_ring(struct adapter *); 300 static void em_destroy_tx_ring(struct adapter *, int); 301 static void em_destroy_rx_ring(struct adapter *, int); 302 static int em_newbuf(struct adapter *, int, int); 303 static int em_encap(struct adapter *, struct mbuf **); 304 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 305 struct mbuf *); 306 static int em_txcsum_pullup(struct adapter *, struct mbuf **); 307 static int em_txcsum(struct adapter *, struct mbuf *, 308 uint32_t *, uint32_t *); 309 310 static int em_get_hw_info(struct adapter *); 311 static int em_is_valid_eaddr(const uint8_t *); 312 static int em_alloc_pci_res(struct adapter *); 313 static void em_free_pci_res(struct adapter *); 314 static int em_reset(struct adapter *); 315 static void em_setup_ifp(struct adapter *); 316 static void em_init_tx_unit(struct adapter *); 317 static void em_init_rx_unit(struct adapter *); 318 static void em_update_stats(struct adapter *); 319 static void em_set_promisc(struct adapter *); 320 static void em_disable_promisc(struct adapter *); 321 static void em_set_multi(struct adapter *); 322 static void em_update_link_status(struct adapter *); 323 static void em_smartspeed(struct adapter *); 324 static void em_set_itr(struct adapter *, uint32_t); 325 static void em_disable_aspm(struct adapter *); 326 327 /* Hardware workarounds */ 328 static int em_82547_fifo_workaround(struct adapter *, int); 329 static void em_82547_update_fifo_head(struct adapter *, int); 330 static int em_82547_tx_fifo_reset(struct adapter *); 331 static void em_82547_move_tail(void *); 332 static void em_82547_move_tail_serialized(struct adapter *); 333 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 334 335 static void em_print_debug_info(struct adapter *); 336 static void em_print_nvm_info(struct adapter *); 337 static void em_print_hw_stats(struct adapter *); 338 339 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 340 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 341 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 342 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 343 static void em_add_sysctl(struct adapter *adapter); 344 345 /* Management and WOL Support */ 346 static void em_get_mgmt(struct adapter *); 347 static void em_rel_mgmt(struct adapter *); 348 static void em_get_hw_control(struct adapter *); 349 static void em_rel_hw_control(struct adapter *); 350 static void em_enable_wol(device_t); 351 352 static device_method_t em_methods[] = { 353 /* Device interface */ 354 DEVMETHOD(device_probe, em_probe), 355 DEVMETHOD(device_attach, em_attach), 356 DEVMETHOD(device_detach, em_detach), 357 DEVMETHOD(device_shutdown, em_shutdown), 358 DEVMETHOD(device_suspend, em_suspend), 359 DEVMETHOD(device_resume, em_resume), 360 { 0, 0 } 361 }; 362 363 static driver_t em_driver = { 364 "em", 365 em_methods, 366 sizeof(struct adapter), 367 }; 368 369 static devclass_t em_devclass; 370 371 DECLARE_DUMMY_MODULE(if_em); 372 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 373 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 374 375 /* 376 * Tunables 377 */ 378 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 379 static int em_rxd = EM_DEFAULT_RXD; 380 static int em_txd = EM_DEFAULT_TXD; 381 static int em_smart_pwr_down = 0; 382 383 /* Controls whether promiscuous also shows bad packets */ 384 static int em_debug_sbp = FALSE; 385 386 static int em_82573_workaround = 1; 387 static int em_msi_enable = 1; 388 389 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 390 TUNABLE_INT("hw.em.rxd", &em_rxd); 391 TUNABLE_INT("hw.em.txd", &em_txd); 392 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 393 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 394 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 395 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 396 397 /* Global used in WOL setup with multiport cards */ 398 static int em_global_quad_port_a = 0; 399 400 /* Set this to one to display debug statistics */ 401 static int em_display_debug_stats = 0; 402 403 #if !defined(KTR_IF_EM) 404 #define KTR_IF_EM KTR_ALL 405 #endif 406 KTR_INFO_MASTER(if_em); 407 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 408 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 409 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 410 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 411 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 412 #define logif(name) KTR_LOG(if_em_ ## name) 413 414 static int 415 em_probe(device_t dev) 416 { 417 const struct em_vendor_info *ent; 418 uint16_t vid, did; 419 420 vid = pci_get_vendor(dev); 421 did = pci_get_device(dev); 422 423 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 424 if (vid == ent->vendor_id && did == ent->device_id) { 425 device_set_desc(dev, ent->desc); 426 device_set_async_attach(dev, TRUE); 427 return (ent->ret); 428 } 429 } 430 return (ENXIO); 431 } 432 433 static int 434 em_attach(device_t dev) 435 { 436 struct adapter *adapter = device_get_softc(dev); 437 struct ifnet *ifp = &adapter->arpcom.ac_if; 438 int tsize, rsize; 439 int error = 0; 440 uint16_t eeprom_data, device_id, apme_mask; 441 442 adapter->dev = adapter->osdep.dev = dev; 443 444 callout_init_mp(&adapter->timer); 445 callout_init_mp(&adapter->tx_fifo_timer); 446 447 /* Determine hardware and mac info */ 448 error = em_get_hw_info(adapter); 449 if (error) { 450 device_printf(dev, "Identify hardware failed\n"); 451 goto fail; 452 } 453 454 /* Setup PCI resources */ 455 error = em_alloc_pci_res(adapter); 456 if (error) { 457 device_printf(dev, "Allocation of PCI resources failed\n"); 458 goto fail; 459 } 460 461 /* 462 * For ICH8 and family we need to map the flash memory, 463 * and this must happen after the MAC is identified. 464 */ 465 if (adapter->hw.mac.type == e1000_ich8lan || 466 adapter->hw.mac.type == e1000_ich9lan || 467 adapter->hw.mac.type == e1000_ich10lan || 468 adapter->hw.mac.type == e1000_pchlan || 469 adapter->hw.mac.type == e1000_pch2lan) { 470 adapter->flash_rid = EM_BAR_FLASH; 471 472 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 473 &adapter->flash_rid, RF_ACTIVE); 474 if (adapter->flash == NULL) { 475 device_printf(dev, "Mapping of Flash failed\n"); 476 error = ENXIO; 477 goto fail; 478 } 479 adapter->osdep.flash_bus_space_tag = 480 rman_get_bustag(adapter->flash); 481 adapter->osdep.flash_bus_space_handle = 482 rman_get_bushandle(adapter->flash); 483 484 /* 485 * This is used in the shared code 486 * XXX this goof is actually not used. 487 */ 488 adapter->hw.flash_address = (uint8_t *)adapter->flash; 489 } 490 491 /* Do Shared Code initialization */ 492 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 493 device_printf(dev, "Setup of Shared code failed\n"); 494 error = ENXIO; 495 goto fail; 496 } 497 498 e1000_get_bus_info(&adapter->hw); 499 500 /* 501 * Validate number of transmit and receive descriptors. It 502 * must not exceed hardware maximum, and must be multiple 503 * of E1000_DBA_ALIGN. 504 */ 505 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 506 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 507 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 508 em_txd < EM_MIN_TXD) { 509 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 510 EM_DEFAULT_TXD, em_txd); 511 adapter->num_tx_desc = EM_DEFAULT_TXD; 512 } else { 513 adapter->num_tx_desc = em_txd; 514 } 515 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 516 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 517 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 518 em_rxd < EM_MIN_RXD) { 519 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 520 EM_DEFAULT_RXD, em_rxd); 521 adapter->num_rx_desc = EM_DEFAULT_RXD; 522 } else { 523 adapter->num_rx_desc = em_rxd; 524 } 525 526 adapter->hw.mac.autoneg = DO_AUTO_NEG; 527 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 528 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 529 adapter->rx_buffer_len = MCLBYTES; 530 531 /* 532 * Interrupt throttle rate 533 */ 534 if (em_int_throttle_ceil == 0) { 535 adapter->int_throttle_ceil = 0; 536 } else { 537 int throttle = em_int_throttle_ceil; 538 539 if (throttle < 0) 540 throttle = EM_DEFAULT_ITR; 541 542 /* Recalculate the tunable value to get the exact frequency. */ 543 throttle = 1000000000 / 256 / throttle; 544 545 /* Upper 16bits of ITR is reserved and should be zero */ 546 if (throttle & 0xffff0000) 547 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 548 549 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 550 } 551 552 e1000_init_script_state_82541(&adapter->hw, TRUE); 553 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 554 555 /* Copper options */ 556 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 557 adapter->hw.phy.mdix = AUTO_ALL_MODES; 558 adapter->hw.phy.disable_polarity_correction = FALSE; 559 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 560 } 561 562 /* Set the frame limits assuming standard ethernet sized frames. */ 563 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 564 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 565 566 /* This controls when hardware reports transmit completion status. */ 567 adapter->hw.mac.report_tx_early = 1; 568 569 /* 570 * Create top level busdma tag 571 */ 572 error = bus_dma_tag_create(NULL, 1, 0, 573 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 574 NULL, NULL, 575 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 576 0, &adapter->parent_dtag); 577 if (error) { 578 device_printf(dev, "could not create top level DMA tag\n"); 579 goto fail; 580 } 581 582 /* 583 * Allocate Transmit Descriptor ring 584 */ 585 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 586 EM_DBA_ALIGN); 587 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 588 if (error) { 589 device_printf(dev, "Unable to allocate tx_desc memory\n"); 590 goto fail; 591 } 592 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 593 594 /* 595 * Allocate Receive Descriptor ring 596 */ 597 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 598 EM_DBA_ALIGN); 599 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 600 if (error) { 601 device_printf(dev, "Unable to allocate rx_desc memory\n"); 602 goto fail; 603 } 604 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 605 606 /* Allocate multicast array memory. */ 607 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 608 M_DEVBUF, M_WAITOK); 609 610 /* Indicate SOL/IDER usage */ 611 if (e1000_check_reset_block(&adapter->hw)) { 612 device_printf(dev, 613 "PHY reset is blocked due to SOL/IDER session.\n"); 614 } 615 616 /* 617 * Start from a known state, this is important in reading the 618 * nvm and mac from that. 619 */ 620 e1000_reset_hw(&adapter->hw); 621 622 /* Make sure we have a good EEPROM before we read from it */ 623 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 624 /* 625 * Some PCI-E parts fail the first check due to 626 * the link being in sleep state, call it again, 627 * if it fails a second time its a real issue. 628 */ 629 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 630 device_printf(dev, 631 "The EEPROM Checksum Is Not Valid\n"); 632 error = EIO; 633 goto fail; 634 } 635 } 636 637 /* Copy the permanent MAC address out of the EEPROM */ 638 if (e1000_read_mac_addr(&adapter->hw) < 0) { 639 device_printf(dev, "EEPROM read error while reading MAC" 640 " address\n"); 641 error = EIO; 642 goto fail; 643 } 644 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 645 device_printf(dev, "Invalid MAC address\n"); 646 error = EIO; 647 goto fail; 648 } 649 650 /* Allocate transmit descriptors and buffers */ 651 error = em_create_tx_ring(adapter); 652 if (error) { 653 device_printf(dev, "Could not setup transmit structures\n"); 654 goto fail; 655 } 656 657 /* Allocate receive descriptors and buffers */ 658 error = em_create_rx_ring(adapter); 659 if (error) { 660 device_printf(dev, "Could not setup receive structures\n"); 661 goto fail; 662 } 663 664 /* Manually turn off all interrupts */ 665 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 666 667 /* Determine if we have to control management hardware */ 668 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 669 670 /* 671 * Setup Wake-on-Lan 672 */ 673 apme_mask = EM_EEPROM_APME; 674 eeprom_data = 0; 675 switch (adapter->hw.mac.type) { 676 case e1000_82542: 677 case e1000_82543: 678 break; 679 680 case e1000_82573: 681 case e1000_82583: 682 adapter->has_amt = 1; 683 /* FALL THROUGH */ 684 685 case e1000_82546: 686 case e1000_82546_rev_3: 687 case e1000_82571: 688 case e1000_82572: 689 case e1000_80003es2lan: 690 if (adapter->hw.bus.func == 1) { 691 e1000_read_nvm(&adapter->hw, 692 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 693 } else { 694 e1000_read_nvm(&adapter->hw, 695 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 696 } 697 break; 698 699 case e1000_ich8lan: 700 case e1000_ich9lan: 701 case e1000_ich10lan: 702 case e1000_pchlan: 703 case e1000_pch2lan: 704 apme_mask = E1000_WUC_APME; 705 adapter->has_amt = TRUE; 706 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 707 break; 708 709 default: 710 e1000_read_nvm(&adapter->hw, 711 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 712 break; 713 } 714 if (eeprom_data & apme_mask) 715 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 716 717 /* 718 * We have the eeprom settings, now apply the special cases 719 * where the eeprom may be wrong or the board won't support 720 * wake on lan on a particular port 721 */ 722 device_id = pci_get_device(dev); 723 switch (device_id) { 724 case E1000_DEV_ID_82546GB_PCIE: 725 adapter->wol = 0; 726 break; 727 728 case E1000_DEV_ID_82546EB_FIBER: 729 case E1000_DEV_ID_82546GB_FIBER: 730 case E1000_DEV_ID_82571EB_FIBER: 731 /* 732 * Wake events only supported on port A for dual fiber 733 * regardless of eeprom setting 734 */ 735 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 736 E1000_STATUS_FUNC_1) 737 adapter->wol = 0; 738 break; 739 740 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 741 case E1000_DEV_ID_82571EB_QUAD_COPPER: 742 case E1000_DEV_ID_82571EB_QUAD_FIBER: 743 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 744 /* if quad port adapter, disable WoL on all but port A */ 745 if (em_global_quad_port_a != 0) 746 adapter->wol = 0; 747 /* Reset for multiple quad port adapters */ 748 if (++em_global_quad_port_a == 4) 749 em_global_quad_port_a = 0; 750 break; 751 } 752 753 /* XXX disable wol */ 754 adapter->wol = 0; 755 756 /* Setup OS specific network interface */ 757 em_setup_ifp(adapter); 758 759 /* Add sysctl tree, must after em_setup_ifp() */ 760 em_add_sysctl(adapter); 761 762 /* Reset the hardware */ 763 error = em_reset(adapter); 764 if (error) { 765 device_printf(dev, "Unable to reset the hardware\n"); 766 goto fail; 767 } 768 769 /* Initialize statistics */ 770 em_update_stats(adapter); 771 772 adapter->hw.mac.get_link_status = 1; 773 em_update_link_status(adapter); 774 775 /* Do we need workaround for 82544 PCI-X adapter? */ 776 if (adapter->hw.bus.type == e1000_bus_type_pcix && 777 adapter->hw.mac.type == e1000_82544) 778 adapter->pcix_82544 = TRUE; 779 else 780 adapter->pcix_82544 = FALSE; 781 782 if (adapter->pcix_82544) { 783 /* 784 * 82544 on PCI-X may split one TX segment 785 * into two TX descs, so we double its number 786 * of spare TX desc here. 787 */ 788 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 789 } else { 790 adapter->spare_tx_desc = EM_TX_SPARE; 791 } 792 793 /* 794 * Keep following relationship between spare_tx_desc, oact_tx_desc 795 * and tx_int_nsegs: 796 * (spare_tx_desc + EM_TX_RESERVED) <= 797 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 798 */ 799 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 800 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 801 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 802 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 803 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 804 805 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 806 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 807 adapter->tx_int_nsegs = adapter->oact_tx_desc; 808 809 /* Non-AMT based hardware can now take control from firmware */ 810 if (adapter->has_manage && !adapter->has_amt && 811 adapter->hw.mac.type >= e1000_82571) 812 em_get_hw_control(adapter); 813 814 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 815 em_intr, adapter, &adapter->intr_tag, 816 ifp->if_serializer); 817 if (error) { 818 device_printf(dev, "Failed to register interrupt handler"); 819 ether_ifdetach(&adapter->arpcom.ac_if); 820 goto fail; 821 } 822 823 ifp->if_cpuid = rman_get_cpuid(adapter->intr_res); 824 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 825 return (0); 826 fail: 827 em_detach(dev); 828 return (error); 829 } 830 831 static int 832 em_detach(device_t dev) 833 { 834 struct adapter *adapter = device_get_softc(dev); 835 836 if (device_is_attached(dev)) { 837 struct ifnet *ifp = &adapter->arpcom.ac_if; 838 839 lwkt_serialize_enter(ifp->if_serializer); 840 841 em_stop(adapter); 842 843 e1000_phy_hw_reset(&adapter->hw); 844 845 em_rel_mgmt(adapter); 846 em_rel_hw_control(adapter); 847 848 if (adapter->wol) { 849 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 850 E1000_WUC_PME_EN); 851 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 852 em_enable_wol(dev); 853 } 854 855 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 856 857 lwkt_serialize_exit(ifp->if_serializer); 858 859 ether_ifdetach(ifp); 860 } else { 861 em_rel_hw_control(adapter); 862 } 863 bus_generic_detach(dev); 864 865 em_free_pci_res(adapter); 866 867 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 868 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 869 870 /* Free Transmit Descriptor ring */ 871 if (adapter->tx_desc_base) 872 em_dma_free(adapter, &adapter->txdma); 873 874 /* Free Receive Descriptor ring */ 875 if (adapter->rx_desc_base) 876 em_dma_free(adapter, &adapter->rxdma); 877 878 /* Free top level busdma tag */ 879 if (adapter->parent_dtag != NULL) 880 bus_dma_tag_destroy(adapter->parent_dtag); 881 882 /* Free sysctl tree */ 883 if (adapter->sysctl_tree != NULL) 884 sysctl_ctx_free(&adapter->sysctl_ctx); 885 886 return (0); 887 } 888 889 static int 890 em_shutdown(device_t dev) 891 { 892 return em_suspend(dev); 893 } 894 895 static int 896 em_suspend(device_t dev) 897 { 898 struct adapter *adapter = device_get_softc(dev); 899 struct ifnet *ifp = &adapter->arpcom.ac_if; 900 901 lwkt_serialize_enter(ifp->if_serializer); 902 903 em_stop(adapter); 904 905 em_rel_mgmt(adapter); 906 em_rel_hw_control(adapter); 907 908 if (adapter->wol) { 909 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 910 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 911 em_enable_wol(dev); 912 } 913 914 lwkt_serialize_exit(ifp->if_serializer); 915 916 return bus_generic_suspend(dev); 917 } 918 919 static int 920 em_resume(device_t dev) 921 { 922 struct adapter *adapter = device_get_softc(dev); 923 struct ifnet *ifp = &adapter->arpcom.ac_if; 924 925 lwkt_serialize_enter(ifp->if_serializer); 926 927 em_init(adapter); 928 em_get_mgmt(adapter); 929 if_devstart(ifp); 930 931 lwkt_serialize_exit(ifp->if_serializer); 932 933 return bus_generic_resume(dev); 934 } 935 936 static void 937 em_start(struct ifnet *ifp) 938 { 939 struct adapter *adapter = ifp->if_softc; 940 struct mbuf *m_head; 941 942 ASSERT_SERIALIZED(ifp->if_serializer); 943 944 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 945 return; 946 947 if (!adapter->link_active) { 948 ifq_purge(&ifp->if_snd); 949 return; 950 } 951 952 while (!ifq_is_empty(&ifp->if_snd)) { 953 /* Now do we at least have a minimal? */ 954 if (EM_IS_OACTIVE(adapter)) { 955 em_tx_collect(adapter); 956 if (EM_IS_OACTIVE(adapter)) { 957 ifp->if_flags |= IFF_OACTIVE; 958 adapter->no_tx_desc_avail1++; 959 break; 960 } 961 } 962 963 logif(pkt_txqueue); 964 m_head = ifq_dequeue(&ifp->if_snd, NULL); 965 if (m_head == NULL) 966 break; 967 968 if (em_encap(adapter, &m_head)) { 969 ifp->if_oerrors++; 970 em_tx_collect(adapter); 971 continue; 972 } 973 974 /* Send a copy of the frame to the BPF listener */ 975 ETHER_BPF_MTAP(ifp, m_head); 976 977 /* Set timeout in case hardware has problems transmitting. */ 978 ifp->if_timer = EM_TX_TIMEOUT; 979 } 980 } 981 982 static int 983 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 984 { 985 struct adapter *adapter = ifp->if_softc; 986 struct ifreq *ifr = (struct ifreq *)data; 987 uint16_t eeprom_data = 0; 988 int max_frame_size, mask, reinit; 989 int error = 0; 990 991 ASSERT_SERIALIZED(ifp->if_serializer); 992 993 switch (command) { 994 case SIOCSIFMTU: 995 switch (adapter->hw.mac.type) { 996 case e1000_82573: 997 /* 998 * 82573 only supports jumbo frames 999 * if ASPM is disabled. 1000 */ 1001 e1000_read_nvm(&adapter->hw, 1002 NVM_INIT_3GIO_3, 1, &eeprom_data); 1003 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1004 max_frame_size = ETHER_MAX_LEN; 1005 break; 1006 } 1007 /* FALL THROUGH */ 1008 1009 /* Limit Jumbo Frame size */ 1010 case e1000_82571: 1011 case e1000_82572: 1012 case e1000_ich9lan: 1013 case e1000_ich10lan: 1014 case e1000_pch2lan: 1015 case e1000_82574: 1016 case e1000_82583: 1017 case e1000_80003es2lan: 1018 max_frame_size = 9234; 1019 break; 1020 1021 case e1000_pchlan: 1022 max_frame_size = 4096; 1023 break; 1024 1025 /* Adapters that do not support jumbo frames */ 1026 case e1000_82542: 1027 case e1000_ich8lan: 1028 max_frame_size = ETHER_MAX_LEN; 1029 break; 1030 1031 default: 1032 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1033 break; 1034 } 1035 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1036 ETHER_CRC_LEN) { 1037 error = EINVAL; 1038 break; 1039 } 1040 1041 ifp->if_mtu = ifr->ifr_mtu; 1042 adapter->max_frame_size = 1043 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1044 1045 if (ifp->if_flags & IFF_RUNNING) 1046 em_init(adapter); 1047 break; 1048 1049 case SIOCSIFFLAGS: 1050 if (ifp->if_flags & IFF_UP) { 1051 if ((ifp->if_flags & IFF_RUNNING)) { 1052 if ((ifp->if_flags ^ adapter->if_flags) & 1053 (IFF_PROMISC | IFF_ALLMULTI)) { 1054 em_disable_promisc(adapter); 1055 em_set_promisc(adapter); 1056 } 1057 } else { 1058 em_init(adapter); 1059 } 1060 } else if (ifp->if_flags & IFF_RUNNING) { 1061 em_stop(adapter); 1062 } 1063 adapter->if_flags = ifp->if_flags; 1064 break; 1065 1066 case SIOCADDMULTI: 1067 case SIOCDELMULTI: 1068 if (ifp->if_flags & IFF_RUNNING) { 1069 em_disable_intr(adapter); 1070 em_set_multi(adapter); 1071 if (adapter->hw.mac.type == e1000_82542 && 1072 adapter->hw.revision_id == E1000_REVISION_2) 1073 em_init_rx_unit(adapter); 1074 #ifdef DEVICE_POLLING 1075 if (!(ifp->if_flags & IFF_POLLING)) 1076 #endif 1077 em_enable_intr(adapter); 1078 } 1079 break; 1080 1081 case SIOCSIFMEDIA: 1082 /* Check SOL/IDER usage */ 1083 if (e1000_check_reset_block(&adapter->hw)) { 1084 device_printf(adapter->dev, "Media change is" 1085 " blocked due to SOL/IDER session.\n"); 1086 break; 1087 } 1088 /* FALL THROUGH */ 1089 1090 case SIOCGIFMEDIA: 1091 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1092 break; 1093 1094 case SIOCSIFCAP: 1095 reinit = 0; 1096 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1097 if (mask & IFCAP_HWCSUM) { 1098 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 1099 reinit = 1; 1100 } 1101 if (mask & IFCAP_VLAN_HWTAGGING) { 1102 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1103 reinit = 1; 1104 } 1105 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1106 em_init(adapter); 1107 break; 1108 1109 default: 1110 error = ether_ioctl(ifp, command, data); 1111 break; 1112 } 1113 return (error); 1114 } 1115 1116 static void 1117 em_watchdog(struct ifnet *ifp) 1118 { 1119 struct adapter *adapter = ifp->if_softc; 1120 1121 ASSERT_SERIALIZED(ifp->if_serializer); 1122 1123 /* 1124 * The timer is set to 5 every time start queues a packet. 1125 * Then txeof keeps resetting it as long as it cleans at 1126 * least one descriptor. 1127 * Finally, anytime all descriptors are clean the timer is 1128 * set to 0. 1129 */ 1130 1131 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1132 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1133 /* 1134 * If we reach here, all TX jobs are completed and 1135 * the TX engine should have been idled for some time. 1136 * We don't need to call if_devstart() here. 1137 */ 1138 ifp->if_flags &= ~IFF_OACTIVE; 1139 ifp->if_timer = 0; 1140 return; 1141 } 1142 1143 /* 1144 * If we are in this routine because of pause frames, then 1145 * don't reset the hardware. 1146 */ 1147 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1148 E1000_STATUS_TXOFF) { 1149 ifp->if_timer = EM_TX_TIMEOUT; 1150 return; 1151 } 1152 1153 if (e1000_check_for_link(&adapter->hw) == 0) 1154 if_printf(ifp, "watchdog timeout -- resetting\n"); 1155 1156 ifp->if_oerrors++; 1157 adapter->watchdog_events++; 1158 1159 em_init(adapter); 1160 1161 if (!ifq_is_empty(&ifp->if_snd)) 1162 if_devstart(ifp); 1163 } 1164 1165 static void 1166 em_init(void *xsc) 1167 { 1168 struct adapter *adapter = xsc; 1169 struct ifnet *ifp = &adapter->arpcom.ac_if; 1170 device_t dev = adapter->dev; 1171 uint32_t pba; 1172 1173 ASSERT_SERIALIZED(ifp->if_serializer); 1174 1175 em_stop(adapter); 1176 1177 /* 1178 * Packet Buffer Allocation (PBA) 1179 * Writing PBA sets the receive portion of the buffer 1180 * the remainder is used for the transmit buffer. 1181 * 1182 * Devices before the 82547 had a Packet Buffer of 64K. 1183 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1184 * After the 82547 the buffer was reduced to 40K. 1185 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1186 * Note: default does not leave enough room for Jumbo Frame >10k. 1187 */ 1188 switch (adapter->hw.mac.type) { 1189 case e1000_82547: 1190 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1191 if (adapter->max_frame_size > 8192) 1192 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1193 else 1194 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1195 adapter->tx_fifo_head = 0; 1196 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1197 adapter->tx_fifo_size = 1198 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1199 break; 1200 1201 /* Total Packet Buffer on these is 48K */ 1202 case e1000_82571: 1203 case e1000_82572: 1204 case e1000_80003es2lan: 1205 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1206 break; 1207 1208 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1209 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1210 break; 1211 1212 case e1000_82574: 1213 case e1000_82583: 1214 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1215 break; 1216 1217 case e1000_ich8lan: 1218 pba = E1000_PBA_8K; 1219 break; 1220 1221 case e1000_ich9lan: 1222 case e1000_ich10lan: 1223 #define E1000_PBA_10K 0x000A 1224 pba = E1000_PBA_10K; 1225 break; 1226 1227 case e1000_pchlan: 1228 case e1000_pch2lan: 1229 pba = E1000_PBA_26K; 1230 break; 1231 1232 default: 1233 /* Devices before 82547 had a Packet Buffer of 64K. */ 1234 if (adapter->max_frame_size > 8192) 1235 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1236 else 1237 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1238 } 1239 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1240 1241 /* Get the latest mac address, User can use a LAA */ 1242 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1243 1244 /* Put the address into the Receive Address Array */ 1245 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1246 1247 /* 1248 * With the 82571 adapter, RAR[0] may be overwritten 1249 * when the other port is reset, we make a duplicate 1250 * in RAR[14] for that eventuality, this assures 1251 * the interface continues to function. 1252 */ 1253 if (adapter->hw.mac.type == e1000_82571) { 1254 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1255 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1256 E1000_RAR_ENTRIES - 1); 1257 } 1258 1259 /* Reset the hardware */ 1260 if (em_reset(adapter)) { 1261 device_printf(dev, "Unable to reset the hardware\n"); 1262 /* XXX em_stop()? */ 1263 return; 1264 } 1265 em_update_link_status(adapter); 1266 1267 /* Setup VLAN support, basic and offload if available */ 1268 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1269 1270 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1271 uint32_t ctrl; 1272 1273 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1274 ctrl |= E1000_CTRL_VME; 1275 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1276 } 1277 1278 /* Set hardware offload abilities */ 1279 if (ifp->if_capenable & IFCAP_TXCSUM) 1280 ifp->if_hwassist = EM_CSUM_FEATURES; 1281 else 1282 ifp->if_hwassist = 0; 1283 1284 /* Configure for OS presence */ 1285 em_get_mgmt(adapter); 1286 1287 /* Prepare transmit descriptors and buffers */ 1288 em_init_tx_ring(adapter); 1289 em_init_tx_unit(adapter); 1290 1291 /* Setup Multicast table */ 1292 em_set_multi(adapter); 1293 1294 /* Prepare receive descriptors and buffers */ 1295 if (em_init_rx_ring(adapter)) { 1296 device_printf(dev, "Could not setup receive structures\n"); 1297 em_stop(adapter); 1298 return; 1299 } 1300 em_init_rx_unit(adapter); 1301 1302 /* Don't lose promiscuous settings */ 1303 em_set_promisc(adapter); 1304 1305 ifp->if_flags |= IFF_RUNNING; 1306 ifp->if_flags &= ~IFF_OACTIVE; 1307 1308 callout_reset(&adapter->timer, hz, em_timer, adapter); 1309 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1310 1311 /* MSI/X configuration for 82574 */ 1312 if (adapter->hw.mac.type == e1000_82574) { 1313 int tmp; 1314 1315 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1316 tmp |= E1000_CTRL_EXT_PBA_CLR; 1317 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1318 /* 1319 * XXX MSIX 1320 * Set the IVAR - interrupt vector routing. 1321 * Each nibble represents a vector, high bit 1322 * is enable, other 3 bits are the MSIX table 1323 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1324 * Link (other) to 2, hence the magic number. 1325 */ 1326 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1327 } 1328 1329 #ifdef DEVICE_POLLING 1330 /* 1331 * Only enable interrupts if we are not polling, make sure 1332 * they are off otherwise. 1333 */ 1334 if (ifp->if_flags & IFF_POLLING) 1335 em_disable_intr(adapter); 1336 else 1337 #endif /* DEVICE_POLLING */ 1338 em_enable_intr(adapter); 1339 1340 /* AMT based hardware can now take control from firmware */ 1341 if (adapter->has_manage && adapter->has_amt && 1342 adapter->hw.mac.type >= e1000_82571) 1343 em_get_hw_control(adapter); 1344 1345 /* Don't reset the phy next time init gets called */ 1346 adapter->hw.phy.reset_disable = TRUE; 1347 } 1348 1349 #ifdef DEVICE_POLLING 1350 1351 static void 1352 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1353 { 1354 struct adapter *adapter = ifp->if_softc; 1355 uint32_t reg_icr; 1356 1357 ASSERT_SERIALIZED(ifp->if_serializer); 1358 1359 switch (cmd) { 1360 case POLL_REGISTER: 1361 em_disable_intr(adapter); 1362 break; 1363 1364 case POLL_DEREGISTER: 1365 em_enable_intr(adapter); 1366 break; 1367 1368 case POLL_AND_CHECK_STATUS: 1369 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1370 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1371 callout_stop(&adapter->timer); 1372 adapter->hw.mac.get_link_status = 1; 1373 em_update_link_status(adapter); 1374 callout_reset(&adapter->timer, hz, em_timer, adapter); 1375 } 1376 /* FALL THROUGH */ 1377 case POLL_ONLY: 1378 if (ifp->if_flags & IFF_RUNNING) { 1379 em_rxeof(adapter, count); 1380 em_txeof(adapter); 1381 1382 if (!ifq_is_empty(&ifp->if_snd)) 1383 if_devstart(ifp); 1384 } 1385 break; 1386 } 1387 } 1388 1389 #endif /* DEVICE_POLLING */ 1390 1391 static void 1392 em_intr(void *xsc) 1393 { 1394 struct adapter *adapter = xsc; 1395 struct ifnet *ifp = &adapter->arpcom.ac_if; 1396 uint32_t reg_icr; 1397 1398 logif(intr_beg); 1399 ASSERT_SERIALIZED(ifp->if_serializer); 1400 1401 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1402 1403 if ((adapter->hw.mac.type >= e1000_82571 && 1404 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1405 reg_icr == 0) { 1406 logif(intr_end); 1407 return; 1408 } 1409 1410 /* 1411 * XXX: some laptops trigger several spurious interrupts 1412 * on em(4) when in the resume cycle. The ICR register 1413 * reports all-ones value in this case. Processing such 1414 * interrupts would lead to a freeze. I don't know why. 1415 */ 1416 if (reg_icr == 0xffffffff) { 1417 logif(intr_end); 1418 return; 1419 } 1420 1421 if (ifp->if_flags & IFF_RUNNING) { 1422 if (reg_icr & 1423 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1424 em_rxeof(adapter, -1); 1425 if (reg_icr & E1000_ICR_TXDW) { 1426 em_txeof(adapter); 1427 if (!ifq_is_empty(&ifp->if_snd)) 1428 if_devstart(ifp); 1429 } 1430 } 1431 1432 /* Link status change */ 1433 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1434 callout_stop(&adapter->timer); 1435 adapter->hw.mac.get_link_status = 1; 1436 em_update_link_status(adapter); 1437 1438 /* Deal with TX cruft when link lost */ 1439 em_tx_purge(adapter); 1440 1441 callout_reset(&adapter->timer, hz, em_timer, adapter); 1442 } 1443 1444 if (reg_icr & E1000_ICR_RXO) 1445 adapter->rx_overruns++; 1446 1447 logif(intr_end); 1448 } 1449 1450 static void 1451 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1452 { 1453 struct adapter *adapter = ifp->if_softc; 1454 u_char fiber_type = IFM_1000_SX; 1455 1456 ASSERT_SERIALIZED(ifp->if_serializer); 1457 1458 em_update_link_status(adapter); 1459 1460 ifmr->ifm_status = IFM_AVALID; 1461 ifmr->ifm_active = IFM_ETHER; 1462 1463 if (!adapter->link_active) 1464 return; 1465 1466 ifmr->ifm_status |= IFM_ACTIVE; 1467 1468 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1469 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1470 if (adapter->hw.mac.type == e1000_82545) 1471 fiber_type = IFM_1000_LX; 1472 ifmr->ifm_active |= fiber_type | IFM_FDX; 1473 } else { 1474 switch (adapter->link_speed) { 1475 case 10: 1476 ifmr->ifm_active |= IFM_10_T; 1477 break; 1478 case 100: 1479 ifmr->ifm_active |= IFM_100_TX; 1480 break; 1481 1482 case 1000: 1483 ifmr->ifm_active |= IFM_1000_T; 1484 break; 1485 } 1486 if (adapter->link_duplex == FULL_DUPLEX) 1487 ifmr->ifm_active |= IFM_FDX; 1488 else 1489 ifmr->ifm_active |= IFM_HDX; 1490 } 1491 } 1492 1493 static int 1494 em_media_change(struct ifnet *ifp) 1495 { 1496 struct adapter *adapter = ifp->if_softc; 1497 struct ifmedia *ifm = &adapter->media; 1498 1499 ASSERT_SERIALIZED(ifp->if_serializer); 1500 1501 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1502 return (EINVAL); 1503 1504 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1505 case IFM_AUTO: 1506 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1507 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1508 break; 1509 1510 case IFM_1000_LX: 1511 case IFM_1000_SX: 1512 case IFM_1000_T: 1513 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1514 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1515 break; 1516 1517 case IFM_100_TX: 1518 adapter->hw.mac.autoneg = FALSE; 1519 adapter->hw.phy.autoneg_advertised = 0; 1520 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1521 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1522 else 1523 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1524 break; 1525 1526 case IFM_10_T: 1527 adapter->hw.mac.autoneg = FALSE; 1528 adapter->hw.phy.autoneg_advertised = 0; 1529 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1530 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1531 else 1532 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1533 break; 1534 1535 default: 1536 if_printf(ifp, "Unsupported media type\n"); 1537 break; 1538 } 1539 1540 /* 1541 * As the speed/duplex settings my have changed we need to 1542 * reset the PHY. 1543 */ 1544 adapter->hw.phy.reset_disable = FALSE; 1545 1546 em_init(adapter); 1547 1548 return (0); 1549 } 1550 1551 static int 1552 em_encap(struct adapter *adapter, struct mbuf **m_headp) 1553 { 1554 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1555 bus_dmamap_t map; 1556 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1557 struct e1000_tx_desc *ctxd = NULL; 1558 struct mbuf *m_head = *m_headp; 1559 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1560 int maxsegs, nsegs, i, j, first, last = 0, error; 1561 1562 if (m_head->m_len < EM_TXCSUM_MINHL && 1563 (m_head->m_flags & EM_CSUM_FEATURES)) { 1564 /* 1565 * Make sure that ethernet header and ip.ip_hl are in 1566 * contiguous memory, since if TXCSUM is enabled, later 1567 * TX context descriptor's setup need to access ip.ip_hl. 1568 */ 1569 error = em_txcsum_pullup(adapter, m_headp); 1570 if (error) { 1571 KKASSERT(*m_headp == NULL); 1572 return error; 1573 } 1574 m_head = *m_headp; 1575 } 1576 1577 txd_upper = txd_lower = 0; 1578 txd_used = 0; 1579 1580 /* 1581 * Capture the first descriptor index, this descriptor 1582 * will have the index of the EOP which is the only one 1583 * that now gets a DONE bit writeback. 1584 */ 1585 first = adapter->next_avail_tx_desc; 1586 tx_buffer = &adapter->tx_buffer_area[first]; 1587 tx_buffer_mapped = tx_buffer; 1588 map = tx_buffer->map; 1589 1590 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1591 KASSERT(maxsegs >= adapter->spare_tx_desc, 1592 ("not enough spare TX desc")); 1593 if (adapter->pcix_82544) { 1594 /* Half it; see the comment in em_attach() */ 1595 maxsegs >>= 1; 1596 } 1597 if (maxsegs > EM_MAX_SCATTER) 1598 maxsegs = EM_MAX_SCATTER; 1599 1600 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1601 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1602 if (error) { 1603 if (error == ENOBUFS) 1604 adapter->mbuf_alloc_failed++; 1605 else 1606 adapter->no_tx_dma_setup++; 1607 1608 m_freem(*m_headp); 1609 *m_headp = NULL; 1610 return error; 1611 } 1612 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1613 1614 m_head = *m_headp; 1615 adapter->tx_nsegs += nsegs; 1616 1617 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1618 /* TX csum offloading will consume one TX desc */ 1619 adapter->tx_nsegs += em_txcsum(adapter, m_head, 1620 &txd_upper, &txd_lower); 1621 } 1622 i = adapter->next_avail_tx_desc; 1623 1624 /* Set up our transmit descriptors */ 1625 for (j = 0; j < nsegs; j++) { 1626 /* If adapter is 82544 and on PCIX bus */ 1627 if(adapter->pcix_82544) { 1628 DESC_ARRAY desc_array; 1629 uint32_t array_elements, counter; 1630 1631 /* 1632 * Check the Address and Length combination and 1633 * split the data accordingly 1634 */ 1635 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1636 segs[j].ds_len, &desc_array); 1637 for (counter = 0; counter < array_elements; counter++) { 1638 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1639 1640 tx_buffer = &adapter->tx_buffer_area[i]; 1641 ctxd = &adapter->tx_desc_base[i]; 1642 1643 ctxd->buffer_addr = htole64( 1644 desc_array.descriptor[counter].address); 1645 ctxd->lower.data = htole32( 1646 E1000_TXD_CMD_IFCS | txd_lower | 1647 desc_array.descriptor[counter].length); 1648 ctxd->upper.data = htole32(txd_upper); 1649 1650 last = i; 1651 if (++i == adapter->num_tx_desc) 1652 i = 0; 1653 1654 txd_used++; 1655 } 1656 } else { 1657 tx_buffer = &adapter->tx_buffer_area[i]; 1658 ctxd = &adapter->tx_desc_base[i]; 1659 1660 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1661 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1662 txd_lower | segs[j].ds_len); 1663 ctxd->upper.data = htole32(txd_upper); 1664 1665 last = i; 1666 if (++i == adapter->num_tx_desc) 1667 i = 0; 1668 } 1669 } 1670 1671 adapter->next_avail_tx_desc = i; 1672 if (adapter->pcix_82544) { 1673 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1674 adapter->num_tx_desc_avail -= txd_used; 1675 } else { 1676 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1677 adapter->num_tx_desc_avail -= nsegs; 1678 } 1679 1680 /* Handle VLAN tag */ 1681 if (m_head->m_flags & M_VLANTAG) { 1682 /* Set the vlan id. */ 1683 ctxd->upper.fields.special = 1684 htole16(m_head->m_pkthdr.ether_vlantag); 1685 1686 /* Tell hardware to add tag */ 1687 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1688 } 1689 1690 tx_buffer->m_head = m_head; 1691 tx_buffer_mapped->map = tx_buffer->map; 1692 tx_buffer->map = map; 1693 1694 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1695 adapter->tx_nsegs = 0; 1696 1697 /* 1698 * Report Status (RS) is turned on 1699 * every tx_int_nsegs descriptors. 1700 */ 1701 cmd = E1000_TXD_CMD_RS; 1702 1703 /* 1704 * Keep track of the descriptor, which will 1705 * be written back by hardware. 1706 */ 1707 adapter->tx_dd[adapter->tx_dd_tail] = last; 1708 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1709 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1710 } 1711 1712 /* 1713 * Last Descriptor of Packet needs End Of Packet (EOP) 1714 */ 1715 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1716 1717 /* 1718 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 1719 * that this frame is available to transmit. 1720 */ 1721 if (adapter->hw.mac.type == e1000_82547 && 1722 adapter->link_duplex == HALF_DUPLEX) { 1723 em_82547_move_tail_serialized(adapter); 1724 } else { 1725 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1726 if (adapter->hw.mac.type == e1000_82547) { 1727 em_82547_update_fifo_head(adapter, 1728 m_head->m_pkthdr.len); 1729 } 1730 } 1731 return (0); 1732 } 1733 1734 /* 1735 * 82547 workaround to avoid controller hang in half-duplex environment. 1736 * The workaround is to avoid queuing a large packet that would span 1737 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1738 * in this case. We do that only when FIFO is quiescent. 1739 */ 1740 static void 1741 em_82547_move_tail_serialized(struct adapter *adapter) 1742 { 1743 struct e1000_tx_desc *tx_desc; 1744 uint16_t hw_tdt, sw_tdt, length = 0; 1745 bool eop = 0; 1746 1747 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1748 1749 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1750 sw_tdt = adapter->next_avail_tx_desc; 1751 1752 while (hw_tdt != sw_tdt) { 1753 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1754 length += tx_desc->lower.flags.length; 1755 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1756 if (++hw_tdt == adapter->num_tx_desc) 1757 hw_tdt = 0; 1758 1759 if (eop) { 1760 if (em_82547_fifo_workaround(adapter, length)) { 1761 adapter->tx_fifo_wrk_cnt++; 1762 callout_reset(&adapter->tx_fifo_timer, 1, 1763 em_82547_move_tail, adapter); 1764 break; 1765 } 1766 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1767 em_82547_update_fifo_head(adapter, length); 1768 length = 0; 1769 } 1770 } 1771 } 1772 1773 static void 1774 em_82547_move_tail(void *xsc) 1775 { 1776 struct adapter *adapter = xsc; 1777 struct ifnet *ifp = &adapter->arpcom.ac_if; 1778 1779 lwkt_serialize_enter(ifp->if_serializer); 1780 em_82547_move_tail_serialized(adapter); 1781 lwkt_serialize_exit(ifp->if_serializer); 1782 } 1783 1784 static int 1785 em_82547_fifo_workaround(struct adapter *adapter, int len) 1786 { 1787 int fifo_space, fifo_pkt_len; 1788 1789 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1790 1791 if (adapter->link_duplex == HALF_DUPLEX) { 1792 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1793 1794 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1795 if (em_82547_tx_fifo_reset(adapter)) 1796 return (0); 1797 else 1798 return (1); 1799 } 1800 } 1801 return (0); 1802 } 1803 1804 static void 1805 em_82547_update_fifo_head(struct adapter *adapter, int len) 1806 { 1807 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1808 1809 /* tx_fifo_head is always 16 byte aligned */ 1810 adapter->tx_fifo_head += fifo_pkt_len; 1811 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1812 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1813 } 1814 1815 static int 1816 em_82547_tx_fifo_reset(struct adapter *adapter) 1817 { 1818 uint32_t tctl; 1819 1820 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1821 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1822 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1823 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1824 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1825 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1826 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1827 /* Disable TX unit */ 1828 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1829 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1830 tctl & ~E1000_TCTL_EN); 1831 1832 /* Reset FIFO pointers */ 1833 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1834 adapter->tx_head_addr); 1835 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1836 adapter->tx_head_addr); 1837 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1838 adapter->tx_head_addr); 1839 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1840 adapter->tx_head_addr); 1841 1842 /* Re-enable TX unit */ 1843 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1844 E1000_WRITE_FLUSH(&adapter->hw); 1845 1846 adapter->tx_fifo_head = 0; 1847 adapter->tx_fifo_reset_cnt++; 1848 1849 return (TRUE); 1850 } else { 1851 return (FALSE); 1852 } 1853 } 1854 1855 static void 1856 em_set_promisc(struct adapter *adapter) 1857 { 1858 struct ifnet *ifp = &adapter->arpcom.ac_if; 1859 uint32_t reg_rctl; 1860 1861 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1862 1863 if (ifp->if_flags & IFF_PROMISC) { 1864 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1865 /* Turn this on if you want to see bad packets */ 1866 if (em_debug_sbp) 1867 reg_rctl |= E1000_RCTL_SBP; 1868 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1869 } else if (ifp->if_flags & IFF_ALLMULTI) { 1870 reg_rctl |= E1000_RCTL_MPE; 1871 reg_rctl &= ~E1000_RCTL_UPE; 1872 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1873 } 1874 } 1875 1876 static void 1877 em_disable_promisc(struct adapter *adapter) 1878 { 1879 uint32_t reg_rctl; 1880 1881 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1882 1883 reg_rctl &= ~E1000_RCTL_UPE; 1884 reg_rctl &= ~E1000_RCTL_MPE; 1885 reg_rctl &= ~E1000_RCTL_SBP; 1886 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1887 } 1888 1889 static void 1890 em_set_multi(struct adapter *adapter) 1891 { 1892 struct ifnet *ifp = &adapter->arpcom.ac_if; 1893 struct ifmultiaddr *ifma; 1894 uint32_t reg_rctl = 0; 1895 uint8_t *mta; 1896 int mcnt = 0; 1897 1898 mta = adapter->mta; 1899 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1900 1901 if (adapter->hw.mac.type == e1000_82542 && 1902 adapter->hw.revision_id == E1000_REVISION_2) { 1903 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1904 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1905 e1000_pci_clear_mwi(&adapter->hw); 1906 reg_rctl |= E1000_RCTL_RST; 1907 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1908 msec_delay(5); 1909 } 1910 1911 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1912 if (ifma->ifma_addr->sa_family != AF_LINK) 1913 continue; 1914 1915 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1916 break; 1917 1918 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1919 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1920 mcnt++; 1921 } 1922 1923 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1924 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1925 reg_rctl |= E1000_RCTL_MPE; 1926 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1927 } else { 1928 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1929 } 1930 1931 if (adapter->hw.mac.type == e1000_82542 && 1932 adapter->hw.revision_id == E1000_REVISION_2) { 1933 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1934 reg_rctl &= ~E1000_RCTL_RST; 1935 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1936 msec_delay(5); 1937 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1938 e1000_pci_set_mwi(&adapter->hw); 1939 } 1940 } 1941 1942 /* 1943 * This routine checks for link status and updates statistics. 1944 */ 1945 static void 1946 em_timer(void *xsc) 1947 { 1948 struct adapter *adapter = xsc; 1949 struct ifnet *ifp = &adapter->arpcom.ac_if; 1950 1951 lwkt_serialize_enter(ifp->if_serializer); 1952 1953 em_update_link_status(adapter); 1954 em_update_stats(adapter); 1955 1956 /* Reset LAA into RAR[0] on 82571 */ 1957 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 1958 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1959 1960 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1961 em_print_hw_stats(adapter); 1962 1963 em_smartspeed(adapter); 1964 1965 callout_reset(&adapter->timer, hz, em_timer, adapter); 1966 1967 lwkt_serialize_exit(ifp->if_serializer); 1968 } 1969 1970 static void 1971 em_update_link_status(struct adapter *adapter) 1972 { 1973 struct e1000_hw *hw = &adapter->hw; 1974 struct ifnet *ifp = &adapter->arpcom.ac_if; 1975 device_t dev = adapter->dev; 1976 uint32_t link_check = 0; 1977 1978 /* Get the cached link value or read phy for real */ 1979 switch (hw->phy.media_type) { 1980 case e1000_media_type_copper: 1981 if (hw->mac.get_link_status) { 1982 /* Do the work to read phy */ 1983 e1000_check_for_link(hw); 1984 link_check = !hw->mac.get_link_status; 1985 if (link_check) /* ESB2 fix */ 1986 e1000_cfg_on_link_up(hw); 1987 } else { 1988 link_check = TRUE; 1989 } 1990 break; 1991 1992 case e1000_media_type_fiber: 1993 e1000_check_for_link(hw); 1994 link_check = 1995 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1996 break; 1997 1998 case e1000_media_type_internal_serdes: 1999 e1000_check_for_link(hw); 2000 link_check = adapter->hw.mac.serdes_has_link; 2001 break; 2002 2003 case e1000_media_type_unknown: 2004 default: 2005 break; 2006 } 2007 2008 /* Now check for a transition */ 2009 if (link_check && adapter->link_active == 0) { 2010 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2011 &adapter->link_duplex); 2012 2013 /* 2014 * Check if we should enable/disable SPEED_MODE bit on 2015 * 82571/82572 2016 */ 2017 if (adapter->link_speed != SPEED_1000 && 2018 (hw->mac.type == e1000_82571 || 2019 hw->mac.type == e1000_82572)) { 2020 int tarc0; 2021 2022 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2023 tarc0 &= ~SPEED_MODE_BIT; 2024 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2025 } 2026 if (bootverbose) { 2027 device_printf(dev, "Link is up %d Mbps %s\n", 2028 adapter->link_speed, 2029 ((adapter->link_duplex == FULL_DUPLEX) ? 2030 "Full Duplex" : "Half Duplex")); 2031 } 2032 adapter->link_active = 1; 2033 adapter->smartspeed = 0; 2034 ifp->if_baudrate = adapter->link_speed * 1000000; 2035 ifp->if_link_state = LINK_STATE_UP; 2036 if_link_state_change(ifp); 2037 } else if (!link_check && adapter->link_active == 1) { 2038 ifp->if_baudrate = adapter->link_speed = 0; 2039 adapter->link_duplex = 0; 2040 if (bootverbose) 2041 device_printf(dev, "Link is Down\n"); 2042 adapter->link_active = 0; 2043 #if 0 2044 /* Link down, disable watchdog */ 2045 if->if_timer = 0; 2046 #endif 2047 ifp->if_link_state = LINK_STATE_DOWN; 2048 if_link_state_change(ifp); 2049 } 2050 } 2051 2052 static void 2053 em_stop(struct adapter *adapter) 2054 { 2055 struct ifnet *ifp = &adapter->arpcom.ac_if; 2056 int i; 2057 2058 ASSERT_SERIALIZED(ifp->if_serializer); 2059 2060 em_disable_intr(adapter); 2061 2062 callout_stop(&adapter->timer); 2063 callout_stop(&adapter->tx_fifo_timer); 2064 2065 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2066 ifp->if_timer = 0; 2067 2068 e1000_reset_hw(&adapter->hw); 2069 if (adapter->hw.mac.type >= e1000_82544) 2070 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2071 2072 for (i = 0; i < adapter->num_tx_desc; i++) { 2073 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2074 2075 if (tx_buffer->m_head != NULL) { 2076 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2077 m_freem(tx_buffer->m_head); 2078 tx_buffer->m_head = NULL; 2079 } 2080 } 2081 2082 for (i = 0; i < adapter->num_rx_desc; i++) { 2083 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2084 2085 if (rx_buffer->m_head != NULL) { 2086 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2087 m_freem(rx_buffer->m_head); 2088 rx_buffer->m_head = NULL; 2089 } 2090 } 2091 2092 if (adapter->fmp != NULL) 2093 m_freem(adapter->fmp); 2094 adapter->fmp = NULL; 2095 adapter->lmp = NULL; 2096 2097 adapter->csum_flags = 0; 2098 adapter->csum_ehlen = 0; 2099 adapter->csum_iphlen = 0; 2100 2101 adapter->tx_dd_head = 0; 2102 adapter->tx_dd_tail = 0; 2103 adapter->tx_nsegs = 0; 2104 } 2105 2106 static int 2107 em_get_hw_info(struct adapter *adapter) 2108 { 2109 device_t dev = adapter->dev; 2110 2111 /* Save off the information about this board */ 2112 adapter->hw.vendor_id = pci_get_vendor(dev); 2113 adapter->hw.device_id = pci_get_device(dev); 2114 adapter->hw.revision_id = pci_get_revid(dev); 2115 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2116 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2117 2118 /* Do Shared Code Init and Setup */ 2119 if (e1000_set_mac_type(&adapter->hw)) 2120 return ENXIO; 2121 return 0; 2122 } 2123 2124 static int 2125 em_alloc_pci_res(struct adapter *adapter) 2126 { 2127 device_t dev = adapter->dev; 2128 u_int intr_flags; 2129 int val, rid; 2130 2131 /* Enable bus mastering */ 2132 pci_enable_busmaster(dev); 2133 2134 adapter->memory_rid = EM_BAR_MEM; 2135 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2136 &adapter->memory_rid, RF_ACTIVE); 2137 if (adapter->memory == NULL) { 2138 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2139 return (ENXIO); 2140 } 2141 adapter->osdep.mem_bus_space_tag = 2142 rman_get_bustag(adapter->memory); 2143 adapter->osdep.mem_bus_space_handle = 2144 rman_get_bushandle(adapter->memory); 2145 2146 /* XXX This is quite goofy, it is not actually used */ 2147 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2148 2149 /* Only older adapters use IO mapping */ 2150 if (adapter->hw.mac.type > e1000_82543 && 2151 adapter->hw.mac.type < e1000_82571) { 2152 /* Figure our where our IO BAR is ? */ 2153 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2154 val = pci_read_config(dev, rid, 4); 2155 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2156 adapter->io_rid = rid; 2157 break; 2158 } 2159 rid += 4; 2160 /* check for 64bit BAR */ 2161 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2162 rid += 4; 2163 } 2164 if (rid >= PCIR_CARDBUSCIS) { 2165 device_printf(dev, "Unable to locate IO BAR\n"); 2166 return (ENXIO); 2167 } 2168 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2169 &adapter->io_rid, RF_ACTIVE); 2170 if (adapter->ioport == NULL) { 2171 device_printf(dev, "Unable to allocate bus resource: " 2172 "ioport\n"); 2173 return (ENXIO); 2174 } 2175 adapter->hw.io_base = 0; 2176 adapter->osdep.io_bus_space_tag = 2177 rman_get_bustag(adapter->ioport); 2178 adapter->osdep.io_bus_space_handle = 2179 rman_get_bushandle(adapter->ioport); 2180 } 2181 2182 adapter->intr_type = pci_alloc_1intr(dev, em_msi_enable, 2183 &adapter->intr_rid, &intr_flags); 2184 2185 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2186 &adapter->intr_rid, intr_flags); 2187 if (adapter->intr_res == NULL) { 2188 device_printf(dev, "Unable to allocate bus resource: " 2189 "interrupt\n"); 2190 return (ENXIO); 2191 } 2192 2193 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2194 adapter->hw.back = &adapter->osdep; 2195 return (0); 2196 } 2197 2198 static void 2199 em_free_pci_res(struct adapter *adapter) 2200 { 2201 device_t dev = adapter->dev; 2202 2203 if (adapter->intr_res != NULL) { 2204 bus_release_resource(dev, SYS_RES_IRQ, 2205 adapter->intr_rid, adapter->intr_res); 2206 } 2207 2208 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2209 pci_release_msi(dev); 2210 2211 if (adapter->memory != NULL) { 2212 bus_release_resource(dev, SYS_RES_MEMORY, 2213 adapter->memory_rid, adapter->memory); 2214 } 2215 2216 if (adapter->flash != NULL) { 2217 bus_release_resource(dev, SYS_RES_MEMORY, 2218 adapter->flash_rid, adapter->flash); 2219 } 2220 2221 if (adapter->ioport != NULL) { 2222 bus_release_resource(dev, SYS_RES_IOPORT, 2223 adapter->io_rid, adapter->ioport); 2224 } 2225 } 2226 2227 static int 2228 em_reset(struct adapter *adapter) 2229 { 2230 device_t dev = adapter->dev; 2231 uint16_t rx_buffer_size; 2232 2233 /* When hardware is reset, fifo_head is also reset */ 2234 adapter->tx_fifo_head = 0; 2235 2236 /* Set up smart power down as default off on newer adapters. */ 2237 if (!em_smart_pwr_down && 2238 (adapter->hw.mac.type == e1000_82571 || 2239 adapter->hw.mac.type == e1000_82572)) { 2240 uint16_t phy_tmp = 0; 2241 2242 /* Speed up time to link by disabling smart power down. */ 2243 e1000_read_phy_reg(&adapter->hw, 2244 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2245 phy_tmp &= ~IGP02E1000_PM_SPD; 2246 e1000_write_phy_reg(&adapter->hw, 2247 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2248 } 2249 2250 /* 2251 * These parameters control the automatic generation (Tx) and 2252 * response (Rx) to Ethernet PAUSE frames. 2253 * - High water mark should allow for at least two frames to be 2254 * received after sending an XOFF. 2255 * - Low water mark works best when it is very near the high water mark. 2256 * This allows the receiver to restart by sending XON when it has 2257 * drained a bit. Here we use an arbitary value of 1500 which will 2258 * restart after one full frame is pulled from the buffer. There 2259 * could be several smaller frames in the buffer and if so they will 2260 * not trigger the XON until their total number reduces the buffer 2261 * by 1500. 2262 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2263 */ 2264 rx_buffer_size = 2265 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2266 2267 adapter->hw.fc.high_water = rx_buffer_size - 2268 roundup2(adapter->max_frame_size, 1024); 2269 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2270 2271 if (adapter->hw.mac.type == e1000_80003es2lan) 2272 adapter->hw.fc.pause_time = 0xFFFF; 2273 else 2274 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2275 2276 adapter->hw.fc.send_xon = TRUE; 2277 2278 adapter->hw.fc.requested_mode = e1000_fc_full; 2279 2280 /* Workaround: no TX flow ctrl for PCH */ 2281 if (adapter->hw.mac.type == e1000_pchlan) 2282 adapter->hw.fc.requested_mode = e1000_fc_rx_pause; 2283 2284 /* Override - settings for PCH2LAN, ya its magic :) */ 2285 if (adapter->hw.mac.type == e1000_pch2lan) { 2286 adapter->hw.fc.high_water = 0x5C20; 2287 adapter->hw.fc.low_water = 0x5048; 2288 adapter->hw.fc.pause_time = 0x0650; 2289 adapter->hw.fc.refresh_time = 0x0400; 2290 2291 /* Jumbos need adjusted PBA */ 2292 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2293 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2294 else 2295 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2296 } 2297 2298 /* Issue a global reset */ 2299 e1000_reset_hw(&adapter->hw); 2300 if (adapter->hw.mac.type >= e1000_82544) 2301 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2302 em_disable_aspm(adapter); 2303 2304 if (e1000_init_hw(&adapter->hw) < 0) { 2305 device_printf(dev, "Hardware Initialization Failed\n"); 2306 return (EIO); 2307 } 2308 2309 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2310 e1000_get_phy_info(&adapter->hw); 2311 e1000_check_for_link(&adapter->hw); 2312 2313 return (0); 2314 } 2315 2316 static void 2317 em_setup_ifp(struct adapter *adapter) 2318 { 2319 struct ifnet *ifp = &adapter->arpcom.ac_if; 2320 2321 if_initname(ifp, device_get_name(adapter->dev), 2322 device_get_unit(adapter->dev)); 2323 ifp->if_softc = adapter; 2324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2325 ifp->if_init = em_init; 2326 ifp->if_ioctl = em_ioctl; 2327 ifp->if_start = em_start; 2328 #ifdef DEVICE_POLLING 2329 ifp->if_poll = em_poll; 2330 #endif 2331 ifp->if_watchdog = em_watchdog; 2332 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2333 ifq_set_ready(&ifp->if_snd); 2334 2335 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2336 2337 if (adapter->hw.mac.type >= e1000_82543) 2338 ifp->if_capabilities = IFCAP_HWCSUM; 2339 2340 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2341 ifp->if_capenable = ifp->if_capabilities; 2342 2343 if (ifp->if_capenable & IFCAP_TXCSUM) 2344 ifp->if_hwassist = EM_CSUM_FEATURES; 2345 2346 /* 2347 * Tell the upper layer(s) we support long frames. 2348 */ 2349 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2350 2351 /* 2352 * Specify the media types supported by this adapter and register 2353 * callbacks to update media and link information 2354 */ 2355 ifmedia_init(&adapter->media, IFM_IMASK, 2356 em_media_change, em_media_status); 2357 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2358 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2359 u_char fiber_type = IFM_1000_SX; /* default type */ 2360 2361 if (adapter->hw.mac.type == e1000_82545) 2362 fiber_type = IFM_1000_LX; 2363 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2364 0, NULL); 2365 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2366 } else { 2367 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2368 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2369 0, NULL); 2370 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2371 0, NULL); 2372 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2373 0, NULL); 2374 if (adapter->hw.phy.type != e1000_phy_ife) { 2375 ifmedia_add(&adapter->media, 2376 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2377 ifmedia_add(&adapter->media, 2378 IFM_ETHER | IFM_1000_T, 0, NULL); 2379 } 2380 } 2381 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2382 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2383 } 2384 2385 2386 /* 2387 * Workaround for SmartSpeed on 82541 and 82547 controllers 2388 */ 2389 static void 2390 em_smartspeed(struct adapter *adapter) 2391 { 2392 uint16_t phy_tmp; 2393 2394 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2395 adapter->hw.mac.autoneg == 0 || 2396 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2397 return; 2398 2399 if (adapter->smartspeed == 0) { 2400 /* 2401 * If Master/Slave config fault is asserted twice, 2402 * we assume back-to-back 2403 */ 2404 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2405 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2406 return; 2407 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2408 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2409 e1000_read_phy_reg(&adapter->hw, 2410 PHY_1000T_CTRL, &phy_tmp); 2411 if (phy_tmp & CR_1000T_MS_ENABLE) { 2412 phy_tmp &= ~CR_1000T_MS_ENABLE; 2413 e1000_write_phy_reg(&adapter->hw, 2414 PHY_1000T_CTRL, phy_tmp); 2415 adapter->smartspeed++; 2416 if (adapter->hw.mac.autoneg && 2417 !e1000_phy_setup_autoneg(&adapter->hw) && 2418 !e1000_read_phy_reg(&adapter->hw, 2419 PHY_CONTROL, &phy_tmp)) { 2420 phy_tmp |= MII_CR_AUTO_NEG_EN | 2421 MII_CR_RESTART_AUTO_NEG; 2422 e1000_write_phy_reg(&adapter->hw, 2423 PHY_CONTROL, phy_tmp); 2424 } 2425 } 2426 } 2427 return; 2428 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2429 /* If still no link, perhaps using 2/3 pair cable */ 2430 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2431 phy_tmp |= CR_1000T_MS_ENABLE; 2432 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2433 if (adapter->hw.mac.autoneg && 2434 !e1000_phy_setup_autoneg(&adapter->hw) && 2435 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2436 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2437 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2438 } 2439 } 2440 2441 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2442 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2443 adapter->smartspeed = 0; 2444 } 2445 2446 static int 2447 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2448 struct em_dma_alloc *dma) 2449 { 2450 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2451 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2452 &dma->dma_tag, &dma->dma_map, 2453 &dma->dma_paddr); 2454 if (dma->dma_vaddr == NULL) 2455 return ENOMEM; 2456 else 2457 return 0; 2458 } 2459 2460 static void 2461 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2462 { 2463 if (dma->dma_tag == NULL) 2464 return; 2465 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2466 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2467 bus_dma_tag_destroy(dma->dma_tag); 2468 } 2469 2470 static int 2471 em_create_tx_ring(struct adapter *adapter) 2472 { 2473 device_t dev = adapter->dev; 2474 struct em_buffer *tx_buffer; 2475 int error, i; 2476 2477 adapter->tx_buffer_area = 2478 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2479 M_DEVBUF, M_WAITOK | M_ZERO); 2480 2481 /* 2482 * Create DMA tags for tx buffers 2483 */ 2484 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2485 1, 0, /* alignment, bounds */ 2486 BUS_SPACE_MAXADDR, /* lowaddr */ 2487 BUS_SPACE_MAXADDR, /* highaddr */ 2488 NULL, NULL, /* filter, filterarg */ 2489 EM_TSO_SIZE, /* maxsize */ 2490 EM_MAX_SCATTER, /* nsegments */ 2491 EM_MAX_SEGSIZE, /* maxsegsize */ 2492 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2493 BUS_DMA_ONEBPAGE, /* flags */ 2494 &adapter->txtag); 2495 if (error) { 2496 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2497 kfree(adapter->tx_buffer_area, M_DEVBUF); 2498 adapter->tx_buffer_area = NULL; 2499 return error; 2500 } 2501 2502 /* 2503 * Create DMA maps for tx buffers 2504 */ 2505 for (i = 0; i < adapter->num_tx_desc; i++) { 2506 tx_buffer = &adapter->tx_buffer_area[i]; 2507 2508 error = bus_dmamap_create(adapter->txtag, 2509 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2510 &tx_buffer->map); 2511 if (error) { 2512 device_printf(dev, "Unable to create TX DMA map\n"); 2513 em_destroy_tx_ring(adapter, i); 2514 return error; 2515 } 2516 } 2517 return (0); 2518 } 2519 2520 static void 2521 em_init_tx_ring(struct adapter *adapter) 2522 { 2523 /* Clear the old ring contents */ 2524 bzero(adapter->tx_desc_base, 2525 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2526 2527 /* Reset state */ 2528 adapter->next_avail_tx_desc = 0; 2529 adapter->next_tx_to_clean = 0; 2530 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2531 } 2532 2533 static void 2534 em_init_tx_unit(struct adapter *adapter) 2535 { 2536 uint32_t tctl, tarc, tipg = 0; 2537 uint64_t bus_addr; 2538 2539 /* Setup the Base and Length of the Tx Descriptor Ring */ 2540 bus_addr = adapter->txdma.dma_paddr; 2541 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2542 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2543 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2544 (uint32_t)(bus_addr >> 32)); 2545 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2546 (uint32_t)bus_addr); 2547 /* Setup the HW Tx Head and Tail descriptor pointers */ 2548 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2549 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2550 2551 /* Set the default values for the Tx Inter Packet Gap timer */ 2552 switch (adapter->hw.mac.type) { 2553 case e1000_82542: 2554 tipg = DEFAULT_82542_TIPG_IPGT; 2555 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2556 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2557 break; 2558 2559 case e1000_80003es2lan: 2560 tipg = DEFAULT_82543_TIPG_IPGR1; 2561 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2562 E1000_TIPG_IPGR2_SHIFT; 2563 break; 2564 2565 default: 2566 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2567 adapter->hw.phy.media_type == 2568 e1000_media_type_internal_serdes) 2569 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2570 else 2571 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2572 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2573 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2574 break; 2575 } 2576 2577 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2578 2579 /* NOTE: 0 is not allowed for TIDV */ 2580 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2581 if(adapter->hw.mac.type >= e1000_82540) 2582 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2583 2584 if (adapter->hw.mac.type == e1000_82571 || 2585 adapter->hw.mac.type == e1000_82572) { 2586 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2587 tarc |= SPEED_MODE_BIT; 2588 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2589 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2590 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2591 tarc |= 1; 2592 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2593 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2594 tarc |= 1; 2595 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2596 } 2597 2598 /* Program the Transmit Control Register */ 2599 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2600 tctl &= ~E1000_TCTL_CT; 2601 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2602 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2603 2604 if (adapter->hw.mac.type >= e1000_82571) 2605 tctl |= E1000_TCTL_MULR; 2606 2607 /* This write will effectively turn on the transmit unit. */ 2608 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2609 } 2610 2611 static void 2612 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2613 { 2614 struct em_buffer *tx_buffer; 2615 int i; 2616 2617 if (adapter->tx_buffer_area == NULL) 2618 return; 2619 2620 for (i = 0; i < ndesc; i++) { 2621 tx_buffer = &adapter->tx_buffer_area[i]; 2622 2623 KKASSERT(tx_buffer->m_head == NULL); 2624 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2625 } 2626 bus_dma_tag_destroy(adapter->txtag); 2627 2628 kfree(adapter->tx_buffer_area, M_DEVBUF); 2629 adapter->tx_buffer_area = NULL; 2630 } 2631 2632 /* 2633 * The offload context needs to be set when we transfer the first 2634 * packet of a particular protocol (TCP/UDP). This routine has been 2635 * enhanced to deal with inserted VLAN headers. 2636 * 2637 * If the new packet's ether header length, ip header length and 2638 * csum offloading type are same as the previous packet, we should 2639 * avoid allocating a new csum context descriptor; mainly to take 2640 * advantage of the pipeline effect of the TX data read request. 2641 * 2642 * This function returns number of TX descrptors allocated for 2643 * csum context. 2644 */ 2645 static int 2646 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2647 uint32_t *txd_upper, uint32_t *txd_lower) 2648 { 2649 struct e1000_context_desc *TXD; 2650 struct em_buffer *tx_buffer; 2651 struct ether_vlan_header *eh; 2652 struct ip *ip; 2653 int curr_txd, ehdrlen, csum_flags; 2654 uint32_t cmd, hdr_len, ip_hlen; 2655 uint16_t etype; 2656 2657 /* 2658 * Determine where frame payload starts. 2659 * Jump over vlan headers if already present, 2660 * helpful for QinQ too. 2661 */ 2662 KASSERT(mp->m_len >= ETHER_HDR_LEN, 2663 ("em_txcsum_pullup is not called (eh)?")); 2664 eh = mtod(mp, struct ether_vlan_header *); 2665 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2666 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN, 2667 ("em_txcsum_pullup is not called (evh)?")); 2668 etype = ntohs(eh->evl_proto); 2669 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN; 2670 } else { 2671 etype = ntohs(eh->evl_encap_proto); 2672 ehdrlen = ETHER_HDR_LEN; 2673 } 2674 2675 /* 2676 * We only support TCP/UDP for IPv4 for the moment. 2677 * TODO: Support SCTP too when it hits the tree. 2678 */ 2679 if (etype != ETHERTYPE_IP) 2680 return 0; 2681 2682 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE, 2683 ("em_txcsum_pullup is not called (eh+ip_vhl)?")); 2684 2685 /* NOTE: We could only safely access ip.ip_vhl part */ 2686 ip = (struct ip *)(mp->m_data + ehdrlen); 2687 ip_hlen = ip->ip_hl << 2; 2688 2689 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2690 2691 if (adapter->csum_ehlen == ehdrlen && 2692 adapter->csum_iphlen == ip_hlen && 2693 adapter->csum_flags == csum_flags) { 2694 /* 2695 * Same csum offload context as the previous packets; 2696 * just return. 2697 */ 2698 *txd_upper = adapter->csum_txd_upper; 2699 *txd_lower = adapter->csum_txd_lower; 2700 return 0; 2701 } 2702 2703 /* 2704 * Setup a new csum offload context. 2705 */ 2706 2707 curr_txd = adapter->next_avail_tx_desc; 2708 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 2709 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2710 2711 cmd = 0; 2712 2713 /* Setup of IP header checksum. */ 2714 if (csum_flags & CSUM_IP) { 2715 /* 2716 * Start offset for header checksum calculation. 2717 * End offset for header checksum calculation. 2718 * Offset of place to put the checksum. 2719 */ 2720 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2721 TXD->lower_setup.ip_fields.ipcse = 2722 htole16(ehdrlen + ip_hlen - 1); 2723 TXD->lower_setup.ip_fields.ipcso = 2724 ehdrlen + offsetof(struct ip, ip_sum); 2725 cmd |= E1000_TXD_CMD_IP; 2726 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2727 } 2728 hdr_len = ehdrlen + ip_hlen; 2729 2730 if (csum_flags & CSUM_TCP) { 2731 /* 2732 * Start offset for payload checksum calculation. 2733 * End offset for payload checksum calculation. 2734 * Offset of place to put the checksum. 2735 */ 2736 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2737 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2738 TXD->upper_setup.tcp_fields.tucso = 2739 hdr_len + offsetof(struct tcphdr, th_sum); 2740 cmd |= E1000_TXD_CMD_TCP; 2741 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2742 } else if (csum_flags & CSUM_UDP) { 2743 /* 2744 * Start offset for header checksum calculation. 2745 * End offset for header checksum calculation. 2746 * Offset of place to put the checksum. 2747 */ 2748 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2749 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2750 TXD->upper_setup.tcp_fields.tucso = 2751 hdr_len + offsetof(struct udphdr, uh_sum); 2752 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2753 } 2754 2755 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2756 E1000_TXD_DTYP_D; /* Data descr */ 2757 2758 /* Save the information for this csum offloading context */ 2759 adapter->csum_ehlen = ehdrlen; 2760 adapter->csum_iphlen = ip_hlen; 2761 adapter->csum_flags = csum_flags; 2762 adapter->csum_txd_upper = *txd_upper; 2763 adapter->csum_txd_lower = *txd_lower; 2764 2765 TXD->tcp_seg_setup.data = htole32(0); 2766 TXD->cmd_and_length = 2767 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2768 2769 if (++curr_txd == adapter->num_tx_desc) 2770 curr_txd = 0; 2771 2772 KKASSERT(adapter->num_tx_desc_avail > 0); 2773 adapter->num_tx_desc_avail--; 2774 2775 adapter->next_avail_tx_desc = curr_txd; 2776 return 1; 2777 } 2778 2779 static int 2780 em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0) 2781 { 2782 struct mbuf *m = *m0; 2783 struct ether_header *eh; 2784 int len; 2785 2786 adapter->tx_csum_try_pullup++; 2787 2788 len = ETHER_HDR_LEN + EM_IPVHL_SIZE; 2789 2790 if (__predict_false(!M_WRITABLE(m))) { 2791 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2792 adapter->tx_csum_drop1++; 2793 m_freem(m); 2794 *m0 = NULL; 2795 return ENOBUFS; 2796 } 2797 eh = mtod(m, struct ether_header *); 2798 2799 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2800 len += EVL_ENCAPLEN; 2801 2802 if (m->m_len < len) { 2803 adapter->tx_csum_drop2++; 2804 m_freem(m); 2805 *m0 = NULL; 2806 return ENOBUFS; 2807 } 2808 return 0; 2809 } 2810 2811 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2812 adapter->tx_csum_pullup1++; 2813 m = m_pullup(m, ETHER_HDR_LEN); 2814 if (m == NULL) { 2815 adapter->tx_csum_pullup1_failed++; 2816 *m0 = NULL; 2817 return ENOBUFS; 2818 } 2819 *m0 = m; 2820 } 2821 eh = mtod(m, struct ether_header *); 2822 2823 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2824 len += EVL_ENCAPLEN; 2825 2826 if (m->m_len < len) { 2827 adapter->tx_csum_pullup2++; 2828 m = m_pullup(m, len); 2829 if (m == NULL) { 2830 adapter->tx_csum_pullup2_failed++; 2831 *m0 = NULL; 2832 return ENOBUFS; 2833 } 2834 *m0 = m; 2835 } 2836 return 0; 2837 } 2838 2839 static void 2840 em_txeof(struct adapter *adapter) 2841 { 2842 struct ifnet *ifp = &adapter->arpcom.ac_if; 2843 struct em_buffer *tx_buffer; 2844 int first, num_avail; 2845 2846 if (adapter->tx_dd_head == adapter->tx_dd_tail) 2847 return; 2848 2849 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2850 return; 2851 2852 num_avail = adapter->num_tx_desc_avail; 2853 first = adapter->next_tx_to_clean; 2854 2855 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 2856 struct e1000_tx_desc *tx_desc; 2857 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2858 2859 tx_desc = &adapter->tx_desc_base[dd_idx]; 2860 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2861 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2862 2863 if (++dd_idx == adapter->num_tx_desc) 2864 dd_idx = 0; 2865 2866 while (first != dd_idx) { 2867 logif(pkt_txclean); 2868 2869 num_avail++; 2870 2871 tx_buffer = &adapter->tx_buffer_area[first]; 2872 if (tx_buffer->m_head) { 2873 ifp->if_opackets++; 2874 bus_dmamap_unload(adapter->txtag, 2875 tx_buffer->map); 2876 m_freem(tx_buffer->m_head); 2877 tx_buffer->m_head = NULL; 2878 } 2879 2880 if (++first == adapter->num_tx_desc) 2881 first = 0; 2882 } 2883 } else { 2884 break; 2885 } 2886 } 2887 adapter->next_tx_to_clean = first; 2888 adapter->num_tx_desc_avail = num_avail; 2889 2890 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2891 adapter->tx_dd_head = 0; 2892 adapter->tx_dd_tail = 0; 2893 } 2894 2895 if (!EM_IS_OACTIVE(adapter)) { 2896 ifp->if_flags &= ~IFF_OACTIVE; 2897 2898 /* All clean, turn off the timer */ 2899 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2900 ifp->if_timer = 0; 2901 } 2902 } 2903 2904 static void 2905 em_tx_collect(struct adapter *adapter) 2906 { 2907 struct ifnet *ifp = &adapter->arpcom.ac_if; 2908 struct em_buffer *tx_buffer; 2909 int tdh, first, num_avail, dd_idx = -1; 2910 2911 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2912 return; 2913 2914 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 2915 if (tdh == adapter->next_tx_to_clean) 2916 return; 2917 2918 if (adapter->tx_dd_head != adapter->tx_dd_tail) 2919 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2920 2921 num_avail = adapter->num_tx_desc_avail; 2922 first = adapter->next_tx_to_clean; 2923 2924 while (first != tdh) { 2925 logif(pkt_txclean); 2926 2927 num_avail++; 2928 2929 tx_buffer = &adapter->tx_buffer_area[first]; 2930 if (tx_buffer->m_head) { 2931 ifp->if_opackets++; 2932 bus_dmamap_unload(adapter->txtag, 2933 tx_buffer->map); 2934 m_freem(tx_buffer->m_head); 2935 tx_buffer->m_head = NULL; 2936 } 2937 2938 if (first == dd_idx) { 2939 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2940 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2941 adapter->tx_dd_head = 0; 2942 adapter->tx_dd_tail = 0; 2943 dd_idx = -1; 2944 } else { 2945 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2946 } 2947 } 2948 2949 if (++first == adapter->num_tx_desc) 2950 first = 0; 2951 } 2952 adapter->next_tx_to_clean = first; 2953 adapter->num_tx_desc_avail = num_avail; 2954 2955 if (!EM_IS_OACTIVE(adapter)) { 2956 ifp->if_flags &= ~IFF_OACTIVE; 2957 2958 /* All clean, turn off the timer */ 2959 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2960 ifp->if_timer = 0; 2961 } 2962 } 2963 2964 /* 2965 * When Link is lost sometimes there is work still in the TX ring 2966 * which will result in a watchdog, rather than allow that do an 2967 * attempted cleanup and then reinit here. Note that this has been 2968 * seens mostly with fiber adapters. 2969 */ 2970 static void 2971 em_tx_purge(struct adapter *adapter) 2972 { 2973 struct ifnet *ifp = &adapter->arpcom.ac_if; 2974 2975 if (!adapter->link_active && ifp->if_timer) { 2976 em_tx_collect(adapter); 2977 if (ifp->if_timer) { 2978 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2979 ifp->if_timer = 0; 2980 em_init(adapter); 2981 } 2982 } 2983 } 2984 2985 static int 2986 em_newbuf(struct adapter *adapter, int i, int init) 2987 { 2988 struct mbuf *m; 2989 bus_dma_segment_t seg; 2990 bus_dmamap_t map; 2991 struct em_buffer *rx_buffer; 2992 int error, nseg; 2993 2994 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2995 if (m == NULL) { 2996 adapter->mbuf_cluster_failed++; 2997 if (init) { 2998 if_printf(&adapter->arpcom.ac_if, 2999 "Unable to allocate RX mbuf\n"); 3000 } 3001 return (ENOBUFS); 3002 } 3003 m->m_len = m->m_pkthdr.len = MCLBYTES; 3004 3005 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN) 3006 m_adj(m, ETHER_ALIGN); 3007 3008 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3009 adapter->rx_sparemap, m, 3010 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3011 if (error) { 3012 m_freem(m); 3013 if (init) { 3014 if_printf(&adapter->arpcom.ac_if, 3015 "Unable to load RX mbuf\n"); 3016 } 3017 return (error); 3018 } 3019 3020 rx_buffer = &adapter->rx_buffer_area[i]; 3021 if (rx_buffer->m_head != NULL) 3022 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3023 3024 map = rx_buffer->map; 3025 rx_buffer->map = adapter->rx_sparemap; 3026 adapter->rx_sparemap = map; 3027 3028 rx_buffer->m_head = m; 3029 3030 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3031 return (0); 3032 } 3033 3034 static int 3035 em_create_rx_ring(struct adapter *adapter) 3036 { 3037 device_t dev = adapter->dev; 3038 struct em_buffer *rx_buffer; 3039 int i, error; 3040 3041 adapter->rx_buffer_area = 3042 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3043 M_DEVBUF, M_WAITOK | M_ZERO); 3044 3045 /* 3046 * Create DMA tag for rx buffers 3047 */ 3048 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3049 1, 0, /* alignment, bounds */ 3050 BUS_SPACE_MAXADDR, /* lowaddr */ 3051 BUS_SPACE_MAXADDR, /* highaddr */ 3052 NULL, NULL, /* filter, filterarg */ 3053 MCLBYTES, /* maxsize */ 3054 1, /* nsegments */ 3055 MCLBYTES, /* maxsegsize */ 3056 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3057 &adapter->rxtag); 3058 if (error) { 3059 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3060 kfree(adapter->rx_buffer_area, M_DEVBUF); 3061 adapter->rx_buffer_area = NULL; 3062 return error; 3063 } 3064 3065 /* 3066 * Create spare DMA map for rx buffers 3067 */ 3068 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3069 &adapter->rx_sparemap); 3070 if (error) { 3071 device_printf(dev, "Unable to create spare RX DMA map\n"); 3072 bus_dma_tag_destroy(adapter->rxtag); 3073 kfree(adapter->rx_buffer_area, M_DEVBUF); 3074 adapter->rx_buffer_area = NULL; 3075 return error; 3076 } 3077 3078 /* 3079 * Create DMA maps for rx buffers 3080 */ 3081 for (i = 0; i < adapter->num_rx_desc; i++) { 3082 rx_buffer = &adapter->rx_buffer_area[i]; 3083 3084 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3085 &rx_buffer->map); 3086 if (error) { 3087 device_printf(dev, "Unable to create RX DMA map\n"); 3088 em_destroy_rx_ring(adapter, i); 3089 return error; 3090 } 3091 } 3092 return (0); 3093 } 3094 3095 static int 3096 em_init_rx_ring(struct adapter *adapter) 3097 { 3098 int i, error; 3099 3100 /* Reset descriptor ring */ 3101 bzero(adapter->rx_desc_base, 3102 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3103 3104 /* Allocate new ones. */ 3105 for (i = 0; i < adapter->num_rx_desc; i++) { 3106 error = em_newbuf(adapter, i, 1); 3107 if (error) 3108 return (error); 3109 } 3110 3111 /* Setup our descriptor pointers */ 3112 adapter->next_rx_desc_to_check = 0; 3113 3114 return (0); 3115 } 3116 3117 static void 3118 em_init_rx_unit(struct adapter *adapter) 3119 { 3120 struct ifnet *ifp = &adapter->arpcom.ac_if; 3121 uint64_t bus_addr; 3122 uint32_t rctl; 3123 3124 /* 3125 * Make sure receives are disabled while setting 3126 * up the descriptor ring 3127 */ 3128 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3129 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3130 3131 if (adapter->hw.mac.type >= e1000_82540) { 3132 uint32_t itr; 3133 3134 /* 3135 * Set the interrupt throttling rate. Value is calculated 3136 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3137 */ 3138 if (adapter->int_throttle_ceil) 3139 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3140 else 3141 itr = 0; 3142 em_set_itr(adapter, itr); 3143 } 3144 3145 /* Disable accelerated ackknowledge */ 3146 if (adapter->hw.mac.type == e1000_82574) { 3147 E1000_WRITE_REG(&adapter->hw, 3148 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3149 } 3150 3151 /* Receive Checksum Offload for TCP and UDP */ 3152 if (ifp->if_capenable & IFCAP_RXCSUM) { 3153 uint32_t rxcsum; 3154 3155 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3156 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3157 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3158 } 3159 3160 /* 3161 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3162 * long latencies are observed, like Lenovo X60. This 3163 * change eliminates the problem, but since having positive 3164 * values in RDTR is a known source of problems on other 3165 * platforms another solution is being sought. 3166 */ 3167 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3168 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3169 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3170 } 3171 3172 /* 3173 * Setup the Base and Length of the Rx Descriptor Ring 3174 */ 3175 bus_addr = adapter->rxdma.dma_paddr; 3176 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3177 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3178 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3179 (uint32_t)(bus_addr >> 32)); 3180 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3181 (uint32_t)bus_addr); 3182 3183 /* 3184 * Setup the HW Rx Head and Tail Descriptor Pointers 3185 */ 3186 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3187 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3188 3189 /* Set early receive threshold on appropriate hw */ 3190 if (((adapter->hw.mac.type == e1000_ich9lan) || 3191 (adapter->hw.mac.type == e1000_pch2lan) || 3192 (adapter->hw.mac.type == e1000_ich10lan)) && 3193 (ifp->if_mtu > ETHERMTU)) { 3194 uint32_t rxdctl; 3195 3196 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3197 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3); 3198 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13)); 3199 } 3200 3201 if (adapter->hw.mac.type == e1000_pch2lan) { 3202 if (ifp->if_mtu > ETHERMTU) 3203 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3204 else 3205 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3206 } 3207 3208 /* Setup the Receive Control Register */ 3209 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3210 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3211 E1000_RCTL_RDMTS_HALF | 3212 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3213 3214 /* Make sure VLAN Filters are off */ 3215 rctl &= ~E1000_RCTL_VFE; 3216 3217 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3218 rctl |= E1000_RCTL_SBP; 3219 else 3220 rctl &= ~E1000_RCTL_SBP; 3221 3222 switch (adapter->rx_buffer_len) { 3223 default: 3224 case 2048: 3225 rctl |= E1000_RCTL_SZ_2048; 3226 break; 3227 3228 case 4096: 3229 rctl |= E1000_RCTL_SZ_4096 | 3230 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3231 break; 3232 3233 case 8192: 3234 rctl |= E1000_RCTL_SZ_8192 | 3235 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3236 break; 3237 3238 case 16384: 3239 rctl |= E1000_RCTL_SZ_16384 | 3240 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3241 break; 3242 } 3243 3244 if (ifp->if_mtu > ETHERMTU) 3245 rctl |= E1000_RCTL_LPE; 3246 else 3247 rctl &= ~E1000_RCTL_LPE; 3248 3249 /* Enable Receives */ 3250 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3251 } 3252 3253 static void 3254 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3255 { 3256 struct em_buffer *rx_buffer; 3257 int i; 3258 3259 if (adapter->rx_buffer_area == NULL) 3260 return; 3261 3262 for (i = 0; i < ndesc; i++) { 3263 rx_buffer = &adapter->rx_buffer_area[i]; 3264 3265 KKASSERT(rx_buffer->m_head == NULL); 3266 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3267 } 3268 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3269 bus_dma_tag_destroy(adapter->rxtag); 3270 3271 kfree(adapter->rx_buffer_area, M_DEVBUF); 3272 adapter->rx_buffer_area = NULL; 3273 } 3274 3275 static void 3276 em_rxeof(struct adapter *adapter, int count) 3277 { 3278 struct ifnet *ifp = &adapter->arpcom.ac_if; 3279 uint8_t status, accept_frame = 0, eop = 0; 3280 uint16_t len, desc_len, prev_len_adj; 3281 struct e1000_rx_desc *current_desc; 3282 struct mbuf *mp; 3283 int i; 3284 3285 i = adapter->next_rx_desc_to_check; 3286 current_desc = &adapter->rx_desc_base[i]; 3287 3288 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3289 return; 3290 3291 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3292 struct mbuf *m = NULL; 3293 3294 logif(pkt_receive); 3295 3296 mp = adapter->rx_buffer_area[i].m_head; 3297 3298 /* 3299 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3300 * needs to access the last received byte in the mbuf. 3301 */ 3302 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3303 BUS_DMASYNC_POSTREAD); 3304 3305 accept_frame = 1; 3306 prev_len_adj = 0; 3307 desc_len = le16toh(current_desc->length); 3308 status = current_desc->status; 3309 if (status & E1000_RXD_STAT_EOP) { 3310 count--; 3311 eop = 1; 3312 if (desc_len < ETHER_CRC_LEN) { 3313 len = 0; 3314 prev_len_adj = ETHER_CRC_LEN - desc_len; 3315 } else { 3316 len = desc_len - ETHER_CRC_LEN; 3317 } 3318 } else { 3319 eop = 0; 3320 len = desc_len; 3321 } 3322 3323 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3324 uint8_t last_byte; 3325 uint32_t pkt_len = desc_len; 3326 3327 if (adapter->fmp != NULL) 3328 pkt_len += adapter->fmp->m_pkthdr.len; 3329 3330 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3331 if (TBI_ACCEPT(&adapter->hw, status, 3332 current_desc->errors, pkt_len, last_byte, 3333 adapter->min_frame_size, adapter->max_frame_size)) { 3334 e1000_tbi_adjust_stats_82543(&adapter->hw, 3335 &adapter->stats, pkt_len, 3336 adapter->hw.mac.addr, 3337 adapter->max_frame_size); 3338 if (len > 0) 3339 len--; 3340 } else { 3341 accept_frame = 0; 3342 } 3343 } 3344 3345 if (accept_frame) { 3346 if (em_newbuf(adapter, i, 0) != 0) { 3347 ifp->if_iqdrops++; 3348 goto discard; 3349 } 3350 3351 /* Assign correct length to the current fragment */ 3352 mp->m_len = len; 3353 3354 if (adapter->fmp == NULL) { 3355 mp->m_pkthdr.len = len; 3356 adapter->fmp = mp; /* Store the first mbuf */ 3357 adapter->lmp = mp; 3358 } else { 3359 /* 3360 * Chain mbuf's together 3361 */ 3362 3363 /* 3364 * Adjust length of previous mbuf in chain if 3365 * we received less than 4 bytes in the last 3366 * descriptor. 3367 */ 3368 if (prev_len_adj > 0) { 3369 adapter->lmp->m_len -= prev_len_adj; 3370 adapter->fmp->m_pkthdr.len -= 3371 prev_len_adj; 3372 } 3373 adapter->lmp->m_next = mp; 3374 adapter->lmp = adapter->lmp->m_next; 3375 adapter->fmp->m_pkthdr.len += len; 3376 } 3377 3378 if (eop) { 3379 adapter->fmp->m_pkthdr.rcvif = ifp; 3380 ifp->if_ipackets++; 3381 3382 if (ifp->if_capenable & IFCAP_RXCSUM) { 3383 em_rxcsum(adapter, current_desc, 3384 adapter->fmp); 3385 } 3386 3387 if (status & E1000_RXD_STAT_VP) { 3388 adapter->fmp->m_pkthdr.ether_vlantag = 3389 (le16toh(current_desc->special) & 3390 E1000_RXD_SPC_VLAN_MASK); 3391 adapter->fmp->m_flags |= M_VLANTAG; 3392 } 3393 m = adapter->fmp; 3394 adapter->fmp = NULL; 3395 adapter->lmp = NULL; 3396 } 3397 } else { 3398 ifp->if_ierrors++; 3399 discard: 3400 #ifdef foo 3401 /* Reuse loaded DMA map and just update mbuf chain */ 3402 mp = adapter->rx_buffer_area[i].m_head; 3403 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3404 mp->m_data = mp->m_ext.ext_buf; 3405 mp->m_next = NULL; 3406 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 3407 m_adj(mp, ETHER_ALIGN); 3408 #endif 3409 if (adapter->fmp != NULL) { 3410 m_freem(adapter->fmp); 3411 adapter->fmp = NULL; 3412 adapter->lmp = NULL; 3413 } 3414 m = NULL; 3415 } 3416 3417 /* Zero out the receive descriptors status. */ 3418 current_desc->status = 0; 3419 3420 if (m != NULL) 3421 ifp->if_input(ifp, m); 3422 3423 /* Advance our pointers to the next descriptor. */ 3424 if (++i == adapter->num_rx_desc) 3425 i = 0; 3426 current_desc = &adapter->rx_desc_base[i]; 3427 } 3428 adapter->next_rx_desc_to_check = i; 3429 3430 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3431 if (--i < 0) 3432 i = adapter->num_rx_desc - 1; 3433 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3434 } 3435 3436 static void 3437 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3438 struct mbuf *mp) 3439 { 3440 /* 82543 or newer only */ 3441 if (adapter->hw.mac.type < e1000_82543 || 3442 /* Ignore Checksum bit is set */ 3443 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3444 return; 3445 3446 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3447 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3448 /* IP Checksum Good */ 3449 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3450 } 3451 3452 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3453 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3454 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3455 CSUM_PSEUDO_HDR | 3456 CSUM_FRAG_NOT_CHECKED; 3457 mp->m_pkthdr.csum_data = htons(0xffff); 3458 } 3459 } 3460 3461 static void 3462 em_enable_intr(struct adapter *adapter) 3463 { 3464 uint32_t ims_mask = IMS_ENABLE_MASK; 3465 3466 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3467 3468 #if 0 3469 /* XXX MSIX */ 3470 if (adapter->hw.mac.type == e1000_82574) { 3471 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3472 ims_mask |= EM_MSIX_MASK; 3473 } 3474 #endif 3475 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3476 } 3477 3478 static void 3479 em_disable_intr(struct adapter *adapter) 3480 { 3481 uint32_t clear = 0xffffffff; 3482 3483 /* 3484 * The first version of 82542 had an errata where when link was forced 3485 * it would stay up even up even if the cable was disconnected. 3486 * Sequence errors were used to detect the disconnect and then the 3487 * driver would unforce the link. This code in the in the ISR. For 3488 * this to work correctly the Sequence error interrupt had to be 3489 * enabled all the time. 3490 */ 3491 if (adapter->hw.mac.type == e1000_82542 && 3492 adapter->hw.revision_id == E1000_REVISION_2) 3493 clear &= ~E1000_ICR_RXSEQ; 3494 else if (adapter->hw.mac.type == e1000_82574) 3495 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3496 3497 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3498 3499 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3500 } 3501 3502 /* 3503 * Bit of a misnomer, what this really means is 3504 * to enable OS management of the system... aka 3505 * to disable special hardware management features 3506 */ 3507 static void 3508 em_get_mgmt(struct adapter *adapter) 3509 { 3510 /* A shared code workaround */ 3511 #define E1000_82542_MANC2H E1000_MANC2H 3512 if (adapter->has_manage) { 3513 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3514 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3515 3516 /* disable hardware interception of ARP */ 3517 manc &= ~(E1000_MANC_ARP_EN); 3518 3519 /* enable receiving management packets to the host */ 3520 if (adapter->hw.mac.type >= e1000_82571) { 3521 manc |= E1000_MANC_EN_MNG2HOST; 3522 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3523 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3524 manc2h |= E1000_MNG2HOST_PORT_623; 3525 manc2h |= E1000_MNG2HOST_PORT_664; 3526 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3527 } 3528 3529 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3530 } 3531 } 3532 3533 /* 3534 * Give control back to hardware management 3535 * controller if there is one. 3536 */ 3537 static void 3538 em_rel_mgmt(struct adapter *adapter) 3539 { 3540 if (adapter->has_manage) { 3541 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3542 3543 /* re-enable hardware interception of ARP */ 3544 manc |= E1000_MANC_ARP_EN; 3545 3546 if (adapter->hw.mac.type >= e1000_82571) 3547 manc &= ~E1000_MANC_EN_MNG2HOST; 3548 3549 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3550 } 3551 } 3552 3553 /* 3554 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3555 * For ASF and Pass Through versions of f/w this means that 3556 * the driver is loaded. For AMT version (only with 82573) 3557 * of the f/w this means that the network i/f is open. 3558 */ 3559 static void 3560 em_get_hw_control(struct adapter *adapter) 3561 { 3562 /* Let firmware know the driver has taken over */ 3563 if (adapter->hw.mac.type == e1000_82573) { 3564 uint32_t swsm; 3565 3566 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3567 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3568 swsm | E1000_SWSM_DRV_LOAD); 3569 } else { 3570 uint32_t ctrl_ext; 3571 3572 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3573 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3574 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3575 } 3576 adapter->control_hw = 1; 3577 } 3578 3579 /* 3580 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3581 * For ASF and Pass Through versions of f/w this means that the 3582 * driver is no longer loaded. For AMT version (only with 82573) 3583 * of the f/w this means that the network i/f is closed. 3584 */ 3585 static void 3586 em_rel_hw_control(struct adapter *adapter) 3587 { 3588 if (!adapter->control_hw) 3589 return; 3590 adapter->control_hw = 0; 3591 3592 /* Let firmware taken over control of h/w */ 3593 if (adapter->hw.mac.type == e1000_82573) { 3594 uint32_t swsm; 3595 3596 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3597 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3598 swsm & ~E1000_SWSM_DRV_LOAD); 3599 } else { 3600 uint32_t ctrl_ext; 3601 3602 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3603 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3604 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3605 } 3606 } 3607 3608 static int 3609 em_is_valid_eaddr(const uint8_t *addr) 3610 { 3611 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3612 3613 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3614 return (FALSE); 3615 3616 return (TRUE); 3617 } 3618 3619 /* 3620 * Enable PCI Wake On Lan capability 3621 */ 3622 void 3623 em_enable_wol(device_t dev) 3624 { 3625 uint16_t cap, status; 3626 uint8_t id; 3627 3628 /* First find the capabilities pointer*/ 3629 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3630 3631 /* Read the PM Capabilities */ 3632 id = pci_read_config(dev, cap, 1); 3633 if (id != PCIY_PMG) /* Something wrong */ 3634 return; 3635 3636 /* 3637 * OK, we have the power capabilities, 3638 * so now get the status register 3639 */ 3640 cap += PCIR_POWER_STATUS; 3641 status = pci_read_config(dev, cap, 2); 3642 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3643 pci_write_config(dev, cap, status, 2); 3644 } 3645 3646 3647 /* 3648 * 82544 Coexistence issue workaround. 3649 * There are 2 issues. 3650 * 1. Transmit Hang issue. 3651 * To detect this issue, following equation can be used... 3652 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3653 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3654 * 3655 * 2. DAC issue. 3656 * To detect this issue, following equation can be used... 3657 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3658 * If SUM[3:0] is in between 9 to c, we will have this issue. 3659 * 3660 * WORKAROUND: 3661 * Make sure we do not have ending address 3662 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3663 */ 3664 static uint32_t 3665 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3666 { 3667 uint32_t safe_terminator; 3668 3669 /* 3670 * Since issue is sensitive to length and address. 3671 * Let us first check the address... 3672 */ 3673 if (length <= 4) { 3674 desc_array->descriptor[0].address = address; 3675 desc_array->descriptor[0].length = length; 3676 desc_array->elements = 1; 3677 return (desc_array->elements); 3678 } 3679 3680 safe_terminator = 3681 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3682 3683 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3684 if (safe_terminator == 0 || 3685 (safe_terminator > 4 && safe_terminator < 9) || 3686 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3687 desc_array->descriptor[0].address = address; 3688 desc_array->descriptor[0].length = length; 3689 desc_array->elements = 1; 3690 return (desc_array->elements); 3691 } 3692 3693 desc_array->descriptor[0].address = address; 3694 desc_array->descriptor[0].length = length - 4; 3695 desc_array->descriptor[1].address = address + (length - 4); 3696 desc_array->descriptor[1].length = 4; 3697 desc_array->elements = 2; 3698 return (desc_array->elements); 3699 } 3700 3701 static void 3702 em_update_stats(struct adapter *adapter) 3703 { 3704 struct ifnet *ifp = &adapter->arpcom.ac_if; 3705 3706 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3707 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3708 adapter->stats.symerrs += 3709 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3710 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3711 } 3712 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3713 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3714 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3715 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3716 3717 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3718 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3719 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3720 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3721 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3722 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3723 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3724 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3725 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3726 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3727 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3728 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3729 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3730 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3731 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3732 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3733 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3734 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3735 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3736 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3737 3738 /* For the 64-bit byte counters the low dword must be read first. */ 3739 /* Both registers clear on the read of the high dword */ 3740 3741 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3742 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3743 3744 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3745 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3746 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3747 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3748 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3749 3750 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3751 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3752 3753 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3754 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3755 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3756 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3757 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3758 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3759 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3760 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3761 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3762 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3763 3764 if (adapter->hw.mac.type >= e1000_82543) { 3765 adapter->stats.algnerrc += 3766 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3767 adapter->stats.rxerrc += 3768 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3769 adapter->stats.tncrs += 3770 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3771 adapter->stats.cexterr += 3772 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3773 adapter->stats.tsctc += 3774 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3775 adapter->stats.tsctfc += 3776 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3777 } 3778 3779 ifp->if_collisions = adapter->stats.colc; 3780 3781 /* Rx Errors */ 3782 ifp->if_ierrors = 3783 adapter->dropped_pkts + adapter->stats.rxerrc + 3784 adapter->stats.crcerrs + adapter->stats.algnerrc + 3785 adapter->stats.ruc + adapter->stats.roc + 3786 adapter->stats.mpc + adapter->stats.cexterr; 3787 3788 /* Tx Errors */ 3789 ifp->if_oerrors = 3790 adapter->stats.ecol + adapter->stats.latecol + 3791 adapter->watchdog_events; 3792 } 3793 3794 static void 3795 em_print_debug_info(struct adapter *adapter) 3796 { 3797 device_t dev = adapter->dev; 3798 uint8_t *hw_addr = adapter->hw.hw_addr; 3799 3800 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3801 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3802 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3803 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3804 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3805 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3806 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3807 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3808 adapter->hw.fc.high_water, 3809 adapter->hw.fc.low_water); 3810 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3811 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3812 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3813 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3814 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3815 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3816 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3817 (long long)adapter->tx_fifo_wrk_cnt, 3818 (long long)adapter->tx_fifo_reset_cnt); 3819 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3820 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3821 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3822 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3823 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3824 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3825 device_printf(dev, "Num Tx descriptors avail = %d\n", 3826 adapter->num_tx_desc_avail); 3827 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3828 adapter->no_tx_desc_avail1); 3829 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3830 adapter->no_tx_desc_avail2); 3831 device_printf(dev, "Std mbuf failed = %ld\n", 3832 adapter->mbuf_alloc_failed); 3833 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3834 adapter->mbuf_cluster_failed); 3835 device_printf(dev, "Driver dropped packets = %ld\n", 3836 adapter->dropped_pkts); 3837 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3838 adapter->no_tx_dma_setup); 3839 3840 device_printf(dev, "TXCSUM try pullup = %lu\n", 3841 adapter->tx_csum_try_pullup); 3842 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n", 3843 adapter->tx_csum_pullup1); 3844 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n", 3845 adapter->tx_csum_pullup1_failed); 3846 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n", 3847 adapter->tx_csum_pullup2); 3848 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n", 3849 adapter->tx_csum_pullup2_failed); 3850 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n", 3851 adapter->tx_csum_drop1); 3852 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n", 3853 adapter->tx_csum_drop2); 3854 } 3855 3856 static void 3857 em_print_hw_stats(struct adapter *adapter) 3858 { 3859 device_t dev = adapter->dev; 3860 3861 device_printf(dev, "Excessive collisions = %lld\n", 3862 (long long)adapter->stats.ecol); 3863 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3864 device_printf(dev, "Symbol errors = %lld\n", 3865 (long long)adapter->stats.symerrs); 3866 #endif 3867 device_printf(dev, "Sequence errors = %lld\n", 3868 (long long)adapter->stats.sec); 3869 device_printf(dev, "Defer count = %lld\n", 3870 (long long)adapter->stats.dc); 3871 device_printf(dev, "Missed Packets = %lld\n", 3872 (long long)adapter->stats.mpc); 3873 device_printf(dev, "Receive No Buffers = %lld\n", 3874 (long long)adapter->stats.rnbc); 3875 /* RLEC is inaccurate on some hardware, calculate our own. */ 3876 device_printf(dev, "Receive Length Errors = %lld\n", 3877 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 3878 device_printf(dev, "Receive errors = %lld\n", 3879 (long long)adapter->stats.rxerrc); 3880 device_printf(dev, "Crc errors = %lld\n", 3881 (long long)adapter->stats.crcerrs); 3882 device_printf(dev, "Alignment errors = %lld\n", 3883 (long long)adapter->stats.algnerrc); 3884 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3885 (long long)adapter->stats.cexterr); 3886 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 3887 device_printf(dev, "watchdog timeouts = %ld\n", 3888 adapter->watchdog_events); 3889 device_printf(dev, "XON Rcvd = %lld\n", 3890 (long long)adapter->stats.xonrxc); 3891 device_printf(dev, "XON Xmtd = %lld\n", 3892 (long long)adapter->stats.xontxc); 3893 device_printf(dev, "XOFF Rcvd = %lld\n", 3894 (long long)adapter->stats.xoffrxc); 3895 device_printf(dev, "XOFF Xmtd = %lld\n", 3896 (long long)adapter->stats.xofftxc); 3897 device_printf(dev, "Good Packets Rcvd = %lld\n", 3898 (long long)adapter->stats.gprc); 3899 device_printf(dev, "Good Packets Xmtd = %lld\n", 3900 (long long)adapter->stats.gptc); 3901 } 3902 3903 static void 3904 em_print_nvm_info(struct adapter *adapter) 3905 { 3906 uint16_t eeprom_data; 3907 int i, j, row = 0; 3908 3909 /* Its a bit crude, but it gets the job done */ 3910 kprintf("\nInterface EEPROM Dump:\n"); 3911 kprintf("Offset\n0x0000 "); 3912 for (i = 0, j = 0; i < 32; i++, j++) { 3913 if (j == 8) { /* Make the offset block */ 3914 j = 0; ++row; 3915 kprintf("\n0x00%x0 ",row); 3916 } 3917 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 3918 kprintf("%04x ", eeprom_data); 3919 } 3920 kprintf("\n"); 3921 } 3922 3923 static int 3924 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3925 { 3926 struct adapter *adapter; 3927 struct ifnet *ifp; 3928 int error, result; 3929 3930 result = -1; 3931 error = sysctl_handle_int(oidp, &result, 0, req); 3932 if (error || !req->newptr) 3933 return (error); 3934 3935 adapter = (struct adapter *)arg1; 3936 ifp = &adapter->arpcom.ac_if; 3937 3938 lwkt_serialize_enter(ifp->if_serializer); 3939 3940 if (result == 1) 3941 em_print_debug_info(adapter); 3942 3943 /* 3944 * This value will cause a hex dump of the 3945 * first 32 16-bit words of the EEPROM to 3946 * the screen. 3947 */ 3948 if (result == 2) 3949 em_print_nvm_info(adapter); 3950 3951 lwkt_serialize_exit(ifp->if_serializer); 3952 3953 return (error); 3954 } 3955 3956 static int 3957 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3958 { 3959 int error, result; 3960 3961 result = -1; 3962 error = sysctl_handle_int(oidp, &result, 0, req); 3963 if (error || !req->newptr) 3964 return (error); 3965 3966 if (result == 1) { 3967 struct adapter *adapter = (struct adapter *)arg1; 3968 struct ifnet *ifp = &adapter->arpcom.ac_if; 3969 3970 lwkt_serialize_enter(ifp->if_serializer); 3971 em_print_hw_stats(adapter); 3972 lwkt_serialize_exit(ifp->if_serializer); 3973 } 3974 return (error); 3975 } 3976 3977 static void 3978 em_add_sysctl(struct adapter *adapter) 3979 { 3980 sysctl_ctx_init(&adapter->sysctl_ctx); 3981 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 3982 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3983 device_get_nameunit(adapter->dev), 3984 CTLFLAG_RD, 0, ""); 3985 if (adapter->sysctl_tree == NULL) { 3986 device_printf(adapter->dev, "can't add sysctl node\n"); 3987 } else { 3988 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 3989 SYSCTL_CHILDREN(adapter->sysctl_tree), 3990 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 3991 em_sysctl_debug_info, "I", "Debug Information"); 3992 3993 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 3994 SYSCTL_CHILDREN(adapter->sysctl_tree), 3995 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 3996 em_sysctl_stats, "I", "Statistics"); 3997 3998 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 3999 SYSCTL_CHILDREN(adapter->sysctl_tree), 4000 OID_AUTO, "rxd", CTLFLAG_RD, 4001 &adapter->num_rx_desc, 0, NULL); 4002 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4003 SYSCTL_CHILDREN(adapter->sysctl_tree), 4004 OID_AUTO, "txd", CTLFLAG_RD, 4005 &adapter->num_tx_desc, 0, NULL); 4006 4007 if (adapter->hw.mac.type >= e1000_82540) { 4008 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4009 SYSCTL_CHILDREN(adapter->sysctl_tree), 4010 OID_AUTO, "int_throttle_ceil", 4011 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4012 em_sysctl_int_throttle, "I", 4013 "interrupt throttling rate"); 4014 } 4015 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4016 SYSCTL_CHILDREN(adapter->sysctl_tree), 4017 OID_AUTO, "int_tx_nsegs", 4018 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4019 em_sysctl_int_tx_nsegs, "I", 4020 "# segments per TX interrupt"); 4021 } 4022 } 4023 4024 static int 4025 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4026 { 4027 struct adapter *adapter = (void *)arg1; 4028 struct ifnet *ifp = &adapter->arpcom.ac_if; 4029 int error, throttle; 4030 4031 throttle = adapter->int_throttle_ceil; 4032 error = sysctl_handle_int(oidp, &throttle, 0, req); 4033 if (error || req->newptr == NULL) 4034 return error; 4035 if (throttle < 0 || throttle > 1000000000 / 256) 4036 return EINVAL; 4037 4038 if (throttle) { 4039 /* 4040 * Set the interrupt throttling rate in 256ns increments, 4041 * recalculate sysctl value assignment to get exact frequency. 4042 */ 4043 throttle = 1000000000 / 256 / throttle; 4044 4045 /* Upper 16bits of ITR is reserved and should be zero */ 4046 if (throttle & 0xffff0000) 4047 return EINVAL; 4048 } 4049 4050 lwkt_serialize_enter(ifp->if_serializer); 4051 4052 if (throttle) 4053 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4054 else 4055 adapter->int_throttle_ceil = 0; 4056 4057 if (ifp->if_flags & IFF_RUNNING) 4058 em_set_itr(adapter, throttle); 4059 4060 lwkt_serialize_exit(ifp->if_serializer); 4061 4062 if (bootverbose) { 4063 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4064 adapter->int_throttle_ceil); 4065 } 4066 return 0; 4067 } 4068 4069 static int 4070 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4071 { 4072 struct adapter *adapter = (void *)arg1; 4073 struct ifnet *ifp = &adapter->arpcom.ac_if; 4074 int error, segs; 4075 4076 segs = adapter->tx_int_nsegs; 4077 error = sysctl_handle_int(oidp, &segs, 0, req); 4078 if (error || req->newptr == NULL) 4079 return error; 4080 if (segs <= 0) 4081 return EINVAL; 4082 4083 lwkt_serialize_enter(ifp->if_serializer); 4084 4085 /* 4086 * Don't allow int_tx_nsegs to become: 4087 * o Less the oact_tx_desc 4088 * o Too large that no TX desc will cause TX interrupt to 4089 * be generated (OACTIVE will never recover) 4090 * o Too small that will cause tx_dd[] overflow 4091 */ 4092 if (segs < adapter->oact_tx_desc || 4093 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4094 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4095 error = EINVAL; 4096 } else { 4097 error = 0; 4098 adapter->tx_int_nsegs = segs; 4099 } 4100 4101 lwkt_serialize_exit(ifp->if_serializer); 4102 4103 return error; 4104 } 4105 4106 static void 4107 em_set_itr(struct adapter *adapter, uint32_t itr) 4108 { 4109 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4110 if (adapter->hw.mac.type == e1000_82574) { 4111 int i; 4112 4113 /* 4114 * When using MSIX interrupts we need to 4115 * throttle using the EITR register 4116 */ 4117 for (i = 0; i < 4; ++i) { 4118 E1000_WRITE_REG(&adapter->hw, 4119 E1000_EITR_82574(i), itr); 4120 } 4121 } 4122 } 4123 4124 /* 4125 * Disable the L0s, Errata #20 4126 */ 4127 static void 4128 em_disable_aspm(struct adapter *adapter) 4129 { 4130 uint16_t link_cap, link_ctrl; 4131 uint8_t pcie_ptr, reg; 4132 device_t dev = adapter->dev; 4133 4134 switch (adapter->hw.mac.type) { 4135 case e1000_82573: 4136 case e1000_82574: 4137 case e1000_82583: 4138 break; 4139 4140 default: 4141 return; 4142 } 4143 4144 pcie_ptr = pci_get_pciecap_ptr(dev); 4145 if (pcie_ptr == 0) 4146 return; 4147 4148 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4149 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4150 return; 4151 4152 if (bootverbose) 4153 if_printf(&adapter->arpcom.ac_if, "disable L0s\n"); 4154 4155 reg = pcie_ptr + PCIER_LINKCTRL; 4156 link_ctrl = pci_read_config(dev, reg, 2); 4157 link_ctrl &= ~PCIEM_LNKCTL_ASPM_L0S; 4158 pci_write_config(dev, reg, link_ctrl, 2); 4159 } 4160