1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2015, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - We must call lwkt_serialize_handler_enable() prior to enabling the 71 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 72 * the hardware interrupt in order to avoid handler execution races from 73 * scheduled interrupt threads. 74 */ 75 76 #include "opt_ifpoll.h" 77 78 #include <sys/param.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/interrupt.h> 82 #include <sys/kernel.h> 83 #include <sys/ktr.h> 84 #include <sys/malloc.h> 85 #include <sys/mbuf.h> 86 #include <sys/proc.h> 87 #include <sys/rman.h> 88 #include <sys/serialize.h> 89 #include <sys/socket.h> 90 #include <sys/sockio.h> 91 #include <sys/sysctl.h> 92 #include <sys/systm.h> 93 94 #include <net/bpf.h> 95 #include <net/ethernet.h> 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_poll.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <netinet/ip.h> 106 #include <netinet/tcp.h> 107 #include <netinet/udp.h> 108 109 #include <bus/pci/pcivar.h> 110 #include <bus/pci/pcireg.h> 111 112 #include <dev/netif/ig_hal/e1000_api.h> 113 #include <dev/netif/ig_hal/e1000_82571.h> 114 #include <dev/netif/ig_hal/e1000_dragonfly.h> 115 #include <dev/netif/em/if_em.h> 116 117 #define DEBUG_HW 0 118 119 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 120 #define EM_VER " 7.6.2" 121 122 #define _EM_DEVICE(id, ret) \ 123 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 124 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 125 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 126 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 127 128 static const struct em_vendor_info em_vendor_info_array[] = { 129 EM_DEVICE(82540EM), 130 EM_DEVICE(82540EM_LOM), 131 EM_DEVICE(82540EP), 132 EM_DEVICE(82540EP_LOM), 133 EM_DEVICE(82540EP_LP), 134 135 EM_DEVICE(82541EI), 136 EM_DEVICE(82541ER), 137 EM_DEVICE(82541ER_LOM), 138 EM_DEVICE(82541EI_MOBILE), 139 EM_DEVICE(82541GI), 140 EM_DEVICE(82541GI_LF), 141 EM_DEVICE(82541GI_MOBILE), 142 143 EM_DEVICE(82542), 144 145 EM_DEVICE(82543GC_FIBER), 146 EM_DEVICE(82543GC_COPPER), 147 148 EM_DEVICE(82544EI_COPPER), 149 EM_DEVICE(82544EI_FIBER), 150 EM_DEVICE(82544GC_COPPER), 151 EM_DEVICE(82544GC_LOM), 152 153 EM_DEVICE(82545EM_COPPER), 154 EM_DEVICE(82545EM_FIBER), 155 EM_DEVICE(82545GM_COPPER), 156 EM_DEVICE(82545GM_FIBER), 157 EM_DEVICE(82545GM_SERDES), 158 159 EM_DEVICE(82546EB_COPPER), 160 EM_DEVICE(82546EB_FIBER), 161 EM_DEVICE(82546EB_QUAD_COPPER), 162 EM_DEVICE(82546GB_COPPER), 163 EM_DEVICE(82546GB_FIBER), 164 EM_DEVICE(82546GB_SERDES), 165 EM_DEVICE(82546GB_PCIE), 166 EM_DEVICE(82546GB_QUAD_COPPER), 167 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 168 169 EM_DEVICE(82547EI), 170 EM_DEVICE(82547EI_MOBILE), 171 EM_DEVICE(82547GI), 172 173 EM_EMX_DEVICE(82571EB_COPPER), 174 EM_EMX_DEVICE(82571EB_FIBER), 175 EM_EMX_DEVICE(82571EB_SERDES), 176 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 177 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 178 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 179 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 180 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 181 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 182 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 183 184 EM_EMX_DEVICE(82572EI_COPPER), 185 EM_EMX_DEVICE(82572EI_FIBER), 186 EM_EMX_DEVICE(82572EI_SERDES), 187 EM_EMX_DEVICE(82572EI), 188 189 EM_EMX_DEVICE(82573E), 190 EM_EMX_DEVICE(82573E_IAMT), 191 EM_EMX_DEVICE(82573L), 192 193 EM_DEVICE(82583V), 194 195 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 196 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 197 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 198 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 199 200 EM_DEVICE(ICH8_IGP_M_AMT), 201 EM_DEVICE(ICH8_IGP_AMT), 202 EM_DEVICE(ICH8_IGP_C), 203 EM_DEVICE(ICH8_IFE), 204 EM_DEVICE(ICH8_IFE_GT), 205 EM_DEVICE(ICH8_IFE_G), 206 EM_DEVICE(ICH8_IGP_M), 207 EM_DEVICE(ICH8_82567V_3), 208 209 EM_DEVICE(ICH9_IGP_M_AMT), 210 EM_DEVICE(ICH9_IGP_AMT), 211 EM_DEVICE(ICH9_IGP_C), 212 EM_DEVICE(ICH9_IGP_M), 213 EM_DEVICE(ICH9_IGP_M_V), 214 EM_DEVICE(ICH9_IFE), 215 EM_DEVICE(ICH9_IFE_GT), 216 EM_DEVICE(ICH9_IFE_G), 217 EM_DEVICE(ICH9_BM), 218 219 EM_EMX_DEVICE(82574L), 220 EM_EMX_DEVICE(82574LA), 221 222 EM_DEVICE(ICH10_R_BM_LM), 223 EM_DEVICE(ICH10_R_BM_LF), 224 EM_DEVICE(ICH10_R_BM_V), 225 EM_DEVICE(ICH10_D_BM_LM), 226 EM_DEVICE(ICH10_D_BM_LF), 227 EM_DEVICE(ICH10_D_BM_V), 228 229 EM_DEVICE(PCH_M_HV_LM), 230 EM_DEVICE(PCH_M_HV_LC), 231 EM_DEVICE(PCH_D_HV_DM), 232 EM_DEVICE(PCH_D_HV_DC), 233 234 EM_DEVICE(PCH2_LV_LM), 235 EM_DEVICE(PCH2_LV_V), 236 237 EM_EMX_DEVICE(PCH_LPT_I217_LM), 238 EM_EMX_DEVICE(PCH_LPT_I217_V), 239 EM_EMX_DEVICE(PCH_LPTLP_I218_LM), 240 EM_EMX_DEVICE(PCH_LPTLP_I218_V), 241 EM_EMX_DEVICE(PCH_I218_LM2), 242 EM_EMX_DEVICE(PCH_I218_V2), 243 EM_EMX_DEVICE(PCH_I218_LM3), 244 EM_EMX_DEVICE(PCH_I218_V3), 245 EM_EMX_DEVICE(PCH_SPT_I219_LM), 246 EM_EMX_DEVICE(PCH_SPT_I219_V), 247 EM_EMX_DEVICE(PCH_SPT_I219_LM2), 248 EM_EMX_DEVICE(PCH_SPT_I219_V2), 249 EM_EMX_DEVICE(PCH_LBG_I219_LM3), 250 EM_EMX_DEVICE(PCH_SPT_I219_LM4), 251 EM_EMX_DEVICE(PCH_SPT_I219_V4), 252 EM_EMX_DEVICE(PCH_SPT_I219_LM5), 253 EM_EMX_DEVICE(PCH_SPT_I219_V5), 254 EM_EMX_DEVICE(PCH_CNP_I219_LM6), 255 EM_EMX_DEVICE(PCH_CNP_I219_V6), 256 EM_EMX_DEVICE(PCH_CNP_I219_LM7), 257 EM_EMX_DEVICE(PCH_CNP_I219_V7), 258 EM_EMX_DEVICE(PCH_CNP_I219_LM8), 259 EM_EMX_DEVICE(PCH_CNP_I219_V8), 260 EM_EMX_DEVICE(PCH_CNP_I219_LM9), 261 EM_EMX_DEVICE(PCH_CNP_I219_V9), 262 EM_EMX_DEVICE(PCH_CNP_I219_LM10), 263 EM_EMX_DEVICE(PCH_CNP_I219_V10), 264 EM_EMX_DEVICE(PCH_CNP_I219_LM11), 265 EM_EMX_DEVICE(PCH_CNP_I219_V11), 266 EM_EMX_DEVICE(PCH_CNP_I219_LM12), 267 EM_EMX_DEVICE(PCH_CNP_I219_V12), 268 EM_EMX_DEVICE(PCH_CNP_I219_LM13), 269 EM_EMX_DEVICE(PCH_CNP_I219_V13), 270 EM_EMX_DEVICE(PCH_CNP_I219_LM14), 271 EM_EMX_DEVICE(PCH_CNP_I219_V14), 272 273 /* required last entry */ 274 EM_DEVICE_NULL 275 }; 276 277 static int em_probe(device_t); 278 static int em_attach(device_t); 279 static int em_detach(device_t); 280 static int em_shutdown(device_t); 281 static int em_suspend(device_t); 282 static int em_resume(device_t); 283 284 static void em_init(void *); 285 static void em_stop(struct adapter *); 286 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 287 static void em_start(struct ifnet *, struct ifaltq_subque *); 288 #ifdef IFPOLL_ENABLE 289 static void em_npoll(struct ifnet *, struct ifpoll_info *); 290 static void em_npoll_compat(struct ifnet *, void *, int); 291 #endif 292 static void em_watchdog(struct ifnet *); 293 static void em_media_status(struct ifnet *, struct ifmediareq *); 294 static int em_media_change(struct ifnet *); 295 static void em_timer(void *); 296 297 static void em_intr(void *); 298 static void em_intr_mask(void *); 299 static void em_intr_body(struct adapter *, boolean_t); 300 static void em_rxeof(struct adapter *, int); 301 static void em_txeof(struct adapter *); 302 static void em_tx_collect(struct adapter *, boolean_t); 303 static void em_tx_purge(struct adapter *); 304 static void em_txgc_timer(void *); 305 static void em_enable_intr(struct adapter *); 306 static void em_disable_intr(struct adapter *); 307 308 static int em_dma_malloc(struct adapter *, bus_size_t, 309 struct em_dma_alloc *); 310 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 311 static void em_init_tx_ring(struct adapter *); 312 static int em_init_rx_ring(struct adapter *); 313 static int em_create_tx_ring(struct adapter *); 314 static int em_create_rx_ring(struct adapter *); 315 static void em_destroy_tx_ring(struct adapter *, int); 316 static void em_destroy_rx_ring(struct adapter *, int); 317 static int em_newbuf(struct adapter *, int, int); 318 static int em_encap(struct adapter *, struct mbuf **, int *, int *); 319 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 320 struct mbuf *); 321 static int em_txcsum(struct adapter *, struct mbuf *, 322 uint32_t *, uint32_t *); 323 static int em_tso_pullup(struct adapter *, struct mbuf **); 324 static int em_tso_setup(struct adapter *, struct mbuf *, 325 uint32_t *, uint32_t *); 326 327 static int em_get_hw_info(struct adapter *); 328 static int em_is_valid_eaddr(const uint8_t *); 329 static int em_alloc_pci_res(struct adapter *); 330 static void em_free_pci_res(struct adapter *); 331 static int em_reset(struct adapter *); 332 static void em_setup_ifp(struct adapter *); 333 static void em_init_tx_unit(struct adapter *); 334 static void em_init_rx_unit(struct adapter *); 335 static void em_update_stats(struct adapter *); 336 static void em_set_promisc(struct adapter *); 337 static void em_disable_promisc(struct adapter *); 338 static void em_set_multi(struct adapter *); 339 static void em_update_link_status(struct adapter *); 340 static void em_smartspeed(struct adapter *); 341 static void em_set_itr(struct adapter *, uint32_t); 342 static void em_disable_aspm(struct adapter *); 343 static void em_flush_tx_ring(struct adapter *); 344 static void em_flush_rx_ring(struct adapter *); 345 static void em_flush_txrx_ring(struct adapter *); 346 347 /* Hardware workarounds */ 348 static int em_82547_fifo_workaround(struct adapter *, int); 349 static void em_82547_update_fifo_head(struct adapter *, int); 350 static int em_82547_tx_fifo_reset(struct adapter *); 351 static void em_82547_move_tail(void *); 352 static void em_82547_move_tail_serialized(struct adapter *); 353 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 354 355 static void em_print_debug_info(struct adapter *); 356 static void em_print_nvm_info(struct adapter *); 357 static void em_print_hw_stats(struct adapter *); 358 359 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 360 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 361 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 362 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 363 static void em_add_sysctl(struct adapter *adapter); 364 365 /* Management and WOL Support */ 366 static void em_get_mgmt(struct adapter *); 367 static void em_rel_mgmt(struct adapter *); 368 static void em_get_hw_control(struct adapter *); 369 static void em_rel_hw_control(struct adapter *); 370 static void em_enable_wol(device_t); 371 372 static device_method_t em_methods[] = { 373 /* Device interface */ 374 DEVMETHOD(device_probe, em_probe), 375 DEVMETHOD(device_attach, em_attach), 376 DEVMETHOD(device_detach, em_detach), 377 DEVMETHOD(device_shutdown, em_shutdown), 378 DEVMETHOD(device_suspend, em_suspend), 379 DEVMETHOD(device_resume, em_resume), 380 DEVMETHOD_END 381 }; 382 383 static driver_t em_driver = { 384 "em", 385 em_methods, 386 sizeof(struct adapter), 387 }; 388 389 static devclass_t em_devclass; 390 391 DECLARE_DUMMY_MODULE(if_em); 392 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 393 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 394 395 /* 396 * Tunables 397 */ 398 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 399 static int em_rxd = EM_DEFAULT_RXD; 400 static int em_txd = EM_DEFAULT_TXD; 401 static int em_smart_pwr_down = 0; 402 403 /* Controls whether promiscuous also shows bad packets */ 404 static int em_debug_sbp = FALSE; 405 406 static int em_82573_workaround = 1; 407 static int em_msi_enable = 1; 408 409 static char em_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_NONE; 410 411 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 412 TUNABLE_INT("hw.em.rxd", &em_rxd); 413 TUNABLE_INT("hw.em.txd", &em_txd); 414 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 415 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 416 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 417 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 418 TUNABLE_STR("hw.em.flow_ctrl", em_flowctrl, sizeof(em_flowctrl)); 419 420 /* Global used in WOL setup with multiport cards */ 421 static int em_global_quad_port_a = 0; 422 423 /* Set this to one to display debug statistics */ 424 static int em_display_debug_stats = 0; 425 426 #if !defined(KTR_IF_EM) 427 #define KTR_IF_EM KTR_ALL 428 #endif 429 KTR_INFO_MASTER(if_em); 430 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 431 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 432 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 433 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 434 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 435 #define logif(name) KTR_LOG(if_em_ ## name) 436 437 static __inline void 438 em_tx_intr(struct adapter *adapter) 439 { 440 struct ifnet *ifp = &adapter->arpcom.ac_if; 441 442 em_txeof(adapter); 443 if (!ifq_is_empty(&ifp->if_snd)) 444 if_devstart(ifp); 445 } 446 447 static __inline void 448 em_free_txbuffer(struct adapter *adapter, struct em_buffer *tx_buffer) 449 { 450 451 KKASSERT(tx_buffer->m_head != NULL); 452 KKASSERT(adapter->tx_nmbuf > 0); 453 adapter->tx_nmbuf--; 454 455 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 456 m_freem(tx_buffer->m_head); 457 tx_buffer->m_head = NULL; 458 } 459 460 static __inline void 461 em_try_txgc(struct adapter *adapter, int dec) 462 { 463 464 if (adapter->tx_running > 0) { 465 adapter->tx_running -= dec; 466 if (adapter->tx_running <= 0 && adapter->tx_nmbuf && 467 adapter->num_tx_desc_avail < adapter->num_tx_desc && 468 adapter->num_tx_desc_avail + adapter->tx_int_nsegs > 469 adapter->num_tx_desc) 470 em_tx_collect(adapter, TRUE); 471 } 472 } 473 474 static void 475 em_txgc_timer(void *xadapter) 476 { 477 struct adapter *adapter = xadapter; 478 struct ifnet *ifp = &adapter->arpcom.ac_if; 479 480 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP | IFF_NPOLLING)) != 481 (IFF_RUNNING | IFF_UP)) 482 return; 483 484 if (!lwkt_serialize_try(ifp->if_serializer)) 485 goto done; 486 487 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP | IFF_NPOLLING)) != 488 (IFF_RUNNING | IFF_UP)) { 489 lwkt_serialize_exit(ifp->if_serializer); 490 return; 491 } 492 em_try_txgc(adapter, EM_TX_RUNNING_DEC); 493 494 lwkt_serialize_exit(ifp->if_serializer); 495 done: 496 callout_reset(&adapter->tx_gc_timer, 1, em_txgc_timer, adapter); 497 } 498 499 static int 500 em_probe(device_t dev) 501 { 502 const struct em_vendor_info *ent; 503 uint16_t vid, did; 504 505 vid = pci_get_vendor(dev); 506 did = pci_get_device(dev); 507 508 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 509 if (vid == ent->vendor_id && did == ent->device_id) { 510 device_set_desc(dev, ent->desc); 511 device_set_async_attach(dev, TRUE); 512 return (ent->ret); 513 } 514 } 515 return (ENXIO); 516 } 517 518 static int 519 em_attach(device_t dev) 520 { 521 struct adapter *adapter = device_get_softc(dev); 522 struct ifnet *ifp = &adapter->arpcom.ac_if; 523 int tsize, rsize; 524 int error = 0; 525 int cap; 526 uint16_t eeprom_data, device_id, apme_mask; 527 driver_intr_t *intr_func; 528 char flowctrl[IFM_ETH_FC_STRLEN]; 529 530 adapter->dev = adapter->osdep.dev = dev; 531 532 /* 533 * Some versions of I219 only have PCI AF. 534 */ 535 if (pci_is_pcie(dev) || pci_find_extcap(dev, PCIY_PCIAF, &cap) == 0) 536 adapter->flags |= EM_FLAG_GEN2; 537 538 callout_init_mp(&adapter->timer); 539 callout_init_mp(&adapter->tx_fifo_timer); 540 callout_init_mp(&adapter->tx_gc_timer); 541 542 ifmedia_init(&adapter->media, IFM_IMASK | IFM_ETH_FCMASK, 543 em_media_change, em_media_status); 544 545 /* Determine hardware and mac info */ 546 error = em_get_hw_info(adapter); 547 if (error) { 548 device_printf(dev, "Identify hardware failed\n"); 549 goto fail; 550 } 551 552 /* Setup PCI resources */ 553 error = em_alloc_pci_res(adapter); 554 if (error) { 555 device_printf(dev, "Allocation of PCI resources failed\n"); 556 goto fail; 557 } 558 559 /* 560 * For ICH8 and family we need to map the flash memory, 561 * and this must happen after the MAC is identified. 562 * 563 * (SPT does not map the flash with a separate BAR) 564 */ 565 if (adapter->hw.mac.type == e1000_ich8lan || 566 adapter->hw.mac.type == e1000_ich9lan || 567 adapter->hw.mac.type == e1000_ich10lan || 568 adapter->hw.mac.type == e1000_pchlan || 569 adapter->hw.mac.type == e1000_pch2lan || 570 adapter->hw.mac.type == e1000_pch_lpt) { 571 adapter->flash_rid = EM_BAR_FLASH; 572 573 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 574 &adapter->flash_rid, RF_ACTIVE); 575 if (adapter->flash == NULL) { 576 device_printf(dev, "Mapping of Flash failed\n"); 577 error = ENXIO; 578 goto fail; 579 } 580 adapter->osdep.flash_bus_space_tag = 581 rman_get_bustag(adapter->flash); 582 adapter->osdep.flash_bus_space_handle = 583 rman_get_bushandle(adapter->flash); 584 585 /* 586 * This is used in the shared code 587 * XXX this goof is actually not used. 588 */ 589 adapter->hw.flash_address = (uint8_t *)adapter->flash; 590 } else if (adapter->hw.mac.type >= e1000_pch_spt) { 591 /* 592 * In the new SPT device flash is not a seperate BAR, 593 * rather it is also in BAR0, so use the same tag and 594 * an offset handle for the FLASH read/write macros 595 * in the shared code. 596 */ 597 adapter->osdep.flash_bus_space_tag = 598 adapter->osdep.mem_bus_space_tag; 599 adapter->osdep.flash_bus_space_handle = 600 adapter->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; 601 } 602 603 switch (adapter->hw.mac.type) { 604 case e1000_82571: 605 case e1000_82572: 606 case e1000_pch_lpt: 607 case e1000_pch_spt: 608 case e1000_pch_cnp: 609 /* 610 * Pullup extra 4bytes into the first data segment for 611 * TSO, see: 612 * 82571/82572 specification update errata #7 613 * 614 * Same applies to I217 (and maybe I218 and I219). 615 * 616 * NOTE: 617 * 4bytes instead of 2bytes, which are mentioned in the 618 * errata, are pulled; mainly to keep rest of the data 619 * properly aligned. 620 */ 621 adapter->flags |= EM_FLAG_TSO_PULLEX; 622 /* FALL THROUGH */ 623 624 default: 625 if (adapter->flags & EM_FLAG_GEN2) 626 adapter->flags |= EM_FLAG_TSO; 627 break; 628 } 629 630 /* Do Shared Code initialization */ 631 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 632 device_printf(dev, "Setup of Shared code failed\n"); 633 error = ENXIO; 634 goto fail; 635 } 636 637 e1000_get_bus_info(&adapter->hw); 638 639 /* 640 * Validate number of transmit and receive descriptors. It 641 * must not exceed hardware maximum, and must be multiple 642 * of E1000_DBA_ALIGN. 643 */ 644 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 645 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 646 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 647 em_txd < EM_MIN_TXD) { 648 if (adapter->hw.mac.type < e1000_82544) 649 adapter->num_tx_desc = EM_MAX_TXD_82543; 650 else 651 adapter->num_tx_desc = EM_DEFAULT_TXD; 652 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 653 adapter->num_tx_desc, em_txd); 654 } else { 655 adapter->num_tx_desc = em_txd; 656 } 657 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 658 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 659 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 660 em_rxd < EM_MIN_RXD) { 661 if (adapter->hw.mac.type < e1000_82544) 662 adapter->num_rx_desc = EM_MAX_RXD_82543; 663 else 664 adapter->num_rx_desc = EM_DEFAULT_RXD; 665 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 666 adapter->num_rx_desc, em_rxd); 667 } else { 668 adapter->num_rx_desc = em_rxd; 669 } 670 671 adapter->hw.mac.autoneg = DO_AUTO_NEG; 672 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 673 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 674 adapter->rx_buffer_len = MCLBYTES; 675 676 /* 677 * Interrupt throttle rate 678 */ 679 if (em_int_throttle_ceil == 0) { 680 adapter->int_throttle_ceil = 0; 681 } else { 682 int throttle = em_int_throttle_ceil; 683 684 if (throttle < 0) 685 throttle = EM_DEFAULT_ITR; 686 687 /* Recalculate the tunable value to get the exact frequency. */ 688 throttle = 1000000000 / 256 / throttle; 689 690 /* Upper 16bits of ITR is reserved and should be zero */ 691 if (throttle & 0xffff0000) 692 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 693 694 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 695 } 696 697 e1000_init_script_state_82541(&adapter->hw, TRUE); 698 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 699 700 /* Copper options */ 701 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 702 adapter->hw.phy.mdix = AUTO_ALL_MODES; 703 adapter->hw.phy.disable_polarity_correction = FALSE; 704 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 705 } 706 707 /* Set the frame limits assuming standard ethernet sized frames. */ 708 adapter->hw.mac.max_frame_size = 709 ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 710 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 711 712 /* This controls when hardware reports transmit completion status. */ 713 adapter->hw.mac.report_tx_early = 1; 714 715 /* 716 * Create top level busdma tag 717 */ 718 error = bus_dma_tag_create(NULL, 1, 0, 719 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 720 NULL, NULL, 721 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 722 0, &adapter->parent_dtag); 723 if (error) { 724 device_printf(dev, "could not create top level DMA tag\n"); 725 goto fail; 726 } 727 728 /* 729 * Allocate Transmit Descriptor ring 730 */ 731 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 732 EM_DBA_ALIGN); 733 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 734 if (error) { 735 device_printf(dev, "Unable to allocate tx_desc memory\n"); 736 goto fail; 737 } 738 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 739 740 /* 741 * Allocate Receive Descriptor ring 742 */ 743 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 744 EM_DBA_ALIGN); 745 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 746 if (error) { 747 device_printf(dev, "Unable to allocate rx_desc memory\n"); 748 goto fail; 749 } 750 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 751 752 /* Allocate multicast array memory. */ 753 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 754 M_DEVBUF, M_WAITOK); 755 756 /* Indicate SOL/IDER usage */ 757 if (e1000_check_reset_block(&adapter->hw)) { 758 device_printf(dev, 759 "PHY reset is blocked due to SOL/IDER session.\n"); 760 } 761 762 /* Disable EEE */ 763 adapter->hw.dev_spec.ich8lan.eee_disable = 1; 764 765 /* 766 * Start from a known state, this is important in reading the 767 * nvm and mac from that. 768 */ 769 e1000_reset_hw(&adapter->hw); 770 771 /* Make sure we have a good EEPROM before we read from it */ 772 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 773 /* 774 * Some PCI-E parts fail the first check due to 775 * the link being in sleep state, call it again, 776 * if it fails a second time its a real issue. 777 */ 778 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 779 device_printf(dev, 780 "The EEPROM Checksum Is Not Valid\n"); 781 error = EIO; 782 goto fail; 783 } 784 } 785 786 /* Copy the permanent MAC address out of the EEPROM */ 787 if (e1000_read_mac_addr(&adapter->hw) < 0) { 788 device_printf(dev, "EEPROM read error while reading MAC" 789 " address\n"); 790 error = EIO; 791 goto fail; 792 } 793 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 794 device_printf(dev, "Invalid MAC address\n"); 795 error = EIO; 796 goto fail; 797 } 798 799 /* Disable ULP support */ 800 e1000_disable_ulp_lpt_lp(&adapter->hw, TRUE); 801 802 /* Allocate transmit descriptors and buffers */ 803 error = em_create_tx_ring(adapter); 804 if (error) { 805 device_printf(dev, "Could not setup transmit structures\n"); 806 goto fail; 807 } 808 809 /* Allocate receive descriptors and buffers */ 810 error = em_create_rx_ring(adapter); 811 if (error) { 812 device_printf(dev, "Could not setup receive structures\n"); 813 goto fail; 814 } 815 816 /* Manually turn off all interrupts */ 817 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 818 819 /* Determine if we have to control management hardware */ 820 if (e1000_enable_mng_pass_thru(&adapter->hw)) 821 adapter->flags |= EM_FLAG_HAS_MGMT; 822 823 /* 824 * Setup Wake-on-Lan 825 */ 826 apme_mask = EM_EEPROM_APME; 827 eeprom_data = 0; 828 switch (adapter->hw.mac.type) { 829 case e1000_82542: 830 case e1000_82543: 831 break; 832 833 case e1000_82573: 834 case e1000_82583: 835 adapter->flags |= EM_FLAG_HAS_AMT; 836 /* FALL THROUGH */ 837 838 case e1000_82546: 839 case e1000_82546_rev_3: 840 case e1000_82571: 841 case e1000_82572: 842 case e1000_80003es2lan: 843 if (adapter->hw.bus.func == 1) { 844 e1000_read_nvm(&adapter->hw, 845 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 846 } else { 847 e1000_read_nvm(&adapter->hw, 848 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 849 } 850 break; 851 852 case e1000_ich8lan: 853 case e1000_ich9lan: 854 case e1000_ich10lan: 855 case e1000_pchlan: 856 case e1000_pch2lan: 857 case e1000_pch_lpt: 858 case e1000_pch_spt: 859 case e1000_pch_cnp: 860 apme_mask = E1000_WUC_APME; 861 adapter->flags |= EM_FLAG_HAS_AMT; 862 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 863 break; 864 865 default: 866 e1000_read_nvm(&adapter->hw, 867 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 868 break; 869 } 870 if (eeprom_data & apme_mask) 871 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 872 873 /* 874 * We have the eeprom settings, now apply the special cases 875 * where the eeprom may be wrong or the board won't support 876 * wake on lan on a particular port 877 */ 878 device_id = pci_get_device(dev); 879 switch (device_id) { 880 case E1000_DEV_ID_82546GB_PCIE: 881 adapter->wol = 0; 882 break; 883 884 case E1000_DEV_ID_82546EB_FIBER: 885 case E1000_DEV_ID_82546GB_FIBER: 886 case E1000_DEV_ID_82571EB_FIBER: 887 /* 888 * Wake events only supported on port A for dual fiber 889 * regardless of eeprom setting 890 */ 891 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 892 E1000_STATUS_FUNC_1) 893 adapter->wol = 0; 894 break; 895 896 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 897 case E1000_DEV_ID_82571EB_QUAD_COPPER: 898 case E1000_DEV_ID_82571EB_QUAD_FIBER: 899 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 900 /* if quad port adapter, disable WoL on all but port A */ 901 if (em_global_quad_port_a != 0) 902 adapter->wol = 0; 903 /* Reset for multiple quad port adapters */ 904 if (++em_global_quad_port_a == 4) 905 em_global_quad_port_a = 0; 906 break; 907 } 908 909 /* XXX disable wol */ 910 adapter->wol = 0; 911 912 /* Setup flow control. */ 913 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl), 914 em_flowctrl); 915 adapter->ifm_flowctrl = ifmedia_str2ethfc(flowctrl); 916 if (adapter->hw.mac.type == e1000_pchlan) { 917 /* Only PAUSE reception is supported on PCH */ 918 adapter->ifm_flowctrl &= ~IFM_ETH_TXPAUSE; 919 } 920 921 /* Setup OS specific network interface */ 922 em_setup_ifp(adapter); 923 924 /* Add sysctl tree, must after em_setup_ifp() */ 925 em_add_sysctl(adapter); 926 927 #ifdef IFPOLL_ENABLE 928 /* Polling setup */ 929 ifpoll_compat_setup(&adapter->npoll, 930 device_get_sysctl_ctx(dev), device_get_sysctl_tree(dev), 931 device_get_unit(dev), ifp->if_serializer); 932 #endif 933 934 /* Reset the hardware */ 935 error = em_reset(adapter); 936 if (error) { 937 /* 938 * Some 82573 parts fail the first reset, call it again, 939 * if it fails a second time its a real issue. 940 */ 941 error = em_reset(adapter); 942 if (error) { 943 device_printf(dev, "Unable to reset the hardware\n"); 944 ether_ifdetach(ifp); 945 goto fail; 946 } 947 } 948 949 /* Initialize statistics */ 950 em_update_stats(adapter); 951 952 adapter->hw.mac.get_link_status = 1; 953 em_update_link_status(adapter); 954 955 /* Do we need workaround for 82544 PCI-X adapter? */ 956 if (adapter->hw.bus.type == e1000_bus_type_pcix && 957 adapter->hw.mac.type == e1000_82544) 958 adapter->pcix_82544 = TRUE; 959 else 960 adapter->pcix_82544 = FALSE; 961 962 if (adapter->pcix_82544) { 963 /* 964 * 82544 on PCI-X may split one TX segment 965 * into two TX descs, so we double its number 966 * of spare TX desc here. 967 */ 968 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 969 } else { 970 adapter->spare_tx_desc = EM_TX_SPARE; 971 } 972 if (adapter->flags & EM_FLAG_TSO) 973 adapter->spare_tx_desc = EM_TX_SPARE_TSO; 974 adapter->tx_wreg_nsegs = EM_DEFAULT_TXWREG; 975 976 /* 977 * Keep following relationship between spare_tx_desc, oact_tx_desc 978 * and tx_int_nsegs: 979 * (spare_tx_desc + EM_TX_RESERVED) <= 980 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 981 */ 982 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 983 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 984 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 985 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 986 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 987 988 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 989 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 990 adapter->tx_int_nsegs = adapter->oact_tx_desc; 991 992 /* Non-AMT based hardware can now take control from firmware */ 993 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 994 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571) 995 em_get_hw_control(adapter); 996 997 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 998 999 /* 1000 * Missing Interrupt Following ICR read: 1001 * 1002 * 82571/82572 specification update errata #76 1003 * 82573 specification update errata #31 1004 * 82574 specification update errata #12 1005 * 82583 specification update errata #4 1006 */ 1007 intr_func = em_intr; 1008 if ((adapter->flags & EM_FLAG_SHARED_INTR) && 1009 (adapter->hw.mac.type == e1000_82571 || 1010 adapter->hw.mac.type == e1000_82572 || 1011 adapter->hw.mac.type == e1000_82573 || 1012 adapter->hw.mac.type == e1000_82574 || 1013 adapter->hw.mac.type == e1000_82583)) 1014 intr_func = em_intr_mask; 1015 1016 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 1017 intr_func, adapter, &adapter->intr_tag, 1018 ifp->if_serializer); 1019 if (error) { 1020 device_printf(dev, "Failed to register interrupt handler"); 1021 ether_ifdetach(ifp); 1022 goto fail; 1023 } 1024 return (0); 1025 fail: 1026 em_detach(dev); 1027 return (error); 1028 } 1029 1030 static int 1031 em_detach(device_t dev) 1032 { 1033 struct adapter *adapter = device_get_softc(dev); 1034 1035 if (device_is_attached(dev)) { 1036 struct ifnet *ifp = &adapter->arpcom.ac_if; 1037 1038 lwkt_serialize_enter(ifp->if_serializer); 1039 1040 em_stop(adapter); 1041 1042 e1000_phy_hw_reset(&adapter->hw); 1043 1044 em_rel_mgmt(adapter); 1045 em_rel_hw_control(adapter); 1046 1047 if (adapter->wol) { 1048 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 1049 E1000_WUC_PME_EN); 1050 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 1051 em_enable_wol(dev); 1052 } 1053 1054 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 1055 1056 lwkt_serialize_exit(ifp->if_serializer); 1057 1058 ether_ifdetach(ifp); 1059 } else if (adapter->memory != NULL) { 1060 em_rel_hw_control(adapter); 1061 } 1062 1063 ifmedia_removeall(&adapter->media); 1064 bus_generic_detach(dev); 1065 1066 em_free_pci_res(adapter); 1067 1068 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 1069 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 1070 1071 /* Free Transmit Descriptor ring */ 1072 if (adapter->tx_desc_base) 1073 em_dma_free(adapter, &adapter->txdma); 1074 1075 /* Free Receive Descriptor ring */ 1076 if (adapter->rx_desc_base) 1077 em_dma_free(adapter, &adapter->rxdma); 1078 1079 /* Free top level busdma tag */ 1080 if (adapter->parent_dtag != NULL) 1081 bus_dma_tag_destroy(adapter->parent_dtag); 1082 1083 if (adapter->mta != NULL) 1084 kfree(adapter->mta, M_DEVBUF); 1085 1086 return (0); 1087 } 1088 1089 static int 1090 em_shutdown(device_t dev) 1091 { 1092 return em_suspend(dev); 1093 } 1094 1095 static int 1096 em_suspend(device_t dev) 1097 { 1098 struct adapter *adapter = device_get_softc(dev); 1099 struct ifnet *ifp = &adapter->arpcom.ac_if; 1100 1101 lwkt_serialize_enter(ifp->if_serializer); 1102 1103 em_stop(adapter); 1104 1105 em_rel_mgmt(adapter); 1106 em_rel_hw_control(adapter); 1107 1108 if (adapter->wol) { 1109 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 1110 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 1111 em_enable_wol(dev); 1112 } 1113 1114 lwkt_serialize_exit(ifp->if_serializer); 1115 1116 return bus_generic_suspend(dev); 1117 } 1118 1119 static int 1120 em_resume(device_t dev) 1121 { 1122 struct adapter *adapter = device_get_softc(dev); 1123 struct ifnet *ifp = &adapter->arpcom.ac_if; 1124 1125 lwkt_serialize_enter(ifp->if_serializer); 1126 1127 if (adapter->hw.mac.type == e1000_pch2lan) 1128 e1000_resume_workarounds_pchlan(&adapter->hw); 1129 1130 em_init(adapter); 1131 em_get_mgmt(adapter); 1132 if_devstart(ifp); 1133 1134 lwkt_serialize_exit(ifp->if_serializer); 1135 1136 return bus_generic_resume(dev); 1137 } 1138 1139 static void 1140 em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1141 { 1142 struct adapter *adapter = ifp->if_softc; 1143 struct mbuf *m_head; 1144 int idx = -1, nsegs = 0; 1145 1146 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1147 ASSERT_SERIALIZED(ifp->if_serializer); 1148 1149 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1150 return; 1151 1152 if (!adapter->link_active) { 1153 ifq_purge(&ifp->if_snd); 1154 return; 1155 } 1156 1157 while (!ifq_is_empty(&ifp->if_snd)) { 1158 /* Now do we at least have a minimal? */ 1159 if (EM_IS_OACTIVE(adapter)) { 1160 em_tx_collect(adapter, FALSE); 1161 if (EM_IS_OACTIVE(adapter)) { 1162 ifq_set_oactive(&ifp->if_snd); 1163 adapter->no_tx_desc_avail1++; 1164 break; 1165 } 1166 } 1167 1168 logif(pkt_txqueue); 1169 m_head = ifq_dequeue(&ifp->if_snd); 1170 if (m_head == NULL) 1171 break; 1172 1173 if (em_encap(adapter, &m_head, &nsegs, &idx)) { 1174 IFNET_STAT_INC(ifp, oerrors, 1); 1175 em_tx_collect(adapter, FALSE); 1176 continue; 1177 } 1178 1179 /* 1180 * TX interrupt are aggressively aggregated, so increasing 1181 * opackets at TX interrupt time will make the opackets 1182 * statistics vastly inaccurate; we do the opackets increment 1183 * now. 1184 */ 1185 IFNET_STAT_INC(ifp, opackets, 1); 1186 1187 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) { 1188 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1189 nsegs = 0; 1190 idx = -1; 1191 } 1192 1193 /* Send a copy of the frame to the BPF listener */ 1194 ETHER_BPF_MTAP(ifp, m_head); 1195 1196 /* Set timeout in case hardware has problems transmitting. */ 1197 ifp->if_timer = EM_TX_TIMEOUT; 1198 } 1199 if (idx >= 0) 1200 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1201 adapter->tx_running = EM_TX_RUNNING; 1202 } 1203 1204 static int 1205 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1206 { 1207 struct adapter *adapter = ifp->if_softc; 1208 struct ifreq *ifr = (struct ifreq *)data; 1209 uint16_t eeprom_data = 0; 1210 int max_frame_size, mask, reinit; 1211 int error = 0; 1212 1213 ASSERT_SERIALIZED(ifp->if_serializer); 1214 1215 switch (command) { 1216 case SIOCSIFMTU: 1217 switch (adapter->hw.mac.type) { 1218 case e1000_82573: 1219 /* 1220 * 82573 only supports jumbo frames 1221 * if ASPM is disabled. 1222 */ 1223 e1000_read_nvm(&adapter->hw, 1224 NVM_INIT_3GIO_3, 1, &eeprom_data); 1225 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1226 max_frame_size = ETHER_MAX_LEN; 1227 break; 1228 } 1229 /* FALL THROUGH */ 1230 1231 /* Limit Jumbo Frame size */ 1232 case e1000_82571: 1233 case e1000_82572: 1234 case e1000_ich9lan: 1235 case e1000_ich10lan: 1236 case e1000_pch2lan: 1237 case e1000_pch_lpt: 1238 case e1000_pch_spt: 1239 case e1000_pch_cnp: 1240 case e1000_82574: 1241 case e1000_82583: 1242 case e1000_80003es2lan: 1243 max_frame_size = 9234; 1244 break; 1245 1246 case e1000_pchlan: 1247 max_frame_size = 4096; 1248 break; 1249 1250 /* Adapters that do not support jumbo frames */ 1251 case e1000_82542: 1252 case e1000_ich8lan: 1253 max_frame_size = ETHER_MAX_LEN; 1254 break; 1255 1256 default: 1257 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1258 break; 1259 } 1260 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1261 ETHER_CRC_LEN) { 1262 error = EINVAL; 1263 break; 1264 } 1265 1266 ifp->if_mtu = ifr->ifr_mtu; 1267 adapter->hw.mac.max_frame_size = 1268 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1269 1270 if (ifp->if_flags & IFF_RUNNING) 1271 em_init(adapter); 1272 break; 1273 1274 case SIOCSIFFLAGS: 1275 if (ifp->if_flags & IFF_UP) { 1276 if ((ifp->if_flags & IFF_RUNNING)) { 1277 if ((ifp->if_flags ^ adapter->if_flags) & 1278 (IFF_PROMISC | IFF_ALLMULTI)) { 1279 em_disable_promisc(adapter); 1280 em_set_promisc(adapter); 1281 } 1282 } else { 1283 em_init(adapter); 1284 } 1285 } else if (ifp->if_flags & IFF_RUNNING) { 1286 em_stop(adapter); 1287 } 1288 adapter->if_flags = ifp->if_flags; 1289 break; 1290 1291 case SIOCADDMULTI: 1292 case SIOCDELMULTI: 1293 if (ifp->if_flags & IFF_RUNNING) { 1294 em_disable_intr(adapter); 1295 em_set_multi(adapter); 1296 if (adapter->hw.mac.type == e1000_82542 && 1297 adapter->hw.revision_id == E1000_REVISION_2) 1298 em_init_rx_unit(adapter); 1299 #ifdef IFPOLL_ENABLE 1300 if (!(ifp->if_flags & IFF_NPOLLING)) 1301 #endif 1302 em_enable_intr(adapter); 1303 } 1304 break; 1305 1306 case SIOCSIFMEDIA: 1307 /* Check SOL/IDER usage */ 1308 if (e1000_check_reset_block(&adapter->hw)) { 1309 device_printf(adapter->dev, "Media change is" 1310 " blocked due to SOL/IDER session.\n"); 1311 break; 1312 } 1313 /* FALL THROUGH */ 1314 1315 case SIOCGIFMEDIA: 1316 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1317 break; 1318 1319 case SIOCSIFCAP: 1320 reinit = 0; 1321 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1322 if (mask & IFCAP_RXCSUM) { 1323 ifp->if_capenable ^= IFCAP_RXCSUM; 1324 reinit = 1; 1325 } 1326 if (mask & IFCAP_TXCSUM) { 1327 ifp->if_capenable ^= IFCAP_TXCSUM; 1328 if (ifp->if_capenable & IFCAP_TXCSUM) 1329 ifp->if_hwassist |= EM_CSUM_FEATURES; 1330 else 1331 ifp->if_hwassist &= ~EM_CSUM_FEATURES; 1332 } 1333 if (mask & IFCAP_TSO) { 1334 ifp->if_capenable ^= IFCAP_TSO; 1335 if (ifp->if_capenable & IFCAP_TSO) 1336 ifp->if_hwassist |= CSUM_TSO; 1337 else 1338 ifp->if_hwassist &= ~CSUM_TSO; 1339 } 1340 if (mask & IFCAP_VLAN_HWTAGGING) { 1341 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1342 reinit = 1; 1343 } 1344 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1345 em_init(adapter); 1346 break; 1347 1348 default: 1349 error = ether_ioctl(ifp, command, data); 1350 break; 1351 } 1352 return (error); 1353 } 1354 1355 static void 1356 em_watchdog(struct ifnet *ifp) 1357 { 1358 struct adapter *adapter = ifp->if_softc; 1359 1360 ASSERT_SERIALIZED(ifp->if_serializer); 1361 1362 /* 1363 * The timer is set to 5 every time start queues a packet. 1364 * Then txeof keeps resetting it as long as it cleans at 1365 * least one descriptor. 1366 * Finally, anytime all descriptors are clean the timer is 1367 * set to 0. 1368 */ 1369 1370 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1371 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1372 /* 1373 * If we reach here, all TX jobs are completed and 1374 * the TX engine should have been idled for some time. 1375 * We don't need to call if_devstart() here. 1376 */ 1377 ifq_clr_oactive(&ifp->if_snd); 1378 ifp->if_timer = 0; 1379 return; 1380 } 1381 1382 /* 1383 * If we are in this routine because of pause frames, then 1384 * don't reset the hardware. 1385 */ 1386 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1387 E1000_STATUS_TXOFF) { 1388 ifp->if_timer = EM_TX_TIMEOUT; 1389 return; 1390 } 1391 1392 if (e1000_check_for_link(&adapter->hw) == 0) 1393 if_printf(ifp, "watchdog timeout -- resetting\n"); 1394 1395 IFNET_STAT_INC(ifp, oerrors, 1); 1396 adapter->watchdog_events++; 1397 1398 em_init(adapter); 1399 1400 if (!ifq_is_empty(&ifp->if_snd)) 1401 if_devstart(ifp); 1402 } 1403 1404 static void 1405 em_init(void *xsc) 1406 { 1407 struct adapter *adapter = xsc; 1408 struct ifnet *ifp = &adapter->arpcom.ac_if; 1409 device_t dev = adapter->dev; 1410 1411 ASSERT_SERIALIZED(ifp->if_serializer); 1412 1413 em_stop(adapter); 1414 1415 /* Get the latest mac address, User can use a LAA */ 1416 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1417 1418 /* Put the address into the Receive Address Array */ 1419 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1420 1421 /* 1422 * With the 82571 adapter, RAR[0] may be overwritten 1423 * when the other port is reset, we make a duplicate 1424 * in RAR[14] for that eventuality, this assures 1425 * the interface continues to function. 1426 */ 1427 if (adapter->hw.mac.type == e1000_82571) { 1428 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1429 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1430 E1000_RAR_ENTRIES - 1); 1431 } 1432 1433 /* Reset the hardware */ 1434 if (em_reset(adapter)) { 1435 device_printf(dev, "Unable to reset the hardware\n"); 1436 /* XXX em_stop()? */ 1437 return; 1438 } 1439 em_update_link_status(adapter); 1440 1441 /* Setup VLAN support, basic and offload if available */ 1442 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1443 1444 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1445 uint32_t ctrl; 1446 1447 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1448 ctrl |= E1000_CTRL_VME; 1449 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1450 } 1451 1452 /* Configure for OS presence */ 1453 em_get_mgmt(adapter); 1454 1455 /* Prepare transmit descriptors and buffers */ 1456 em_init_tx_ring(adapter); 1457 em_init_tx_unit(adapter); 1458 1459 /* Setup Multicast table */ 1460 em_set_multi(adapter); 1461 1462 /* Prepare receive descriptors and buffers */ 1463 if (em_init_rx_ring(adapter)) { 1464 device_printf(dev, "Could not setup receive structures\n"); 1465 em_stop(adapter); 1466 return; 1467 } 1468 em_init_rx_unit(adapter); 1469 1470 /* Don't lose promiscuous settings */ 1471 em_set_promisc(adapter); 1472 1473 /* Reset hardware counters */ 1474 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1475 1476 /* MSI/X configuration for 82574 */ 1477 if (adapter->hw.mac.type == e1000_82574) { 1478 int tmp; 1479 1480 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1481 tmp |= E1000_CTRL_EXT_PBA_CLR; 1482 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1483 /* 1484 * XXX MSIX 1485 * Set the IVAR - interrupt vector routing. 1486 * Each nibble represents a vector, high bit 1487 * is enable, other 3 bits are the MSIX table 1488 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1489 * Link (other) to 2, hence the magic number. 1490 */ 1491 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1492 } 1493 1494 #ifdef IFPOLL_ENABLE 1495 /* 1496 * Only enable interrupts if we are not polling, make sure 1497 * they are off otherwise. 1498 */ 1499 if (ifp->if_flags & IFF_NPOLLING) 1500 em_disable_intr(adapter); 1501 else 1502 #endif /* IFPOLL_ENABLE */ 1503 em_enable_intr(adapter); 1504 1505 /* AMT based hardware can now take control from firmware */ 1506 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 1507 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) && 1508 adapter->hw.mac.type >= e1000_82571) 1509 em_get_hw_control(adapter); 1510 1511 ifp->if_flags |= IFF_RUNNING; 1512 ifq_clr_oactive(&ifp->if_snd); 1513 1514 #ifdef IFPOLL_ENABLE 1515 if ((ifp->if_flags & IFF_NPOLLING) == 0) 1516 #endif 1517 { 1518 callout_reset_bycpu(&adapter->tx_gc_timer, 1, 1519 em_txgc_timer, adapter, 1520 rman_get_cpuid(adapter->intr_res)); 1521 } 1522 callout_reset(&adapter->timer, hz, em_timer, adapter); 1523 } 1524 1525 #ifdef IFPOLL_ENABLE 1526 1527 static void 1528 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1529 { 1530 struct adapter *adapter = ifp->if_softc; 1531 1532 ASSERT_SERIALIZED(ifp->if_serializer); 1533 1534 if (adapter->npoll.ifpc_stcount-- == 0) { 1535 uint32_t reg_icr; 1536 1537 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac; 1538 1539 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1540 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1541 callout_stop(&adapter->timer); 1542 adapter->hw.mac.get_link_status = 1; 1543 em_update_link_status(adapter); 1544 callout_reset(&adapter->timer, hz, em_timer, adapter); 1545 } 1546 } 1547 1548 em_rxeof(adapter, count); 1549 1550 em_tx_intr(adapter); 1551 em_try_txgc(adapter, 1); 1552 } 1553 1554 static void 1555 em_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1556 { 1557 struct adapter *adapter = ifp->if_softc; 1558 1559 ASSERT_SERIALIZED(ifp->if_serializer); 1560 1561 if (info != NULL) { 1562 int cpuid = adapter->npoll.ifpc_cpuid; 1563 1564 info->ifpi_rx[cpuid].poll_func = em_npoll_compat; 1565 info->ifpi_rx[cpuid].arg = NULL; 1566 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1567 1568 ifq_set_cpuid(&ifp->if_snd, cpuid); 1569 } else { 1570 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 1571 } 1572 if (ifp->if_flags & IFF_RUNNING) 1573 em_init(adapter); 1574 } 1575 1576 #endif /* IFPOLL_ENABLE */ 1577 1578 static void 1579 em_intr(void *xsc) 1580 { 1581 em_intr_body(xsc, TRUE); 1582 } 1583 1584 static void 1585 em_intr_body(struct adapter *adapter, boolean_t chk_asserted) 1586 { 1587 struct ifnet *ifp = &adapter->arpcom.ac_if; 1588 uint32_t reg_icr; 1589 1590 logif(intr_beg); 1591 ASSERT_SERIALIZED(ifp->if_serializer); 1592 1593 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1594 1595 if (chk_asserted && 1596 ((adapter->hw.mac.type >= e1000_82571 && 1597 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1598 reg_icr == 0)) { 1599 logif(intr_end); 1600 return; 1601 } 1602 1603 /* 1604 * XXX: some laptops trigger several spurious interrupts 1605 * on em(4) when in the resume cycle. The ICR register 1606 * reports all-ones value in this case. Processing such 1607 * interrupts would lead to a freeze. I don't know why. 1608 */ 1609 if (reg_icr == 0xffffffff) { 1610 logif(intr_end); 1611 return; 1612 } 1613 1614 if (ifp->if_flags & IFF_RUNNING) { 1615 if (reg_icr & 1616 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1617 em_rxeof(adapter, -1); 1618 if (reg_icr & E1000_ICR_TXDW) 1619 em_tx_intr(adapter); 1620 } 1621 1622 /* Link status change */ 1623 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1624 callout_stop(&adapter->timer); 1625 adapter->hw.mac.get_link_status = 1; 1626 em_update_link_status(adapter); 1627 1628 /* Deal with TX cruft when link lost */ 1629 em_tx_purge(adapter); 1630 1631 callout_reset(&adapter->timer, hz, em_timer, adapter); 1632 } 1633 1634 if (reg_icr & E1000_ICR_RXO) 1635 adapter->rx_overruns++; 1636 1637 logif(intr_end); 1638 } 1639 1640 static void 1641 em_intr_mask(void *xsc) 1642 { 1643 struct adapter *adapter = xsc; 1644 1645 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 1646 /* 1647 * NOTE: 1648 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1649 * so don't check it. 1650 */ 1651 em_intr_body(adapter, FALSE); 1652 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); 1653 } 1654 1655 static void 1656 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1657 { 1658 struct adapter *adapter = ifp->if_softc; 1659 1660 ASSERT_SERIALIZED(ifp->if_serializer); 1661 1662 em_update_link_status(adapter); 1663 1664 ifmr->ifm_status = IFM_AVALID; 1665 ifmr->ifm_active = IFM_ETHER; 1666 1667 if (!adapter->link_active) { 1668 if (adapter->hw.mac.autoneg) 1669 ifmr->ifm_active |= IFM_NONE; 1670 else 1671 ifmr->ifm_active = adapter->media.ifm_media; 1672 return; 1673 } 1674 1675 ifmr->ifm_status |= IFM_ACTIVE; 1676 if (adapter->ifm_flowctrl & IFM_ETH_FORCEPAUSE) 1677 ifmr->ifm_active |= adapter->ifm_flowctrl; 1678 1679 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1680 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1681 u_char fiber_type = IFM_1000_SX; 1682 1683 if (adapter->hw.mac.type == e1000_82545) 1684 fiber_type = IFM_1000_LX; 1685 ifmr->ifm_active |= fiber_type | IFM_FDX; 1686 } else { 1687 switch (adapter->link_speed) { 1688 case 10: 1689 ifmr->ifm_active |= IFM_10_T; 1690 break; 1691 case 100: 1692 ifmr->ifm_active |= IFM_100_TX; 1693 break; 1694 1695 case 1000: 1696 ifmr->ifm_active |= IFM_1000_T; 1697 break; 1698 } 1699 if (adapter->link_duplex == FULL_DUPLEX) 1700 ifmr->ifm_active |= IFM_FDX; 1701 else 1702 ifmr->ifm_active |= IFM_HDX; 1703 } 1704 if (ifmr->ifm_active & IFM_FDX) { 1705 ifmr->ifm_active |= 1706 e1000_fc2ifmedia(adapter->hw.fc.current_mode); 1707 } 1708 } 1709 1710 static int 1711 em_media_change(struct ifnet *ifp) 1712 { 1713 struct adapter *adapter = ifp->if_softc; 1714 struct ifmedia *ifm = &adapter->media; 1715 1716 ASSERT_SERIALIZED(ifp->if_serializer); 1717 1718 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1719 return (EINVAL); 1720 1721 if (adapter->hw.mac.type == e1000_pchlan && 1722 (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)) { 1723 if (bootverbose) 1724 if_printf(ifp, "TX PAUSE is not supported on PCH\n"); 1725 return EINVAL; 1726 } 1727 1728 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1729 case IFM_AUTO: 1730 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1731 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1732 break; 1733 1734 case IFM_1000_LX: 1735 case IFM_1000_SX: 1736 case IFM_1000_T: 1737 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1738 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1739 break; 1740 1741 case IFM_100_TX: 1742 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) { 1743 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1744 } else { 1745 if (IFM_OPTIONS(ifm->ifm_media) & 1746 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 1747 if (bootverbose) { 1748 if_printf(ifp, "Flow control is not " 1749 "allowed for half-duplex\n"); 1750 } 1751 return EINVAL; 1752 } 1753 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1754 } 1755 adapter->hw.mac.autoneg = FALSE; 1756 adapter->hw.phy.autoneg_advertised = 0; 1757 break; 1758 1759 case IFM_10_T: 1760 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) { 1761 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1762 } else { 1763 if (IFM_OPTIONS(ifm->ifm_media) & 1764 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 1765 if (bootverbose) { 1766 if_printf(ifp, "Flow control is not " 1767 "allowed for half-duplex\n"); 1768 } 1769 return EINVAL; 1770 } 1771 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1772 } 1773 adapter->hw.mac.autoneg = FALSE; 1774 adapter->hw.phy.autoneg_advertised = 0; 1775 break; 1776 1777 default: 1778 if (bootverbose) { 1779 if_printf(ifp, "Unsupported media type %d\n", 1780 IFM_SUBTYPE(ifm->ifm_media)); 1781 } 1782 return EINVAL; 1783 } 1784 adapter->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK; 1785 1786 if (ifp->if_flags & IFF_RUNNING) 1787 em_init(adapter); 1788 1789 return (0); 1790 } 1791 1792 static int 1793 em_encap(struct adapter *adapter, struct mbuf **m_headp, 1794 int *segs_used, int *idx) 1795 { 1796 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1797 bus_dmamap_t map; 1798 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1799 struct e1000_tx_desc *ctxd = NULL; 1800 struct mbuf *m_head = *m_headp; 1801 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1802 int maxsegs, nsegs, i, j, first, last = 0, error; 1803 1804 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1805 error = em_tso_pullup(adapter, m_headp); 1806 if (error) 1807 return error; 1808 m_head = *m_headp; 1809 } 1810 1811 txd_upper = txd_lower = 0; 1812 txd_used = 0; 1813 1814 /* 1815 * Capture the first descriptor index, this descriptor 1816 * will have the index of the EOP which is the only one 1817 * that now gets a DONE bit writeback. 1818 */ 1819 first = adapter->next_avail_tx_desc; 1820 tx_buffer = &adapter->tx_buffer_area[first]; 1821 tx_buffer_mapped = tx_buffer; 1822 map = tx_buffer->map; 1823 1824 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1825 KASSERT(maxsegs >= adapter->spare_tx_desc, 1826 ("not enough spare TX desc")); 1827 if (adapter->pcix_82544) { 1828 /* Half it; see the comment in em_attach() */ 1829 maxsegs >>= 1; 1830 } 1831 if (maxsegs > EM_MAX_SCATTER) 1832 maxsegs = EM_MAX_SCATTER; 1833 1834 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1835 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1836 if (error) { 1837 if (error == ENOBUFS) 1838 adapter->mbuf_alloc_failed++; 1839 else 1840 adapter->no_tx_dma_setup++; 1841 1842 m_freem(*m_headp); 1843 *m_headp = NULL; 1844 return error; 1845 } 1846 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1847 1848 m_head = *m_headp; 1849 adapter->tx_nsegs += nsegs; 1850 *segs_used += nsegs; 1851 1852 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1853 /* TSO will consume one TX desc */ 1854 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 1855 adapter->tx_nsegs += i; 1856 *segs_used += i; 1857 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1858 /* TX csum offloading will consume one TX desc */ 1859 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower); 1860 adapter->tx_nsegs += i; 1861 *segs_used += i; 1862 } 1863 1864 /* Handle VLAN tag */ 1865 if (m_head->m_flags & M_VLANTAG) { 1866 /* Set the vlan id. */ 1867 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16); 1868 /* Tell hardware to add tag */ 1869 txd_lower |= htole32(E1000_TXD_CMD_VLE); 1870 } 1871 1872 i = adapter->next_avail_tx_desc; 1873 1874 /* Set up our transmit descriptors */ 1875 for (j = 0; j < nsegs; j++) { 1876 /* If adapter is 82544 and on PCIX bus */ 1877 if(adapter->pcix_82544) { 1878 DESC_ARRAY desc_array; 1879 uint32_t array_elements, counter; 1880 1881 /* 1882 * Check the Address and Length combination and 1883 * split the data accordingly 1884 */ 1885 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1886 segs[j].ds_len, &desc_array); 1887 for (counter = 0; counter < array_elements; counter++) { 1888 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1889 1890 tx_buffer = &adapter->tx_buffer_area[i]; 1891 ctxd = &adapter->tx_desc_base[i]; 1892 1893 ctxd->buffer_addr = htole64( 1894 desc_array.descriptor[counter].address); 1895 ctxd->lower.data = htole32( 1896 E1000_TXD_CMD_IFCS | txd_lower | 1897 desc_array.descriptor[counter].length); 1898 ctxd->upper.data = htole32(txd_upper); 1899 1900 last = i; 1901 if (++i == adapter->num_tx_desc) 1902 i = 0; 1903 1904 txd_used++; 1905 } 1906 } else { 1907 tx_buffer = &adapter->tx_buffer_area[i]; 1908 ctxd = &adapter->tx_desc_base[i]; 1909 1910 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1911 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1912 txd_lower | segs[j].ds_len); 1913 ctxd->upper.data = htole32(txd_upper); 1914 1915 last = i; 1916 if (++i == adapter->num_tx_desc) 1917 i = 0; 1918 } 1919 } 1920 1921 adapter->next_avail_tx_desc = i; 1922 if (adapter->pcix_82544) { 1923 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1924 adapter->num_tx_desc_avail -= txd_used; 1925 } else { 1926 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1927 adapter->num_tx_desc_avail -= nsegs; 1928 } 1929 adapter->tx_nmbuf++; 1930 1931 tx_buffer->m_head = m_head; 1932 tx_buffer_mapped->map = tx_buffer->map; 1933 tx_buffer->map = map; 1934 1935 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1936 adapter->tx_nsegs = 0; 1937 1938 /* 1939 * Report Status (RS) is turned on 1940 * every tx_int_nsegs descriptors. 1941 */ 1942 cmd = E1000_TXD_CMD_RS; 1943 1944 /* 1945 * Keep track of the descriptor, which will 1946 * be written back by hardware. 1947 */ 1948 adapter->tx_dd[adapter->tx_dd_tail] = last; 1949 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1950 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1951 } 1952 1953 /* 1954 * Last Descriptor of Packet needs End Of Packet (EOP) 1955 */ 1956 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1957 1958 if (adapter->hw.mac.type == e1000_82547) { 1959 /* 1960 * Advance the Transmit Descriptor Tail (TDT), this tells the 1961 * E1000 that this frame is available to transmit. 1962 */ 1963 if (adapter->link_duplex == HALF_DUPLEX) { 1964 em_82547_move_tail_serialized(adapter); 1965 } else { 1966 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1967 em_82547_update_fifo_head(adapter, 1968 m_head->m_pkthdr.len); 1969 } 1970 } else { 1971 /* 1972 * Defer TDT updating, until enough descriptors are setup 1973 */ 1974 *idx = i; 1975 } 1976 return (0); 1977 } 1978 1979 /* 1980 * 82547 workaround to avoid controller hang in half-duplex environment. 1981 * The workaround is to avoid queuing a large packet that would span 1982 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1983 * in this case. We do that only when FIFO is quiescent. 1984 */ 1985 static void 1986 em_82547_move_tail_serialized(struct adapter *adapter) 1987 { 1988 struct e1000_tx_desc *tx_desc; 1989 uint16_t hw_tdt, sw_tdt, length = 0; 1990 bool eop = 0; 1991 1992 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1993 1994 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1995 sw_tdt = adapter->next_avail_tx_desc; 1996 1997 while (hw_tdt != sw_tdt) { 1998 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1999 length += tx_desc->lower.flags.length; 2000 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 2001 if (++hw_tdt == adapter->num_tx_desc) 2002 hw_tdt = 0; 2003 2004 if (eop) { 2005 if (em_82547_fifo_workaround(adapter, length)) { 2006 adapter->tx_fifo_wrk_cnt++; 2007 callout_reset(&adapter->tx_fifo_timer, 1, 2008 em_82547_move_tail, adapter); 2009 break; 2010 } 2011 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 2012 em_82547_update_fifo_head(adapter, length); 2013 length = 0; 2014 } 2015 } 2016 } 2017 2018 static void 2019 em_82547_move_tail(void *xsc) 2020 { 2021 struct adapter *adapter = xsc; 2022 struct ifnet *ifp = &adapter->arpcom.ac_if; 2023 2024 lwkt_serialize_enter(ifp->if_serializer); 2025 em_82547_move_tail_serialized(adapter); 2026 lwkt_serialize_exit(ifp->if_serializer); 2027 } 2028 2029 static int 2030 em_82547_fifo_workaround(struct adapter *adapter, int len) 2031 { 2032 int fifo_space, fifo_pkt_len; 2033 2034 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2035 2036 if (adapter->link_duplex == HALF_DUPLEX) { 2037 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 2038 2039 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 2040 if (em_82547_tx_fifo_reset(adapter)) 2041 return (0); 2042 else 2043 return (1); 2044 } 2045 } 2046 return (0); 2047 } 2048 2049 static void 2050 em_82547_update_fifo_head(struct adapter *adapter, int len) 2051 { 2052 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2053 2054 /* tx_fifo_head is always 16 byte aligned */ 2055 adapter->tx_fifo_head += fifo_pkt_len; 2056 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 2057 adapter->tx_fifo_head -= adapter->tx_fifo_size; 2058 } 2059 2060 static int 2061 em_82547_tx_fifo_reset(struct adapter *adapter) 2062 { 2063 uint32_t tctl; 2064 2065 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 2066 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 2067 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 2068 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 2069 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 2070 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 2071 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 2072 /* Disable TX unit */ 2073 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2074 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 2075 tctl & ~E1000_TCTL_EN); 2076 2077 /* Reset FIFO pointers */ 2078 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 2079 adapter->tx_head_addr); 2080 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 2081 adapter->tx_head_addr); 2082 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 2083 adapter->tx_head_addr); 2084 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 2085 adapter->tx_head_addr); 2086 2087 /* Re-enable TX unit */ 2088 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2089 E1000_WRITE_FLUSH(&adapter->hw); 2090 2091 adapter->tx_fifo_head = 0; 2092 adapter->tx_fifo_reset_cnt++; 2093 2094 return (TRUE); 2095 } else { 2096 return (FALSE); 2097 } 2098 } 2099 2100 static void 2101 em_set_promisc(struct adapter *adapter) 2102 { 2103 struct ifnet *ifp = &adapter->arpcom.ac_if; 2104 uint32_t reg_rctl; 2105 2106 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2107 2108 if (ifp->if_flags & IFF_PROMISC) { 2109 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2110 /* Turn this on if you want to see bad packets */ 2111 if (em_debug_sbp) 2112 reg_rctl |= E1000_RCTL_SBP; 2113 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2114 } else if (ifp->if_flags & IFF_ALLMULTI) { 2115 reg_rctl |= E1000_RCTL_MPE; 2116 reg_rctl &= ~E1000_RCTL_UPE; 2117 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2118 } 2119 } 2120 2121 static void 2122 em_disable_promisc(struct adapter *adapter) 2123 { 2124 struct ifnet *ifp = &adapter->arpcom.ac_if; 2125 uint32_t reg_rctl; 2126 int mcnt = 0; 2127 2128 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2129 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP); 2130 2131 if (ifp->if_flags & IFF_ALLMULTI) { 2132 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2133 } else { 2134 const struct ifmultiaddr *ifma; 2135 2136 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2137 if (ifma->ifma_addr->sa_family != AF_LINK) 2138 continue; 2139 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2140 break; 2141 mcnt++; 2142 } 2143 } 2144 /* Don't disable if in MAX groups */ 2145 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2146 reg_rctl &= ~E1000_RCTL_MPE; 2147 2148 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2149 } 2150 2151 static void 2152 em_set_multi(struct adapter *adapter) 2153 { 2154 struct ifnet *ifp = &adapter->arpcom.ac_if; 2155 struct ifmultiaddr *ifma; 2156 uint32_t reg_rctl = 0; 2157 uint8_t *mta; 2158 int mcnt = 0; 2159 2160 mta = adapter->mta; 2161 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2162 2163 if (adapter->hw.mac.type == e1000_82542 && 2164 adapter->hw.revision_id == E1000_REVISION_2) { 2165 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2166 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2167 e1000_pci_clear_mwi(&adapter->hw); 2168 reg_rctl |= E1000_RCTL_RST; 2169 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2170 msec_delay(5); 2171 } 2172 2173 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2174 if (ifma->ifma_addr->sa_family != AF_LINK) 2175 continue; 2176 2177 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2178 break; 2179 2180 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2181 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2182 mcnt++; 2183 } 2184 2185 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 2186 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2187 reg_rctl |= E1000_RCTL_MPE; 2188 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2189 } else { 2190 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 2191 } 2192 2193 if (adapter->hw.mac.type == e1000_82542 && 2194 adapter->hw.revision_id == E1000_REVISION_2) { 2195 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2196 reg_rctl &= ~E1000_RCTL_RST; 2197 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2198 msec_delay(5); 2199 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2200 e1000_pci_set_mwi(&adapter->hw); 2201 } 2202 } 2203 2204 /* 2205 * This routine checks for link status and updates statistics. 2206 */ 2207 static void 2208 em_timer(void *xsc) 2209 { 2210 struct adapter *adapter = xsc; 2211 struct ifnet *ifp = &adapter->arpcom.ac_if; 2212 2213 lwkt_serialize_enter(ifp->if_serializer); 2214 2215 em_update_link_status(adapter); 2216 em_update_stats(adapter); 2217 2218 /* Reset LAA into RAR[0] on 82571 */ 2219 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 2220 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2221 2222 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 2223 em_print_hw_stats(adapter); 2224 2225 em_smartspeed(adapter); 2226 2227 callout_reset(&adapter->timer, hz, em_timer, adapter); 2228 2229 lwkt_serialize_exit(ifp->if_serializer); 2230 } 2231 2232 static void 2233 em_update_link_status(struct adapter *adapter) 2234 { 2235 struct e1000_hw *hw = &adapter->hw; 2236 struct ifnet *ifp = &adapter->arpcom.ac_if; 2237 device_t dev = adapter->dev; 2238 uint32_t link_check = 0; 2239 2240 /* Get the cached link value or read phy for real */ 2241 switch (hw->phy.media_type) { 2242 case e1000_media_type_copper: 2243 if (hw->mac.get_link_status) { 2244 if (hw->mac.type >= e1000_pch_spt) 2245 msec_delay(50); 2246 /* Do the work to read phy */ 2247 e1000_check_for_link(hw); 2248 link_check = !hw->mac.get_link_status; 2249 if (link_check) /* ESB2 fix */ 2250 e1000_cfg_on_link_up(hw); 2251 } else { 2252 link_check = TRUE; 2253 } 2254 break; 2255 2256 case e1000_media_type_fiber: 2257 e1000_check_for_link(hw); 2258 link_check = 2259 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 2260 break; 2261 2262 case e1000_media_type_internal_serdes: 2263 e1000_check_for_link(hw); 2264 link_check = adapter->hw.mac.serdes_has_link; 2265 break; 2266 2267 case e1000_media_type_unknown: 2268 default: 2269 break; 2270 } 2271 2272 /* Now check for a transition */ 2273 if (link_check && adapter->link_active == 0) { 2274 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2275 &adapter->link_duplex); 2276 2277 /* 2278 * Check if we should enable/disable SPEED_MODE bit on 2279 * 82571/82572 2280 */ 2281 if (adapter->link_speed != SPEED_1000 && 2282 (hw->mac.type == e1000_82571 || 2283 hw->mac.type == e1000_82572)) { 2284 int tarc0; 2285 2286 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2287 tarc0 &= ~TARC_SPEED_MODE_BIT; 2288 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2289 } 2290 if (bootverbose) { 2291 char flowctrl[IFM_ETH_FC_STRLEN]; 2292 2293 e1000_fc2str(hw->fc.current_mode, flowctrl, 2294 sizeof(flowctrl)); 2295 device_printf(dev, "Link is up %d Mbps %s, " 2296 "Flow control: %s\n", 2297 adapter->link_speed, 2298 (adapter->link_duplex == FULL_DUPLEX) ? 2299 "Full Duplex" : "Half Duplex", 2300 flowctrl); 2301 } 2302 if (adapter->ifm_flowctrl & IFM_ETH_FORCEPAUSE) 2303 e1000_force_flowctrl(hw, adapter->ifm_flowctrl); 2304 adapter->link_active = 1; 2305 adapter->smartspeed = 0; 2306 ifp->if_baudrate = adapter->link_speed * 1000000; 2307 ifp->if_link_state = LINK_STATE_UP; 2308 if_link_state_change(ifp); 2309 } else if (!link_check && adapter->link_active == 1) { 2310 ifp->if_baudrate = adapter->link_speed = 0; 2311 adapter->link_duplex = 0; 2312 if (bootverbose) 2313 device_printf(dev, "Link is Down\n"); 2314 adapter->link_active = 0; 2315 #if 0 2316 /* Link down, disable watchdog */ 2317 if->if_timer = 0; 2318 #endif 2319 ifp->if_link_state = LINK_STATE_DOWN; 2320 if_link_state_change(ifp); 2321 } 2322 } 2323 2324 static void 2325 em_stop(struct adapter *adapter) 2326 { 2327 struct ifnet *ifp = &adapter->arpcom.ac_if; 2328 int i; 2329 2330 ASSERT_SERIALIZED(ifp->if_serializer); 2331 2332 em_disable_intr(adapter); 2333 2334 callout_stop(&adapter->timer); 2335 callout_stop(&adapter->tx_fifo_timer); 2336 2337 ifp->if_flags &= ~IFF_RUNNING; 2338 ifq_clr_oactive(&ifp->if_snd); 2339 ifp->if_timer = 0; 2340 adapter->tx_running = 0; 2341 callout_stop(&adapter->tx_gc_timer); 2342 2343 /* I219 needs some special flushing to avoid hangs */ 2344 if (adapter->hw.mac.type >= e1000_pch_spt) 2345 em_flush_txrx_ring(adapter); 2346 2347 e1000_reset_hw(&adapter->hw); 2348 if (adapter->hw.mac.type >= e1000_82544) 2349 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2350 2351 for (i = 0; i < adapter->num_tx_desc; i++) { 2352 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2353 2354 if (tx_buffer->m_head != NULL) 2355 em_free_txbuffer(adapter, tx_buffer); 2356 } 2357 2358 for (i = 0; i < adapter->num_rx_desc; i++) { 2359 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2360 2361 if (rx_buffer->m_head != NULL) { 2362 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2363 m_freem(rx_buffer->m_head); 2364 rx_buffer->m_head = NULL; 2365 } 2366 } 2367 2368 if (adapter->fmp != NULL) 2369 m_freem(adapter->fmp); 2370 adapter->fmp = NULL; 2371 adapter->lmp = NULL; 2372 2373 adapter->csum_flags = 0; 2374 adapter->csum_lhlen = 0; 2375 adapter->csum_iphlen = 0; 2376 adapter->csum_thlen = 0; 2377 adapter->csum_mss = 0; 2378 adapter->csum_pktlen = 0; 2379 2380 adapter->tx_dd_head = 0; 2381 adapter->tx_dd_tail = 0; 2382 adapter->tx_nsegs = 0; 2383 } 2384 2385 static int 2386 em_get_hw_info(struct adapter *adapter) 2387 { 2388 device_t dev = adapter->dev; 2389 2390 /* Save off the information about this board */ 2391 adapter->hw.vendor_id = pci_get_vendor(dev); 2392 adapter->hw.device_id = pci_get_device(dev); 2393 adapter->hw.revision_id = pci_get_revid(dev); 2394 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2395 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2396 2397 /* Do Shared Code Init and Setup */ 2398 if (e1000_set_mac_type(&adapter->hw)) 2399 return ENXIO; 2400 return 0; 2401 } 2402 2403 static int 2404 em_alloc_pci_res(struct adapter *adapter) 2405 { 2406 device_t dev = adapter->dev; 2407 u_int intr_flags; 2408 int val, rid, msi_enable; 2409 2410 /* Enable bus mastering */ 2411 pci_enable_busmaster(dev); 2412 2413 adapter->memory_rid = EM_BAR_MEM; 2414 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2415 &adapter->memory_rid, RF_ACTIVE); 2416 if (adapter->memory == NULL) { 2417 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2418 return (ENXIO); 2419 } 2420 adapter->osdep.mem_bus_space_tag = 2421 rman_get_bustag(adapter->memory); 2422 adapter->osdep.mem_bus_space_handle = 2423 rman_get_bushandle(adapter->memory); 2424 2425 /* XXX This is quite goofy, it is not actually used */ 2426 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2427 2428 /* Only older adapters use IO mapping */ 2429 if (adapter->hw.mac.type > e1000_82543 && 2430 adapter->hw.mac.type < e1000_82571) { 2431 /* Figure our where our IO BAR is ? */ 2432 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2433 val = pci_read_config(dev, rid, 4); 2434 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2435 adapter->io_rid = rid; 2436 break; 2437 } 2438 rid += 4; 2439 /* check for 64bit BAR */ 2440 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2441 rid += 4; 2442 } 2443 if (rid >= PCIR_CARDBUSCIS) { 2444 device_printf(dev, "Unable to locate IO BAR\n"); 2445 return (ENXIO); 2446 } 2447 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2448 &adapter->io_rid, RF_ACTIVE); 2449 if (adapter->ioport == NULL) { 2450 device_printf(dev, "Unable to allocate bus resource: " 2451 "ioport\n"); 2452 return (ENXIO); 2453 } 2454 adapter->hw.io_base = 0; 2455 adapter->osdep.io_bus_space_tag = 2456 rman_get_bustag(adapter->ioport); 2457 adapter->osdep.io_bus_space_handle = 2458 rman_get_bushandle(adapter->ioport); 2459 } 2460 2461 /* 2462 * Don't enable MSI-X on 82574, see: 2463 * 82574 specification update errata #15 2464 * 2465 * Don't enable MSI on PCI/PCI-X chips, see: 2466 * 82540 specification update errata #6 2467 * 82545 specification update errata #4 2468 * 2469 * Don't enable MSI on 82571/82572, see: 2470 * 82571/82572 specification update errata #63 2471 */ 2472 msi_enable = em_msi_enable; 2473 if (msi_enable && 2474 ((adapter->flags & EM_FLAG_GEN2) == 0 || 2475 adapter->hw.mac.type == e1000_82571 || 2476 adapter->hw.mac.type == e1000_82572)) 2477 msi_enable = 0; 2478 again: 2479 adapter->intr_type = pci_alloc_1intr(dev, msi_enable, 2480 &adapter->intr_rid, &intr_flags); 2481 2482 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) { 2483 int unshared; 2484 2485 unshared = device_getenv_int(dev, "irq.unshared", 0); 2486 if (!unshared) { 2487 adapter->flags |= EM_FLAG_SHARED_INTR; 2488 if (bootverbose) 2489 device_printf(dev, "IRQ shared\n"); 2490 } else { 2491 intr_flags &= ~RF_SHAREABLE; 2492 if (bootverbose) 2493 device_printf(dev, "IRQ unshared\n"); 2494 } 2495 } 2496 2497 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2498 &adapter->intr_rid, intr_flags); 2499 if (adapter->intr_res == NULL) { 2500 device_printf(dev, "Unable to allocate bus resource: %s\n", 2501 adapter->intr_type == PCI_INTR_TYPE_MSI ? 2502 "MSI" : "legacy intr"); 2503 if (!msi_enable) { 2504 /* Retry with MSI. */ 2505 msi_enable = 1; 2506 adapter->flags &= ~EM_FLAG_SHARED_INTR; 2507 goto again; 2508 } 2509 return (ENXIO); 2510 } 2511 2512 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2513 adapter->hw.back = &adapter->osdep; 2514 return (0); 2515 } 2516 2517 static void 2518 em_free_pci_res(struct adapter *adapter) 2519 { 2520 device_t dev = adapter->dev; 2521 2522 if (adapter->intr_res != NULL) { 2523 bus_release_resource(dev, SYS_RES_IRQ, 2524 adapter->intr_rid, adapter->intr_res); 2525 } 2526 2527 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2528 pci_release_msi(dev); 2529 2530 if (adapter->memory != NULL) { 2531 bus_release_resource(dev, SYS_RES_MEMORY, 2532 adapter->memory_rid, adapter->memory); 2533 } 2534 2535 if (adapter->flash != NULL) { 2536 bus_release_resource(dev, SYS_RES_MEMORY, 2537 adapter->flash_rid, adapter->flash); 2538 } 2539 2540 if (adapter->ioport != NULL) { 2541 bus_release_resource(dev, SYS_RES_IOPORT, 2542 adapter->io_rid, adapter->ioport); 2543 } 2544 } 2545 2546 static int 2547 em_reset(struct adapter *adapter) 2548 { 2549 device_t dev = adapter->dev; 2550 uint16_t rx_buffer_size; 2551 uint32_t pba; 2552 2553 /* When hardware is reset, fifo_head is also reset */ 2554 adapter->tx_fifo_head = 0; 2555 2556 /* Set up smart power down as default off on newer adapters. */ 2557 if (!em_smart_pwr_down && 2558 (adapter->hw.mac.type == e1000_82571 || 2559 adapter->hw.mac.type == e1000_82572)) { 2560 uint16_t phy_tmp = 0; 2561 2562 /* Speed up time to link by disabling smart power down. */ 2563 e1000_read_phy_reg(&adapter->hw, 2564 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2565 phy_tmp &= ~IGP02E1000_PM_SPD; 2566 e1000_write_phy_reg(&adapter->hw, 2567 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2568 } 2569 2570 /* 2571 * Packet Buffer Allocation (PBA) 2572 * Writing PBA sets the receive portion of the buffer 2573 * the remainder is used for the transmit buffer. 2574 * 2575 * Devices before the 82547 had a Packet Buffer of 64K. 2576 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 2577 * After the 82547 the buffer was reduced to 40K. 2578 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 2579 * Note: default does not leave enough room for Jumbo Frame >10k. 2580 */ 2581 switch (adapter->hw.mac.type) { 2582 case e1000_82547: 2583 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 2584 if (adapter->hw.mac.max_frame_size > 8192) 2585 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2586 else 2587 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2588 adapter->tx_fifo_head = 0; 2589 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 2590 adapter->tx_fifo_size = 2591 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 2592 break; 2593 2594 /* Total Packet Buffer on these is 48K */ 2595 case e1000_82571: 2596 case e1000_82572: 2597 case e1000_80003es2lan: 2598 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2599 break; 2600 2601 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2602 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2603 break; 2604 2605 case e1000_82574: 2606 case e1000_82583: 2607 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2608 break; 2609 2610 case e1000_ich8lan: 2611 pba = E1000_PBA_8K; 2612 break; 2613 2614 case e1000_ich9lan: 2615 case e1000_ich10lan: 2616 #define E1000_PBA_10K 0x000A 2617 pba = E1000_PBA_10K; 2618 break; 2619 2620 case e1000_pchlan: 2621 case e1000_pch2lan: 2622 case e1000_pch_lpt: 2623 case e1000_pch_spt: 2624 case e1000_pch_cnp: 2625 pba = E1000_PBA_26K; 2626 break; 2627 2628 default: 2629 /* Devices before 82547 had a Packet Buffer of 64K. */ 2630 if (adapter->hw.mac.max_frame_size > 8192) 2631 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2632 else 2633 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2634 } 2635 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2636 2637 /* 2638 * These parameters control the automatic generation (Tx) and 2639 * response (Rx) to Ethernet PAUSE frames. 2640 * - High water mark should allow for at least two frames to be 2641 * received after sending an XOFF. 2642 * - Low water mark works best when it is very near the high water mark. 2643 * This allows the receiver to restart by sending XON when it has 2644 * drained a bit. Here we use an arbitary value of 1500 which will 2645 * restart after one full frame is pulled from the buffer. There 2646 * could be several smaller frames in the buffer and if so they will 2647 * not trigger the XON until their total number reduces the buffer 2648 * by 1500. 2649 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2650 */ 2651 rx_buffer_size = 2652 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2653 2654 adapter->hw.fc.high_water = rx_buffer_size - 2655 roundup2(adapter->hw.mac.max_frame_size, 1024); 2656 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2657 2658 if (adapter->hw.mac.type == e1000_80003es2lan) 2659 adapter->hw.fc.pause_time = 0xFFFF; 2660 else 2661 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2662 2663 adapter->hw.fc.send_xon = TRUE; 2664 2665 adapter->hw.fc.requested_mode = e1000_ifmedia2fc(adapter->ifm_flowctrl); 2666 2667 /* 2668 * Device specific overrides/settings 2669 */ 2670 switch (adapter->hw.mac.type) { 2671 case e1000_pchlan: 2672 KASSERT(adapter->hw.fc.requested_mode == e1000_fc_rx_pause || 2673 adapter->hw.fc.requested_mode == e1000_fc_none, 2674 ("unsupported flow control on PCH %d", 2675 adapter->hw.fc.requested_mode)); 2676 adapter->hw.fc.pause_time = 0xFFFF; /* override */ 2677 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2678 adapter->hw.fc.high_water = 0x3500; 2679 adapter->hw.fc.low_water = 0x1500; 2680 } else { 2681 adapter->hw.fc.high_water = 0x5000; 2682 adapter->hw.fc.low_water = 0x3000; 2683 } 2684 adapter->hw.fc.refresh_time = 0x1000; 2685 break; 2686 2687 case e1000_pch2lan: 2688 case e1000_pch_lpt: 2689 case e1000_pch_spt: 2690 case e1000_pch_cnp: 2691 adapter->hw.fc.high_water = 0x5C20; 2692 adapter->hw.fc.low_water = 0x5048; 2693 adapter->hw.fc.pause_time = 0x0650; 2694 adapter->hw.fc.refresh_time = 0x0400; 2695 /* Jumbos need adjusted PBA */ 2696 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2697 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2698 else 2699 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2700 break; 2701 2702 case e1000_ich9lan: 2703 case e1000_ich10lan: 2704 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2705 adapter->hw.fc.high_water = 0x2800; 2706 adapter->hw.fc.low_water = 2707 adapter->hw.fc.high_water - 8; 2708 break; 2709 } 2710 /* FALL THROUGH */ 2711 default: 2712 if (adapter->hw.mac.type == e1000_80003es2lan) 2713 adapter->hw.fc.pause_time = 0xFFFF; 2714 break; 2715 } 2716 2717 /* I219 needs some special flushing to avoid hangs */ 2718 if (adapter->hw.mac.type >= e1000_pch_spt) 2719 em_flush_txrx_ring(adapter); 2720 2721 /* Issue a global reset */ 2722 e1000_reset_hw(&adapter->hw); 2723 if (adapter->hw.mac.type >= e1000_82544) 2724 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2725 em_disable_aspm(adapter); 2726 2727 if (e1000_init_hw(&adapter->hw) < 0) { 2728 device_printf(dev, "Hardware Initialization Failed\n"); 2729 return (EIO); 2730 } 2731 2732 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2733 e1000_get_phy_info(&adapter->hw); 2734 e1000_check_for_link(&adapter->hw); 2735 2736 return (0); 2737 } 2738 2739 static void 2740 em_setup_ifp(struct adapter *adapter) 2741 { 2742 struct ifnet *ifp = &adapter->arpcom.ac_if; 2743 2744 if_initname(ifp, device_get_name(adapter->dev), 2745 device_get_unit(adapter->dev)); 2746 ifp->if_softc = adapter; 2747 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2748 ifp->if_init = em_init; 2749 ifp->if_ioctl = em_ioctl; 2750 ifp->if_start = em_start; 2751 #ifdef IFPOLL_ENABLE 2752 ifp->if_npoll = em_npoll; 2753 #endif 2754 ifp->if_watchdog = em_watchdog; 2755 ifp->if_nmbclusters = adapter->num_rx_desc; 2756 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2757 ifq_set_ready(&ifp->if_snd); 2758 2759 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2760 2761 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2762 if (adapter->hw.mac.type >= e1000_82543) 2763 ifp->if_capabilities |= IFCAP_HWCSUM; 2764 if (adapter->flags & EM_FLAG_TSO) 2765 ifp->if_capabilities |= IFCAP_TSO; 2766 ifp->if_capenable = ifp->if_capabilities; 2767 2768 if (ifp->if_capenable & IFCAP_TXCSUM) 2769 ifp->if_hwassist |= EM_CSUM_FEATURES; 2770 if (ifp->if_capenable & IFCAP_TSO) 2771 ifp->if_hwassist |= CSUM_TSO; 2772 2773 /* 2774 * Tell the upper layer(s) we support long frames. 2775 */ 2776 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2777 2778 /* 2779 * Specify the media types supported by this adapter and register 2780 * callbacks to update media and link information 2781 */ 2782 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2783 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2784 u_char fiber_type = IFM_1000_SX; /* default type */ 2785 2786 if (adapter->hw.mac.type == e1000_82545) 2787 fiber_type = IFM_1000_LX; 2788 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2789 0, NULL); 2790 } else { 2791 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2792 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2793 0, NULL); 2794 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2795 0, NULL); 2796 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2797 0, NULL); 2798 if (adapter->hw.phy.type != e1000_phy_ife) { 2799 ifmedia_add(&adapter->media, 2800 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2801 } 2802 } 2803 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2804 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO | 2805 adapter->ifm_flowctrl); 2806 } 2807 2808 2809 /* 2810 * Workaround for SmartSpeed on 82541 and 82547 controllers 2811 */ 2812 static void 2813 em_smartspeed(struct adapter *adapter) 2814 { 2815 uint16_t phy_tmp; 2816 2817 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2818 adapter->hw.mac.autoneg == 0 || 2819 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2820 return; 2821 2822 if (adapter->smartspeed == 0) { 2823 /* 2824 * If Master/Slave config fault is asserted twice, 2825 * we assume back-to-back 2826 */ 2827 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2828 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2829 return; 2830 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2831 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2832 e1000_read_phy_reg(&adapter->hw, 2833 PHY_1000T_CTRL, &phy_tmp); 2834 if (phy_tmp & CR_1000T_MS_ENABLE) { 2835 phy_tmp &= ~CR_1000T_MS_ENABLE; 2836 e1000_write_phy_reg(&adapter->hw, 2837 PHY_1000T_CTRL, phy_tmp); 2838 adapter->smartspeed++; 2839 if (adapter->hw.mac.autoneg && 2840 !e1000_phy_setup_autoneg(&adapter->hw) && 2841 !e1000_read_phy_reg(&adapter->hw, 2842 PHY_CONTROL, &phy_tmp)) { 2843 phy_tmp |= MII_CR_AUTO_NEG_EN | 2844 MII_CR_RESTART_AUTO_NEG; 2845 e1000_write_phy_reg(&adapter->hw, 2846 PHY_CONTROL, phy_tmp); 2847 } 2848 } 2849 } 2850 return; 2851 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2852 /* If still no link, perhaps using 2/3 pair cable */ 2853 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2854 phy_tmp |= CR_1000T_MS_ENABLE; 2855 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2856 if (adapter->hw.mac.autoneg && 2857 !e1000_phy_setup_autoneg(&adapter->hw) && 2858 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2859 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2860 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2861 } 2862 } 2863 2864 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2865 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2866 adapter->smartspeed = 0; 2867 } 2868 2869 static int 2870 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2871 struct em_dma_alloc *dma) 2872 { 2873 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2874 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2875 &dma->dma_tag, &dma->dma_map, 2876 &dma->dma_paddr); 2877 if (dma->dma_vaddr == NULL) 2878 return ENOMEM; 2879 else 2880 return 0; 2881 } 2882 2883 static void 2884 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2885 { 2886 if (dma->dma_tag == NULL) 2887 return; 2888 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2889 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2890 bus_dma_tag_destroy(dma->dma_tag); 2891 } 2892 2893 static int 2894 em_create_tx_ring(struct adapter *adapter) 2895 { 2896 device_t dev = adapter->dev; 2897 struct em_buffer *tx_buffer; 2898 int error, i; 2899 2900 adapter->tx_buffer_area = 2901 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2902 M_DEVBUF, M_WAITOK | M_ZERO); 2903 2904 /* 2905 * Create DMA tags for tx buffers 2906 */ 2907 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2908 1, 0, /* alignment, bounds */ 2909 BUS_SPACE_MAXADDR, /* lowaddr */ 2910 BUS_SPACE_MAXADDR, /* highaddr */ 2911 NULL, NULL, /* filter, filterarg */ 2912 EM_TSO_SIZE, /* maxsize */ 2913 EM_MAX_SCATTER, /* nsegments */ 2914 PAGE_SIZE, /* maxsegsize */ 2915 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2916 BUS_DMA_ONEBPAGE, /* flags */ 2917 &adapter->txtag); 2918 if (error) { 2919 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2920 kfree(adapter->tx_buffer_area, M_DEVBUF); 2921 adapter->tx_buffer_area = NULL; 2922 return error; 2923 } 2924 2925 /* 2926 * Create DMA maps for tx buffers 2927 */ 2928 for (i = 0; i < adapter->num_tx_desc; i++) { 2929 tx_buffer = &adapter->tx_buffer_area[i]; 2930 2931 error = bus_dmamap_create(adapter->txtag, 2932 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2933 &tx_buffer->map); 2934 if (error) { 2935 device_printf(dev, "Unable to create TX DMA map\n"); 2936 em_destroy_tx_ring(adapter, i); 2937 return error; 2938 } 2939 } 2940 return (0); 2941 } 2942 2943 static void 2944 em_init_tx_ring(struct adapter *adapter) 2945 { 2946 /* Clear the old ring contents */ 2947 bzero(adapter->tx_desc_base, 2948 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2949 2950 /* Reset state */ 2951 adapter->next_avail_tx_desc = 0; 2952 adapter->next_tx_to_clean = 0; 2953 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2954 adapter->tx_nmbuf = 0; 2955 adapter->tx_running = 0; 2956 } 2957 2958 static void 2959 em_init_tx_unit(struct adapter *adapter) 2960 { 2961 uint32_t tctl, tarc, tipg = 0; 2962 uint64_t bus_addr; 2963 2964 /* Setup the Base and Length of the Tx Descriptor Ring */ 2965 bus_addr = adapter->txdma.dma_paddr; 2966 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2967 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2968 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2969 (uint32_t)(bus_addr >> 32)); 2970 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2971 (uint32_t)bus_addr); 2972 /* Setup the HW Tx Head and Tail descriptor pointers */ 2973 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2974 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2975 if (adapter->flags & EM_FLAG_GEN2) { 2976 uint32_t txdctl = 0; 2977 2978 txdctl |= 0x1f; /* PTHRESH */ 2979 txdctl |= 1 << 8; /* HTHRESH */ 2980 txdctl |= 1 << 16; /* WTHRESH */ 2981 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2982 txdctl |= E1000_TXDCTL_GRAN; 2983 txdctl |= 1 << 25; /* LWTHRESH */ 2984 2985 E1000_WRITE_REG(&adapter->hw, E1000_TXDCTL(0), txdctl); 2986 } 2987 2988 /* Set the default values for the Tx Inter Packet Gap timer */ 2989 switch (adapter->hw.mac.type) { 2990 case e1000_82542: 2991 tipg = DEFAULT_82542_TIPG_IPGT; 2992 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2993 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2994 break; 2995 2996 case e1000_80003es2lan: 2997 tipg = DEFAULT_82543_TIPG_IPGR1; 2998 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2999 E1000_TIPG_IPGR2_SHIFT; 3000 break; 3001 3002 default: 3003 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3004 adapter->hw.phy.media_type == 3005 e1000_media_type_internal_serdes) 3006 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3007 else 3008 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3009 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3010 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3011 break; 3012 } 3013 3014 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3015 3016 /* NOTE: 0 is not allowed for TIDV */ 3017 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 3018 if(adapter->hw.mac.type >= e1000_82540) 3019 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 3020 3021 if (adapter->hw.mac.type == e1000_82571 || 3022 adapter->hw.mac.type == e1000_82572) { 3023 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3024 tarc |= TARC_SPEED_MODE_BIT; 3025 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3026 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3027 /* errata: program both queues to unweighted RR */ 3028 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3029 tarc |= 1; 3030 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3031 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3032 tarc |= 1; 3033 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3034 } else if (adapter->hw.mac.type == e1000_82574) { 3035 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3036 tarc |= TARC_ERRATA_BIT; 3037 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3038 } 3039 3040 /* Program the Transmit Control Register */ 3041 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3042 tctl &= ~E1000_TCTL_CT; 3043 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3044 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3045 3046 if (adapter->hw.mac.type >= e1000_82571) 3047 tctl |= E1000_TCTL_MULR; 3048 3049 /* This write will effectively turn on the transmit unit. */ 3050 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3051 3052 if (adapter->hw.mac.type == e1000_82571 || 3053 adapter->hw.mac.type == e1000_82572 || 3054 adapter->hw.mac.type == e1000_80003es2lan) { 3055 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 3056 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3057 tarc &= ~(1 << 28); 3058 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3059 } else if (adapter->hw.mac.type >= e1000_pch_spt) { 3060 uint32_t reg; 3061 3062 reg = E1000_READ_REG(&adapter->hw, E1000_IOSFPC); 3063 reg |= E1000_RCTL_RDMTS_HEX; 3064 E1000_WRITE_REG(&adapter->hw, E1000_IOSFPC, reg); 3065 reg = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3066 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 3067 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), reg); 3068 } 3069 } 3070 3071 static void 3072 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 3073 { 3074 struct em_buffer *tx_buffer; 3075 int i; 3076 3077 if (adapter->tx_buffer_area == NULL) 3078 return; 3079 3080 for (i = 0; i < ndesc; i++) { 3081 tx_buffer = &adapter->tx_buffer_area[i]; 3082 3083 KKASSERT(tx_buffer->m_head == NULL); 3084 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 3085 } 3086 bus_dma_tag_destroy(adapter->txtag); 3087 3088 kfree(adapter->tx_buffer_area, M_DEVBUF); 3089 adapter->tx_buffer_area = NULL; 3090 } 3091 3092 /* 3093 * The offload context needs to be set when we transfer the first 3094 * packet of a particular protocol (TCP/UDP). This routine has been 3095 * enhanced to deal with inserted VLAN headers. 3096 * 3097 * If the new packet's ether header length, ip header length and 3098 * csum offloading type are same as the previous packet, we should 3099 * avoid allocating a new csum context descriptor; mainly to take 3100 * advantage of the pipeline effect of the TX data read request. 3101 * 3102 * This function returns number of TX descrptors allocated for 3103 * csum context. 3104 */ 3105 static int 3106 em_txcsum(struct adapter *adapter, struct mbuf *mp, 3107 uint32_t *txd_upper, uint32_t *txd_lower) 3108 { 3109 struct e1000_context_desc *TXD; 3110 int curr_txd, ehdrlen, csum_flags; 3111 uint32_t cmd, hdr_len, ip_hlen; 3112 3113 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 3114 ip_hlen = mp->m_pkthdr.csum_iphlen; 3115 ehdrlen = mp->m_pkthdr.csum_lhlen; 3116 3117 if (adapter->csum_lhlen == ehdrlen && 3118 adapter->csum_iphlen == ip_hlen && 3119 adapter->csum_flags == csum_flags) { 3120 /* 3121 * Same csum offload context as the previous packets; 3122 * just return. 3123 */ 3124 *txd_upper = adapter->csum_txd_upper; 3125 *txd_lower = adapter->csum_txd_lower; 3126 return 0; 3127 } 3128 3129 /* 3130 * Setup a new csum offload context. 3131 */ 3132 3133 curr_txd = adapter->next_avail_tx_desc; 3134 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 3135 3136 cmd = 0; 3137 3138 /* Setup of IP header checksum. */ 3139 if (csum_flags & CSUM_IP) { 3140 /* 3141 * Start offset for header checksum calculation. 3142 * End offset for header checksum calculation. 3143 * Offset of place to put the checksum. 3144 */ 3145 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3146 TXD->lower_setup.ip_fields.ipcse = 3147 htole16(ehdrlen + ip_hlen - 1); 3148 TXD->lower_setup.ip_fields.ipcso = 3149 ehdrlen + offsetof(struct ip, ip_sum); 3150 cmd |= E1000_TXD_CMD_IP; 3151 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 3152 } 3153 hdr_len = ehdrlen + ip_hlen; 3154 3155 if (csum_flags & CSUM_TCP) { 3156 /* 3157 * Start offset for payload checksum calculation. 3158 * End offset for payload checksum calculation. 3159 * Offset of place to put the checksum. 3160 */ 3161 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3162 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3163 TXD->upper_setup.tcp_fields.tucso = 3164 hdr_len + offsetof(struct tcphdr, th_sum); 3165 cmd |= E1000_TXD_CMD_TCP; 3166 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3167 } else if (csum_flags & CSUM_UDP) { 3168 /* 3169 * Start offset for header checksum calculation. 3170 * End offset for header checksum calculation. 3171 * Offset of place to put the checksum. 3172 */ 3173 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3174 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3175 TXD->upper_setup.tcp_fields.tucso = 3176 hdr_len + offsetof(struct udphdr, uh_sum); 3177 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3178 } 3179 3180 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 3181 E1000_TXD_DTYP_D; /* Data descr */ 3182 3183 /* Save the information for this csum offloading context */ 3184 adapter->csum_lhlen = ehdrlen; 3185 adapter->csum_iphlen = ip_hlen; 3186 adapter->csum_flags = csum_flags; 3187 adapter->csum_txd_upper = *txd_upper; 3188 adapter->csum_txd_lower = *txd_lower; 3189 3190 TXD->tcp_seg_setup.data = htole32(0); 3191 TXD->cmd_and_length = 3192 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 3193 3194 if (++curr_txd == adapter->num_tx_desc) 3195 curr_txd = 0; 3196 3197 KKASSERT(adapter->num_tx_desc_avail > 0); 3198 adapter->num_tx_desc_avail--; 3199 3200 adapter->next_avail_tx_desc = curr_txd; 3201 return 1; 3202 } 3203 3204 static void 3205 em_txeof(struct adapter *adapter) 3206 { 3207 struct ifnet *ifp = &adapter->arpcom.ac_if; 3208 struct em_buffer *tx_buffer; 3209 int first, num_avail; 3210 3211 if (adapter->tx_dd_head == adapter->tx_dd_tail) 3212 return; 3213 3214 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3215 return; 3216 3217 num_avail = adapter->num_tx_desc_avail; 3218 first = adapter->next_tx_to_clean; 3219 3220 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 3221 struct e1000_tx_desc *tx_desc; 3222 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3223 3224 tx_desc = &adapter->tx_desc_base[dd_idx]; 3225 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 3226 EM_INC_TXDD_IDX(adapter->tx_dd_head); 3227 3228 if (++dd_idx == adapter->num_tx_desc) 3229 dd_idx = 0; 3230 3231 while (first != dd_idx) { 3232 logif(pkt_txclean); 3233 3234 KKASSERT(num_avail < adapter->num_tx_desc); 3235 num_avail++; 3236 3237 tx_buffer = &adapter->tx_buffer_area[first]; 3238 if (tx_buffer->m_head != NULL) 3239 em_free_txbuffer(adapter, tx_buffer); 3240 3241 if (++first == adapter->num_tx_desc) 3242 first = 0; 3243 } 3244 } else { 3245 break; 3246 } 3247 } 3248 adapter->next_tx_to_clean = first; 3249 adapter->num_tx_desc_avail = num_avail; 3250 3251 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 3252 adapter->tx_dd_head = 0; 3253 adapter->tx_dd_tail = 0; 3254 } 3255 3256 if (!EM_IS_OACTIVE(adapter)) { 3257 ifq_clr_oactive(&ifp->if_snd); 3258 3259 /* All clean, turn off the timer */ 3260 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3261 ifp->if_timer = 0; 3262 } 3263 adapter->tx_running = EM_TX_RUNNING; 3264 } 3265 3266 static void 3267 em_tx_collect(struct adapter *adapter, boolean_t gc) 3268 { 3269 struct ifnet *ifp = &adapter->arpcom.ac_if; 3270 struct em_buffer *tx_buffer; 3271 int tdh, first, num_avail, dd_idx = -1; 3272 3273 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3274 return; 3275 3276 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 3277 if (tdh == adapter->next_tx_to_clean) { 3278 if (gc && adapter->tx_nmbuf > 0) 3279 adapter->tx_running = EM_TX_RUNNING; 3280 return; 3281 } 3282 if (gc) 3283 adapter->tx_gc++; 3284 3285 if (adapter->tx_dd_head != adapter->tx_dd_tail) 3286 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3287 3288 num_avail = adapter->num_tx_desc_avail; 3289 first = adapter->next_tx_to_clean; 3290 3291 while (first != tdh) { 3292 logif(pkt_txclean); 3293 3294 KKASSERT(num_avail < adapter->num_tx_desc); 3295 num_avail++; 3296 3297 tx_buffer = &adapter->tx_buffer_area[first]; 3298 if (tx_buffer->m_head != NULL) 3299 em_free_txbuffer(adapter, tx_buffer); 3300 3301 if (first == dd_idx) { 3302 EM_INC_TXDD_IDX(adapter->tx_dd_head); 3303 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 3304 adapter->tx_dd_head = 0; 3305 adapter->tx_dd_tail = 0; 3306 dd_idx = -1; 3307 } else { 3308 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3309 } 3310 } 3311 3312 if (++first == adapter->num_tx_desc) 3313 first = 0; 3314 } 3315 adapter->next_tx_to_clean = first; 3316 adapter->num_tx_desc_avail = num_avail; 3317 3318 if (!EM_IS_OACTIVE(adapter)) { 3319 ifq_clr_oactive(&ifp->if_snd); 3320 3321 /* All clean, turn off the timer */ 3322 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3323 ifp->if_timer = 0; 3324 } 3325 if (!gc || adapter->tx_nmbuf > 0) 3326 adapter->tx_running = EM_TX_RUNNING; 3327 } 3328 3329 /* 3330 * When Link is lost sometimes there is work still in the TX ring 3331 * which will result in a watchdog, rather than allow that do an 3332 * attempted cleanup and then reinit here. Note that this has been 3333 * seens mostly with fiber adapters. 3334 */ 3335 static void 3336 em_tx_purge(struct adapter *adapter) 3337 { 3338 struct ifnet *ifp = &adapter->arpcom.ac_if; 3339 3340 if (!adapter->link_active && ifp->if_timer) { 3341 em_tx_collect(adapter, FALSE); 3342 if (ifp->if_timer) { 3343 if_printf(ifp, "Link lost, TX pending, reinit\n"); 3344 ifp->if_timer = 0; 3345 em_init(adapter); 3346 } 3347 } 3348 } 3349 3350 static int 3351 em_newbuf(struct adapter *adapter, int i, int init) 3352 { 3353 struct mbuf *m; 3354 bus_dma_segment_t seg; 3355 bus_dmamap_t map; 3356 struct em_buffer *rx_buffer; 3357 int error, nseg; 3358 3359 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 3360 if (m == NULL) { 3361 adapter->mbuf_cluster_failed++; 3362 if (init) { 3363 if_printf(&adapter->arpcom.ac_if, 3364 "Unable to allocate RX mbuf\n"); 3365 } 3366 return (ENOBUFS); 3367 } 3368 m->m_len = m->m_pkthdr.len = MCLBYTES; 3369 3370 if (adapter->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN) 3371 m_adj(m, ETHER_ALIGN); 3372 3373 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3374 adapter->rx_sparemap, m, 3375 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3376 if (error) { 3377 m_freem(m); 3378 if (init) { 3379 if_printf(&adapter->arpcom.ac_if, 3380 "Unable to load RX mbuf\n"); 3381 } 3382 return (error); 3383 } 3384 3385 rx_buffer = &adapter->rx_buffer_area[i]; 3386 if (rx_buffer->m_head != NULL) 3387 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3388 3389 map = rx_buffer->map; 3390 rx_buffer->map = adapter->rx_sparemap; 3391 adapter->rx_sparemap = map; 3392 3393 rx_buffer->m_head = m; 3394 3395 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3396 return (0); 3397 } 3398 3399 static int 3400 em_create_rx_ring(struct adapter *adapter) 3401 { 3402 device_t dev = adapter->dev; 3403 struct em_buffer *rx_buffer; 3404 int i, error; 3405 3406 adapter->rx_buffer_area = 3407 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3408 M_DEVBUF, M_WAITOK | M_ZERO); 3409 3410 /* 3411 * Create DMA tag for rx buffers 3412 */ 3413 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3414 1, 0, /* alignment, bounds */ 3415 BUS_SPACE_MAXADDR, /* lowaddr */ 3416 BUS_SPACE_MAXADDR, /* highaddr */ 3417 NULL, NULL, /* filter, filterarg */ 3418 MCLBYTES, /* maxsize */ 3419 1, /* nsegments */ 3420 MCLBYTES, /* maxsegsize */ 3421 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3422 &adapter->rxtag); 3423 if (error) { 3424 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3425 kfree(adapter->rx_buffer_area, M_DEVBUF); 3426 adapter->rx_buffer_area = NULL; 3427 return error; 3428 } 3429 3430 /* 3431 * Create spare DMA map for rx buffers 3432 */ 3433 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3434 &adapter->rx_sparemap); 3435 if (error) { 3436 device_printf(dev, "Unable to create spare RX DMA map\n"); 3437 bus_dma_tag_destroy(adapter->rxtag); 3438 kfree(adapter->rx_buffer_area, M_DEVBUF); 3439 adapter->rx_buffer_area = NULL; 3440 return error; 3441 } 3442 3443 /* 3444 * Create DMA maps for rx buffers 3445 */ 3446 for (i = 0; i < adapter->num_rx_desc; i++) { 3447 rx_buffer = &adapter->rx_buffer_area[i]; 3448 3449 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3450 &rx_buffer->map); 3451 if (error) { 3452 device_printf(dev, "Unable to create RX DMA map\n"); 3453 em_destroy_rx_ring(adapter, i); 3454 return error; 3455 } 3456 } 3457 return (0); 3458 } 3459 3460 static int 3461 em_init_rx_ring(struct adapter *adapter) 3462 { 3463 int i, error; 3464 3465 /* Reset descriptor ring */ 3466 bzero(adapter->rx_desc_base, 3467 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3468 3469 /* Allocate new ones. */ 3470 for (i = 0; i < adapter->num_rx_desc; i++) { 3471 error = em_newbuf(adapter, i, 1); 3472 if (error) 3473 return (error); 3474 } 3475 3476 /* Setup our descriptor pointers */ 3477 adapter->next_rx_desc_to_check = 0; 3478 3479 return (0); 3480 } 3481 3482 static void 3483 em_init_rx_unit(struct adapter *adapter) 3484 { 3485 struct ifnet *ifp = &adapter->arpcom.ac_if; 3486 uint64_t bus_addr; 3487 uint32_t rctl, rxcsum; 3488 3489 /* 3490 * Make sure receives are disabled while setting 3491 * up the descriptor ring 3492 */ 3493 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3494 /* Do not disable if ever enabled on this hardware */ 3495 if (adapter->hw.mac.type != e1000_82574 && 3496 adapter->hw.mac.type != e1000_82583) 3497 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3498 3499 if (adapter->hw.mac.type >= e1000_82540) { 3500 uint32_t itr; 3501 3502 /* 3503 * Set the interrupt throttling rate. Value is calculated 3504 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3505 */ 3506 if (adapter->int_throttle_ceil) 3507 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3508 else 3509 itr = 0; 3510 em_set_itr(adapter, itr); 3511 } 3512 3513 /* Disable accelerated ackknowledge */ 3514 if (adapter->hw.mac.type == e1000_82574) { 3515 uint32_t rfctl; 3516 3517 rfctl = E1000_READ_REG(&adapter->hw, E1000_RFCTL); 3518 rfctl |= E1000_RFCTL_ACK_DIS; 3519 E1000_WRITE_REG(&adapter->hw, E1000_RFCTL, rfctl); 3520 } 3521 3522 /* Receive Checksum Offload for IP and TCP/UDP */ 3523 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3524 if (ifp->if_capenable & IFCAP_RXCSUM) 3525 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3526 else 3527 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3528 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3529 3530 /* 3531 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3532 * long latencies are observed, like Lenovo X60. This 3533 * change eliminates the problem, but since having positive 3534 * values in RDTR is a known source of problems on other 3535 * platforms another solution is being sought. 3536 */ 3537 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3538 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3539 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3540 } 3541 3542 /* 3543 * Setup the Base and Length of the Rx Descriptor Ring 3544 */ 3545 bus_addr = adapter->rxdma.dma_paddr; 3546 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3547 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3548 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3549 (uint32_t)(bus_addr >> 32)); 3550 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3551 (uint32_t)bus_addr); 3552 3553 /* 3554 * Setup the HW Rx Head and Tail Descriptor Pointers 3555 */ 3556 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3557 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3558 3559 /* Set PTHRESH for improved jumbo performance */ 3560 if (ifp->if_mtu > ETHERMTU) { 3561 uint32_t rxdctl; 3562 3563 if (adapter->hw.mac.type == e1000_ich9lan || 3564 adapter->hw.mac.type == e1000_pch2lan || 3565 adapter->hw.mac.type == e1000_ich10lan) { 3566 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3567 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), 3568 rxdctl | 3); 3569 } else if (adapter->hw.mac.type == e1000_82574) { 3570 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3571 rxdctl |= 0x20; /* PTHRESH */ 3572 rxdctl |= 4 << 8; /* HTHRESH */ 3573 rxdctl |= 4 << 16; /* WTHRESH */ 3574 rxdctl |= 1 << 24; /* Switch to granularity */ 3575 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl); 3576 } 3577 } 3578 3579 if (adapter->hw.mac.type >= e1000_pch2lan) { 3580 if (ifp->if_mtu > ETHERMTU) 3581 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3582 else 3583 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3584 } 3585 3586 /* Setup the Receive Control Register */ 3587 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3588 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3589 E1000_RCTL_RDMTS_HALF | 3590 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3591 3592 /* Make sure VLAN Filters are off */ 3593 rctl &= ~E1000_RCTL_VFE; 3594 3595 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3596 rctl |= E1000_RCTL_SBP; 3597 else 3598 rctl &= ~E1000_RCTL_SBP; 3599 3600 switch (adapter->rx_buffer_len) { 3601 default: 3602 case 2048: 3603 rctl |= E1000_RCTL_SZ_2048; 3604 break; 3605 3606 case 4096: 3607 rctl |= E1000_RCTL_SZ_4096 | 3608 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3609 break; 3610 3611 case 8192: 3612 rctl |= E1000_RCTL_SZ_8192 | 3613 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3614 break; 3615 3616 case 16384: 3617 rctl |= E1000_RCTL_SZ_16384 | 3618 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3619 break; 3620 } 3621 3622 if (ifp->if_mtu > ETHERMTU) 3623 rctl |= E1000_RCTL_LPE; 3624 else 3625 rctl &= ~E1000_RCTL_LPE; 3626 3627 /* Enable Receives */ 3628 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3629 } 3630 3631 static void 3632 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3633 { 3634 struct em_buffer *rx_buffer; 3635 int i; 3636 3637 if (adapter->rx_buffer_area == NULL) 3638 return; 3639 3640 for (i = 0; i < ndesc; i++) { 3641 rx_buffer = &adapter->rx_buffer_area[i]; 3642 3643 KKASSERT(rx_buffer->m_head == NULL); 3644 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3645 } 3646 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3647 bus_dma_tag_destroy(adapter->rxtag); 3648 3649 kfree(adapter->rx_buffer_area, M_DEVBUF); 3650 adapter->rx_buffer_area = NULL; 3651 } 3652 3653 static void 3654 em_rxeof(struct adapter *adapter, int count) 3655 { 3656 struct ifnet *ifp = &adapter->arpcom.ac_if; 3657 uint8_t status, accept_frame = 0, eop = 0; 3658 uint16_t len, desc_len, prev_len_adj; 3659 struct e1000_rx_desc *current_desc; 3660 struct mbuf *mp; 3661 int i; 3662 3663 i = adapter->next_rx_desc_to_check; 3664 current_desc = &adapter->rx_desc_base[i]; 3665 3666 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3667 return; 3668 3669 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3670 struct mbuf *m = NULL; 3671 3672 logif(pkt_receive); 3673 3674 mp = adapter->rx_buffer_area[i].m_head; 3675 3676 /* 3677 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3678 * needs to access the last received byte in the mbuf. 3679 */ 3680 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3681 BUS_DMASYNC_POSTREAD); 3682 3683 accept_frame = 1; 3684 prev_len_adj = 0; 3685 desc_len = le16toh(current_desc->length); 3686 status = current_desc->status; 3687 if (status & E1000_RXD_STAT_EOP) { 3688 count--; 3689 eop = 1; 3690 if (desc_len < ETHER_CRC_LEN) { 3691 len = 0; 3692 prev_len_adj = ETHER_CRC_LEN - desc_len; 3693 } else { 3694 len = desc_len - ETHER_CRC_LEN; 3695 } 3696 } else { 3697 eop = 0; 3698 len = desc_len; 3699 } 3700 3701 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3702 uint8_t last_byte; 3703 uint32_t pkt_len = desc_len; 3704 3705 if (adapter->fmp != NULL) 3706 pkt_len += adapter->fmp->m_pkthdr.len; 3707 3708 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3709 if (TBI_ACCEPT(&adapter->hw, status, 3710 current_desc->errors, pkt_len, last_byte, 3711 adapter->min_frame_size, 3712 adapter->hw.mac.max_frame_size)) { 3713 e1000_tbi_adjust_stats_82543(&adapter->hw, 3714 &adapter->stats, pkt_len, 3715 adapter->hw.mac.addr, 3716 adapter->hw.mac.max_frame_size); 3717 if (len > 0) 3718 len--; 3719 } else { 3720 accept_frame = 0; 3721 } 3722 } 3723 3724 if (accept_frame) { 3725 if (em_newbuf(adapter, i, 0) != 0) { 3726 IFNET_STAT_INC(ifp, iqdrops, 1); 3727 goto discard; 3728 } 3729 3730 /* Assign correct length to the current fragment */ 3731 mp->m_len = len; 3732 3733 if (adapter->fmp == NULL) { 3734 mp->m_pkthdr.len = len; 3735 adapter->fmp = mp; /* Store the first mbuf */ 3736 adapter->lmp = mp; 3737 } else { 3738 /* 3739 * Chain mbuf's together 3740 */ 3741 3742 /* 3743 * Adjust length of previous mbuf in chain if 3744 * we received less than 4 bytes in the last 3745 * descriptor. 3746 */ 3747 if (prev_len_adj > 0) { 3748 adapter->lmp->m_len -= prev_len_adj; 3749 adapter->fmp->m_pkthdr.len -= 3750 prev_len_adj; 3751 } 3752 adapter->lmp->m_next = mp; 3753 adapter->lmp = adapter->lmp->m_next; 3754 adapter->fmp->m_pkthdr.len += len; 3755 } 3756 3757 if (eop) { 3758 adapter->fmp->m_pkthdr.rcvif = ifp; 3759 IFNET_STAT_INC(ifp, ipackets, 1); 3760 3761 if (ifp->if_capenable & IFCAP_RXCSUM) { 3762 em_rxcsum(adapter, current_desc, 3763 adapter->fmp); 3764 } 3765 3766 if (status & E1000_RXD_STAT_VP) { 3767 adapter->fmp->m_pkthdr.ether_vlantag = 3768 (le16toh(current_desc->special) & 3769 E1000_RXD_SPC_VLAN_MASK); 3770 adapter->fmp->m_flags |= M_VLANTAG; 3771 } 3772 m = adapter->fmp; 3773 adapter->fmp = NULL; 3774 adapter->lmp = NULL; 3775 } 3776 } else { 3777 IFNET_STAT_INC(ifp, ierrors, 1); 3778 discard: 3779 #ifdef foo 3780 /* Reuse loaded DMA map and just update mbuf chain */ 3781 mp = adapter->rx_buffer_area[i].m_head; 3782 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3783 mp->m_data = mp->m_ext.ext_buf; 3784 mp->m_next = NULL; 3785 if (adapter->hw.mac.max_frame_size <= 3786 (MCLBYTES - ETHER_ALIGN)) 3787 m_adj(mp, ETHER_ALIGN); 3788 #endif 3789 if (adapter->fmp != NULL) { 3790 m_freem(adapter->fmp); 3791 adapter->fmp = NULL; 3792 adapter->lmp = NULL; 3793 } 3794 m = NULL; 3795 } 3796 3797 /* Zero out the receive descriptors status. */ 3798 current_desc->status = 0; 3799 3800 if (m != NULL) 3801 ifp->if_input(ifp, m, NULL, -1); 3802 3803 /* Advance our pointers to the next descriptor. */ 3804 if (++i == adapter->num_rx_desc) 3805 i = 0; 3806 current_desc = &adapter->rx_desc_base[i]; 3807 } 3808 adapter->next_rx_desc_to_check = i; 3809 3810 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3811 if (--i < 0) 3812 i = adapter->num_rx_desc - 1; 3813 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3814 } 3815 3816 static void 3817 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3818 struct mbuf *mp) 3819 { 3820 /* 82543 or newer only */ 3821 if (adapter->hw.mac.type < e1000_82543 || 3822 /* Ignore Checksum bit is set */ 3823 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3824 return; 3825 3826 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3827 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3828 /* IP Checksum Good */ 3829 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3830 } 3831 3832 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3833 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3834 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3835 CSUM_PSEUDO_HDR | 3836 CSUM_FRAG_NOT_CHECKED; 3837 mp->m_pkthdr.csum_data = htons(0xffff); 3838 } 3839 } 3840 3841 static void 3842 em_enable_intr(struct adapter *adapter) 3843 { 3844 uint32_t ims_mask = IMS_ENABLE_MASK; 3845 3846 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3847 3848 #if 0 3849 /* XXX MSIX */ 3850 if (adapter->hw.mac.type == e1000_82574) { 3851 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3852 ims_mask |= EM_MSIX_MASK; 3853 } 3854 #endif 3855 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3856 } 3857 3858 static void 3859 em_disable_intr(struct adapter *adapter) 3860 { 3861 uint32_t clear = 0xffffffff; 3862 3863 /* 3864 * The first version of 82542 had an errata where when link was forced 3865 * it would stay up even up even if the cable was disconnected. 3866 * Sequence errors were used to detect the disconnect and then the 3867 * driver would unforce the link. This code in the in the ISR. For 3868 * this to work correctly the Sequence error interrupt had to be 3869 * enabled all the time. 3870 */ 3871 if (adapter->hw.mac.type == e1000_82542 && 3872 adapter->hw.revision_id == E1000_REVISION_2) 3873 clear &= ~E1000_ICR_RXSEQ; 3874 else if (adapter->hw.mac.type == e1000_82574) 3875 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3876 3877 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3878 3879 adapter->npoll.ifpc_stcount = 0; 3880 3881 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3882 } 3883 3884 /* 3885 * Bit of a misnomer, what this really means is 3886 * to enable OS management of the system... aka 3887 * to disable special hardware management features 3888 */ 3889 static void 3890 em_get_mgmt(struct adapter *adapter) 3891 { 3892 /* A shared code workaround */ 3893 #define E1000_82542_MANC2H E1000_MANC2H 3894 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3895 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3896 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3897 3898 /* disable hardware interception of ARP */ 3899 manc &= ~(E1000_MANC_ARP_EN); 3900 3901 /* enable receiving management packets to the host */ 3902 if (adapter->hw.mac.type >= e1000_82571) { 3903 manc |= E1000_MANC_EN_MNG2HOST; 3904 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3905 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3906 manc2h |= E1000_MNG2HOST_PORT_623; 3907 manc2h |= E1000_MNG2HOST_PORT_664; 3908 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3909 } 3910 3911 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3912 } 3913 } 3914 3915 /* 3916 * Give control back to hardware management 3917 * controller if there is one. 3918 */ 3919 static void 3920 em_rel_mgmt(struct adapter *adapter) 3921 { 3922 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3923 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3924 3925 /* re-enable hardware interception of ARP */ 3926 manc |= E1000_MANC_ARP_EN; 3927 3928 if (adapter->hw.mac.type >= e1000_82571) 3929 manc &= ~E1000_MANC_EN_MNG2HOST; 3930 3931 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3932 } 3933 } 3934 3935 /* 3936 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3937 * For ASF and Pass Through versions of f/w this means that 3938 * the driver is loaded. For AMT version (only with 82573) 3939 * of the f/w this means that the network i/f is open. 3940 */ 3941 static void 3942 em_get_hw_control(struct adapter *adapter) 3943 { 3944 /* Let firmware know the driver has taken over */ 3945 if (adapter->hw.mac.type == e1000_82573) { 3946 uint32_t swsm; 3947 3948 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3949 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3950 swsm | E1000_SWSM_DRV_LOAD); 3951 } else { 3952 uint32_t ctrl_ext; 3953 3954 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3955 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3956 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3957 } 3958 adapter->flags |= EM_FLAG_HW_CTRL; 3959 } 3960 3961 /* 3962 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3963 * For ASF and Pass Through versions of f/w this means that the 3964 * driver is no longer loaded. For AMT version (only with 82573) 3965 * of the f/w this means that the network i/f is closed. 3966 */ 3967 static void 3968 em_rel_hw_control(struct adapter *adapter) 3969 { 3970 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0) 3971 return; 3972 adapter->flags &= ~EM_FLAG_HW_CTRL; 3973 3974 /* Let firmware taken over control of h/w */ 3975 if (adapter->hw.mac.type == e1000_82573) { 3976 uint32_t swsm; 3977 3978 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3979 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3980 swsm & ~E1000_SWSM_DRV_LOAD); 3981 } else { 3982 uint32_t ctrl_ext; 3983 3984 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3985 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3986 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3987 } 3988 } 3989 3990 static int 3991 em_is_valid_eaddr(const uint8_t *addr) 3992 { 3993 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3994 3995 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3996 return (FALSE); 3997 3998 return (TRUE); 3999 } 4000 4001 /* 4002 * Enable PCI Wake On Lan capability 4003 */ 4004 static void 4005 em_enable_wol(device_t dev) 4006 { 4007 uint16_t cap, status; 4008 uint8_t id; 4009 4010 /* First find the capabilities pointer*/ 4011 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 4012 4013 /* Read the PM Capabilities */ 4014 id = pci_read_config(dev, cap, 1); 4015 if (id != PCIY_PMG) /* Something wrong */ 4016 return; 4017 4018 /* 4019 * OK, we have the power capabilities, 4020 * so now get the status register 4021 */ 4022 cap += PCIR_POWER_STATUS; 4023 status = pci_read_config(dev, cap, 2); 4024 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4025 pci_write_config(dev, cap, status, 2); 4026 } 4027 4028 4029 /* 4030 * 82544 Coexistence issue workaround. 4031 * There are 2 issues. 4032 * 1. Transmit Hang issue. 4033 * To detect this issue, following equation can be used... 4034 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4035 * If SUM[3:0] is in between 1 to 4, we will have this issue. 4036 * 4037 * 2. DAC issue. 4038 * To detect this issue, following equation can be used... 4039 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4040 * If SUM[3:0] is in between 9 to c, we will have this issue. 4041 * 4042 * WORKAROUND: 4043 * Make sure we do not have ending address 4044 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 4045 */ 4046 static uint32_t 4047 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 4048 { 4049 uint32_t safe_terminator; 4050 4051 /* 4052 * Since issue is sensitive to length and address. 4053 * Let us first check the address... 4054 */ 4055 if (length <= 4) { 4056 desc_array->descriptor[0].address = address; 4057 desc_array->descriptor[0].length = length; 4058 desc_array->elements = 1; 4059 return (desc_array->elements); 4060 } 4061 4062 safe_terminator = 4063 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 4064 4065 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 4066 if (safe_terminator == 0 || 4067 (safe_terminator > 4 && safe_terminator < 9) || 4068 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 4069 desc_array->descriptor[0].address = address; 4070 desc_array->descriptor[0].length = length; 4071 desc_array->elements = 1; 4072 return (desc_array->elements); 4073 } 4074 4075 desc_array->descriptor[0].address = address; 4076 desc_array->descriptor[0].length = length - 4; 4077 desc_array->descriptor[1].address = address + (length - 4); 4078 desc_array->descriptor[1].length = 4; 4079 desc_array->elements = 2; 4080 return (desc_array->elements); 4081 } 4082 4083 static void 4084 em_update_stats(struct adapter *adapter) 4085 { 4086 struct ifnet *ifp = &adapter->arpcom.ac_if; 4087 4088 if (adapter->hw.phy.media_type == e1000_media_type_copper || 4089 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4090 adapter->stats.symerrs += 4091 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 4092 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 4093 } 4094 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 4095 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 4096 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 4097 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 4098 4099 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 4100 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 4101 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 4102 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 4103 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 4104 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 4105 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 4106 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 4107 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4108 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4109 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4110 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4111 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4112 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4113 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4114 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4115 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4116 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4117 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4118 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4119 4120 /* For the 64-bit byte counters the low dword must be read first. */ 4121 /* Both registers clear on the read of the high dword */ 4122 4123 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 4124 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 4125 4126 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4127 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4128 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4129 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4130 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4131 4132 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 4133 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4134 4135 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 4136 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 4137 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 4138 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 4139 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 4140 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 4141 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 4142 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 4143 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 4144 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 4145 4146 if (adapter->hw.mac.type >= e1000_82543) { 4147 adapter->stats.algnerrc += 4148 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4149 adapter->stats.rxerrc += 4150 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4151 adapter->stats.tncrs += 4152 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4153 adapter->stats.cexterr += 4154 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4155 adapter->stats.tsctc += 4156 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4157 adapter->stats.tsctfc += 4158 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4159 } 4160 4161 IFNET_STAT_SET(ifp, collisions, adapter->stats.colc); 4162 4163 /* Rx Errors */ 4164 IFNET_STAT_SET(ifp, ierrors, 4165 adapter->dropped_pkts + adapter->stats.rxerrc + 4166 adapter->stats.crcerrs + adapter->stats.algnerrc + 4167 adapter->stats.ruc + adapter->stats.roc + 4168 adapter->stats.mpc + adapter->stats.cexterr); 4169 4170 /* Tx Errors */ 4171 IFNET_STAT_SET(ifp, oerrors, 4172 adapter->stats.ecol + adapter->stats.latecol + 4173 adapter->watchdog_events); 4174 } 4175 4176 static void 4177 em_print_debug_info(struct adapter *adapter) 4178 { 4179 device_t dev = adapter->dev; 4180 uint8_t *hw_addr = adapter->hw.hw_addr; 4181 4182 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 4183 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 4184 E1000_READ_REG(&adapter->hw, E1000_CTRL), 4185 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 4186 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 4187 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 4188 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 4189 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 4190 adapter->hw.fc.high_water, 4191 adapter->hw.fc.low_water); 4192 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 4193 E1000_READ_REG(&adapter->hw, E1000_TIDV), 4194 E1000_READ_REG(&adapter->hw, E1000_TADV)); 4195 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 4196 E1000_READ_REG(&adapter->hw, E1000_RDTR), 4197 E1000_READ_REG(&adapter->hw, E1000_RADV)); 4198 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 4199 (long long)adapter->tx_fifo_wrk_cnt, 4200 (long long)adapter->tx_fifo_reset_cnt); 4201 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4202 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 4203 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 4204 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4205 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 4206 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 4207 device_printf(dev, "Num Tx descriptors avail = %d\n", 4208 adapter->num_tx_desc_avail); 4209 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 4210 adapter->no_tx_desc_avail1); 4211 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 4212 adapter->no_tx_desc_avail2); 4213 device_printf(dev, "Std mbuf failed = %ld\n", 4214 adapter->mbuf_alloc_failed); 4215 device_printf(dev, "Std mbuf cluster failed = %ld\n", 4216 adapter->mbuf_cluster_failed); 4217 device_printf(dev, "Driver dropped packets = %ld\n", 4218 adapter->dropped_pkts); 4219 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 4220 adapter->no_tx_dma_setup); 4221 } 4222 4223 static void 4224 em_print_hw_stats(struct adapter *adapter) 4225 { 4226 device_t dev = adapter->dev; 4227 4228 device_printf(dev, "Excessive collisions = %lld\n", 4229 (long long)adapter->stats.ecol); 4230 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 4231 device_printf(dev, "Symbol errors = %lld\n", 4232 (long long)adapter->stats.symerrs); 4233 #endif 4234 device_printf(dev, "Sequence errors = %lld\n", 4235 (long long)adapter->stats.sec); 4236 device_printf(dev, "Defer count = %lld\n", 4237 (long long)adapter->stats.dc); 4238 device_printf(dev, "Missed Packets = %lld\n", 4239 (long long)adapter->stats.mpc); 4240 device_printf(dev, "Receive No Buffers = %lld\n", 4241 (long long)adapter->stats.rnbc); 4242 /* RLEC is inaccurate on some hardware, calculate our own. */ 4243 device_printf(dev, "Receive Length Errors = %lld\n", 4244 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 4245 device_printf(dev, "Receive errors = %lld\n", 4246 (long long)adapter->stats.rxerrc); 4247 device_printf(dev, "Crc errors = %lld\n", 4248 (long long)adapter->stats.crcerrs); 4249 device_printf(dev, "Alignment errors = %lld\n", 4250 (long long)adapter->stats.algnerrc); 4251 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 4252 (long long)adapter->stats.cexterr); 4253 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 4254 device_printf(dev, "watchdog timeouts = %ld\n", 4255 adapter->watchdog_events); 4256 device_printf(dev, "XON Rcvd = %lld\n", 4257 (long long)adapter->stats.xonrxc); 4258 device_printf(dev, "XON Xmtd = %lld\n", 4259 (long long)adapter->stats.xontxc); 4260 device_printf(dev, "XOFF Rcvd = %lld\n", 4261 (long long)adapter->stats.xoffrxc); 4262 device_printf(dev, "XOFF Xmtd = %lld\n", 4263 (long long)adapter->stats.xofftxc); 4264 device_printf(dev, "Good Packets Rcvd = %lld\n", 4265 (long long)adapter->stats.gprc); 4266 device_printf(dev, "Good Packets Xmtd = %lld\n", 4267 (long long)adapter->stats.gptc); 4268 } 4269 4270 static void 4271 em_print_nvm_info(struct adapter *adapter) 4272 { 4273 uint16_t eeprom_data; 4274 int i, j, row = 0; 4275 4276 /* Its a bit crude, but it gets the job done */ 4277 kprintf("\nInterface EEPROM Dump:\n"); 4278 kprintf("Offset\n0x0000 "); 4279 for (i = 0, j = 0; i < 32; i++, j++) { 4280 if (j == 8) { /* Make the offset block */ 4281 j = 0; ++row; 4282 kprintf("\n0x00%x0 ",row); 4283 } 4284 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4285 kprintf("%04x ", eeprom_data); 4286 } 4287 kprintf("\n"); 4288 } 4289 4290 static int 4291 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4292 { 4293 struct adapter *adapter; 4294 struct ifnet *ifp; 4295 int error, result; 4296 4297 result = -1; 4298 error = sysctl_handle_int(oidp, &result, 0, req); 4299 if (error || !req->newptr) 4300 return (error); 4301 4302 adapter = (struct adapter *)arg1; 4303 ifp = &adapter->arpcom.ac_if; 4304 4305 lwkt_serialize_enter(ifp->if_serializer); 4306 4307 if (result == 1) 4308 em_print_debug_info(adapter); 4309 4310 /* 4311 * This value will cause a hex dump of the 4312 * first 32 16-bit words of the EEPROM to 4313 * the screen. 4314 */ 4315 if (result == 2) 4316 em_print_nvm_info(adapter); 4317 4318 lwkt_serialize_exit(ifp->if_serializer); 4319 4320 return (error); 4321 } 4322 4323 static int 4324 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4325 { 4326 int error, result; 4327 4328 result = -1; 4329 error = sysctl_handle_int(oidp, &result, 0, req); 4330 if (error || !req->newptr) 4331 return (error); 4332 4333 if (result == 1) { 4334 struct adapter *adapter = (struct adapter *)arg1; 4335 struct ifnet *ifp = &adapter->arpcom.ac_if; 4336 4337 lwkt_serialize_enter(ifp->if_serializer); 4338 em_print_hw_stats(adapter); 4339 lwkt_serialize_exit(ifp->if_serializer); 4340 } 4341 return (error); 4342 } 4343 4344 static void 4345 em_add_sysctl(struct adapter *adapter) 4346 { 4347 struct sysctl_ctx_list *ctx; 4348 struct sysctl_oid *tree; 4349 4350 ctx = device_get_sysctl_ctx(adapter->dev); 4351 tree = device_get_sysctl_tree(adapter->dev); 4352 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4353 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4354 em_sysctl_debug_info, "I", "Debug Information"); 4355 4356 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4357 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4358 em_sysctl_stats, "I", "Statistics"); 4359 4360 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4361 OID_AUTO, "rxd", CTLFLAG_RD, 4362 &adapter->num_rx_desc, 0, NULL); 4363 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4364 OID_AUTO, "txd", CTLFLAG_RD, 4365 &adapter->num_tx_desc, 0, NULL); 4366 4367 if (adapter->hw.mac.type >= e1000_82540) { 4368 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4369 OID_AUTO, "int_throttle_ceil", 4370 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4371 em_sysctl_int_throttle, "I", 4372 "interrupt throttling rate"); 4373 } 4374 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4375 OID_AUTO, "int_tx_nsegs", 4376 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4377 em_sysctl_int_tx_nsegs, "I", 4378 "# segments per TX interrupt"); 4379 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4380 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW, 4381 &adapter->tx_wreg_nsegs, 0, 4382 "# segments before write to hardware register"); 4383 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_nmbuf", 4384 CTLFLAG_RD, &adapter->tx_nmbuf, 0, "# of pending TX mbufs"); 4385 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_gc", 4386 CTLFLAG_RW, &adapter->tx_gc, "# of TX GC"); 4387 } 4388 4389 static int 4390 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4391 { 4392 struct adapter *adapter = (void *)arg1; 4393 struct ifnet *ifp = &adapter->arpcom.ac_if; 4394 int error, throttle; 4395 4396 throttle = adapter->int_throttle_ceil; 4397 error = sysctl_handle_int(oidp, &throttle, 0, req); 4398 if (error || req->newptr == NULL) 4399 return error; 4400 if (throttle < 0 || throttle > 1000000000 / 256) 4401 return EINVAL; 4402 4403 if (throttle) { 4404 /* 4405 * Set the interrupt throttling rate in 256ns increments, 4406 * recalculate sysctl value assignment to get exact frequency. 4407 */ 4408 throttle = 1000000000 / 256 / throttle; 4409 4410 /* Upper 16bits of ITR is reserved and should be zero */ 4411 if (throttle & 0xffff0000) 4412 return EINVAL; 4413 } 4414 4415 lwkt_serialize_enter(ifp->if_serializer); 4416 4417 if (throttle) 4418 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4419 else 4420 adapter->int_throttle_ceil = 0; 4421 4422 if (ifp->if_flags & IFF_RUNNING) 4423 em_set_itr(adapter, throttle); 4424 4425 lwkt_serialize_exit(ifp->if_serializer); 4426 4427 if (bootverbose) { 4428 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4429 adapter->int_throttle_ceil); 4430 } 4431 return 0; 4432 } 4433 4434 static int 4435 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4436 { 4437 struct adapter *adapter = (void *)arg1; 4438 struct ifnet *ifp = &adapter->arpcom.ac_if; 4439 int error, segs; 4440 4441 segs = adapter->tx_int_nsegs; 4442 error = sysctl_handle_int(oidp, &segs, 0, req); 4443 if (error || req->newptr == NULL) 4444 return error; 4445 if (segs <= 0) 4446 return EINVAL; 4447 4448 lwkt_serialize_enter(ifp->if_serializer); 4449 4450 /* 4451 * Don't allow int_tx_nsegs to become: 4452 * o Less the oact_tx_desc 4453 * o Too large that no TX desc will cause TX interrupt to 4454 * be generated (OACTIVE will never recover) 4455 * o Too small that will cause tx_dd[] overflow 4456 */ 4457 if (segs < adapter->oact_tx_desc || 4458 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4459 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4460 error = EINVAL; 4461 } else { 4462 error = 0; 4463 adapter->tx_int_nsegs = segs; 4464 } 4465 4466 lwkt_serialize_exit(ifp->if_serializer); 4467 4468 return error; 4469 } 4470 4471 static void 4472 em_set_itr(struct adapter *adapter, uint32_t itr) 4473 { 4474 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4475 if (adapter->hw.mac.type == e1000_82574) { 4476 int i; 4477 4478 /* 4479 * When using MSIX interrupts we need to 4480 * throttle using the EITR register 4481 */ 4482 for (i = 0; i < 4; ++i) { 4483 E1000_WRITE_REG(&adapter->hw, 4484 E1000_EITR_82574(i), itr); 4485 } 4486 } 4487 } 4488 4489 static void 4490 em_disable_aspm(struct adapter *adapter) 4491 { 4492 uint16_t link_cap, link_ctrl, disable; 4493 uint8_t pcie_ptr, reg; 4494 device_t dev = adapter->dev; 4495 4496 switch (adapter->hw.mac.type) { 4497 case e1000_82571: 4498 case e1000_82572: 4499 case e1000_82573: 4500 /* 4501 * 82573 specification update 4502 * errata #8 disable L0s 4503 * errata #41 disable L1 4504 * 4505 * 82571/82572 specification update 4506 # errata #13 disable L1 4507 * errata #68 disable L0s 4508 */ 4509 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4510 break; 4511 4512 case e1000_82574: 4513 case e1000_82583: 4514 /* 4515 * 82574 specification update errata #20 4516 * 82583 specification update errata #9 4517 * 4518 * There is no need to disable L1 4519 */ 4520 disable = PCIEM_LNKCTL_ASPM_L0S; 4521 break; 4522 4523 default: 4524 return; 4525 } 4526 4527 pcie_ptr = pci_get_pciecap_ptr(dev); 4528 if (pcie_ptr == 0) 4529 return; 4530 4531 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4532 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4533 return; 4534 4535 if (bootverbose) { 4536 if_printf(&adapter->arpcom.ac_if, 4537 "disable ASPM %#02x\n", disable); 4538 } 4539 4540 reg = pcie_ptr + PCIER_LINKCTRL; 4541 link_ctrl = pci_read_config(dev, reg, 2); 4542 link_ctrl &= ~disable; 4543 pci_write_config(dev, reg, link_ctrl, 2); 4544 } 4545 4546 static int 4547 em_tso_pullup(struct adapter *adapter, struct mbuf **mp) 4548 { 4549 int iphlen, hoff, thoff, ex = 0; 4550 struct mbuf *m; 4551 struct ip *ip; 4552 4553 m = *mp; 4554 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4555 4556 iphlen = m->m_pkthdr.csum_iphlen; 4557 thoff = m->m_pkthdr.csum_thlen; 4558 hoff = m->m_pkthdr.csum_lhlen; 4559 4560 KASSERT(iphlen > 0, ("invalid ip hlen")); 4561 KASSERT(thoff > 0, ("invalid tcp hlen")); 4562 KASSERT(hoff > 0, ("invalid ether hlen")); 4563 4564 if (adapter->flags & EM_FLAG_TSO_PULLEX) 4565 ex = 4; 4566 4567 if (m->m_len < hoff + iphlen + thoff + ex) { 4568 m = m_pullup(m, hoff + iphlen + thoff + ex); 4569 if (m == NULL) { 4570 *mp = NULL; 4571 return ENOBUFS; 4572 } 4573 *mp = m; 4574 } 4575 ip = mtodoff(m, struct ip *, hoff); 4576 ip->ip_len = 0; 4577 4578 return 0; 4579 } 4580 4581 static int 4582 em_tso_setup(struct adapter *adapter, struct mbuf *mp, 4583 uint32_t *txd_upper, uint32_t *txd_lower) 4584 { 4585 struct e1000_context_desc *TXD; 4586 int hoff, iphlen, thoff, hlen; 4587 int mss, pktlen, curr_txd; 4588 4589 iphlen = mp->m_pkthdr.csum_iphlen; 4590 thoff = mp->m_pkthdr.csum_thlen; 4591 hoff = mp->m_pkthdr.csum_lhlen; 4592 mss = mp->m_pkthdr.tso_segsz; 4593 pktlen = mp->m_pkthdr.len; 4594 4595 if (adapter->csum_flags == CSUM_TSO && 4596 adapter->csum_iphlen == iphlen && 4597 adapter->csum_lhlen == hoff && 4598 adapter->csum_thlen == thoff && 4599 adapter->csum_mss == mss && 4600 adapter->csum_pktlen == pktlen) { 4601 *txd_upper = adapter->csum_txd_upper; 4602 *txd_lower = adapter->csum_txd_lower; 4603 return 0; 4604 } 4605 hlen = hoff + iphlen + thoff; 4606 4607 /* 4608 * Setup a new TSO context. 4609 */ 4610 4611 curr_txd = adapter->next_avail_tx_desc; 4612 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 4613 4614 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4615 E1000_TXD_DTYP_D | /* Data descr type */ 4616 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4617 4618 /* IP and/or TCP header checksum calculation and insertion. */ 4619 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4620 4621 /* 4622 * Start offset for header checksum calculation. 4623 * End offset for header checksum calculation. 4624 * Offset of place put the checksum. 4625 */ 4626 TXD->lower_setup.ip_fields.ipcss = hoff; 4627 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4628 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4629 4630 /* 4631 * Start offset for payload checksum calculation. 4632 * End offset for payload checksum calculation. 4633 * Offset of place to put the checksum. 4634 */ 4635 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4636 TXD->upper_setup.tcp_fields.tucse = 0; 4637 TXD->upper_setup.tcp_fields.tucso = 4638 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4639 4640 /* 4641 * Payload size per packet w/o any headers. 4642 * Length of all headers up to payload. 4643 */ 4644 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4645 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4646 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4647 E1000_TXD_CMD_DEXT | /* Extended descr */ 4648 E1000_TXD_CMD_TSE | /* TSE context */ 4649 E1000_TXD_CMD_IP | /* Do IP csum */ 4650 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4651 (pktlen - hlen)); /* Total len */ 4652 4653 /* Save the information for this TSO context */ 4654 adapter->csum_flags = CSUM_TSO; 4655 adapter->csum_lhlen = hoff; 4656 adapter->csum_iphlen = iphlen; 4657 adapter->csum_thlen = thoff; 4658 adapter->csum_mss = mss; 4659 adapter->csum_pktlen = pktlen; 4660 adapter->csum_txd_upper = *txd_upper; 4661 adapter->csum_txd_lower = *txd_lower; 4662 4663 if (++curr_txd == adapter->num_tx_desc) 4664 curr_txd = 0; 4665 4666 KKASSERT(adapter->num_tx_desc_avail > 0); 4667 adapter->num_tx_desc_avail--; 4668 4669 adapter->next_avail_tx_desc = curr_txd; 4670 return 1; 4671 } 4672 4673 /* 4674 * Remove all descriptors from the TX ring. 4675 * 4676 * We want to clear all pending descriptors from the TX ring. Zeroing 4677 * happens when the HW reads the regs. We assign the ring itself as 4678 * the data of the next descriptor. We don't care about the data we 4679 * are about to reset the HW. 4680 */ 4681 static void 4682 em_flush_tx_ring(struct adapter *adapter) 4683 { 4684 struct e1000_hw *hw = &adapter->hw; 4685 struct e1000_tx_desc *txd; 4686 uint32_t tctl; 4687 4688 tctl = E1000_READ_REG(hw, E1000_TCTL); 4689 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 4690 4691 txd = &adapter->tx_desc_base[adapter->next_avail_tx_desc++]; 4692 if (adapter->next_avail_tx_desc == adapter->num_tx_desc) 4693 adapter->next_avail_tx_desc = 0; 4694 4695 /* Just use the ring as a dummy buffer addr */ 4696 txd->buffer_addr = adapter->txdma.dma_paddr; 4697 txd->lower.data = htole32(E1000_TXD_CMD_IFCS | 512); 4698 txd->upper.data = 0; 4699 4700 E1000_WRITE_REG(hw, E1000_TDT(0), adapter->next_avail_tx_desc); 4701 usec_delay(250); 4702 } 4703 4704 /* 4705 * Remove all descriptors from the RX ring. 4706 * 4707 * Mark all descriptors in the RX ring as consumed and disable the RX ring. 4708 */ 4709 static void 4710 em_flush_rx_ring(struct adapter *adapter) 4711 { 4712 struct e1000_hw *hw = &adapter->hw; 4713 uint32_t rctl, rxdctl; 4714 4715 rctl = E1000_READ_REG(hw, E1000_RCTL); 4716 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 4717 E1000_WRITE_FLUSH(hw); 4718 usec_delay(150); 4719 4720 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 4721 /* Zero the lower 14 bits (prefetch and host thresholds) */ 4722 rxdctl &= 0xffffc000; 4723 /* 4724 * Update thresholds: prefetch threshold to 31, host threshold to 1 4725 * and make sure the granularity is "descriptors" and not "cache 4726 * lines". 4727 */ 4728 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 4729 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 4730 4731 /* Momentarily enable the RX ring for the changes to take effect */ 4732 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 4733 E1000_WRITE_FLUSH(hw); 4734 usec_delay(150); 4735 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 4736 } 4737 4738 /* 4739 * Remove all descriptors from the descriptor rings. 4740 * 4741 * In i219, the descriptor rings must be emptied before resetting the HW 4742 * or before changing the device state to D3 during runtime (runtime PM). 4743 * 4744 * Failure to do this will cause the HW to enter a unit hang state which 4745 * can only be released by PCI reset on the device. 4746 */ 4747 static void 4748 em_flush_txrx_ring(struct adapter *adapter) 4749 { 4750 struct e1000_hw *hw = &adapter->hw; 4751 device_t dev = adapter->dev; 4752 uint16_t hang_state; 4753 uint32_t fext_nvm11; 4754 4755 /* 4756 * First, disable MULR fix in FEXTNVM11. 4757 */ 4758 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 4759 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 4760 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 4761 4762 /* 4763 * Do nothing if we're not in faulty state, or if the queue is 4764 * empty. 4765 */ 4766 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 4767 if ((hang_state & FLUSH_DESC_REQUIRED) && 4768 E1000_READ_REG(hw, E1000_TDLEN(0))) 4769 em_flush_tx_ring(adapter); 4770 4771 /* 4772 * Recheck, maybe the fault is caused by the RX ring. 4773 */ 4774 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 4775 if (hang_state & FLUSH_DESC_REQUIRED) 4776 em_flush_rx_ring(adapter); 4777 } 4778