1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /*$FreeBSD: src/sys/dev/em/if_em.h,v 1.1.2.13 2003/06/09 21:43:41 pdeuskar Exp $*/ 35 /*$DragonFly: src/sys/dev/netif/em/if_em.h,v 1.10 2005/05/25 01:44:21 dillon Exp $*/ 36 37 #ifndef _EM_H_DEFINED_ 38 #define _EM_H_DEFINED_ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/mbuf.h> 43 #include <sys/protosw.h> 44 #include <sys/socket.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/sockio.h> 48 #include <sys/endian.h> 49 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 56 #include <net/bpf.h> 57 #include <net/if_types.h> 58 #include <net/vlan/if_vlan_var.h> 59 60 #include <netinet/in_systm.h> 61 #include <netinet/in.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 #include <netinet/udp.h> 65 66 #include <sys/bus.h> 67 #include <machine/bus.h> 68 #include <sys/rman.h> 69 #include <machine/resource.h> 70 #include <vm/vm.h> 71 #include <vm/pmap.h> 72 #include <machine/clock.h> 73 #include <bus/pci/pcivar.h> 74 #include <bus/pci/pcireg.h> 75 #include <sys/proc.h> 76 #include <sys/sysctl.h> 77 #include <sys/thread2.h> 78 #include <sys/serialize.h> 79 #include "opt_bdg.h" 80 81 #include <dev/netif/em/if_em_hw.h> 82 83 /* Tunables */ 84 85 /* 86 * EM_MAX_TXD: Maximum number of Transmit Descriptors 87 * Valid Range: 80-256 for 82542 and 82543-based adapters 88 * 80-4096 for others 89 * Default Value: 256 90 * This value is the number of transmit descriptors allocated by the driver. 91 * Increasing this value allows the driver to queue more transmits. Each 92 * descriptor is 16 bytes. 93 */ 94 #define EM_MAX_TXD 256 95 96 /* 97 * EM_MAX_RXD - Maximum number of receive Descriptors 98 * Valid Range: 80-256 for 82542 and 82543-based adapters 99 * 80-4096 for others 100 * Default Value: 256 101 * This value is the number of receive descriptors allocated by the driver. 102 * Increasing this value allows the driver to buffer more incoming packets. 103 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 104 * descriptor. The maximum MTU size is 16110. 105 * 106 */ 107 #define EM_MAX_RXD 256 108 109 /* 110 * EM_TIDV - Transmit Interrupt Delay Value 111 * Valid Range: 0-65535 (0=off) 112 * Default Value: 64 113 * This value delays the generation of transmit interrupts in units of 114 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 115 * efficiency if properly tuned for specific network traffic. If the 116 * system is reporting dropped transmits, this value may be set too high 117 * causing the driver to run out of available transmit descriptors. 118 */ 119 #define EM_TIDV 64 120 121 /* 122 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544) 123 * Valid Range: 0-65535 (0=off) 124 * Default Value: 64 125 * This value, in units of 1.024 microseconds, limits the delay in which a 126 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 127 * this value ensures that an interrupt is generated after the initial 128 * packet is sent on the wire within the set amount of time. Proper tuning, 129 * along with EM_TIDV, may improve traffic throughput in specific 130 * network conditions. 131 */ 132 #define EM_TADV 64 133 134 /* 135 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 136 * Valid Range: 0-65535 (0=off) 137 * Default Value: 0 138 * This value delays the generation of receive interrupts in units of 1.024 139 * microseconds. Receive interrupt reduction can improve CPU efficiency if 140 * properly tuned for specific network traffic. Increasing this value adds 141 * extra latency to frame reception and can end up decreasing the throughput 142 * of TCP traffic. If the system is reporting dropped receives, this value 143 * may be set too high, causing the driver to run out of available receive 144 * descriptors. 145 * 146 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 147 * may hang (stop transmitting) under certain network conditions. 148 * If this occurs a WATCHDOG message is logged in the system event log. 149 * In addition, the controller is automatically reset, restoring the 150 * network connection. To eliminate the potential for the hang 151 * ensure that EM_RDTR is set to 0. 152 */ 153 #define EM_RDTR 0 154 155 /* 156 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 157 * Valid Range: 0-65535 (0=off) 158 * Default Value: 64 159 * This value, in units of 1.024 microseconds, limits the delay in which a 160 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 161 * this value ensures that an interrupt is generated after the initial 162 * packet is received within the set amount of time. Proper tuning, 163 * along with EM_RDTR, may improve traffic throughput in specific network 164 * conditions. 165 */ 166 #define EM_RADV 64 167 168 169 /* 170 * This parameter controls the maximum no of times the driver will loop 171 * in the isr. 172 * Minimum Value = 1 173 */ 174 #define EM_MAX_INTR 3 175 176 /* 177 * Inform the stack about transmit checksum offload capabilities. 178 */ 179 #define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 180 181 /* 182 * This parameter controls the duration of transmit watchdog timer. 183 */ 184 #define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 185 186 /* 187 * This parameter controls when the driver calls the routine to reclaim 188 * transmit descriptors. 189 */ 190 #define EM_TX_CLEANUP_THRESHOLD EM_MAX_TXD / 8 191 192 /* 193 * This parameter controls whether or not autonegotation is enabled. 194 * 0 - Disable autonegotiation 195 * 1 - Enable autonegotiation 196 */ 197 #define DO_AUTO_NEG 1 198 199 /* 200 * This parameter control whether or not the driver will wait for 201 * autonegotiation to complete. 202 * 1 - Wait for autonegotiation to complete 203 * 0 - Don't wait for autonegotiation to complete 204 */ 205 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 206 207 /* 208 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 209 * compatibility issue with 82541/82547 devices and some switches. 210 * See the "Known Limitations" section of the README file for a complete 211 * description and a list of affected switches. 212 * 213 * 0 = Hardware default 214 * 1 = Master mode 215 * 2 = Slave mode 216 * 3 = Auto master/slave 217 */ 218 /* #define EM_MASTER_SLAVE 2 */ 219 220 /* Tunables -- End */ 221 222 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 223 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 224 ADVERTISE_1000_FULL) 225 226 #define EM_VENDOR_ID 0x8086 227 #define EM_MMBA 0x0010 /* Mem base address */ 228 #define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 229 230 #define EM_JUMBO_PBA 0x00000028 231 #define EM_DEFAULT_PBA 0x00000030 232 #define EM_SMARTSPEED_DOWNSHIFT 3 233 #define EM_SMARTSPEED_MAX 15 234 235 236 #define MAX_NUM_MULTICAST_ADDRESSES 128 237 #define PCI_ANY_ID (~0U) 238 #define ETHER_ALIGN 2 239 240 /* Defines for printing debug information */ 241 #define DEBUG_INIT 0 242 #define DEBUG_IOCTL 0 243 #define DEBUG_HW 0 244 245 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 246 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 247 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 248 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 249 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 250 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 251 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 252 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 253 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 254 255 256 /* Supported RX Buffer Sizes */ 257 #define EM_RXBUFFER_2048 2048 258 #define EM_RXBUFFER_4096 4096 259 #define EM_RXBUFFER_8192 8192 260 #define EM_RXBUFFER_16384 16384 261 262 #define EM_MAX_SCATTER 64 263 264 /* ****************************************************************************** 265 * vendor_info_array 266 * 267 * This array contains the list of Subvendor/Subdevice IDs on which the driver 268 * should load. 269 * 270 * ******************************************************************************/ 271 typedef struct _em_vendor_info_t { 272 unsigned int vendor_id; 273 unsigned int device_id; 274 unsigned int subvendor_id; 275 unsigned int subdevice_id; 276 unsigned int index; 277 } em_vendor_info_t; 278 279 280 struct em_buffer { 281 struct mbuf *m_head; 282 bus_dmamap_t map; /* bus_dma map for packet */ 283 }; 284 285 struct em_q { 286 bus_dmamap_t map; /* bus_dma map for packet */ 287 int nsegs; /* # of segments/descriptors */ 288 bus_dma_segment_t segs[EM_MAX_SCATTER]; 289 }; 290 291 /* 292 * Bus dma allocation structure used by 293 * em_dma_malloc and em_dma_free. 294 */ 295 struct em_dma_alloc { 296 bus_addr_t dma_paddr; 297 caddr_t dma_vaddr; 298 bus_dma_tag_t dma_tag; 299 bus_dmamap_t dma_map; 300 bus_dma_segment_t dma_seg; 301 bus_size_t dma_size; 302 int dma_nseg; 303 }; 304 305 typedef enum _XSUM_CONTEXT_T { 306 OFFLOAD_NONE, 307 OFFLOAD_TCP_IP, 308 OFFLOAD_UDP_IP 309 } XSUM_CONTEXT_T; 310 311 struct adapter; 312 struct em_int_delay_info { 313 struct adapter *adapter; /* Back-pointer to the adapter struct */ 314 int offset; /* Register offset to read/write */ 315 int value; /* Current value in usecs */ 316 }; 317 318 /* For 82544 PCIX Workaround */ 319 typedef struct _ADDRESS_LENGTH_PAIR 320 { 321 u_int64_t address; 322 u_int32_t length; 323 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 324 325 typedef struct _DESCRIPTOR_PAIR 326 { 327 ADDRESS_LENGTH_PAIR descriptor[4]; 328 u_int32_t elements; 329 } DESC_ARRAY, *PDESC_ARRAY; 330 331 /* Our adapter structure */ 332 struct adapter { 333 struct arpcom interface_data; 334 struct em_hw hw; 335 336 /* FreeBSD operating-system-specific structures */ 337 struct lwkt_serialize serializer; 338 struct em_osdep osdep; 339 struct device *dev; 340 struct resource *res_memory; 341 struct resource *res_ioport; 342 struct resource *res_interrupt; 343 void *int_handler_tag; 344 struct ifmedia media; 345 struct callout timer; 346 struct callout tx_fifo_timer; 347 int io_rid; 348 349 /* Info about the board itself */ 350 u_int32_t part_num; 351 u_int8_t link_active; 352 u_int16_t link_speed; 353 u_int16_t link_duplex; 354 u_int32_t smartspeed; 355 struct em_int_delay_info tx_int_delay; 356 struct em_int_delay_info tx_abs_int_delay; 357 struct em_int_delay_info rx_int_delay; 358 struct em_int_delay_info rx_abs_int_delay; 359 360 XSUM_CONTEXT_T active_checksum_context; 361 362 /* 363 * Transmit definitions 364 * 365 * We have an array of num_tx_desc descriptors (handled 366 * by the controller) paired with an array of tx_buffers 367 * (at tx_buffer_area). 368 * The index of the next available descriptor is next_avail_tx_desc. 369 * The number of remaining tx_desc is num_tx_desc_avail. 370 */ 371 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 372 struct em_tx_desc *tx_desc_base; 373 u_int32_t next_avail_tx_desc; 374 u_int32_t oldest_used_tx_desc; 375 volatile u_int16_t num_tx_desc_avail; 376 u_int16_t num_tx_desc; 377 u_int32_t txd_cmd; 378 struct em_buffer *tx_buffer_area; 379 bus_dma_tag_t txtag; /* dma tag for tx */ 380 381 /* 382 * Receive definitions 383 * 384 * we have an array of num_rx_desc rx_desc (handled by the 385 * controller), and paired with an array of rx_buffers 386 * (at rx_buffer_area). 387 * The next pair to check on receive is at offset next_rx_desc_to_check 388 */ 389 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 390 struct em_rx_desc *rx_desc_base; 391 u_int32_t next_rx_desc_to_check; 392 u_int16_t num_rx_desc; 393 u_int32_t rx_buffer_len; 394 struct em_buffer *rx_buffer_area; 395 bus_dma_tag_t rxtag; 396 397 /* Jumbo frame */ 398 struct mbuf *fmp; 399 struct mbuf *lmp; 400 401 u_int16_t tx_fifo_head; 402 403 struct sysctl_ctx_list sysctl_ctx; 404 struct sysctl_oid *sysctl_tree; 405 406 /* Misc stats maintained by the driver */ 407 unsigned long dropped_pkts; 408 unsigned long mbuf_alloc_failed; 409 unsigned long mbuf_cluster_failed; 410 unsigned long no_tx_desc_avail1; 411 unsigned long no_tx_desc_avail2; 412 unsigned long no_tx_map_avail; 413 unsigned long no_tx_dma_setup; 414 u_int64_t tx_fifo_reset; 415 u_int64_t tx_fifo_wrk; 416 417 /* For 82544 PCIX Workaround */ 418 boolean_t pcix_82544; 419 boolean_t in_detach; 420 421 #ifdef DBG_STATS 422 unsigned long no_pkts_avail; 423 unsigned long clean_tx_interrupts; 424 425 #endif 426 struct em_hw_stats stats; 427 }; 428 429 #endif /* _EM_H_DEFINED_ */ 430