1 /* 2 * Copyright (c) 2001-2008, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_EM_H_ 33 #define _IF_EM_H_ 34 35 /* Tunables */ 36 37 /* 38 * EM_TXD: Maximum number of Transmit Descriptors 39 * Valid Range: 256 for 82542 and 82543-based adapters 40 * 256-4096 for others 41 * Default Value: 256 42 * This value is the number of transmit descriptors allocated by the driver. 43 * Increasing this value allows the driver to queue more transmits. Each 44 * descriptor is 16 bytes. 45 * Since TDLEN should be multiple of 128bytes, the number of transmit 46 * desscriptors should meet the following condition. 47 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 48 */ 49 #define EM_MIN_TXD 256 50 #define EM_MAX_TXD_82543 EM_MIN_TXD 51 #define EM_MAX_TXD 4096 52 #define EM_DEFAULT_TXD 512 53 54 /* 55 * EM_RXD - Maximum number of receive Descriptors 56 * Valid Range: 256 for 82542 and 82543-based adapters 57 * 256-4096 for others 58 * Default Value: 256 59 * This value is the number of receive descriptors allocated by the driver. 60 * Increasing this value allows the driver to buffer more incoming packets. 61 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 62 * descriptor. The maximum MTU size is 16110. 63 * Since TDLEN should be multiple of 128bytes, the number of transmit 64 * desscriptors should meet the following condition. 65 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 66 */ 67 #define EM_MIN_RXD 256 68 #define EM_MAX_RXD_82543 EM_MIN_RXD 69 #define EM_MAX_RXD 4096 70 #define EM_DEFAULT_RXD 512 71 72 /* 73 * EM_TIDV - Transmit Interrupt Delay Value 74 * Valid Range: 0-65535 (0=off) 75 * Default Value: 64 76 * This value delays the generation of transmit interrupts in units of 77 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 78 * efficiency if properly tuned for specific network traffic. If the 79 * system is reporting dropped transmits, this value may be set too high 80 * causing the driver to run out of available transmit descriptors. 81 * 82 * NOTE: 83 * It is not used. In DragonFly the TX interrupt moderation is done by 84 * conditionally setting RS bit in TX descriptors. See the description 85 * in struct adapter. 86 */ 87 #define EM_TIDV 64 88 89 /* 90 * EM_TADV - Transmit Absolute Interrupt Delay Value 91 * (Not valid for 82542/82543/82544) 92 * Valid Range: 0-65535 (0=off) 93 * Default Value: 64 94 * This value, in units of 1.024 microseconds, limits the delay in which a 95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 96 * this value ensures that an interrupt is generated after the initial 97 * packet is sent on the wire within the set amount of time. Proper tuning, 98 * along with EM_TIDV, may improve traffic throughput in specific 99 * network conditions. 100 * 101 * NOTE: 102 * It is not used. In DragonFly the TX interrupt moderation is done by 103 * conditionally setting RS bit in TX descriptors. See the description 104 * in struct adapter. 105 */ 106 #define EM_TADV 64 107 108 /* 109 * Receive Interrupt Delay Timer (Packet Timer) 110 * 111 * NOTE: 112 * RDTR and RADV are deprecated; use ITR instead. They are only used to 113 * workaround hardware bug on certain 82573 based NICs. 114 */ 115 #define EM_RDTR_82573 32 116 117 /* 118 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 119 * 120 * NOTE: 121 * RDTR and RADV are deprecated; use ITR instead. They are only used to 122 * workaround hardware bug on certain 82573 based NICs. 123 */ 124 #define EM_RADV_82573 64 125 126 /* 127 * This parameter controls the duration of transmit watchdog timer. 128 */ 129 #define EM_TX_TIMEOUT 5 130 131 /* One for TX csum offloading desc, the other 2 are reserved */ 132 #define EM_TX_RESERVED 3 133 134 /* Large enough for 16K jumbo frame */ 135 #define EM_TX_SPARE 8 136 /* Large enough for 64K jumbo frame */ 137 #define EM_TX_SPARE_TSO 33 138 139 #define EM_TX_OACTIVE_MAX 64 140 141 /* Interrupt throttle rate */ 142 #define EM_DEFAULT_ITR 6000 143 144 /* Number of segments sent before writing to TX related registers */ 145 #define EM_DEFAULT_TXWREG 8 146 147 /* 148 * This parameter controls whether or not autonegotation is enabled. 149 * 0 - Disable autonegotiation 150 * 1 - Enable autonegotiation 151 */ 152 #define DO_AUTO_NEG 1 153 154 /* 155 * This parameter control whether or not the driver will wait for 156 * autonegotiation to complete. 157 * 1 - Wait for autonegotiation to complete 158 * 0 - Don't wait for autonegotiation to complete 159 */ 160 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 161 162 /* Tunables -- End */ 163 164 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ 165 ADVERTISE_10_FULL | \ 166 ADVERTISE_100_HALF | \ 167 ADVERTISE_100_FULL | \ 168 ADVERTISE_1000_FULL) 169 170 #define AUTO_ALL_MODES 0 171 172 /* PHY master/slave setting */ 173 #define EM_MASTER_SLAVE e1000_ms_hw_default 174 175 /* 176 * Micellaneous constants 177 */ 178 #define EM_VENDOR_ID 0x8086 179 180 #define EM_BAR_MEM PCIR_BAR(0) 181 #define EM_BAR_FLASH PCIR_BAR(1) 182 183 #define EM_JUMBO_PBA 0x00000028 184 #define EM_DEFAULT_PBA 0x00000030 185 #define EM_SMARTSPEED_DOWNSHIFT 3 186 #define EM_SMARTSPEED_MAX 15 187 #define EM_MAX_INTR 10 188 189 #define MAX_NUM_MULTICAST_ADDRESSES 128 190 #define PCI_ANY_ID (~0U) 191 #define EM_FC_PAUSE_TIME 1000 192 #define EM_EEPROM_APME 0x400; 193 194 /* 195 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 196 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 197 * also optimize cache line size effect. H/W supports up to cache line size 128. 198 */ 199 #define EM_DBA_ALIGN 128 200 201 #define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 202 203 /* PCI Config defines */ 204 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 205 #define EM_BAR_TYPE_MASK 0x00000001 206 #define EM_BAR_TYPE_MMEM 0x00000000 207 #define EM_BAR_TYPE_IO 0x00000001 208 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 209 #define EM_BAR_MEM_TYPE_MASK 0x00000006 210 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 211 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 212 213 #define EM_MAX_SCATTER 64 214 #define EM_TSO_SIZE (IP_MAXPACKET + \ 215 sizeof(struct ether_vlan_header)) 216 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 217 #define ETH_ZLEN 60 218 219 #define EM_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 220 221 /* 222 * 82574 has a nonstandard address for EIAC 223 * and since its only used in MSIX, and in 224 * the em driver only 82574 uses MSIX we can 225 * solve it just using this define. 226 */ 227 #define EM_EIAC 0x000DC 228 229 /* Used in for 82547 10Mb Half workaround */ 230 #define EM_PBA_BYTES_SHIFT 0xA 231 #define EM_TX_HEAD_ADDR_SHIFT 7 232 #define EM_PBA_TX_MASK 0xFFFF0000 233 #define EM_FIFO_HDR 0x10 234 #define EM_82547_PKT_THRESH 0x3e0 235 236 /* 237 * Bus dma allocation structure used by 238 * em_dma_malloc and em_dma_free. 239 */ 240 struct em_dma_alloc { 241 bus_addr_t dma_paddr; 242 void *dma_vaddr; 243 bus_dma_tag_t dma_tag; 244 bus_dmamap_t dma_map; 245 }; 246 247 /* Our adapter structure */ 248 struct adapter { 249 struct arpcom arpcom; 250 struct e1000_hw hw; 251 int flags; 252 #define EM_FLAG_SHARED_INTR 0x0001 253 #define EM_FLAG_HAS_MGMT 0x0002 254 #define EM_FLAG_HAS_AMT 0x0004 255 #define EM_FLAG_HW_CTRL 0x0008 256 #define EM_FLAG_TSO 0x0010 257 #define EM_FLAG_TSO_PULLEX 0x0020 258 259 /* DragonFly operating-system-specific structures. */ 260 struct e1000_osdep osdep; 261 device_t dev; 262 263 bus_dma_tag_t parent_dtag; 264 265 struct resource *memory; 266 int memory_rid; 267 struct resource *flash; 268 int flash_rid; 269 270 struct resource *ioport; 271 int io_rid; 272 273 struct resource *intr_res; 274 void *intr_tag; 275 int intr_rid; 276 int intr_type; 277 278 struct ifmedia media; 279 struct callout timer; 280 struct callout tx_fifo_timer; 281 int if_flags; 282 int min_frame_size; 283 284 /* WOL register value */ 285 int wol; 286 287 /* Multicast array memory */ 288 uint8_t *mta; 289 290 /* Info about the board itself */ 291 uint8_t link_active; 292 uint16_t link_speed; 293 uint16_t link_duplex; 294 uint32_t smartspeed; 295 int int_throttle_ceil; 296 297 /* Polling */ 298 struct ifpoll_compat npoll; 299 300 /* 301 * Transmit definitions 302 * 303 * We have an array of num_tx_desc descriptors (handled 304 * by the controller) paired with an array of tx_buffers 305 * (at tx_buffer_area). 306 * The index of the next available descriptor is next_avail_tx_desc. 307 * The number of remaining tx_desc is num_tx_desc_avail. 308 */ 309 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 310 struct e1000_tx_desc *tx_desc_base; 311 struct em_buffer *tx_buffer_area; 312 uint32_t next_avail_tx_desc; 313 uint32_t next_tx_to_clean; 314 int num_tx_desc_avail; 315 int num_tx_desc; 316 bus_dma_tag_t txtag; /* dma tag for tx */ 317 int spare_tx_desc; 318 int oact_tx_desc; 319 320 /* Saved csum offloading context information */ 321 int csum_flags; 322 int csum_lhlen; 323 int csum_iphlen; 324 325 int csum_thlen; /* TSO */ 326 int csum_mss; /* TSO */ 327 int csum_pktlen; /* TSO */ 328 329 uint32_t csum_txd_upper; 330 uint32_t csum_txd_lower; 331 332 int tx_wreg_nsegs; 333 334 /* 335 * Variables used to reduce TX interrupt rate and 336 * number of device's TX ring write requests. 337 * 338 * tx_nsegs: 339 * Number of TX descriptors setup so far. 340 * 341 * tx_int_nsegs: 342 * Once tx_nsegs > tx_int_nsegs, RS bit will be set 343 * in the last TX descriptor of the packet, and 344 * tx_nsegs will be reset to 0. So TX interrupt and 345 * TX ring write request should be generated roughly 346 * every tx_int_nsegs TX descriptors. 347 * 348 * tx_dd[]: 349 * Index of the TX descriptors which have RS bit set, 350 * i.e. DD bit will be set on this TX descriptor after 351 * the data of the TX descriptor are transfered to 352 * hardware's internal packet buffer. Only the TX 353 * descriptors listed in tx_dd[] will be checked upon 354 * TX interrupt. This array is used as circular ring. 355 * 356 * tx_dd_tail, tx_dd_head: 357 * Tail and head index of valid elements in tx_dd[]. 358 * tx_dd_tail == tx_dd_head means there is no valid 359 * elements in tx_dd[]. tx_dd_tail points to the position 360 * which is one beyond the last valid element in tx_dd[]. 361 * tx_dd_head points to the first valid element in 362 * tx_dd[]. 363 */ 364 int tx_int_nsegs; 365 int tx_nsegs; 366 int tx_dd_tail; 367 int tx_dd_head; 368 #define EM_TXDD_MAX 64 369 #define EM_TXDD_SAFE 48 /* must be less than EM_TXDD_MAX */ 370 int tx_dd[EM_TXDD_MAX]; 371 372 /* 373 * Receive definitions 374 * 375 * we have an array of num_rx_desc rx_desc (handled by the 376 * controller), and paired with an array of rx_buffers 377 * (at rx_buffer_area). 378 * The next pair to check on receive is at offset next_rx_desc_to_check 379 */ 380 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 381 struct e1000_rx_desc *rx_desc_base; 382 uint32_t next_rx_desc_to_check; 383 uint32_t rx_buffer_len; 384 int num_rx_desc; 385 struct em_buffer *rx_buffer_area; 386 bus_dma_tag_t rxtag; 387 bus_dmamap_t rx_sparemap; 388 389 /* 390 * First/last mbuf pointers, for 391 * collecting multisegment RX packets. 392 */ 393 struct mbuf *fmp; 394 struct mbuf *lmp; 395 396 /* Misc stats maintained by the driver */ 397 unsigned long dropped_pkts; 398 unsigned long mbuf_alloc_failed; 399 unsigned long mbuf_cluster_failed; 400 unsigned long no_tx_desc_avail1; 401 unsigned long no_tx_desc_avail2; 402 unsigned long no_tx_map_avail; 403 unsigned long no_tx_dma_setup; 404 unsigned long watchdog_events; 405 unsigned long rx_overruns; 406 unsigned long rx_irq; 407 unsigned long tx_irq; 408 unsigned long link_irq; 409 410 /* 82547 workaround */ 411 uint32_t tx_fifo_size; 412 uint32_t tx_fifo_head; 413 uint32_t tx_fifo_head_addr; 414 uint64_t tx_fifo_reset_cnt; 415 uint64_t tx_fifo_wrk_cnt; 416 uint32_t tx_head_addr; 417 418 /* For 82544 PCIX Workaround */ 419 boolean_t pcix_82544; 420 421 struct e1000_hw_stats stats; 422 }; 423 424 struct em_vendor_info { 425 uint16_t vendor_id; 426 uint16_t device_id; 427 int ret; 428 const char *desc; 429 }; 430 431 struct em_buffer { 432 struct mbuf *m_head; 433 bus_dmamap_t map; /* bus_dma map for packet */ 434 }; 435 436 /* For 82544 PCIX Workaround */ 437 typedef struct _ADDRESS_LENGTH_PAIR { 438 uint64_t address; 439 uint32_t length; 440 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 441 442 typedef struct _DESCRIPTOR_PAIR { 443 ADDRESS_LENGTH_PAIR descriptor[4]; 444 uint32_t elements; 445 } DESC_ARRAY, *PDESC_ARRAY; 446 447 #define EM_IS_OACTIVE(adapter) \ 448 ((adapter)->num_tx_desc_avail <= (adapter)->oact_tx_desc) 449 450 #define EM_INC_TXDD_IDX(idx) \ 451 do { \ 452 if (++(idx) == EM_TXDD_MAX) \ 453 (idx) = 0; \ 454 } while (0) 455 456 #endif /* _IF_EM_H_ */ 457